mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
Refactor into AigerReader class
This commit is contained in:
Eddie Hung
parent
2a8cc36578
commit
f1befe1b44
2 changed files with 94 additions and 81 deletions
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@ -30,25 +30,85 @@ YOSYS_NAMESPACE_BEGIN
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#define log_debug log
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static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name);
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static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name);
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void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name)
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: design(design), f(f), clk_name(clk_name)
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{
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auto module = new RTLIL::Module;
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module = new RTLIL::Module;
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module->name = RTLIL::escape_id("aig"); // TODO: Name?
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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}
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void AigerReader::parse_aiger()
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{
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std::string header;
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f >> header;
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if (header == "aag")
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parse_aiger_ascii(module, f, clk_name);
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else if (header == "aig")
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parse_aiger_binary(module, f, clk_name);
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else
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if (header != "aag" && header != "aig")
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log_error("Unsupported AIGER file!\n");
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// Parse rest of header
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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// Optional values
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B = C = J = F = 0;
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for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
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if (f.peek() != ' ') break;
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if (!(f >> i))
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log_error("Invalid AIGER header\n");
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}
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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line_count = 1;
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if (header == "aag")
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary();
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else
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log_abort();
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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std::string s;
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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if (c == 'i' || c == 'l' || c == 'o') {
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f.ignore(1);
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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log_error("Line %u has invalid symbol position!\n", line_count);
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RTLIL::Wire* wire;
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if (c == 'i') wire = inputs[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'o') wire = outputs[l1];
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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else if (c == 'b' || c == 'j' || c == 'f') {
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// TODO
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}
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else if (c == 'c') {
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f.ignore(1);
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if (f.peek() == '\n')
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break;
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// Else constraint (TODO)
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break;
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}
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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}
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module->fixup_ports();
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design->add(module);
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}
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@ -81,38 +141,14 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
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return wire;
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}
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static void parse_aiger_header(std::istream &f, unsigned &M, unsigned &I, unsigned &L, unsigned &O, unsigned &A, unsigned &B, unsigned &C, unsigned &J, unsigned &F)
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void AigerReader::parse_aiger_ascii()
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{
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
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if (f.peek() != ' ') break;
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if (!(f >> i))
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log_error("Invalid AIGER header\n");
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}
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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}
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static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name)
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{
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unsigned M, I, L, O, A;
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unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
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parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
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unsigned line_count = 1;
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std::string line;
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std::stringstream ss;
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unsigned l1, l2, l3;
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// Parse inputs
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std::vector<RTLIL::Wire*> inputs;
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for (unsigned i = 0; i < I; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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@ -124,7 +160,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
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}
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// Parse latches
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std::vector<RTLIL::Wire*> latches;
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
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@ -165,7 +200,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
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}
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// Parse outputs
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std::vector<RTLIL::Wire*> outputs;
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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@ -210,39 +244,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
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and_cell->setPort("\\Y", o_wire);
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}
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std::getline(f, line); // Ignore up to start of next line
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std::string s;
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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if (c == 'i' || c == 'l' || c == 'o') {
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f.ignore(1);
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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log_error("Line %u has invalid symbol position!\n", line_count);
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RTLIL::Wire* wire;
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if (c == 'i') wire = inputs[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'o') wire = outputs[l1];
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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else if (c == 'b' || c == 'j' || c == 'f') {
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// TODO
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}
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else if (c == 'c') {
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f.ignore(1);
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if (f.peek() == '\n')
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break;
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// Else constraint (TODO)
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break;
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}
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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}
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}
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static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
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@ -254,18 +255,12 @@ static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
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return ref - (x | (ch << (7 * i)));
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}
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static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name)
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void AigerReader::parse_aiger_binary()
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{
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unsigned M, I, L, O, A;
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unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
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parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
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unsigned line_count = 1;
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unsigned l1, l2, l3;
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std::string line;
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// Parse inputs
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std::vector<RTLIL::Wire*> inputs;
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for (unsigned i = 1; i <= I; ++i) {
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RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
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wire->port_input = true;
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@ -273,7 +268,6 @@ static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::stri
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}
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// Parse latches
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std::vector<RTLIL::Wire*> latches;
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
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@ -314,7 +308,6 @@ static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::stri
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}
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// Parse outputs
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std::vector<RTLIL::Wire*> outputs;
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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@ -385,7 +378,8 @@ struct AigerFrontend : public Frontend {
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}
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extra_args(f, filename, args, argidx);
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parse_aiger(design, *f);
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AigerReader reader(design, *f);
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reader.parse_aiger();
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}
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} AigerFrontend;
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@ -24,7 +24,26 @@
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YOSYS_NAMESPACE_BEGIN
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extern void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
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struct AigerReader
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{
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RTLIL::Design *design;
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std::istream &f;
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std::string clk_name;
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RTLIL::Module *module;
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unsigned M, I, L, O, A;
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unsigned B, C, J, F; // Optional in AIGER 1.9
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unsigned line_count;
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std::vector<RTLIL::Wire*> inputs;
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std::vector<RTLIL::Wire*> latches;
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std::vector<RTLIL::Wire*> outputs;
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AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
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void parse_aiger();
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void parse_aiger_ascii();
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void parse_aiger_binary();
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};
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YOSYS_NAMESPACE_END
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