mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

If d_bit already in sigbit_chain_next, create extra wire

Browse source
This commit is contained in:
Eddie Hung 2019-06-10 16:16:40 -07:00
parent c314ca3c51
commit f19aa8d989
1 changed files with 6 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

9
passes/techmap/shregmap.cc
View file

@ -293,10 +293,13 @@ struct ShregmapWorker
if (opts.init || sigbit_init.count(q_bit) == 0) if (opts.init || sigbit_init.count(q_bit) == 0)
{ {
if (sigbit_chain_next.count(d_bit)) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
if (!r.second) {
sigbit_with_non_chain_users.insert(d_bit); sigbit_with_non_chain_users.insert(d_bit);
} else Wire *wire = module->addWire(NEW_ID);
sigbit_chain_next[d_bit] = cell; module->connect(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));
}
sigbit_chain_prev[q_bit] = cell; sigbit_chain_prev[q_bit] = cell;
continue; continue;