mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Verific: add default parameters to modules

Browse source
This commit is contained in:
Miodrag Milanovic 2023-09-27 16:57:18 +02:00
parent c4762d930e
commit f193ebdded
1 changed files with 8 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

9
frontends/verific/verific.cc
View file

@ -1275,9 +1275,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
const char *param_name ;
const char *param_value ;
MapIter mi;
FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
module->avail_parameters(RTLIL::escape_id(param_name));
module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value);
}
SetIter si; SetIter si;
MapIter mi, mi2; MapIter mi2;
Port *port; Port *port;
PortBus *portbus; PortBus *portbus;
Net *net; Net *net;