From aa081f83c791b1d666214776aaf744a80ce6a690 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 17:40:39 -0700 Subject: [PATCH 1/5] dffinit -noreinit to silently continue when init value is 1'bx --- passes/techmap/dffinit.cc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..37479da65 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -135,10 +135,18 @@ struct DffinitPass : public Pass { continue; while (GetSize(value.bits) <= i) value.bits.push_back(State::S0); - if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) - log_error("Trying to assign a different init value for %s.%s.%s which technically " - "have a conflicted init value.\n", - log_id(module), log_id(cell), log_id(it.second)); + if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) { + if (init_bits.at(sig[i]) != State::Sx) { + log_error("Trying to assign a different init value for %s.%s.%s which technically " + "have a conflicted init value.\n", + log_id(module), log_id(cell), log_id(it.second)); + } + else { + // Trying to overwrite an existing INIT value with 1'bx, + // silently ignore? + continue; + } + } value.bits[i] = init_bits.at(sig[i]); cleanup_bits.insert(sig[i]); } From 1f62dc9081feb4852b1848d01951f631853edb38 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 17:41:20 -0700 Subject: [PATCH 2/5] synth_xilinx to call dffinit with -noreinit --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8aa7b508e..fc0e76bad 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -250,7 +250,7 @@ struct SynthXilinxPass : public ScriptPass if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + run("dffinit -noreinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } From fc349de0338db3831e7156a5dc60f028382bcab1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 08:05:37 -0700 Subject: [PATCH 3/5] Revert "dffinit -noreinit to silently continue when init value is 1'bx" This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690. --- passes/techmap/dffinit.cc | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 37479da65..48390488e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -135,18 +135,10 @@ struct DffinitPass : public Pass { continue; while (GetSize(value.bits) <= i) value.bits.push_back(State::S0); - if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) { - if (init_bits.at(sig[i]) != State::Sx) { - log_error("Trying to assign a different init value for %s.%s.%s which technically " - "have a conflicted init value.\n", - log_id(module), log_id(cell), log_id(it.second)); - } - else { - // Trying to overwrite an existing INIT value with 1'bx, - // silently ignore? - continue; - } - } + if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) + log_error("Trying to assign a different init value for %s.%s.%s which technically " + "have a conflicted init value.\n", + log_id(module), log_id(cell), log_id(it.second)); value.bits[i] = init_bits.at(sig[i]); cleanup_bits.insert(sig[i]); } From e08df0c7390e1e7736c3d5b0abbe2679bf9b4518 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 08:06:16 -0700 Subject: [PATCH 4/5] If init is 1'bx, do not add to dict as per @cliffordwolf --- passes/techmap/dffinit.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..0ad33dc0e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -102,7 +102,8 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - init_bits[sigmap(SigBit(wire, i))] = value[i]; + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) for (auto bit : sigmap(wire)) From 1d43a25f08920643f413cf74b18adfb32815fcd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 09:55:02 -0700 Subject: [PATCH 5/5] Revert "synth_xilinx to call dffinit with -noreinit" This reverts commit 1f62dc9081feb4852b1848d01951f631853edb38. --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fc0e76bad..8aa7b508e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -250,7 +250,7 @@ struct SynthXilinxPass : public ScriptPass if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); - run("dffinit -noreinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); }