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https://github.com/YosysHQ/yosys
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read_xaiger2: Update box handling
This commit is contained in:
Martin Povišer
parent
3a1b003cc3
commit
f168b2f4b1
1 changed files with 178 additions and 5 deletions
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@ -95,6 +95,8 @@ struct Xaiger2Frontend : public Frontend {
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outputs.push_back(po);
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}
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std::vector<std::pair<Cell *, Module *>> boxes;
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std::vector<bool> retained_boxes;
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std::vector<SigBit> bits(2 + 2*M, RTLIL::Sm);
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bits[0] = RTLIL::S0;
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bits[1] = RTLIL::S1;
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@ -115,6 +117,34 @@ struct Xaiger2Frontend : public Frontend {
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log_error("Map file references non-existent signal bit %s[%d]\n",
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name.c_str(), woffset);
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bits[lit] = SigBit(w, woffset);
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} else if (type == "box") {
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int box_seq;
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std::string name;
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if (!(map_file >> box_seq >> name))
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log_error("Bad map file (20)\n");
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if (box_seq < 0)
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log_error("Bad map file (21)\n");
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Cell *box = module->cell(RTLIL::escape_id(name));
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if (!box)
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log_error("Map file references non-existent box %s\n",
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name.c_str());
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Module *def = design->module(box->type);
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if (def && !box->parameters.empty()) {
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// TODO: This is potentially costly even if a cached derivation exists
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def = design->module(def->derive(design, box->parameters));
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log_assert(def);
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}
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if (!def)
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log_error("Bad map file (22)\n");
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if (box_seq >= boxes.size()) {
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boxes.resize(box_seq + 1);
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retained_boxes.resize(box_seq + 1);
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}
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boxes[box_seq] = std::make_pair(box, def);
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} else {
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std::string scratch;
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std::getline(map_file, scratch);
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@ -130,7 +160,73 @@ struct Xaiger2Frontend : public Frontend {
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log_error("Missing 'c' ahead of extensions\n");
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if (f->peek() == '\n')
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f->get();
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auto extensions_start = f->tellg();
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log_debug("reading 'h' (first pass)\n");
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for (int c = f->get(); c != EOF; c = f->get()) {
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if (c == 'h') {
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uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes;
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len = read_be32(*f);
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read_be32(*f);
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ci_num = read_be32(*f);
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co_num = read_be32(*f);
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pi_num = read_be32(*f);
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po_num = read_be32(*f);
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no_boxes = read_be32(*f);
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log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n",
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len, ci_num, co_num, pi_num, po_num, no_boxes);
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int ci_counter = 0;
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for (uint32_t i = 0; i < no_boxes; i++) {
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uint32_t box_inputs, box_outputs, box_id, box_seq;
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box_inputs = read_be32(*f);
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box_outputs = read_be32(*f);
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box_id = read_be32(*f);
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box_seq = read_be32(*f);
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log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size());
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log_assert(box_seq < boxes.size());
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auto [cell, def] = boxes[box_seq];
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log_assert(cell && def);
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retained_boxes[box_seq] = true;
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int box_ci_idx = 0;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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if (port->port_output) {
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if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width)
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log_error("Malformed design (1)\n");
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SigSpec &conn = cell->connections_[port_id];
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for (int j = 0; j < port->width; j++) {
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if (conn[j].wire && conn[j].wire->port_output)
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conn[j] = module->addWire(module->uniquify(
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stringf("$box$%s$%s$%d",
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cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(),
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port_id.isPublic() ? port_id.c_str() + 1 : port_id.c_str(),
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j)));
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bits[2*(pi_num + ci_counter + box_ci_idx++) + 2] = conn[j];
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}
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}
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}
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log_assert(box_ci_idx == box_outputs);
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ci_counter += box_ci_idx;
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}
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log_assert(pi_num + ci_counter == ci_num);
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} else if (c == '\n') {
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break;
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} else {
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uint32_t len = read_be32(*f);
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f->ignore(len);
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log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len);
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}
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}
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f->seekg(extensions_start);
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bool read_mapping = false;
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uint32_t no_cells, no_instances;
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for (int c = f->get(); c != EOF; c = f->get()) {
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@ -172,10 +268,11 @@ struct Xaiger2Frontend : public Frontend {
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log_assert(bits[out_lit] == RTLIL::Sm);
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log_assert(cell_id < cells.size());
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auto &cell = cells[cell_id];
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Cell *instance = module->addCell(NEW_ID, cell.type);
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auto out_w = module->addWire(NEW_ID);
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Cell *instance = module->addCell(module->uniquify(stringf("$sc%d", out_lit)), cell.type);
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auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit)));
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instance->setPort(cell.out, out_w);
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bits[out_lit] = out_w;
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log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type));
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for (auto in : cell.ins) {
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uint32_t in_lit = read_be32(*f);
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log_assert(out_lit < bits.size());
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@ -195,6 +292,74 @@ struct Xaiger2Frontend : public Frontend {
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if (!read_mapping)
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log_error("Missing mapping (no 'M' section)\n");
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log("Read %d instances with cell library of size %d.\n",
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no_instances, no_cells);
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f->seekg(extensions_start);
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log_debug("reading 'h' (second pass)\n");
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int co_counter = 0;
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for (int c = f->get(); c != EOF; c = f->get()) {
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if (c == 'h') {
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uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes;
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len = read_be32(*f);
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read_be32(*f);
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ci_num = read_be32(*f);
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co_num = read_be32(*f);
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pi_num = read_be32(*f);
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po_num = read_be32(*f);
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no_boxes = read_be32(*f);
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log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n",
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len, ci_num, co_num, pi_num, po_num, no_boxes);
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for (uint32_t i = 0; i < no_boxes; i++) {
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uint32_t box_inputs, box_outputs, box_id, box_seq;
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box_inputs = read_be32(*f);
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box_outputs = read_be32(*f);
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box_id = read_be32(*f);
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box_seq = read_be32(*f);
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log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size());
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log_assert(box_seq < boxes.size());
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auto [cell, def] = boxes[box_seq];
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log_assert(cell && def);
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int box_co_idx = 0;
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for (auto port_id : def->ports) {
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Wire *port = def->wire(port_id);
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SigSpec conn;
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if (port->port_input) {
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if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width)
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log_error("Malformed design (2)\n");
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SigSpec conn;
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for (int j = 0; j < port->width; j++) {
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log_assert(co_counter + box_co_idx < outputs.size());
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int lit = outputs[co_counter + box_co_idx++];
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log_assert(lit >= 0 && lit < bits.size());
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SigBit bit = bits[lit];
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if (bit == RTLIL::Sm)
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log_error("Malformed mapping (1)\n");
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conn.append(bit);
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}
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cell->setPort(port_id, conn);
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}
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}
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log_assert(box_co_idx == box_inputs);
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co_counter += box_co_idx;
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}
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log_assert(po_num + co_counter == co_num);
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} else if (c == '\n') {
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break;
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} else {
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uint32_t len = read_be32(*f);
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f->ignore(len);
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log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len);
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}
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}
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while (true) {
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std::string scratch;
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std::getline(*f, scratch);
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@ -204,10 +369,9 @@ struct Xaiger2Frontend : public Frontend {
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log("input file: %s\n", scratch.c_str());
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}
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log("Read %d instances with cell library of size %d.\n",
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no_instances, no_cells);
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log_debug("co_counter=%d\n", co_counter);
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// TODO
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// TODO: seek without close/open
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map_file.close();
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map_file.open(map_filename);
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while (map_file >> type) {
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@ -217,11 +381,13 @@ struct Xaiger2Frontend : public Frontend {
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std::string name;
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if (!(map_file >> po_idx >> woffset >> name))
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log_error("Bad map file (3)\n");
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po_idx += co_counter;
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if (po_idx < 0 || po_idx >= outputs.size())
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log_error("Bad map file (4)\n");
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int lit = outputs[po_idx];
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if (lit < 0 || lit >= bits.size())
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log_error("Bad map file (5)\n");
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log("output=%d lit=%d\n", po_idx, lit);
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if (bits[lit] == RTLIL::Sm)
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log_error("Bad map file (6)\n");
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Wire *w = module->wire(name);
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@ -236,6 +402,7 @@ struct Xaiger2Frontend : public Frontend {
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std::string box_port;
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if (!(map_file >> po_idx >> poffset >> box_name >> box_port))
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log_error("Bad map file (7)\n");
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po_idx += co_counter;
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if (po_idx < 0 || po_idx >= outputs.size())
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log_error("Bad map file (8)\n");
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int lit = outputs[po_idx];
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@ -257,6 +424,12 @@ struct Xaiger2Frontend : public Frontend {
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std::getline(map_file, scratch);
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}
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}
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int box_seq = 0;
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for (auto [cell, def] : boxes) {
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if (!retained_boxes[box_seq++])
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module->remove(cell);
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}
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, Design *design) override
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