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SystemVerilog also has assume(), added implicit -D FORMAL

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This commit is contained in:
Clifford Wolf 2015-10-13 14:21:20 +02:00
parent 34f34be17c
commit f13e387321
3 changed files with 5 additions and 4 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -170,7 +170,7 @@ YOSYS_NAMESPACE_END
"always_latch" { SV_KEYWORD(TOK_ALWAYS); }
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }