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SystemVerilog also has assume(), added implicit -D FORMAL

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This commit is contained in:
Clifford Wolf 2015-10-13 14:21:20 +02:00
parent 34f34be17c
commit f13e387321
3 changed files with 5 additions and 4 deletions
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4
frontends/verilog/verilog_frontend.cc
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@ -63,8 +63,8 @@ struct VerilogFrontend : public Frontend {
log(" of SystemVerilog is supported)\n");
log("\n");
log(" -formal\n");
log(" enable support for assert() and assume() statements\n");
log(" (assert support is also enabled with -sv)\n");
log(" enable support for assert() and assume() from SystemVerilog\n");
log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
log("\n");
log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n");