mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-20 12:53:39 +00:00
Code Activity

SystemVerilog also has assume(), added implicit -D FORMAL

Browse source
This commit is contained in:
Clifford Wolf 2015-10-13 14:21:20 +02:00
parent 34f34be17c
commit f13e387321
3 changed files with 5 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

3
frontends/verilog/preproc.cc
View file

@ -39,6 +39,7 @@
#include <string.h>
YOSYS_NAMESPACE_BEGIN
using namespace VERILOG_FRONTEND;
static std::list<std::string> output_code;
static std::list<std::string> input_buffer;
@ -222,7 +223,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
input_file(f, filename);
defines_map["YOSYS"] = "1";
defines_map["SYNTHESIS"] = "1";
defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1";
while (!input_buffer.empty())
{