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rm debug logs
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1 changed files with 0 additions and 2 deletions
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@ -1108,7 +1108,6 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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for (size_t i = 0; i < children.size(); i++) {
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for (size_t i = 0; i < children.size(); i++) {
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AstNode *child = children[i];
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AstNode *child = children[i];
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if (child->type == AST_IMPORT) {
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if (child->type == AST_IMPORT) {
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log_debug("Processing import for package: %s\n", child->str.c_str());
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// Find the package in the design
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// Find the package in the design
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AstNode *package_node = nullptr;
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AstNode *package_node = nullptr;
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@ -1126,7 +1125,6 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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// If not found, look in design->verilog_packages (for packages from other files)
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// If not found, look in design->verilog_packages (for packages from other files)
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if (!package_node && simplify_design_context != nullptr) {
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if (!package_node && simplify_design_context != nullptr) {
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log_debug("Looking for package in design context, found %zu packages\n", simplify_design_context->verilog_packages.size());
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for (auto &design_package : simplify_design_context->verilog_packages) {
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for (auto &design_package : simplify_design_context->verilog_packages) {
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// Handle both with and without leading backslash
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// Handle both with and without leading backslash
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std::string package_name = design_package->str;
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std::string package_name = design_package->str;
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