mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-23 16:04:37 +00:00
sim: Make cycle width small as possible and configurable
This commit is contained in:
parent
db8c1878a0
commit
f11a61b32b
2 changed files with 40 additions and 30 deletions
|
@ -10,7 +10,7 @@ logger -expect-no-warnings
|
|||
logger -expect log "Co-simulating cycle 41" 2
|
||||
logger -warn "Co-simulating cycle 42"
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -n 21 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 202 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 41 -sim-cmp
|
||||
logger -check-expected
|
||||
|
||||
# over limit stops at final step
|
||||
|
@ -18,29 +18,29 @@ logger -expect log "Co-simulating cycle 41" 2
|
|||
sim -clock clk -r sim_cycles.fst -scope dff -n 30 -sim-cmp
|
||||
# -stop warns for over limit
|
||||
logger -nowarn "Stop time is after simulation file end time"
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 300 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 50 -sim-cmp
|
||||
logger -check-expected
|
||||
|
||||
# don't auto step last
|
||||
logger -expect log "Co-simulating cycle 40" 2
|
||||
logger -warn "Co-simulating cycle 41"
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -n 20 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 200 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 40 -sim-cmp
|
||||
logger -check-expected
|
||||
|
||||
# -n 10 == -stop 100
|
||||
# -n 10 == -stop 20
|
||||
# should simulate up to 20 and not more
|
||||
logger -expect log "Co-simulating cycle 20" 2
|
||||
logger -warn "Co-simulating cycle 21"
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -n 10 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 100 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 20 -sim-cmp
|
||||
logger -check-expected
|
||||
|
||||
# -n 1 == -stop 10
|
||||
# -n 1 == -stop 2
|
||||
logger -expect log "Co-simulating cycle 2" 2
|
||||
logger -warn "Co-simulating cycle 3"
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -n 1 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 10 -sim-cmp
|
||||
sim -clock clk -r sim_cycles.fst -scope dff -stop 2 -sim-cmp
|
||||
logger -check-expected
|
||||
|
||||
# -n 0 == -stop 0
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue