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fabulous: improvements to the pass

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-11-10 09:53:07 +01:00 • committed by myrtle
parent e3f9ff2679
commit f111bbdf40
13 changed files with 335 additions and 134 deletions
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33
tests/arch/fabulous/regfile.ys Normal file
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read_verilog <<EOT
module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
reg [3:0] mem[0:31];
always @(posedge clk)
if (we) mem[aw] <= wd;
always @(posedge clk)
ra <= mem[aa];
always @(posedge clk)
rb <= mem[ab];
endmodule
EOT
synth_fabulous -top sync_sync
cd sync_sync
select -assert-count 1 t:RegFile_32x4
design -reset
read_verilog <<EOT
module async_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output reg [3:0] ra, rb);
reg [3:0] mem[0:31];
always @(posedge clk)
if (we) mem[aw] <= wd;
always @(posedge clk)
ra <= mem[aa];
always @(*)
rb <= mem[ab];
endmodule
EOT
synth_fabulous -top async_sync
cd async_sync
select -assert-count 1 t:RegFile_32x4