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fabulous: improvements to the pass

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Signed-off-by: gatecat <gatecat@ds0.me>
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gatecat 2022-11-10 09:53:07 +01:00 • committed by myrtle
parent e3f9ff2679
commit f111bbdf40
13 changed files with 335 additions and 134 deletions
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10
tests/arch/fabulous/logic.ys Normal file
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read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-max 1 t:LUT1
select -assert-max 6 t:LUT2
select -assert-max 2 t:LUT4
select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D