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Merge remote-tracking branch 'origin/read_aiger' into xaig

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This commit is contained in:
Eddie Hung 2019-02-13 14:09:36 -08:00
commit f0f5d8a5cc
4 changed files with 12 additions and 17 deletions
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2
backends/verilog/verilog_backend.cc
View file

@ -1251,7 +1251,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str()); f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
std::string init; std::string init;
if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
std::stringstream ss; std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */); dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
init = ss.str(); init = ss.str();

13
frontends/aiger/aigerparse.cc
View file

@ -316,9 +316,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
} }
log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix? module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
inv->setPort("\\A", wire_inv);
inv->setPort("\\Y", wire);
return wire; return wire;
} }
@ -409,7 +407,7 @@ void AigerReader::parse_aiger_ascii(bool create_and)
std::getline(f, line); // Ignore up to start of next line std::getline(f, line); // Ignore up to start of next line
// Parse AND // Parse AND
for (unsigned i = 0; i < A; ++i, ++line_count) { for (unsigned i = 0; i < A; ++i) {
if (!(f >> l1 >> l2 >> l3)) if (!(f >> l1 >> l2 >> l3))
log_error("Line %u cannot be interpreted as an AND!\n", line_count); log_error("Line %u cannot be interpreted as an AND!\n", line_count);
@ -419,14 +417,9 @@ void AigerReader::parse_aiger_ascii(bool create_and)
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
and_cell->setPort("\\A", i1_wire);
and_cell->setPort("\\B", i2_wire);
and_cell->setPort("\\Y", o_wire);
} }
} }
std::getline(f, line); // Ignore up to start of next line
} }
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref) static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)

2
passes/techmap/abc.cc
View file

@ -52,6 +52,8 @@
#include <cerrno> #include <cerrno>
#include <sstream> #include <sstream>
#include <climits> #include <climits>
#include <array>
#include <functional>
#ifndef _WIN32 #ifndef _WIN32
# include <unistd.h> # include <unistd.h>

12
techlibs/common/simlib.v
View file

@ -1464,7 +1464,7 @@ module \$dff (CLK, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK; input CLK;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
@ -1484,7 +1484,7 @@ module \$dffe (CLK, EN, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK, EN; input CLK, EN;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
@ -1506,7 +1506,7 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK; input CLK;
input [WIDTH-1:0] SET, CLR, D; input [WIDTH-1:0] SET, CLR, D;
@ -1540,7 +1540,7 @@ parameter WIDTH = 0;
parameter CLK_POLARITY = 1'b1; parameter CLK_POLARITY = 1'b1;
parameter ARST_POLARITY = 1'b1; parameter ARST_POLARITY = 1'b1;
parameter ARST_VALUE = 0; parameter ARST_VALUE = 0;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input CLK, ARST; input CLK, ARST;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
@ -1563,7 +1563,7 @@ module \$dlatch (EN, D, Q);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input EN; input EN;
input [WIDTH-1:0] D; input [WIDTH-1:0] D;
@ -1585,7 +1585,7 @@ parameter WIDTH = 0;
parameter EN_POLARITY = 1'b1; parameter EN_POLARITY = 1'b1;
parameter SET_POLARITY = 1'b1; parameter SET_POLARITY = 1'b1;
parameter CLR_POLARITY = 1'b1; parameter CLR_POLARITY = 1'b1;
parameter INIT = {WIDTH{1'bx}}; parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
input EN; input EN;
input [WIDTH-1:0] SET, CLR, D; input [WIDTH-1:0] SET, CLR, D;