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[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
ccfb4ff2a9
commit
f0f352e971
4 changed files with 77 additions and 15 deletions
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@ -728,7 +728,7 @@ module DSP48E1 (
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maj_xyz_gated[23] ^ int_carry_out[1],
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1'bx
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};
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end else if (USE_SIMD == "FOUR48") begin
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end else begin
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assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin};
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assign int_carry_in[3:1] = int_carry_out[2:0];
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assign ext_carry_out = {
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@ -738,7 +738,7 @@ module DSP48E1 (
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end
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genvar i;
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for (i = 0; i < 4; i++)
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for (i = 0; i < 4; i = i + 1)
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assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]}
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+ xor_xyz_muxed[i*12 +: 12] + int_carry_in[i];
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endgenerate
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4
techlibs/xilinx/tests/.gitignore
vendored
4
techlibs/xilinx/tests/.gitignore
vendored
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@ -5,3 +5,7 @@ bram2.log
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bram2_syn.v
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bram2_tb
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dsp_work*/
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test_dsp_model_ref.v
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test_dsp_model_uut.v
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test_dsp_model
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*.vcd
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11
techlibs/xilinx/tests/test_dsp_model.sh
Normal file
11
techlibs/xilinx/tests/test_dsp_model.sh
Normal file
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@ -0,0 +1,11 @@
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#!/bin/bash
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set -ex
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sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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if [ ! -f "test_dsp_model_ref.v" ]; then
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cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
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fi
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for tb in mult_noreg_nopreadd_nocasc
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do
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
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vvp -N ./test_dsp_model
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done
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@ -83,12 +83,21 @@ module testbench;
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reg config_valid = 0;
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task drc;
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config_valid = 1;
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if (AREG != 2 && INMODE[0]) config_valid = 0;
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if (BREG != 2 && INMODE[4]) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
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begin
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config_valid = 1;
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if (AREG != 2 && INMODE[0]) config_valid = 0;
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if (BREG != 2 && INMODE[4]) config_valid = 0;
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if (OPMODE[1:0] == 2'b10 && PREG != 1) config_valid = 0;
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if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b010 || OPMODE[6:4] == 3'b110) && PREG != 1) config_valid = 0;
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if ((OPMODE[6:4] == 3'b100) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
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if ((CARRYINSEL == 3'b100 || CARRYINSEL == 3'b101 || CARRYINSEL == 3'b111) && (PREG != 1)) config_valid = 0;
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if (OPMODE[6:4] == 3'b111) config_valid = 0;
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if ((ALUMODE[3:2] == 2'b01 || ALUMODE[3:2] == 2'b11) && OPMODE[3:2] != 2'b00 && OPMODE[3:2] != 2'b10) config_valid = 0;
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if ((OPMODE[3:0] == 4'b0101) && CARRYINSEL == 3'b010) config_valid = 0;
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if (CARRYINSEL == 3'b010 && OPMODE != 7'b0001010) config_valid = 0;
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if (CARRYINSEL == 3'b001 && OPMODE != 7'b1010101) config_valid = 0;
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end
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endtask
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initial begin
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@ -109,7 +118,7 @@ module testbench;
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#5;
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CLK = 1'b1;
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#10;
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CLK = 1'b0
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CLK = 1'b0;
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#5;
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CLK = 1'b1;
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#10;
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@ -118,7 +127,8 @@ module testbench;
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repeat (300) begin
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clkcycle;
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do begin
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config_valid = 0;
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while (!config_valid) begin
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A = $urandom;
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ACIN = $urandom;
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B = $urandom;
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@ -130,9 +140,11 @@ module testbench;
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{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom;
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{ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom;
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OPMODE = $urandom;
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if ($urandom & 1'b1)
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OPMODE[3:0] = 4'b0101; // test multiply more than other modes
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{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
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drc;
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end while (!config_valid);
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end
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end
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if (errcount == 0) begin
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@ -194,6 +206,7 @@ module testbench;
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.BCIN (BCIN),
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.C (C),
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.CARRYCASCIN (CARRYCASCIN),
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.CARRYINSEL (CARRYINSEL),
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.CEA1 (CEA1),
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.CEA2 (CEA2),
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.CEAD (CEAD),
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@ -275,6 +288,7 @@ module testbench;
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.BCIN (BCIN),
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.C (C),
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.CARRYCASCIN (CARRYCASCIN),
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.CARRYINSEL (CARRYINSEL),
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.CEA1 (CEA1),
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.CEA2 (CEA2),
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.CEAD (CEAD),
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@ -305,6 +319,39 @@ module testbench;
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.RSTM (RSTM),
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.RSTP (RSTP)
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);
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endmodule
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module mult_noreg_nopreadd_nocasc;
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testbench #(
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.ACASCREG (0),
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.ADREG (0),
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.ALUMODEREG (0),
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.AREG (0),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (0),
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.BREG (0),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (0),
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.DREG (0),
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.INMODEREG (0),
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.MREG (0),
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.OPMODEREG (0),
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.PREG (0),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("FALSE"),
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.USE_MULT ("DYNAMIC"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"),
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.MASK (48'h3FFFFFFFFFFF),
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.PATTERN (48'h000000000000),
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.IS_ALUMODE_INVERTED(4'b0),
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.IS_CARRYIN_INVERTED(1'b0),
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.IS_CLK_INVERTED (1'b0),
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.IS_INMODE_INVERTED (5'b0),
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.IS_OPMODE_INVERTED (7'b0)
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) testbench ();
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endmodule
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