Merge branch 'YosysHQ:main' into master

.github/workflows/extra-builds.yml

@@ -81,3 +81,17 @@ jobs:
           END
 
           make -C build -f ../Makefile CXX=clang -j$(nproc)
+
+  nix-build:
+    name: "Build nix flake"
+    needs: pre_job
+    if: needs.pre_job.outputs.should_skip != 'true'
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: true
+      - uses: cachix/install-nix-action@v26
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.18.1/install
+      - run: nix build .?submodules=1

.github/workflows/nix-github-actions.yml

@@ -1,15 +0,0 @@
-name: "build nix flake"
-on:
-  pull_request:
-  push:
-jobs:
-  tests:
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v4
-      with:
-       submodules: true
-    - uses: cachix/install-nix-action@v26
-      with:
-       install_url: https://releases.nixos.org/nix/nix-2.18.1/install
-    - run: nix build .?submodules=1

Makefile

@@ -140,7 +140,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.41+101
+YOSYS_VER := 0.41+108
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -949,7 +949,13 @@ define DOC_USAGE_STDERR
 docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated
 	-$(Q) ./$$< --help 2> $$@
 endef
-DOCS_USAGE_STDERR := yosys-config yosys-filterlib yosys-abc
+DOCS_USAGE_STDERR := yosys-config yosys-filterlib
+
+# The in-tree ABC (yosys-abc) is only built when ABCEXTERNAL is not set.
+ifeq ($(ABCEXTERNAL),)
+DOCS_USAGE_STDERR += yosys-abc
+endif
+
 $(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage))))
 
 # others print to stdout

backends/cxxrtl/cxxrtl_backend.cc

@@ -3263,6 +3263,7 @@ struct CxxrtlWorker {
 						debug_wire_type = wire_type; // wire is a member
 
 					if (!debug_alias) continue;
+					if (wire->port_input || wire->port_output) continue; // preserve input/output metadata in flags
 					const RTLIL::Wire *it = wire;
 					while (flow.is_inlinable(it)) {
 						log_assert(flow.wire_comb_defs[it].size() == 1);