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Merge pull request #868 from YosysHQ/clifford/fixmem

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Various mem2reg-related improvements in handling of memories
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Clifford Wolf 2019-03-13 13:40:30 +01:00 committed by GitHub
parent 1cd04a6838 9284cf92b8
commit f0b2d8e467
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GPG key ID: 4AEE18F83AFDEB23
2 changed files with 24 additions and 40 deletions
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45
frontends/ast/simplify.cc
View file

@ -50,7 +50,6 @@ using namespace AST_INTERNAL;
bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param)
{ {
static int recursion_counter = 0; static int recursion_counter = 0;
static pair<string, int> last_blocking_assignment_warn;
static bool deep_recursion_warning = false; static bool deep_recursion_warning = false;
if (recursion_counter++ == 1000 && deep_recursion_warning) { if (recursion_counter++ == 1000 && deep_recursion_warning) {
@ -72,7 +71,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (stage == 0) if (stage == 0)
{ {
log_assert(type == AST_MODULE || type == AST_INTERFACE); log_assert(type == AST_MODULE || type == AST_INTERFACE);
last_blocking_assignment_warn = pair<string, int>();
deep_recursion_warning = true; deep_recursion_warning = true;
while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
@ -1592,14 +1590,6 @@ skip_dynamic_range_lvalue_expansion:;
sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN"; std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
if (type == AST_ASSIGN_EQ) {
pair<string, int> this_blocking_assignment_warn(filename, linenum);
if (this_blocking_assignment_warn != last_blocking_assignment_warn)
log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
filename.c_str(), linenum);
last_blocking_assignment_warn = this_blocking_assignment_warn;
}
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
bool mem_signed = children[0]->id2ast->is_signed; bool mem_signed = children[0]->id2ast->is_signed;
children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);
@ -2928,7 +2918,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags) dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
{ {
uint32_t children_flags = 0; uint32_t children_flags = 0;
int ignore_children_counter = 0; int lhs_children_counter = 0;
if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ)
{ {
@ -2954,12 +2944,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1; proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
} }
// remember if this is a constant index or not // for proper (non-init) writes: remember if this is a constant index or not
if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) { if ((flags & MEM2REG_FL_INIT) == 0) {
if (children[0]->children[0]->children[0]->type == AST_CONSTANT) if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS; if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
else mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS; else
mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
}
} }
// remember where this is // remember where this is
@ -2974,7 +2966,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
} }
} }
ignore_children_counter = 1; lhs_children_counter = 1;
} }
if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY) if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY)
@ -3017,12 +3009,23 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
log_assert((flags & ~0x000000ff) == 0); log_assert((flags & ~0x000000ff) == 0);
for (auto child : children) for (auto child : children)
if (ignore_children_counter > 0) {
ignore_children_counter--; if (lhs_children_counter > 0) {
else if (proc_flags_p) lhs_children_counter--;
if (child->children.size() && child->children[0]->type == AST_RANGE && child->children[0]->children.size()) {
for (auto c : child->children[0]->children) {
if (proc_flags_p)
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
else
c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
}
}
} else
if (proc_flags_p)
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags); child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
else else
child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags); child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
}
flags &= ~children_flags | backup_flags; flags &= ~children_flags | backup_flags;

19
techlibs/ice40/cells_sim.v
View file

@ -414,24 +414,6 @@ module SB_RAM40_4K (
$readmemh(INIT_FILE, memory); $readmemh(INIT_FILE, memory);
else else
for (i=0; i<16; i=i+1) begin for (i=0; i<16; i=i+1) begin
`ifdef YOSYS
memory[ 0*16 + i] <= INIT_0[16*i +: 16];
memory[ 1*16 + i] <= INIT_1[16*i +: 16];
memory[ 2*16 + i] <= INIT_2[16*i +: 16];
memory[ 3*16 + i] <= INIT_3[16*i +: 16];
memory[ 4*16 + i] <= INIT_4[16*i +: 16];
memory[ 5*16 + i] <= INIT_5[16*i +: 16];
memory[ 6*16 + i] <= INIT_6[16*i +: 16];
memory[ 7*16 + i] <= INIT_7[16*i +: 16];
memory[ 8*16 + i] <= INIT_8[16*i +: 16];
memory[ 9*16 + i] <= INIT_9[16*i +: 16];
memory[10*16 + i] <= INIT_A[16*i +: 16];
memory[11*16 + i] <= INIT_B[16*i +: 16];
memory[12*16 + i] <= INIT_C[16*i +: 16];
memory[13*16 + i] <= INIT_D[16*i +: 16];
memory[14*16 + i] <= INIT_E[16*i +: 16];
memory[15*16 + i] <= INIT_F[16*i +: 16];
`else
memory[ 0*16 + i] = INIT_0[16*i +: 16]; memory[ 0*16 + i] = INIT_0[16*i +: 16];
memory[ 1*16 + i] = INIT_1[16*i +: 16]; memory[ 1*16 + i] = INIT_1[16*i +: 16];
memory[ 2*16 + i] = INIT_2[16*i +: 16]; memory[ 2*16 + i] = INIT_2[16*i +: 16];
@ -448,7 +430,6 @@ module SB_RAM40_4K (
memory[13*16 + i] = INIT_D[16*i +: 16]; memory[13*16 + i] = INIT_D[16*i +: 16];
memory[14*16 + i] = INIT_E[16*i +: 16]; memory[14*16 + i] = INIT_E[16*i +: 16];
memory[15*16 + i] = INIT_F[16*i +: 16]; memory[15*16 + i] = INIT_F[16*i +: 16];
`endif
end end
end end