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Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

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Alberto Gonzalez 2020-02-23 07:19:52 +00:00
parent 6edca05793
commit f0afd65035
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9 changed files with 384 additions and 301 deletions
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frontends/verilog/verilog_frontend.h
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@ -87,7 +87,6 @@ YOSYS_NAMESPACE_END
// the usual bison/flex stuff
extern int frontend_verilog_yydebug;
int frontend_verilog_yylex(void);
void frontend_verilog_yyerror(char const *fmt, ...);
void frontend_verilog_yyrestart(FILE *f);
int frontend_verilog_yyparse(void);