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Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
This commit is contained in:
Alberto Gonzalez
parent
6edca05793
commit
f0afd65035
9 changed files with 384 additions and 301 deletions
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@ -44,18 +44,18 @@ using namespace AST_INTERNAL;
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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std::stringstream sstr;
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sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (gen_attributes)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -77,18 +77,18 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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}
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std::stringstream sstr;
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sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
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sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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if (that != NULL)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -105,17 +105,17 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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std::stringstream sstr;
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sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
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sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -139,17 +139,17 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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log_assert(cond.size() == 1);
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std::stringstream sstr;
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sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
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sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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cell->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -199,11 +199,11 @@ struct AST_INTERNAL::ProcessGenerator
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{
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// generate process and simple root case
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proc = new RTLIL::Process;
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proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
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proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
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proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
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log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
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attr.first.c_str());
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proc->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -234,8 +234,8 @@ struct AST_INTERNAL::ProcessGenerator
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if (found_anyedge_syncs) {
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if (found_global_syncs)
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log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
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log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
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log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
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log("Note: Assuming pure combinatorial block at %s:%d.%d-%d.%d in\n", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
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log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
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}
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@ -249,12 +249,12 @@ struct AST_INTERNAL::ProcessGenerator
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continue;
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found_clocked_sync = true;
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if (found_global_syncs || found_anyedge_syncs)
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log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
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log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
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RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
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syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
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syncrule->signal = child->children[0]->genRTLIL();
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if (GetSize(syncrule->signal) != 1)
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log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
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log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
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addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
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proc->syncs.push_back(syncrule);
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}
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@ -335,7 +335,7 @@ struct AST_INTERNAL::ProcessGenerator
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} while (current_module->wires_.count(wire_name) > 0);
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RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
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wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
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wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
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chunk.wire = wire;
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chunk.offset = 0;
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@ -470,13 +470,13 @@ struct AST_INTERNAL::ProcessGenerator
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case AST_CASE:
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{
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RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
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sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
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sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
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sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
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current_case->switches.push_back(sw);
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
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sw->attributes[attr.first] = attr.second->asAttrConst();
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}
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@ -504,7 +504,7 @@ struct AST_INTERNAL::ProcessGenerator
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RTLIL::CaseRule *backup_case = current_case;
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current_case = new RTLIL::CaseRule;
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current_case->attributes["\\src"] = stringf("%s:%d", child->filename.c_str(), child->linenum);
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current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
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last_generated_case = current_case;
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addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
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for (auto node : child->children) {
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@ -554,16 +554,16 @@ struct AST_INTERNAL::ProcessGenerator
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break;
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case AST_WIRE:
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log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
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log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n");
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break;
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case AST_ASSIGN:
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log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
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log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n");
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break;
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case AST_PARAMETER:
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case AST_LOCALPARAM:
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log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
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log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n");
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break;
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case AST_NONE:
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@ -614,7 +614,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (id_ast == NULL && current_scope.count(str))
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id_ast = current_scope.at(str);
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if (!id_ast)
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log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
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if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
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if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
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this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
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@ -624,7 +624,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (id_ast->children[0]->type == AST_CONSTANT)
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this_width = id_ast->children[0]->bits.size();
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else
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log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str());
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if (children.size() != 0)
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range = children[0];
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} else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
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@ -636,7 +636,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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// log("---\n");
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// id_ast->dumpAst(NULL, "decl> ");
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// dumpAst(NULL, "ref> ");
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log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str());
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}
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} else {
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this_width = id_ast->range_left - id_ast->range_right + 1;
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@ -647,12 +647,12 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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this_width = 32;
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} else if (id_ast->type == AST_MEMORY) {
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if (!id_ast->children[0]->range_valid)
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log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
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this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
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if (children.size() > 1)
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range = children[1];
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} else
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log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());
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if (range) {
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if (range->children.size() == 1)
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this_width = 1;
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@ -662,7 +662,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
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if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
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log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
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this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
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delete left_at_zero_ast;
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delete right_at_zero_ast;
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@ -678,7 +678,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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case AST_TO_BITS:
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while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
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log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n");
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children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
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width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
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break;
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@ -706,7 +706,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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case AST_REPLICATE:
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while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
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log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
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children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
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width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
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sign_hint = false;
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@ -780,7 +780,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (!id2ast->is_signed)
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sign_hint = false;
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if (!id2ast->children[0]->range_valid)
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log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
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log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
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this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
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width_hint = max(width_hint, this_width);
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break;
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@ -790,7 +790,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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if (GetSize(children) == 1) {
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while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
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if (children[0]->type != AST_CONSTANT)
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log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
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log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
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RTLIL::unescape_id(str).c_str());
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width_hint = max(width_hint, int(children[0]->asInt(true)));
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}
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@ -812,7 +812,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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default:
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for (auto f : log_files)
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current_ast_mod->dumpAst(f, "verilog-ast> ");
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log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
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log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
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}
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if (*found_real)
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@ -845,7 +845,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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std::string type_name;
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current_filename = filename;
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set_line_num(linenum);
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switch (type)
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{
|
||||
|
|
@ -874,7 +873,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// This is used by the hierarchy pass to know when it can replace interface connection with the individual
|
||||
// signals.
|
||||
RTLIL::Wire *wire = current_module->addWire(str, 1);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->start_offset = 0;
|
||||
wire->port_id = port_id;
|
||||
wire->port_input = true;
|
||||
|
|
@ -905,18 +904,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (flag_pwires)
|
||||
{
|
||||
if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Parameter `%s' with non-constant value!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str());
|
||||
|
||||
RTLIL::Const val = children[0]->bitsAsConst();
|
||||
RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
|
||||
current_module->connect(wire, val);
|
||||
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
|
||||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
wire->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
}
|
||||
|
|
@ -925,15 +924,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// create an RTLIL::Wire for an AST_WIRE node
|
||||
case AST_WIRE: {
|
||||
if (current_module->wires_.count(str) != 0)
|
||||
log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Re-definition of signal `%s'!\n", str.c_str());
|
||||
if (!range_valid)
|
||||
log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
|
||||
|
||||
if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
|
||||
log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
|
||||
log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
|
||||
|
||||
RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->start_offset = range_right;
|
||||
wire->port_id = port_id;
|
||||
wire->port_input = is_input;
|
||||
|
|
@ -942,7 +941,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
wire->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
|
||||
|
|
@ -954,17 +953,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
// create an RTLIL::Memory for an AST_MEMORY node
|
||||
case AST_MEMORY: {
|
||||
if (current_module->memories.count(str) != 0)
|
||||
log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Re-definition of memory `%s'!\n", str.c_str());
|
||||
|
||||
log_assert(children.size() >= 2);
|
||||
log_assert(children[0]->type == AST_RANGE);
|
||||
log_assert(children[1]->type == AST_RANGE);
|
||||
|
||||
if (!children[0]->range_valid || !children[1]->range_valid)
|
||||
log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
|
||||
|
||||
RTLIL::Memory *memory = new RTLIL::Memory;
|
||||
memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
memory->name = str;
|
||||
memory->width = children[0]->range_left - children[0]->range_right + 1;
|
||||
if (children[1]->range_right < children[1]->range_left) {
|
||||
|
|
@ -978,7 +977,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
memory->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
}
|
||||
|
|
@ -1001,7 +1000,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
RTLIL::SigSpec sig = realAsConst(width_hint);
|
||||
log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
|
||||
log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
|
||||
return sig;
|
||||
}
|
||||
|
||||
|
|
@ -1019,16 +1018,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
|
||||
RTLIL::Wire *wire = current_module->addWire(str);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
wire->name = str;
|
||||
if (flag_autowire)
|
||||
log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
else
|
||||
log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
||||
}
|
||||
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
|
||||
if (id2ast->children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str());
|
||||
chunk = RTLIL::Const(id2ast->children[0]->bits);
|
||||
goto use_const_chunk;
|
||||
}
|
||||
|
|
@ -1043,11 +1042,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
is_interface = true;
|
||||
}
|
||||
else {
|
||||
log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
|
||||
}
|
||||
|
||||
if (id2ast->type == AST_MEMORY)
|
||||
log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
|
||||
|
||||
// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
|
||||
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
|
||||
|
|
@ -1073,7 +1072,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
use_const_chunk:
|
||||
if (children.size() != 0) {
|
||||
if (children[0]->type != AST_RANGE)
|
||||
log_file_error(filename, linenum, "Single range expected.\n");
|
||||
log_file_error(filename, location.first_line, "Single range expected.\n");
|
||||
int source_width = id2ast->range_left - id2ast->range_right + 1;
|
||||
int source_offset = id2ast->range_right;
|
||||
if (!children[0]->range_valid) {
|
||||
|
|
@ -1082,7 +1081,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
|
||||
while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
|
||||
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
||||
AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
children[0]->children[1]->clone() : children[0]->children[0]->clone());
|
||||
|
|
@ -1110,10 +1109,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
|
||||
if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
|
||||
if (chunk.width == 1)
|
||||
log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
|
||||
log_file_warning(filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
|
||||
str.c_str());
|
||||
else
|
||||
log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
|
||||
log_file_warning(filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
|
||||
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
|
||||
} else {
|
||||
|
|
@ -1127,10 +1126,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
chunk.offset += add_undef_bits_lsb;
|
||||
}
|
||||
if (add_undef_bits_lsb)
|
||||
log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
|
||||
log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
|
||||
if (add_undef_bits_msb)
|
||||
log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
|
||||
log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
|
||||
}
|
||||
}
|
||||
|
|
@ -1170,7 +1169,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
RTLIL::SigSpec left = children[0]->genRTLIL();
|
||||
RTLIL::SigSpec right = children[1]->genRTLIL();
|
||||
if (!left.is_fully_const())
|
||||
log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
|
||||
log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
|
||||
int count = left.as_int();
|
||||
RTLIL::SigSpec sig;
|
||||
for (int i = 0; i < count; i++)
|
||||
|
|
@ -1360,13 +1359,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
case AST_MEMRD:
|
||||
{
|
||||
std::stringstream sstr;
|
||||
sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
|
||||
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
|
||||
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
is_signed = id2ast->is_signed;
|
||||
|
|
@ -1398,10 +1397,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
case AST_MEMINIT:
|
||||
{
|
||||
std::stringstream sstr;
|
||||
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
|
||||
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
|
||||
int mem_width, mem_size, addr_bits;
|
||||
id2ast->meminfo(mem_width, mem_size, addr_bits);
|
||||
|
|
@ -1409,7 +1408,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int num_words = 1;
|
||||
if (type == AST_MEMINIT) {
|
||||
if (children[2]->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
|
||||
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
|
||||
num_words = int(children[2]->asInt(false));
|
||||
cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
|
||||
}
|
||||
|
|
@ -1461,18 +1460,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
IdString cellname;
|
||||
if (str.empty()) {
|
||||
std::stringstream sstr;
|
||||
sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
|
||||
sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
|
||||
cellname = sstr.str();
|
||||
} else {
|
||||
cellname = str;
|
||||
}
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
|
||||
|
|
@ -1493,7 +1492,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
new_left.append(left[i]);
|
||||
new_right.append(right[i]);
|
||||
}
|
||||
log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
|
||||
log_file_warning(filename, location.first_line, "Ignoring assignment to constant bits:\n"
|
||||
" old assignment: %s = %s\n new assignment: %s = %s.\n",
|
||||
log_signal(left), log_signal(right),
|
||||
log_signal(new_left), log_signal(new_right));
|
||||
|
|
@ -1510,10 +1509,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int port_counter = 0, para_counter = 0;
|
||||
|
||||
if (current_module->count_id(str) != 0)
|
||||
log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(str, "");
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
|
||||
cell->set_bool_attribute("\\module_not_derived");
|
||||
|
||||
|
|
@ -1529,7 +1528,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int extra_const_flags = 0;
|
||||
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
|
||||
if (child->children[0]->type == AST_REALVALUE) {
|
||||
log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_id(cell), log_id(paraname), child->children[0]->realvalue);
|
||||
extra_const_flags = RTLIL::CONST_FLAG_REAL;
|
||||
auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
|
||||
|
|
@ -1537,7 +1536,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
delete strnode;
|
||||
}
|
||||
if (child->children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
|
||||
log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",
|
||||
log_id(cell), log_id(paraname));
|
||||
cell->parameters[paraname] = child->children[0]->asParaConst();
|
||||
cell->parameters[paraname].flags |= extra_const_flags;
|
||||
|
|
@ -1560,7 +1559,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
for (auto &attr : attributes) {
|
||||
if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
|
||||
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
|
||||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
if (cell->type == "$specify2") {
|
||||
|
|
@ -1568,7 +1567,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int dst_width = GetSize(cell->getPort("\\DST"));
|
||||
bool full = cell->getParam("\\FULL").as_bool();
|
||||
if (!full && src_width != dst_width)
|
||||
log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
|
||||
log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
|
||||
cell->setParam("\\SRC_WIDTH", Const(src_width));
|
||||
cell->setParam("\\DST_WIDTH", Const(dst_width));
|
||||
}
|
||||
|
|
@ -1576,7 +1575,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int dat_width = GetSize(cell->getPort("\\DAT"));
|
||||
int dst_width = GetSize(cell->getPort("\\DST"));
|
||||
if (dat_width != dst_width)
|
||||
log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
|
||||
log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
|
||||
int src_width = GetSize(cell->getPort("\\SRC"));
|
||||
cell->setParam("\\SRC_WIDTH", Const(src_width));
|
||||
cell->setParam("\\DST_WIDTH", Const(dst_width));
|
||||
|
|
@ -1608,30 +1607,30 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int sz = children.size();
|
||||
if (str == "$info") {
|
||||
if (sz > 0)
|
||||
log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str());
|
||||
log_file_info(filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_info(filename, linenum, "\n");
|
||||
log_file_info(filename, location.first_line, "\n");
|
||||
} else if (str == "$warning") {
|
||||
if (sz > 0)
|
||||
log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str());
|
||||
log_file_warning(filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_warning(filename, linenum, "\n");
|
||||
log_file_warning(filename, location.first_line, "\n");
|
||||
} else if (str == "$error") {
|
||||
if (sz > 0)
|
||||
log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str());
|
||||
log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_error(filename, linenum, "\n");
|
||||
log_file_error(filename, location.first_line, "\n");
|
||||
} else if (str == "$fatal") {
|
||||
// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
|
||||
// if no parameter is given, default value is 1
|
||||
// dollar_finish(sz ? children[0] : 1);
|
||||
// perhaps create & use log_file_fatal()
|
||||
if (sz > 0)
|
||||
log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str());
|
||||
log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_error(filename, linenum, "FATAL.\n");
|
||||
log_file_error(filename, location.first_line, "FATAL.\n");
|
||||
} else {
|
||||
log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str());
|
||||
log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str());
|
||||
}
|
||||
} break;
|
||||
|
||||
|
|
@ -1642,32 +1641,32 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int width = width_hint;
|
||||
|
||||
if (GetSize(children) > 1)
|
||||
log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
|
||||
log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n",
|
||||
RTLIL::unescape_id(str).c_str(), GetSize(children));
|
||||
|
||||
if (GetSize(children) == 1) {
|
||||
if (children[0]->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
|
||||
log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
|
||||
RTLIL::unescape_id(str).c_str());
|
||||
width = children[0]->asInt(true);
|
||||
}
|
||||
|
||||
if (width <= 0)
|
||||
log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
|
||||
|
||||
Cell *cell = current_module->addCell(myid, str.substr(1));
|
||||
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->parameters["\\WIDTH"] = width;
|
||||
|
||||
if (attributes.count("\\reg")) {
|
||||
auto &attr = attributes.at("\\reg");
|
||||
if (attr->type != AST_CONSTANT)
|
||||
log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
|
||||
log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
|
||||
cell->attributes["\\reg"] = attr->asAttrConst();
|
||||
}
|
||||
|
||||
Wire *wire = current_module->addWire(myid + "_wire", width);
|
||||
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
|
||||
wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
|
||||
cell->setPort("\\Y", wire);
|
||||
|
||||
is_signed = sign_hint;
|
||||
|
|
@ -1680,7 +1679,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
for (auto f : log_files)
|
||||
current_ast_mod->dumpAst(f, "verilog-ast> ");
|
||||
type_name = type2str(type);
|
||||
log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
|
||||
log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
|
||||
}
|
||||
|
||||
return RTLIL::SigSpec();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue