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Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

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This commit is contained in:
Alberto Gonzalez 2020-02-23 07:19:52 +00:00
parent 6edca05793
commit f0afd65035
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9 changed files with 384 additions and 301 deletions
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9
frontends/ast/ast.h
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@ -156,6 +156,13 @@ namespace AST
AST_TYPEDEF
};
struct AstSrcLocType {
unsigned int first_line, last_line;
unsigned int first_column, last_column;
AstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}
AstSrcLocType(int _first_line, int _first_column, int _last_line, int _last_column) : first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}
};
// convert an node type to a string (e.g. for debug output)
std::string type2str(AstNodeType type);
@ -199,7 +206,7 @@ namespace AST
// it is automatically set by the constructor using AST::current_filename and
// the AST::get_line_num() callback function.
std::string filename;
int linenum;
AstSrcLocType location;
// creating and deleting nodes
AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL, AstNode *child3 = NULL);