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opt_share: Fix input confusion with ANDNOT, ORNOT gates

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Distinguish between the A, B input ports of `$_ANDNOT_`, `$_ORNOT_`
gates when considering those for sharing. Unlike the input ports of the
other supported single-bit gates, those are not interchangeable.

Fixes #3848.
This commit is contained in:
Martin Povišer 2023-07-19 20:08:22 +02:00 • committed by Lofty
parent 83c9261d6c
commit f0ae046c5a
2 changed files with 31 additions and 0 deletions
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28
tests/opt/bug3848.ys Normal file
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read_verilog -icells <<EOF
module test(a, b, s, y);
input a, b, s;
output y;
wire f, g;
$_ANDNOT_ g1(.A(a), .B(b), .Y(f));
$_ANDNOT_ g2(.A(b), .B(a), .Y(g));
$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
endmodule
EOF
equiv_opt -assert opt_share
design -reset
read_verilog -icells <<EOF
module test(a, b, s, y);
input a, b, s;
output y;
wire f, g;
$_ORNOT_ g1(.A(a), .B(b), .Y(f));
$_ORNOT_ g2(.A(b), .B(a), .Y(g));
$_MUX_ m(.A(f), .B(g), .S(s), .Y(y));
endmodule
EOF
equiv_opt -assert opt_share