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sv: support declaration in procedural for initialization

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In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
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Zachary Snow 2021-08-30 11:35:36 -06:00 • committed by Zachary Snow
parent 1dbf91a8ef
commit f0a52e3dd2
5 changed files with 104 additions and 1 deletions
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6
tests/verilog/for_decl_shadow.ys Normal file
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@ -0,0 +1,6 @@
read_verilog -sv for_decl_shadow.sv
hierarchy
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert