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sv: support declaration in procedural for initialization

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In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.
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Zachary Snow 2021-08-30 11:35:36 -06:00 • committed by Zachary Snow
parent 1dbf91a8ef
commit f0a52e3dd2
5 changed files with 104 additions and 1 deletions
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32
tests/verilog/for_decl_shadow.sv Normal file
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module gate(x);
output reg [15:0] x;
if (1) begin : gen
integer x;
initial begin
for (integer x = 5; x < 10; x++)
if (x == 5)
gen.x = 0;
else
gen.x += 2 ** x;
x = x * 2;
end
end
initial x = gen.x;
endmodule
module gold(x);
output reg [15:0] x;
if (1) begin : gen
integer x;
integer z;
initial begin
for (z = 5; z < 10; z++)
if (z == 5)
x = 0;
else
x += 2 ** z;
x = x * 2;
end
end
initial x = gen.x;
endmodule