sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.

tests/verilog/for_decl_no_init.ys

@@ -0,0 +1,9 @@
+logger -expect error "For loop variable declaration is missing initialization!" 1
+read_verilog -sv <<EOT
+module top;
+    integer z;
+    initial
+        for (integer i; i < 10; i = i + 1)
+            z = i;
+endmodule
+EOT