sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.

tests/verilog/for_decl_no_init.ys

@@ -0,0 +1,9 @@
+logger -expect error "For loop variable declaration is missing initialization!" 1
+read_verilog -sv <<EOT
+module top;
+    integer z;
+    initial
+        for (integer i; i < 10; i = i + 1)
+            z = i;
+endmodule
+EOT

tests/verilog/for_decl_no_sv.ys

@@ -0,0 +1,9 @@
+logger -expect error "For loop inline variable declaration is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+    integer z;
+    initial
+        for (integer i = 1; i < 10; i = i + 1)
+            z = i;
+endmodule
+EOT

tests/verilog/for_decl_shadow.sv

@@ -0,0 +1,32 @@
+module gate(x);
+	output reg [15:0] x;
+	if (1) begin : gen
+		integer x;
+		initial begin
+			for (integer x = 5; x < 10; x++)
+				if (x == 5)
+					gen.x = 0;
+				else
+					gen.x += 2 ** x;
+			x = x * 2;
+		end
+	end
+	initial x = gen.x;
+endmodule
+
+module gold(x);
+	output reg [15:0] x;
+	if (1) begin : gen
+		integer x;
+		integer z;
+		initial begin
+			for (z = 5; z < 10; z++)
+				if (z == 5)
+					x = 0;
+				else
+					x += 2 ** z;
+			x = x * 2;
+		end
+	end
+	initial x = gen.x;
+endmodule

tests/verilog/for_decl_shadow.ys

@@ -0,0 +1,6 @@
+read_verilog -sv for_decl_shadow.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert