mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Resolve struct member multiple dimensions defined in stages with typedef

Browse source
This commit is contained in:
Dag Lem 2024-01-05 19:29:06 +01:00 • committed by Zachary Snow
parent fab326d3e8
commit f09ea16bd1
3 changed files with 62 additions and 55 deletions
Download patch file Download diff file Expand all files Collapse all files

12
frontends/verilog/verilog_parser.y
View file

@ -1900,10 +1900,11 @@ struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_toke
;
member_type_token:
member_type
| hierarchical_type_id {
addWiretypeNode($1, astbuf1);
}
member_type range_or_multirange {
AstNode *range = checkRange(astbuf1, $2);
if (range)
astbuf1->children.push_back(range);
}
| {
delete astbuf1;
} struct_union {
@ -1919,7 +1920,8 @@ member_type_token:
;
member_type: type_atom type_signing
| type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
| type_vec type_signing
| hierarchical_type_id { addWiretypeNode($1, astbuf1); }
;
struct_var_list: struct_var