3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 14:23:41 +00:00

Renamed $_INV_ cell type to $_NOT_

This commit is contained in:
Clifford Wolf 2014-08-15 14:11:40 +02:00
parent bf486002d9
commit f092b50148
19 changed files with 47 additions and 47 deletions

View file

@ -623,7 +623,7 @@ struct FreduceWorker
batches.push_back(outputs);
bits_full_total += outputs.size();
}
if (inv_mode && it.second->type == "$_INV_")
if (inv_mode && it.second->type == "$_NOT_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
}
@ -718,7 +718,7 @@ struct FreduceWorker
{
inv_sig = module->addWire(NEW_ID);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
inv_cell->setPort("\\A", grp[0].bit);
inv_cell->setPort("\\Y", inv_sig);
}