3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 00:13:18 +00:00

Renamed $_INV_ cell type to $_NOT_

This commit is contained in:
Clifford Wolf 2014-08-15 14:11:40 +02:00
parent bf486002d9
commit f092b50148
19 changed files with 47 additions and 47 deletions

View file

@ -367,7 +367,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis
\bigskip
\begin{block}{The built-in logic gate types are:}
{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
\end{block}
\bigskip