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Renamed $_INV_ cell type to $_NOT_

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This commit is contained in:
Clifford Wolf 2014-08-15 14:11:40 +02:00
parent bf486002d9
commit f092b50148
19 changed files with 47 additions and 47 deletions
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4
manual/CHAPTER_StateOfTheArt/simlib_yosys.v
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@ -20,12 +20,12 @@
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
* logic cells (_INV_, _AND_, ...) that are generated by the default technology
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*
*/
module _INV_(A, Y);
module _NOT_(A, Y);
input A;
output Y;
assign Y = ~A;