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Progress in presentation

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This commit is contained in:
Clifford Wolf 2014-02-16 17:56:19 +01:00
parent 42ce3db983
commit f08c71b96c
5 changed files with 79 additions and 1 deletions
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15
manual/PRESENTATION_ExAdv/mymul_test.ys Normal file
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read_verilog mymul_test.v
hierarchy -check -top test
techmap -map sym_mul_map.v \
-map mymul_map.v;;
rename test test_mapped
read_verilog mymul_test.v
miter -equiv test test_mapped miter
flatten miter
sat -verify -prove trigger 0 miter
splitnets -ports test_mapped/A
show -prefix mymul -format pdf -notitle test_mapped