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Rename implicit_ports.sv test to implicit_ports.v

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-06-07 13:12:25 +02:00
parent 169de05f3b
commit f01a61f093
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16
tests/simple/implicit_ports.sv
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// Test implicit port connections
module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
assign cout = cin;
assign result = a + b;
endmodule
module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
wire cin = 1;
alu alu (
.a(a),
.b, // Implicit connection is equivalent to .b(b)
.cin(), // Explicitely unconnected
.cout(cout),
.result(alu_result)
);
endmodule