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Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

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c60k28 2018-03-31 22:48:47 -06:00
parent 93985d91b1
commit efed2420d6
11 changed files with 232 additions and 177 deletions
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27
techlibs/intel/synth_intel.cc
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@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass {
log("\n");
log("This command runs synthesis for Intel FPGAs.\n");
log("\n");
log(" -family < max10 | a10gx | cyclonev | cycloneiv | cycloneive>\n");
log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if not family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
@ -49,6 +49,11 @@ struct SynthIntelPass : public ScriptPass {
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
log(" -vpr <file>\n");
log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
log(" compatible with the Quartus flow. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
@ -68,7 +73,7 @@ struct SynthIntelPass : public ScriptPass {
log("\n");
}
string top_opt, family_opt, vout_file;
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram;
virtual void clear_flags() YS_OVERRIDE
@ -76,6 +81,7 @@ struct SynthIntelPass : public ScriptPass {
top_opt = "-auto-top";
family_opt = "max10";
vout_file = "";
blif_file = "";
retime = false;
flatten = true;
nobram = false;
@ -101,6 +107,10 @@ struct SynthIntelPass : public ScriptPass {
vout_file = args[++argidx];
continue;
}
if (args[argidx] == "-vpr" && argidx+1 < args.size()) {
blif_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
@ -198,7 +208,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_luts"))
{
if(family_opt=="a10gx" || family_opt=="cyclonev")
run("abc -luts 2:2,3,6:5,10" + string(retime ? " -dff" : ""));
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else
run("abc -lut 4" + string(retime ? " -dff" : ""));
run("clean");
@ -236,7 +246,16 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
}
if (check_label("vpr"))
{
if (!blif_file.empty() || help_mode)
{
run(stringf("opt_clean -purge"));
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
}
}
}
} SynthIntelPass;
PRIVATE_NAMESPACE_END