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Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
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c60k28
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11 changed files with 232 additions and 177 deletions
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@ -16,33 +16,45 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Intel FPGA technology mapping. User must first simulate the generated \
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// > netlist before going to test it on board.
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// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
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// 2) Cyclone V 7-input LUT function was wrong implemented. Removed abc option to map this function \
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// and added the explanation in this file instead. Such function needs to be implemented.
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// Normal mode DFF negedge clk, negedge reset
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module \$_DFF_N_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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parameter power_up=1'bx;
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dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Normal mode DFF
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module \$_DFF_P_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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parameter power_up=1'bx;
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dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active Low Reset DFF
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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parameter power_up=1'bx;
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dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active High Reset DFF
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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parameter power_up=1'bx;
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wire R_i = ~ R;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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parameter WYSIWYG="TRUE";
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parameter power_up=1'bx;
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wire E_i = ~ E;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
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dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
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endmodule
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// Input buffer map
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@ -61,6 +73,10 @@ module \$lut (A, Y);
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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wire VCC;
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wire GND;
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assign {VCC,GND} = {1'b1,1'b0};
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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@ -72,11 +88,11 @@ module \$lut (A, Y);
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(1'b1),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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.datac(VCC),
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.datad(VCC),
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 3) begin
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@ -86,10 +102,10 @@ module \$lut (A, Y);
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(1'b1),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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.datad(VCC),
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 4) begin
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@ -100,9 +116,9 @@ module \$lut (A, Y);
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(1'b1),
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.dataf(1'b1),
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.datag(1'b1));
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 5) begin
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@ -114,8 +130,8 @@ module \$lut (A, Y);
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(1'b1),
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.datag(1'b1));
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 6) begin
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@ -128,21 +144,16 @@ module \$lut (A, Y);
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datag(1'b1));
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.datag(VCC));
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end
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else
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/*else
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if(WIDTH == 7) begin
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cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datag(A[6]));
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end
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TODO: There's not a just 7-input function on Cyclone V, see the following note:
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**Extended LUT Mode**
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Use extended LUT mode to implement a specific set of 7-input functions. The set must
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be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
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[source](Device Interfaces and Integration Basics for Cyclone V Devices).
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end*/
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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