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https://github.com/YosysHQ/yosys
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Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device
This commit is contained in:
c60k28
parent
93985d91b1
commit
efed2420d6
11 changed files with 232 additions and 177 deletions
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@ -1,5 +1,5 @@
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OBJS += techlibs/achronix/synth_speedster.o
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OBJS += techlibs/achronix/synth_achronix.o
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$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v))
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$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v))
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@ -16,53 +16,25 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// Normal mode DFF negedge clk, negedge reset
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module \$_DFF_N_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Normal mode DFF
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module \$_DFF_P_ (input D, C, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active Low Reset DFF
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active High Reset DFF
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module \$_DFF_PP0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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wire R_i = ~ R;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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// Async Active Low Reset DFF
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module \$_DFF_PN0_ (input D, C, R, output Q);
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parameter WYSIWYG="TRUE";
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
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endmodule
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/* */
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module \$__DFFE_PP0 (input D, C, E, R, output Q);
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parameter WYSIWYG="TRUE";
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wire E_i = ~ E;
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dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
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endmodule
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Achronix eFPGA technology mapping. User must first simulate the generated \
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// > netlist before going to test it on board/custom chip.
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// > Input/Output buffers <
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// Input buffer map
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module \$__inpad (input I, output O);
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PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1));
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endmodule
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// > end buffers <
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// > Look-Up table <
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// > VT: I still think Achronix folks would have choosen a better \
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// > logic architecture.
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// LUT Map
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/* 0 -> datac
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1 -> cin */
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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@ -70,19 +42,31 @@ module \$lut (A, Y);
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output Y;
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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// VT: This is not consistent and ACE will complain: assign Y = ~A[0];
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
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end else
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if (WIDTH == 2) begin
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0));
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LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
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end else
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if(WIDTH == 3) begin
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LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0));
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LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
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end else
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if(WIDTH == 4) begin
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LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
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LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
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(.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
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end else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule //
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endmodule
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// > end LUT <
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// > Flops <
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// DFF flop
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module \$_DFF_P_ (input D, C, output Q);
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DFF _TECHMAP_REPLACE_
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(.q(Q), .d(D), .ck(C));
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endmodule
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@ -16,50 +16,31 @@
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Achronix eFPGA technology sim models. User must first simulate the generated \
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// > netlist before going to test it on board/custom chip.
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// > Changelog: 1) Removed unused VCC/GND modules
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// > 2) Altera comments here (?). Removed.
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// > 3) Reusing LUT sim model, removed wrong wires and parameters.
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera MAX10 devices Input Buffer Primitive */
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module PADIN (output padout, input padin);
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assign padout = padin;
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endmodule // fiftyfivenm_io_ibuf
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endmodule
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/* Altera MAX10 devices Output Buffer Primitive */
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module PADOUT (output padout, input padin, input oe);
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assign padout = padin;
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assign oe = oe;
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endmodule // fiftyfivenm_io_obuf
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endmodule
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/* Altera MAX10 4-input non-fracturable LUT Primitive */
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module LUT4 (output dout,
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input din0, din1, din2, din3);
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/* Internal parameters which define the behaviour
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of the LUT primitive.
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lut_mask define the lut function, can be expressed in 16-digit bin or hex.
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sum_lutc_input define the type of LUT (combinational | arithmetic).
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dont_touch for retiming || carry options.
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lpm_type for WYSIWYG */
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parameter lut_function = 16'hFFFF;
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//parameter dont_touch = "off";
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//parameter lpm_type = "fiftyfivenm_lcell_comb";
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//parameter sum_lutc_input = "datac";
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reg [1:0] lut_type;
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reg cout_rt;
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parameter [15:0] lut_function = 16'hFFFF;
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reg combout_rt;
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wire dataa_w;
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wire datab_w;
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wire datac_w;
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wire datad_w;
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wire cin_w;
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assign dataa_w = din0;
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assign datab_w = din1;
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@ -78,49 +59,21 @@ reg [1:0] s1;
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s1 = datab ? s2[3:2] : s2[1:0];
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lut_data = dataa ? s1[1] : s1[0];
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end
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endfunction
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initial begin
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/*if (sum_lutc_input == "datac")*/ lut_type = 0;
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/*else
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if (sum_lutc_input == "cin") lut_type = 1;
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else begin
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$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
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$finish();
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end*/
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end
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always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
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if (lut_type == 0) begin // logic function
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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datac_w, datad_w);
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end
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else if (lut_type == 1) begin // arithmetic function
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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cin_w, datad_w);
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end
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cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0);
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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datac_w, datad_w);
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end
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assign dout = combout_rt & 1'b1;
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//assign cout = cout_rt & 1'b1;
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endmodule // fiftyfivenm_lcell_comb
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/* Altera MAX10 D Flip-Flop Primitive */
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// TODO: Implement advanced simulation functions
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module dffeas ( output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload );
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q;
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always @(posedge clk)
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q <= d;
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endmodule
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module DFF (output q,
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input d, ck);
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reg q;
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always @(posedge ck)
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q <= d;
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endmodule
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@ -25,14 +25,14 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthIntelPass : public ScriptPass {
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SynthIntelPass() : ScriptPass("synth_speedster", "synthesis for Acrhonix Speedster22i FPGAs.") { }
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struct SynthAchronixPass : public ScriptPass {
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SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
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virtual void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_speedster [options]\n");
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log(" synth_achronix [options]\n");
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log("\n");
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log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n");
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log("\n");
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@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass {
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_SPEEDSTER pass.\n");
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log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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@ -146,9 +146,9 @@ struct SynthIntelPass : public ScriptPass {
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run("opt -undriven -fine");
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run("dffsr2dff");
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run("dff2dffe -direct-match $_DFF_*");
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run("opt -full");
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run("opt -fine");
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run("techmap -map +/techmap.v");
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run("opt -fast");
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run("opt -full");
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run("clean -purge");
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run("setundef -undriven -zero");
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if (retime || help_mode)
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@ -157,7 +157,7 @@ struct SynthIntelPass : public ScriptPass {
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if (check_label("map_luts"))
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{
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run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
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run("abc -lut 4" + string(retime ? " -dff" : ""));
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run("clean");
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}
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@ -165,7 +165,7 @@ struct SynthIntelPass : public ScriptPass {
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{
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run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I");
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run("techmap -map +/achronix/speedster22i/cells_map.v");
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run("dffinit -ff dffeas Q INIT");
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// VT: not done yet run("dffinit -highlow -ff DFF q power_up");
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run("clean -purge");
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}
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@ -179,10 +179,10 @@ struct SynthIntelPass : public ScriptPass {
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if (check_label("vout"))
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{
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s",
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run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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}
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}
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} SynthIntelPass;
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} SynthAchronixPass;
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PRIVATE_NAMESPACE_END
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