mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 03:10:26 +00:00
Code Activity

Add RAM32X1D support

Browse source
This commit is contained in:
Eddie Hung 2019-06-24 16:16:50 -07:00
parent fb8fab4a29
commit efd04880db
5 changed files with 73 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

17
techlibs/xilinx/cells_sim.v
View file

@ -278,6 +278,23 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [31:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,