From 3f71bc469de63ae6380e10e5f198a8ba1b7d7b3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:01:22 +0200 Subject: [PATCH 001/342] check: Rephrase comment --- passes/cmds/check.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 255c32fba..1848d34b6 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -284,10 +284,10 @@ struct CheckPass : public Pass { for (auto &loop : topo.loops) { string message = stringf("found logic loop in module %s:\n", log_id(module)); - // `loop` only contains wire bits, or an occassional special helper node for cells for - // which we have done the edges fallback. The cell and its ports that led to an edge is - // an information we need to recover now. For that we need to have the previous wire bit - // of the loop at hand. + // `loop` only contains wire bits, or an occasional special helper node for cells for + // which we have done the edges fallback. The cell and its ports that led to an edge are + // a piece of information we need to recover now. For that we need to have the previous + // wire bit of the loop at hand. SigBit prev; for (auto it = loop.rbegin(); it != loop.rend(); it++) if (it->second != -1) { // skip the fallback helper nodes From e70b1251adc4e932fd069ee66372b25ce5f7a2b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:01:37 +0200 Subject: [PATCH 002/342] check: Adjust prints --- passes/cmds/check.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 1848d34b6..c849b986c 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -316,10 +316,10 @@ struct CheckPass : public Pass { SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit]; if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT) - message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit, + message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit, log_id(to_port), to_bit); if (nhits == HITS_LIMIT) - message += " ...\n"; + message += " ...\n"; } }; From 0cefe8a1e87d3b33c856ad9103bcc6ea07debd33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 18 Jul 2024 13:04:27 +0200 Subject: [PATCH 003/342] check: Skip detailed edge modeling if costly --- passes/cmds/check.cc | 79 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 69 insertions(+), 10 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index c849b986c..83fe781a0 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -59,6 +59,12 @@ struct CheckPass : public Pass { log(" -assert\n"); log(" produce a runtime error if any problems are found in the current design\n"); log("\n"); + log(" -force-detailed-loop-check\n"); + log(" for the detection of combinatorial loops, use a detailed connectivity\n"); + log(" model for all internal cells for which it is available. This disables\n"); + log(" falling back to a simpler overapproximating model for those cells for\n"); + log(" which the detailed model is expected costly.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -68,6 +74,8 @@ struct CheckPass : public Pass { bool mapped = false; bool allow_tbuf = false; bool assert_mode = false; + bool force_detailed_loop_check = false; + bool suggest_detail = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -91,6 +99,10 @@ struct CheckPass : public Pass { assert_mode = true; continue; } + if (args[argidx] == "-force-detailed-loop-check") { + force_detailed_loop_check = true; + continue; + } break; } extra_args(args, argidx, design); @@ -154,9 +166,10 @@ struct CheckPass : public Pass { struct CircuitEdgesDatabase : AbstractCellEdgesDatabase { TopoSort> &topo; SigMap sigmap; + bool force_detail; - CircuitEdgesDatabase(TopoSort> &topo, SigMap &sigmap) - : topo(topo), sigmap(sigmap) {} + CircuitEdgesDatabase(TopoSort> &topo, SigMap &sigmap, bool force_detail) + : topo(topo), sigmap(sigmap), force_detail(force_detail) {} void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { @@ -171,10 +184,41 @@ struct CheckPass : public Pass { topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset)); } - bool add_edges_from_cell(Cell *cell) { - if (AbstractCellEdgesDatabase::add_edges_from_cell(cell)) + bool detail_costly(Cell *cell) { + // Only those cell types for which the edge data can expode quadratically + // in port widths are those for us to check. + if (!cell->type.in( + ID($add), ID($sub), + ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) + return false; + + int in_widths = 0, out_widths = 0; + + for (auto &conn : cell->connections()) { + if (cell->input(conn.first)) + in_widths += conn.second.size(); + if (cell->output(conn.first)) + out_widths += conn.second.size(); + } + + const int threshold = 1024; + + // if the multiplication may overflow we will catch it here + if (in_widths + out_widths >= threshold) return true; + if (in_widths * out_widths >= threshold) + return true; + + return false; + } + + bool add_edges_from_cell(Cell *cell) { + if (force_detail || !detail_costly(cell)) { + if (AbstractCellEdgesDatabase::add_edges_from_cell(cell)) + return true; + } + // We don't have accurate cell edges, do the fallback of all input-output pairs for (auto &conn : cell->connections()) { if (cell->input(conn.first)) @@ -189,12 +233,15 @@ struct CheckPass : public Pass { topo.edge(std::make_pair(cell->name, -1), std::make_pair(bit.wire->name, bit.offset)); } - return true; + + // Return false to signify the fallback + return false; } }; - CircuitEdgesDatabase edges_db(topo, sigmap); + CircuitEdgesDatabase edges_db(topo, sigmap, force_detailed_loop_check); + pool coarsened_cells; for (auto cell : module->cells()) { if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) { @@ -225,8 +272,10 @@ struct CheckPass : public Pass { } if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \ - || RTLIL::builtin_ff_cell_types().count(cell->type)) - edges_db.add_edges_from_cell(cell); + || RTLIL::builtin_ff_cell_types().count(cell->type)) { + if (!edges_db.add_edges_from_cell(cell)) + coarsened_cells.insert(cell); + } } pool init_bits; @@ -334,9 +383,16 @@ struct CheckPass : public Pass { std::string src_attr = driver->get_src_attribute(); driver_src = stringf(" source: %s", src_attr.c_str()); } + message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str()); - MatchingEdgePrinter printer(message, sigmap, prev, bit); - printer.add_edges_from_cell(driver); + + if (!coarsened_cells.count(driver)) { + MatchingEdgePrinter printer(message, sigmap, prev, bit); + printer.add_edges_from_cell(driver); + } else { + message += " (cell's internal connectivity overapproximated; loop may be a false positive)\n"; + suggest_detail = true; + } if (wire->name.isPublic()) { std::string wire_src; @@ -376,6 +432,9 @@ struct CheckPass : public Pass { log("Found and reported %d problems.\n", counter); + if (suggest_detail) + log("Consider re-running with '-force-detailed-loop-check' to rule out false positives.\n"); + if (assert_mode && counter > 0) log_error("Found %d problems in 'check -assert'.\n", counter); } From 3b48e9df61126f5f4b6514f9208aa7b2c170ba84 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 1 Mar 2024 10:43:34 +0100 Subject: [PATCH 004/342] Add initial NanoXplore pass --- techlibs/nanoxplore/Makefile.inc | 6 + techlibs/nanoxplore/cells_map.v | 34 ++++ techlibs/nanoxplore/cells_sim.v | 10 ++ techlibs/nanoxplore/synth_nanoxplore.cc | 228 ++++++++++++++++++++++++ 4 files changed, 278 insertions(+) create mode 100644 techlibs/nanoxplore/Makefile.inc create mode 100644 techlibs/nanoxplore/cells_map.v create mode 100644 techlibs/nanoxplore/cells_sim.v create mode 100644 techlibs/nanoxplore/synth_nanoxplore.cc diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc new file mode 100644 index 000000000..7e2923c40 --- /dev/null +++ b/techlibs/nanoxplore/Makefile.inc @@ -0,0 +1,6 @@ + +OBJS += techlibs/nanoxplore/synth_nanoxplore.o + +# Techmap +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v new file mode 100644 index 000000000..4a83fafc2 --- /dev/null +++ b/techlibs/nanoxplore/cells_map.v @@ -0,0 +1,34 @@ +`default_nettype none + +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0])); + end else + if (WIDTH == 2) begin + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1])); + end else + if (WIDTH == 3) begin + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2])); + end else + if (WIDTH == 4) begin + NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3])); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v new file mode 100644 index 000000000..d665e0f89 --- /dev/null +++ b/techlibs/nanoxplore/cells_sim.v @@ -0,0 +1,10 @@ +module NX_LUT(input I1, I2, I3, I4, output O); + +parameter lut_table = 16'h0000; + +wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0]; +wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0]; +wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0]; +assign O = I1 ? s3[1] : s3[0]; + +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc new file mode 100644 index 000000000..3d8a34c06 --- /dev/null +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -0,0 +1,228 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Hannah Ravensloft + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthNanoXplorePass : public ScriptPass +{ + SynthNanoXplorePass() : ScriptPass("synth_nanoxplore", "synthesis for NanoXplore FPGAs") { } + + void on_register() override + { + RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300"; + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_nanoxplore [options]\n"); + log("\n"); + log("This command runs synthesis for NanoXplore FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, json_file; + bool flatten, abc9; + + void clear_flags() override + { + top_opt = "-auto-top"; + json_file = ""; + flatten = true; + abc9 = false; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-flatten") { + flatten = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_NANOXPLORE pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + if (check_label("begin")) + { + run("read_verilog -lib -specify +/nanoxplore/cells_sim.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (check_label("coarse")) + { + run("proc"); + if (flatten || help_mode) + run("flatten", "(skip if -noflatten)"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + run("alumacc"); + run("opt"); + run("memory -nomap"); + run("opt_clean"); + } + + if (check_label("map_ram")) + { + } + + if (check_label("map_ffram")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine -mux_undef"); + } + + if (check_label("map_gates")) + { + run("techmap"); + run("opt -fast"); + } + + if (check_label("map_ffs")) + { + run("techmap"); + run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0"); + run("techmap -map +/nanoxplore/cells_map.v"); + run("opt_expr -undriven -mux_undef"); + run("clean -purge"); + } + + if (check_label("map_luts")) + { + if (abc9) { + std::string abc9_opts = " -maxlut 4"; + std::string k = "synth_nanoxplore.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + run("abc9" + abc9_opts); + } else { + std::string abc_args = " -dress"; + abc_args += " -lut 4"; + run("abc" + abc_args); + } + run("techmap -map +/nanoxplore/cells_map.v t:$lut"); + run("opt -fast"); + run("clean"); + } + + if (check_label("check")) + { + run("autoname"); + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthNanoXplorePass; + +PRIVATE_NAMESPACE_END From 94b6f19cf0a1cc5077c84d31528a34b26a0d1bae Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 10:44:42 +0100 Subject: [PATCH 005/342] Make lut init match vendor tools --- techlibs/nanoxplore/cells_map.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 4a83fafc2..a0d0e6957 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -10,19 +10,20 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin - localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + localparam [15:0] INIT = {{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, + {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}}; NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0])); + .I1(A[0]), .I2(1'b0), .I3(1'b0), .I4(1'b0)); end else if (WIDTH == 2) begin - localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + localparam [15:0] INIT = {{4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}}; NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1])); + .I1(A[0]), .I2(A[1]), .I3(1'b0), .I4(1'b0), ); end else if (WIDTH == 3) begin - localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + localparam [15:0] INIT = {{8{LUT[7:0]}}, {8{LUT[7:0]}}}; NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), - .I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2])); + .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(1'b0)); end else if (WIDTH == 4) begin NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y), From 93543bd87476351af0aee3f45eb6717e79610d64 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 10:45:15 +0100 Subject: [PATCH 006/342] add lut tests --- tests/arch/nanoxplore/.gitignore | 2 ++ tests/arch/nanoxplore/logic.ys | 9 +++++++++ tests/arch/nanoxplore/run-test.sh | 4 ++++ 3 files changed, 15 insertions(+) create mode 100644 tests/arch/nanoxplore/.gitignore create mode 100644 tests/arch/nanoxplore/logic.ys create mode 100755 tests/arch/nanoxplore/run-test.sh diff --git a/tests/arch/nanoxplore/.gitignore b/tests/arch/nanoxplore/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/arch/nanoxplore/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/arch/nanoxplore/logic.ys b/tests/arch/nanoxplore/logic.ys new file mode 100644 index 000000000..2edcbfebd --- /dev/null +++ b/tests/arch/nanoxplore/logic.ys @@ -0,0 +1,9 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:NX_LUT +select -assert-none t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/run-test.sh b/tests/arch/nanoxplore/run-test.sh new file mode 100755 index 000000000..4be4b70ae --- /dev/null +++ b/tests/arch/nanoxplore/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" From b4a17cccc30c9bf2ea2a4c212882eaca4be73ce6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 10:49:48 +0100 Subject: [PATCH 007/342] add few more tests --- tests/arch/nanoxplore/mux.ys | 41 +++++++++++++++++++++++++++++++++ tests/arch/nanoxplore/tribuf.ys | 12 ++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/arch/nanoxplore/mux.ys create mode 100644 tests/arch/nanoxplore/tribuf.ys diff --git a/tests/arch/nanoxplore/mux.ys b/tests/arch/nanoxplore/mux.ys new file mode 100644 index 000000000..8c92ab156 --- /dev/null +++ b/tests/arch/nanoxplore/mux.ys @@ -0,0 +1,41 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_LUT + +select -assert-none t:NX_LUT %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +#select -assert-count 2 t:NX_LUT + +select -assert-none t:NX_LUT %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +#select -assert-count 5 t:NX_LUT + +select -assert-none t:NX_LUT %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 13 t:NX_LUT + +select -assert-none t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys new file mode 100644 index 000000000..c72e2e1ad --- /dev/null +++ b/tests/arch/nanoxplore/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From b4e9bb0d85f38ce81fd3eb7733e8ea35a269dc82 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 1 Mar 2024 10:55:54 +0100 Subject: [PATCH 008/342] Add FFs and related tests --- techlibs/nanoxplore/cells_map.v | 33 +++++++++++++++++++++++ techlibs/nanoxplore/cells_sim.v | 25 +++++++++++++++++ tests/arch/nanoxplore/adffs.ys | 46 ++++++++++++++++++++++++++++++++ tests/arch/nanoxplore/dffs.ys | 22 +++++++++++++++ tests/arch/nanoxplore/fsm.ys | 16 +++++++++++ tests/arch/nanoxplore/latches.ys | 35 ++++++++++++++++++++++++ tests/arch/nanoxplore/shifter.ys | 10 +++++++ 7 files changed, 187 insertions(+) create mode 100644 tests/arch/nanoxplore/adffs.ys create mode 100644 tests/arch/nanoxplore/dffs.ys create mode 100644 tests/arch/nanoxplore/fsm.ys create mode 100644 tests/arch/nanoxplore/latches.ys create mode 100644 tests/arch/nanoxplore/shifter.ys diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index a0d0e6957..efa2a2af5 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -33,3 +33,36 @@ module \$lut (A, Y); end endgenerate endmodule + +(* techmap_celltype = "$_DFF_[NP]P[01]_" *) +module dff(input D, C, R, output Q); + parameter _TECHMAP_CELLTYPE = "$_DFF_PP1_"; + localparam dff_edge = _TECHMAP_CELLTYPE[6*8 +: 8] == "N"; + localparam dff_type = _TECHMAP_CELLTYPE[8*8 +: 8] == "1"; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); +endmodule + +(* techmap_celltype = "$_ALDFF_[NP]P_" *) +module aldff(input D, C, L, AD, output Q); + parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_"; + localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N"; + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q)); +endmodule + +module \$_SDFF_PP0_ (input D, C, R, output Q); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); +endmodule + +module \$_SDFF_PP1_ (input D, C, R, output Q); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); +endmodule + +module \$_SDFF_NP0_ (input D, C, R, output Q); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); +endmodule + +module \$_SDFF_NP1_ (input D, C, R, output Q); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index d665e0f89..0a69a8a6a 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -8,3 +8,28 @@ wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0]; assign O = I1 ? s3[1] : s3[0]; endmodule + +module NX_DFF(input I, CK, L, R, output reg O); + +parameter dff_ctxt = 1'bx; +parameter dff_edge = 1'b0; +parameter dff_init = 1'b0; +parameter dff_load = 1'b0; +parameter dff_sync = 1'b0; +parameter dff_type = 1'b0; + +initial begin + O = dff_ctxt; +end + +wire clock = CK ^ dff_edge; +wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type; +wire async_reset = !dff_sync && dff_init && R; +wire sync_reset = dff_sync && dff_init && R; + +always @(posedge clock, posedge async_reset) + if (async_reset) O <= load; + else if (sync_reset) O <= load; + else O <= I; + +endmodule diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys new file mode 100644 index 000000000..6a4f63ad7 --- /dev/null +++ b/tests/arch/nanoxplore/adffs.ys @@ -0,0 +1,46 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_DFF %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF +select -assert-count 1 t:NX_LUT + +select -assert-none t:NX_DFF t:NX_LUT %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_DFF %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF +select -assert-count 1 t:NX_LUT + +select -assert-none t:NX_DFF t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys new file mode 100644 index 000000000..ba7dff41c --- /dev/null +++ b/tests/arch/nanoxplore/dffs.ys @@ -0,0 +1,22 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF +select -assert-count 1 t:NX_LUT + +select -assert-none t:NX_DFF t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys new file mode 100644 index 000000000..ee00be4e1 --- /dev/null +++ b/tests/arch/nanoxplore/fsm.ys @@ -0,0 +1,16 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore +async2sync +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 6 t:NX_DFF +select -assert-count 13 t:NX_LUT +select -assert-none t:NX_DFF t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys new file mode 100644 index 000000000..32609dbce --- /dev/null +++ b/tests/arch/nanoxplore/latches.ys @@ -0,0 +1,35 @@ +read_verilog ../common/latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_nanoxplore +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_DFF %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_nanoxplore +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:NX_LUT +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_LUT t:NX_DFF %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_nanoxplore +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:NX_LUT +select -assert-count 1 t:NX_DFF + +select -assert-none t:NX_LUT t:NX_DFF %% t:* %D diff --git a/tests/arch/nanoxplore/shifter.ys b/tests/arch/nanoxplore/shifter.ys new file mode 100644 index 000000000..a3502df2a --- /dev/null +++ b/tests/arch/nanoxplore/shifter.ys @@ -0,0 +1,10 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:NX_DFF +select -assert-none t:NX_DFF %% t:* %D From b3f59c98209e43029afea0a44ce3bd5b94cea38d Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 1 Mar 2024 11:10:52 +0100 Subject: [PATCH 009/342] Add NX_CY --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/arith_map.v | 71 ++++++++++++++++++++++++++++++++ techlibs/nanoxplore/cells_sim.v | 6 +++ tests/arch/nanoxplore/add_sub.ys | 10 +++++ 4 files changed, 88 insertions(+) create mode 100644 techlibs/nanoxplore/arith_map.v create mode 100644 tests/arch/nanoxplore/add_sub.ys diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 7e2923c40..bd8bd228e 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -2,5 +2,6 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o # Techmap +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v new file mode 100644 index 000000000..69e83b68c --- /dev/null +++ b/techlibs/nanoxplore/arith_map.v @@ -0,0 +1,71 @@ +`default_nettype none + +(* techmap_celltype = "$alu" *) +module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up4; + input integer N; + begin + round_up4 = ((N + 3) / 4) * 4; + end + endfunction + + localparam Y_WIDTH4 = round_up4(Y_WIDTH); + + (* force_downto *) + wire [Y_WIDTH4-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH4-1:0] BX = B_buf; + (* force_downto *) + wire [Y_WIDTH4:0] C = {CO, CI}; + (* force_downto *) + wire [Y_WIDTH4-1:0] FCO, Y1; + + genvar i; + generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice + NX_CY cy_i ( + .CI(C[i]), + .A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]), + .B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]), + .S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]), + .CO(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i+1 < Y_WIDTH) + assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1])); + if (i+2 < Y_WIDTH) + assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2])); + if (i+3 < Y_WIDTH) + assign CO[i+3] = FCO[i]; + + end endgenerate + + assign X = AA ^ BB; + assign Y = Y1[Y_WIDTH-1:0]; +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 0a69a8a6a..1f04b216e 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -33,3 +33,9 @@ always @(posedge clock, posedge async_reset) else O <= I; endmodule + +module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); +parameter add_carry = 0; + +assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI; +endmodule diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys new file mode 100644 index 000000000..0cfc201f5 --- /dev/null +++ b/tests/arch/nanoxplore/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:NX_CY +select -assert-count 4 t:NX_LUT +select -assert-none t:NX_CY t:NX_LUT %% t:* %D + From 8374f0336de9f031ea8dac5c13df4eb56c6fc440 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 11:11:23 +0100 Subject: [PATCH 010/342] add family and ability to disable carry chains --- techlibs/nanoxplore/synth_nanoxplore.cc | 38 ++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 3d8a34c06..eda65b66b 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Hannah Ravensloft + * Copyright (C) 2024 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -45,6 +46,15 @@ struct SynthNanoXplorePass : public ScriptPass log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); + log(" -family \n"); + log(" run synthesis for the specified NanoXplore architecture\n"); + log(" generate the synthesis netlist for the specified family.\n"); + log(" supported values:\n"); + log(" - medium: NG-Medium\n"); + log(" - large: NG-Large\n"); + log(" - ultra: NG-Ultra\n"); + log(" - u300: NG-Ultra300\n"); + log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -60,21 +70,26 @@ struct SynthNanoXplorePass : public ScriptPass log(" -abc9\n"); log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); + log(" -nocy\n"); + log(" do not map adders to CY cells\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, json_file; - bool flatten, abc9; + string top_opt, json_file, family; + bool flatten, abc9, nocy; void clear_flags() override { top_opt = "-auto-top"; json_file = ""; + family = ""; flatten = true; abc9 = false; + nocy = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -89,6 +104,10 @@ struct SynthNanoXplorePass : public ScriptPass top_opt = "-top " + args[++argidx]; continue; } + if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) { + family = args[++argidx]; + continue; + } if (args[argidx] == "-json" && argidx+1 < args.size()) { json_file = args[++argidx]; continue; @@ -113,10 +132,19 @@ struct SynthNanoXplorePass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-nocy") { + nocy = true; + continue; + } break; } extra_args(args, argidx, design); + if (family.empty()) { + log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); + family = "ultra"; + } + if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -175,13 +203,15 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_gates")) { - run("techmap"); + if (nocy) + run("techmap"); + else + run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v"); run("opt -fast"); } if (check_label("map_ffs")) { - run("techmap"); run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0"); run("techmap -map +/nanoxplore/cells_map.v"); run("opt_expr -undriven -mux_undef"); From 5d898ab22392335d019c85fdd1b71e3986091a39 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 12:07:20 +0100 Subject: [PATCH 011/342] Add blackboxes --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/cells_bb.v | 33105 ++++++++++++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 2 +- 3 files changed, 33107 insertions(+), 1 deletion(-) create mode 100644 techlibs/nanoxplore/cells_bb.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index bd8bd228e..0f7bcdbed 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -3,5 +3,6 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v new file mode 100644 index 000000000..7ebad4ae8 --- /dev/null +++ b/techlibs/nanoxplore/cells_bb.v @@ -0,0 +1,33105 @@ +(* blackbox *) +module ACC84_2DSP(clk, rst, X, Z); + input [83:0] X; + output [84:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +(* blackbox *) +module ACC92_2DSP(clk, rst, X, Z); + input [55:0] X; + output [91:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +(* blackbox *) +module ACC98_2DSP(clk, rst, X, Z); + input [55:0] X; + output [97:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +(* blackbox *) +module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z); + input [41:0] X; + input [41:0] Y; + output [84:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module ADD84_2DSP(clk, rst, X, Y, Z); + input [83:0] X; + input [83:0] Y; + output [84:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module NX_BD(I, O); + input I; + output O; + parameter mode = "global_lowskew"; +endmodule + +(* blackbox *) +module NX_BFF(I, O); + input I; + output O; +endmodule + +(* blackbox *) +module NX_BFR(I, O); + input I; + output O; + parameter data_inv = 1'b0; + parameter iobname = ""; + parameter location = ""; + parameter mode = 0; + parameter path = 0; + parameter ring = 0; +endmodule + +(* blackbox *) +module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1 +, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4 +, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6); + input AI1; + input AI2; + input AI3; + input AI4; + input AI5; + input AI6; + output AO1; + output AO2; + output AO3; + output AO4; + output AO5; + output AO6; + input BI1; + input BI2; + input BI3; + input BI4; + input BI5; + input BI6; + output BO1; + output BO2; + output BO3; + output BO4; + output BO5; + output BO6; + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CI6; + input CK1; + input CK2; + output CO1; + output CO2; + output CO3; + output CO4; + output CO5; + output CO6; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter mode = 0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; + parameter use_cdest_arst = 2'b00; + parameter use_csrc_arst = 2'b00; + parameter use_ddest_arst = 2'b00; + parameter use_dsrc_arst = 2'b00; +endmodule + +(* blackbox *) +module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_bdest_arst = 2'b00; +endmodule + +(* blackbox *) +module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; +endmodule + +(* blackbox *) +module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; +endmodule + +(* blackbox *) +module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; +endmodule + +(* blackbox *) +module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO +, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4 +, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3 +, DO4, DO5, DO6); + input ADRSTI; + output ADRSTO; + input AI1; + input AI2; + input AI3; + input AI4; + input AI5; + input AI6; + output AO1; + output AO2; + output AO3; + output AO4; + output AO5; + output AO6; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input BI1; + input BI2; + input BI3; + input BI4; + input BI5; + input BI6; + output BO1; + output BO2; + output BO3; + output BO4; + output BO5; + output BO6; + input BSRSTI; + output BSRSTO; + input CDRSTI; + output CDRSTO; + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CI6; + input CK1; + input CK2; + output CO1; + output CO2; + output CO3; + output CO4; + output CO5; + output CO6; + input CSRSTI; + output CSRSTO; + input DDRSTI; + output DDRSTO; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + input DSRSTI; + output DSRSTO; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter mode = 0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + parameter use_cdest_arst = 1'b0; + parameter use_csrc_arst = 1'b0; + parameter use_ddest_arst = 1'b0; + parameter use_dsrc_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_bdest_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; +endmodule + +(* blackbox *) +module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; +endmodule + +(* blackbox *) +module NX_CKS(CKI, CMD, CKO); + input CKI; + output CKO; + input CMD; + parameter ck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_CKS_U(CKI, CMD, CKO); + input CKI; + output CKO; + input CMD; +endmodule + +(* blackbox *) +module NX_CMUX_U(CKI0, CKI1, SEL, CKO); + input CKI0; + input CKI1; + output CKO; + input SEL; +endmodule + +(* blackbox *) +module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 +, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 +, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45 +, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2 +, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7 +, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4 +, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK); + input ALIGN_E_I; + output ALIGN_O; + input ALIGN_S_I; + input BUF_FE_I; + input BUF_R_I; + output BUSY_O; + input CDR_R_I; + output CH_A_O1; + output CH_A_O2; + output CH_A_O3; + output CH_A_O4; + output CH_A_O5; + output CH_A_O6; + output CH_A_O7; + output CH_A_O8; + output CH_COM_O1; + output CH_COM_O2; + output CH_COM_O3; + output CH_COM_O4; + output CH_COM_O5; + output CH_COM_O6; + output CH_COM_O7; + output CH_COM_O8; + output CH_F_O1; + output CH_F_O2; + output CH_F_O3; + output CH_F_O4; + output CH_F_O5; + output CH_F_O6; + output CH_F_O7; + output CH_F_O8; + output CH_K_O1; + output CH_K_O2; + output CH_K_O3; + output CH_K_O4; + output CH_K_O5; + output CH_K_O6; + output CH_K_O7; + output CH_K_O8; + input CKG_RN_I; + output DATA_O1; + output DATA_O10; + output DATA_O11; + output DATA_O12; + output DATA_O13; + output DATA_O14; + output DATA_O15; + output DATA_O16; + output DATA_O17; + output DATA_O18; + output DATA_O19; + output DATA_O2; + output DATA_O20; + output DATA_O21; + output DATA_O22; + output DATA_O23; + output DATA_O24; + output DATA_O25; + output DATA_O26; + output DATA_O27; + output DATA_O28; + output DATA_O29; + output DATA_O3; + output DATA_O30; + output DATA_O31; + output DATA_O32; + output DATA_O33; + output DATA_O34; + output DATA_O35; + output DATA_O36; + output DATA_O37; + output DATA_O38; + output DATA_O39; + output DATA_O4; + output DATA_O40; + output DATA_O41; + output DATA_O42; + output DATA_O43; + output DATA_O44; + output DATA_O45; + output DATA_O46; + output DATA_O47; + output DATA_O48; + output DATA_O49; + output DATA_O5; + output DATA_O50; + output DATA_O51; + output DATA_O52; + output DATA_O53; + output DATA_O54; + output DATA_O55; + output DATA_O56; + output DATA_O57; + output DATA_O58; + output DATA_O59; + output DATA_O6; + output DATA_O60; + output DATA_O61; + output DATA_O62; + output DATA_O63; + output DATA_O64; + output DATA_O7; + output DATA_O8; + output DATA_O9; + input DEC_E_I; + input DSCR_E_I; + output D_ERR_O1; + output D_ERR_O2; + output D_ERR_O3; + output D_ERR_O4; + output D_ERR_O5; + output D_ERR_O6; + output D_ERR_O7; + output D_ERR_O8; + inout [9:0] LINK; + output LOCK_O; + output LOS_O; + output NIT_O1; + output NIT_O2; + output NIT_O3; + output NIT_O4; + output NIT_O5; + output NIT_O6; + output NIT_O7; + output NIT_O8; + input OVS_BS_I1; + input OVS_BS_I2; + input PLL_RN_I; + input REP_E_I; + input RST_N_I; + input RX_I; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + parameter location = ""; + parameter pcs_8b_dscr_sel = 1'b0; + parameter pcs_align_bypass = 1'b0; + parameter pcs_buffers_bypass = 1'b0; + parameter pcs_buffers_use_cdc = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_comma_mask = 10'b0000000000; + parameter pcs_debug_en = 1'b0; + parameter pcs_dec_bypass = 1'b0; + parameter pcs_dscr_bypass = 1'b0; + parameter pcs_el_buff_diff_bef_comp = 3'b000; + parameter pcs_el_buff_max_comp = 3'b000; + parameter pcs_el_buff_only_one_skp = 1'b0; + parameter pcs_el_buff_skp_char_0 = 9'b000000000; + parameter pcs_el_buff_skp_char_1 = 9'b000000000; + parameter pcs_el_buff_skp_char_2 = 9'b000000000; + parameter pcs_el_buff_skp_char_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_0 = 9'b000000000; + parameter pcs_el_buff_skp_header_1 = 9'b000000000; + parameter pcs_el_buff_skp_header_2 = 9'b000000000; + parameter pcs_el_buff_skp_header_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_size = 2'b00; + parameter pcs_el_buff_skp_seq_size = 2'b00; + parameter pcs_el_buff_underflow_handle = 1'b0; + parameter pcs_fsm_sel = 2'b00; + parameter pcs_fsm_watchdog_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_m_comma_en = 1'b0; + parameter pcs_m_comma_val = 10'b0000000000; + parameter pcs_nb_comma_bef_realign = 2'b00; + parameter pcs_p_comma_en = 1'b0; + parameter pcs_p_comma_val = 10'b0000000000; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_sync_supported = 1'b0; + parameter pma_cdr_cp = 4'b0000; + parameter pma_clk_pos = 1'b0; + parameter pma_ctrl_term = 6'b000000; + parameter pma_loopback = 1'b0; + parameter pma_pll_cpump_n = 3'b000; + parameter pma_pll_divf = 2'b00; + parameter pma_pll_divf_en_n = 1'b0; + parameter pma_pll_divm = 2'b00; + parameter pma_pll_divm_en_n = 1'b0; + parameter pma_pll_divn = 1'b0; + parameter pma_pll_divn_en_n = 1'b0; + parameter test = 2'b00; +endmodule + +(* blackbox *) +module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6 +, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27 +, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48 +, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5 +, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2 +, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7 +, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK); + input ALIGN_E_I; + output ALIGN_O; + input ALIGN_S_I; + input BUF_R_I; + output BUSY_O; + output CH_A_O1; + output CH_A_O2; + output CH_A_O3; + output CH_A_O4; + output CH_A_O5; + output CH_A_O6; + output CH_A_O7; + output CH_A_O8; + output CH_COM_O1; + output CH_COM_O2; + output CH_COM_O3; + output CH_COM_O4; + output CH_COM_O5; + output CH_COM_O6; + output CH_COM_O7; + output CH_COM_O8; + output CH_F_O1; + output CH_F_O2; + output CH_F_O3; + output CH_F_O4; + output CH_F_O5; + output CH_F_O6; + output CH_F_O7; + output CH_F_O8; + output CH_K_O1; + output CH_K_O2; + output CH_K_O3; + output CH_K_O4; + output CH_K_O5; + output CH_K_O6; + output CH_K_O7; + output CH_K_O8; + output DATA_O1; + output DATA_O10; + output DATA_O11; + output DATA_O12; + output DATA_O13; + output DATA_O14; + output DATA_O15; + output DATA_O16; + output DATA_O17; + output DATA_O18; + output DATA_O19; + output DATA_O2; + output DATA_O20; + output DATA_O21; + output DATA_O22; + output DATA_O23; + output DATA_O24; + output DATA_O25; + output DATA_O26; + output DATA_O27; + output DATA_O28; + output DATA_O29; + output DATA_O3; + output DATA_O30; + output DATA_O31; + output DATA_O32; + output DATA_O33; + output DATA_O34; + output DATA_O35; + output DATA_O36; + output DATA_O37; + output DATA_O38; + output DATA_O39; + output DATA_O4; + output DATA_O40; + output DATA_O41; + output DATA_O42; + output DATA_O43; + output DATA_O44; + output DATA_O45; + output DATA_O46; + output DATA_O47; + output DATA_O48; + output DATA_O49; + output DATA_O5; + output DATA_O50; + output DATA_O51; + output DATA_O52; + output DATA_O53; + output DATA_O54; + output DATA_O55; + output DATA_O56; + output DATA_O57; + output DATA_O58; + output DATA_O59; + output DATA_O6; + output DATA_O60; + output DATA_O61; + output DATA_O62; + output DATA_O63; + output DATA_O64; + output DATA_O7; + output DATA_O8; + output DATA_O9; + input DBG_S_I1; + input DBG_S_I2; + input DBG_S_I3; + input DEC_E_I; + input DSCR_E_I; + output D_ERR_O1; + output D_ERR_O2; + output D_ERR_O3; + output D_ERR_O4; + output D_ERR_O5; + output D_ERR_O6; + output D_ERR_O7; + output D_ERR_O8; + inout [9:0] LINK; + output LL_FLOCK_O; + output LL_SLOCK_O; + output LOS_O; + input MEYE_RST_I; + output NIT_O1; + output NIT_O2; + output NIT_O3; + output NIT_O4; + output NIT_O5; + output NIT_O6; + output NIT_O7; + output NIT_O8; + input OVS_BS_I1; + input OVS_BS_I2; + output PLL_LOCKT_O; + output PLL_LOCK_O; + input PMA_RSTN_I; + input PWDN_N_I; + input REP_E_I; + input RST_N_I; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + output VREALIGN_O; + parameter gearbox_en = 1'b0; + parameter gearbox_mode = 1'b0; + parameter location = ""; + parameter pcs_8b_dscr_sel = 1'b0; + parameter pcs_align_bypass = 1'b0; + parameter pcs_buffers_bypass = 1'b0; + parameter pcs_buffers_use_cdc = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_comma_mask = 10'b0000000000; + parameter pcs_debug_en = 1'b0; + parameter pcs_dec_bypass = 1'b0; + parameter pcs_dscr_bypass = 1'b0; + parameter pcs_el_buff_diff_bef_comp = 4'b0000; + parameter pcs_el_buff_max_comp = 4'b0000; + parameter pcs_el_buff_only_one_skp = 1'b0; + parameter pcs_el_buff_skp_char_0 = 9'b000000000; + parameter pcs_el_buff_skp_char_1 = 9'b000000000; + parameter pcs_el_buff_skp_char_2 = 9'b000000000; + parameter pcs_el_buff_skp_char_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_0 = 9'b000000000; + parameter pcs_el_buff_skp_header_1 = 9'b000000000; + parameter pcs_el_buff_skp_header_2 = 9'b000000000; + parameter pcs_el_buff_skp_header_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_size = 2'b00; + parameter pcs_el_buff_skp_seq_size = 2'b00; + parameter pcs_fsm_sel = 2'b00; + parameter pcs_fsm_watchdog_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_m_comma_en = 1'b0; + parameter pcs_m_comma_val = 10'b0000000000; + parameter pcs_nb_comma_bef_realign = 2'b00; + parameter pcs_p_comma_en = 1'b0; + parameter pcs_p_comma_val = 10'b0000000000; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_sync_supported = 1'b0; + parameter pma_cdr_cp = 4'b0000; + parameter pma_clk_pos = 1'b0; + parameter pma_coarse_ppm = 3'b000; + parameter pma_ctrl_term = 6'b000000; + parameter pma_dco_divl = 2'b00; + parameter pma_dco_divm = 1'b0; + parameter pma_dco_divn = 2'b00; + parameter pma_dco_reg_res = 2'b00; + parameter pma_dco_vref_sel = 1'b0; + parameter pma_fine_ppm = 3'b000; + parameter pma_loopback = 1'b0; + parameter pma_m_eye_ppm = 3'b000; + parameter pma_peak_detect_cmd = 2'b00; + parameter pma_peak_detect_on = 1'b0; + parameter pma_pll_cpump_n = 3'b000; + parameter pma_pll_divf = 2'b00; + parameter pma_pll_divf_en_n = 1'b0; + parameter pma_pll_divm = 2'b00; + parameter pma_pll_divm_en_n = 1'b0; + parameter pma_pll_divn = 1'b0; + parameter pma_pll_divn_en_n = 1'b0; +endmodule + +(* blackbox *) +module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 +, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I +, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17 +, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38 +, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59 +, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK); + output BUSY_O; + input CH_K_I1; + input CH_K_I2; + input CH_K_I3; + input CH_K_I4; + input CH_K_I5; + input CH_K_I6; + input CH_K_I7; + input CH_K_I8; + input CLK_E_I; + input DATA_I1; + input DATA_I10; + input DATA_I11; + input DATA_I12; + input DATA_I13; + input DATA_I14; + input DATA_I15; + input DATA_I16; + input DATA_I17; + input DATA_I18; + input DATA_I19; + input DATA_I2; + input DATA_I20; + input DATA_I21; + input DATA_I22; + input DATA_I23; + input DATA_I24; + input DATA_I25; + input DATA_I26; + input DATA_I27; + input DATA_I28; + input DATA_I29; + input DATA_I3; + input DATA_I30; + input DATA_I31; + input DATA_I32; + input DATA_I33; + input DATA_I34; + input DATA_I35; + input DATA_I36; + input DATA_I37; + input DATA_I38; + input DATA_I39; + input DATA_I4; + input DATA_I40; + input DATA_I41; + input DATA_I42; + input DATA_I43; + input DATA_I44; + input DATA_I45; + input DATA_I46; + input DATA_I47; + input DATA_I48; + input DATA_I49; + input DATA_I5; + input DATA_I50; + input DATA_I51; + input DATA_I52; + input DATA_I53; + input DATA_I54; + input DATA_I55; + input DATA_I56; + input DATA_I57; + input DATA_I58; + input DATA_I59; + input DATA_I6; + input DATA_I60; + input DATA_I61; + input DATA_I62; + input DATA_I63; + input DATA_I64; + input DATA_I7; + input DATA_I8; + input DATA_I9; + input ENC_E_I1; + input ENC_E_I2; + input ENC_E_I3; + input ENC_E_I4; + input ENC_E_I5; + input ENC_E_I6; + input ENC_E_I7; + input ENC_E_I8; + input EOF_I1; + input EOF_I2; + input EOF_I3; + input EOF_I4; + input EOF_I5; + input EOF_I6; + input EOF_I7; + input EOF_I8; + input EOMF_I1; + input EOMF_I2; + input EOMF_I3; + input EOMF_I4; + input EOMF_I5; + input EOMF_I6; + input EOMF_I7; + input EOMF_I8; + inout [19:0] LINK; + input REP_E_I; + input RST_N_I; + input SCR_E_I1; + input SCR_E_I2; + input SCR_E_I3; + input SCR_E_I4; + input SCR_E_I5; + input SCR_E_I6; + input SCR_E_I7; + input SCR_E_I8; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TX_O; + parameter location = ""; + parameter pcs_8b_scr_sel = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_enc_bypass = 1'b0; + parameter pcs_esistream_fsm_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_scr_bypass = 1'b0; + parameter pcs_scr_init = 17'b00000000000000000; + parameter pcs_sync_supported = 1'b0; + parameter pma_clk_pos = 1'b0; + parameter pma_loopback = 1'b0; + parameter test = 2'b00; +endmodule + +(* blackbox *) +module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 +, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I +, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21 +, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42 +, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63 +, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK); + output BUSY_O; + input CH_K_I1; + input CH_K_I2; + input CH_K_I3; + input CH_K_I4; + input CH_K_I5; + input CH_K_I6; + input CH_K_I7; + input CH_K_I8; + input CLK_E_I; + output CLK_O; + input DATA_I1; + input DATA_I10; + input DATA_I11; + input DATA_I12; + input DATA_I13; + input DATA_I14; + input DATA_I15; + input DATA_I16; + input DATA_I17; + input DATA_I18; + input DATA_I19; + input DATA_I2; + input DATA_I20; + input DATA_I21; + input DATA_I22; + input DATA_I23; + input DATA_I24; + input DATA_I25; + input DATA_I26; + input DATA_I27; + input DATA_I28; + input DATA_I29; + input DATA_I3; + input DATA_I30; + input DATA_I31; + input DATA_I32; + input DATA_I33; + input DATA_I34; + input DATA_I35; + input DATA_I36; + input DATA_I37; + input DATA_I38; + input DATA_I39; + input DATA_I4; + input DATA_I40; + input DATA_I41; + input DATA_I42; + input DATA_I43; + input DATA_I44; + input DATA_I45; + input DATA_I46; + input DATA_I47; + input DATA_I48; + input DATA_I49; + input DATA_I5; + input DATA_I50; + input DATA_I51; + input DATA_I52; + input DATA_I53; + input DATA_I54; + input DATA_I55; + input DATA_I56; + input DATA_I57; + input DATA_I58; + input DATA_I59; + input DATA_I6; + input DATA_I60; + input DATA_I61; + input DATA_I62; + input DATA_I63; + input DATA_I64; + input DATA_I7; + input DATA_I8; + input DATA_I9; + input ENC_E_I1; + input ENC_E_I2; + input ENC_E_I3; + input ENC_E_I4; + input ENC_E_I5; + input ENC_E_I6; + input ENC_E_I7; + input ENC_E_I8; + input EOF_I1; + input EOF_I2; + input EOF_I3; + input EOF_I4; + input EOF_I5; + input EOF_I6; + input EOF_I7; + input EOF_I8; + input EOMF_I1; + input EOMF_I2; + input EOMF_I3; + input EOMF_I4; + input EOMF_I5; + input EOMF_I6; + input EOMF_I7; + input EOMF_I8; + output INV_K_O; + inout [19:0] LINK; + input PWDN_N_I; + input REP_E_I; + input RST_N_I; + input SCR_E_I1; + input SCR_E_I2; + input SCR_E_I3; + input SCR_E_I4; + input SCR_E_I5; + input SCR_E_I6; + input SCR_E_I7; + input SCR_E_I8; + parameter gearbox_en = 1'b0; + parameter gearbox_mode = 1'b0; + parameter location = ""; + parameter pcs_8b_scr_sel = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_enc_bypass = 1'b0; + parameter pcs_esistream_fsm_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_scr_bypass = 1'b0; + parameter pcs_scr_init = 17'b00000000000000000; + parameter pcs_sync_supported = 1'b0; + parameter pma_clk_pos = 1'b0; + parameter pma_loopback = 1'b0; +endmodule + +//(* blackbox *) +//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4); +// input A1; +// input A2; +// input A3; +// input A4; +// input B1; +// input B2; +// input B3; +// input B4; +// input CI; +// output CO; +// output S1; +// output S2; +// output S3; +// output S4; +// parameter add_carry = 0; +//endmodule + +(* blackbox *) +module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID); + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + input FCK; + output FLD; + output FLG; + input FZ; + input IO; + output [4:0] O; + input R; + input SCK; + parameter data_size = 5; + parameter differential = ""; + parameter dpath_dynamic = 1'b0; + parameter drive = ""; + parameter inputDelayLine = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +//(* blackbox *) +//module NX_DFF(I, CK, L, R, O); +// input CK; +// input I; +// input L; +// output O; +// input R; +// parameter dff_ctxt = 1'b0; +// parameter dff_edge = 1'b0; +// parameter dff_init = 1'b0; +// parameter dff_load = 1'b0; +// parameter dff_sync = 1'b0; +// parameter dff_type = 1'b0; +//endmodule + +(* blackbox *) +module NX_DFR(I, CK, L, R, O); + input CK; + input I; + input L; + output O; + input R; + parameter data_inv = 1'b0; + parameter dff_edge = 1'b0; + parameter dff_init = 1'b0; + parameter dff_load = 1'b0; + parameter dff_sync = 1'b0; + parameter dff_type = 1'b0; + parameter iobname = ""; + parameter location = ""; + parameter mode = 0; + parameter path = 0; + parameter ring = 0; +endmodule + +(* blackbox *) +module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9 +, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12 +, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15 +, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11 +, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32 +, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53 +, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18 +, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39 +, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4 +, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3 +, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24 +, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45 +, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI2; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO2; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO49; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + input RZ; + input WE; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 +, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 +, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 +, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37 +, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 +, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 +, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 +, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 +, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 +, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 +, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12 +, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33 +, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54 +, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI19; + input CAI2; + input CAI20; + input CAI21; + input CAI22; + input CAI23; + input CAI24; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO19; + output CAO2; + output CAO20; + output CAO21; + output CAO22; + output CAO23; + output CAO24; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO57; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + input RZ; + input WE; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO36; + output CO56; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 1'b0; + parameter ALU_MUX = 1'b0; + parameter ALU_OP = 6'b000000; + parameter CO_SEL = 1'b0; + parameter ENABLE_PR_ALU_RST = 1'b0; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 2'b00; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_ALU_MUX = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; + parameter Z_FEEDBACK_SHL12 = 1'b0; +endmodule + +(* blackbox *) +module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO57; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [17:0] CAI; + output [17:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO36; + output CO48; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 1'b0; + parameter ALU_MUX = 1'b0; + parameter ALU_OP = 6'b000000; + parameter CO_SEL = 1'b0; + parameter ENABLE_PR_ALU_RST = 1'b0; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 2'b00; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_ALU_MUX = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; + parameter Z_FEEDBACK_SHL12 = 1'b0; +endmodule + +(* blackbox *) +module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 +, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 +, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 +, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57 +, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 +, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 +, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 +, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 +, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 +, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 +, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11 +, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32 +, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53 +, Z54, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI19; + input CAI2; + input CAI20; + input CAI21; + input CAI22; + input CAI23; + input CAI24; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO19; + output CAO2; + output CAO20; + output CAO21; + output CAO22; + output CAO23; + output CAO24; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO43; + output CO57; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + output RESERVED; + input RZ; + input WE; + input WEZ; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 27'b000000000000000000000000000; + parameter raw_config1 = 24'b000000000000000000000000; + parameter raw_config2 = 14'b00000000000000; + parameter raw_config3 = 3'b000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO42; + output CO56; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + input WEZ; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 2'b00; + parameter ALU_OP = 3'b000; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CCO_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_CZ_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter INV_RST = 1'b0; + parameter INV_RSTZ = 1'b0; + parameter INV_WE = 1'b0; + parameter INV_WEZ = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CCI = 1'b0; + parameter MUX_CCO = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_CZ = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 3'b000; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CCO_MUX = 1'b0; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_CZ_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_RSTZ_MUX = 1'b0; + parameter PR_RST_MUX = 1'b0; + parameter PR_WEZ_MUX = 1'b0; + parameter PR_WE_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; +endmodule + +(* blackbox *) +module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO43; + output CO57; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + input WEZ; + output [55:0] Z; + parameter raw_config0 = 27'b000000000000000000000000000; + parameter raw_config1 = 24'b000000000000000000000000; + parameter raw_config2 = 14'b00000000000000; + parameter raw_config3 = 3'b000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [17:0] CAI; + output [17:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO49; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_ECC(CKD, CHK, COR, ERR); + input CHK; + input CKD; + output COR; + output ERR; +endmodule + +(* blackbox *) +module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO); + input [17:0] I; + output [17:0] O; + input [5:0] RAI; + output [5:0] RAO; + input RCK; + output REQ; + input RRSTI; + output RRSTO; + input [5:0] WAI; + output [5:0] WAO; + input WCK; + input WE; + input WEA; + output WEQ; + input WRSTI; + output WRSTO; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 6'b000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17 +, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2 +, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23 +, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7 +, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2 +, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2); + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I17; + input I18; + input I19; + input I2; + input I20; + input I21; + input I22; + input I23; + input I24; + input I25; + input I26; + input I27; + input I28; + input I29; + input I3; + input I30; + input I31; + input I32; + input I33; + input I34; + input I35; + input I36; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O17; + output O18; + output O19; + output O2; + output O20; + output O21; + output O22; + output O23; + output O24; + output O25; + output O26; + output O27; + output O28; + output O29; + output O3; + output O30; + output O31; + output O32; + output O33; + output O34; + output O35; + output O36; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RAI1; + input RAI2; + input RAI3; + input RAI4; + input RAI5; + input RAI6; + input RAI7; + output RAO1; + output RAO2; + output RAO3; + output RAO4; + output RAO5; + output RAO6; + output RAO7; + input RCK; + output REQ1; + output REQ2; + input RRSTI; + output RRSTO; + input WAI1; + input WAI2; + input WAI3; + input WAI4; + input WAI5; + input WAI6; + input WAI7; + output WAO1; + output WAO2; + output WAO3; + output WAO4; + output WAO5; + output WAO6; + output WAO7; + input WCK; + input WE; + input WEA; + output WEQ1; + output WEQ2; + input WRSTI; + output WRSTO; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_GCK_U(SI1, SI2, CMD, SO); + input CMD; + input SI1; + input SI2; + output SO; + parameter inv_in = 1'b0; + parameter inv_out = 1'b0; + parameter std_mode = "BYPASS"; +endmodule + +(* blackbox *) +module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o +, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o +, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o +, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o +, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o +, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o +, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i +, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i +, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o +, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o +, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o +, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o +, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i); + input hssl_clk_ref_i; + input hssl_clk_user_i; + output hssl_clock_o; + input pma_clk_ext_i; + input pma_rx0_i; + input pma_rx1_i; + input pma_rx2_i; + input pma_rx3_i; + input pma_rx4_i; + input pma_rx5_i; + output pma_tx0_o; + output pma_tx1_o; + output pma_tx2_o; + output pma_tx3_o; + output pma_tx4_o; + output pma_tx5_o; + input usr_calibrate_pma_en_i; + output usr_calibrate_pma_out_o; + input [7:0] usr_calibrate_pma_res_n2_i; + input [7:0] usr_calibrate_pma_res_n3_i; + input [7:0] usr_calibrate_pma_res_p1_i; + input [7:0] usr_calibrate_pma_res_p4_i; + input [3:0] usr_calibrate_pma_sel_i; + input [5:0] usr_com_ctrl_rx_sel_i; + input [5:0] usr_com_ctrl_tx_sel_i; + input [3:0] usr_com_rx_pma_ctle_cap_i; + input [3:0] usr_com_rx_pma_ctle_resn_i; + input [3:0] usr_com_rx_pma_ctle_resp_i; + input usr_com_rx_pma_m_eye_i; + input [5:0] usr_com_tx_pma_main_en_i; + input usr_com_tx_pma_main_sign_i; + input [3:0] usr_com_tx_pma_margin_input_sel_i; + input [4:0] usr_com_tx_pma_margin_input_sel_var_i; + input [3:0] usr_com_tx_pma_margin_sel_i; + input [4:0] usr_com_tx_pma_margin_sel_var_i; + input [4:0] usr_com_tx_pma_post_en_i; + input [3:0] usr_com_tx_pma_post_input_sel_i; + input [3:0] usr_com_tx_pma_post_input_sel_var_i; + input usr_com_tx_pma_post_sign_i; + input usr_com_tx_pma_pre_en_i; + input [3:0] usr_com_tx_pma_pre_input_sel_i; + input usr_com_tx_pma_pre_sign_i; + input usr_main_rst_n_i; + input [7:0] usr_main_test_i; + output [7:0] usr_main_test_o; + input usr_pcs_ctrl_ovs_en_i; + input usr_pcs_ctrl_pll_lock_en_i; + output usr_pll_lock_o; + input usr_pll_pma_rst_n_i; + output usr_rx0_busy_o; + input usr_rx0_ctrl_align_en_i; + input usr_rx0_ctrl_align_sync_i; + output [7:0] usr_rx0_ctrl_char_is_a_o; + output usr_rx0_ctrl_char_is_aligned_o; + output [7:0] usr_rx0_ctrl_char_is_comma_o; + output [7:0] usr_rx0_ctrl_char_is_f_o; + output [7:0] usr_rx0_ctrl_char_is_k_o; + input usr_rx0_ctrl_dec_en_i; + output [7:0] usr_rx0_ctrl_disp_err_o; + input usr_rx0_ctrl_dscr_en_i; + input usr_rx0_ctrl_el_buff_fifo_en_i; + input usr_rx0_ctrl_el_buff_rst_i; + output [7:0] usr_rx0_ctrl_not_in_table_o; + input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; + input usr_rx0_ctrl_replace_en_i; + output [63:0] usr_rx0_data_o; + output usr_rx0_pll_lock_o; + input usr_rx0_pma_cdr_rst_i; + input usr_rx0_pma_ckgen_rst_n_i; + output usr_rx0_pma_loss_of_signal_o; + input usr_rx0_pma_pll_rst_n_i; + input usr_rx0_rst_n_i; + input [3:0] usr_rx0_test_i; + output [7:0] usr_rx0_test_o; + output usr_rx1_busy_o; + input usr_rx1_ctrl_align_en_i; + input usr_rx1_ctrl_align_sync_i; + output [7:0] usr_rx1_ctrl_char_is_a_o; + output usr_rx1_ctrl_char_is_aligned_o; + output [7:0] usr_rx1_ctrl_char_is_comma_o; + output [7:0] usr_rx1_ctrl_char_is_f_o; + output [7:0] usr_rx1_ctrl_char_is_k_o; + input usr_rx1_ctrl_dec_en_i; + output [7:0] usr_rx1_ctrl_disp_err_o; + input usr_rx1_ctrl_dscr_en_i; + input usr_rx1_ctrl_el_buff_fifo_en_i; + input usr_rx1_ctrl_el_buff_rst_i; + output [7:0] usr_rx1_ctrl_not_in_table_o; + input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; + input usr_rx1_ctrl_replace_en_i; + output [63:0] usr_rx1_data_o; + output usr_rx1_pll_lock_o; + input usr_rx1_pma_cdr_rst_i; + input usr_rx1_pma_ckgen_rst_n_i; + output usr_rx1_pma_loss_of_signal_o; + input usr_rx1_pma_pll_rst_n_i; + input usr_rx1_rst_n_i; + input [3:0] usr_rx1_test_i; + output [7:0] usr_rx1_test_o; + output usr_rx2_busy_o; + input usr_rx2_ctrl_align_en_i; + input usr_rx2_ctrl_align_sync_i; + output [7:0] usr_rx2_ctrl_char_is_a_o; + output usr_rx2_ctrl_char_is_aligned_o; + output [7:0] usr_rx2_ctrl_char_is_comma_o; + output [7:0] usr_rx2_ctrl_char_is_f_o; + output [7:0] usr_rx2_ctrl_char_is_k_o; + input usr_rx2_ctrl_dec_en_i; + output [7:0] usr_rx2_ctrl_disp_err_o; + input usr_rx2_ctrl_dscr_en_i; + input usr_rx2_ctrl_el_buff_fifo_en_i; + input usr_rx2_ctrl_el_buff_rst_i; + output [7:0] usr_rx2_ctrl_not_in_table_o; + input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; + input usr_rx2_ctrl_replace_en_i; + output [63:0] usr_rx2_data_o; + output usr_rx2_pll_lock_o; + input usr_rx2_pma_cdr_rst_i; + input usr_rx2_pma_ckgen_rst_n_i; + output usr_rx2_pma_loss_of_signal_o; + input usr_rx2_pma_pll_rst_n_i; + input usr_rx2_rst_n_i; + input [3:0] usr_rx2_test_i; + output [7:0] usr_rx2_test_o; + output usr_rx3_busy_o; + input usr_rx3_ctrl_align_en_i; + input usr_rx3_ctrl_align_sync_i; + output [7:0] usr_rx3_ctrl_char_is_a_o; + output usr_rx3_ctrl_char_is_aligned_o; + output [7:0] usr_rx3_ctrl_char_is_comma_o; + output [7:0] usr_rx3_ctrl_char_is_f_o; + output [7:0] usr_rx3_ctrl_char_is_k_o; + input usr_rx3_ctrl_dec_en_i; + output [7:0] usr_rx3_ctrl_disp_err_o; + input usr_rx3_ctrl_dscr_en_i; + input usr_rx3_ctrl_el_buff_fifo_en_i; + input usr_rx3_ctrl_el_buff_rst_i; + output [7:0] usr_rx3_ctrl_not_in_table_o; + input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; + input usr_rx3_ctrl_replace_en_i; + output [63:0] usr_rx3_data_o; + output usr_rx3_pll_lock_o; + input usr_rx3_pma_cdr_rst_i; + input usr_rx3_pma_ckgen_rst_n_i; + output usr_rx3_pma_loss_of_signal_o; + input usr_rx3_pma_pll_rst_n_i; + input usr_rx3_rst_n_i; + input [3:0] usr_rx3_test_i; + output [7:0] usr_rx3_test_o; + output usr_rx4_busy_o; + input usr_rx4_ctrl_align_en_i; + input usr_rx4_ctrl_align_sync_i; + output [7:0] usr_rx4_ctrl_char_is_a_o; + output usr_rx4_ctrl_char_is_aligned_o; + output [7:0] usr_rx4_ctrl_char_is_comma_o; + output [7:0] usr_rx4_ctrl_char_is_f_o; + output [7:0] usr_rx4_ctrl_char_is_k_o; + input usr_rx4_ctrl_dec_en_i; + output [7:0] usr_rx4_ctrl_disp_err_o; + input usr_rx4_ctrl_dscr_en_i; + input usr_rx4_ctrl_el_buff_fifo_en_i; + input usr_rx4_ctrl_el_buff_rst_i; + output [7:0] usr_rx4_ctrl_not_in_table_o; + input [1:0] usr_rx4_ctrl_ovs_bit_sel_i; + input usr_rx4_ctrl_replace_en_i; + output [63:0] usr_rx4_data_o; + output usr_rx4_pll_lock_o; + input usr_rx4_pma_cdr_rst_i; + input usr_rx4_pma_ckgen_rst_n_i; + output usr_rx4_pma_loss_of_signal_o; + input usr_rx4_pma_pll_rst_n_i; + input usr_rx4_rst_n_i; + input [3:0] usr_rx4_test_i; + output [7:0] usr_rx4_test_o; + output usr_rx5_busy_o; + input usr_rx5_ctrl_align_en_i; + input usr_rx5_ctrl_align_sync_i; + output [7:0] usr_rx5_ctrl_char_is_a_o; + output usr_rx5_ctrl_char_is_aligned_o; + output [7:0] usr_rx5_ctrl_char_is_comma_o; + output [7:0] usr_rx5_ctrl_char_is_f_o; + output [7:0] usr_rx5_ctrl_char_is_k_o; + input usr_rx5_ctrl_dec_en_i; + output [7:0] usr_rx5_ctrl_disp_err_o; + input usr_rx5_ctrl_dscr_en_i; + input usr_rx5_ctrl_el_buff_fifo_en_i; + input usr_rx5_ctrl_el_buff_rst_i; + output [7:0] usr_rx5_ctrl_not_in_table_o; + input [1:0] usr_rx5_ctrl_ovs_bit_sel_i; + input usr_rx5_ctrl_replace_en_i; + output [63:0] usr_rx5_data_o; + output usr_rx5_pll_lock_o; + input usr_rx5_pma_cdr_rst_i; + input usr_rx5_pma_ckgen_rst_n_i; + output usr_rx5_pma_loss_of_signal_o; + input usr_rx5_pma_pll_rst_n_i; + input usr_rx5_rst_n_i; + input [3:0] usr_rx5_test_i; + output [7:0] usr_rx5_test_o; + output usr_tx0_busy_o; + input [7:0] usr_tx0_ctrl_char_is_k_i; + input [7:0] usr_tx0_ctrl_enc_en_i; + input [7:0] usr_tx0_ctrl_end_of_frame_i; + input [7:0] usr_tx0_ctrl_end_of_multiframe_i; + input usr_tx0_ctrl_replace_en_i; + input [7:0] usr_tx0_ctrl_scr_en_i; + input [63:0] usr_tx0_data_i; + input usr_tx0_pma_clk_en_i; + input usr_tx0_rst_n_i; + input [3:0] usr_tx0_test_i; + output [3:0] usr_tx0_test_o; + output usr_tx1_busy_o; + input [7:0] usr_tx1_ctrl_char_is_k_i; + input [7:0] usr_tx1_ctrl_enc_en_i; + input [7:0] usr_tx1_ctrl_end_of_frame_i; + input [7:0] usr_tx1_ctrl_end_of_multiframe_i; + input usr_tx1_ctrl_replace_en_i; + input [7:0] usr_tx1_ctrl_scr_en_i; + input [63:0] usr_tx1_data_i; + input usr_tx1_pma_clk_en_i; + input usr_tx1_rst_n_i; + input [3:0] usr_tx1_test_i; + output [3:0] usr_tx1_test_o; + output usr_tx2_busy_o; + input [7:0] usr_tx2_ctrl_char_is_k_i; + input [7:0] usr_tx2_ctrl_enc_en_i; + input [7:0] usr_tx2_ctrl_end_of_frame_i; + input [7:0] usr_tx2_ctrl_end_of_multiframe_i; + input usr_tx2_ctrl_replace_en_i; + input [7:0] usr_tx2_ctrl_scr_en_i; + input [63:0] usr_tx2_data_i; + input usr_tx2_pma_clk_en_i; + input usr_tx2_rst_n_i; + input [3:0] usr_tx2_test_i; + output [3:0] usr_tx2_test_o; + output usr_tx3_busy_o; + input [7:0] usr_tx3_ctrl_char_is_k_i; + input [7:0] usr_tx3_ctrl_enc_en_i; + input [7:0] usr_tx3_ctrl_end_of_frame_i; + input [7:0] usr_tx3_ctrl_end_of_multiframe_i; + input usr_tx3_ctrl_replace_en_i; + input [7:0] usr_tx3_ctrl_scr_en_i; + input [63:0] usr_tx3_data_i; + input usr_tx3_pma_clk_en_i; + input usr_tx3_rst_n_i; + input [3:0] usr_tx3_test_i; + output [3:0] usr_tx3_test_o; + output usr_tx4_busy_o; + input [7:0] usr_tx4_ctrl_char_is_k_i; + input [7:0] usr_tx4_ctrl_enc_en_i; + input [7:0] usr_tx4_ctrl_end_of_frame_i; + input [7:0] usr_tx4_ctrl_end_of_multiframe_i; + input usr_tx4_ctrl_replace_en_i; + input [7:0] usr_tx4_ctrl_scr_en_i; + input [63:0] usr_tx4_data_i; + input usr_tx4_pma_clk_en_i; + input usr_tx4_rst_n_i; + input [3:0] usr_tx4_test_i; + output [3:0] usr_tx4_test_o; + output usr_tx5_busy_o; + input [7:0] usr_tx5_ctrl_char_is_k_i; + input [7:0] usr_tx5_ctrl_enc_en_i; + input [7:0] usr_tx5_ctrl_end_of_frame_i; + input [7:0] usr_tx5_ctrl_end_of_multiframe_i; + input usr_tx5_ctrl_replace_en_i; + input [7:0] usr_tx5_ctrl_scr_en_i; + input [63:0] usr_tx5_data_i; + input usr_tx5_pma_clk_en_i; + input usr_tx5_rst_n_i; + input [3:0] usr_tx5_test_i; + output [3:0] usr_tx5_test_o; + parameter cfg_main_i = 34'b0000000000000000000000000000000000; + parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_tx0_i = 0; + parameter cfg_tx1_i = 0; + parameter cfg_tx2_i = 0; + parameter cfg_tx3_i = 0; + parameter cfg_tx4_i = 0; + parameter cfg_tx5_i = 0; + parameter location = ""; +endmodule + +(* blackbox *) +module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i +, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o +, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o +, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i +, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i +, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o +, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o +, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i +, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i +, usr_dyn_cfg_lane_cs_n_i); + input hssl_clk_ref_i; + input hssl_clk_user_rx_i; + input hssl_clk_user_tx_i; + output hssl_clock_o; + output hssl_rclock_o; + input scan_en_i; + input [7:0] scan_in_i; + output [7:0] scan_out_o; + output usr_calibrate_pma_out_o; + input [3:0] usr_dyn_cfg_addr_i; + input usr_dyn_cfg_calibration_cs_n_i; + input usr_dyn_cfg_en_i; + input [3:0] usr_dyn_cfg_lane_cs_n_i; + input [11:0] usr_dyn_cfg_wdata_i; + input usr_dyn_cfg_wdata_sel_i; + input usr_dyn_cfg_we_n_i; + input usr_main_async_debug_ack_i; + input [1:0] usr_main_async_debug_lane_sel_i; + output usr_main_async_debug_req_o; + input usr_main_rst_n_i; + output [19:0] usr_main_rx_pma_ll_out_o; + output usr_pll_ckfb_lock_o; + output usr_pll_lock_o; + output usr_pll_pma_lock_analog_o; + input usr_pll_pma_pwr_down_n_i; + input usr_pll_pma_rst_n_i; + output usr_rx0_busy_o; + input usr_rx0_ctrl_align_en_i; + input usr_rx0_ctrl_align_sync_i; + output [7:0] usr_rx0_ctrl_char_is_a_o; + output usr_rx0_ctrl_char_is_aligned_o; + output [7:0] usr_rx0_ctrl_char_is_comma_o; + output [7:0] usr_rx0_ctrl_char_is_f_o; + output [7:0] usr_rx0_ctrl_char_is_k_o; + input [2:0] usr_rx0_ctrl_debug_sel_i; + input usr_rx0_ctrl_dec_en_i; + output [7:0] usr_rx0_ctrl_disp_err_o; + input usr_rx0_ctrl_dscr_en_i; + input usr_rx0_ctrl_el_buff_rst_i; + output [7:0] usr_rx0_ctrl_not_in_table_o; + input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; + input usr_rx0_ctrl_replace_en_i; + output usr_rx0_ctrl_valid_realign_o; + output [63:0] usr_rx0_data_o; + output usr_rx0_pma_ll_fast_locked_o; + output usr_rx0_pma_ll_slow_locked_o; + output usr_rx0_pma_loss_of_signal_o; + input usr_rx0_pma_m_eye_rst_i; + output usr_rx0_pma_pll_lock_o; + output usr_rx0_pma_pll_lock_track_o; + input usr_rx0_pma_pwr_down_n_i; + input usr_rx0_pma_rst_n_i; + input usr_rx0_rst_n_i; + output [7:0] usr_rx0_test_o; + output usr_rx1_busy_o; + input usr_rx1_ctrl_align_en_i; + input usr_rx1_ctrl_align_sync_i; + output [7:0] usr_rx1_ctrl_char_is_a_o; + output usr_rx1_ctrl_char_is_aligned_o; + output [7:0] usr_rx1_ctrl_char_is_comma_o; + output [7:0] usr_rx1_ctrl_char_is_f_o; + output [7:0] usr_rx1_ctrl_char_is_k_o; + input [2:0] usr_rx1_ctrl_debug_sel_i; + input usr_rx1_ctrl_dec_en_i; + output [7:0] usr_rx1_ctrl_disp_err_o; + input usr_rx1_ctrl_dscr_en_i; + input usr_rx1_ctrl_el_buff_rst_i; + output [7:0] usr_rx1_ctrl_not_in_table_o; + input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; + input usr_rx1_ctrl_replace_en_i; + output usr_rx1_ctrl_valid_realign_o; + output [63:0] usr_rx1_data_o; + output usr_rx1_pma_ll_fast_locked_o; + output usr_rx1_pma_ll_slow_locked_o; + output usr_rx1_pma_loss_of_signal_o; + input usr_rx1_pma_m_eye_rst_i; + output usr_rx1_pma_pll_lock_o; + output usr_rx1_pma_pll_lock_track_o; + input usr_rx1_pma_pwr_down_n_i; + input usr_rx1_pma_rst_n_i; + input usr_rx1_rst_n_i; + output [7:0] usr_rx1_test_o; + output usr_rx2_busy_o; + input usr_rx2_ctrl_align_en_i; + input usr_rx2_ctrl_align_sync_i; + output [7:0] usr_rx2_ctrl_char_is_a_o; + output usr_rx2_ctrl_char_is_aligned_o; + output [7:0] usr_rx2_ctrl_char_is_comma_o; + output [7:0] usr_rx2_ctrl_char_is_f_o; + output [7:0] usr_rx2_ctrl_char_is_k_o; + input [2:0] usr_rx2_ctrl_debug_sel_i; + input usr_rx2_ctrl_dec_en_i; + output [7:0] usr_rx2_ctrl_disp_err_o; + input usr_rx2_ctrl_dscr_en_i; + input usr_rx2_ctrl_el_buff_rst_i; + output [7:0] usr_rx2_ctrl_not_in_table_o; + input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; + input usr_rx2_ctrl_replace_en_i; + output usr_rx2_ctrl_valid_realign_o; + output [63:0] usr_rx2_data_o; + output usr_rx2_pma_ll_fast_locked_o; + output usr_rx2_pma_ll_slow_locked_o; + output usr_rx2_pma_loss_of_signal_o; + input usr_rx2_pma_m_eye_rst_i; + output usr_rx2_pma_pll_lock_o; + output usr_rx2_pma_pll_lock_track_o; + input usr_rx2_pma_pwr_down_n_i; + input usr_rx2_pma_rst_n_i; + input usr_rx2_rst_n_i; + output [7:0] usr_rx2_test_o; + output usr_rx3_busy_o; + input usr_rx3_ctrl_align_en_i; + input usr_rx3_ctrl_align_sync_i; + output [7:0] usr_rx3_ctrl_char_is_a_o; + output usr_rx3_ctrl_char_is_aligned_o; + output [7:0] usr_rx3_ctrl_char_is_comma_o; + output [7:0] usr_rx3_ctrl_char_is_f_o; + output [7:0] usr_rx3_ctrl_char_is_k_o; + input [2:0] usr_rx3_ctrl_debug_sel_i; + input usr_rx3_ctrl_dec_en_i; + output [7:0] usr_rx3_ctrl_disp_err_o; + input usr_rx3_ctrl_dscr_en_i; + input usr_rx3_ctrl_el_buff_rst_i; + output [7:0] usr_rx3_ctrl_not_in_table_o; + input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; + input usr_rx3_ctrl_replace_en_i; + output usr_rx3_ctrl_valid_realign_o; + output [63:0] usr_rx3_data_o; + output usr_rx3_pma_ll_fast_locked_o; + output usr_rx3_pma_ll_slow_locked_o; + output usr_rx3_pma_loss_of_signal_o; + input usr_rx3_pma_m_eye_rst_i; + output usr_rx3_pma_pll_lock_o; + output usr_rx3_pma_pll_lock_track_o; + input usr_rx3_pma_pwr_down_n_i; + input usr_rx3_pma_rst_n_i; + input usr_rx3_rst_n_i; + output [7:0] usr_rx3_test_o; + output usr_tx0_busy_o; + input [7:0] usr_tx0_ctrl_char_is_k_i; + input usr_tx0_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx0_ctrl_enc_en_i; + input [7:0] usr_tx0_ctrl_end_of_frame_i; + input [7:0] usr_tx0_ctrl_end_of_multiframe_i; + output usr_tx0_ctrl_invalid_k_o; + input usr_tx0_ctrl_replace_en_i; + input [7:0] usr_tx0_ctrl_scr_en_i; + input [63:0] usr_tx0_data_i; + input usr_tx0_pma_clk_en_i; + output usr_tx0_pma_tx_clk_o; + input usr_tx0_rst_n_i; + output usr_tx1_busy_o; + input [7:0] usr_tx1_ctrl_char_is_k_i; + input usr_tx1_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx1_ctrl_enc_en_i; + input [7:0] usr_tx1_ctrl_end_of_frame_i; + input [7:0] usr_tx1_ctrl_end_of_multiframe_i; + output usr_tx1_ctrl_invalid_k_o; + input usr_tx1_ctrl_replace_en_i; + input [7:0] usr_tx1_ctrl_scr_en_i; + input [63:0] usr_tx1_data_i; + input usr_tx1_pma_clk_en_i; + output usr_tx1_pma_tx_clk_o; + input usr_tx1_rst_n_i; + output usr_tx2_busy_o; + input [7:0] usr_tx2_ctrl_char_is_k_i; + input usr_tx2_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx2_ctrl_enc_en_i; + input [7:0] usr_tx2_ctrl_end_of_frame_i; + input [7:0] usr_tx2_ctrl_end_of_multiframe_i; + output usr_tx2_ctrl_invalid_k_o; + input usr_tx2_ctrl_replace_en_i; + input [7:0] usr_tx2_ctrl_scr_en_i; + input [63:0] usr_tx2_data_i; + input usr_tx2_pma_clk_en_i; + output usr_tx2_pma_tx_clk_o; + input usr_tx2_rst_n_i; + output usr_tx3_busy_o; + input [7:0] usr_tx3_ctrl_char_is_k_i; + input usr_tx3_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx3_ctrl_enc_en_i; + input [7:0] usr_tx3_ctrl_end_of_frame_i; + input [7:0] usr_tx3_ctrl_end_of_multiframe_i; + output usr_tx3_ctrl_invalid_k_o; + input usr_tx3_ctrl_replace_en_i; + input [7:0] usr_tx3_ctrl_scr_en_i; + input [63:0] usr_tx3_data_i; + input usr_tx3_pma_clk_en_i; + output usr_tx3_pma_tx_clk_o; + input usr_tx3_rst_n_i; + parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000; + parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0; + parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000; + parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000; + parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000; + parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00; + parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000; + parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0; + parameter cfg_main_clk_to_fabric_div_en_i = 1'b0; + parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0; + parameter cfg_main_clk_to_fabric_sel_i = 1'b0; + parameter cfg_main_rclk_to_fabric_sel_i = 2'b00; + parameter cfg_main_use_only_usr_clock_i = 1'b0; + parameter cfg_pcs_ovs_en_i = 1'b0; + parameter cfg_pcs_ovs_mode_i = 1'b0; + parameter cfg_pcs_pll_lock_ppm_i = 3'b000; + parameter cfg_pcs_word_len_i = 2'b00; + parameter cfg_pll_pma_ckref_ext_i = 1'b0; + parameter cfg_pll_pma_cpump_i = 4'b0000; + parameter cfg_pll_pma_divl_i = 2'b00; + parameter cfg_pll_pma_divm_i = 1'b0; + parameter cfg_pll_pma_divn_i = 2'b00; + parameter cfg_pll_pma_gbx_en_i = 1'b0; + parameter cfg_pll_pma_int_data_len_i = 1'b0; + parameter cfg_pll_pma_lvds_en_i = 1'b0; + parameter cfg_pll_pma_lvds_mux_i = 1'b0; + parameter cfg_pll_pma_mux_ckref_i = 1'b0; + parameter cfg_rx0_gearbox_en_i = 1'b0; + parameter cfg_rx0_gearbox_mode_i = 1'b0; + parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx0_pcs_align_bypass_i = 1'b0; + parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx0_pcs_debug_en_i = 1'b0; + parameter cfg_rx0_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx0_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx0_pcs_loopback_i = 1'b0; + parameter cfg_rx0_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx0_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx0_pcs_polarity_i = 1'b0; + parameter cfg_rx0_pcs_protocol_size_i = 1'b0; + parameter cfg_rx0_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx0_pcs_sync_supported_i = 1'b0; + parameter cfg_rx0_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx0_pma_clk_pos_i = 1'b0; + parameter cfg_rx0_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx0_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx0_pma_dco_divl_i = 2'b00; + parameter cfg_rx0_pma_dco_divm_i = 1'b0; + parameter cfg_rx0_pma_dco_divn_i = 2'b00; + parameter cfg_rx0_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx0_pma_fine_ppm_i = 3'b000; + parameter cfg_rx0_pma_loopback_i = 1'b0; + parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx0_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divf_i = 2'b00; + parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divm_i = 2'b00; + parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divn_i = 1'b0; + parameter cfg_rx1_gearbox_en_i = 1'b0; + parameter cfg_rx1_gearbox_mode_i = 1'b0; + parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx1_pcs_align_bypass_i = 1'b0; + parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx1_pcs_debug_en_i = 1'b0; + parameter cfg_rx1_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx1_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx1_pcs_loopback_i = 1'b0; + parameter cfg_rx1_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx1_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx1_pcs_polarity_i = 1'b0; + parameter cfg_rx1_pcs_protocol_size_i = 1'b0; + parameter cfg_rx1_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx1_pcs_sync_supported_i = 1'b0; + parameter cfg_rx1_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx1_pma_clk_pos_i = 1'b0; + parameter cfg_rx1_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx1_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx1_pma_dco_divl_i = 2'b00; + parameter cfg_rx1_pma_dco_divm_i = 1'b0; + parameter cfg_rx1_pma_dco_divn_i = 2'b00; + parameter cfg_rx1_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx1_pma_fine_ppm_i = 3'b000; + parameter cfg_rx1_pma_loopback_i = 1'b0; + parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx1_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divf_i = 2'b00; + parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divm_i = 2'b00; + parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divn_i = 1'b0; + parameter cfg_rx2_gearbox_en_i = 1'b0; + parameter cfg_rx2_gearbox_mode_i = 1'b0; + parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx2_pcs_align_bypass_i = 1'b0; + parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx2_pcs_debug_en_i = 1'b0; + parameter cfg_rx2_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx2_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx2_pcs_loopback_i = 1'b0; + parameter cfg_rx2_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx2_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx2_pcs_polarity_i = 1'b0; + parameter cfg_rx2_pcs_protocol_size_i = 1'b0; + parameter cfg_rx2_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx2_pcs_sync_supported_i = 1'b0; + parameter cfg_rx2_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx2_pma_clk_pos_i = 1'b0; + parameter cfg_rx2_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx2_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx2_pma_dco_divl_i = 2'b00; + parameter cfg_rx2_pma_dco_divm_i = 1'b0; + parameter cfg_rx2_pma_dco_divn_i = 2'b00; + parameter cfg_rx2_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx2_pma_fine_ppm_i = 3'b000; + parameter cfg_rx2_pma_loopback_i = 1'b0; + parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx2_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divf_i = 2'b00; + parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divm_i = 2'b00; + parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divn_i = 1'b0; + parameter cfg_rx3_gearbox_en_i = 1'b0; + parameter cfg_rx3_gearbox_mode_i = 1'b0; + parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx3_pcs_align_bypass_i = 1'b0; + parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx3_pcs_debug_en_i = 1'b0; + parameter cfg_rx3_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx3_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx3_pcs_loopback_i = 1'b0; + parameter cfg_rx3_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx3_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx3_pcs_polarity_i = 1'b0; + parameter cfg_rx3_pcs_protocol_size_i = 1'b0; + parameter cfg_rx3_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx3_pcs_sync_supported_i = 1'b0; + parameter cfg_rx3_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx3_pma_clk_pos_i = 1'b0; + parameter cfg_rx3_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx3_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx3_pma_dco_divl_i = 2'b00; + parameter cfg_rx3_pma_dco_divm_i = 1'b0; + parameter cfg_rx3_pma_dco_divn_i = 2'b00; + parameter cfg_rx3_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx3_pma_fine_ppm_i = 3'b000; + parameter cfg_rx3_pma_loopback_i = 1'b0; + parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx3_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divf_i = 2'b00; + parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divm_i = 2'b00; + parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divn_i = 1'b0; + parameter cfg_test_mode_i = 2'b00; + parameter cfg_tx0_gearbox_en_i = 1'b0; + parameter cfg_tx0_gearbox_mode_i = 1'b0; + parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx0_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx0_pcs_loopback_i = 1'b0; + parameter cfg_tx0_pcs_polarity_i = 1'b0; + parameter cfg_tx0_pcs_protocol_size_i = 1'b0; + parameter cfg_tx0_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx0_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx0_pcs_sync_supported_i = 1'b0; + parameter cfg_tx0_pma_clk_pos_i = 1'b0; + parameter cfg_tx0_pma_loopback_i = 1'b0; + parameter cfg_tx1_gearbox_en_i = 1'b0; + parameter cfg_tx1_gearbox_mode_i = 1'b0; + parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx1_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx1_pcs_loopback_i = 1'b0; + parameter cfg_tx1_pcs_polarity_i = 1'b0; + parameter cfg_tx1_pcs_protocol_size_i = 1'b0; + parameter cfg_tx1_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx1_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx1_pcs_sync_supported_i = 1'b0; + parameter cfg_tx1_pma_clk_pos_i = 1'b0; + parameter cfg_tx1_pma_loopback_i = 1'b0; + parameter cfg_tx2_gearbox_en_i = 1'b0; + parameter cfg_tx2_gearbox_mode_i = 1'b0; + parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx2_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx2_pcs_loopback_i = 1'b0; + parameter cfg_tx2_pcs_polarity_i = 1'b0; + parameter cfg_tx2_pcs_protocol_size_i = 1'b0; + parameter cfg_tx2_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx2_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx2_pcs_sync_supported_i = 1'b0; + parameter cfg_tx2_pma_clk_pos_i = 1'b0; + parameter cfg_tx2_pma_loopback_i = 1'b0; + parameter cfg_tx3_gearbox_en_i = 1'b0; + parameter cfg_tx3_gearbox_mode_i = 1'b0; + parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx3_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx3_pcs_loopback_i = 1'b0; + parameter cfg_tx3_pcs_polarity_i = 1'b0; + parameter cfg_tx3_pcs_protocol_size_i = 1'b0; + parameter cfg_tx3_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx3_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx3_pcs_sync_supported_i = 1'b0; + parameter cfg_tx3_pma_clk_pos_i = 1'b0; + parameter cfg_tx3_pma_loopback_i = 1'b0; + parameter location = ""; + parameter rx_usrclk_use_pcs_clk_2 = 1'b0; + parameter tx_usrclk_use_pcs_clk_2 = 1'b0; +endmodule + +(* blackbox *) +module NX_IOB(I, C, T, O, IO); + input C; + input I; + inout IO; + output O; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 3; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +(* blackbox *) +module NX_IOB_I(C, T, IO, O); + input C; + input IO; + output O; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 1; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +(* blackbox *) +module NX_IOB_O(I, C, T, IO); + input C; + input I; + output IO; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 2; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +(* blackbox *) +module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 +, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4 +, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3 +, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3 +, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR +, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL +, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI +, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO +, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3 +, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2 +, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1 +, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO +, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI +, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO +, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR +, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL +, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1 +, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5 +, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4 +, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3 +, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2 +, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1 +, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR +, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL +, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI +, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO +, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER +, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL +, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5 +, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO +, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI +, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO +, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR +, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL +, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1 +, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5 +); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + output FLD; + output FLG; + input FZ; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + input P24RR; + input P25CI1; + input P25CI2; + input P25CI3; + input P25CI4; + input P25CI5; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + input P28RR; + input P29CI1; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + input P30RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + input P4RR; + input P5CI1; + input P5CI2; + input P5CI3; + input P5CI4; + input P5CI5; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + input P9RR; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter mode_io_cal = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA); + input [1:0] DS; + input GS; + output [2:0] GVDN; + output [2:0] GVIN; + output [2:0] GVON; + input [5:0] LA; + output [3:0] PA; +endmodule + +(* blackbox *) +module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 +, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 +, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19 +, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 +, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 +, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 +, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 +, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN +, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN +, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 +, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 +, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20 +, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output AL1D; + output AL1T; + output AL2D; + output AL2T; + output AL3D; + output AL3T; + input ALCK1; + input ALCK2; + input ALCK3; + input CA1D1; + input CA1D2; + input CA1D3; + input CA1D4; + input CA1D5; + input CA1D6; + input CA1N1; + input CA1N2; + input CA1N3; + input CA1N4; + input CA1P1; + input CA1P2; + input CA1P3; + input CA1P4; + input CA1T1; + input CA1T2; + input CA1T3; + input CA1T4; + input CA2D1; + input CA2D2; + input CA2D3; + input CA2D4; + input CA2D5; + input CA2D6; + input CA2N1; + input CA2N2; + input CA2N3; + input CA2N4; + input CA2P1; + input CA2P2; + input CA2P3; + input CA2P4; + input CA2T1; + input CA2T2; + input CA2T3; + input CA2T4; + input CCK; + output CKO1; + output CKO2; + output DCL; + input DCRN; + input DQ1CI1; + input DQ1CI2; + input DQ1CI3; + input DQ1CI4; + input DQ1CI5; + input DQ1CI6; + input DQ1CI7; + input DQ1CI8; + input DQ2CI1; + input DQ2CI2; + input DQ2CI3; + input DQ2CI4; + input DQ2CI5; + input DQ2CI6; + input DQ2CI7; + input DQ2CI8; + input DQ3CI1; + input DQ3CI2; + input DQ3CI3; + input DQ3CI4; + input DQ3CI5; + input DQ3CI6; + input DQ3CI7; + input DQ3CI8; + input DQS1CI1; + input DQS1CI2; + input DQS1CI3; + input DQS1CI4; + input DQS1CI5; + input DQS1CI6; + input DQS1CI7; + input DQS1CI8; + input DQS2CI1; + input DQS2CI2; + input DQS2CI3; + input DQS2CI4; + input DQS2CI5; + input DQS2CI6; + input DQS2CI7; + input DQS2CI8; + input DQS3CI1; + input DQS3CI2; + input DQS3CI3; + input DQS3CI4; + input DQS3CI5; + input DQS3CI6; + input DQS3CI7; + input DQS3CI8; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRCCSN; + input DRDPA1CSN; + input DRDPA2CSN; + input DRDPA3CSN; + input DRE; + input DRI1; + input DRI1CSN; + input DRI2; + input DRI2CSN; + input DRI3; + input DRI3CSN; + input DRI4; + input DRI5; + input DRI6; + output DRO1; + input DRO1CSN; + output DRO2; + input DRO2CSN; + output DRO3; + input DRO3CSN; + output DRO4; + output DRO5; + output DRO6; + input DRWDS; + input DRWEN; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + input FCK1; + input FCK2; + input FDCK; + output FLD; + output FLG; + input FZ; + input LD1RN; + input LD2RN; + input LD3RN; + input LDSCK1; + input LDSCK2; + input LDSCK3; + input LE; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input SE; + input SWRX1CK; + input SWRX2CK; + parameter cal_delay1 = ""; + parameter cal_delay2 = ""; + parameter div1 = 3'b000; + parameter div2 = 3'b000; + parameter div3 = 3'b000; + parameter div_swrx1 = 3'b000; + parameter div_swrx2 = 3'b000; + parameter inv_ld_sck1 = 1'b0; + parameter inv_ld_sck2 = 1'b0; + parameter inv_ld_sck3 = 1'b0; + parameter link_ld_12 = 1'b0; + parameter link_ld_23 = 1'b0; + parameter location = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_side3 = 0; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_dc_clk = 2'b00; + parameter sel_ld_fck1 = 2'b00; + parameter sel_ld_fck2 = 2'b00; + parameter sel_ld_fck3 = 2'b00; + parameter sel_sw_fck1 = 2'b00; + parameter sel_sw_fck2 = 2'b00; + parameter use_dc = 1'b0; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 +, RO2, RO3, RO4, RO5, CTO, LINK); + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 2'b00; + parameter variant = ""; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 +, RO2, RO3, RO4, RO5, CTO, LINK); + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 2'b00; + parameter variant = ""; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1 +, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK); + input CI1; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EI6; + input EI7; + input EI8; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + output RO6; + output RO7; + output RO8; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter cpath_type = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter epath_type = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter rpath_type = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 1'b0; +endmodule + +(* blackbox *) +module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 +, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1 +, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR +, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL +, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI +, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4 +, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3 +, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2 +, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1 +, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO +, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI +, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO +, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR +, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL +, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1 +, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5 +, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4 +, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3 +, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2 +, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1 +, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR +, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL +, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI +, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO +, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER +, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL +, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5 +, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4 +, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3 +, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2 +, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR +, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL +, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1 +, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5 +, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4 +, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3 +, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2 +, P34RO3, P34RO4, P34RO5); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + input P24RR; + input P25CI1; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + input P28RR; + input P29CI1; + input P29CI2; + input P29CI3; + input P29CI4; + input P29CI5; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + input P30RR; + input P31CI1; + input P31CL; + output P31CO; + input P31CR; + input P31CTI; + output P31CTO; + input P31EI1; + input P31EI2; + input P31EI3; + input P31EI4; + input P31EI5; + input P31EL; + output P31EO; + input P31ER; + input P31RI; + input P31RL; + output P31RO1; + output P31RO2; + output P31RO3; + output P31RO4; + output P31RO5; + input P31RR; + input P32CI1; + input P32CL; + output P32CO; + input P32CR; + input P32CTI; + output P32CTO; + input P32EI1; + input P32EI2; + input P32EI3; + input P32EI4; + input P32EI5; + input P32EL; + output P32EO; + input P32ER; + input P32RI; + input P32RL; + output P32RO1; + output P32RO2; + output P32RO3; + output P32RO4; + output P32RO5; + input P32RR; + input P33CI1; + input P33CL; + output P33CO; + input P33CR; + input P33CTI; + output P33CTO; + input P33EI1; + input P33EI2; + input P33EI3; + input P33EI4; + input P33EI5; + input P33EL; + output P33EO; + input P33ER; + input P33RI; + input P33RL; + output P33RO1; + output P33RO2; + output P33RO3; + output P33RO4; + output P33RO5; + input P33RR; + input P34CI1; + input P34CL; + output P34CO; + input P34CR; + input P34CTI; + output P34CTO; + input P34EI1; + input P34EI2; + input P34EI3; + input P34EI4; + input P34EI5; + input P34EL; + output P34EO; + input P34ER; + input P34RI; + input P34RL; + output P34RO1; + output P34RO2; + output P34RO3; + output P34RO4; + output P34RO5; + input P34RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + input P4RR; + input P5CI1; + input P5CI2; + input P5CI3; + input P5CI4; + input P5CI5; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + input P9RR; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter mode_io_cal = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); + input CTCK; + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + output FLD; + output FLG; + input FZ; + inout [41:0] LINKN; + inout [41:0] LINKP; + input RRCK; + input RRST; + input RTCK; + input TRST; + input WRCK; + input WTCK; + parameter data_size = 5; + parameter location = ""; +endmodule + +(* blackbox *) +module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); + input CTCK; + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + output FLD; + output FLG; + input FZ; + inout [41:0] LINKN; + inout [41:0] LINKP; + input RRCK; + input RRST; + input RTCK; + input TRST; + input WRCK; + input WTCK; + parameter data_size = 5; + parameter location = ""; +endmodule + +(* blackbox *) +module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON); + output ALD; + output ALT; + output [5:0] DID; + input [3:0] DRA; + input [2:0] DRDN; + input DRE; + input [5:0] DRI; + input [2:0] DRIN; + output [5:0] DRO; + input [2:0] DRON; + input DRWDS; + input DRWEN; + input [5:0] FA; + input FCK; + output FLD; + output FLG; + input FZ; + input LDRN; + inout [41:0] LINK; + input SCK; + parameter data_size = 5; + parameter location = ""; +endmodule + +(* blackbox *) +module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 +, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 +, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN +, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN +, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 +, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 +, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL +, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6 +, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI +, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6 +, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL +, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6 +, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI +, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6 +, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL +, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6 +, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI +, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6 +, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL +, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6 +, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI +, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6 +, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL +, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6 +, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI +, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6 +, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL +, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6 +, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI +, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6 +, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL +, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6 +, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI +, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6 +, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL +, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6 +, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI +, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6 +, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL +, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6 +, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI +, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6 +, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL +, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6 +, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI +, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6 +, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL +, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6 +, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI +, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6 +, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL +, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8); + output AL1D; + output AL1T; + output AL2D; + output AL2T; + output AL3D; + output AL3T; + input ALCK1; + input ALCK2; + input ALCK3; + input CA1D1; + input CA1D2; + input CA1D3; + input CA1D4; + input CA1D5; + input CA1D6; + input CA1N1; + input CA1N2; + input CA1N3; + input CA1N4; + input CA1P1; + input CA1P2; + input CA1P3; + input CA1P4; + input CA1T1; + input CA1T2; + input CA1T3; + input CA1T4; + input CA2D1; + input CA2D2; + input CA2D3; + input CA2D4; + input CA2D5; + input CA2D6; + input CA2N1; + input CA2N2; + input CA2N3; + input CA2N4; + input CA2P1; + input CA2P2; + input CA2P3; + input CA2P4; + input CA2T1; + input CA2T2; + input CA2T3; + input CA2T4; + input CCK; + output CKO1; + output CKO2; + output DCL; + input DCRN; + input DQ1CI1; + input DQ1CI2; + input DQ1CI3; + input DQ1CI4; + input DQ1CI5; + input DQ1CI6; + input DQ1CI7; + input DQ1CI8; + input DQ2CI1; + input DQ2CI2; + input DQ2CI3; + input DQ2CI4; + input DQ2CI5; + input DQ2CI6; + input DQ2CI7; + input DQ2CI8; + input DQ3CI1; + input DQ3CI2; + input DQ3CI3; + input DQ3CI4; + input DQ3CI5; + input DQ3CI6; + input DQ3CI7; + input DQ3CI8; + input DQS1CI1; + input DQS1CI2; + input DQS1CI3; + input DQS1CI4; + input DQS1CI5; + input DQS1CI6; + input DQS1CI7; + input DQS1CI8; + input DQS2CI1; + input DQS2CI2; + input DQS2CI3; + input DQS2CI4; + input DQS2CI5; + input DQS2CI6; + input DQS2CI7; + input DQS2CI8; + input DQS3CI1; + input DQS3CI2; + input DQS3CI3; + input DQS3CI4; + input DQS3CI5; + input DQS3CI6; + input DQS3CI7; + input DQS3CI8; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRCCSN; + input DRDPA1CSN; + input DRDPA2CSN; + input DRDPA3CSN; + input DRE; + input DRI1; + input DRI1CSN; + input DRI2; + input DRI2CSN; + input DRI3; + input DRI3CSN; + input DRI4; + input DRI5; + input DRI6; + output DRO1; + input DRO1CSN; + output DRO2; + input DRO2CSN; + output DRO3; + input DRO3CSN; + output DRO4; + output DRO5; + output DRO6; + input DRWDS; + input DRWEN; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + input FCK1; + input FCK2; + input FDCK; + output FLD; + output FLG; + input FZ; + input LD1RN; + input LD2RN; + input LD3RN; + input LDSCK1; + input LDSCK2; + input LDSCK3; + input LE; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EI6; + input P10EI7; + input P10EI8; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + output P10RO6; + output P10RO7; + output P10RO8; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EI6; + input P11EI7; + input P11EI8; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + output P11RO6; + output P11RO7; + output P11RO8; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EI6; + input P12EI7; + input P12EI8; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + output P12RO6; + output P12RO7; + output P12RO8; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EI6; + input P13EI7; + input P13EI8; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + output P13RO6; + output P13RO7; + output P13RO8; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EI6; + input P14EI7; + input P14EI8; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + output P14RO6; + output P14RO7; + output P14RO8; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EI6; + input P15EI7; + input P15EI8; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + output P15RO6; + output P15RO7; + output P15RO8; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EI6; + input P16EI7; + input P16EI8; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + output P16RO6; + output P16RO7; + output P16RO8; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EI6; + input P17EI7; + input P17EI8; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + output P17RO6; + output P17RO7; + output P17RO8; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EI6; + input P18EI7; + input P18EI8; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + output P18RO6; + output P18RO7; + output P18RO8; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EI6; + input P19EI7; + input P19EI8; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + output P19RO6; + output P19RO7; + output P19RO8; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EI6; + input P1EI7; + input P1EI8; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + output P1RO6; + output P1RO7; + output P1RO8; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EI6; + input P20EI7; + input P20EI8; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + output P20RO6; + output P20RO7; + output P20RO8; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EI6; + input P21EI7; + input P21EI8; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + output P21RO6; + output P21RO7; + output P21RO8; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EI6; + input P22EI7; + input P22EI8; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + output P22RO6; + output P22RO7; + output P22RO8; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EI6; + input P23EI7; + input P23EI8; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + output P23RO6; + output P23RO7; + output P23RO8; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EI6; + input P24EI7; + input P24EI8; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + output P24RO6; + output P24RO7; + output P24RO8; + input P24RR; + input P25CI1; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EI6; + input P25EI7; + input P25EI8; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + output P25RO6; + output P25RO7; + output P25RO8; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EI6; + input P26EI7; + input P26EI8; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + output P26RO6; + output P26RO7; + output P26RO8; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EI6; + input P27EI7; + input P27EI8; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + output P27RO6; + output P27RO7; + output P27RO8; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EI6; + input P28EI7; + input P28EI8; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + output P28RO6; + output P28RO7; + output P28RO8; + input P28RR; + input P29CI1; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EI6; + input P29EI7; + input P29EI8; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + output P29RO6; + output P29RO7; + output P29RO8; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EI6; + input P2EI7; + input P2EI8; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + output P2RO6; + output P2RO7; + output P2RO8; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EI6; + input P30EI7; + input P30EI8; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + output P30RO6; + output P30RO7; + output P30RO8; + input P30RR; + input P31CI1; + input P31CL; + output P31CO; + input P31CR; + input P31CTI; + output P31CTO; + input P31EI1; + input P31EI2; + input P31EI3; + input P31EI4; + input P31EI5; + input P31EI6; + input P31EI7; + input P31EI8; + input P31EL; + output P31EO; + input P31ER; + input P31RI; + input P31RL; + output P31RO1; + output P31RO2; + output P31RO3; + output P31RO4; + output P31RO5; + output P31RO6; + output P31RO7; + output P31RO8; + input P31RR; + input P32CI1; + input P32CL; + output P32CO; + input P32CR; + input P32CTI; + output P32CTO; + input P32EI1; + input P32EI2; + input P32EI3; + input P32EI4; + input P32EI5; + input P32EI6; + input P32EI7; + input P32EI8; + input P32EL; + output P32EO; + input P32ER; + input P32RI; + input P32RL; + output P32RO1; + output P32RO2; + output P32RO3; + output P32RO4; + output P32RO5; + output P32RO6; + output P32RO7; + output P32RO8; + input P32RR; + input P33CI1; + input P33CL; + output P33CO; + input P33CR; + input P33CTI; + output P33CTO; + input P33EI1; + input P33EI2; + input P33EI3; + input P33EI4; + input P33EI5; + input P33EI6; + input P33EI7; + input P33EI8; + input P33EL; + output P33EO; + input P33ER; + input P33RI; + input P33RL; + output P33RO1; + output P33RO2; + output P33RO3; + output P33RO4; + output P33RO5; + output P33RO6; + output P33RO7; + output P33RO8; + input P33RR; + input P34CI1; + input P34CL; + output P34CO; + input P34CR; + input P34CTI; + output P34CTO; + input P34EI1; + input P34EI2; + input P34EI3; + input P34EI4; + input P34EI5; + input P34EI6; + input P34EI7; + input P34EI8; + input P34EL; + output P34EO; + input P34ER; + input P34RI; + input P34RL; + output P34RO1; + output P34RO2; + output P34RO3; + output P34RO4; + output P34RO5; + output P34RO6; + output P34RO7; + output P34RO8; + input P34RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EI6; + input P3EI7; + input P3EI8; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + output P3RO6; + output P3RO7; + output P3RO8; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EI6; + input P4EI7; + input P4EI8; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + output P4RO6; + output P4RO7; + output P4RO8; + input P4RR; + input P5CI1; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EI6; + input P5EI7; + input P5EI8; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + output P5RO6; + output P5RO7; + output P5RO8; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EI6; + input P6EI7; + input P6EI8; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + output P6RO6; + output P6RO7; + output P6RO8; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EI6; + input P7EI7; + input P7EI8; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + output P7RO6; + output P7RO7; + output P7RO8; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EI6; + input P8EI7; + input P8EI8; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + output P8RO6; + output P8RO7; + output P8RO8; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EI6; + input P9EI7; + input P9EI8; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + output P9RO6; + output P9RO7; + output P9RO8; + input P9RR; + input SE; + input SWRX1CK; + input SWRX2CK; + parameter cal_delay1 = ""; + parameter cal_delay2 = ""; + parameter div1 = 3'b000; + parameter div2 = 3'b000; + parameter div3 = 3'b000; + parameter div_swrx1 = 3'b000; + parameter div_swrx2 = 3'b000; + parameter inv_ld_sck1 = 1'b0; + parameter inv_ld_sck2 = 1'b0; + parameter inv_ld_sck3 = 1'b0; + parameter link_ld_12 = 1'b0; + parameter link_ld_23 = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_side3 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_dc_clk = 2'b00; + parameter sel_ld_fck1 = 2'b00; + parameter sel_ld_fck2 = 2'b00; + parameter sel_ld_fck3 = 2'b00; + parameter sel_sw_fck1 = 2'b00; + parameter sel_sw_fck2 = 2'b00; + parameter use_dc = 1'b0; +endmodule + +//(* blackbox *) +//module NX_LUT(I1, I2, I3, I4, O); +// input I1; +// input I2; +// input I3; +// input I4; +// output O; +// parameter lut_table = 16'b0000000000000000; +//endmodule + +(* blackbox *) +module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY); + output D1; + output D2; + output D3; + input FBK; + output OSC; + output RDY; + input REF; + output VCO; + parameter clk_outdiv1 = 0; + parameter clk_outdiv2 = 0; + parameter clk_outdiv3 = 0; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 0; + parameter fbk_delay_on = 1'b0; + parameter fbk_div_on = 1'b0; + parameter fbk_intdiv = 2; + parameter location = ""; + parameter ref_div_on = 1'b0; + parameter vco_range = 0; +endmodule + +(* blackbox *) +module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED); + output CAL_LOCKED; + output DIVO1; + output DIVO2; + output DIVP1; + output DIVP2; + output DIVP3; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + input R; + input REF; + output REFO; + output VCO; + parameter cfg_use_pll = 1'b1; + parameter clk_outdivo1 = 0; + parameter clk_outdivp1 = 0; + parameter clk_outdivp2 = 0; + parameter clk_outdivp3o2 = 0; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 0; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 2; + parameter location = ""; + parameter pll_cpump = 3'b010; + parameter ref_intdiv = 0; + parameter ref_osc_on = 1'b0; + parameter wfg_sync_cal_lock = 1'b0; + parameter wfg_sync_pll_lock = 1'b0; +endmodule + +(* blackbox *) +module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV +, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5); + input ARST_CAL; + output CAL1; + output CAL2; + output CAL3; + output CAL4; + output CAL5; + output CAL_LOCKED; + input CLK_CAL; + output CLK_CAL_DIV; + output CLK_DIV1; + output CLK_DIV2; + output CLK_DIV3; + output CLK_DIV4; + output CLK_DIVD1; + output CLK_DIVD2; + output CLK_DIVD3; + output CLK_DIVD4; + output CLK_DIVD5; + input EXT_CAL1; + input EXT_CAL2; + input EXT_CAL3; + input EXT_CAL4; + input EXT_CAL5; + input EXT_CAL_LOCKED; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + output PLL_LOCKEDA; + input R; + input REF; + output REFO; + output VCO; + parameter cal_delay = 6'b011011; + parameter cal_div = 4'b0111; + parameter clk_cal_sel = 2'b01; + parameter clk_outdiv1 = 3'b000; + parameter clk_outdiv2 = 3'b000; + parameter clk_outdiv3 = 3'b000; + parameter clk_outdiv4 = 3'b000; + parameter clk_outdivd1 = 4'b0000; + parameter clk_outdivd2 = 4'b0000; + parameter clk_outdivd3 = 4'b0000; + parameter clk_outdivd4 = 4'b0000; + parameter clk_outdivd5 = 4'b0000; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 6'b000000; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 7'b0000000; + parameter location = ""; + parameter pll_cpump = 4'b0000; + parameter pll_lock = 4'b0000; + parameter pll_lpf_cap = 4'b0000; + parameter pll_lpf_res = 4'b0000; + parameter pll_odf = 2'b00; + parameter ref_intdiv = 5'b00000; + parameter ref_osc_on = 1'b0; + parameter use_cal = 1'b0; + parameter use_pll = 1'b1; +endmodule + +(* blackbox *) +module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV); + input ARST_CAL; + output [4:0] CAL; + output CAL_LOCKED; + input CLK_CAL; + output CLK_CAL_DIV; + output [3:0] CLK_DIV; + output [4:0] CLK_DIVD; + input [4:0] EXT_CAL; + input EXT_CAL_LOCKED; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + output PLL_LOCKEDA; + input R; + input REF; + output REFO; + output VCO; + parameter cal_delay = 6'b011011; + parameter cal_div = 4'b0111; + parameter clk_cal_sel = 2'b01; + parameter clk_outdiv1 = 3'b000; + parameter clk_outdiv2 = 3'b000; + parameter clk_outdiv3 = 3'b000; + parameter clk_outdiv4 = 3'b000; + parameter clk_outdivd1 = 4'b0000; + parameter clk_outdivd2 = 4'b0000; + parameter clk_outdivd3 = 4'b0000; + parameter clk_outdivd4 = 4'b0000; + parameter clk_outdivd5 = 4'b0000; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 6'b000000; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 7'b0000000; + parameter location = ""; + parameter pll_cpump = 4'b0000; + parameter pll_lock = 4'b0000; + parameter pll_lpf_cap = 4'b0000; + parameter pll_lpf_res = 4'b0000; + parameter pll_odf = 2'b00; + parameter ref_intdiv = 5'b00000; + parameter ref_osc_on = 1'b0; + parameter use_cal = 1'b0; + parameter use_pll = 1'b1; +endmodule + +(* blackbox *) +module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2 +, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3 +, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2 +, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2 +, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7 +, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2 +, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0); + input CAL_1P_I1; + input CAL_1P_I2; + input CAL_1P_I3; + input CAL_1P_I4; + input CAL_1P_I5; + input CAL_1P_I6; + input CAL_1P_I7; + input CAL_1P_I8; + input CAL_2N_I1; + input CAL_2N_I2; + input CAL_2N_I3; + input CAL_2N_I4; + input CAL_2N_I5; + input CAL_2N_I6; + input CAL_2N_I7; + input CAL_2N_I8; + input CAL_3N_I1; + input CAL_3N_I2; + input CAL_3N_I3; + input CAL_3N_I4; + input CAL_3N_I5; + input CAL_3N_I6; + input CAL_3N_I7; + input CAL_3N_I8; + input CAL_4P_I1; + input CAL_4P_I2; + input CAL_4P_I3; + input CAL_4P_I4; + input CAL_4P_I5; + input CAL_4P_I6; + input CAL_4P_I7; + input CAL_4P_I8; + input CAL_E_I; + output CAL_O; + input CAL_SEL_I1; + input CAL_SEL_I2; + input CAL_SEL_I3; + input CAL_SEL_I4; + input CLK_EXT_I; + output CLK_O; + input CLK_REF_I; + input CLK_USER_I; + input CT_CAP_I1; + input CT_CAP_I2; + input CT_CAP_I3; + input CT_CAP_I4; + input CT_RESN_I1; + input CT_RESN_I2; + input CT_RESN_I3; + input CT_RESN_I4; + input CT_RESP_I1; + input CT_RESP_I2; + input CT_RESP_I3; + input CT_RESP_I4; + inout [9:0] LINK_RX0; + inout [9:0] LINK_RX1; + inout [9:0] LINK_RX2; + inout [9:0] LINK_RX3; + inout [9:0] LINK_RX4; + inout [9:0] LINK_RX5; + inout [19:0] LINK_TX0; + inout [19:0] LINK_TX1; + inout [19:0] LINK_TX2; + inout [19:0] LINK_TX3; + inout [19:0] LINK_TX4; + inout [19:0] LINK_TX5; + input LOCK_E_I; + output LOCK_O; + input MAIN_EN_I1; + input MAIN_EN_I2; + input MAIN_EN_I3; + input MAIN_EN_I4; + input MAIN_EN_I5; + input MAIN_EN_I6; + input MAIN_SG_I; + input MARG_ISV_I1; + input MARG_ISV_I2; + input MARG_ISV_I3; + input MARG_ISV_I4; + input MARG_ISV_I5; + input MARG_IS_I1; + input MARG_IS_I2; + input MARG_IS_I3; + input MARG_IS_I4; + input MARG_SV_I1; + input MARG_SV_I2; + input MARG_SV_I3; + input MARG_SV_I4; + input MARG_SV_I5; + input MARG_S_I1; + input MARG_S_I2; + input MARG_S_I3; + input MARG_S_I4; + input M_EYE_I; + input OVS_E_I; + input PLL_RN_I; + input POST_EN_I1; + input POST_EN_I2; + input POST_EN_I3; + input POST_EN_I4; + input POST_EN_I5; + input POST_ISV_I1; + input POST_ISV_I2; + input POST_ISV_I3; + input POST_ISV_I4; + input POST_IS_I1; + input POST_IS_I2; + input POST_IS_I3; + input POST_IS_I4; + input POST_SG_I; + input PRE_EN_I; + input PRE_IS_I1; + input PRE_IS_I2; + input PRE_IS_I3; + input PRE_IS_I4; + input PRE_SG_I; + input RST_N_I; + input RX_SEL_I1; + input RX_SEL_I2; + input RX_SEL_I3; + input RX_SEL_I4; + input RX_SEL_I5; + input RX_SEL_I6; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + input TST_I5; + input TST_I6; + input TST_I7; + input TST_I8; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + input TX_SEL_I1; + input TX_SEL_I2; + input TX_SEL_I3; + input TX_SEL_I4; + input TX_SEL_I5; + input TX_SEL_I6; + parameter location = ""; + parameter main_clk_to_fabric_div_en = 1'b0; + parameter main_clk_to_fabric_div_mode = 1'b0; + parameter main_clk_to_fabric_sel = 1'b0; + parameter main_test = 8'b00000000; + parameter main_use_only_usr_clock = 1'b0; + parameter main_use_pcs_clk_2 = 1'b0; + parameter pcs_ovs_mode = 1'b0; + parameter pcs_pll_lock_count = 3'b000; + parameter pcs_word_len = 2'b00; + parameter pll_pma_cpump_n = 3'b000; + parameter pll_pma_divf = 2'b00; + parameter pll_pma_divf_en_n = 1'b0; + parameter pll_pma_divm = 2'b00; + parameter pll_pma_divm_en_n = 1'b0; + parameter pll_pma_divn = 1'b0; + parameter pll_pma_divn_en_n = 1'b0; + parameter pll_pma_int_data_len = 1'b0; + parameter pll_pma_lvds_mux = 1'b0; + parameter pll_pma_mux_ckref = 1'b0; + parameter rx_pma_half_step = 1'b0; +endmodule + +(* blackbox *) +module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6 +, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8 +, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14 +, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3 +, LINK_TX0); + output CAL_OUT_O; + output CLK_O; + input CLK_REF_I; + input CLK_RX_I; + output CLK_RX_O; + input CLK_TX_I; + input DBG_A_I; + output DBG_R_O; + input DBG_S_I1; + input DBG_S_I2; + input DC_ADD_I1; + input DC_ADD_I2; + input DC_ADD_I3; + input DC_ADD_I4; + input DC_CCSN_I; + input DC_E_I; + input DC_LCSN_I1; + input DC_LCSN_I2; + input DC_LCSN_I3; + input DC_LCSN_I4; + input DC_WDATAS_I; + input DC_WDATA_I1; + input DC_WDATA_I10; + input DC_WDATA_I11; + input DC_WDATA_I12; + input DC_WDATA_I2; + input DC_WDATA_I3; + input DC_WDATA_I4; + input DC_WDATA_I5; + input DC_WDATA_I6; + input DC_WDATA_I7; + input DC_WDATA_I8; + input DC_WDATA_I9; + input DC_WE_N_I; + output FB_LOCK_O; + inout [9:0] LINK_RX0; + inout [9:0] LINK_RX1; + inout [9:0] LINK_RX2; + inout [9:0] LINK_RX3; + inout [19:0] LINK_TX0; + inout [19:0] LINK_TX1; + inout [19:0] LINK_TX2; + inout [19:0] LINK_TX3; + output LL_O1; + output LL_O10; + output LL_O11; + output LL_O12; + output LL_O13; + output LL_O14; + output LL_O15; + output LL_O16; + output LL_O17; + output LL_O18; + output LL_O19; + output LL_O2; + output LL_O20; + output LL_O3; + output LL_O4; + output LL_O5; + output LL_O6; + output LL_O7; + output LL_O8; + output LL_O9; + output LOCKA_O; + output LOCK_O; + input PLL_RN_I; + input PWDN_N_I; + input RST_N_I; + input SCAN_I1; + input SCAN_I2; + input SCAN_I3; + input SCAN_I4; + input SCAN_I5; + input SCAN_I6; + input SCAN_I7; + input SCAN_I8; + output SCAN_O1; + output SCAN_O2; + output SCAN_O3; + output SCAN_O4; + output SCAN_O5; + output SCAN_O6; + output SCAN_O7; + output SCAN_O8; + input SE_I; + parameter dyn_all_rx_pma_m_eye = 1'b0; + parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0; + parameter dyn_all_rx_pma_m_eye_dn = 1'b0; + parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0; + parameter dyn_all_rx_pma_m_eye_step = 4'b0000; + parameter dyn_all_rx_pma_m_eye_up = 1'b0; + parameter dyn_all_rx_pma_threshold_1 = 5'b00000; + parameter dyn_all_rx_pma_threshold_2 = 5'b00000; + parameter dyn_all_rx_pma_trim_locked = 3'b000; + parameter dyn_all_rx_pma_trim_mode = 2'b00; + parameter dyn_all_rx_pma_trim_unlocked = 3'b000; + parameter dyn_rx0_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx0_pma_ctle_res_p = 4'b0000; + parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx0_pma_termination_cmd = 6'b000000; + parameter dyn_rx1_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx1_pma_ctle_res_p = 4'b0000; + parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx1_pma_termination_cmd = 6'b000000; + parameter dyn_rx2_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx2_pma_ctle_res_p = 4'b0000; + parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx2_pma_termination_cmd = 6'b000000; + parameter dyn_rx3_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx3_pma_ctle_res_p = 4'b0000; + parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx3_pma_termination_cmd = 6'b000000; + parameter dyn_tx0_pma_main_en = 6'b000000; + parameter dyn_tx0_pma_main_sign = 1'b0; + parameter dyn_tx0_pma_margin_input = 9'b000000000; + parameter dyn_tx0_pma_margin_sel = 9'b000000000; + parameter dyn_tx0_pma_post_en = 5'b00000; + parameter dyn_tx0_pma_post_sel = 8'b00000000; + parameter dyn_tx0_pma_post_sign = 1'b0; + parameter dyn_tx0_pma_pre_en = 1'b0; + parameter dyn_tx0_pma_pre_sel = 4'b0000; + parameter dyn_tx0_pma_pre_sign = 1'b0; + parameter dyn_tx1_pma_main_en = 6'b000000; + parameter dyn_tx1_pma_main_sign = 1'b0; + parameter dyn_tx1_pma_margin_input = 9'b000000000; + parameter dyn_tx1_pma_margin_sel = 9'b000000000; + parameter dyn_tx1_pma_post_en = 5'b00000; + parameter dyn_tx1_pma_post_sel = 8'b00000000; + parameter dyn_tx1_pma_post_sign = 1'b0; + parameter dyn_tx1_pma_pre_en = 1'b0; + parameter dyn_tx1_pma_pre_sel = 4'b0000; + parameter dyn_tx1_pma_pre_sign = 1'b0; + parameter dyn_tx2_pma_main_en = 6'b000000; + parameter dyn_tx2_pma_main_sign = 1'b0; + parameter dyn_tx2_pma_margin_input = 9'b000000000; + parameter dyn_tx2_pma_margin_sel = 9'b000000000; + parameter dyn_tx2_pma_post_en = 5'b00000; + parameter dyn_tx2_pma_post_sel = 8'b00000000; + parameter dyn_tx2_pma_post_sign = 1'b0; + parameter dyn_tx2_pma_pre_en = 1'b0; + parameter dyn_tx2_pma_pre_sel = 4'b0000; + parameter dyn_tx2_pma_pre_sign = 1'b0; + parameter dyn_tx3_pma_main_en = 6'b000000; + parameter dyn_tx3_pma_main_sign = 1'b0; + parameter dyn_tx3_pma_margin_input = 9'b000000000; + parameter dyn_tx3_pma_margin_sel = 9'b000000000; + parameter dyn_tx3_pma_post_en = 5'b00000; + parameter dyn_tx3_pma_post_sel = 8'b00000000; + parameter dyn_tx3_pma_post_sign = 1'b0; + parameter dyn_tx3_pma_pre_en = 1'b0; + parameter dyn_tx3_pma_pre_sel = 4'b0000; + parameter dyn_tx3_pma_pre_sign = 1'b0; + parameter location = ""; + parameter main_clk_to_fabric_div_en = 1'b0; + parameter main_clk_to_fabric_div_mode = 1'b0; + parameter main_clk_to_fabric_sel = 1'b0; + parameter main_rclk_to_fabric_sel = 2'b00; + parameter main_use_only_usr_clock = 1'b0; + parameter pcs_ovs_en = 1'b0; + parameter pcs_ovs_mode = 1'b0; + parameter pcs_pll_lock_ppm = 3'b000; + parameter pcs_word_len = 2'b00; + parameter pll_pma_ckref_ext = 1'b0; + parameter pll_pma_cpump = 4'b0000; + parameter pll_pma_divl = 2'b00; + parameter pll_pma_divm = 1'b0; + parameter pll_pma_divn = 2'b00; + parameter pll_pma_gbx_en = 1'b0; + parameter pll_pma_int_data_len = 1'b0; + parameter pll_pma_lvds_en = 1'b0; + parameter pll_pma_lvds_mux = 1'b0; + parameter pll_pma_mux_ckref = 1'b0; + parameter rx_usrclk_use_pcs_clk_2 = 1'b0; + parameter test_mode = 2'b00; + parameter tx_usrclk_use_pcs_clk_2 = 1'b0; +endmodule + +(* blackbox *) +module NX_R5_L(A_CKEM_I, A_CKEP_I, A_CKES_I, AR_A_I32, AR_A_I31, AR_A_I30, AR_A_I29, AR_A_I28, AR_A_I27, AR_A_I26, AR_A_I25, AR_A_I24, AR_A_I23, AR_A_I22, AR_A_I21, AR_A_I20, AR_A_I19, AR_A_I18, AR_A_I17, AR_A_I16, AR_A_I15 +, AR_A_I14, AR_A_I13, AR_A_I12, AR_A_I11, AR_A_I10, AR_A_I9, AR_A_I8, AR_A_I7, AR_A_I6, AR_A_I5, AR_A_I4, AR_A_I3, AR_A_I2, AR_A_I1, AR_BU_I2, AR_BU_I1, AR_CH_I4, AR_CH_I3, AR_CH_I2, AR_CH_I1, AR_IDS_I8 +, AR_IDS_I7, AR_IDS_I6, AR_IDS_I5, AR_IDS_I4, AR_IDS_I3, AR_IDS_I2, AR_IDS_I1, AR_LE_I4, AR_LE_I3, AR_LE_I2, AR_LE_I1, AR_LK_I2, AR_LK_I1, AR_PR_I3, AR_PR_I2, AR_PR_I1, AR_RYM_I, AR_RYP_I, AR_SZ_I3, AR_SZ_I2, AR_SZ_I1 +, AR_VD_I, AT_RS_I, AW_A_I32, AW_A_I31, AW_A_I30, AW_A_I29, AW_A_I28, AW_A_I27, AW_A_I26, AW_A_I25, AW_A_I24, AW_A_I23, AW_A_I22, AW_A_I21, AW_A_I20, AW_A_I19, AW_A_I18, AW_A_I17, AW_A_I16, AW_A_I15, AW_A_I14 +, AW_A_I13, AW_A_I12, AW_A_I11, AW_A_I10, AW_A_I9, AW_A_I8, AW_A_I7, AW_A_I6, AW_A_I5, AW_A_I4, AW_A_I3, AW_A_I2, AW_A_I1, AW_BU_I2, AW_BU_I1, AW_CH_I4, AW_CH_I3, AW_CH_I2, AW_CH_I1, AW_IDS_I8, AW_IDS_I7 +, AW_IDS_I6, AW_IDS_I5, AW_IDS_I4, AW_IDS_I3, AW_IDS_I2, AW_IDS_I1, AW_LE_I4, AW_LE_I3, AW_LE_I2, AW_LE_I1, AW_LK_I2, AW_LK_I1, AW_PR_I3, AW_PR_I2, AW_PR_I1, AW_RYM_I, AW_RYP_I, AW_SZ_I3, AW_SZ_I2, AW_SZ_I1, AW_VD_I +, B_IDM_I4, B_IDM_I3, B_IDM_I2, B_IDM_I1, B_IDP_I4, B_IDP_I3, B_IDP_I2, B_IDP_I1, B_RDY_I, B_RSPM_I2, B_RSPM_I1, B_RSPP_I2, B_RSPP_I1, B_VDM_I, B_VDP_I, CDB_PW_I, CDB_RS_I, CFG_EE_I, CFG_IE_I, CFG_NM_I, CK_I +, CS_PW_I, DB_E_I, DB_NCK_I, DB_RA_I20, DB_RA_I19, DB_RA_I18, DB_RA_I17, DB_RA_I16, DB_RA_I15, DB_RA_I14, DB_RA_I13, DB_RA_I12, DB_RA_I11, DB_RA_I10, DB_RA_I9, DB_RA_I8, DB_RA_I7, DB_RA_I6, DB_RA_I5, DB_RA_I4, DB_RA_I3 +, DB_RA_I2, DB_RA_I1, DB_RAV_I, DB_SA_I20, DB_SA_I19, DB_SA_I18, DB_SA_I17, DB_SA_I16, DB_SA_I15, DB_SA_I14, DB_SA_I13, DB_SA_I12, DB_SA_I11, DB_SA_I10, DB_SA_I9, DB_SA_I8, DB_SA_I7, DB_SA_I6, DB_SA_I5, DB_SA_I4, DB_SA_I3 +, DB_SA_I2, DB_SA_I1, DB_SAV_I, DEV_E_I, DFTS_I8, DFTS_I7, DFTS_I6, DFTS_I5, DFTS_I4, DFTS_I3, DFTS_I2, DFTS_I1, E_DB_I, ERR_R_I, EVENT_I, GID_I4, GID_I3, GID_I2, GID_I1, INIT_P_I, INIT_R_I +, LOC_R_I, NCPUH_I, NET_RS_I, N_FIQ_I, N_IDE_I, N_IRQ_I, N_PRS_I, N_RS_I, N_SPRS_I, N_TRS_I, P_A_I29, P_A_I28, P_A_I27, P_A_I26, P_A_I25, P_A_I24, P_A_I23, P_A_I22, P_A_I21, P_A_I20, P_A_I19 +, P_A_I18, P_A_I17, P_A_I16, P_A_I15, P_A_I14, P_A_I13, P_A_I12, P_A_I11, P_A_I10, P_A_I9, P_A_I8, P_A_I7, P_A_I6, P_A_I5, P_A_I4, P_A_I3, P_A_I2, P_A_I1, P_ECC_I, PLVL_I, P_CK_E_I +, P_CK_I, P_E_I, PPV_BS_I20, PPV_BS_I19, PPV_BS_I18, PPV_BS_I17, PPV_BS_I16, PPV_BS_I15, PPV_BS_I14, PPV_BS_I13, PPV_BS_I12, PPV_BS_I11, PPV_BS_I10, PPV_BS_I9, PPV_BS_I8, PPV_BS_I7, PPV_BS_I6, PPV_BS_I5, PPV_BS_I4, PPV_BS_I3, PPV_BS_I2 +, PPV_BS_I1, PPV_SZ_I5, PPV_SZ_I4, PPV_SZ_I3, PPV_SZ_I2, PPV_SZ_I1, PPX_BS_I20, PPX_BS_I19, PPX_BS_I18, PPX_BS_I17, PPX_BS_I16, PPX_BS_I15, PPX_BS_I14, PPX_BS_I13, PPX_BS_I12, PPX_BS_I11, PPX_BS_I10, PPX_BS_I9, PPX_BS_I8, PPX_BS_I7, PPX_BS_I6 +, PPX_BS_I5, PPX_BS_I4, PPX_BS_I3, PPX_BS_I2, PPX_BS_I1, PPX_SZ_I5, PPX_SZ_I4, PPX_SZ_I3, PPX_SZ_I2, PPX_SZ_I1, P_RS_I, P_SEL_I, PW_D_I32, PW_D_I31, PW_D_I30, PW_D_I29, PW_D_I28, PW_D_I27, PW_D_I26, PW_D_I25, PW_D_I24 +, PW_D_I23, PW_D_I22, PW_D_I21, PW_D_I20, PW_D_I19, PW_D_I18, PW_D_I17, PW_D_I16, PW_D_I15, PW_D_I14, PW_D_I13, PW_D_I12, PW_D_I11, PW_D_I10, PW_D_I9, PW_D_I8, PW_D_I7, PW_D_I6, PW_D_I5, PW_D_I4, PW_D_I3 +, PW_D_I2, PW_D_I1, PW_I, RAMCTL_I8, RAMCTL_I7, RAMCTL_I6, RAMCTL_I5, RAMCTL_I4, RAMCTL_I3, RAMCTL_I2, RAMCTL_I1, R_DM_I64, R_DM_I63, R_DM_I62, R_DM_I61, R_DM_I60, R_DM_I59, R_DM_I58, R_DM_I57, R_DM_I56, R_DM_I55 +, R_DM_I54, R_DM_I53, R_DM_I52, R_DM_I51, R_DM_I50, R_DM_I49, R_DM_I48, R_DM_I47, R_DM_I46, R_DM_I45, R_DM_I44, R_DM_I43, R_DM_I42, R_DM_I41, R_DM_I40, R_DM_I39, R_DM_I38, R_DM_I37, R_DM_I36, R_DM_I35, R_DM_I34 +, R_DM_I33, R_DM_I32, R_DM_I31, R_DM_I30, R_DM_I29, R_DM_I28, R_DM_I27, R_DM_I26, R_DM_I25, R_DM_I24, R_DM_I23, R_DM_I22, R_DM_I21, R_DM_I20, R_DM_I19, R_DM_I18, R_DM_I17, R_DM_I16, R_DM_I15, R_DM_I14, R_DM_I13 +, R_DM_I12, R_DM_I11, R_DM_I10, R_DM_I9, R_DM_I8, R_DM_I7, R_DM_I6, R_DM_I5, R_DM_I4, R_DM_I3, R_DM_I2, R_DM_I1, R_DP_I32, R_DP_I31, R_DP_I30, R_DP_I29, R_DP_I28, R_DP_I27, R_DP_I26, R_DP_I25, R_DP_I24 +, R_DP_I23, R_DP_I22, R_DP_I21, R_DP_I20, R_DP_I19, R_DP_I18, R_DP_I17, R_DP_I16, R_DP_I15, R_DP_I14, R_DP_I13, R_DP_I12, R_DP_I11, R_DP_I10, R_DP_I9, R_DP_I8, R_DP_I7, R_DP_I6, R_DP_I5, R_DP_I4, R_DP_I3 +, R_DP_I2, R_DP_I1, R_IDM_I4, R_IDM_I3, R_IDM_I2, R_IDM_I1, R_IDP_I4, R_IDP_I3, R_IDP_I2, R_IDP_I1, R_LSTM_I, R_LSTP_I, R_RDY_I, R_RSPM_I2, R_RSPM_I1, R_RSPP_I2, R_RSPP_I1, RS_BYP_I, R_VDM_I, R_VDP_I, SE_I +, SW_CK_I, SW_DI_I, T_DI_I, TE_INI_I, VINI_I, W_D_I64, W_D_I63, W_D_I62, W_D_I61, W_D_I60, W_D_I59, W_D_I58, W_D_I57, W_D_I56, W_D_I55, W_D_I54, W_D_I53, W_D_I52, W_D_I51, W_D_I50, W_D_I49 +, W_D_I48, W_D_I47, W_D_I46, W_D_I45, W_D_I44, W_D_I43, W_D_I42, W_D_I41, W_D_I40, W_D_I39, W_D_I38, W_D_I37, W_D_I36, W_D_I35, W_D_I34, W_D_I33, W_D_I32, W_D_I31, W_D_I30, W_D_I29, W_D_I28 +, W_D_I27, W_D_I26, W_D_I25, W_D_I24, W_D_I23, W_D_I22, W_D_I21, W_D_I20, W_D_I19, W_D_I18, W_D_I17, W_D_I16, W_D_I15, W_D_I14, W_D_I13, W_D_I12, W_D_I11, W_D_I10, W_D_I9, W_D_I8, W_D_I7 +, W_D_I6, W_D_I5, W_D_I4, W_D_I3, W_D_I2, W_D_I1, W_IDS_I8, W_IDS_I7, W_IDS_I6, W_IDS_I5, W_IDS_I4, W_IDS_I3, W_IDS_I2, W_IDS_I1, W_LST_I, W_RYM_I, W_RYP_I, W_SBS_I8, W_SBS_I7, W_SBS_I6, W_SBS_I5 +, W_SBS_I4, W_SBS_I3, W_SBS_I2, W_SBS_I1, W_VD_I, AR_AM_O32, AR_AM_O31, AR_AM_O30, AR_AM_O29, AR_AM_O28, AR_AM_O27, AR_AM_O26, AR_AM_O25, AR_AM_O24, AR_AM_O23, AR_AM_O22, AR_AM_O21, AR_AM_O20, AR_AM_O19, AR_AM_O18, AR_AM_O17 +, AR_AM_O16, AR_AM_O15, AR_AM_O14, AR_AM_O13, AR_AM_O12, AR_AM_O11, AR_AM_O10, AR_AM_O9, AR_AM_O8, AR_AM_O7, AR_AM_O6, AR_AM_O5, AR_AM_O4, AR_AM_O3, AR_AM_O2, AR_AM_O1, AR_AP_O32, AR_AP_O31, AR_AP_O30, AR_AP_O29, AR_AP_O28 +, AR_AP_O27, AR_AP_O26, AR_AP_O25, AR_AP_O24, AR_AP_O23, AR_AP_O22, AR_AP_O21, AR_AP_O20, AR_AP_O19, AR_AP_O18, AR_AP_O17, AR_AP_O16, AR_AP_O15, AR_AP_O14, AR_AP_O13, AR_AP_O12, AR_AP_O11, AR_AP_O10, AR_AP_O9, AR_AP_O8, AR_AP_O7 +, AR_AP_O6, AR_AP_O5, AR_AP_O4, AR_AP_O3, AR_AP_O2, AR_AP_O1, AR_BUM_O2, AR_BUM_O1, AR_BUP_O2, AR_BUP_O1, AR_CHM_O4, AR_CHM_O3, AR_CHM_O2, AR_CHM_O1, AR_CHP_O4, AR_CHP_O3, AR_CHP_O2, AR_CHP_O1, AR_IDM_O4, AR_IDM_O3, AR_IDM_O2 +, AR_IDM_O1, AR_IDP_O4, AR_IDP_O3, AR_IDP_O2, AR_IDP_O1, AR_INM_O4, AR_INM_O3, AR_INM_O2, AR_INM_O1, AR_LEM_O4, AR_LEM_O3, AR_LEM_O2, AR_LEM_O1, AR_LEP_O4, AR_LEP_O3, AR_LEP_O2, AR_LEP_O1, AR_LKM_O2, AR_LKM_O1, AR_LKP_O2, AR_LKP_O1 +, AR_PRM_O3, AR_PRM_O2, AR_PRM_O1, AR_PRP_O3, AR_PRP_O2, AR_PRP_O1, AR_RDY_O, AR_SHM_O, AR_SZM_O3, AR_SZM_O2, AR_SZM_O1, AR_SZP_O3, AR_SZP_O2, AR_SZP_O1, AR_VDM_O, AR_VDP_O, AW_AM_O32, AW_AM_O31, AW_AM_O30, AW_AM_O29, AW_AM_O28 +, AW_AM_O27, AW_AM_O26, AW_AM_O25, AW_AM_O24, AW_AM_O23, AW_AM_O22, AW_AM_O21, AW_AM_O20, AW_AM_O19, AW_AM_O18, AW_AM_O17, AW_AM_O16, AW_AM_O15, AW_AM_O14, AW_AM_O13, AW_AM_O12, AW_AM_O11, AW_AM_O10, AW_AM_O9, AW_AM_O8, AW_AM_O7 +, AW_AM_O6, AW_AM_O5, AW_AM_O4, AW_AM_O3, AW_AM_O2, AW_AM_O1, AW_AP_O32, AW_AP_O31, AW_AP_O30, AW_AP_O29, AW_AP_O28, AW_AP_O27, AW_AP_O26, AW_AP_O25, AW_AP_O24, AW_AP_O23, AW_AP_O22, AW_AP_O21, AW_AP_O20, AW_AP_O19, AW_AP_O18 +, AW_AP_O17, AW_AP_O16, AW_AP_O15, AW_AP_O14, AW_AP_O13, AW_AP_O12, AW_AP_O11, AW_AP_O10, AW_AP_O9, AW_AP_O8, AW_AP_O7, AW_AP_O6, AW_AP_O5, AW_AP_O4, AW_AP_O3, AW_AP_O2, AW_AP_O1, AW_BUM_O2, AW_BUM_O1, AW_BUP_O2, AW_BUP_O1 +, AW_CHM_O4, AW_CHM_O3, AW_CHM_O2, AW_CHM_O1, AW_CHP_O4, AW_CHP_O3, AW_CHP_O2, AW_CHP_O1, AW_IDM_O4, AW_IDM_O3, AW_IDM_O2, AW_IDM_O1, AW_IDP_O4, AW_IDP_O3, AW_IDP_O2, AW_IDP_O1, AW_INM_O4, AW_INM_O3, AW_INM_O2, AW_INM_O1, AW_LEM_O4 +, AW_LEM_O3, AW_LEM_O2, AW_LEM_O1, AW_LEP_O4, AW_LEP_O3, AW_LEP_O2, AW_LEP_O1, AW_LKM_O2, AW_LKM_O1, AW_LKP_O2, AW_LKP_O1, AW_PRM_O3, AW_PRM_O2, AW_PRM_O1, AW_PRP_O3, AW_PRP_O2, AW_PRP_O1, AW_RDY_O, AW_SHM_O, AW_SZM_O3, AW_SZM_O2 +, AW_SZM_O1, AW_SZP_O3, AW_SZP_O2, AW_SZP_O1, AW_VDM_O, AW_VDP_O, B_IDS_O8, B_IDS_O7, B_IDS_O6, B_IDS_O5, B_IDS_O4, B_IDS_O3, B_IDS_O2, B_IDS_O1, B_RDYM_O, B_RDYP_O, B_RSP_O2, B_RSP_O1, B_VD_O, CDB_PW_O, CDB_RS_O +, COM_RX_O, COM_TX_O, CS_PW_O, DB_ACK_O, DB_NPD_O, DB_RS_O, DFTS_O8, DFTS_O7, DFTS_O6, DFTS_O5, DFTS_O4, DFTS_O3, DFTS_O2, DFTS_O1, ET_ASC_O8, ET_ASC_O7, ET_ASC_O6, ET_ASC_O5, ET_ASC_O4, ET_ASC_O3, ET_ASC_O2 +, ET_ASC_O1, ET_E_O, ET_EXT_O2, ET_EXT_O1, EVENT_O, FP_DZC_O, FP_IDC_O, FP_IOC_O, FP_IXC_O, FP_OFC_O, FP_UFC_O, JTAG_O, N_CKST_O, N_PMU_O, N_TDO_O, N_VFIQ_O, N_VIRQ_O, N_VRST_O, N_EPST_O, N_IPST_O, P_RD_O32 +, P_RD_O31, P_RD_O30, P_RD_O29, P_RD_O28, P_RD_O27, P_RD_O26, P_RD_O25, P_RD_O24, P_RD_O23, P_RD_O22, P_RD_O21, P_RD_O20, P_RD_O19, P_RD_O18, P_RD_O17, P_RD_O16, P_RD_O15, P_RD_O14, P_RD_O13, P_RD_O12, P_RD_O11 +, P_RD_O10, P_RD_O9, P_RD_O8, P_RD_O7, P_RD_O6, P_RD_O5, P_RD_O4, P_RD_O3, P_RD_O2, P_RD_O1, P_RDY_O, P_VER_O, RD_O64, RD_O63, RD_O62, RD_O61, RD_O60, RD_O59, RD_O58, RD_O57, RD_O56 +, RD_O55, RD_O54, RD_O53, RD_O52, RD_O51, RD_O50, RD_O49, RD_O48, RD_O47, RD_O46, RD_O45, RD_O44, RD_O43, RD_O42, RD_O41, RD_O40, RD_O39, RD_O38, RD_O37, RD_O36, RD_O35 +, RD_O34, RD_O33, RD_O32, RD_O31, RD_O30, RD_O29, RD_O28, RD_O27, RD_O26, RD_O25, RD_O24, RD_O23, RD_O22, RD_O21, RD_O20, RD_O19, RD_O18, RD_O17, RD_O16, RD_O15, RD_O14 +, RD_O13, RD_O12, RD_O11, RD_O10, RD_O9, RD_O8, RD_O7, RD_O6, RD_O5, RD_O4, RD_O3, RD_O2, RD_O1, R_IDS_O8, R_IDS_O7, R_IDS_O6, R_IDS_O5, R_IDS_O4, R_IDS_O3, R_IDS_O2, R_IDS_O1 +, R_LST_O, R_RDYM_O, R_RDYP_O, R_RSP_O2, R_RSP_O1, R_VD_O, SWDO_O, SWDO_E_O, TDO_O, T_CK_O, T_CTL_O, T_DATA_O32, T_DATA_O31, T_DATA_O30, T_DATA_O29, T_DATA_O28, T_DATA_O27, T_DATA_O26, T_DATA_O25, T_DATA_O24, T_DATA_O23 +, T_DATA_O22, T_DATA_O21, T_DATA_O20, T_DATA_O19, T_DATA_O18, T_DATA_O17, T_DATA_O16, T_DATA_O15, T_DATA_O14, T_DATA_O13, T_DATA_O12, T_DATA_O11, T_DATA_O10, T_DATA_O9, T_DATA_O8, T_DATA_O7, T_DATA_O6, T_DATA_O5, T_DATA_O4, T_DATA_O3, T_DATA_O2 +, T_DATA_O1, W_DM_O64, W_DM_O63, W_DM_O62, W_DM_O61, W_DM_O60, W_DM_O59, W_DM_O58, W_DM_O57, W_DM_O56, W_DM_O55, W_DM_O54, W_DM_O53, W_DM_O52, W_DM_O51, W_DM_O50, W_DM_O49, W_DM_O48, W_DM_O47, W_DM_O46, W_DM_O45 +, W_DM_O44, W_DM_O43, W_DM_O42, W_DM_O41, W_DM_O40, W_DM_O39, W_DM_O38, W_DM_O37, W_DM_O36, W_DM_O35, W_DM_O34, W_DM_O33, W_DM_O32, W_DM_O31, W_DM_O30, W_DM_O29, W_DM_O28, W_DM_O27, W_DM_O26, W_DM_O25, W_DM_O24 +, W_DM_O23, W_DM_O22, W_DM_O21, W_DM_O20, W_DM_O19, W_DM_O18, W_DM_O17, W_DM_O16, W_DM_O15, W_DM_O14, W_DM_O13, W_DM_O12, W_DM_O11, W_DM_O10, W_DM_O9, W_DM_O8, W_DM_O7, W_DM_O6, W_DM_O5, W_DM_O4, W_DM_O3 +, W_DM_O2, W_DM_O1, W_DP_O32, W_DP_O31, W_DP_O30, W_DP_O29, W_DP_O28, W_DP_O27, W_DP_O26, W_DP_O25, W_DP_O24, W_DP_O23, W_DP_O22, W_DP_O21, W_DP_O20, W_DP_O19, W_DP_O18, W_DP_O17, W_DP_O16, W_DP_O15, W_DP_O14 +, W_DP_O13, W_DP_O12, W_DP_O11, W_DP_O10, W_DP_O9, W_DP_O8, W_DP_O7, W_DP_O6, W_DP_O5, W_DP_O4, W_DP_O3, W_DP_O2, W_DP_O1, W_IDM_O4, W_IDM_O3, W_IDM_O2, W_IDM_O1, W_IDP_O4, W_IDP_O3, W_IDP_O2, W_IDP_O1 +, W_LSTM_O, W_LSTP_O, W_RDY_O, W_SBM_O8, W_SBM_O7, W_SBM_O6, W_SBM_O5, W_SBM_O4, W_SBM_O3, W_SBM_O2, W_SBM_O1, W_SBP_O4, W_SBP_O3, W_SBP_O2, W_SBP_O1, W_VDM_O, W_VDP_O); + output AR_AM_O1; + output AR_AM_O10; + output AR_AM_O11; + output AR_AM_O12; + output AR_AM_O13; + output AR_AM_O14; + output AR_AM_O15; + output AR_AM_O16; + output AR_AM_O17; + output AR_AM_O18; + output AR_AM_O19; + output AR_AM_O2; + output AR_AM_O20; + output AR_AM_O21; + output AR_AM_O22; + output AR_AM_O23; + output AR_AM_O24; + output AR_AM_O25; + output AR_AM_O26; + output AR_AM_O27; + output AR_AM_O28; + output AR_AM_O29; + output AR_AM_O3; + output AR_AM_O30; + output AR_AM_O31; + output AR_AM_O32; + output AR_AM_O4; + output AR_AM_O5; + output AR_AM_O6; + output AR_AM_O7; + output AR_AM_O8; + output AR_AM_O9; + output AR_AP_O1; + output AR_AP_O10; + output AR_AP_O11; + output AR_AP_O12; + output AR_AP_O13; + output AR_AP_O14; + output AR_AP_O15; + output AR_AP_O16; + output AR_AP_O17; + output AR_AP_O18; + output AR_AP_O19; + output AR_AP_O2; + output AR_AP_O20; + output AR_AP_O21; + output AR_AP_O22; + output AR_AP_O23; + output AR_AP_O24; + output AR_AP_O25; + output AR_AP_O26; + output AR_AP_O27; + output AR_AP_O28; + output AR_AP_O29; + output AR_AP_O3; + output AR_AP_O30; + output AR_AP_O31; + output AR_AP_O32; + output AR_AP_O4; + output AR_AP_O5; + output AR_AP_O6; + output AR_AP_O7; + output AR_AP_O8; + output AR_AP_O9; + input AR_A_I1; + input AR_A_I10; + input AR_A_I11; + input AR_A_I12; + input AR_A_I13; + input AR_A_I14; + input AR_A_I15; + input AR_A_I16; + input AR_A_I17; + input AR_A_I18; + input AR_A_I19; + input AR_A_I2; + input AR_A_I20; + input AR_A_I21; + input AR_A_I22; + input AR_A_I23; + input AR_A_I24; + input AR_A_I25; + input AR_A_I26; + input AR_A_I27; + input AR_A_I28; + input AR_A_I29; + input AR_A_I3; + input AR_A_I30; + input AR_A_I31; + input AR_A_I32; + input AR_A_I4; + input AR_A_I5; + input AR_A_I6; + input AR_A_I7; + input AR_A_I8; + input AR_A_I9; + output AR_BUM_O1; + output AR_BUM_O2; + output AR_BUP_O1; + output AR_BUP_O2; + input AR_BU_I1; + input AR_BU_I2; + output AR_CHM_O1; + output AR_CHM_O2; + output AR_CHM_O3; + output AR_CHM_O4; + output AR_CHP_O1; + output AR_CHP_O2; + output AR_CHP_O3; + output AR_CHP_O4; + input AR_CH_I1; + input AR_CH_I2; + input AR_CH_I3; + input AR_CH_I4; + output AR_IDM_O1; + output AR_IDM_O2; + output AR_IDM_O3; + output AR_IDM_O4; + output AR_IDP_O1; + output AR_IDP_O2; + output AR_IDP_O3; + output AR_IDP_O4; + input AR_IDS_I1; + input AR_IDS_I2; + input AR_IDS_I3; + input AR_IDS_I4; + input AR_IDS_I5; + input AR_IDS_I6; + input AR_IDS_I7; + input AR_IDS_I8; + output AR_INM_O1; + output AR_INM_O2; + output AR_INM_O3; + output AR_INM_O4; + output AR_LEM_O1; + output AR_LEM_O2; + output AR_LEM_O3; + output AR_LEM_O4; + output AR_LEP_O1; + output AR_LEP_O2; + output AR_LEP_O3; + output AR_LEP_O4; + input AR_LE_I1; + input AR_LE_I2; + input AR_LE_I3; + input AR_LE_I4; + output AR_LKM_O1; + output AR_LKM_O2; + output AR_LKP_O1; + output AR_LKP_O2; + input AR_LK_I1; + input AR_LK_I2; + output AR_PRM_O1; + output AR_PRM_O2; + output AR_PRM_O3; + output AR_PRP_O1; + output AR_PRP_O2; + output AR_PRP_O3; + input AR_PR_I1; + input AR_PR_I2; + input AR_PR_I3; + output AR_RDY_O; + input AR_RYM_I; + input AR_RYP_I; + output AR_SHM_O; + output AR_SZM_O1; + output AR_SZM_O2; + output AR_SZM_O3; + output AR_SZP_O1; + output AR_SZP_O2; + output AR_SZP_O3; + input AR_SZ_I1; + input AR_SZ_I2; + input AR_SZ_I3; + output AR_VDM_O; + output AR_VDP_O; + input AR_VD_I; + input AT_RS_I; + output AW_AM_O1; + output AW_AM_O10; + output AW_AM_O11; + output AW_AM_O12; + output AW_AM_O13; + output AW_AM_O14; + output AW_AM_O15; + output AW_AM_O16; + output AW_AM_O17; + output AW_AM_O18; + output AW_AM_O19; + output AW_AM_O2; + output AW_AM_O20; + output AW_AM_O21; + output AW_AM_O22; + output AW_AM_O23; + output AW_AM_O24; + output AW_AM_O25; + output AW_AM_O26; + output AW_AM_O27; + output AW_AM_O28; + output AW_AM_O29; + output AW_AM_O3; + output AW_AM_O30; + output AW_AM_O31; + output AW_AM_O32; + output AW_AM_O4; + output AW_AM_O5; + output AW_AM_O6; + output AW_AM_O7; + output AW_AM_O8; + output AW_AM_O9; + output AW_AP_O1; + output AW_AP_O10; + output AW_AP_O11; + output AW_AP_O12; + output AW_AP_O13; + output AW_AP_O14; + output AW_AP_O15; + output AW_AP_O16; + output AW_AP_O17; + output AW_AP_O18; + output AW_AP_O19; + output AW_AP_O2; + output AW_AP_O20; + output AW_AP_O21; + output AW_AP_O22; + output AW_AP_O23; + output AW_AP_O24; + output AW_AP_O25; + output AW_AP_O26; + output AW_AP_O27; + output AW_AP_O28; + output AW_AP_O29; + output AW_AP_O3; + output AW_AP_O30; + output AW_AP_O31; + output AW_AP_O32; + output AW_AP_O4; + output AW_AP_O5; + output AW_AP_O6; + output AW_AP_O7; + output AW_AP_O8; + output AW_AP_O9; + input AW_A_I1; + input AW_A_I10; + input AW_A_I11; + input AW_A_I12; + input AW_A_I13; + input AW_A_I14; + input AW_A_I15; + input AW_A_I16; + input AW_A_I17; + input AW_A_I18; + input AW_A_I19; + input AW_A_I2; + input AW_A_I20; + input AW_A_I21; + input AW_A_I22; + input AW_A_I23; + input AW_A_I24; + input AW_A_I25; + input AW_A_I26; + input AW_A_I27; + input AW_A_I28; + input AW_A_I29; + input AW_A_I3; + input AW_A_I30; + input AW_A_I31; + input AW_A_I32; + input AW_A_I4; + input AW_A_I5; + input AW_A_I6; + input AW_A_I7; + input AW_A_I8; + input AW_A_I9; + output AW_BUM_O1; + output AW_BUM_O2; + output AW_BUP_O1; + output AW_BUP_O2; + input AW_BU_I1; + input AW_BU_I2; + output AW_CHM_O1; + output AW_CHM_O2; + output AW_CHM_O3; + output AW_CHM_O4; + output AW_CHP_O1; + output AW_CHP_O2; + output AW_CHP_O3; + output AW_CHP_O4; + input AW_CH_I1; + input AW_CH_I2; + input AW_CH_I3; + input AW_CH_I4; + output AW_IDM_O1; + output AW_IDM_O2; + output AW_IDM_O3; + output AW_IDM_O4; + output AW_IDP_O1; + output AW_IDP_O2; + output AW_IDP_O3; + output AW_IDP_O4; + input AW_IDS_I1; + input AW_IDS_I2; + input AW_IDS_I3; + input AW_IDS_I4; + input AW_IDS_I5; + input AW_IDS_I6; + input AW_IDS_I7; + input AW_IDS_I8; + output AW_INM_O1; + output AW_INM_O2; + output AW_INM_O3; + output AW_INM_O4; + output AW_LEM_O1; + output AW_LEM_O2; + output AW_LEM_O3; + output AW_LEM_O4; + output AW_LEP_O1; + output AW_LEP_O2; + output AW_LEP_O3; + output AW_LEP_O4; + input AW_LE_I1; + input AW_LE_I2; + input AW_LE_I3; + input AW_LE_I4; + output AW_LKM_O1; + output AW_LKM_O2; + output AW_LKP_O1; + output AW_LKP_O2; + input AW_LK_I1; + input AW_LK_I2; + output AW_PRM_O1; + output AW_PRM_O2; + output AW_PRM_O3; + output AW_PRP_O1; + output AW_PRP_O2; + output AW_PRP_O3; + input AW_PR_I1; + input AW_PR_I2; + input AW_PR_I3; + output AW_RDY_O; + input AW_RYM_I; + input AW_RYP_I; + output AW_SHM_O; + output AW_SZM_O1; + output AW_SZM_O2; + output AW_SZM_O3; + output AW_SZP_O1; + output AW_SZP_O2; + output AW_SZP_O3; + input AW_SZ_I1; + input AW_SZ_I2; + input AW_SZ_I3; + output AW_VDM_O; + output AW_VDP_O; + input AW_VD_I; + input A_CKEM_I; + input A_CKEP_I; + input A_CKES_I; + input B_IDM_I1; + input B_IDM_I2; + input B_IDM_I3; + input B_IDM_I4; + input B_IDP_I1; + input B_IDP_I2; + input B_IDP_I3; + input B_IDP_I4; + output B_IDS_O1; + output B_IDS_O2; + output B_IDS_O3; + output B_IDS_O4; + output B_IDS_O5; + output B_IDS_O6; + output B_IDS_O7; + output B_IDS_O8; + output B_RDYM_O; + output B_RDYP_O; + input B_RDY_I; + input B_RSPM_I1; + input B_RSPM_I2; + input B_RSPP_I1; + input B_RSPP_I2; + output B_RSP_O1; + output B_RSP_O2; + input B_VDM_I; + input B_VDP_I; + output B_VD_O; + input CDB_PW_I; + output CDB_PW_O; + input CDB_RS_I; + output CDB_RS_O; + input CFG_EE_I; + input CFG_IE_I; + input CFG_NM_I; + input CK_I; + output COM_RX_O; + output COM_TX_O; + input CS_PW_I; + output CS_PW_O; + output DB_ACK_O; + input DB_E_I; + input DB_NCK_I; + output DB_NPD_O; + input DB_RAV_I; + input DB_RA_I1; + input DB_RA_I10; + input DB_RA_I11; + input DB_RA_I12; + input DB_RA_I13; + input DB_RA_I14; + input DB_RA_I15; + input DB_RA_I16; + input DB_RA_I17; + input DB_RA_I18; + input DB_RA_I19; + input DB_RA_I2; + input DB_RA_I20; + input DB_RA_I3; + input DB_RA_I4; + input DB_RA_I5; + input DB_RA_I6; + input DB_RA_I7; + input DB_RA_I8; + input DB_RA_I9; + output DB_RS_O; + input DB_SAV_I; + input DB_SA_I1; + input DB_SA_I10; + input DB_SA_I11; + input DB_SA_I12; + input DB_SA_I13; + input DB_SA_I14; + input DB_SA_I15; + input DB_SA_I16; + input DB_SA_I17; + input DB_SA_I18; + input DB_SA_I19; + input DB_SA_I2; + input DB_SA_I20; + input DB_SA_I3; + input DB_SA_I4; + input DB_SA_I5; + input DB_SA_I6; + input DB_SA_I7; + input DB_SA_I8; + input DB_SA_I9; + input DEV_E_I; + input DFTS_I1; + input DFTS_I2; + input DFTS_I3; + input DFTS_I4; + input DFTS_I5; + input DFTS_I6; + input DFTS_I7; + input DFTS_I8; + output DFTS_O1; + output DFTS_O2; + output DFTS_O3; + output DFTS_O4; + output DFTS_O5; + output DFTS_O6; + output DFTS_O7; + output DFTS_O8; + input ERR_R_I; + output ET_ASC_O1; + output ET_ASC_O2; + output ET_ASC_O3; + output ET_ASC_O4; + output ET_ASC_O5; + output ET_ASC_O6; + output ET_ASC_O7; + output ET_ASC_O8; + output ET_EXT_O1; + output ET_EXT_O2; + output ET_E_O; + input EVENT_I; + output EVENT_O; + input E_DB_I; + output FP_DZC_O; + output FP_IDC_O; + output FP_IOC_O; + output FP_IXC_O; + output FP_OFC_O; + output FP_UFC_O; + input GID_I1; + input GID_I2; + input GID_I3; + input GID_I4; + input INIT_P_I; + input INIT_R_I; + output JTAG_O; + input LOC_R_I; + input NCPUH_I; + input NET_RS_I; + output N_CKST_O; + output N_EPST_O; + input N_FIQ_I; + input N_IDE_I; + output N_IPST_O; + input N_IRQ_I; + output N_PMU_O; + input N_PRS_I; + input N_RS_I; + input N_SPRS_I; + output N_TDO_O; + input N_TRS_I; + output N_VFIQ_O; + output N_VIRQ_O; + output N_VRST_O; + input PLVL_I; + input PPV_BS_I1; + input PPV_BS_I10; + input PPV_BS_I11; + input PPV_BS_I12; + input PPV_BS_I13; + input PPV_BS_I14; + input PPV_BS_I15; + input PPV_BS_I16; + input PPV_BS_I17; + input PPV_BS_I18; + input PPV_BS_I19; + input PPV_BS_I2; + input PPV_BS_I20; + input PPV_BS_I3; + input PPV_BS_I4; + input PPV_BS_I5; + input PPV_BS_I6; + input PPV_BS_I7; + input PPV_BS_I8; + input PPV_BS_I9; + input PPV_SZ_I1; + input PPV_SZ_I2; + input PPV_SZ_I3; + input PPV_SZ_I4; + input PPV_SZ_I5; + input PPX_BS_I1; + input PPX_BS_I10; + input PPX_BS_I11; + input PPX_BS_I12; + input PPX_BS_I13; + input PPX_BS_I14; + input PPX_BS_I15; + input PPX_BS_I16; + input PPX_BS_I17; + input PPX_BS_I18; + input PPX_BS_I19; + input PPX_BS_I2; + input PPX_BS_I20; + input PPX_BS_I3; + input PPX_BS_I4; + input PPX_BS_I5; + input PPX_BS_I6; + input PPX_BS_I7; + input PPX_BS_I8; + input PPX_BS_I9; + input PPX_SZ_I1; + input PPX_SZ_I2; + input PPX_SZ_I3; + input PPX_SZ_I4; + input PPX_SZ_I5; + input PW_D_I1; + input PW_D_I10; + input PW_D_I11; + input PW_D_I12; + input PW_D_I13; + input PW_D_I14; + input PW_D_I15; + input PW_D_I16; + input PW_D_I17; + input PW_D_I18; + input PW_D_I19; + input PW_D_I2; + input PW_D_I20; + input PW_D_I21; + input PW_D_I22; + input PW_D_I23; + input PW_D_I24; + input PW_D_I25; + input PW_D_I26; + input PW_D_I27; + input PW_D_I28; + input PW_D_I29; + input PW_D_I3; + input PW_D_I30; + input PW_D_I31; + input PW_D_I32; + input PW_D_I4; + input PW_D_I5; + input PW_D_I6; + input PW_D_I7; + input PW_D_I8; + input PW_D_I9; + input PW_I; + input P_A_I1; + input P_A_I10; + input P_A_I11; + input P_A_I12; + input P_A_I13; + input P_A_I14; + input P_A_I15; + input P_A_I16; + input P_A_I17; + input P_A_I18; + input P_A_I19; + input P_A_I2; + input P_A_I20; + input P_A_I21; + input P_A_I22; + input P_A_I23; + input P_A_I24; + input P_A_I25; + input P_A_I26; + input P_A_I27; + input P_A_I28; + input P_A_I29; + input P_A_I3; + input P_A_I4; + input P_A_I5; + input P_A_I6; + input P_A_I7; + input P_A_I8; + input P_A_I9; + input P_CK_E_I; + input P_CK_I; + input P_ECC_I; + input P_E_I; + output P_RDY_O; + output P_RD_O1; + output P_RD_O10; + output P_RD_O11; + output P_RD_O12; + output P_RD_O13; + output P_RD_O14; + output P_RD_O15; + output P_RD_O16; + output P_RD_O17; + output P_RD_O18; + output P_RD_O19; + output P_RD_O2; + output P_RD_O20; + output P_RD_O21; + output P_RD_O22; + output P_RD_O23; + output P_RD_O24; + output P_RD_O25; + output P_RD_O26; + output P_RD_O27; + output P_RD_O28; + output P_RD_O29; + output P_RD_O3; + output P_RD_O30; + output P_RD_O31; + output P_RD_O32; + output P_RD_O4; + output P_RD_O5; + output P_RD_O6; + output P_RD_O7; + output P_RD_O8; + output P_RD_O9; + input P_RS_I; + input P_SEL_I; + output P_VER_O; + input RAMCTL_I1; + input RAMCTL_I2; + input RAMCTL_I3; + input RAMCTL_I4; + input RAMCTL_I5; + input RAMCTL_I6; + input RAMCTL_I7; + input RAMCTL_I8; + output RD_O1; + output RD_O10; + output RD_O11; + output RD_O12; + output RD_O13; + output RD_O14; + output RD_O15; + output RD_O16; + output RD_O17; + output RD_O18; + output RD_O19; + output RD_O2; + output RD_O20; + output RD_O21; + output RD_O22; + output RD_O23; + output RD_O24; + output RD_O25; + output RD_O26; + output RD_O27; + output RD_O28; + output RD_O29; + output RD_O3; + output RD_O30; + output RD_O31; + output RD_O32; + output RD_O33; + output RD_O34; + output RD_O35; + output RD_O36; + output RD_O37; + output RD_O38; + output RD_O39; + output RD_O4; + output RD_O40; + output RD_O41; + output RD_O42; + output RD_O43; + output RD_O44; + output RD_O45; + output RD_O46; + output RD_O47; + output RD_O48; + output RD_O49; + output RD_O5; + output RD_O50; + output RD_O51; + output RD_O52; + output RD_O53; + output RD_O54; + output RD_O55; + output RD_O56; + output RD_O57; + output RD_O58; + output RD_O59; + output RD_O6; + output RD_O60; + output RD_O61; + output RD_O62; + output RD_O63; + output RD_O64; + output RD_O7; + output RD_O8; + output RD_O9; + input RS_BYP_I; + input R_DM_I1; + input R_DM_I10; + input R_DM_I11; + input R_DM_I12; + input R_DM_I13; + input R_DM_I14; + input R_DM_I15; + input R_DM_I16; + input R_DM_I17; + input R_DM_I18; + input R_DM_I19; + input R_DM_I2; + input R_DM_I20; + input R_DM_I21; + input R_DM_I22; + input R_DM_I23; + input R_DM_I24; + input R_DM_I25; + input R_DM_I26; + input R_DM_I27; + input R_DM_I28; + input R_DM_I29; + input R_DM_I3; + input R_DM_I30; + input R_DM_I31; + input R_DM_I32; + input R_DM_I33; + input R_DM_I34; + input R_DM_I35; + input R_DM_I36; + input R_DM_I37; + input R_DM_I38; + input R_DM_I39; + input R_DM_I4; + input R_DM_I40; + input R_DM_I41; + input R_DM_I42; + input R_DM_I43; + input R_DM_I44; + input R_DM_I45; + input R_DM_I46; + input R_DM_I47; + input R_DM_I48; + input R_DM_I49; + input R_DM_I5; + input R_DM_I50; + input R_DM_I51; + input R_DM_I52; + input R_DM_I53; + input R_DM_I54; + input R_DM_I55; + input R_DM_I56; + input R_DM_I57; + input R_DM_I58; + input R_DM_I59; + input R_DM_I6; + input R_DM_I60; + input R_DM_I61; + input R_DM_I62; + input R_DM_I63; + input R_DM_I64; + input R_DM_I7; + input R_DM_I8; + input R_DM_I9; + input R_DP_I1; + input R_DP_I10; + input R_DP_I11; + input R_DP_I12; + input R_DP_I13; + input R_DP_I14; + input R_DP_I15; + input R_DP_I16; + input R_DP_I17; + input R_DP_I18; + input R_DP_I19; + input R_DP_I2; + input R_DP_I20; + input R_DP_I21; + input R_DP_I22; + input R_DP_I23; + input R_DP_I24; + input R_DP_I25; + input R_DP_I26; + input R_DP_I27; + input R_DP_I28; + input R_DP_I29; + input R_DP_I3; + input R_DP_I30; + input R_DP_I31; + input R_DP_I32; + input R_DP_I4; + input R_DP_I5; + input R_DP_I6; + input R_DP_I7; + input R_DP_I8; + input R_DP_I9; + input R_IDM_I1; + input R_IDM_I2; + input R_IDM_I3; + input R_IDM_I4; + input R_IDP_I1; + input R_IDP_I2; + input R_IDP_I3; + input R_IDP_I4; + output R_IDS_O1; + output R_IDS_O2; + output R_IDS_O3; + output R_IDS_O4; + output R_IDS_O5; + output R_IDS_O6; + output R_IDS_O7; + output R_IDS_O8; + input R_LSTM_I; + input R_LSTP_I; + output R_LST_O; + output R_RDYM_O; + output R_RDYP_O; + input R_RDY_I; + input R_RSPM_I1; + input R_RSPM_I2; + input R_RSPP_I1; + input R_RSPP_I2; + output R_RSP_O1; + output R_RSP_O2; + input R_VDM_I; + input R_VDP_I; + output R_VD_O; + input SE_I; + output SWDO_E_O; + output SWDO_O; + input SW_CK_I; + input SW_DI_I; + output TDO_O; + input TE_INI_I; + output T_CK_O; + output T_CTL_O; + output T_DATA_O1; + output T_DATA_O10; + output T_DATA_O11; + output T_DATA_O12; + output T_DATA_O13; + output T_DATA_O14; + output T_DATA_O15; + output T_DATA_O16; + output T_DATA_O17; + output T_DATA_O18; + output T_DATA_O19; + output T_DATA_O2; + output T_DATA_O20; + output T_DATA_O21; + output T_DATA_O22; + output T_DATA_O23; + output T_DATA_O24; + output T_DATA_O25; + output T_DATA_O26; + output T_DATA_O27; + output T_DATA_O28; + output T_DATA_O29; + output T_DATA_O3; + output T_DATA_O30; + output T_DATA_O31; + output T_DATA_O32; + output T_DATA_O4; + output T_DATA_O5; + output T_DATA_O6; + output T_DATA_O7; + output T_DATA_O8; + output T_DATA_O9; + input T_DI_I; + input VINI_I; + output W_DM_O1; + output W_DM_O10; + output W_DM_O11; + output W_DM_O12; + output W_DM_O13; + output W_DM_O14; + output W_DM_O15; + output W_DM_O16; + output W_DM_O17; + output W_DM_O18; + output W_DM_O19; + output W_DM_O2; + output W_DM_O20; + output W_DM_O21; + output W_DM_O22; + output W_DM_O23; + output W_DM_O24; + output W_DM_O25; + output W_DM_O26; + output W_DM_O27; + output W_DM_O28; + output W_DM_O29; + output W_DM_O3; + output W_DM_O30; + output W_DM_O31; + output W_DM_O32; + output W_DM_O33; + output W_DM_O34; + output W_DM_O35; + output W_DM_O36; + output W_DM_O37; + output W_DM_O38; + output W_DM_O39; + output W_DM_O4; + output W_DM_O40; + output W_DM_O41; + output W_DM_O42; + output W_DM_O43; + output W_DM_O44; + output W_DM_O45; + output W_DM_O46; + output W_DM_O47; + output W_DM_O48; + output W_DM_O49; + output W_DM_O5; + output W_DM_O50; + output W_DM_O51; + output W_DM_O52; + output W_DM_O53; + output W_DM_O54; + output W_DM_O55; + output W_DM_O56; + output W_DM_O57; + output W_DM_O58; + output W_DM_O59; + output W_DM_O6; + output W_DM_O60; + output W_DM_O61; + output W_DM_O62; + output W_DM_O63; + output W_DM_O64; + output W_DM_O7; + output W_DM_O8; + output W_DM_O9; + output W_DP_O1; + output W_DP_O10; + output W_DP_O11; + output W_DP_O12; + output W_DP_O13; + output W_DP_O14; + output W_DP_O15; + output W_DP_O16; + output W_DP_O17; + output W_DP_O18; + output W_DP_O19; + output W_DP_O2; + output W_DP_O20; + output W_DP_O21; + output W_DP_O22; + output W_DP_O23; + output W_DP_O24; + output W_DP_O25; + output W_DP_O26; + output W_DP_O27; + output W_DP_O28; + output W_DP_O29; + output W_DP_O3; + output W_DP_O30; + output W_DP_O31; + output W_DP_O32; + output W_DP_O4; + output W_DP_O5; + output W_DP_O6; + output W_DP_O7; + output W_DP_O8; + output W_DP_O9; + input W_D_I1; + input W_D_I10; + input W_D_I11; + input W_D_I12; + input W_D_I13; + input W_D_I14; + input W_D_I15; + input W_D_I16; + input W_D_I17; + input W_D_I18; + input W_D_I19; + input W_D_I2; + input W_D_I20; + input W_D_I21; + input W_D_I22; + input W_D_I23; + input W_D_I24; + input W_D_I25; + input W_D_I26; + input W_D_I27; + input W_D_I28; + input W_D_I29; + input W_D_I3; + input W_D_I30; + input W_D_I31; + input W_D_I32; + input W_D_I33; + input W_D_I34; + input W_D_I35; + input W_D_I36; + input W_D_I37; + input W_D_I38; + input W_D_I39; + input W_D_I4; + input W_D_I40; + input W_D_I41; + input W_D_I42; + input W_D_I43; + input W_D_I44; + input W_D_I45; + input W_D_I46; + input W_D_I47; + input W_D_I48; + input W_D_I49; + input W_D_I5; + input W_D_I50; + input W_D_I51; + input W_D_I52; + input W_D_I53; + input W_D_I54; + input W_D_I55; + input W_D_I56; + input W_D_I57; + input W_D_I58; + input W_D_I59; + input W_D_I6; + input W_D_I60; + input W_D_I61; + input W_D_I62; + input W_D_I63; + input W_D_I64; + input W_D_I7; + input W_D_I8; + input W_D_I9; + output W_IDM_O1; + output W_IDM_O2; + output W_IDM_O3; + output W_IDM_O4; + output W_IDP_O1; + output W_IDP_O2; + output W_IDP_O3; + output W_IDP_O4; + input W_IDS_I1; + input W_IDS_I2; + input W_IDS_I3; + input W_IDS_I4; + input W_IDS_I5; + input W_IDS_I6; + input W_IDS_I7; + input W_IDS_I8; + output W_LSTM_O; + output W_LSTP_O; + input W_LST_I; + output W_RDY_O; + input W_RYM_I; + input W_RYP_I; + output W_SBM_O1; + output W_SBM_O2; + output W_SBM_O3; + output W_SBM_O4; + output W_SBM_O5; + output W_SBM_O6; + output W_SBM_O7; + output W_SBM_O8; + output W_SBP_O1; + output W_SBP_O2; + output W_SBP_O3; + output W_SBP_O4; + input W_SBS_I1; + input W_SBS_I2; + input W_SBS_I3; + input W_SBS_I4; + input W_SBS_I5; + input W_SBS_I6; + input W_SBS_I7; + input W_SBS_I8; + output W_VDM_O; + output W_VDP_O; + input W_VD_I; +endmodule + +(* blackbox *) +module NX_R5_L_WRAP(CLKIN, nRESET0, nSYSPORESET, nCPUHALT0, DBGNOCLKSTOP, nCLKSTOPPED0, nWFEPIPESTOPPED0, nWFIPIPESTOPPED0, EVENTI0, EVENTO0, VINITHI0, CFGEE, CFGIE, INITRAMA0, LOCZRAMA0, TEINIT, CFGNMFI0, PARECCENRAM0, PARITYLEVEL, ERRENRAM0, INITPPX0 +, nFIQ0, nIRQ0, nPMUIRQ0, ACLKENM0, AWREADYM0, AWSHAREM0, AWVALIDM0, WLASTM0, WREADYM0, WVALIDM0, BREADYM0, BVALIDM0, ARREADYM0, ARSHAREM0, ARVALIDM0, RLASTM0, RREADYM0, RVALIDM0, ACLKENS0, AWREADYS0, AWVALIDS0 +, WLASTS0, WREADYS0, WVALIDS0, BREADYS0, BVALIDS0, ARREADYS0, ARVALIDS0, RLASTS0, RREADYS0, RVALIDS0, ACLKENP0, AWVALIDP0, AWREADYP0, WLASTP0, WVALIDP0, WREADYP0, BVALIDP0, BREADYP0, ARVALIDP0, ARREADYP0, RLASTP0 +, RVALIDP0, RREADYP0, DBGEN0, NIDEN0, EDBGRQ0, DBGACK0, DBGRSTREQ0, COMMRX0, COMMTX0, DBGNOPWRDWN, DBGROMADDRV, DBGSELFADDRV0, nETMPORESET, ETMEN0, nVALIRQ0, nVALFIQ0, nVALRESET0, FPIXC0, FPOFC0, FPUFC0, FPIOC0 +, FPDZC0, FPIDC0, ATRESETn, TRACECLK, TRACECTL, PCLKSYS, PCLKENSYS, PRESETSYSn, PENABLESYS, PREADYSYS, PSELSYS, PSLVERRSYS, PWRITESYS, CDBGPWRUPACK, CDBGPWRUPREQ, CDBGRSTACK, CDBGRSTREQ, CSYSPWRUPACK, CSYSPWRUPREQ, DEVICEEN, JTAGNSW +, nPOTRST, nTDOEN, nTRST, SWCLKTCK, SWDITMS, SWDO, SWDOEN, TDI, TDO, PPXBASE0, PPXSIZE0, PPVBASE0, PPVSIZE0, AWADDRM0, AWBURSTM0, AWCACHEM0, AWIDM0, AWLENM0, AWLOCKM0, AWPROTM0, AWSIZEM0 +, AWINNERM0, WDATAM0, WIDM0, WSTRBM0, BIDM0, BRESPM0, ARADDRM0, ARBURSTM0, ARCACHEM0, ARIDM0, ARLENM0, ARLOCKM0, ARPROTM0, ARSIZEM0, ARINNERM0, RDATAM0, RIDM0, RRESPM0, AWADDRS0, AWBURSTS0, AWCACHES0 +, AWIDS0, AWLENS0, AWLOCKS0, AWPROTS0, AWSIZES0, WDATAS0, WIDS0, WSTRBS0, BIDS0, BRESPS0, ARADDRS0, ARBURSTS0, ARCACHES0, ARIDS0, ARLENS0, ARLOCKS0, ARPROTS0, ARSIZES0, RDATAS0, RIDS0, RRESPS0 +, AWIDP0, AWADDRP0, AWLENP0, AWSIZEP0, AWBURSTP0, AWLOCKP0, AWCACHEP0, AWPROTP0, WIDP0, WDATAP0, WSTRBP0, BIDP0, BRESPP0, ARIDP0, ARADDRP0, ARLENP0, ARSIZEP0, ARBURSTP0, ARLOCKP0, ARCACHEP0, ARPROTP0 +, RIDP0, RDATAP0, RRESPP0, DBGROMADDR, DBGSELFADDR0, ETMASICCTL0, ETMEXTOUT0, TRACEDATA, PADDRSYS, PRDATASYS, PWDATASYS, GROUPID); + input ACLKENM0; + input ACLKENP0; + input ACLKENS0; + output [31:0] ARADDRM0; + output [31:0] ARADDRP0; + input [31:0] ARADDRS0; + output [1:0] ARBURSTM0; + output [1:0] ARBURSTP0; + input [1:0] ARBURSTS0; + output [3:0] ARCACHEM0; + output [3:0] ARCACHEP0; + input [3:0] ARCACHES0; + output [3:0] ARIDM0; + output [3:0] ARIDP0; + input [7:0] ARIDS0; + output [3:0] ARINNERM0; + output [3:0] ARLENM0; + output [3:0] ARLENP0; + input [3:0] ARLENS0; + output [1:0] ARLOCKM0; + output [1:0] ARLOCKP0; + input [1:0] ARLOCKS0; + output [2:0] ARPROTM0; + output [2:0] ARPROTP0; + input [2:0] ARPROTS0; + input ARREADYM0; + input ARREADYP0; + output ARREADYS0; + output ARSHAREM0; + output [2:0] ARSIZEM0; + output [2:0] ARSIZEP0; + input [2:0] ARSIZES0; + output ARVALIDM0; + output ARVALIDP0; + input ARVALIDS0; + input ATRESETn; + output [31:0] AWADDRM0; + output [31:0] AWADDRP0; + input [31:0] AWADDRS0; + output [1:0] AWBURSTM0; + output [1:0] AWBURSTP0; + input [1:0] AWBURSTS0; + output [3:0] AWCACHEM0; + output [3:0] AWCACHEP0; + input [3:0] AWCACHES0; + output [3:0] AWIDM0; + output [3:0] AWIDP0; + input [7:0] AWIDS0; + output [3:0] AWINNERM0; + output [3:0] AWLENM0; + output [3:0] AWLENP0; + input [3:0] AWLENS0; + output [1:0] AWLOCKM0; + output [1:0] AWLOCKP0; + input [1:0] AWLOCKS0; + output [2:0] AWPROTM0; + output [2:0] AWPROTP0; + input [2:0] AWPROTS0; + input AWREADYM0; + input AWREADYP0; + output AWREADYS0; + output AWSHAREM0; + output [2:0] AWSIZEM0; + output [2:0] AWSIZEP0; + input [2:0] AWSIZES0; + output AWVALIDM0; + output AWVALIDP0; + input AWVALIDS0; + input [3:0] BIDM0; + input [3:0] BIDP0; + output [7:0] BIDS0; + output BREADYM0; + output BREADYP0; + input BREADYS0; + input [1:0] BRESPM0; + input [1:0] BRESPP0; + output [1:0] BRESPS0; + input BVALIDM0; + input BVALIDP0; + output BVALIDS0; + input CDBGPWRUPACK; + output CDBGPWRUPREQ; + input CDBGRSTACK; + output CDBGRSTREQ; + input CFGEE; + input CFGIE; + input CFGNMFI0; + input CLKIN; + output COMMRX0; + output COMMTX0; + input CSYSPWRUPACK; + output CSYSPWRUPREQ; + output DBGACK0; + input DBGEN0; + input DBGNOCLKSTOP; + output DBGNOPWRDWN; + input [19:0] DBGROMADDR; + input DBGROMADDRV; + output DBGRSTREQ0; + input [19:0] DBGSELFADDR0; + input DBGSELFADDRV0; + input DEVICEEN; + input EDBGRQ0; + input ERRENRAM0; + output [7:0] ETMASICCTL0; + output ETMEN0; + output [1:0] ETMEXTOUT0; + input EVENTI0; + output EVENTO0; + output FPDZC0; + output FPIDC0; + output FPIOC0; + output FPIXC0; + output FPOFC0; + output FPUFC0; + input [3:0] GROUPID; + input INITPPX0; + input INITRAMA0; + output JTAGNSW; + input LOCZRAMA0; + input NIDEN0; + input [28:0] PADDRSYS; + input PARECCENRAM0; + input PARITYLEVEL; + input PCLKENSYS; + input PCLKSYS; + input PENABLESYS; + input [19:0] PPVBASE0; + input [4:0] PPVSIZE0; + input [19:0] PPXBASE0; + input [4:0] PPXSIZE0; + output [31:0] PRDATASYS; + output PREADYSYS; + input PRESETSYSn; + input PSELSYS; + output PSLVERRSYS; + input [31:0] PWDATASYS; + input PWRITESYS; + input [63:0] RDATAM0; + input [31:0] RDATAP0; + output [63:0] RDATAS0; + input [3:0] RIDM0; + input [3:0] RIDP0; + output [7:0] RIDS0; + input RLASTM0; + input RLASTP0; + output RLASTS0; + output RREADYM0; + output RREADYP0; + input RREADYS0; + input [1:0] RRESPM0; + input [1:0] RRESPP0; + output [1:0] RRESPS0; + input RVALIDM0; + input RVALIDP0; + output RVALIDS0; + input SWCLKTCK; + input SWDITMS; + output SWDO; + output SWDOEN; + input TDI; + output TDO; + input TEINIT; + output TRACECLK; + output TRACECTL; + output [31:0] TRACEDATA; + input VINITHI0; + output [63:0] WDATAM0; + output [31:0] WDATAP0; + input [63:0] WDATAS0; + output [3:0] WIDM0; + output [3:0] WIDP0; + input [7:0] WIDS0; + output WLASTM0; + output WLASTP0; + input WLASTS0; + input WREADYM0; + input WREADYP0; + output WREADYS0; + output [7:0] WSTRBM0; + output [3:0] WSTRBP0; + input [7:0] WSTRBS0; + output WVALIDM0; + output WVALIDP0; + input WVALIDS0; + output nCLKSTOPPED0; + input nCPUHALT0; + input nETMPORESET; + input nFIQ0; + input nIRQ0; + output nPMUIRQ0; + input nPOTRST; + input nRESET0; + input nSYSPORESET; + output nTDOEN; + input nTRST; + output nVALFIQ0; + output nVALIRQ0; + output nVALRESET0; + output nWFEPIPESTOPPED0; + output nWFIPIPESTOPPED0; +endmodule + +(* blackbox *) +module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 +, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 +, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3 +, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24 +, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21 +, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE +, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR); + input AA1; + input AA10; + input AA11; + input AA12; + input AA13; + input AA14; + input AA15; + input AA16; + input AA2; + input AA3; + input AA4; + input AA5; + input AA6; + input AA7; + input AA8; + input AA9; + input ACK; + input ACKC; + input ACKD; + input ACKR; + output ACOR; + input ACS; + output AERR; + input AI1; + input AI10; + input AI11; + input AI12; + input AI13; + input AI14; + input AI15; + input AI16; + input AI17; + input AI18; + input AI19; + input AI2; + input AI20; + input AI21; + input AI22; + input AI23; + input AI24; + input AI3; + input AI4; + input AI5; + input AI6; + input AI7; + input AI8; + input AI9; + output AO1; + output AO10; + output AO11; + output AO12; + output AO13; + output AO14; + output AO15; + output AO16; + output AO17; + output AO18; + output AO19; + output AO2; + output AO20; + output AO21; + output AO22; + output AO23; + output AO24; + output AO3; + output AO4; + output AO5; + output AO6; + output AO7; + output AO8; + output AO9; + input AR; + input AWE; + input BA1; + input BA10; + input BA11; + input BA12; + input BA13; + input BA14; + input BA15; + input BA16; + input BA2; + input BA3; + input BA4; + input BA5; + input BA6; + input BA7; + input BA8; + input BA9; + input BCK; + input BCKC; + input BCKD; + input BCKR; + output BCOR; + input BCS; + output BERR; + input BI1; + input BI10; + input BI11; + input BI12; + input BI13; + input BI14; + input BI15; + input BI16; + input BI17; + input BI18; + input BI19; + input BI2; + input BI20; + input BI21; + input BI22; + input BI23; + input BI24; + input BI3; + input BI4; + input BI5; + input BI6; + input BI7; + input BI8; + input BI9; + output BO1; + output BO10; + output BO11; + output BO12; + output BO13; + output BO14; + output BO15; + output BO16; + output BO17; + output BO18; + output BO19; + output BO2; + output BO20; + output BO21; + output BO22; + output BO23; + output BO24; + output BO3; + output BO4; + output BO5; + output BO6; + output BO7; + output BO8; + output BO9; + input BR; + input BWE; + parameter mcka_edge = 1'b0; + parameter mckb_edge = 1'b0; + parameter mem_ctxt = ""; + parameter pcka_edge = 1'b0; + parameter pckb_edge = 1'b0; + parameter pipe_ia = 1'b0; + parameter pipe_ib = 1'b0; + parameter pipe_oa = 1'b0; + parameter pipe_ob = 1'b0; + parameter raw_config0 = 4'b0000; + parameter raw_config1 = 16'b0000000000000000; + parameter raw_l_enable = 1'b0; + parameter raw_l_extend = 4'b0000; + parameter raw_u_enable = 1'b0; + parameter raw_u_extend = 8'b00000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_RAM_SLOWECC_1K_36_1r1w(ACK, BCK, ACOR, AERR, ACS, AWE, AR, BCS, BWE, BR, AO, AI, AA); + input [9:0] AA; + input ACK; + output ACOR; + input ACS; + output AERR; + input [35:0] AI; + output [35:0] AO; + input AR; + input AWE; + input BCK; + input BCS; + input BR; + input BWE; + parameter mem_ctxt = ""; +endmodule + +(* blackbox *) +module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA +, BA); + input [15:0] AA; + input ACK; + input ACKD; + input ACKR; + output ACOR; + input ACS; + output AERR; + input [23:0] AI; + output [23:0] AO; + input AR; + input AWE; + input [15:0] BA; + input BCK; + input BCKD; + input BCKR; + output BCOR; + input BCS; + output BERR; + input [23:0] BI; + output [23:0] BO; + input BR; + input BWE; + parameter mcka_edge = 1'b0; + parameter mckb_edge = 1'b0; + parameter mem_ctxt = ""; + parameter pcka_edge = 1'b0; + parameter pckb_edge = 1'b0; + parameter pipe_ia = 1'b0; + parameter pipe_ib = 1'b0; + parameter pipe_oa = 1'b0; + parameter pipe_ob = 1'b0; + parameter raw_config0 = 4'b0000; + parameter raw_config1 = 16'b0000000000000000; + parameter raw_l_enable = 1'b0; + parameter raw_l_extend = 4'b0000; + parameter raw_u_enable = 1'b0; + parameter raw_u_extend = 8'b00000000; + parameter std_mode = ""; +endmodule + +(* blackbox *) +module NX_RB(CK1, CK2, CK3, CK4, EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EI9, EI10, EI11, EI12, EI13, EI14, EI15, EI16, EI17 +, EI18, EI19, EI20, EI21, EI22, EI23, EI24, EI25, EI26, EI27, EI28, EI29, EI30, EI31, EI32, EI33, EI34, EI35, EI36, EI37, EI38 +, EI39, EI40, EI41, EI42, EI43, EI44, EI45, EI46, EI47, EI48, EI49, EI50, EI51, EI52, EI53, EI54, EI55, EI56, EI57, EI58, EI59 +, EI60, EI61, EI62, EI63, EI64, EI65, EI66, EI67, EI68, EI69, EI70, EI71, EI72, EI73, EI74, EI75, EI76, EI77, EI78, EI79, EI80 +, EI81, EI82, EI83, EI84, EI85, EI86, EI87, EI88, EI89, EI90, EI91, EI92, EI93, EI94, EI95, EI96, EI97, EI98, EI99, EI100, EI101 +, EI102, EI103, EI104, EI105, EI106, EI107, EI108, EI109, EI110, EI111, EI112, EI113, EI114, EI115, EI116, EI117, EI118, EI119, EI120, EI121, EI122 +, EI123, EI124, EI125, EI126, EI127, EI128, EI129, EI130, EI131, EI132, EI133, EI134, EI135, EI136, EI137, EI138, EI139, EI140, EI141, EI142, EI143 +, EI144, EI145, EI146, EI147, EI148, EI149, EI150, EI151, EI152, EI153, EI154, EI155, EI156, EI157, EI158, EI159, EI160, EI161, EI162, EI163, EI164 +, EI165, EI166, EI167, EI168, EI169, EI170, EI171, EI172, EI173, EI174, EI175, EI176, EI177, EI178, EI179, EI180, EI181, EI182, EI183, EI184, EI185 +, EI186, EI187, EI188, EI189, EI190, EI191, EI192, EI_CK, EO_CK, EO1, EO2, EO3, EO4, EO5, EO6, EO7, EO8, EO9, EO10, EO11, EO12 +, EO13, EO14, EO15, EO16, EO17, EO18, EO19, EO20, EO21, EO22, EO23, EO24, EO25, EO26, EO27, EO28, EO29, EO30, EO31, EO32, EO33 +, EO34, EO35, EO36, EO37, EO38, EO39, EO40, EO41, EO42, EO43, EO44, EO45, EO46, EO47, EO48, EO49, EO50, EO51, EO52, EO53, EO54 +, EO55, EO56, EO57, EO58, EO59, EO60, EO61, EO62, EO63, EO64, EO65, EO66, EO67, EO68, EO69, EO70, EO71, EO72, EO73, EO74, EO75 +, EO76, EO77, EO78, EO79, EO80, EO81, EO82, EO83, EO84, EO85, EO86, EO87, EO88, EO89, EO90, EO91, EO92, EO93, EO94, EO95, EO96 +, EO97, EO98, EO99, EO100, EO101, EO102, EO103, EO104, EO105, EO106, EO107, EO108, EO109, EO110, EO111, EO112, EO113, EO114, EO115, EO116, EO117 +, EO118, EO119, EO120, EO121, EO122, EO123, EO124, EO125, EO126, EO127, EO128, EO129, EO130, EO131, EO132, EO133, EO134, EO135, EO136, EO137, EO138 +, EO139, EO140, EO141, EO142, EO143, EO144, EO145, EO146, EO147, EO148, EO149, EO150, EO151, EO152, EO153, EO154, EO155, EO156, EO157, EO158, EO159 +, EO160, EO161, EO162, EO163, EO164, EO165, EO166, EO167, EO168, EO169, EO170, EO171, EO172, EO173, EO174, EO175, EO176, EO177, EO178, EO179, EO180 +, EO181, EO182, EO183, EO184, EO185, EO186, EO187, EO188, EO189, EO190, EO191, EO192, FI1, FI2, FI3, FI4, FI5, FI6, FI7, FI8, FI9 +, FI10, FI11, FI12, FI13, FI14, FI15, FI16, FI17, FI18, FI19, FI20, FI21, FI22, FI23, FI24, FI25, FI26, FI27, FI28, FI29, FI30 +, FI31, FI32, FI33, FI34, FI35, FI36, FI37, FI38, FI39, FI40, FI41, FI42, FI43, FI44, FI45, FI46, FI47, FI48, FI49, FI50, FI51 +, FI52, FI53, FI54, FI55, FI56, FI57, FI58, FI59, FI60, FI61, FI62, FI63, FI64, FI65, FI66, FI67, FI68, FI69, FI70, FI71, FI72 +, FI73, FI74, FI75, FI76, FI77, FI78, FI79, FI80, FI81, FI82, FI83, FI84, FI85, FI86, FI87, FI88, FI89, FI90, FI91, FI92, FI93 +, FI94, FI95, FI96, FI97, FI98, FI99, FI100, FI101, FI102, FI103, FI104, FI105, FI106, FI107, FI108, FI109, FI110, FI111, FI112, FI113, FI114 +, FI115, FI116, FI117, FI118, FI119, FI120, FI121, FI122, FI123, FI124, FI125, FI126, FI127, FI128, FI129, FI130, FI131, FI132, FI133, FI134, FI135 +, FI136, FI137, FI138, FI139, FI140, FI141, FI142, FI143, FI144, FI145, FI146, FI147, FI148, FI149, FI150, FI151, FI152, FI153, FI154, FI155, FI156 +, FI157, FI158, FI159, FI160, FI161, FI162, FI163, FI164, FI165, FI166, FI167, FI168, FI169, FI170, FI171, FI172, FI173, FI174, FI175, FI176, FI177 +, FI178, FI179, FI180, FI181, FI182, FI183, FI184, FI185, FI186, FI187, FI188, FI189, FI190, FI191, FI192, FO1, FO2, FO3, FO4, FO5, FO6 +, FO7, FO8, FO9, FO10, FO11, FO12, FO13, FO14, FO15, FO16, FO17, FO18, FO19, FO20, FO21, FO22, FO23, FO24, FO25, FO26, FO27 +, FO28, FO29, FO30, FO31, FO32, FO33, FO34, FO35, FO36, FO37, FO38, FO39, FO40, FO41, FO42, FO43, FO44, FO45, FO46, FO47, FO48 +, FO49, FO50, FO51, FO52, FO53, FO54, FO55, FO56, FO57, FO58, FO59, FO60, FO61, FO62, FO63, FO64, FO65, FO66, FO67, FO68, FO69 +, FO70, FO71, FO72, FO73, FO74, FO75, FO76, FO77, FO78, FO79, FO80, FO81, FO82, FO83, FO84, FO85, FO86, FO87, FO88, FO89, FO90 +, FO91, FO92, FO93, FO94, FO95, FO96, FO97, FO98, FO99, FO100, FO101, FO102, FO103, FO104, FO105, FO106, FO107, FO108, FO109, FO110, FO111 +, FO112, FO113, FO114, FO115, FO116, FO117, FO118, FO119, FO120, FO121, FO122, FO123, FO124, FO125, FO126, FO127, FO128, FO129, FO130, FO131, FO132 +, FO133, FO134, FO135, FO136, FO137, FO138, FO139, FO140, FO141, FO142, FO143, FO144, FO145, FO146, FO147, FO148, FO149, FO150, FO151, FO152, FO153 +, FO154, FO155, FO156, FO157, FO158, FO159, FO160, FO161, FO162, FO163, FO164, FO165, FO166, FO167, FO168, FO169, FO170, FO171, FO172, FO173, FO174 +, FO175, FO176, FO177, FO178, FO179, FO180, FO181, FO182, FO183, FO184, FO185, FO186, FO187, FO188, FO189, FO190, FO191, FO192); + input CK1; + input CK2; + input CK3; + input CK4; + input EI1; + input EI10; + input EI100; + input EI101; + input EI102; + input EI103; + input EI104; + input EI105; + input EI106; + input EI107; + input EI108; + input EI109; + input EI11; + input EI110; + input EI111; + input EI112; + input EI113; + input EI114; + input EI115; + input EI116; + input EI117; + input EI118; + input EI119; + input EI12; + input EI120; + input EI121; + input EI122; + input EI123; + input EI124; + input EI125; + input EI126; + input EI127; + input EI128; + input EI129; + input EI13; + input EI130; + input EI131; + input EI132; + input EI133; + input EI134; + input EI135; + input EI136; + input EI137; + input EI138; + input EI139; + input EI14; + input EI140; + input EI141; + input EI142; + input EI143; + input EI144; + input EI145; + input EI146; + input EI147; + input EI148; + input EI149; + input EI15; + input EI150; + input EI151; + input EI152; + input EI153; + input EI154; + input EI155; + input EI156; + input EI157; + input EI158; + input EI159; + input EI16; + input EI160; + input EI161; + input EI162; + input EI163; + input EI164; + input EI165; + input EI166; + input EI167; + input EI168; + input EI169; + input EI17; + input EI170; + input EI171; + input EI172; + input EI173; + input EI174; + input EI175; + input EI176; + input EI177; + input EI178; + input EI179; + input EI18; + input EI180; + input EI181; + input EI182; + input EI183; + input EI184; + input EI185; + input EI186; + input EI187; + input EI188; + input EI189; + input EI19; + input EI190; + input EI191; + input EI192; + input EI2; + input EI20; + input EI21; + input EI22; + input EI23; + input EI24; + input EI25; + input EI26; + input EI27; + input EI28; + input EI29; + input EI3; + input EI30; + input EI31; + input EI32; + input EI33; + input EI34; + input EI35; + input EI36; + input EI37; + input EI38; + input EI39; + input EI4; + input EI40; + input EI41; + input EI42; + input EI43; + input EI44; + input EI45; + input EI46; + input EI47; + input EI48; + input EI49; + input EI5; + input EI50; + input EI51; + input EI52; + input EI53; + input EI54; + input EI55; + input EI56; + input EI57; + input EI58; + input EI59; + input EI6; + input EI60; + input EI61; + input EI62; + input EI63; + input EI64; + input EI65; + input EI66; + input EI67; + input EI68; + input EI69; + input EI7; + input EI70; + input EI71; + input EI72; + input EI73; + input EI74; + input EI75; + input EI76; + input EI77; + input EI78; + input EI79; + input EI8; + input EI80; + input EI81; + input EI82; + input EI83; + input EI84; + input EI85; + input EI86; + input EI87; + input EI88; + input EI89; + input EI9; + input EI90; + input EI91; + input EI92; + input EI93; + input EI94; + input EI95; + input EI96; + input EI97; + input EI98; + input EI99; + output EI_CK; + output EO1; + output EO10; + output EO100; + output EO101; + output EO102; + output EO103; + output EO104; + output EO105; + output EO106; + output EO107; + output EO108; + output EO109; + output EO11; + output EO110; + output EO111; + output EO112; + output EO113; + output EO114; + output EO115; + output EO116; + output EO117; + output EO118; + output EO119; + output EO12; + output EO120; + output EO121; + output EO122; + output EO123; + output EO124; + output EO125; + output EO126; + output EO127; + output EO128; + output EO129; + output EO13; + output EO130; + output EO131; + output EO132; + output EO133; + output EO134; + output EO135; + output EO136; + output EO137; + output EO138; + output EO139; + output EO14; + output EO140; + output EO141; + output EO142; + output EO143; + output EO144; + output EO145; + output EO146; + output EO147; + output EO148; + output EO149; + output EO15; + output EO150; + output EO151; + output EO152; + output EO153; + output EO154; + output EO155; + output EO156; + output EO157; + output EO158; + output EO159; + output EO16; + output EO160; + output EO161; + output EO162; + output EO163; + output EO164; + output EO165; + output EO166; + output EO167; + output EO168; + output EO169; + output EO17; + output EO170; + output EO171; + output EO172; + output EO173; + output EO174; + output EO175; + output EO176; + output EO177; + output EO178; + output EO179; + output EO18; + output EO180; + output EO181; + output EO182; + output EO183; + output EO184; + output EO185; + output EO186; + output EO187; + output EO188; + output EO189; + output EO19; + output EO190; + output EO191; + output EO192; + output EO2; + output EO20; + output EO21; + output EO22; + output EO23; + output EO24; + output EO25; + output EO26; + output EO27; + output EO28; + output EO29; + output EO3; + output EO30; + output EO31; + output EO32; + output EO33; + output EO34; + output EO35; + output EO36; + output EO37; + output EO38; + output EO39; + output EO4; + output EO40; + output EO41; + output EO42; + output EO43; + output EO44; + output EO45; + output EO46; + output EO47; + output EO48; + output EO49; + output EO5; + output EO50; + output EO51; + output EO52; + output EO53; + output EO54; + output EO55; + output EO56; + output EO57; + output EO58; + output EO59; + output EO6; + output EO60; + output EO61; + output EO62; + output EO63; + output EO64; + output EO65; + output EO66; + output EO67; + output EO68; + output EO69; + output EO7; + output EO70; + output EO71; + output EO72; + output EO73; + output EO74; + output EO75; + output EO76; + output EO77; + output EO78; + output EO79; + output EO8; + output EO80; + output EO81; + output EO82; + output EO83; + output EO84; + output EO85; + output EO86; + output EO87; + output EO88; + output EO89; + output EO9; + output EO90; + output EO91; + output EO92; + output EO93; + output EO94; + output EO95; + output EO96; + output EO97; + output EO98; + output EO99; + output EO_CK; + input FI1; + input FI10; + input FI100; + input FI101; + input FI102; + input FI103; + input FI104; + input FI105; + input FI106; + input FI107; + input FI108; + input FI109; + input FI11; + input FI110; + input FI111; + input FI112; + input FI113; + input FI114; + input FI115; + input FI116; + input FI117; + input FI118; + input FI119; + input FI12; + input FI120; + input FI121; + input FI122; + input FI123; + input FI124; + input FI125; + input FI126; + input FI127; + input FI128; + input FI129; + input FI13; + input FI130; + input FI131; + input FI132; + input FI133; + input FI134; + input FI135; + input FI136; + input FI137; + input FI138; + input FI139; + input FI14; + input FI140; + input FI141; + input FI142; + input FI143; + input FI144; + input FI145; + input FI146; + input FI147; + input FI148; + input FI149; + input FI15; + input FI150; + input FI151; + input FI152; + input FI153; + input FI154; + input FI155; + input FI156; + input FI157; + input FI158; + input FI159; + input FI16; + input FI160; + input FI161; + input FI162; + input FI163; + input FI164; + input FI165; + input FI166; + input FI167; + input FI168; + input FI169; + input FI17; + input FI170; + input FI171; + input FI172; + input FI173; + input FI174; + input FI175; + input FI176; + input FI177; + input FI178; + input FI179; + input FI18; + input FI180; + input FI181; + input FI182; + input FI183; + input FI184; + input FI185; + input FI186; + input FI187; + input FI188; + input FI189; + input FI19; + input FI190; + input FI191; + input FI192; + input FI2; + input FI20; + input FI21; + input FI22; + input FI23; + input FI24; + input FI25; + input FI26; + input FI27; + input FI28; + input FI29; + input FI3; + input FI30; + input FI31; + input FI32; + input FI33; + input FI34; + input FI35; + input FI36; + input FI37; + input FI38; + input FI39; + input FI4; + input FI40; + input FI41; + input FI42; + input FI43; + input FI44; + input FI45; + input FI46; + input FI47; + input FI48; + input FI49; + input FI5; + input FI50; + input FI51; + input FI52; + input FI53; + input FI54; + input FI55; + input FI56; + input FI57; + input FI58; + input FI59; + input FI6; + input FI60; + input FI61; + input FI62; + input FI63; + input FI64; + input FI65; + input FI66; + input FI67; + input FI68; + input FI69; + input FI7; + input FI70; + input FI71; + input FI72; + input FI73; + input FI74; + input FI75; + input FI76; + input FI77; + input FI78; + input FI79; + input FI8; + input FI80; + input FI81; + input FI82; + input FI83; + input FI84; + input FI85; + input FI86; + input FI87; + input FI88; + input FI89; + input FI9; + input FI90; + input FI91; + input FI92; + input FI93; + input FI94; + input FI95; + input FI96; + input FI97; + input FI98; + input FI99; + output FO1; + output FO10; + output FO100; + output FO101; + output FO102; + output FO103; + output FO104; + output FO105; + output FO106; + output FO107; + output FO108; + output FO109; + output FO11; + output FO110; + output FO111; + output FO112; + output FO113; + output FO114; + output FO115; + output FO116; + output FO117; + output FO118; + output FO119; + output FO12; + output FO120; + output FO121; + output FO122; + output FO123; + output FO124; + output FO125; + output FO126; + output FO127; + output FO128; + output FO129; + output FO13; + output FO130; + output FO131; + output FO132; + output FO133; + output FO134; + output FO135; + output FO136; + output FO137; + output FO138; + output FO139; + output FO14; + output FO140; + output FO141; + output FO142; + output FO143; + output FO144; + output FO145; + output FO146; + output FO147; + output FO148; + output FO149; + output FO15; + output FO150; + output FO151; + output FO152; + output FO153; + output FO154; + output FO155; + output FO156; + output FO157; + output FO158; + output FO159; + output FO16; + output FO160; + output FO161; + output FO162; + output FO163; + output FO164; + output FO165; + output FO166; + output FO167; + output FO168; + output FO169; + output FO17; + output FO170; + output FO171; + output FO172; + output FO173; + output FO174; + output FO175; + output FO176; + output FO177; + output FO178; + output FO179; + output FO18; + output FO180; + output FO181; + output FO182; + output FO183; + output FO184; + output FO185; + output FO186; + output FO187; + output FO188; + output FO189; + output FO19; + output FO190; + output FO191; + output FO192; + output FO2; + output FO20; + output FO21; + output FO22; + output FO23; + output FO24; + output FO25; + output FO26; + output FO27; + output FO28; + output FO29; + output FO3; + output FO30; + output FO31; + output FO32; + output FO33; + output FO34; + output FO35; + output FO36; + output FO37; + output FO38; + output FO39; + output FO4; + output FO40; + output FO41; + output FO42; + output FO43; + output FO44; + output FO45; + output FO46; + output FO47; + output FO48; + output FO49; + output FO5; + output FO50; + output FO51; + output FO52; + output FO53; + output FO54; + output FO55; + output FO56; + output FO57; + output FO58; + output FO59; + output FO6; + output FO60; + output FO61; + output FO62; + output FO63; + output FO64; + output FO65; + output FO66; + output FO67; + output FO68; + output FO69; + output FO7; + output FO70; + output FO71; + output FO72; + output FO73; + output FO74; + output FO75; + output FO76; + output FO77; + output FO78; + output FO79; + output FO8; + output FO80; + output FO81; + output FO82; + output FO83; + output FO84; + output FO85; + output FO86; + output FO87; + output FO88; + output FO89; + output FO9; + output FO90; + output FO91; + output FO92; + output FO93; + output FO94; + output FO95; + output FO96; + output FO97; + output FO98; + output FO99; + parameter inputBypass = 24'b000000000000000000000000; + parameter inputClk = 2'b00; + parameter inputContext = ""; + parameter outputBypass = 24'b000000000000000000000000; + parameter outputClk = 2'b00; + parameter outputContext = ""; +endmodule + +(* blackbox *) +module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO); + input [3:0] CK; + input [191:0] EI; + output EI_CK; + output [191:0] EO; + output EO_CK; + input [191:0] FI; + output [191:0] FO; + parameter inputBypass = 24'b000000000000000000000000; + parameter inputClk = 2'b00; + parameter inputContext = ""; + parameter outputBypass = 24'b000000000000000000000000; + parameter outputClk = 2'b00; + parameter outputContext = ""; +endmodule + +(* blackbox *) +module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter addr_mask = 5'b00000; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + parameter we_mask = 1'b0; + parameter wea_mask = 1'b0; +endmodule + +(* blackbox *) +module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA); + input [17:0] I; + output [17:0] O; + input [4:0] RA; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA); + input [17:0] I; + output [17:0] O; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); + output COR; + output ERR; + input [15:0] I; + output [15:0] O; + input [5:0] RA; + input RCK; + input RE; + input [5:0] WA; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 +, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 +, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 +, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1 +, WA2, WA3, WA4, WA5, WA6, WE, WEA); + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I17; + input I18; + input I19; + input I2; + input I20; + input I21; + input I22; + input I23; + input I24; + input I25; + input I26; + input I27; + input I28; + input I29; + input I3; + input I30; + input I31; + input I32; + input I33; + input I34; + input I35; + input I36; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O17; + output O18; + output O19; + output O2; + output O20; + output O21; + output O22; + output O23; + output O24; + output O25; + output O26; + output O27; + output O28; + output O29; + output O3; + output O30; + output O31; + output O32; + output O33; + output O34; + output O35; + output O36; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA10; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RA7; + input RA8; + input RA9; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); + output COR; + output ERR; + input [15:0] I; + output [15:0] O; + input [5:0] RA; + input RCK; + input RE; + input [5:0] WA; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); + input DCK; + output [5:0] DID; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + input FCK; + input [4:0] I; + output IO; + input R; + input SCK; + parameter data_size = 5; + parameter differential = ""; + parameter drive = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter slewRate = ""; + parameter spath_dynamic = 1'b0; + parameter standard = ""; +endmodule + +(* blackbox *) +module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO +, DID); + input CCK; + input CI; + input CL; + input CR; + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + input FCK; + output FLD; + output FLG; + input FZ; + input [4:0] I; + inout IO; + output [4:0] O; + input RRX; + input RTX; + input SCK; + parameter cpath_registered = 1'b0; + parameter data_size = 5; + parameter differential = ""; + parameter dpath_dynamic = 1'b0; + parameter drive = ""; + parameter inputDelayLine = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter slewRate = ""; + parameter spath_dynamic = 1'b0; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +(* blackbox *) +module NX_SERVICE_IF_U(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7 +, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20 +, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2 +, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4 +, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10 +, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31 +, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7 +, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7 +, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13 +, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34 +, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20 +, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6 +, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27 +, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12 +, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1 +, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22 +, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2 +, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7 +, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o +, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15 +, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36 +, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11 +, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32 +, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53 +, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74 +, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95 +, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116 +, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9 +, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30 +, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51 +, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72 +, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93 +, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114 +, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1, fabric_thsens_fm_mode_w_i2 +, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22, fabric_thsens_fm_mode_w_i23 +, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10, fabric_thsens_fm_config_w_i11 +, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3, fabric_thsens_fm_data_o4 +, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8, fabric_thsens_fm_mode_r_o9 +, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29, fabric_thsens_fm_mode_r_o30 +, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18, fabric_thsens_fm_config_r_o19 +, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5 +, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26 +, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8 +, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2 +, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8 +, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2 +, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23 +, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44 +, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17 +, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38 +, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2 +, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2 +, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5 +, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8 +, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2 +, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17 +, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6 +, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2 +, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17 +, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7 +, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28 +, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i +, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1 +, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22 +, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12 +, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o +); + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_clk_bsm_o; + input fabric_clk_otp_mux_i; + output fabric_clk_otp_o; + output fabric_clk_user0_o; + output fabric_clk_user1_o; + input fabric_enable_TMR_i1; + input fabric_enable_TMR_i2; + input fabric_enable_TMR_i3; + output fabric_flag_ready_TMR_o1; + output fabric_flag_ready_TMR_o2; + output fabric_flag_ready_TMR_o3; + output fabric_flag_trigger0_o; + output fabric_flag_trigger1_o; + input fabric_io_in_i1; + input fabric_io_in_i10; + input fabric_io_in_i11; + input fabric_io_in_i12; + input fabric_io_in_i13; + input fabric_io_in_i14; + input fabric_io_in_i15; + input fabric_io_in_i16; + input fabric_io_in_i17; + input fabric_io_in_i18; + input fabric_io_in_i19; + input fabric_io_in_i2; + input fabric_io_in_i20; + input fabric_io_in_i21; + input fabric_io_in_i22; + input fabric_io_in_i23; + input fabric_io_in_i24; + input fabric_io_in_i25; + input fabric_io_in_i26; + input fabric_io_in_i27; + input fabric_io_in_i28; + input fabric_io_in_i29; + input fabric_io_in_i3; + input fabric_io_in_i30; + input fabric_io_in_i31; + input fabric_io_in_i32; + input fabric_io_in_i33; + input fabric_io_in_i34; + input fabric_io_in_i35; + input fabric_io_in_i4; + input fabric_io_in_i5; + input fabric_io_in_i6; + input fabric_io_in_i7; + input fabric_io_in_i8; + input fabric_io_in_i9; + input fabric_io_oe_i1; + input fabric_io_oe_i10; + input fabric_io_oe_i11; + input fabric_io_oe_i12; + input fabric_io_oe_i13; + input fabric_io_oe_i14; + input fabric_io_oe_i15; + input fabric_io_oe_i16; + input fabric_io_oe_i17; + input fabric_io_oe_i18; + input fabric_io_oe_i19; + input fabric_io_oe_i2; + input fabric_io_oe_i20; + input fabric_io_oe_i21; + input fabric_io_oe_i22; + input fabric_io_oe_i23; + input fabric_io_oe_i24; + input fabric_io_oe_i25; + input fabric_io_oe_i26; + input fabric_io_oe_i27; + input fabric_io_oe_i28; + input fabric_io_oe_i29; + input fabric_io_oe_i3; + input fabric_io_oe_i30; + input fabric_io_oe_i31; + input fabric_io_oe_i32; + input fabric_io_oe_i33; + input fabric_io_oe_i34; + input fabric_io_oe_i35; + input fabric_io_oe_i4; + input fabric_io_oe_i5; + input fabric_io_oe_i6; + input fabric_io_oe_i7; + input fabric_io_oe_i8; + input fabric_io_oe_i9; + output fabric_io_out_o1; + output fabric_io_out_o10; + output fabric_io_out_o11; + output fabric_io_out_o12; + output fabric_io_out_o13; + output fabric_io_out_o14; + output fabric_io_out_o15; + output fabric_io_out_o16; + output fabric_io_out_o17; + output fabric_io_out_o18; + output fabric_io_out_o19; + output fabric_io_out_o2; + output fabric_io_out_o20; + output fabric_io_out_o21; + output fabric_io_out_o22; + output fabric_io_out_o23; + output fabric_io_out_o24; + output fabric_io_out_o25; + output fabric_io_out_o26; + output fabric_io_out_o27; + output fabric_io_out_o28; + output fabric_io_out_o29; + output fabric_io_out_o3; + output fabric_io_out_o30; + output fabric_io_out_o31; + output fabric_io_out_o32; + output fabric_io_out_o33; + output fabric_io_out_o34; + output fabric_io_out_o35; + output fabric_io_out_o4; + output fabric_io_out_o5; + output fabric_io_out_o6; + output fabric_io_out_o7; + output fabric_io_out_o8; + output fabric_io_out_o9; + output fabric_jtag_tck_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i1; + input fabric_lowskew_i10; + input fabric_lowskew_i11; + input fabric_lowskew_i12; + input fabric_lowskew_i13; + input fabric_lowskew_i14; + input fabric_lowskew_i15; + input fabric_lowskew_i16; + input fabric_lowskew_i17; + input fabric_lowskew_i18; + input fabric_lowskew_i19; + input fabric_lowskew_i2; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + input fabric_lowskew_i24; + input fabric_lowskew_i25; + input fabric_lowskew_i26; + input fabric_lowskew_i27; + input fabric_lowskew_i28; + input fabric_lowskew_i29; + input fabric_lowskew_i3; + input fabric_lowskew_i30; + input fabric_lowskew_i31; + input fabric_lowskew_i32; + input fabric_lowskew_i33; + input fabric_lowskew_i34; + input fabric_lowskew_i35; + input fabric_lowskew_i36; + input fabric_lowskew_i37; + input fabric_lowskew_i38; + input fabric_lowskew_i39; + input fabric_lowskew_i4; + input fabric_lowskew_i40; + input fabric_lowskew_i5; + input fabric_lowskew_i6; + input fabric_lowskew_i7; + input fabric_lowskew_i8; + input fabric_lowskew_i9; + output fabric_lowskew_o1; + output fabric_lowskew_o2; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + output fabric_otp_user_ack_o; + input fabric_otp_user_add_i1; + input fabric_otp_user_add_i2; + input fabric_otp_user_add_i3; + input fabric_otp_user_add_i4; + input fabric_otp_user_add_i5; + input fabric_otp_user_add_i6; + input fabric_otp_user_add_i7; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output fabric_otp_user_bist1fail_o1; + output fabric_otp_user_bist1fail_o2; + output fabric_otp_user_bist1fail_o3; + output fabric_otp_user_bist1fail_o4; + output fabric_otp_user_bist1fail_o5; + output fabric_otp_user_bist1fail_o6; + output fabric_otp_user_bist1fail_o7; + output fabric_otp_user_bist1fail_o8; + output fabric_otp_user_bist2fail_o1; + output fabric_otp_user_bist2fail_o2; + output fabric_otp_user_bist2fail_o3; + output fabric_otp_user_bist2fail_o4; + output fabric_otp_user_bist2fail_o5; + output fabric_otp_user_bist2fail_o6; + output fabric_otp_user_bist2fail_o7; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clk_i; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input fabric_otp_user_din_i1; + input fabric_otp_user_din_i10; + input fabric_otp_user_din_i11; + input fabric_otp_user_din_i12; + input fabric_otp_user_din_i13; + input fabric_otp_user_din_i14; + input fabric_otp_user_din_i15; + input fabric_otp_user_din_i16; + input fabric_otp_user_din_i17; + input fabric_otp_user_din_i18; + input fabric_otp_user_din_i19; + input fabric_otp_user_din_i2; + input fabric_otp_user_din_i20; + input fabric_otp_user_din_i21; + input fabric_otp_user_din_i22; + input fabric_otp_user_din_i23; + input fabric_otp_user_din_i24; + input fabric_otp_user_din_i25; + input fabric_otp_user_din_i26; + input fabric_otp_user_din_i27; + input fabric_otp_user_din_i28; + input fabric_otp_user_din_i29; + input fabric_otp_user_din_i3; + input fabric_otp_user_din_i30; + input fabric_otp_user_din_i31; + input fabric_otp_user_din_i32; + input fabric_otp_user_din_i33; + input fabric_otp_user_din_i34; + input fabric_otp_user_din_i35; + input fabric_otp_user_din_i36; + input fabric_otp_user_din_i37; + input fabric_otp_user_din_i38; + input fabric_otp_user_din_i39; + input fabric_otp_user_din_i4; + input fabric_otp_user_din_i5; + input fabric_otp_user_din_i6; + input fabric_otp_user_din_i7; + input fabric_otp_user_din_i8; + input fabric_otp_user_din_i9; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output fabric_otp_user_dout_o1; + output fabric_otp_user_dout_o10; + output fabric_otp_user_dout_o11; + output fabric_otp_user_dout_o12; + output fabric_otp_user_dout_o13; + output fabric_otp_user_dout_o14; + output fabric_otp_user_dout_o15; + output fabric_otp_user_dout_o16; + output fabric_otp_user_dout_o17; + output fabric_otp_user_dout_o18; + output fabric_otp_user_dout_o19; + output fabric_otp_user_dout_o2; + output fabric_otp_user_dout_o20; + output fabric_otp_user_dout_o21; + output fabric_otp_user_dout_o22; + output fabric_otp_user_dout_o23; + output fabric_otp_user_dout_o24; + output fabric_otp_user_dout_o25; + output fabric_otp_user_dout_o26; + output fabric_otp_user_dout_o27; + output fabric_otp_user_dout_o28; + output fabric_otp_user_dout_o29; + output fabric_otp_user_dout_o3; + output fabric_otp_user_dout_o30; + output fabric_otp_user_dout_o31; + output fabric_otp_user_dout_o32; + output fabric_otp_user_dout_o33; + output fabric_otp_user_dout_o34; + output fabric_otp_user_dout_o35; + output fabric_otp_user_dout_o36; + output fabric_otp_user_dout_o37; + output fabric_otp_user_dout_o38; + output fabric_otp_user_dout_o39; + output fabric_otp_user_dout_o4; + output fabric_otp_user_dout_o40; + output fabric_otp_user_dout_o41; + output fabric_otp_user_dout_o5; + output fabric_otp_user_dout_o6; + output fabric_otp_user_dout_o7; + output fabric_otp_user_dout_o8; + output fabric_otp_user_dout_o9; + input fabric_otp_user_eccbypass_i; + output fabric_otp_user_flagstate_o1; + output fabric_otp_user_flagstate_o2; + output fabric_otp_user_flagstate_o3; + output fabric_otp_user_flagstate_o4; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input fabric_otp_user_prgwidth_i1; + input fabric_otp_user_prgwidth_i2; + input fabric_otp_user_prgwidth_i3; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output fabric_otp_user_startword_o1; + output fabric_otp_user_startword_o10; + output fabric_otp_user_startword_o11; + output fabric_otp_user_startword_o12; + output fabric_otp_user_startword_o13; + output fabric_otp_user_startword_o14; + output fabric_otp_user_startword_o15; + output fabric_otp_user_startword_o16; + output fabric_otp_user_startword_o2; + output fabric_otp_user_startword_o3; + output fabric_otp_user_startword_o4; + output fabric_otp_user_startword_o5; + output fabric_otp_user_startword_o6; + output fabric_otp_user_startword_o7; + output fabric_otp_user_startword_o8; + output fabric_otp_user_startword_o9; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input fabric_otp_user_tst_scanin_i1; + input fabric_otp_user_tst_scanin_i2; + input fabric_otp_user_tst_scanin_i3; + input fabric_otp_user_tst_scanin_i4; + input fabric_otp_user_tst_scanin_i5; + output fabric_otp_user_tst_scanout_o1; + output fabric_otp_user_tst_scanout_o2; + output fabric_otp_user_tst_scanout_o3; + output fabric_otp_user_tst_scanout_o4; + output fabric_otp_user_tst_scanout_o5; + output fabric_otp_user_wlromout_o1; + output fabric_otp_user_wlromout_o10; + output fabric_otp_user_wlromout_o2; + output fabric_otp_user_wlromout_o3; + output fabric_otp_user_wlromout_o4; + output fabric_otp_user_wlromout_o5; + output fabric_otp_user_wlromout_o6; + output fabric_otp_user_wlromout_o7; + output fabric_otp_user_wlromout_o8; + output fabric_otp_user_wlromout_o9; + input fabric_otp_user_wordlock_i; + input fabric_parusr_clk_i; + input fabric_parusr_cs_i; + input fabric_parusr_data_i1; + input fabric_parusr_data_i10; + input fabric_parusr_data_i11; + input fabric_parusr_data_i12; + input fabric_parusr_data_i13; + input fabric_parusr_data_i14; + input fabric_parusr_data_i15; + input fabric_parusr_data_i16; + input fabric_parusr_data_i2; + input fabric_parusr_data_i3; + input fabric_parusr_data_i4; + input fabric_parusr_data_i5; + input fabric_parusr_data_i6; + input fabric_parusr_data_i7; + input fabric_parusr_data_i8; + input fabric_parusr_data_i9; + output fabric_parusr_data_o1; + output fabric_parusr_data_o10; + output fabric_parusr_data_o11; + output fabric_parusr_data_o12; + output fabric_parusr_data_o13; + output fabric_parusr_data_o14; + output fabric_parusr_data_o15; + output fabric_parusr_data_o16; + output fabric_parusr_data_o2; + output fabric_parusr_data_o3; + output fabric_parusr_data_o4; + output fabric_parusr_data_o5; + output fabric_parusr_data_o6; + output fabric_parusr_data_o7; + output fabric_parusr_data_o8; + output fabric_parusr_data_o9; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input fabric_parusr_type_i1; + input fabric_parusr_type_i2; + input fabric_spare_i1; + input fabric_spare_i10; + input fabric_spare_i100; + input fabric_spare_i101; + input fabric_spare_i102; + input fabric_spare_i103; + input fabric_spare_i104; + input fabric_spare_i105; + input fabric_spare_i106; + input fabric_spare_i107; + input fabric_spare_i108; + input fabric_spare_i109; + input fabric_spare_i11; + input fabric_spare_i110; + input fabric_spare_i111; + input fabric_spare_i112; + input fabric_spare_i113; + input fabric_spare_i114; + input fabric_spare_i115; + input fabric_spare_i116; + input fabric_spare_i117; + input fabric_spare_i118; + input fabric_spare_i119; + input fabric_spare_i12; + input fabric_spare_i120; + input fabric_spare_i121; + input fabric_spare_i122; + input fabric_spare_i123; + input fabric_spare_i124; + input fabric_spare_i125; + input fabric_spare_i126; + input fabric_spare_i127; + input fabric_spare_i128; + input fabric_spare_i13; + input fabric_spare_i14; + input fabric_spare_i15; + input fabric_spare_i16; + input fabric_spare_i17; + input fabric_spare_i18; + input fabric_spare_i19; + input fabric_spare_i2; + input fabric_spare_i20; + input fabric_spare_i21; + input fabric_spare_i22; + input fabric_spare_i23; + input fabric_spare_i24; + input fabric_spare_i25; + input fabric_spare_i26; + input fabric_spare_i27; + input fabric_spare_i28; + input fabric_spare_i29; + input fabric_spare_i3; + input fabric_spare_i30; + input fabric_spare_i31; + input fabric_spare_i32; + input fabric_spare_i33; + input fabric_spare_i34; + input fabric_spare_i35; + input fabric_spare_i36; + input fabric_spare_i37; + input fabric_spare_i38; + input fabric_spare_i39; + input fabric_spare_i4; + input fabric_spare_i40; + input fabric_spare_i41; + input fabric_spare_i42; + input fabric_spare_i43; + input fabric_spare_i44; + input fabric_spare_i45; + input fabric_spare_i46; + input fabric_spare_i47; + input fabric_spare_i48; + input fabric_spare_i49; + input fabric_spare_i5; + input fabric_spare_i50; + input fabric_spare_i51; + input fabric_spare_i52; + input fabric_spare_i53; + input fabric_spare_i54; + input fabric_spare_i55; + input fabric_spare_i56; + input fabric_spare_i57; + input fabric_spare_i58; + input fabric_spare_i59; + input fabric_spare_i6; + input fabric_spare_i60; + input fabric_spare_i61; + input fabric_spare_i62; + input fabric_spare_i63; + input fabric_spare_i64; + input fabric_spare_i65; + input fabric_spare_i66; + input fabric_spare_i67; + input fabric_spare_i68; + input fabric_spare_i69; + input fabric_spare_i7; + input fabric_spare_i70; + input fabric_spare_i71; + input fabric_spare_i72; + input fabric_spare_i73; + input fabric_spare_i74; + input fabric_spare_i75; + input fabric_spare_i76; + input fabric_spare_i77; + input fabric_spare_i78; + input fabric_spare_i79; + input fabric_spare_i8; + input fabric_spare_i80; + input fabric_spare_i81; + input fabric_spare_i82; + input fabric_spare_i83; + input fabric_spare_i84; + input fabric_spare_i85; + input fabric_spare_i86; + input fabric_spare_i87; + input fabric_spare_i88; + input fabric_spare_i89; + input fabric_spare_i9; + input fabric_spare_i90; + input fabric_spare_i91; + input fabric_spare_i92; + input fabric_spare_i93; + input fabric_spare_i94; + input fabric_spare_i95; + input fabric_spare_i96; + input fabric_spare_i97; + input fabric_spare_i98; + input fabric_spare_i99; + output fabric_spare_o1; + output fabric_spare_o10; + output fabric_spare_o100; + output fabric_spare_o101; + output fabric_spare_o102; + output fabric_spare_o103; + output fabric_spare_o104; + output fabric_spare_o105; + output fabric_spare_o106; + output fabric_spare_o107; + output fabric_spare_o108; + output fabric_spare_o109; + output fabric_spare_o11; + output fabric_spare_o110; + output fabric_spare_o111; + output fabric_spare_o112; + output fabric_spare_o113; + output fabric_spare_o114; + output fabric_spare_o115; + output fabric_spare_o116; + output fabric_spare_o117; + output fabric_spare_o118; + output fabric_spare_o119; + output fabric_spare_o12; + output fabric_spare_o120; + output fabric_spare_o121; + output fabric_spare_o122; + output fabric_spare_o123; + output fabric_spare_o124; + output fabric_spare_o125; + output fabric_spare_o126; + output fabric_spare_o127; + output fabric_spare_o128; + output fabric_spare_o13; + output fabric_spare_o14; + output fabric_spare_o15; + output fabric_spare_o16; + output fabric_spare_o17; + output fabric_spare_o18; + output fabric_spare_o19; + output fabric_spare_o2; + output fabric_spare_o20; + output fabric_spare_o21; + output fabric_spare_o22; + output fabric_spare_o23; + output fabric_spare_o24; + output fabric_spare_o25; + output fabric_spare_o26; + output fabric_spare_o27; + output fabric_spare_o28; + output fabric_spare_o29; + output fabric_spare_o3; + output fabric_spare_o30; + output fabric_spare_o31; + output fabric_spare_o32; + output fabric_spare_o33; + output fabric_spare_o34; + output fabric_spare_o35; + output fabric_spare_o36; + output fabric_spare_o37; + output fabric_spare_o38; + output fabric_spare_o39; + output fabric_spare_o4; + output fabric_spare_o40; + output fabric_spare_o41; + output fabric_spare_o42; + output fabric_spare_o43; + output fabric_spare_o44; + output fabric_spare_o45; + output fabric_spare_o46; + output fabric_spare_o47; + output fabric_spare_o48; + output fabric_spare_o49; + output fabric_spare_o5; + output fabric_spare_o50; + output fabric_spare_o51; + output fabric_spare_o52; + output fabric_spare_o53; + output fabric_spare_o54; + output fabric_spare_o55; + output fabric_spare_o56; + output fabric_spare_o57; + output fabric_spare_o58; + output fabric_spare_o59; + output fabric_spare_o6; + output fabric_spare_o60; + output fabric_spare_o61; + output fabric_spare_o62; + output fabric_spare_o63; + output fabric_spare_o64; + output fabric_spare_o65; + output fabric_spare_o66; + output fabric_spare_o67; + output fabric_spare_o68; + output fabric_spare_o69; + output fabric_spare_o7; + output fabric_spare_o70; + output fabric_spare_o71; + output fabric_spare_o72; + output fabric_spare_o73; + output fabric_spare_o74; + output fabric_spare_o75; + output fabric_spare_o76; + output fabric_spare_o77; + output fabric_spare_o78; + output fabric_spare_o79; + output fabric_spare_o8; + output fabric_spare_o80; + output fabric_spare_o81; + output fabric_spare_o82; + output fabric_spare_o83; + output fabric_spare_o84; + output fabric_spare_o85; + output fabric_spare_o86; + output fabric_spare_o87; + output fabric_spare_o88; + output fabric_spare_o89; + output fabric_spare_o9; + output fabric_spare_o90; + output fabric_spare_o91; + output fabric_spare_o92; + output fabric_spare_o93; + output fabric_spare_o94; + output fabric_spare_o95; + output fabric_spare_o96; + output fabric_spare_o97; + output fabric_spare_o98; + output fabric_spare_o99; + input fabric_spi_arst_tmr_n_i1; + input fabric_spi_arst_tmr_n_i2; + input fabric_spi_arst_tmr_n_i3; + input fabric_spi_arst_tmr_n_i4; + input fabric_spi_arst_tmr_n_i5; + input fabric_spi_arst_tmr_n_i6; + input fabric_spi_arst_tmr_n_i7; + input fabric_spi_arst_tmr_n_i8; + input fabric_spi_arst_tmr_n_i9; + output fabric_spi_bsm_release_o1; + output fabric_spi_bsm_release_o2; + output fabric_spi_bsm_release_o3; + output fabric_spi_busy_o1; + output fabric_spi_busy_o2; + output fabric_spi_busy_o3; + input fabric_spi_clk_i0; + input fabric_spi_clk_i1; + input fabric_spi_clk_i2; + input fabric_spi_cmd_bytes_i1; + input fabric_spi_cmd_bytes_i2; + input fabric_spi_cmd_bytes_i3; + input fabric_spi_cmd_bytes_i4; + input fabric_spi_cmd_bytes_i5; + input fabric_spi_cmd_bytes_i6; + output fabric_spi_cmd_full_o1; + output fabric_spi_cmd_full_o2; + output fabric_spi_cmd_full_o3; + input fabric_spi_cmd_mode_i1; + input fabric_spi_cmd_mode_i2; + input fabric_spi_cmd_mode_i3; + input fabric_spi_cmd_mode_i4; + input fabric_spi_cmd_mode_i5; + input fabric_spi_cmd_mode_i6; + input fabric_spi_cmd_push_i1; + input fabric_spi_cmd_push_i2; + input fabric_spi_cmd_push_i3; + input fabric_spi_cmd_type_i1; + input fabric_spi_cmd_type_i2; + input fabric_spi_cmd_type_i3; + input fabric_spi_cmd_type_i4; + input fabric_spi_cmd_type_i5; + input fabric_spi_cmd_type_i6; + input fabric_spi_cpha_i1; + input fabric_spi_cpha_i2; + input fabric_spi_cpha_i3; + input fabric_spi_cpol_i1; + input fabric_spi_cpol_i2; + input fabric_spi_cpol_i3; + input fabric_spi_cs_holdtime_i1; + input fabric_spi_cs_holdtime_i10; + input fabric_spi_cs_holdtime_i11; + input fabric_spi_cs_holdtime_i12; + input fabric_spi_cs_holdtime_i2; + input fabric_spi_cs_holdtime_i3; + input fabric_spi_cs_holdtime_i4; + input fabric_spi_cs_holdtime_i5; + input fabric_spi_cs_holdtime_i6; + input fabric_spi_cs_holdtime_i7; + input fabric_spi_cs_holdtime_i8; + input fabric_spi_cs_holdtime_i9; + input fabric_spi_cs_offtime_i1; + input fabric_spi_cs_offtime_i10; + input fabric_spi_cs_offtime_i11; + input fabric_spi_cs_offtime_i12; + input fabric_spi_cs_offtime_i2; + input fabric_spi_cs_offtime_i3; + input fabric_spi_cs_offtime_i4; + input fabric_spi_cs_offtime_i5; + input fabric_spi_cs_offtime_i6; + input fabric_spi_cs_offtime_i7; + input fabric_spi_cs_offtime_i8; + input fabric_spi_cs_offtime_i9; + input fabric_spi_cs_setuptime_i1; + input fabric_spi_cs_setuptime_i10; + input fabric_spi_cs_setuptime_i11; + input fabric_spi_cs_setuptime_i12; + input fabric_spi_cs_setuptime_i2; + input fabric_spi_cs_setuptime_i3; + input fabric_spi_cs_setuptime_i4; + input fabric_spi_cs_setuptime_i5; + input fabric_spi_cs_setuptime_i6; + input fabric_spi_cs_setuptime_i7; + input fabric_spi_cs_setuptime_i8; + input fabric_spi_cs_setuptime_i9; + input fabric_spi_data_in_unlimited_i1; + input fabric_spi_data_in_unlimited_i2; + input fabric_spi_data_in_unlimited_i3; + input fabric_spi_enable_i1; + input fabric_spi_enable_i2; + input fabric_spi_enable_i3; + output fabric_spi_error_endianness_o1; + output fabric_spi_error_endianness_o2; + output fabric_spi_error_endianness_o3; + output fabric_spi_error_loopback_o1; + output fabric_spi_error_loopback_o2; + output fabric_spi_error_loopback_o3; + output fabric_spi_error_mode_o1; + output fabric_spi_error_mode_o2; + output fabric_spi_error_mode_o3; + output fabric_spi_error_sel_o1; + output fabric_spi_error_sel_o2; + output fabric_spi_error_sel_o3; + input fabric_spi_fifo_arst_tmr_n_i1; + input fabric_spi_fifo_arst_tmr_n_i2; + input fabric_spi_fifo_arst_tmr_n_i3; + input fabric_spi_fifo_arst_tmr_n_i4; + input fabric_spi_fifo_arst_tmr_n_i5; + input fabric_spi_fifo_arst_tmr_n_i6; + input fabric_spi_fifo_arst_tmr_n_i7; + input fabric_spi_fifo_arst_tmr_n_i8; + input fabric_spi_fifo_arst_tmr_n_i9; + output fabric_spi_init_done_o1; + output fabric_spi_init_done_o2; + output fabric_spi_init_done_o3; + input fabric_spi_legacy_enable_i1; + input fabric_spi_legacy_enable_i2; + input fabric_spi_legacy_enable_i3; + input fabric_spi_legacy_master_i1; + input fabric_spi_legacy_master_i2; + input fabric_spi_legacy_master_i3; + input fabric_spi_loopback_i1; + input fabric_spi_loopback_i2; + input fabric_spi_loopback_i3; + input fabric_spi_lsb_first_i1; + input fabric_spi_lsb_first_i2; + input fabric_spi_lsb_first_i3; + output fabric_spi_miso_data_inv_o1; + output fabric_spi_miso_data_inv_o2; + output fabric_spi_miso_data_inv_o3; + output fabric_spi_miso_data_o1; + output fabric_spi_miso_data_o10; + output fabric_spi_miso_data_o11; + output fabric_spi_miso_data_o12; + output fabric_spi_miso_data_o13; + output fabric_spi_miso_data_o14; + output fabric_spi_miso_data_o15; + output fabric_spi_miso_data_o16; + output fabric_spi_miso_data_o17; + output fabric_spi_miso_data_o18; + output fabric_spi_miso_data_o19; + output fabric_spi_miso_data_o2; + output fabric_spi_miso_data_o20; + output fabric_spi_miso_data_o21; + output fabric_spi_miso_data_o22; + output fabric_spi_miso_data_o23; + output fabric_spi_miso_data_o24; + output fabric_spi_miso_data_o3; + output fabric_spi_miso_data_o4; + output fabric_spi_miso_data_o5; + output fabric_spi_miso_data_o6; + output fabric_spi_miso_data_o7; + output fabric_spi_miso_data_o8; + output fabric_spi_miso_data_o9; + output fabric_spi_miso_empty_o1; + output fabric_spi_miso_empty_o2; + output fabric_spi_miso_empty_o3; + input fabric_spi_miso_pop_i1; + input fabric_spi_miso_pop_i2; + input fabric_spi_miso_pop_i3; + input fabric_spi_mosi_data_i1; + input fabric_spi_mosi_data_i10; + input fabric_spi_mosi_data_i11; + input fabric_spi_mosi_data_i12; + input fabric_spi_mosi_data_i13; + input fabric_spi_mosi_data_i14; + input fabric_spi_mosi_data_i15; + input fabric_spi_mosi_data_i16; + input fabric_spi_mosi_data_i17; + input fabric_spi_mosi_data_i18; + input fabric_spi_mosi_data_i19; + input fabric_spi_mosi_data_i2; + input fabric_spi_mosi_data_i20; + input fabric_spi_mosi_data_i21; + input fabric_spi_mosi_data_i22; + input fabric_spi_mosi_data_i23; + input fabric_spi_mosi_data_i24; + input fabric_spi_mosi_data_i3; + input fabric_spi_mosi_data_i4; + input fabric_spi_mosi_data_i5; + input fabric_spi_mosi_data_i6; + input fabric_spi_mosi_data_i7; + input fabric_spi_mosi_data_i8; + input fabric_spi_mosi_data_i9; + input fabric_spi_mosi_data_inv_i1; + input fabric_spi_mosi_data_inv_i2; + input fabric_spi_mosi_data_inv_i3; + output fabric_spi_mosi_full_o1; + output fabric_spi_mosi_full_o2; + output fabric_spi_mosi_full_o3; + input fabric_spi_mosi_push_i1; + input fabric_spi_mosi_push_i2; + input fabric_spi_mosi_push_i3; + input fabric_spi_needed_i1; + input fabric_spi_needed_i2; + input fabric_spi_needed_i3; + input fabric_spi_powerdown_cycle_i1; + input fabric_spi_powerdown_cycle_i10; + input fabric_spi_powerdown_cycle_i11; + input fabric_spi_powerdown_cycle_i12; + input fabric_spi_powerdown_cycle_i13; + input fabric_spi_powerdown_cycle_i14; + input fabric_spi_powerdown_cycle_i15; + input fabric_spi_powerdown_cycle_i16; + input fabric_spi_powerdown_cycle_i17; + input fabric_spi_powerdown_cycle_i18; + input fabric_spi_powerdown_cycle_i19; + input fabric_spi_powerdown_cycle_i2; + input fabric_spi_powerdown_cycle_i20; + input fabric_spi_powerdown_cycle_i21; + input fabric_spi_powerdown_cycle_i22; + input fabric_spi_powerdown_cycle_i23; + input fabric_spi_powerdown_cycle_i24; + input fabric_spi_powerdown_cycle_i25; + input fabric_spi_powerdown_cycle_i26; + input fabric_spi_powerdown_cycle_i27; + input fabric_spi_powerdown_cycle_i28; + input fabric_spi_powerdown_cycle_i29; + input fabric_spi_powerdown_cycle_i3; + input fabric_spi_powerdown_cycle_i30; + input fabric_spi_powerdown_cycle_i31; + input fabric_spi_powerdown_cycle_i32; + input fabric_spi_powerdown_cycle_i33; + input fabric_spi_powerdown_cycle_i34; + input fabric_spi_powerdown_cycle_i35; + input fabric_spi_powerdown_cycle_i36; + input fabric_spi_powerdown_cycle_i37; + input fabric_spi_powerdown_cycle_i38; + input fabric_spi_powerdown_cycle_i39; + input fabric_spi_powerdown_cycle_i4; + input fabric_spi_powerdown_cycle_i40; + input fabric_spi_powerdown_cycle_i41; + input fabric_spi_powerdown_cycle_i42; + input fabric_spi_powerdown_cycle_i43; + input fabric_spi_powerdown_cycle_i44; + input fabric_spi_powerdown_cycle_i45; + input fabric_spi_powerdown_cycle_i46; + input fabric_spi_powerdown_cycle_i47; + input fabric_spi_powerdown_cycle_i48; + input fabric_spi_powerdown_cycle_i5; + input fabric_spi_powerdown_cycle_i6; + input fabric_spi_powerdown_cycle_i7; + input fabric_spi_powerdown_cycle_i8; + input fabric_spi_powerdown_cycle_i9; + input fabric_spi_powerup_cycle_i1; + input fabric_spi_powerup_cycle_i10; + input fabric_spi_powerup_cycle_i11; + input fabric_spi_powerup_cycle_i12; + input fabric_spi_powerup_cycle_i13; + input fabric_spi_powerup_cycle_i14; + input fabric_spi_powerup_cycle_i15; + input fabric_spi_powerup_cycle_i16; + input fabric_spi_powerup_cycle_i17; + input fabric_spi_powerup_cycle_i18; + input fabric_spi_powerup_cycle_i19; + input fabric_spi_powerup_cycle_i2; + input fabric_spi_powerup_cycle_i20; + input fabric_spi_powerup_cycle_i21; + input fabric_spi_powerup_cycle_i22; + input fabric_spi_powerup_cycle_i23; + input fabric_spi_powerup_cycle_i24; + input fabric_spi_powerup_cycle_i25; + input fabric_spi_powerup_cycle_i26; + input fabric_spi_powerup_cycle_i27; + input fabric_spi_powerup_cycle_i28; + input fabric_spi_powerup_cycle_i29; + input fabric_spi_powerup_cycle_i3; + input fabric_spi_powerup_cycle_i30; + input fabric_spi_powerup_cycle_i31; + input fabric_spi_powerup_cycle_i32; + input fabric_spi_powerup_cycle_i33; + input fabric_spi_powerup_cycle_i34; + input fabric_spi_powerup_cycle_i35; + input fabric_spi_powerup_cycle_i36; + input fabric_spi_powerup_cycle_i37; + input fabric_spi_powerup_cycle_i38; + input fabric_spi_powerup_cycle_i39; + input fabric_spi_powerup_cycle_i4; + input fabric_spi_powerup_cycle_i40; + input fabric_spi_powerup_cycle_i41; + input fabric_spi_powerup_cycle_i42; + input fabric_spi_powerup_cycle_i43; + input fabric_spi_powerup_cycle_i44; + input fabric_spi_powerup_cycle_i45; + input fabric_spi_powerup_cycle_i46; + input fabric_spi_powerup_cycle_i47; + input fabric_spi_powerup_cycle_i48; + input fabric_spi_powerup_cycle_i5; + input fabric_spi_powerup_cycle_i6; + input fabric_spi_powerup_cycle_i7; + input fabric_spi_powerup_cycle_i8; + input fabric_spi_powerup_cycle_i9; + input fabric_spi_rst_n_i1; + input fabric_spi_rst_n_i2; + input fabric_spi_rst_n_i3; + input fabric_spi_sck_i0; + input fabric_spi_sck_i1; + input fabric_spi_sck_i2; + input fabric_spi_vcc_enable_i1; + input fabric_spi_vcc_enable_i2; + input fabric_spi_vcc_enable_i3; + output fabric_spi_vcc_used_o1; + output fabric_spi_vcc_used_o2; + output fabric_spi_vcc_used_o3; + input fabric_spw0_apb_slv_paddr_i1; + input fabric_spw0_apb_slv_paddr_i2; + input fabric_spw0_apb_slv_paddr_i3; + input fabric_spw0_apb_slv_paddr_i4; + input fabric_spw0_apb_slv_paddr_i5; + input fabric_spw0_apb_slv_penable_i; + output fabric_spw0_apb_slv_prdata_o1; + output fabric_spw0_apb_slv_prdata_o10; + output fabric_spw0_apb_slv_prdata_o11; + output fabric_spw0_apb_slv_prdata_o12; + output fabric_spw0_apb_slv_prdata_o13; + output fabric_spw0_apb_slv_prdata_o14; + output fabric_spw0_apb_slv_prdata_o15; + output fabric_spw0_apb_slv_prdata_o16; + output fabric_spw0_apb_slv_prdata_o17; + output fabric_spw0_apb_slv_prdata_o18; + output fabric_spw0_apb_slv_prdata_o19; + output fabric_spw0_apb_slv_prdata_o2; + output fabric_spw0_apb_slv_prdata_o20; + output fabric_spw0_apb_slv_prdata_o21; + output fabric_spw0_apb_slv_prdata_o22; + output fabric_spw0_apb_slv_prdata_o23; + output fabric_spw0_apb_slv_prdata_o24; + output fabric_spw0_apb_slv_prdata_o25; + output fabric_spw0_apb_slv_prdata_o26; + output fabric_spw0_apb_slv_prdata_o27; + output fabric_spw0_apb_slv_prdata_o28; + output fabric_spw0_apb_slv_prdata_o29; + output fabric_spw0_apb_slv_prdata_o3; + output fabric_spw0_apb_slv_prdata_o30; + output fabric_spw0_apb_slv_prdata_o31; + output fabric_spw0_apb_slv_prdata_o4; + output fabric_spw0_apb_slv_prdata_o5; + output fabric_spw0_apb_slv_prdata_o6; + output fabric_spw0_apb_slv_prdata_o7; + output fabric_spw0_apb_slv_prdata_o8; + output fabric_spw0_apb_slv_prdata_o9; + output fabric_spw0_apb_slv_pready_o; + input fabric_spw0_apb_slv_psel_i; + output fabric_spw0_apb_slv_pslverr_o; + input fabric_spw0_apb_slv_pwdata_i1; + input fabric_spw0_apb_slv_pwdata_i10; + input fabric_spw0_apb_slv_pwdata_i11; + input fabric_spw0_apb_slv_pwdata_i12; + input fabric_spw0_apb_slv_pwdata_i13; + input fabric_spw0_apb_slv_pwdata_i14; + input fabric_spw0_apb_slv_pwdata_i15; + input fabric_spw0_apb_slv_pwdata_i16; + input fabric_spw0_apb_slv_pwdata_i17; + input fabric_spw0_apb_slv_pwdata_i18; + input fabric_spw0_apb_slv_pwdata_i19; + input fabric_spw0_apb_slv_pwdata_i2; + input fabric_spw0_apb_slv_pwdata_i20; + input fabric_spw0_apb_slv_pwdata_i21; + input fabric_spw0_apb_slv_pwdata_i22; + input fabric_spw0_apb_slv_pwdata_i23; + input fabric_spw0_apb_slv_pwdata_i24; + input fabric_spw0_apb_slv_pwdata_i25; + input fabric_spw0_apb_slv_pwdata_i26; + input fabric_spw0_apb_slv_pwdata_i27; + input fabric_spw0_apb_slv_pwdata_i28; + input fabric_spw0_apb_slv_pwdata_i29; + input fabric_spw0_apb_slv_pwdata_i3; + input fabric_spw0_apb_slv_pwdata_i30; + input fabric_spw0_apb_slv_pwdata_i31; + input fabric_spw0_apb_slv_pwdata_i4; + input fabric_spw0_apb_slv_pwdata_i5; + input fabric_spw0_apb_slv_pwdata_i6; + input fabric_spw0_apb_slv_pwdata_i7; + input fabric_spw0_apb_slv_pwdata_i8; + input fabric_spw0_apb_slv_pwdata_i9; + input fabric_spw0_apb_slv_pwrite_i; + input fabric_spw0_clk_i; + input fabric_spw0_clk_tx_i; + input fabric_spw0_rst_n_i; + output fabric_spw0_rx_fifo_data_o1; + output fabric_spw0_rx_fifo_data_o2; + output fabric_spw0_rx_fifo_data_o3; + output fabric_spw0_rx_fifo_data_o4; + output fabric_spw0_rx_fifo_data_o5; + output fabric_spw0_rx_fifo_data_o6; + output fabric_spw0_rx_fifo_data_o7; + output fabric_spw0_rx_fifo_data_o8; + output fabric_spw0_rx_fifo_data_o9; + output fabric_spw0_rx_fifo_empty_o; + input fabric_spw0_rx_fifo_read_i; + input fabric_spw0_tick_ctm_i; + output fabric_spw0_tick_ctm_o; + input fabric_spw0_tx_fifo_data_i1; + input fabric_spw0_tx_fifo_data_i2; + input fabric_spw0_tx_fifo_data_i3; + input fabric_spw0_tx_fifo_data_i4; + input fabric_spw0_tx_fifo_data_i5; + input fabric_spw0_tx_fifo_data_i6; + input fabric_spw0_tx_fifo_data_i7; + input fabric_spw0_tx_fifo_data_i8; + input fabric_spw0_tx_fifo_data_i9; + output fabric_spw0_tx_fifo_full_o; + input fabric_spw0_tx_fifo_write_i; + output fabric_spw0_user_shared_o; + input fabric_spw1_apb_slv_paddr_i1; + input fabric_spw1_apb_slv_paddr_i2; + input fabric_spw1_apb_slv_paddr_i3; + input fabric_spw1_apb_slv_paddr_i4; + input fabric_spw1_apb_slv_paddr_i5; + input fabric_spw1_apb_slv_penable_i; + output fabric_spw1_apb_slv_prdata_o1; + output fabric_spw1_apb_slv_prdata_o10; + output fabric_spw1_apb_slv_prdata_o11; + output fabric_spw1_apb_slv_prdata_o12; + output fabric_spw1_apb_slv_prdata_o13; + output fabric_spw1_apb_slv_prdata_o14; + output fabric_spw1_apb_slv_prdata_o15; + output fabric_spw1_apb_slv_prdata_o16; + output fabric_spw1_apb_slv_prdata_o17; + output fabric_spw1_apb_slv_prdata_o18; + output fabric_spw1_apb_slv_prdata_o19; + output fabric_spw1_apb_slv_prdata_o2; + output fabric_spw1_apb_slv_prdata_o20; + output fabric_spw1_apb_slv_prdata_o21; + output fabric_spw1_apb_slv_prdata_o22; + output fabric_spw1_apb_slv_prdata_o23; + output fabric_spw1_apb_slv_prdata_o24; + output fabric_spw1_apb_slv_prdata_o25; + output fabric_spw1_apb_slv_prdata_o26; + output fabric_spw1_apb_slv_prdata_o27; + output fabric_spw1_apb_slv_prdata_o28; + output fabric_spw1_apb_slv_prdata_o29; + output fabric_spw1_apb_slv_prdata_o3; + output fabric_spw1_apb_slv_prdata_o30; + output fabric_spw1_apb_slv_prdata_o31; + output fabric_spw1_apb_slv_prdata_o4; + output fabric_spw1_apb_slv_prdata_o5; + output fabric_spw1_apb_slv_prdata_o6; + output fabric_spw1_apb_slv_prdata_o7; + output fabric_spw1_apb_slv_prdata_o8; + output fabric_spw1_apb_slv_prdata_o9; + output fabric_spw1_apb_slv_pready_o; + input fabric_spw1_apb_slv_psel_i; + output fabric_spw1_apb_slv_pslverr_o; + input fabric_spw1_apb_slv_pwdata_i1; + input fabric_spw1_apb_slv_pwdata_i10; + input fabric_spw1_apb_slv_pwdata_i11; + input fabric_spw1_apb_slv_pwdata_i12; + input fabric_spw1_apb_slv_pwdata_i13; + input fabric_spw1_apb_slv_pwdata_i14; + input fabric_spw1_apb_slv_pwdata_i15; + input fabric_spw1_apb_slv_pwdata_i16; + input fabric_spw1_apb_slv_pwdata_i17; + input fabric_spw1_apb_slv_pwdata_i18; + input fabric_spw1_apb_slv_pwdata_i19; + input fabric_spw1_apb_slv_pwdata_i2; + input fabric_spw1_apb_slv_pwdata_i20; + input fabric_spw1_apb_slv_pwdata_i21; + input fabric_spw1_apb_slv_pwdata_i22; + input fabric_spw1_apb_slv_pwdata_i23; + input fabric_spw1_apb_slv_pwdata_i24; + input fabric_spw1_apb_slv_pwdata_i25; + input fabric_spw1_apb_slv_pwdata_i26; + input fabric_spw1_apb_slv_pwdata_i27; + input fabric_spw1_apb_slv_pwdata_i28; + input fabric_spw1_apb_slv_pwdata_i29; + input fabric_spw1_apb_slv_pwdata_i3; + input fabric_spw1_apb_slv_pwdata_i30; + input fabric_spw1_apb_slv_pwdata_i31; + input fabric_spw1_apb_slv_pwdata_i4; + input fabric_spw1_apb_slv_pwdata_i5; + input fabric_spw1_apb_slv_pwdata_i6; + input fabric_spw1_apb_slv_pwdata_i7; + input fabric_spw1_apb_slv_pwdata_i8; + input fabric_spw1_apb_slv_pwdata_i9; + input fabric_spw1_apb_slv_pwrite_i; + input fabric_spw1_clk_i; + input fabric_spw1_clk_tx_i; + input fabric_spw1_rst_n_i; + output fabric_spw1_rx_fifo_data_o1; + output fabric_spw1_rx_fifo_data_o2; + output fabric_spw1_rx_fifo_data_o3; + output fabric_spw1_rx_fifo_data_o4; + output fabric_spw1_rx_fifo_data_o5; + output fabric_spw1_rx_fifo_data_o6; + output fabric_spw1_rx_fifo_data_o7; + output fabric_spw1_rx_fifo_data_o8; + output fabric_spw1_rx_fifo_data_o9; + output fabric_spw1_rx_fifo_empty_o; + input fabric_spw1_rx_fifo_read_i; + input fabric_spw1_tick_ctm_i; + output fabric_spw1_tick_ctm_o; + input fabric_spw1_tx_fifo_data_i1; + input fabric_spw1_tx_fifo_data_i2; + input fabric_spw1_tx_fifo_data_i3; + input fabric_spw1_tx_fifo_data_i4; + input fabric_spw1_tx_fifo_data_i5; + input fabric_spw1_tx_fifo_data_i6; + input fabric_spw1_tx_fifo_data_i7; + input fabric_spw1_tx_fifo_data_i8; + input fabric_spw1_tx_fifo_data_i9; + output fabric_spw1_tx_fifo_full_o; + input fabric_spw1_tx_fifo_write_i; + output fabric_spw1_user_shared_o; + output fabric_status_cold_start_o; + input fabric_thsens_arst_tmr_n_i1; + input fabric_thsens_arst_tmr_n_i2; + input fabric_thsens_arst_tmr_n_i3; + input fabric_thsens_clk_div_ratio_i1; + input fabric_thsens_clk_div_ratio_i2; + input fabric_thsens_clk_div_ratio_i3; + input fabric_thsens_clk_div_ratio_i4; + input fabric_thsens_clk_div_ratio_i5; + input fabric_thsens_clk_div_ratio_i6; + input fabric_thsens_clk_div_ratio_i7; + input fabric_thsens_clk_div_ratio_i8; + input fabric_thsens_clk_i; + output fabric_thsens_fm_config_r_o1; + output fabric_thsens_fm_config_r_o10; + output fabric_thsens_fm_config_r_o11; + output fabric_thsens_fm_config_r_o12; + output fabric_thsens_fm_config_r_o13; + output fabric_thsens_fm_config_r_o14; + output fabric_thsens_fm_config_r_o15; + output fabric_thsens_fm_config_r_o16; + output fabric_thsens_fm_config_r_o17; + output fabric_thsens_fm_config_r_o18; + output fabric_thsens_fm_config_r_o19; + output fabric_thsens_fm_config_r_o2; + output fabric_thsens_fm_config_r_o20; + output fabric_thsens_fm_config_r_o21; + output fabric_thsens_fm_config_r_o22; + output fabric_thsens_fm_config_r_o23; + output fabric_thsens_fm_config_r_o24; + output fabric_thsens_fm_config_r_o25; + output fabric_thsens_fm_config_r_o26; + output fabric_thsens_fm_config_r_o27; + output fabric_thsens_fm_config_r_o3; + output fabric_thsens_fm_config_r_o4; + output fabric_thsens_fm_config_r_o5; + output fabric_thsens_fm_config_r_o6; + output fabric_thsens_fm_config_r_o7; + output fabric_thsens_fm_config_r_o8; + output fabric_thsens_fm_config_r_o9; + input fabric_thsens_fm_config_w_i1; + input fabric_thsens_fm_config_w_i10; + input fabric_thsens_fm_config_w_i11; + input fabric_thsens_fm_config_w_i12; + input fabric_thsens_fm_config_w_i13; + input fabric_thsens_fm_config_w_i14; + input fabric_thsens_fm_config_w_i15; + input fabric_thsens_fm_config_w_i16; + input fabric_thsens_fm_config_w_i17; + input fabric_thsens_fm_config_w_i18; + input fabric_thsens_fm_config_w_i19; + input fabric_thsens_fm_config_w_i2; + input fabric_thsens_fm_config_w_i20; + input fabric_thsens_fm_config_w_i21; + input fabric_thsens_fm_config_w_i22; + input fabric_thsens_fm_config_w_i23; + input fabric_thsens_fm_config_w_i24; + input fabric_thsens_fm_config_w_i25; + input fabric_thsens_fm_config_w_i26; + input fabric_thsens_fm_config_w_i27; + input fabric_thsens_fm_config_w_i3; + input fabric_thsens_fm_config_w_i4; + input fabric_thsens_fm_config_w_i5; + input fabric_thsens_fm_config_w_i6; + input fabric_thsens_fm_config_w_i7; + input fabric_thsens_fm_config_w_i8; + input fabric_thsens_fm_config_w_i9; + input fabric_thsens_fm_config_wen_i; + output fabric_thsens_fm_data_o1; + output fabric_thsens_fm_data_o10; + output fabric_thsens_fm_data_o11; + output fabric_thsens_fm_data_o12; + output fabric_thsens_fm_data_o13; + output fabric_thsens_fm_data_o14; + output fabric_thsens_fm_data_o2; + output fabric_thsens_fm_data_o3; + output fabric_thsens_fm_data_o4; + output fabric_thsens_fm_data_o5; + output fabric_thsens_fm_data_o6; + output fabric_thsens_fm_data_o7; + output fabric_thsens_fm_data_o8; + output fabric_thsens_fm_data_o9; + input fabric_thsens_fm_enable_i; + output fabric_thsens_fm_mode_r_o1; + output fabric_thsens_fm_mode_r_o10; + output fabric_thsens_fm_mode_r_o11; + output fabric_thsens_fm_mode_r_o12; + output fabric_thsens_fm_mode_r_o13; + output fabric_thsens_fm_mode_r_o14; + output fabric_thsens_fm_mode_r_o15; + output fabric_thsens_fm_mode_r_o16; + output fabric_thsens_fm_mode_r_o17; + output fabric_thsens_fm_mode_r_o18; + output fabric_thsens_fm_mode_r_o19; + output fabric_thsens_fm_mode_r_o2; + output fabric_thsens_fm_mode_r_o20; + output fabric_thsens_fm_mode_r_o21; + output fabric_thsens_fm_mode_r_o22; + output fabric_thsens_fm_mode_r_o23; + output fabric_thsens_fm_mode_r_o24; + output fabric_thsens_fm_mode_r_o25; + output fabric_thsens_fm_mode_r_o26; + output fabric_thsens_fm_mode_r_o27; + output fabric_thsens_fm_mode_r_o28; + output fabric_thsens_fm_mode_r_o29; + output fabric_thsens_fm_mode_r_o3; + output fabric_thsens_fm_mode_r_o30; + output fabric_thsens_fm_mode_r_o31; + output fabric_thsens_fm_mode_r_o32; + output fabric_thsens_fm_mode_r_o4; + output fabric_thsens_fm_mode_r_o5; + output fabric_thsens_fm_mode_r_o6; + output fabric_thsens_fm_mode_r_o7; + output fabric_thsens_fm_mode_r_o8; + output fabric_thsens_fm_mode_r_o9; + input fabric_thsens_fm_mode_w_i1; + input fabric_thsens_fm_mode_w_i10; + input fabric_thsens_fm_mode_w_i11; + input fabric_thsens_fm_mode_w_i12; + input fabric_thsens_fm_mode_w_i13; + input fabric_thsens_fm_mode_w_i14; + input fabric_thsens_fm_mode_w_i15; + input fabric_thsens_fm_mode_w_i16; + input fabric_thsens_fm_mode_w_i17; + input fabric_thsens_fm_mode_w_i18; + input fabric_thsens_fm_mode_w_i19; + input fabric_thsens_fm_mode_w_i2; + input fabric_thsens_fm_mode_w_i20; + input fabric_thsens_fm_mode_w_i21; + input fabric_thsens_fm_mode_w_i22; + input fabric_thsens_fm_mode_w_i23; + input fabric_thsens_fm_mode_w_i24; + input fabric_thsens_fm_mode_w_i25; + input fabric_thsens_fm_mode_w_i26; + input fabric_thsens_fm_mode_w_i27; + input fabric_thsens_fm_mode_w_i28; + input fabric_thsens_fm_mode_w_i29; + input fabric_thsens_fm_mode_w_i3; + input fabric_thsens_fm_mode_w_i30; + input fabric_thsens_fm_mode_w_i31; + input fabric_thsens_fm_mode_w_i32; + input fabric_thsens_fm_mode_w_i4; + input fabric_thsens_fm_mode_w_i5; + input fabric_thsens_fm_mode_w_i6; + input fabric_thsens_fm_mode_w_i7; + input fabric_thsens_fm_mode_w_i8; + input fabric_thsens_fm_mode_w_i9; + input fabric_thsens_fm_mode_wen_i; + output fabric_thsens_fm_overflow_o; + output fabric_thsens_fm_valid_o; + output fabric_thsens_otp_config_o1; + output fabric_thsens_otp_config_o10; + output fabric_thsens_otp_config_o11; + output fabric_thsens_otp_config_o12; + output fabric_thsens_otp_config_o13; + output fabric_thsens_otp_config_o14; + output fabric_thsens_otp_config_o15; + output fabric_thsens_otp_config_o16; + output fabric_thsens_otp_config_o17; + output fabric_thsens_otp_config_o18; + output fabric_thsens_otp_config_o19; + output fabric_thsens_otp_config_o2; + output fabric_thsens_otp_config_o20; + output fabric_thsens_otp_config_o21; + output fabric_thsens_otp_config_o22; + output fabric_thsens_otp_config_o23; + output fabric_thsens_otp_config_o24; + output fabric_thsens_otp_config_o25; + output fabric_thsens_otp_config_o26; + output fabric_thsens_otp_config_o27; + output fabric_thsens_otp_config_o3; + output fabric_thsens_otp_config_o4; + output fabric_thsens_otp_config_o5; + output fabric_thsens_otp_config_o6; + output fabric_thsens_otp_config_o7; + output fabric_thsens_otp_config_o8; + output fabric_thsens_otp_config_o9; + input fabric_user_clk_i; + input fabric_user_data_i1; + input fabric_user_data_i10; + input fabric_user_data_i11; + input fabric_user_data_i12; + input fabric_user_data_i13; + input fabric_user_data_i14; + input fabric_user_data_i15; + input fabric_user_data_i16; + input fabric_user_data_i17; + input fabric_user_data_i18; + input fabric_user_data_i19; + input fabric_user_data_i2; + input fabric_user_data_i20; + input fabric_user_data_i21; + input fabric_user_data_i22; + input fabric_user_data_i23; + input fabric_user_data_i24; + input fabric_user_data_i25; + input fabric_user_data_i26; + input fabric_user_data_i27; + input fabric_user_data_i28; + input fabric_user_data_i29; + input fabric_user_data_i3; + input fabric_user_data_i30; + input fabric_user_data_i31; + input fabric_user_data_i32; + input fabric_user_data_i4; + input fabric_user_data_i5; + input fabric_user_data_i6; + input fabric_user_data_i7; + input fabric_user_data_i8; + input fabric_user_data_i9; + output fabric_user_data_o1; + output fabric_user_data_o10; + output fabric_user_data_o11; + output fabric_user_data_o12; + output fabric_user_data_o13; + output fabric_user_data_o14; + output fabric_user_data_o15; + output fabric_user_data_o16; + output fabric_user_data_o17; + output fabric_user_data_o18; + output fabric_user_data_o19; + output fabric_user_data_o2; + output fabric_user_data_o20; + output fabric_user_data_o21; + output fabric_user_data_o22; + output fabric_user_data_o23; + output fabric_user_data_o24; + output fabric_user_data_o25; + output fabric_user_data_o26; + output fabric_user_data_o27; + output fabric_user_data_o28; + output fabric_user_data_o29; + output fabric_user_data_o3; + output fabric_user_data_o30; + output fabric_user_data_o31; + output fabric_user_data_o32; + output fabric_user_data_o4; + output fabric_user_data_o5; + output fabric_user_data_o6; + output fabric_user_data_o7; + output fabric_user_data_o8; + output fabric_user_data_o9; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_IF_U_FULL(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_data_from_bist_i1, fabric_mrepair_data_from_bist_i2, fabric_mrepair_data_from_bist_i3, fabric_mrepair_data_from_bist_i4, fabric_mrepair_data_from_bist_i5, fabric_mrepair_data_from_bist_i6, fabric_mrepair_data_from_bist_i7, fabric_mrepair_data_from_bist_i8, fabric_mrepair_data_from_bist_i9, fabric_mrepair_data_from_bist_i10, fabric_mrepair_data_from_bist_i11, fabric_mrepair_data_from_bist_i12, fabric_mrepair_data_from_bist_i13, fabric_mrepair_data_from_bist_i14 +, fabric_mrepair_data_from_bist_i15, fabric_mrepair_data_from_bist_i16, fabric_mrepair_data_from_bist_i17, fabric_mrepair_data_from_bist_i18, fabric_mrepair_data_from_bist_i19, fabric_mrepair_data_from_bist_i20, fabric_mrepair_data_from_bist_i21, fabric_mrepair_data_from_bist_i22, fabric_mrepair_data_from_bist_i23, fabric_mrepair_data_from_bist_i24, fabric_mrepair_data_from_bist_i25, fabric_mrepair_data_from_bist_i26, fabric_mrepair_data_to_bist_o1, fabric_mrepair_data_to_bist_o2, fabric_mrepair_data_to_bist_o3, fabric_mrepair_data_to_bist_o4, fabric_mrepair_data_to_bist_o5, fabric_mrepair_data_to_bist_o6, fabric_mrepair_data_to_bist_o7, fabric_mrepair_data_to_bist_o8, fabric_mrepair_data_to_bist_o9 +, fabric_mrepair_data_to_bist_o10, fabric_mrepair_data_to_bist_o11, fabric_mrepair_data_to_bist_o12, fabric_mrepair_data_to_bist_o13, fabric_mrepair_data_to_bist_o14, fabric_mrepair_data_to_bist_o15, fabric_mrepair_data_to_bist_o16, fabric_mrepair_data_to_bist_o17, fabric_mrepair_data_to_bist_o18, fabric_mrepair_data_to_bist_o19, fabric_mrepair_data_to_bist_o20, fabric_mrepair_data_to_bist_o21, fabric_mrepair_data_to_bist_o22, fabric_mrepair_data_to_bist_o23, fabric_mrepair_data_to_bist_o24, fabric_mrepair_data_to_bist_o25, fabric_mrepair_data_to_bist_o26, fabric_mrepair_shift_en_to_bist_o1, fabric_mrepair_shift_en_to_bist_o2, fabric_mrepair_shift_en_to_bist_o3, fabric_mrepair_shift_en_to_bist_o4 +, fabric_mrepair_shift_en_to_bist_o5, fabric_mrepair_shift_en_to_bist_o6, fabric_mrepair_shift_en_to_bist_o7, fabric_mrepair_shift_en_to_bist_o8, fabric_mrepair_shift_en_to_bist_o9, fabric_mrepair_shift_en_to_bist_o10, fabric_mrepair_shift_en_to_bist_o11, fabric_mrepair_shift_en_to_bist_o12, fabric_mrepair_shift_en_to_bist_o13, fabric_mrepair_shift_en_to_bist_o14, fabric_mrepair_shift_en_to_bist_o15, fabric_mrepair_shift_en_to_bist_o16, fabric_mrepair_shift_en_to_bist_o17, fabric_mrepair_shift_en_to_bist_o18, fabric_mrepair_shift_en_to_bist_o19, fabric_mrepair_shift_en_to_bist_o20, fabric_mrepair_shift_en_to_bist_o21, fabric_mrepair_shift_en_to_bist_o22, fabric_mrepair_shift_en_to_bist_o23, fabric_mrepair_shift_en_to_bist_o24, fabric_mrepair_shift_en_to_bist_o25 +, fabric_mrepair_shift_en_to_bist_o26, fabric_mrepair_sif_load_en_to_bist_o1, fabric_mrepair_sif_load_en_to_bist_o2, fabric_mrepair_sif_load_en_to_bist_o3, fabric_mrepair_sif_load_en_to_bist_o4, fabric_mrepair_sif_load_en_to_bist_o5, fabric_mrepair_sif_load_en_to_bist_o6, fabric_mrepair_sif_load_en_to_bist_o7, fabric_mrepair_sif_load_en_to_bist_o8, fabric_mrepair_sif_load_en_to_bist_o9, fabric_mrepair_sif_load_en_to_bist_o10, fabric_mrepair_sif_load_en_to_bist_o11, fabric_mrepair_sif_load_en_to_bist_o12, fabric_mrepair_sif_load_en_to_bist_o13, fabric_mrepair_sif_load_en_to_bist_o14, fabric_mrepair_sif_load_en_to_bist_o15, fabric_mrepair_sif_load_en_to_bist_o16, fabric_mrepair_sif_load_en_to_bist_o17, fabric_mrepair_sif_load_en_to_bist_o18, fabric_mrepair_sif_load_en_to_bist_o19, fabric_mrepair_sif_load_en_to_bist_o20 +, fabric_mrepair_sif_load_en_to_bist_o21, fabric_mrepair_sif_load_en_to_bist_o22, fabric_mrepair_sif_load_en_to_bist_o23, fabric_mrepair_sif_load_en_to_bist_o24, fabric_mrepair_sif_load_en_to_bist_o25, fabric_mrepair_sif_load_en_to_bist_o26, fabric_mrepair_sif_update_en_to_bist_o1, fabric_mrepair_sif_update_en_to_bist_o2, fabric_mrepair_sif_update_en_to_bist_o3, fabric_mrepair_sif_update_en_to_bist_o4, fabric_mrepair_sif_update_en_to_bist_o5, fabric_mrepair_sif_update_en_to_bist_o6, fabric_mrepair_sif_update_en_to_bist_o7, fabric_mrepair_sif_update_en_to_bist_o8, fabric_mrepair_sif_update_en_to_bist_o9, fabric_mrepair_sif_update_en_to_bist_o10, fabric_mrepair_sif_update_en_to_bist_o11, fabric_mrepair_sif_update_en_to_bist_o12, fabric_mrepair_sif_update_en_to_bist_o13, fabric_mrepair_sif_update_en_to_bist_o14, fabric_mrepair_sif_update_en_to_bist_o15 +, fabric_mrepair_sif_update_en_to_bist_o16, fabric_mrepair_sif_update_en_to_bist_o17, fabric_mrepair_sif_update_en_to_bist_o18, fabric_mrepair_sif_update_en_to_bist_o19, fabric_mrepair_sif_update_en_to_bist_o20, fabric_mrepair_sif_update_en_to_bist_o21, fabric_mrepair_sif_update_en_to_bist_o22, fabric_mrepair_sif_update_en_to_bist_o23, fabric_mrepair_sif_update_en_to_bist_o24, fabric_mrepair_sif_update_en_to_bist_o25, fabric_mrepair_sif_update_en_to_bist_o26, fabric_mrepair_sif_reg_en_to_bist_o1, fabric_mrepair_sif_reg_en_to_bist_o2, fabric_mrepair_sif_reg_en_to_bist_o3, fabric_mrepair_sif_reg_en_to_bist_o4, fabric_mrepair_sif_reg_en_to_bist_o5, fabric_mrepair_sif_reg_en_to_bist_o6, fabric_mrepair_sif_reg_en_to_bist_o7, fabric_mrepair_sif_reg_en_to_bist_o8, fabric_mrepair_sif_reg_en_to_bist_o9, fabric_mrepair_sif_reg_en_to_bist_o10 +, fabric_mrepair_sif_reg_en_to_bist_o11, fabric_mrepair_sif_reg_en_to_bist_o12, fabric_mrepair_sif_reg_en_to_bist_o13, fabric_mrepair_sif_reg_en_to_bist_o14, fabric_mrepair_sif_reg_en_to_bist_o15, fabric_mrepair_sif_reg_en_to_bist_o16, fabric_mrepair_sif_reg_en_to_bist_o17, fabric_mrepair_sif_reg_en_to_bist_o18, fabric_mrepair_sif_reg_en_to_bist_o19, fabric_mrepair_sif_reg_en_to_bist_o20, fabric_mrepair_sif_reg_en_to_bist_o21, fabric_mrepair_sif_reg_en_to_bist_o22, fabric_mrepair_sif_reg_en_to_bist_o23, fabric_mrepair_sif_reg_en_to_bist_o24, fabric_mrepair_sif_reg_en_to_bist_o25, fabric_mrepair_sif_reg_en_to_bist_o26, fabric_mrepair_system_data_to_mem_bist_i1, fabric_mrepair_system_data_to_mem_bist_i2, fabric_mrepair_system_data_to_mem_bist_i3, fabric_mrepair_system_data_to_mem_bist_i4, fabric_mrepair_system_data_to_mem_bist_i5 +, fabric_mrepair_system_data_to_mem_bist_i6, fabric_mrepair_system_data_to_mem_bist_i7, fabric_mrepair_system_data_to_mem_bist_i8, fabric_mrepair_system_data_to_mem_bist_i9, fabric_mrepair_system_data_to_mem_bist_i10, fabric_mrepair_system_data_to_mem_bist_i11, fabric_mrepair_system_data_to_mem_bist_i12, fabric_mrepair_system_data_to_mem_bist_i13, fabric_mrepair_system_data_to_mem_bist_i14, fabric_mrepair_system_data_to_mem_bist_i15, fabric_mrepair_system_data_to_mem_bist_i16, fabric_mrepair_system_data_to_mem_bist_i17, fabric_mrepair_system_data_to_mem_bist_i18, fabric_mrepair_system_data_to_mem_bist_i19, fabric_mrepair_system_data_to_mem_bist_i20, fabric_mrepair_system_data_to_mem_bist_i21, fabric_mrepair_system_data_to_mem_bist_i22, fabric_mrepair_system_data_to_mem_bist_i23, fabric_mrepair_system_data_to_mem_bist_i24, fabric_mrepair_system_data_to_mem_bist_i25, fabric_mrepair_system_data_to_mem_bist_i26 +, fabric_mrepair_shift_en_i1, fabric_mrepair_shift_en_i2, fabric_mrepair_shift_en_i3, fabric_mrepair_shift_en_i4, fabric_mrepair_shift_en_i5, fabric_mrepair_shift_en_i6, fabric_mrepair_shift_en_i7, fabric_mrepair_shift_en_i8, fabric_mrepair_shift_en_i9, fabric_mrepair_shift_en_i10, fabric_mrepair_shift_en_i11, fabric_mrepair_shift_en_i12, fabric_mrepair_shift_en_i13, fabric_mrepair_shift_en_i14, fabric_mrepair_shift_en_i15, fabric_mrepair_shift_en_i16, fabric_mrepair_shift_en_i17, fabric_mrepair_shift_en_i18, fabric_mrepair_shift_en_i19, fabric_mrepair_shift_en_i20, fabric_mrepair_shift_en_i21 +, fabric_mrepair_shift_en_i22, fabric_mrepair_shift_en_i23, fabric_mrepair_shift_en_i24, fabric_mrepair_shift_en_i25, fabric_mrepair_shift_en_i26, fabric_mrepair_sif_load_en_i1, fabric_mrepair_sif_load_en_i2, fabric_mrepair_sif_load_en_i3, fabric_mrepair_sif_load_en_i4, fabric_mrepair_sif_load_en_i5, fabric_mrepair_sif_load_en_i6, fabric_mrepair_sif_load_en_i7, fabric_mrepair_sif_load_en_i8, fabric_mrepair_sif_load_en_i9, fabric_mrepair_sif_load_en_i10, fabric_mrepair_sif_load_en_i11, fabric_mrepair_sif_load_en_i12, fabric_mrepair_sif_load_en_i13, fabric_mrepair_sif_load_en_i14, fabric_mrepair_sif_load_en_i15, fabric_mrepair_sif_load_en_i16 +, fabric_mrepair_sif_load_en_i17, fabric_mrepair_sif_load_en_i18, fabric_mrepair_sif_load_en_i19, fabric_mrepair_sif_load_en_i20, fabric_mrepair_sif_load_en_i21, fabric_mrepair_sif_load_en_i22, fabric_mrepair_sif_load_en_i23, fabric_mrepair_sif_load_en_i24, fabric_mrepair_sif_load_en_i25, fabric_mrepair_sif_load_en_i26, fabric_mrepair_sif_update_en_i1, fabric_mrepair_sif_update_en_i2, fabric_mrepair_sif_update_en_i3, fabric_mrepair_sif_update_en_i4, fabric_mrepair_sif_update_en_i5, fabric_mrepair_sif_update_en_i6, fabric_mrepair_sif_update_en_i7, fabric_mrepair_sif_update_en_i8, fabric_mrepair_sif_update_en_i9, fabric_mrepair_sif_update_en_i10, fabric_mrepair_sif_update_en_i11 +, fabric_mrepair_sif_update_en_i12, fabric_mrepair_sif_update_en_i13, fabric_mrepair_sif_update_en_i14, fabric_mrepair_sif_update_en_i15, fabric_mrepair_sif_update_en_i16, fabric_mrepair_sif_update_en_i17, fabric_mrepair_sif_update_en_i18, fabric_mrepair_sif_update_en_i19, fabric_mrepair_sif_update_en_i20, fabric_mrepair_sif_update_en_i21, fabric_mrepair_sif_update_en_i22, fabric_mrepair_sif_update_en_i23, fabric_mrepair_sif_update_en_i24, fabric_mrepair_sif_update_en_i25, fabric_mrepair_sif_update_en_i26, fabric_mrepair_sif_reg_en_i1, fabric_mrepair_sif_reg_en_i2, fabric_mrepair_sif_reg_en_i3, fabric_mrepair_sif_reg_en_i4, fabric_mrepair_sif_reg_en_i5, fabric_mrepair_sif_reg_en_i6 +, fabric_mrepair_sif_reg_en_i7, fabric_mrepair_sif_reg_en_i8, fabric_mrepair_sif_reg_en_i9, fabric_mrepair_sif_reg_en_i10, fabric_mrepair_sif_reg_en_i11, fabric_mrepair_sif_reg_en_i12, fabric_mrepair_sif_reg_en_i13, fabric_mrepair_sif_reg_en_i14, fabric_mrepair_sif_reg_en_i15, fabric_mrepair_sif_reg_en_i16, fabric_mrepair_sif_reg_en_i17, fabric_mrepair_sif_reg_en_i18, fabric_mrepair_sif_reg_en_i19, fabric_mrepair_sif_reg_en_i20, fabric_mrepair_sif_reg_en_i21, fabric_mrepair_sif_reg_en_i22, fabric_mrepair_sif_reg_en_i23, fabric_mrepair_sif_reg_en_i24, fabric_mrepair_sif_reg_en_i25, fabric_mrepair_sif_reg_en_i26, fabric_mrepair_system_data_from_mem_bist_o1 +, fabric_mrepair_system_data_from_mem_bist_o2, fabric_mrepair_system_data_from_mem_bist_o3, fabric_mrepair_system_data_from_mem_bist_o4, fabric_mrepair_system_data_from_mem_bist_o5, fabric_mrepair_system_data_from_mem_bist_o6, fabric_mrepair_system_data_from_mem_bist_o7, fabric_mrepair_system_data_from_mem_bist_o8, fabric_mrepair_system_data_from_mem_bist_o9, fabric_mrepair_system_data_from_mem_bist_o10, fabric_mrepair_system_data_from_mem_bist_o11, fabric_mrepair_system_data_from_mem_bist_o12, fabric_mrepair_system_data_from_mem_bist_o13, fabric_mrepair_system_data_from_mem_bist_o14, fabric_mrepair_system_data_from_mem_bist_o15, fabric_mrepair_system_data_from_mem_bist_o16, fabric_mrepair_system_data_from_mem_bist_o17, fabric_mrepair_system_data_from_mem_bist_o18, fabric_mrepair_system_data_from_mem_bist_o19, fabric_mrepair_system_data_from_mem_bist_o20, fabric_mrepair_system_data_from_mem_bist_o21, fabric_mrepair_system_data_from_mem_bist_o22 +, fabric_mrepair_system_data_from_mem_bist_o23, fabric_mrepair_system_data_from_mem_bist_o24, fabric_mrepair_system_data_from_mem_bist_o25, fabric_mrepair_system_data_from_mem_bist_o26, fabric_mrepair_bist_mode_o, fabric_mrepair_mem_type_sel_o1, fabric_mrepair_mem_type_sel_o2, fabric_mrepair_mem_type_sel_o3, fabric_mrepair_mem_type_sel_o4, fabric_mrepair_mem_type_sel_o5, fabric_mrepair_mode_sel_o1, fabric_mrepair_mode_sel_o2, fabric_mrepair_mode_sel_o3, fabric_mrepair_mode_sel_o4, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o +, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_mrepair_pd_active_i1, fabric_mrepair_pd_active_i2, fabric_mrepair_pd_active_i3, fabric_mrepair_pd_active_i4, fabric_mrepair_pd_active_i5, fabric_mrepair_pd_active_i6, fabric_mrepair_pd_active_i7, fabric_mrepair_pd_active_i8, fabric_mrepair_pd_active_i9, fabric_mrepair_pd_active_i10, fabric_mrepair_pd_active_i11, fabric_mrepair_pd_active_i12 +, fabric_mrepair_pd_active_i13, fabric_mrepair_pd_active_i14, fabric_mrepair_pd_active_i15, fabric_mrepair_pd_active_i16, fabric_mrepair_pd_active_i17, fabric_mrepair_pd_active_i18, fabric_mrepair_pd_active_i19, fabric_mrepair_pd_active_i20, fabric_mrepair_pd_active_i21, fabric_mrepair_pd_active_i22, fabric_mrepair_pd_active_i23, fabric_mrepair_pd_active_i24, fabric_mrepair_pd_active_i25, fabric_mrepair_pd_active_i26, fabric_mrepair_chip_status_o1, fabric_mrepair_chip_status_o2, fabric_mrepair_chip_status_o3, fabric_mrepair_chip_status_o4, fabric_mrepair_chip_status_o5, fabric_mrepair_chip_status_o6, fabric_mrepair_chip_status_o7 +, fabric_mrepair_chip_status_o8, fabric_mrepair_chip_status_o9, fabric_mrepair_chip_status_o10, fabric_mrepair_chip_status_o11, fabric_mrepair_chip_status_o12, fabric_mrepair_chip_status_o13, fabric_mrepair_chip_status_o14, fabric_mrepair_chip_status_o15, fabric_mrepair_chip_status_o16, fabric_mrepair_chip_status_o17, fabric_mrepair_chip_status_o18, fabric_mrepair_chip_status_o19, fabric_mrepair_chip_status_o20, fabric_mrepair_chip_status_o21, fabric_mrepair_chip_status_o22, fabric_mrepair_chip_status_o23, fabric_mrepair_chip_status_o24, fabric_mrepair_chip_status_o25, fabric_mrepair_chip_status_o26, fabric_mrepair_chip_status_o27, fabric_mrepair_chip_status_o28 +, fabric_mrepair_chip_status_o29, fabric_mrepair_chip_status_o30, fabric_mrepair_chip_status_o31, fabric_mrepair_chip_status_o32, fabric_mrepair_chip_status_o33, fabric_mrepair_chip_status_o34, fabric_mrepair_chip_status_o35, fabric_mrepair_chip_status_o36, fabric_mrepair_chip_status_o37, fabric_mrepair_chip_status_o38, fabric_mrepair_chip_status_o39, fabric_mrepair_chip_status_o40, fabric_mrepair_chip_status_o41, fabric_mrepair_chip_status_o42, fabric_mrepair_chip_status_o43, fabric_mrepair_chip_status_o44, fabric_mrepair_chip_status_o45, fabric_mrepair_chip_status_o46, fabric_mrepair_chip_status_o47, fabric_mrepair_chip_status_o48, fabric_mrepair_chip_status_o49 +, fabric_mrepair_chip_status_o50, fabric_mrepair_chip_status_o51, fabric_mrepair_chip_status_o52, fabric_mrepair_chip_status_o53, fabric_mrepair_chip_status_o54, fabric_mrepair_chip_status_o55, fabric_mrepair_chip_status_o56, fabric_mrepair_chip_status_o57, fabric_mrepair_chip_status_o58, fabric_mrepair_chip_status_o59, fabric_mrepair_chip_status_o60, fabric_mrepair_chip_status_o61, fabric_mrepair_chip_status_o62, fabric_mrepair_chip_status_o63, fabric_mrepair_chip_status_o64, fabric_mrepair_chip_status_o65, fabric_mrepair_chip_status_o66, fabric_mrepair_chip_status_o67, fabric_mrepair_chip_status_o68, fabric_mrepair_chip_status_o69, fabric_mrepair_chip_status_o70 +, fabric_mrepair_chip_status_o71, fabric_mrepair_chip_status_o72, fabric_mrepair_chip_status_o73, fabric_mrepair_chip_status_o74, fabric_mrepair_chip_status_o75, fabric_mrepair_chip_status_o76, fabric_mrepair_chip_status_o77, fabric_mrepair_chip_status_o78, fabric_mrepair_global_chip_status_o1, fabric_mrepair_global_chip_status_o2, fabric_mrepair_global_chip_status_o3, fabric_mrepair_pd_ready_o1, fabric_mrepair_pd_ready_o2, fabric_mrepair_pd_ready_o3, fabric_mrepair_pd_ready_o4, fabric_mrepair_pd_ready_o5, fabric_mrepair_pd_ready_o6, fabric_mrepair_pd_ready_o7, fabric_mrepair_pd_ready_o8, fabric_mrepair_pd_ready_o9, fabric_mrepair_pd_ready_o10 +, fabric_mrepair_pd_ready_o11, fabric_mrepair_pd_ready_o12, fabric_mrepair_pd_ready_o13, fabric_mrepair_pd_ready_o14, fabric_mrepair_pd_ready_o15, fabric_mrepair_pd_ready_o16, fabric_mrepair_pd_ready_o17, fabric_mrepair_pd_ready_o18, fabric_mrepair_pd_ready_o19, fabric_mrepair_pd_ready_o20, fabric_mrepair_pd_ready_o21, fabric_mrepair_pd_ready_o22, fabric_mrepair_pd_ready_o23, fabric_mrepair_pd_ready_o24, fabric_mrepair_pd_ready_o25, fabric_mrepair_pd_ready_o26, fabric_mrepair_system_dataready_o, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i +, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14 +, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35 +, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2 +, fabric_mrepair_fuse_prgwidth_i3, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18 +, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39 +, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o +, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8 +, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o +, fabric_mrepair_fuse_status_o1, fabric_mrepair_fuse_status_o2, fabric_mrepair_fuse_status_o3, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3 +, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16 +, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37 +, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o +, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6 +, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27 +, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3 +, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3 +, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9 +, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30 +, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16 +, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2 +, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23 +, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8 +, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29 +, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18 +, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i +, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3 +, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i +, fabric_jtag_tdo_usr2_i, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20 +, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9 +, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30 +, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17 +, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3 +, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24 +, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_apb_ready_o, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12 +, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_otp_cfg_fabric_apb_en_i +, fabric_otp_cfg_loader_read_en_i, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2 +, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_debug_lifecycle_o1 +, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_debug_frame_use_encryption_o, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2 +, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_debug_key_correct_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_debug_otp_reload_err_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4 +, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25 +, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_enable_TMR_i1, fabric_enable_TMR_i2 +, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20 +, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1 +, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16 +, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37 +, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58 +, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79 +, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100 +, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121 +, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14 +, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35 +, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56 +, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77 +, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98 +, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119 +, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_din_i1, fabric_dac0_din_i2, fabric_dac0_din_i3, fabric_dac0_din_i4, fabric_dac0_din_i5, fabric_dac0_din_i6, fabric_dac0_din_i7, fabric_dac0_din_i8, fabric_dac0_din_i9, fabric_dac0_din_i10 +, fabric_dac0_din_i11, fabric_dac0_din_i12, fabric_dac0_din_i13, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_in_sel_i1, fabric_dac0_comp_in_sel_i2, fabric_dac0_comp_in_sel_i3, fabric_dac0_comp_in_sel_i4, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_res_i1, fabric_cfg_dac0_reg_res_i2, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i +, fabric_dac1_clk_en_i, fabric_dac1_din_i1, fabric_dac1_din_i2, fabric_dac1_din_i3, fabric_dac1_din_i4, fabric_dac1_din_i5, fabric_dac1_din_i6, fabric_dac1_din_i7, fabric_dac1_din_i8, fabric_dac1_din_i9, fabric_dac1_din_i10, fabric_dac1_din_i11, fabric_dac1_din_i12, fabric_dac1_din_i13, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i +, fabric_dac1_comp_in_sel_i1, fabric_dac1_comp_in_sel_i2, fabric_dac1_comp_in_sel_i3, fabric_dac1_comp_in_sel_i4, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_res_i1, fabric_cfg_dac1_reg_res_i2, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_din_i1, fabric_dac2_din_i2, fabric_dac2_din_i3, fabric_dac2_din_i4, fabric_dac2_din_i5, fabric_dac2_din_i6, fabric_dac2_din_i7, fabric_dac2_din_i8, fabric_dac2_din_i9 +, fabric_dac2_din_i10, fabric_dac2_din_i11, fabric_dac2_din_i12, fabric_dac2_din_i13, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_in_sel_i1, fabric_dac2_comp_in_sel_i2, fabric_dac2_comp_in_sel_i3, fabric_dac2_comp_in_sel_i4, fabric_dac2_comp_in_sel_i5, fabric_dac2_comp_in_sel_i6, fabric_dac2_comp_in_sel_i7, fabric_dac2_comp_in_sel_i8, fabric_dac2_comp_in_sel_i9, fabric_dac2_comp_in_sel_i10 +, fabric_dac2_comp_in_sel_i11, fabric_dac2_comp_in_sel_i12, fabric_dac2_comp_in_sel_i13, fabric_dac2_comp_out_o, fabric_cfg_dac2_reg_res_i1, fabric_cfg_dac2_reg_res_i2, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_din_i1, fabric_dac3_din_i2, fabric_dac3_din_i3, fabric_dac3_din_i4, fabric_dac3_din_i5, fabric_dac3_din_i6, fabric_dac3_din_i7, fabric_dac3_din_i8, fabric_dac3_din_i9, fabric_dac3_din_i10 +, fabric_dac3_din_i11, fabric_dac3_din_i12, fabric_dac3_din_i13, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_in_sel_i1, fabric_dac3_comp_in_sel_i2, fabric_dac3_comp_in_sel_i3, fabric_dac3_comp_in_sel_i4, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_res_i1, fabric_cfg_dac3_reg_res_i2, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i +, fabric_adc0_arst_b_tmr_i1, fabric_adc0_arst_b_tmr_i2, fabric_adc0_arst_b_tmr_i3, fabric_adc0_pwr_down_b_tmr_i1, fabric_adc0_pwr_down_b_tmr_i2, fabric_adc0_pwr_down_b_tmr_i3, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_spare_i1, fabric_adc0_spare_i2, fabric_adc0_spare_i3, fabric_adc0_spare_i4, fabric_adc0_spare_i5, fabric_adc0_spare_i6, fabric_adc0_spare_i7, fabric_adc0_spare_i8, fabric_adc0_spare_i9 +, fabric_adc0_spare_i10, fabric_adc0_spare_i11, fabric_adc0_spare_i12, fabric_adc0_spare_i13, fabric_adc0_spare_i14, fabric_adc0_spare_i15, fabric_adc0_spare_i16, fabric_adc0_dft_test_mode_i1, fabric_adc0_dft_test_mode_i2, fabric_adc0_dft_scan_en_i, fabric_adc0_dft_si_i1, fabric_adc0_dft_si_i2, fabric_adc0_dft_si_i3, fabric_adc0_dft_si_i4, fabric_adc0_dft_si_i5, fabric_adc0_dft_si_i6, fabric_adc0_dft_si_i7, fabric_adc0_dft_si_i8, fabric_adc0_dft_si_i9, fabric_adc0_dft_si_i10, fabric_adc0_dft_si_i11 +, fabric_adc0_dft_si_i12, fabric_adc0_usr_cke_i, fabric_adc0_usr_arst_b_tmr_i1, fabric_adc0_usr_arst_b_tmr_i2, fabric_adc0_usr_arst_b_tmr_i3, fabric_adc0_usr_channel_i1, fabric_adc0_usr_channel_i2, fabric_adc0_usr_channel_i3, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_adc0_usr_sample_o1, fabric_adc0_usr_sample_o2, fabric_adc0_usr_sample_o3, fabric_adc0_usr_sample_o4, fabric_adc0_usr_sample_o5, fabric_adc0_usr_sample_o6, fabric_adc0_usr_sample_o7, fabric_adc0_usr_sample_o8, fabric_adc0_usr_sample_o9, fabric_adc0_usr_sample_o10, fabric_adc0_usr_sample_o11 +, fabric_adc0_usr_sample_o12, fabric_adc0_usr_sample_lsb_i1, fabric_adc0_usr_sample_lsb_i2, fabric_adc0_usr_sample_lsb_i3, fabric_adc0_usr_sample_lsb_i4, fabric_adc0_dbg_addr_i1, fabric_adc0_dbg_addr_i2, fabric_adc0_dbg_addr_i3, fabric_adc0_dbg_addr_i4, fabric_adc0_dbg_data_o1, fabric_adc0_dbg_data_o2, fabric_adc0_dbg_data_o3, fabric_adc0_dbg_data_o4, fabric_adc0_dbg_data_o5, fabric_adc0_dbg_data_o6, fabric_adc0_dbg_data_o7, fabric_adc0_dbg_data_o8, fabric_adc0_dbg_data_o9, fabric_adc0_dbg_data_o10, fabric_adc0_dbg_data_o11, fabric_adc0_dbg_data_o12 +, fabric_adc0_dbg_data_o13, fabric_adc0_dbg_data_o14, fabric_adc0_dbg_data_o15, fabric_adc0_dbg_data_o16, fabric_adc0_dbg_data_o17, fabric_adc0_dbg_data_o18, fabric_adc0_dbg_data_o19, fabric_adc0_dbg_data_o20, fabric_adc0_dbg_data_o21, fabric_adc0_dbg_data_o22, fabric_adc0_dbg_data_o23, fabric_adc0_dbg_data_o24, fabric_adc0_dbg_data_o25, fabric_adc0_dbg_data_o26, fabric_adc0_dbg_data_o27, fabric_adc0_dbg_data_o28, fabric_adc0_dbg_data_o29, fabric_adc0_dbg_data_o30, fabric_adc0_dbg_data_o31, fabric_adc0_dbg_data_o32, fabric_cfg_adc0_clk_cal_div_ratio_i1 +, fabric_cfg_adc0_clk_cal_div_ratio_i2, fabric_cfg_adc0_clk_cal_div_ratio_i3, fabric_cfg_adc0_clk_cal_div_ratio_i4, fabric_cfg_adc0_clk_cal_div_ratio_i5, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_arst_b_tmr_i1, fabric_adc1_arst_b_tmr_i2, fabric_adc1_arst_b_tmr_i3, fabric_adc1_pwr_down_b_tmr_i1, fabric_adc1_pwr_down_b_tmr_i2, fabric_adc1_pwr_down_b_tmr_i3, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_spare_i1, fabric_adc1_spare_i2 +, fabric_adc1_spare_i3, fabric_adc1_spare_i4, fabric_adc1_spare_i5, fabric_adc1_spare_i6, fabric_adc1_spare_i7, fabric_adc1_spare_i8, fabric_adc1_spare_i9, fabric_adc1_spare_i10, fabric_adc1_spare_i11, fabric_adc1_spare_i12, fabric_adc1_spare_i13, fabric_adc1_spare_i14, fabric_adc1_spare_i15, fabric_adc1_spare_i16, fabric_adc1_dft_test_mode_i1, fabric_adc1_dft_test_mode_i2, fabric_adc1_dft_scan_en_i, fabric_adc1_dft_si_i1, fabric_adc1_dft_si_i2, fabric_adc1_dft_si_i3, fabric_adc1_dft_si_i4 +, fabric_adc1_dft_si_i5, fabric_adc1_dft_si_i6, fabric_adc1_dft_si_i7, fabric_adc1_dft_si_i8, fabric_adc1_dft_si_i9, fabric_adc1_dft_si_i10, fabric_adc1_dft_si_i11, fabric_adc1_dft_si_i12, fabric_adc1_usr_cke_i, fabric_adc1_usr_arst_b_tmr_i1, fabric_adc1_usr_arst_b_tmr_i2, fabric_adc1_usr_arst_b_tmr_i3, fabric_adc1_usr_channel_i1, fabric_adc1_usr_channel_i2, fabric_adc1_usr_channel_i3, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_adc1_usr_sample_o1, fabric_adc1_usr_sample_o2, fabric_adc1_usr_sample_o3, fabric_adc1_usr_sample_o4 +, fabric_adc1_usr_sample_o5, fabric_adc1_usr_sample_o6, fabric_adc1_usr_sample_o7, fabric_adc1_usr_sample_o8, fabric_adc1_usr_sample_o9, fabric_adc1_usr_sample_o10, fabric_adc1_usr_sample_o11, fabric_adc1_usr_sample_o12, fabric_adc1_usr_sample_lsb_i1, fabric_adc1_usr_sample_lsb_i2, fabric_adc1_usr_sample_lsb_i3, fabric_adc1_usr_sample_lsb_i4, fabric_adc1_dbg_addr_i1, fabric_adc1_dbg_addr_i2, fabric_adc1_dbg_addr_i3, fabric_adc1_dbg_addr_i4, fabric_adc1_dbg_data_o1, fabric_adc1_dbg_data_o2, fabric_adc1_dbg_data_o3, fabric_adc1_dbg_data_o4, fabric_adc1_dbg_data_o5 +, fabric_adc1_dbg_data_o6, fabric_adc1_dbg_data_o7, fabric_adc1_dbg_data_o8, fabric_adc1_dbg_data_o9, fabric_adc1_dbg_data_o10, fabric_adc1_dbg_data_o11, fabric_adc1_dbg_data_o12, fabric_adc1_dbg_data_o13, fabric_adc1_dbg_data_o14, fabric_adc1_dbg_data_o15, fabric_adc1_dbg_data_o16, fabric_adc1_dbg_data_o17, fabric_adc1_dbg_data_o18, fabric_adc1_dbg_data_o19, fabric_adc1_dbg_data_o20, fabric_adc1_dbg_data_o21, fabric_adc1_dbg_data_o22, fabric_adc1_dbg_data_o23, fabric_adc1_dbg_data_o24, fabric_adc1_dbg_data_o25, fabric_adc1_dbg_data_o26 +, fabric_adc1_dbg_data_o27, fabric_adc1_dbg_data_o28, fabric_adc1_dbg_data_o29, fabric_adc1_dbg_data_o30, fabric_adc1_dbg_data_o31, fabric_adc1_dbg_data_o32, fabric_cfg_adc1_clk_cal_div_ratio_i1, fabric_cfg_adc1_clk_cal_div_ratio_i2, fabric_cfg_adc1_clk_cal_div_ratio_i3, fabric_cfg_adc1_clk_cal_div_ratio_i4, fabric_cfg_adc1_clk_cal_div_ratio_i5, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i, fabric_adc2_clk_i, fabric_adc2_arst_b_tmr_i1, fabric_adc2_arst_b_tmr_i2, fabric_adc2_arst_b_tmr_i3, fabric_adc2_pwr_down_b_tmr_i1, fabric_adc2_pwr_down_b_tmr_i2, fabric_adc2_pwr_down_b_tmr_i3, fabric_adc2_cal_start_i +, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_spare_i1, fabric_adc2_spare_i2, fabric_adc2_spare_i3, fabric_adc2_spare_i4, fabric_adc2_spare_i5, fabric_adc2_spare_i6, fabric_adc2_spare_i7, fabric_adc2_spare_i8, fabric_adc2_spare_i9, fabric_adc2_spare_i10, fabric_adc2_spare_i11, fabric_adc2_spare_i12, fabric_adc2_spare_i13, fabric_adc2_spare_i14, fabric_adc2_spare_i15, fabric_adc2_spare_i16 +, fabric_adc2_dft_test_mode_i1, fabric_adc2_dft_test_mode_i2, fabric_adc2_dft_scan_en_i, fabric_adc2_dft_si_i1, fabric_adc2_dft_si_i2, fabric_adc2_dft_si_i3, fabric_adc2_dft_si_i4, fabric_adc2_dft_si_i5, fabric_adc2_dft_si_i6, fabric_adc2_dft_si_i7, fabric_adc2_dft_si_i8, fabric_adc2_dft_si_i9, fabric_adc2_dft_si_i10, fabric_adc2_dft_si_i11, fabric_adc2_dft_si_i12, fabric_adc2_usr_cke_i, fabric_adc2_usr_arst_b_tmr_i1, fabric_adc2_usr_arst_b_tmr_i2, fabric_adc2_usr_arst_b_tmr_i3, fabric_adc2_usr_channel_i1, fabric_adc2_usr_channel_i2 +, fabric_adc2_usr_channel_i3, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_adc2_usr_sample_o1, fabric_adc2_usr_sample_o2, fabric_adc2_usr_sample_o3, fabric_adc2_usr_sample_o4, fabric_adc2_usr_sample_o5, fabric_adc2_usr_sample_o6, fabric_adc2_usr_sample_o7, fabric_adc2_usr_sample_o8, fabric_adc2_usr_sample_o9, fabric_adc2_usr_sample_o10, fabric_adc2_usr_sample_o11, fabric_adc2_usr_sample_o12, fabric_adc2_usr_sample_lsb_i1, fabric_adc2_usr_sample_lsb_i2, fabric_adc2_usr_sample_lsb_i3, fabric_adc2_usr_sample_lsb_i4, fabric_adc2_dbg_addr_i1, fabric_adc2_dbg_addr_i2 +, fabric_adc2_dbg_addr_i3, fabric_adc2_dbg_addr_i4, fabric_adc2_dbg_data_o1, fabric_adc2_dbg_data_o2, fabric_adc2_dbg_data_o3, fabric_adc2_dbg_data_o4, fabric_adc2_dbg_data_o5, fabric_adc2_dbg_data_o6, fabric_adc2_dbg_data_o7, fabric_adc2_dbg_data_o8, fabric_adc2_dbg_data_o9, fabric_adc2_dbg_data_o10, fabric_adc2_dbg_data_o11, fabric_adc2_dbg_data_o12, fabric_adc2_dbg_data_o13, fabric_adc2_dbg_data_o14, fabric_adc2_dbg_data_o15, fabric_adc2_dbg_data_o16, fabric_adc2_dbg_data_o17, fabric_adc2_dbg_data_o18, fabric_adc2_dbg_data_o19 +, fabric_adc2_dbg_data_o20, fabric_adc2_dbg_data_o21, fabric_adc2_dbg_data_o22, fabric_adc2_dbg_data_o23, fabric_adc2_dbg_data_o24, fabric_adc2_dbg_data_o25, fabric_adc2_dbg_data_o26, fabric_adc2_dbg_data_o27, fabric_adc2_dbg_data_o28, fabric_adc2_dbg_data_o29, fabric_adc2_dbg_data_o30, fabric_adc2_dbg_data_o31, fabric_adc2_dbg_data_o32, fabric_cfg_adc2_clk_cal_div_ratio_i1, fabric_cfg_adc2_clk_cal_div_ratio_i2, fabric_cfg_adc2_clk_cal_div_ratio_i3, fabric_cfg_adc2_clk_cal_div_ratio_i4, fabric_cfg_adc2_clk_cal_div_ratio_i5, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i +, fabric_adc3_arst_b_tmr_i1, fabric_adc3_arst_b_tmr_i2, fabric_adc3_arst_b_tmr_i3, fabric_adc3_pwr_down_b_tmr_i1, fabric_adc3_pwr_down_b_tmr_i2, fabric_adc3_pwr_down_b_tmr_i3, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_spare_i1, fabric_adc3_spare_i2, fabric_adc3_spare_i3, fabric_adc3_spare_i4, fabric_adc3_spare_i5, fabric_adc3_spare_i6, fabric_adc3_spare_i7, fabric_adc3_spare_i8, fabric_adc3_spare_i9 +, fabric_adc3_spare_i10, fabric_adc3_spare_i11, fabric_adc3_spare_i12, fabric_adc3_spare_i13, fabric_adc3_spare_i14, fabric_adc3_spare_i15, fabric_adc3_spare_i16, fabric_adc3_dft_test_mode_i1, fabric_adc3_dft_test_mode_i2, fabric_adc3_dft_scan_en_i, fabric_adc3_dft_si_i1, fabric_adc3_dft_si_i2, fabric_adc3_dft_si_i3, fabric_adc3_dft_si_i4, fabric_adc3_dft_si_i5, fabric_adc3_dft_si_i6, fabric_adc3_dft_si_i7, fabric_adc3_dft_si_i8, fabric_adc3_dft_si_i9, fabric_adc3_dft_si_i10, fabric_adc3_dft_si_i11 +, fabric_adc3_dft_si_i12, fabric_adc3_usr_cke_i, fabric_adc3_usr_arst_b_tmr_i1, fabric_adc3_usr_arst_b_tmr_i2, fabric_adc3_usr_arst_b_tmr_i3, fabric_adc3_usr_channel_i1, fabric_adc3_usr_channel_i2, fabric_adc3_usr_channel_i3, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_adc3_usr_sample_o1, fabric_adc3_usr_sample_o2, fabric_adc3_usr_sample_o3, fabric_adc3_usr_sample_o4, fabric_adc3_usr_sample_o5, fabric_adc3_usr_sample_o6, fabric_adc3_usr_sample_o7, fabric_adc3_usr_sample_o8, fabric_adc3_usr_sample_o9, fabric_adc3_usr_sample_o10, fabric_adc3_usr_sample_o11 +, fabric_adc3_usr_sample_o12, fabric_adc3_usr_sample_lsb_i1, fabric_adc3_usr_sample_lsb_i2, fabric_adc3_usr_sample_lsb_i3, fabric_adc3_usr_sample_lsb_i4, fabric_adc3_dbg_addr_i1, fabric_adc3_dbg_addr_i2, fabric_adc3_dbg_addr_i3, fabric_adc3_dbg_addr_i4, fabric_adc3_dbg_data_o1, fabric_adc3_dbg_data_o2, fabric_adc3_dbg_data_o3, fabric_adc3_dbg_data_o4, fabric_adc3_dbg_data_o5, fabric_adc3_dbg_data_o6, fabric_adc3_dbg_data_o7, fabric_adc3_dbg_data_o8, fabric_adc3_dbg_data_o9, fabric_adc3_dbg_data_o10, fabric_adc3_dbg_data_o11, fabric_adc3_dbg_data_o12 +, fabric_adc3_dbg_data_o13, fabric_adc3_dbg_data_o14, fabric_adc3_dbg_data_o15, fabric_adc3_dbg_data_o16, fabric_adc3_dbg_data_o17, fabric_adc3_dbg_data_o18, fabric_adc3_dbg_data_o19, fabric_adc3_dbg_data_o20, fabric_adc3_dbg_data_o21, fabric_adc3_dbg_data_o22, fabric_adc3_dbg_data_o23, fabric_adc3_dbg_data_o24, fabric_adc3_dbg_data_o25, fabric_adc3_dbg_data_o26, fabric_adc3_dbg_data_o27, fabric_adc3_dbg_data_o28, fabric_adc3_dbg_data_o29, fabric_adc3_dbg_data_o30, fabric_adc3_dbg_data_o31, fabric_adc3_dbg_data_o32, fabric_cfg_adc3_clk_cal_div_ratio_i1 +, fabric_cfg_adc3_clk_cal_div_ratio_i2, fabric_cfg_adc3_clk_cal_div_ratio_i3, fabric_cfg_adc3_clk_cal_div_ratio_i4, fabric_cfg_adc3_clk_cal_div_ratio_i5, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_clock_fabric_i1, fabric_direct0_clock_fabric_i2, fabric_direct0_clock_fabric_i3, fabric_direct0_clock_fabric_i4, fabric_direct0_oe_i1, fabric_direct0_oe_i2, fabric_direct0_oe_i3, fabric_direct0_oe_i4, fabric_direct0_oe_i5, fabric_direct0_oe_i6, fabric_direct0_oe_i7, fabric_direct0_oe_i8, fabric_direct0_oe_i9, fabric_direct0_oe_i10, fabric_direct0_oe_i11 +, fabric_direct0_oe_i12, fabric_direct0_oe_i13, fabric_direct0_oe_i14, fabric_direct0_oe_i15, fabric_direct0_oe_i16, fabric_direct0_oe_i17, fabric_direct0_oe_i18, fabric_direct0_oe_i19, fabric_direct0_oe_i20, fabric_direct0_oe_i21, fabric_direct0_oe_i22, fabric_direct0_oe_i23, fabric_direct0_oe_i24, fabric_direct0_oe_ena_i1, fabric_direct0_oe_ena_i2, fabric_direct0_oe_ena_i3, fabric_direct0_oe_ena_i4, fabric_direct0_oe_ena_i5, fabric_direct0_oe_ena_i6, fabric_direct0_oe_ena_i7, fabric_direct0_oe_ena_i8 +, fabric_direct0_oe_ena_i9, fabric_direct0_oe_ena_i10, fabric_direct0_oe_ena_i11, fabric_direct0_oe_ena_i12, fabric_direct0_oe_ena_i13, fabric_direct0_oe_ena_i14, fabric_direct0_oe_ena_i15, fabric_direct0_oe_ena_i16, fabric_direct0_oe_ena_i17, fabric_direct0_oe_ena_i18, fabric_direct0_oe_ena_i19, fabric_direct0_oe_ena_i20, fabric_direct0_oe_ena_i21, fabric_direct0_oe_ena_i22, fabric_direct0_oe_ena_i23, fabric_direct0_oe_ena_i24, fabric_direct0_oe_rs_i1, fabric_direct0_oe_rs_i2, fabric_direct0_oe_rs_i3, fabric_direct0_oe_rs_i4, fabric_direct0_oe_rs_i5 +, fabric_direct0_oe_rs_i6, fabric_direct0_oe_rs_i7, fabric_direct0_oe_rs_i8, fabric_direct0_oe_rs_i9, fabric_direct0_oe_rs_i10, fabric_direct0_oe_rs_i11, fabric_direct0_oe_rs_i12, fabric_direct0_oe_rs_i13, fabric_direct0_oe_rs_i14, fabric_direct0_oe_rs_i15, fabric_direct0_oe_rs_i16, fabric_direct0_oe_rs_i17, fabric_direct0_oe_rs_i18, fabric_direct0_oe_rs_i19, fabric_direct0_oe_rs_i20, fabric_direct0_oe_rs_i21, fabric_direct0_oe_rs_i22, fabric_direct0_oe_rs_i23, fabric_direct0_oe_rs_i24, fabric_direct0_do_i1, fabric_direct0_do_i2 +, fabric_direct0_do_i3, fabric_direct0_do_i4, fabric_direct0_do_i5, fabric_direct0_do_i6, fabric_direct0_do_i7, fabric_direct0_do_i8, fabric_direct0_do_i9, fabric_direct0_do_i10, fabric_direct0_do_i11, fabric_direct0_do_i12, fabric_direct0_do_i13, fabric_direct0_do_i14, fabric_direct0_do_i15, fabric_direct0_do_i16, fabric_direct0_do_i17, fabric_direct0_do_i18, fabric_direct0_do_i19, fabric_direct0_do_i20, fabric_direct0_do_i21, fabric_direct0_do_i22, fabric_direct0_do_i23 +, fabric_direct0_do_i24, fabric_direct0_do_ena_i1, fabric_direct0_do_ena_i2, fabric_direct0_do_ena_i3, fabric_direct0_do_ena_i4, fabric_direct0_do_ena_i5, fabric_direct0_do_ena_i6, fabric_direct0_do_ena_i7, fabric_direct0_do_ena_i8, fabric_direct0_do_ena_i9, fabric_direct0_do_ena_i10, fabric_direct0_do_ena_i11, fabric_direct0_do_ena_i12, fabric_direct0_do_ena_i13, fabric_direct0_do_ena_i14, fabric_direct0_do_ena_i15, fabric_direct0_do_ena_i16, fabric_direct0_do_ena_i17, fabric_direct0_do_ena_i18, fabric_direct0_do_ena_i19, fabric_direct0_do_ena_i20 +, fabric_direct0_do_ena_i21, fabric_direct0_do_ena_i22, fabric_direct0_do_ena_i23, fabric_direct0_do_ena_i24, fabric_direct0_do_rs_i1, fabric_direct0_do_rs_i2, fabric_direct0_do_rs_i3, fabric_direct0_do_rs_i4, fabric_direct0_do_rs_i5, fabric_direct0_do_rs_i6, fabric_direct0_do_rs_i7, fabric_direct0_do_rs_i8, fabric_direct0_do_rs_i9, fabric_direct0_do_rs_i10, fabric_direct0_do_rs_i11, fabric_direct0_do_rs_i12, fabric_direct0_do_rs_i13, fabric_direct0_do_rs_i14, fabric_direct0_do_rs_i15, fabric_direct0_do_rs_i16, fabric_direct0_do_rs_i17 +, fabric_direct0_do_rs_i18, fabric_direct0_do_rs_i19, fabric_direct0_do_rs_i20, fabric_direct0_do_rs_i21, fabric_direct0_do_rs_i22, fabric_direct0_do_rs_i23, fabric_direct0_do_rs_i24, fabric_direct0_di_o1, fabric_direct0_di_o2, fabric_direct0_di_o3, fabric_direct0_di_o4, fabric_direct0_di_o5, fabric_direct0_di_o6, fabric_direct0_di_o7, fabric_direct0_di_o8, fabric_direct0_di_o9, fabric_direct0_di_o10, fabric_direct0_di_o11, fabric_direct0_di_o12, fabric_direct0_di_o13, fabric_direct0_di_o14 +, fabric_direct0_di_o15, fabric_direct0_di_o16, fabric_direct0_di_o17, fabric_direct0_di_o18, fabric_direct0_di_o19, fabric_direct0_di_o20, fabric_direct0_di_o21, fabric_direct0_di_o22, fabric_direct0_di_o23, fabric_direct0_di_o24, fabric_direct0_di_ena_i1, fabric_direct0_di_ena_i2, fabric_direct0_di_ena_i3, fabric_direct0_di_ena_i4, fabric_direct0_di_ena_i5, fabric_direct0_di_ena_i6, fabric_direct0_di_ena_i7, fabric_direct0_di_ena_i8, fabric_direct0_di_ena_i9, fabric_direct0_di_ena_i10, fabric_direct0_di_ena_i11 +, fabric_direct0_di_ena_i12, fabric_direct0_di_ena_i13, fabric_direct0_di_ena_i14, fabric_direct0_di_ena_i15, fabric_direct0_di_ena_i16, fabric_direct0_di_ena_i17, fabric_direct0_di_ena_i18, fabric_direct0_di_ena_i19, fabric_direct0_di_ena_i20, fabric_direct0_di_ena_i21, fabric_direct0_di_ena_i22, fabric_direct0_di_ena_i23, fabric_direct0_di_ena_i24, fabric_direct0_di_rs_i1, fabric_direct0_di_rs_i2, fabric_direct0_di_rs_i3, fabric_direct0_di_rs_i4, fabric_direct0_di_rs_i5, fabric_direct0_di_rs_i6, fabric_direct0_di_rs_i7, fabric_direct0_di_rs_i8 +, fabric_direct0_di_rs_i9, fabric_direct0_di_rs_i10, fabric_direct0_di_rs_i11, fabric_direct0_di_rs_i12, fabric_direct0_di_rs_i13, fabric_direct0_di_rs_i14, fabric_direct0_di_rs_i15, fabric_direct0_di_rs_i16, fabric_direct0_di_rs_i17, fabric_direct0_di_rs_i18, fabric_direct0_di_rs_i19, fabric_direct0_di_rs_i20, fabric_direct0_di_rs_i21, fabric_direct0_di_rs_i22, fabric_direct0_di_rs_i23, fabric_direct0_di_rs_i24, fabric_direct0_cfg_bank_i1, fabric_direct0_cfg_bank_i2, fabric_direct0_cfg_bank_i3, fabric_direct0_cfg_bank_i4, fabric_direct0_cfg_pad_i1 +, fabric_direct0_cfg_pad_i2, fabric_direct0_cfg_pad_i3, fabric_direct0_cfg_pad_i4, fabric_direct0_cfg_pad_i5, fabric_direct0_cfg_pad_i6, fabric_direct0_cfg_pad_i7, fabric_direct0_cfg_pad_i8, fabric_direct0_cfg_pad_i9, fabric_direct0_cfg_pad_i10, fabric_direct0_cfg_pad_i11, fabric_direct0_cfg_pad_i12, fabric_direct0_cfg_pad_i13, fabric_direct0_cfg_pad_i14, fabric_direct0_cfg_pad_i15, fabric_direct0_cfg_pad_i16, fabric_direct0_cfg_pad_i17, fabric_direct0_cfg_pad_i18, fabric_direct0_cfg_pad_i19, fabric_direct0_cfg_pad_i20, fabric_direct0_cfg_pad_i21, fabric_direct0_cfg_pad_i22 +, fabric_direct0_cfg_pad_i23, fabric_direct0_cfg_pad_i24, fabric_direct0_cfg_pad_i25, fabric_direct0_cfg_pad_i26, fabric_direct0_cfg_pad_i27, fabric_direct0_cfg_pad_i28, fabric_direct0_cfg_pad_i29, fabric_direct0_cfg_pad_i30, fabric_direct0_cfg_pad_i31, fabric_direct0_cfg_pad_i32, fabric_direct0_cfg_pad_i33, fabric_direct0_cfg_pad_i34, fabric_direct0_cfg_pad_i35, fabric_direct0_cfg_pad_i36, fabric_direct0_cfg_pad_i37, fabric_direct0_cfg_pad_i38, fabric_direct0_cfg_pad_i39, fabric_direct0_cfg_pad_i40, fabric_direct0_cfg_pad_i41, fabric_direct0_cfg_pad_i42, fabric_direct0_cfg_pad_i43 +, fabric_direct0_cfg_pad_i44, fabric_direct0_cfg_pad_i45, fabric_direct0_cfg_pad_i46, fabric_direct0_cfg_pad_i47, fabric_direct0_cfg_pad_i48, fabric_direct0_cfg_pad_i49, fabric_direct0_cfg_pad_i50, fabric_direct0_cfg_pad_i51, fabric_direct0_cfg_pad_i52, fabric_direct0_cfg_pad_i53, fabric_direct0_cfg_pad_i54, fabric_direct0_cfg_pad_i55, fabric_direct0_cfg_pad_i56, fabric_direct0_cfg_pad_i57, fabric_direct0_cfg_pad_i58, fabric_direct0_cfg_pad_i59, fabric_direct0_cfg_pad_i60, fabric_direct0_cfg_pad_i61, fabric_direct0_cfg_pad_i62, fabric_direct0_cfg_pad_i63, fabric_direct0_cfg_pad_i64 +, fabric_direct0_cfg_pad_i65, fabric_direct0_cfg_pad_i66, fabric_direct0_cfg_pad_i67, fabric_direct0_cfg_pad_i68, fabric_direct0_cfg_pad_i69, fabric_direct0_cfg_pad_i70, fabric_direct0_cfg_pad_i71, fabric_direct0_cfg_pad_i72, fabric_direct0_cfg_pad_i73, fabric_direct0_cfg_pad_i74, fabric_direct0_cfg_pad_i75, fabric_direct0_cfg_pad_i76, fabric_direct0_cfg_pad_i77, fabric_direct0_cfg_pad_i78, fabric_direct0_cfg_pad_i79, fabric_direct0_cfg_pad_i80, fabric_direct0_cfg_pad_i81, fabric_direct0_cfg_pad_i82, fabric_direct0_cfg_pad_i83, fabric_direct0_cfg_pad_i84, fabric_direct0_cfg_pad_i85 +, fabric_direct0_cfg_pad_i86, fabric_direct0_cfg_pad_i87, fabric_direct0_cfg_pad_i88, fabric_direct0_cfg_pad_i89, fabric_direct0_cfg_pad_i90, fabric_direct0_cfg_pad_i91, fabric_direct0_cfg_pad_i92, fabric_direct0_cfg_pad_i93, fabric_direct0_cfg_pad_i94, fabric_direct0_cfg_pad_i95, fabric_direct0_cfg_pad_i96, fabric_direct0_cfg_pad_i97, fabric_direct0_cfg_pad_i98, fabric_direct0_cfg_pad_i99, fabric_direct0_cfg_pad_i100, fabric_direct0_cfg_pad_i101, fabric_direct0_cfg_pad_i102, fabric_direct0_cfg_pad_i103, fabric_direct0_cfg_pad_i104, fabric_direct0_cfg_pad_i105, fabric_direct0_cfg_pad_i106 +, fabric_direct0_cfg_pad_i107, fabric_direct0_cfg_pad_i108, fabric_direct0_cfg_pad_i109, fabric_direct0_cfg_pad_i110, fabric_direct0_cfg_pad_i111, fabric_direct0_cfg_pad_i112, fabric_direct0_cfg_pad_i113, fabric_direct0_cfg_pad_i114, fabric_direct0_cfg_pad_i115, fabric_direct0_cfg_pad_i116, fabric_direct0_cfg_pad_i117, fabric_direct0_cfg_pad_i118, fabric_direct0_cfg_pad_i119, fabric_direct0_cfg_pad_i120, fabric_direct0_cfg_pad_i121, fabric_direct0_cfg_pad_i122, fabric_direct0_cfg_pad_i123, fabric_direct0_cfg_pad_i124, fabric_direct0_cfg_pad_i125, fabric_direct0_cfg_pad_i126, fabric_direct0_cfg_pad_i127 +, fabric_direct0_cfg_pad_i128, fabric_direct0_cfg_pad_i129, fabric_direct0_cfg_pad_i130, fabric_direct0_cfg_pad_i131, fabric_direct0_cfg_pad_i132, fabric_direct0_cfg_pad_i133, fabric_direct0_cfg_pad_i134, fabric_direct0_cfg_pad_i135, fabric_direct0_cfg_pad_i136, fabric_direct0_cfg_pad_i137, fabric_direct0_cfg_pad_i138, fabric_direct0_cfg_pad_i139, fabric_direct0_cfg_pad_i140, fabric_direct0_cfg_pad_i141, fabric_direct0_cfg_pad_i142, fabric_direct0_cfg_pad_i143, fabric_direct0_cfg_pad_i144, fabric_direct0_cfg_pad_i145, fabric_direct0_cfg_pad_i146, fabric_direct0_cfg_pad_i147, fabric_direct0_cfg_pad_i148 +, fabric_direct0_cfg_pad_i149, fabric_direct0_cfg_pad_i150, fabric_direct0_cfg_pad_i151, fabric_direct0_cfg_pad_i152, fabric_direct0_cfg_pad_i153, fabric_direct0_cfg_pad_i154, fabric_direct0_cfg_pad_i155, fabric_direct0_cfg_pad_i156, fabric_direct0_cfg_pad_i157, fabric_direct0_cfg_pad_i158, fabric_direct0_cfg_pad_i159, fabric_direct0_cfg_pad_i160, fabric_direct0_cfg_pad_i161, fabric_direct0_cfg_pad_i162, fabric_direct0_cfg_pad_i163, fabric_direct0_cfg_pad_i164, fabric_direct0_cfg_pad_i165, fabric_direct0_cfg_pad_i166, fabric_direct0_cfg_pad_i167, fabric_direct0_cfg_pad_i168, fabric_direct0_cfg_pad_i169 +, fabric_direct0_cfg_pad_i170, fabric_direct0_cfg_pad_i171, fabric_direct0_cfg_pad_i172, fabric_direct0_cfg_pad_i173, fabric_direct0_cfg_pad_i174, fabric_direct0_cfg_pad_i175, fabric_direct0_cfg_pad_i176, fabric_direct0_cfg_pad_i177, fabric_direct0_cfg_pad_i178, fabric_direct0_cfg_pad_i179, fabric_direct0_cfg_pad_i180, fabric_direct0_cfg_pad_i181, fabric_direct0_cfg_pad_i182, fabric_direct0_cfg_pad_i183, fabric_direct0_cfg_pad_i184, fabric_direct0_cfg_pad_i185, fabric_direct0_cfg_pad_i186, fabric_direct0_cfg_pad_i187, fabric_direct0_cfg_pad_i188, fabric_direct0_cfg_pad_i189, fabric_direct0_cfg_pad_i190 +, fabric_direct0_cfg_pad_i191, fabric_direct0_cfg_pad_i192, fabric_direct0_cfg_pad_i193, fabric_direct0_cfg_pad_i194, fabric_direct0_cfg_pad_i195, fabric_direct0_cfg_pad_i196, fabric_direct0_cfg_pad_i197, fabric_direct0_cfg_pad_i198, fabric_direct0_cfg_pad_i199, fabric_direct0_cfg_pad_i200, fabric_direct0_cfg_pad_i201, fabric_direct0_cfg_pad_i202, fabric_direct0_cfg_pad_i203, fabric_direct0_cfg_pad_i204, fabric_direct0_cfg_pad_i205, fabric_direct0_cfg_pad_i206, fabric_direct0_cfg_pad_i207, fabric_direct0_cfg_pad_i208, fabric_direct0_cfg_pad_i209, fabric_direct0_cfg_pad_i210, fabric_direct0_cfg_pad_i211 +, fabric_direct0_cfg_pad_i212, fabric_direct0_cfg_pad_i213, fabric_direct0_cfg_pad_i214, fabric_direct0_cfg_pad_i215, fabric_direct0_cfg_pad_i216, fabric_direct0_cfg_pad_i217, fabric_direct0_cfg_pad_i218, fabric_direct0_cfg_pad_i219, fabric_direct0_cfg_pad_i220, fabric_direct0_cfg_pad_i221, fabric_direct0_cfg_pad_i222, fabric_direct0_cfg_pad_i223, fabric_direct0_cfg_pad_i224, fabric_direct0_cfg_pad_i225, fabric_direct0_cfg_pad_i226, fabric_direct0_cfg_pad_i227, fabric_direct0_cfg_pad_i228, fabric_direct0_cfg_pad_i229, fabric_direct0_cfg_pad_i230, fabric_direct0_cfg_pad_i231, fabric_direct0_cfg_pad_i232 +, fabric_direct0_cfg_pad_i233, fabric_direct0_cfg_pad_i234, fabric_direct0_cfg_pad_i235, fabric_direct0_cfg_pad_i236, fabric_direct0_cfg_pad_i237, fabric_direct0_cfg_pad_i238, fabric_direct0_cfg_pad_i239, fabric_direct0_cfg_pad_i240, fabric_direct0_cfg_pad_i241, fabric_direct0_cfg_pad_i242, fabric_direct0_cfg_pad_i243, fabric_direct0_cfg_pad_i244, fabric_direct0_cfg_pad_i245, fabric_direct0_cfg_pad_i246, fabric_direct0_cfg_pad_i247, fabric_direct0_cfg_pad_i248, fabric_direct0_cfg_pad_i249, fabric_direct0_cfg_pad_i250, fabric_direct0_cfg_pad_i251, fabric_direct0_cfg_pad_i252, fabric_direct0_cfg_pad_i253 +, fabric_direct0_cfg_pad_i254, fabric_direct0_cfg_pad_i255, fabric_direct0_cfg_pad_i256, fabric_direct0_cfg_pad_i257, fabric_direct0_cfg_pad_i258, fabric_direct0_cfg_pad_i259, fabric_direct0_cfg_pad_i260, fabric_direct0_cfg_pad_i261, fabric_direct0_cfg_pad_i262, fabric_direct0_cfg_pad_i263, fabric_direct0_cfg_pad_i264, fabric_direct0_cfg_pad_i265, fabric_direct0_cfg_pad_i266, fabric_direct0_cfg_pad_i267, fabric_direct0_cfg_pad_i268, fabric_direct0_cfg_pad_i269, fabric_direct0_cfg_pad_i270, fabric_direct0_cfg_pad_i271, fabric_direct0_cfg_pad_i272, fabric_direct0_cfg_pad_i273, fabric_direct0_cfg_pad_i274 +, fabric_direct0_cfg_pad_i275, fabric_direct0_cfg_pad_i276, fabric_direct0_cfg_pad_i277, fabric_direct0_cfg_pad_i278, fabric_direct0_cfg_pad_i279, fabric_direct0_cfg_pad_i280, fabric_direct0_cfg_pad_i281, fabric_direct0_cfg_pad_i282, fabric_direct0_cfg_pad_i283, fabric_direct0_cfg_pad_i284, fabric_direct0_cfg_pad_i285, fabric_direct0_cfg_pad_i286, fabric_direct0_cfg_pad_i287, fabric_direct0_cfg_pad_i288, fabric_direct0_cfg_pad_i289, fabric_direct0_cfg_pad_i290, fabric_direct0_cfg_pad_i291, fabric_direct0_cfg_pad_i292, fabric_direct0_cfg_pad_i293, fabric_direct0_cfg_pad_i294, fabric_direct0_cfg_pad_i295 +, fabric_direct0_cfg_pad_i296, fabric_direct0_cfg_pad_i297, fabric_direct0_cfg_pad_i298, fabric_direct0_cfg_pad_i299, fabric_direct0_cfg_pad_i300, fabric_direct0_cfg_pad_i301, fabric_direct0_cfg_pad_i302, fabric_direct0_cfg_pad_i303, fabric_direct0_cfg_pad_i304, fabric_direct0_cfg_pad_i305, fabric_direct0_cfg_pad_i306, fabric_direct0_cfg_pad_i307, fabric_direct0_cfg_pad_i308, fabric_direct0_cfg_pad_i309, fabric_direct0_cfg_pad_i310, fabric_direct0_cfg_pad_i311, fabric_direct0_cfg_pad_i312, fabric_direct0_cfg_pad_i313, fabric_direct0_cfg_pad_i314, fabric_direct0_cfg_pad_i315, fabric_direct0_cfg_pad_i316 +, fabric_direct0_cfg_pad_i317, fabric_direct0_cfg_pad_i318, fabric_direct0_cfg_pad_i319, fabric_direct0_cfg_pad_i320, fabric_direct0_cfg_pad_i321, fabric_direct0_cfg_pad_i322, fabric_direct0_cfg_pad_i323, fabric_direct0_cfg_pad_i324, fabric_direct0_cfg_pad_i325, fabric_direct0_cfg_pad_i326, fabric_direct0_cfg_pad_i327, fabric_direct0_cfg_pad_i328, fabric_direct0_cfg_pad_i329, fabric_direct0_cfg_pad_i330, fabric_direct0_cfg_pad_i331, fabric_direct0_cfg_pad_i332, fabric_direct0_cfg_pad_i333, fabric_direct0_cfg_pad_i334, fabric_direct0_cfg_pad_i335, fabric_direct0_cfg_pad_i336, fabric_direct0_cfg_pad_i337 +, fabric_direct0_cfg_pad_i338, fabric_direct0_cfg_pad_i339, fabric_direct0_cfg_pad_i340, fabric_direct0_cfg_pad_i341, fabric_direct0_cfg_pad_i342, fabric_direct0_cfg_pad_i343, fabric_direct0_cfg_pad_i344, fabric_direct0_cfg_pad_i345, fabric_direct0_cfg_pad_i346, fabric_direct0_cfg_pad_i347, fabric_direct0_cfg_pad_i348, fabric_direct0_cfg_pad_i349, fabric_direct0_cfg_pad_i350, fabric_direct0_cfg_pad_i351, fabric_direct0_cfg_pad_i352, fabric_direct0_cfg_pad_i353, fabric_direct0_cfg_pad_i354, fabric_direct0_cfg_pad_i355, fabric_direct0_cfg_pad_i356, fabric_direct0_cfg_pad_i357, fabric_direct0_cfg_pad_i358 +, fabric_direct0_cfg_pad_i359, fabric_direct0_cfg_pad_i360, fabric_direct0_cfg_pad_i361, fabric_direct0_cfg_pad_i362, fabric_direct0_cfg_pad_i363, fabric_direct0_cfg_pad_i364, fabric_direct0_cfg_pad_i365, fabric_direct0_cfg_pad_i366, fabric_direct0_cfg_pad_i367, fabric_direct0_cfg_pad_i368, fabric_direct0_cfg_pad_i369, fabric_direct0_cfg_pad_i370, fabric_direct0_cfg_pad_i371, fabric_direct0_cfg_pad_i372, fabric_direct0_cfg_pad_i373, fabric_direct0_cfg_pad_i374, fabric_direct0_cfg_pad_i375, fabric_direct0_cfg_pad_i376, fabric_direct0_cfg_pad_i377, fabric_direct0_cfg_pad_i378, fabric_direct0_cfg_pad_i379 +, fabric_direct0_cfg_pad_i380, fabric_direct0_cfg_pad_i381, fabric_direct0_cfg_pad_i382, fabric_direct0_cfg_pad_i383, fabric_direct0_cfg_pad_i384, fabric_direct0_cfg_pad_i385, fabric_direct0_cfg_pad_i386, fabric_direct0_cfg_pad_i387, fabric_direct0_cfg_pad_i388, fabric_direct0_cfg_pad_i389, fabric_direct0_cfg_pad_i390, fabric_direct0_cfg_pad_i391, fabric_direct0_cfg_pad_i392, fabric_direct0_cfg_pad_i393, fabric_direct0_cfg_pad_i394, fabric_direct0_cfg_pad_i395, fabric_direct0_cfg_pad_i396, fabric_direct0_cfg_pad_i397, fabric_direct0_cfg_pad_i398, fabric_direct0_cfg_pad_i399, fabric_direct0_cfg_pad_i400 +, fabric_direct0_cfg_pad_i401, fabric_direct0_cfg_pad_i402, fabric_direct0_cfg_pad_i403, fabric_direct0_cfg_pad_i404, fabric_direct0_cfg_pad_i405, fabric_direct0_cfg_pad_i406, fabric_direct0_cfg_pad_i407, fabric_direct0_cfg_pad_i408, fabric_direct0_cfg_pad_i409, fabric_direct0_cfg_pad_i410, fabric_direct0_cfg_pad_i411, fabric_direct0_cfg_pad_i412, fabric_direct0_cfg_pad_i413, fabric_direct0_cfg_pad_i414, fabric_direct0_cfg_pad_i415, fabric_direct0_cfg_pad_i416, fabric_direct0_cfg_pad_i417, fabric_direct0_cfg_pad_i418, fabric_direct0_cfg_pad_i419, fabric_direct0_cfg_pad_i420, fabric_direct0_cfg_pad_i421 +, fabric_direct0_cfg_pad_i422, fabric_direct0_cfg_pad_i423, fabric_direct0_cfg_pad_i424, fabric_direct0_cfg_pad_i425, fabric_direct0_cfg_pad_i426, fabric_direct0_cfg_pad_i427, fabric_direct0_cfg_pad_i428, fabric_direct0_cfg_pad_i429, fabric_direct0_cfg_pad_i430, fabric_direct0_cfg_pad_i431, fabric_direct0_cfg_pad_i432, fabric_direct0_cfg_pad_i433, fabric_direct0_cfg_pad_i434, fabric_direct0_cfg_pad_i435, fabric_direct0_cfg_pad_i436, fabric_direct0_cfg_pad_i437, fabric_direct0_cfg_pad_i438, fabric_direct0_cfg_pad_i439, fabric_direct0_cfg_pad_i440, fabric_direct0_cfg_pad_i441, fabric_direct0_cfg_pad_i442 +, fabric_direct0_cfg_pad_i443, fabric_direct0_cfg_pad_i444, fabric_direct0_cfg_pad_i445, fabric_direct0_cfg_pad_i446, fabric_direct0_cfg_pad_i447, fabric_direct0_cfg_pad_i448, fabric_direct0_cfg_pad_i449, fabric_direct0_cfg_pad_i450, fabric_direct0_cfg_pad_i451, fabric_direct0_cfg_pad_i452, fabric_direct0_cfg_pad_i453, fabric_direct0_cfg_pad_i454, fabric_direct0_cfg_pad_i455, fabric_direct0_cfg_pad_i456, fabric_direct0_cfg_pad_i457, fabric_direct0_cfg_pad_i458, fabric_direct0_cfg_pad_i459, fabric_direct0_cfg_pad_i460, fabric_direct0_cfg_pad_i461, fabric_direct0_cfg_pad_i462, fabric_direct0_cfg_pad_i463 +, fabric_direct0_cfg_pad_i464, fabric_direct0_cfg_pad_i465, fabric_direct0_cfg_pad_i466, fabric_direct0_cfg_pad_i467, fabric_direct0_cfg_pad_i468, fabric_direct0_cfg_pad_i469, fabric_direct0_cfg_pad_i470, fabric_direct0_cfg_pad_i471, fabric_direct0_cfg_pad_i472, fabric_direct0_cfg_pad_i473, fabric_direct0_cfg_pad_i474, fabric_direct0_cfg_pad_i475, fabric_direct0_cfg_pad_i476, fabric_direct0_cfg_pad_i477, fabric_direct0_cfg_pad_i478, fabric_direct0_cfg_pad_i479, fabric_direct0_cfg_pad_i480, fabric_direct0_cfg_pad_i481, fabric_direct0_cfg_pad_i482, fabric_direct0_cfg_pad_i483, fabric_direct0_cfg_pad_i484 +, fabric_direct0_cfg_pad_i485, fabric_direct0_cfg_pad_i486, fabric_direct0_cfg_pad_i487, fabric_direct0_cfg_pad_i488, fabric_direct0_cfg_pad_i489, fabric_direct0_cfg_pad_i490, fabric_direct0_cfg_pad_i491, fabric_direct0_cfg_pad_i492, fabric_direct0_cfg_pad_i493, fabric_direct0_cfg_pad_i494, fabric_direct0_cfg_pad_i495, fabric_direct0_cfg_pad_i496, fabric_direct0_cfg_pad_i497, fabric_direct0_cfg_pad_i498, fabric_direct0_cfg_pad_i499, fabric_direct0_cfg_pad_i500, fabric_direct0_cfg_pad_i501, fabric_direct0_cfg_pad_i502, fabric_direct0_cfg_pad_i503, fabric_direct0_cfg_pad_i504, fabric_direct0_cfg_pad_i505 +, fabric_direct0_cfg_pad_i506, fabric_direct0_cfg_pad_i507, fabric_direct0_cfg_pad_i508, fabric_direct0_cfg_pad_i509, fabric_direct0_cfg_pad_i510, fabric_direct0_cfg_pad_i511, fabric_direct0_cfg_pad_i512, fabric_direct0_cfg_pad_i513, fabric_direct0_cfg_pad_i514, fabric_direct0_cfg_pad_i515, fabric_direct0_cfg_pad_i516, fabric_direct0_cfg_pad_i517, fabric_direct0_cfg_pad_i518, fabric_direct0_cfg_pad_i519, fabric_direct0_cfg_pad_i520, fabric_direct0_cfg_pad_i521, fabric_direct0_cfg_pad_i522, fabric_direct0_cfg_pad_i523, fabric_direct0_cfg_pad_i524, fabric_direct0_cfg_pad_i525, fabric_direct0_cfg_pad_i526 +, fabric_direct0_cfg_pad_i527, fabric_direct0_cfg_pad_i528, fabric_direct0_cfg_pad_i529, fabric_direct0_cfg_pad_i530, fabric_direct0_cfg_pad_i531, fabric_direct0_cfg_pad_i532, fabric_direct0_cfg_pad_i533, fabric_direct0_cfg_pad_i534, fabric_direct0_cfg_pad_i535, fabric_direct0_cfg_pad_i536, fabric_direct0_cfg_pad_i537, fabric_direct0_cfg_pad_i538, fabric_direct0_cfg_pad_i539, fabric_direct0_cfg_pad_i540, fabric_direct0_cfg_pad_i541, fabric_direct0_cfg_pad_i542, fabric_direct0_cfg_pad_i543, fabric_direct0_cfg_pad_i544, fabric_direct0_cfg_pad_i545, fabric_direct0_cfg_pad_i546, fabric_direct0_cfg_pad_i547 +, fabric_direct0_cfg_pad_i548, fabric_direct0_cfg_pad_i549, fabric_direct0_cfg_pad_i550, fabric_direct0_cfg_pad_i551, fabric_direct0_cfg_pad_i552, fabric_direct0_cfg_pad_i553, fabric_direct0_cfg_pad_i554, fabric_direct0_cfg_pad_i555, fabric_direct0_cfg_pad_i556, fabric_direct0_cfg_pad_i557, fabric_direct0_cfg_pad_i558, fabric_direct0_cfg_pad_i559, fabric_direct0_cfg_pad_i560, fabric_direct0_cfg_pad_i561, fabric_direct0_cfg_pad_i562, fabric_direct0_cfg_pad_i563, fabric_direct0_cfg_pad_i564, fabric_direct0_cfg_pad_i565, fabric_direct0_cfg_pad_i566, fabric_direct0_cfg_pad_i567, fabric_direct0_cfg_pad_i568 +, fabric_direct0_cfg_pad_i569, fabric_direct0_cfg_pad_i570, fabric_direct0_cfg_pad_i571, fabric_direct0_cfg_pad_i572, fabric_direct0_cfg_pad_i573, fabric_direct0_cfg_pad_i574, fabric_direct0_cfg_pad_i575, fabric_direct0_cfg_pad_i576, fabric_direct0_cfg_pad_i577, fabric_direct0_cfg_pad_i578, fabric_direct0_cfg_pad_i579, fabric_direct0_cfg_pad_i580, fabric_direct0_cfg_pad_i581, fabric_direct0_cfg_pad_i582, fabric_direct0_cfg_pad_i583, fabric_direct0_cfg_pad_i584, fabric_direct0_cfg_pad_i585, fabric_direct0_cfg_pad_i586, fabric_direct0_cfg_pad_i587, fabric_direct0_cfg_pad_i588, fabric_direct0_cfg_pad_i589 +, fabric_direct0_cfg_pad_i590, fabric_direct0_cfg_pad_i591, fabric_direct0_cfg_pad_i592, fabric_direct0_cfg_pad_i593, fabric_direct0_cfg_pad_i594, fabric_direct0_cfg_pad_i595, fabric_direct0_cfg_pad_i596, fabric_direct0_cfg_pad_i597, fabric_direct0_cfg_pad_i598, fabric_direct0_cfg_pad_i599, fabric_direct0_cfg_pad_i600, fabric_direct0_cfg_pad_i601, fabric_direct0_cfg_pad_i602, fabric_direct0_cfg_pad_i603, fabric_direct0_cfg_pad_i604, fabric_direct0_cfg_pad_i605, fabric_direct0_cfg_pad_i606, fabric_direct0_cfg_pad_i607, fabric_direct0_cfg_pad_i608, fabric_direct0_cfg_pad_i609, fabric_direct0_cfg_pad_i610 +, fabric_direct0_cfg_pad_i611, fabric_direct0_cfg_pad_i612, fabric_direct0_cfg_pad_i613, fabric_direct0_cfg_pad_i614, fabric_direct0_cfg_pad_i615, fabric_direct0_cfg_pad_i616, fabric_direct0_cfg_pad_i617, fabric_direct0_cfg_pad_i618, fabric_direct0_cfg_pad_i619, fabric_direct0_cfg_pad_i620, fabric_direct0_cfg_pad_i621, fabric_direct0_cfg_pad_i622, fabric_direct0_cfg_pad_i623, fabric_direct0_cfg_pad_i624, fabric_direct0_cfg_pad_i625, fabric_direct0_cfg_pad_i626, fabric_direct0_cfg_pad_i627, fabric_direct0_cfg_pad_i628, fabric_direct0_cfg_pad_i629, fabric_direct0_cfg_pad_i630, fabric_direct0_cfg_pad_i631 +, fabric_direct0_cfg_pad_i632, fabric_direct0_cfg_pad_i633, fabric_direct0_cfg_pad_i634, fabric_direct0_cfg_pad_i635, fabric_direct0_cfg_pad_i636, fabric_direct0_cfg_pad_i637, fabric_direct0_cfg_pad_i638, fabric_direct0_cfg_pad_i639, fabric_direct0_cfg_pad_i640, fabric_direct0_cfg_pad_i641, fabric_direct0_cfg_pad_i642, fabric_direct0_cfg_pad_i643, fabric_direct0_cfg_pad_i644, fabric_direct0_cfg_pad_i645, fabric_direct0_cfg_pad_i646, fabric_direct0_cfg_pad_i647, fabric_direct0_cfg_pad_i648, fabric_direct0_cfg_pad_i649, fabric_direct0_cfg_pad_i650, fabric_direct0_cfg_pad_i651, fabric_direct0_cfg_pad_i652 +, fabric_direct0_cfg_pad_i653, fabric_direct0_cfg_pad_i654, fabric_direct0_cfg_pad_i655, fabric_direct0_cfg_pad_i656, fabric_direct0_cfg_pad_i657, fabric_direct0_cfg_pad_i658, fabric_direct0_cfg_pad_i659, fabric_direct0_cfg_pad_i660, fabric_direct0_cfg_pad_i661, fabric_direct0_cfg_pad_i662, fabric_direct0_cfg_pad_i663, fabric_direct0_cfg_pad_i664, fabric_direct0_cfg_pad_i665, fabric_direct0_cfg_pad_i666, fabric_direct0_cfg_pad_i667, fabric_direct0_cfg_pad_i668, fabric_direct0_cfg_pad_i669, fabric_direct0_cfg_pad_i670, fabric_direct0_cfg_pad_i671, fabric_direct0_cfg_pad_i672, fabric_direct0_cfg_pad_i673 +, fabric_direct0_cfg_pad_i674, fabric_direct0_cfg_pad_i675, fabric_direct0_cfg_pad_i676, fabric_direct0_cfg_pad_i677, fabric_direct0_cfg_pad_i678, fabric_direct0_cfg_pad_i679, fabric_direct0_cfg_pad_i680, fabric_direct0_cfg_pad_i681, fabric_direct0_cfg_pad_i682, fabric_direct0_cfg_pad_i683, fabric_direct0_cfg_pad_i684, fabric_direct0_cfg_pad_i685, fabric_direct0_cfg_pad_i686, fabric_direct0_cfg_pad_i687, fabric_direct0_cfg_pad_i688, fabric_direct0_cfg_pad_i689, fabric_direct0_cfg_pad_i690, fabric_direct0_cfg_pad_i691, fabric_direct0_cfg_pad_i692, fabric_direct0_cfg_pad_i693, fabric_direct0_cfg_pad_i694 +, fabric_direct0_cfg_pad_i695, fabric_direct0_cfg_pad_i696, fabric_direct0_cfg_pad_i697, fabric_direct0_cfg_pad_i698, fabric_direct0_cfg_pad_i699, fabric_direct0_cfg_pad_i700, fabric_direct0_cfg_pad_i701, fabric_direct0_cfg_pad_i702, fabric_direct0_cfg_pad_i703, fabric_direct0_cfg_pad_i704, fabric_direct0_cfg_pad_i705, fabric_direct0_cfg_pad_i706, fabric_direct0_cfg_pad_i707, fabric_direct0_cfg_pad_i708, fabric_direct0_cfg_pad_i709, fabric_direct0_cfg_pad_i710, fabric_direct0_cfg_pad_i711, fabric_direct0_cfg_pad_i712, fabric_direct0_cfg_pad_i713, fabric_direct0_cfg_pad_i714, fabric_direct0_cfg_pad_i715 +, fabric_direct0_cfg_pad_i716, fabric_direct0_cfg_pad_i717, fabric_direct0_cfg_pad_i718, fabric_direct0_cfg_pad_i719, fabric_direct0_cfg_pad_i720, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_clock_fabric_i1, fabric_direct2_clock_fabric_i2, fabric_direct2_clock_fabric_i3, fabric_direct2_clock_fabric_i4, fabric_direct2_oe_i1, fabric_direct2_oe_i2, fabric_direct2_oe_i3, fabric_direct2_oe_i4, fabric_direct2_oe_i5, fabric_direct2_oe_i6, fabric_direct2_oe_i7, fabric_direct2_oe_i8, fabric_direct2_oe_i9 +, fabric_direct2_oe_i10, fabric_direct2_oe_i11, fabric_direct2_oe_i12, fabric_direct2_oe_i13, fabric_direct2_oe_i14, fabric_direct2_oe_i15, fabric_direct2_oe_i16, fabric_direct2_oe_i17, fabric_direct2_oe_i18, fabric_direct2_oe_i19, fabric_direct2_oe_i20, fabric_direct2_oe_i21, fabric_direct2_oe_i22, fabric_direct2_oe_i23, fabric_direct2_oe_i24, fabric_direct2_oe_ena_i1, fabric_direct2_oe_ena_i2, fabric_direct2_oe_ena_i3, fabric_direct2_oe_ena_i4, fabric_direct2_oe_ena_i5, fabric_direct2_oe_ena_i6 +, fabric_direct2_oe_ena_i7, fabric_direct2_oe_ena_i8, fabric_direct2_oe_ena_i9, fabric_direct2_oe_ena_i10, fabric_direct2_oe_ena_i11, fabric_direct2_oe_ena_i12, fabric_direct2_oe_ena_i13, fabric_direct2_oe_ena_i14, fabric_direct2_oe_ena_i15, fabric_direct2_oe_ena_i16, fabric_direct2_oe_ena_i17, fabric_direct2_oe_ena_i18, fabric_direct2_oe_ena_i19, fabric_direct2_oe_ena_i20, fabric_direct2_oe_ena_i21, fabric_direct2_oe_ena_i22, fabric_direct2_oe_ena_i23, fabric_direct2_oe_ena_i24, fabric_direct2_oe_rs_i1, fabric_direct2_oe_rs_i2, fabric_direct2_oe_rs_i3 +, fabric_direct2_oe_rs_i4, fabric_direct2_oe_rs_i5, fabric_direct2_oe_rs_i6, fabric_direct2_oe_rs_i7, fabric_direct2_oe_rs_i8, fabric_direct2_oe_rs_i9, fabric_direct2_oe_rs_i10, fabric_direct2_oe_rs_i11, fabric_direct2_oe_rs_i12, fabric_direct2_oe_rs_i13, fabric_direct2_oe_rs_i14, fabric_direct2_oe_rs_i15, fabric_direct2_oe_rs_i16, fabric_direct2_oe_rs_i17, fabric_direct2_oe_rs_i18, fabric_direct2_oe_rs_i19, fabric_direct2_oe_rs_i20, fabric_direct2_oe_rs_i21, fabric_direct2_oe_rs_i22, fabric_direct2_oe_rs_i23, fabric_direct2_oe_rs_i24 +, fabric_direct2_do_i1, fabric_direct2_do_i2, fabric_direct2_do_i3, fabric_direct2_do_i4, fabric_direct2_do_i5, fabric_direct2_do_i6, fabric_direct2_do_i7, fabric_direct2_do_i8, fabric_direct2_do_i9, fabric_direct2_do_i10, fabric_direct2_do_i11, fabric_direct2_do_i12, fabric_direct2_do_i13, fabric_direct2_do_i14, fabric_direct2_do_i15, fabric_direct2_do_i16, fabric_direct2_do_i17, fabric_direct2_do_i18, fabric_direct2_do_i19, fabric_direct2_do_i20, fabric_direct2_do_i21 +, fabric_direct2_do_i22, fabric_direct2_do_i23, fabric_direct2_do_i24, fabric_direct2_do_ena_i1, fabric_direct2_do_ena_i2, fabric_direct2_do_ena_i3, fabric_direct2_do_ena_i4, fabric_direct2_do_ena_i5, fabric_direct2_do_ena_i6, fabric_direct2_do_ena_i7, fabric_direct2_do_ena_i8, fabric_direct2_do_ena_i9, fabric_direct2_do_ena_i10, fabric_direct2_do_ena_i11, fabric_direct2_do_ena_i12, fabric_direct2_do_ena_i13, fabric_direct2_do_ena_i14, fabric_direct2_do_ena_i15, fabric_direct2_do_ena_i16, fabric_direct2_do_ena_i17, fabric_direct2_do_ena_i18 +, fabric_direct2_do_ena_i19, fabric_direct2_do_ena_i20, fabric_direct2_do_ena_i21, fabric_direct2_do_ena_i22, fabric_direct2_do_ena_i23, fabric_direct2_do_ena_i24, fabric_direct2_do_rs_i1, fabric_direct2_do_rs_i2, fabric_direct2_do_rs_i3, fabric_direct2_do_rs_i4, fabric_direct2_do_rs_i5, fabric_direct2_do_rs_i6, fabric_direct2_do_rs_i7, fabric_direct2_do_rs_i8, fabric_direct2_do_rs_i9, fabric_direct2_do_rs_i10, fabric_direct2_do_rs_i11, fabric_direct2_do_rs_i12, fabric_direct2_do_rs_i13, fabric_direct2_do_rs_i14, fabric_direct2_do_rs_i15 +, fabric_direct2_do_rs_i16, fabric_direct2_do_rs_i17, fabric_direct2_do_rs_i18, fabric_direct2_do_rs_i19, fabric_direct2_do_rs_i20, fabric_direct2_do_rs_i21, fabric_direct2_do_rs_i22, fabric_direct2_do_rs_i23, fabric_direct2_do_rs_i24, fabric_direct2_di_o1, fabric_direct2_di_o2, fabric_direct2_di_o3, fabric_direct2_di_o4, fabric_direct2_di_o5, fabric_direct2_di_o6, fabric_direct2_di_o7, fabric_direct2_di_o8, fabric_direct2_di_o9, fabric_direct2_di_o10, fabric_direct2_di_o11, fabric_direct2_di_o12 +, fabric_direct2_di_o13, fabric_direct2_di_o14, fabric_direct2_di_o15, fabric_direct2_di_o16, fabric_direct2_di_o17, fabric_direct2_di_o18, fabric_direct2_di_o19, fabric_direct2_di_o20, fabric_direct2_di_o21, fabric_direct2_di_o22, fabric_direct2_di_o23, fabric_direct2_di_o24, fabric_direct2_di_ena_i1, fabric_direct2_di_ena_i2, fabric_direct2_di_ena_i3, fabric_direct2_di_ena_i4, fabric_direct2_di_ena_i5, fabric_direct2_di_ena_i6, fabric_direct2_di_ena_i7, fabric_direct2_di_ena_i8, fabric_direct2_di_ena_i9 +, fabric_direct2_di_ena_i10, fabric_direct2_di_ena_i11, fabric_direct2_di_ena_i12, fabric_direct2_di_ena_i13, fabric_direct2_di_ena_i14, fabric_direct2_di_ena_i15, fabric_direct2_di_ena_i16, fabric_direct2_di_ena_i17, fabric_direct2_di_ena_i18, fabric_direct2_di_ena_i19, fabric_direct2_di_ena_i20, fabric_direct2_di_ena_i21, fabric_direct2_di_ena_i22, fabric_direct2_di_ena_i23, fabric_direct2_di_ena_i24, fabric_direct2_di_rs_i1, fabric_direct2_di_rs_i2, fabric_direct2_di_rs_i3, fabric_direct2_di_rs_i4, fabric_direct2_di_rs_i5, fabric_direct2_di_rs_i6 +, fabric_direct2_di_rs_i7, fabric_direct2_di_rs_i8, fabric_direct2_di_rs_i9, fabric_direct2_di_rs_i10, fabric_direct2_di_rs_i11, fabric_direct2_di_rs_i12, fabric_direct2_di_rs_i13, fabric_direct2_di_rs_i14, fabric_direct2_di_rs_i15, fabric_direct2_di_rs_i16, fabric_direct2_di_rs_i17, fabric_direct2_di_rs_i18, fabric_direct2_di_rs_i19, fabric_direct2_di_rs_i20, fabric_direct2_di_rs_i21, fabric_direct2_di_rs_i22, fabric_direct2_di_rs_i23, fabric_direct2_di_rs_i24, fabric_direct2_cfg_bank_i1, fabric_direct2_cfg_bank_i2, fabric_direct2_cfg_bank_i3 +, fabric_direct2_cfg_bank_i4, fabric_direct2_cfg_pad_i1, fabric_direct2_cfg_pad_i2, fabric_direct2_cfg_pad_i3, fabric_direct2_cfg_pad_i4, fabric_direct2_cfg_pad_i5, fabric_direct2_cfg_pad_i6, fabric_direct2_cfg_pad_i7, fabric_direct2_cfg_pad_i8, fabric_direct2_cfg_pad_i9, fabric_direct2_cfg_pad_i10, fabric_direct2_cfg_pad_i11, fabric_direct2_cfg_pad_i12, fabric_direct2_cfg_pad_i13, fabric_direct2_cfg_pad_i14, fabric_direct2_cfg_pad_i15, fabric_direct2_cfg_pad_i16, fabric_direct2_cfg_pad_i17, fabric_direct2_cfg_pad_i18, fabric_direct2_cfg_pad_i19, fabric_direct2_cfg_pad_i20 +, fabric_direct2_cfg_pad_i21, fabric_direct2_cfg_pad_i22, fabric_direct2_cfg_pad_i23, fabric_direct2_cfg_pad_i24, fabric_direct2_cfg_pad_i25, fabric_direct2_cfg_pad_i26, fabric_direct2_cfg_pad_i27, fabric_direct2_cfg_pad_i28, fabric_direct2_cfg_pad_i29, fabric_direct2_cfg_pad_i30, fabric_direct2_cfg_pad_i31, fabric_direct2_cfg_pad_i32, fabric_direct2_cfg_pad_i33, fabric_direct2_cfg_pad_i34, fabric_direct2_cfg_pad_i35, fabric_direct2_cfg_pad_i36, fabric_direct2_cfg_pad_i37, fabric_direct2_cfg_pad_i38, fabric_direct2_cfg_pad_i39, fabric_direct2_cfg_pad_i40, fabric_direct2_cfg_pad_i41 +, fabric_direct2_cfg_pad_i42, fabric_direct2_cfg_pad_i43, fabric_direct2_cfg_pad_i44, fabric_direct2_cfg_pad_i45, fabric_direct2_cfg_pad_i46, fabric_direct2_cfg_pad_i47, fabric_direct2_cfg_pad_i48, fabric_direct2_cfg_pad_i49, fabric_direct2_cfg_pad_i50, fabric_direct2_cfg_pad_i51, fabric_direct2_cfg_pad_i52, fabric_direct2_cfg_pad_i53, fabric_direct2_cfg_pad_i54, fabric_direct2_cfg_pad_i55, fabric_direct2_cfg_pad_i56, fabric_direct2_cfg_pad_i57, fabric_direct2_cfg_pad_i58, fabric_direct2_cfg_pad_i59, fabric_direct2_cfg_pad_i60, fabric_direct2_cfg_pad_i61, fabric_direct2_cfg_pad_i62 +, fabric_direct2_cfg_pad_i63, fabric_direct2_cfg_pad_i64, fabric_direct2_cfg_pad_i65, fabric_direct2_cfg_pad_i66, fabric_direct2_cfg_pad_i67, fabric_direct2_cfg_pad_i68, fabric_direct2_cfg_pad_i69, fabric_direct2_cfg_pad_i70, fabric_direct2_cfg_pad_i71, fabric_direct2_cfg_pad_i72, fabric_direct2_cfg_pad_i73, fabric_direct2_cfg_pad_i74, fabric_direct2_cfg_pad_i75, fabric_direct2_cfg_pad_i76, fabric_direct2_cfg_pad_i77, fabric_direct2_cfg_pad_i78, fabric_direct2_cfg_pad_i79, fabric_direct2_cfg_pad_i80, fabric_direct2_cfg_pad_i81, fabric_direct2_cfg_pad_i82, fabric_direct2_cfg_pad_i83 +, fabric_direct2_cfg_pad_i84, fabric_direct2_cfg_pad_i85, fabric_direct2_cfg_pad_i86, fabric_direct2_cfg_pad_i87, fabric_direct2_cfg_pad_i88, fabric_direct2_cfg_pad_i89, fabric_direct2_cfg_pad_i90, fabric_direct2_cfg_pad_i91, fabric_direct2_cfg_pad_i92, fabric_direct2_cfg_pad_i93, fabric_direct2_cfg_pad_i94, fabric_direct2_cfg_pad_i95, fabric_direct2_cfg_pad_i96, fabric_direct2_cfg_pad_i97, fabric_direct2_cfg_pad_i98, fabric_direct2_cfg_pad_i99, fabric_direct2_cfg_pad_i100, fabric_direct2_cfg_pad_i101, fabric_direct2_cfg_pad_i102, fabric_direct2_cfg_pad_i103, fabric_direct2_cfg_pad_i104 +, fabric_direct2_cfg_pad_i105, fabric_direct2_cfg_pad_i106, fabric_direct2_cfg_pad_i107, fabric_direct2_cfg_pad_i108, fabric_direct2_cfg_pad_i109, fabric_direct2_cfg_pad_i110, fabric_direct2_cfg_pad_i111, fabric_direct2_cfg_pad_i112, fabric_direct2_cfg_pad_i113, fabric_direct2_cfg_pad_i114, fabric_direct2_cfg_pad_i115, fabric_direct2_cfg_pad_i116, fabric_direct2_cfg_pad_i117, fabric_direct2_cfg_pad_i118, fabric_direct2_cfg_pad_i119, fabric_direct2_cfg_pad_i120, fabric_direct2_cfg_pad_i121, fabric_direct2_cfg_pad_i122, fabric_direct2_cfg_pad_i123, fabric_direct2_cfg_pad_i124, fabric_direct2_cfg_pad_i125 +, fabric_direct2_cfg_pad_i126, fabric_direct2_cfg_pad_i127, fabric_direct2_cfg_pad_i128, fabric_direct2_cfg_pad_i129, fabric_direct2_cfg_pad_i130, fabric_direct2_cfg_pad_i131, fabric_direct2_cfg_pad_i132, fabric_direct2_cfg_pad_i133, fabric_direct2_cfg_pad_i134, fabric_direct2_cfg_pad_i135, fabric_direct2_cfg_pad_i136, fabric_direct2_cfg_pad_i137, fabric_direct2_cfg_pad_i138, fabric_direct2_cfg_pad_i139, fabric_direct2_cfg_pad_i140, fabric_direct2_cfg_pad_i141, fabric_direct2_cfg_pad_i142, fabric_direct2_cfg_pad_i143, fabric_direct2_cfg_pad_i144, fabric_direct2_cfg_pad_i145, fabric_direct2_cfg_pad_i146 +, fabric_direct2_cfg_pad_i147, fabric_direct2_cfg_pad_i148, fabric_direct2_cfg_pad_i149, fabric_direct2_cfg_pad_i150, fabric_direct2_cfg_pad_i151, fabric_direct2_cfg_pad_i152, fabric_direct2_cfg_pad_i153, fabric_direct2_cfg_pad_i154, fabric_direct2_cfg_pad_i155, fabric_direct2_cfg_pad_i156, fabric_direct2_cfg_pad_i157, fabric_direct2_cfg_pad_i158, fabric_direct2_cfg_pad_i159, fabric_direct2_cfg_pad_i160, fabric_direct2_cfg_pad_i161, fabric_direct2_cfg_pad_i162, fabric_direct2_cfg_pad_i163, fabric_direct2_cfg_pad_i164, fabric_direct2_cfg_pad_i165, fabric_direct2_cfg_pad_i166, fabric_direct2_cfg_pad_i167 +, fabric_direct2_cfg_pad_i168, fabric_direct2_cfg_pad_i169, fabric_direct2_cfg_pad_i170, fabric_direct2_cfg_pad_i171, fabric_direct2_cfg_pad_i172, fabric_direct2_cfg_pad_i173, fabric_direct2_cfg_pad_i174, fabric_direct2_cfg_pad_i175, fabric_direct2_cfg_pad_i176, fabric_direct2_cfg_pad_i177, fabric_direct2_cfg_pad_i178, fabric_direct2_cfg_pad_i179, fabric_direct2_cfg_pad_i180, fabric_direct2_cfg_pad_i181, fabric_direct2_cfg_pad_i182, fabric_direct2_cfg_pad_i183, fabric_direct2_cfg_pad_i184, fabric_direct2_cfg_pad_i185, fabric_direct2_cfg_pad_i186, fabric_direct2_cfg_pad_i187, fabric_direct2_cfg_pad_i188 +, fabric_direct2_cfg_pad_i189, fabric_direct2_cfg_pad_i190, fabric_direct2_cfg_pad_i191, fabric_direct2_cfg_pad_i192, fabric_direct2_cfg_pad_i193, fabric_direct2_cfg_pad_i194, fabric_direct2_cfg_pad_i195, fabric_direct2_cfg_pad_i196, fabric_direct2_cfg_pad_i197, fabric_direct2_cfg_pad_i198, fabric_direct2_cfg_pad_i199, fabric_direct2_cfg_pad_i200, fabric_direct2_cfg_pad_i201, fabric_direct2_cfg_pad_i202, fabric_direct2_cfg_pad_i203, fabric_direct2_cfg_pad_i204, fabric_direct2_cfg_pad_i205, fabric_direct2_cfg_pad_i206, fabric_direct2_cfg_pad_i207, fabric_direct2_cfg_pad_i208, fabric_direct2_cfg_pad_i209 +, fabric_direct2_cfg_pad_i210, fabric_direct2_cfg_pad_i211, fabric_direct2_cfg_pad_i212, fabric_direct2_cfg_pad_i213, fabric_direct2_cfg_pad_i214, fabric_direct2_cfg_pad_i215, fabric_direct2_cfg_pad_i216, fabric_direct2_cfg_pad_i217, fabric_direct2_cfg_pad_i218, fabric_direct2_cfg_pad_i219, fabric_direct2_cfg_pad_i220, fabric_direct2_cfg_pad_i221, fabric_direct2_cfg_pad_i222, fabric_direct2_cfg_pad_i223, fabric_direct2_cfg_pad_i224, fabric_direct2_cfg_pad_i225, fabric_direct2_cfg_pad_i226, fabric_direct2_cfg_pad_i227, fabric_direct2_cfg_pad_i228, fabric_direct2_cfg_pad_i229, fabric_direct2_cfg_pad_i230 +, fabric_direct2_cfg_pad_i231, fabric_direct2_cfg_pad_i232, fabric_direct2_cfg_pad_i233, fabric_direct2_cfg_pad_i234, fabric_direct2_cfg_pad_i235, fabric_direct2_cfg_pad_i236, fabric_direct2_cfg_pad_i237, fabric_direct2_cfg_pad_i238, fabric_direct2_cfg_pad_i239, fabric_direct2_cfg_pad_i240, fabric_direct2_cfg_pad_i241, fabric_direct2_cfg_pad_i242, fabric_direct2_cfg_pad_i243, fabric_direct2_cfg_pad_i244, fabric_direct2_cfg_pad_i245, fabric_direct2_cfg_pad_i246, fabric_direct2_cfg_pad_i247, fabric_direct2_cfg_pad_i248, fabric_direct2_cfg_pad_i249, fabric_direct2_cfg_pad_i250, fabric_direct2_cfg_pad_i251 +, fabric_direct2_cfg_pad_i252, fabric_direct2_cfg_pad_i253, fabric_direct2_cfg_pad_i254, fabric_direct2_cfg_pad_i255, fabric_direct2_cfg_pad_i256, fabric_direct2_cfg_pad_i257, fabric_direct2_cfg_pad_i258, fabric_direct2_cfg_pad_i259, fabric_direct2_cfg_pad_i260, fabric_direct2_cfg_pad_i261, fabric_direct2_cfg_pad_i262, fabric_direct2_cfg_pad_i263, fabric_direct2_cfg_pad_i264, fabric_direct2_cfg_pad_i265, fabric_direct2_cfg_pad_i266, fabric_direct2_cfg_pad_i267, fabric_direct2_cfg_pad_i268, fabric_direct2_cfg_pad_i269, fabric_direct2_cfg_pad_i270, fabric_direct2_cfg_pad_i271, fabric_direct2_cfg_pad_i272 +, fabric_direct2_cfg_pad_i273, fabric_direct2_cfg_pad_i274, fabric_direct2_cfg_pad_i275, fabric_direct2_cfg_pad_i276, fabric_direct2_cfg_pad_i277, fabric_direct2_cfg_pad_i278, fabric_direct2_cfg_pad_i279, fabric_direct2_cfg_pad_i280, fabric_direct2_cfg_pad_i281, fabric_direct2_cfg_pad_i282, fabric_direct2_cfg_pad_i283, fabric_direct2_cfg_pad_i284, fabric_direct2_cfg_pad_i285, fabric_direct2_cfg_pad_i286, fabric_direct2_cfg_pad_i287, fabric_direct2_cfg_pad_i288, fabric_direct2_cfg_pad_i289, fabric_direct2_cfg_pad_i290, fabric_direct2_cfg_pad_i291, fabric_direct2_cfg_pad_i292, fabric_direct2_cfg_pad_i293 +, fabric_direct2_cfg_pad_i294, fabric_direct2_cfg_pad_i295, fabric_direct2_cfg_pad_i296, fabric_direct2_cfg_pad_i297, fabric_direct2_cfg_pad_i298, fabric_direct2_cfg_pad_i299, fabric_direct2_cfg_pad_i300, fabric_direct2_cfg_pad_i301, fabric_direct2_cfg_pad_i302, fabric_direct2_cfg_pad_i303, fabric_direct2_cfg_pad_i304, fabric_direct2_cfg_pad_i305, fabric_direct2_cfg_pad_i306, fabric_direct2_cfg_pad_i307, fabric_direct2_cfg_pad_i308, fabric_direct2_cfg_pad_i309, fabric_direct2_cfg_pad_i310, fabric_direct2_cfg_pad_i311, fabric_direct2_cfg_pad_i312, fabric_direct2_cfg_pad_i313, fabric_direct2_cfg_pad_i314 +, fabric_direct2_cfg_pad_i315, fabric_direct2_cfg_pad_i316, fabric_direct2_cfg_pad_i317, fabric_direct2_cfg_pad_i318, fabric_direct2_cfg_pad_i319, fabric_direct2_cfg_pad_i320, fabric_direct2_cfg_pad_i321, fabric_direct2_cfg_pad_i322, fabric_direct2_cfg_pad_i323, fabric_direct2_cfg_pad_i324, fabric_direct2_cfg_pad_i325, fabric_direct2_cfg_pad_i326, fabric_direct2_cfg_pad_i327, fabric_direct2_cfg_pad_i328, fabric_direct2_cfg_pad_i329, fabric_direct2_cfg_pad_i330, fabric_direct2_cfg_pad_i331, fabric_direct2_cfg_pad_i332, fabric_direct2_cfg_pad_i333, fabric_direct2_cfg_pad_i334, fabric_direct2_cfg_pad_i335 +, fabric_direct2_cfg_pad_i336, fabric_direct2_cfg_pad_i337, fabric_direct2_cfg_pad_i338, fabric_direct2_cfg_pad_i339, fabric_direct2_cfg_pad_i340, fabric_direct2_cfg_pad_i341, fabric_direct2_cfg_pad_i342, fabric_direct2_cfg_pad_i343, fabric_direct2_cfg_pad_i344, fabric_direct2_cfg_pad_i345, fabric_direct2_cfg_pad_i346, fabric_direct2_cfg_pad_i347, fabric_direct2_cfg_pad_i348, fabric_direct2_cfg_pad_i349, fabric_direct2_cfg_pad_i350, fabric_direct2_cfg_pad_i351, fabric_direct2_cfg_pad_i352, fabric_direct2_cfg_pad_i353, fabric_direct2_cfg_pad_i354, fabric_direct2_cfg_pad_i355, fabric_direct2_cfg_pad_i356 +, fabric_direct2_cfg_pad_i357, fabric_direct2_cfg_pad_i358, fabric_direct2_cfg_pad_i359, fabric_direct2_cfg_pad_i360, fabric_direct2_cfg_pad_i361, fabric_direct2_cfg_pad_i362, fabric_direct2_cfg_pad_i363, fabric_direct2_cfg_pad_i364, fabric_direct2_cfg_pad_i365, fabric_direct2_cfg_pad_i366, fabric_direct2_cfg_pad_i367, fabric_direct2_cfg_pad_i368, fabric_direct2_cfg_pad_i369, fabric_direct2_cfg_pad_i370, fabric_direct2_cfg_pad_i371, fabric_direct2_cfg_pad_i372, fabric_direct2_cfg_pad_i373, fabric_direct2_cfg_pad_i374, fabric_direct2_cfg_pad_i375, fabric_direct2_cfg_pad_i376, fabric_direct2_cfg_pad_i377 +, fabric_direct2_cfg_pad_i378, fabric_direct2_cfg_pad_i379, fabric_direct2_cfg_pad_i380, fabric_direct2_cfg_pad_i381, fabric_direct2_cfg_pad_i382, fabric_direct2_cfg_pad_i383, fabric_direct2_cfg_pad_i384, fabric_direct2_cfg_pad_i385, fabric_direct2_cfg_pad_i386, fabric_direct2_cfg_pad_i387, fabric_direct2_cfg_pad_i388, fabric_direct2_cfg_pad_i389, fabric_direct2_cfg_pad_i390, fabric_direct2_cfg_pad_i391, fabric_direct2_cfg_pad_i392, fabric_direct2_cfg_pad_i393, fabric_direct2_cfg_pad_i394, fabric_direct2_cfg_pad_i395, fabric_direct2_cfg_pad_i396, fabric_direct2_cfg_pad_i397, fabric_direct2_cfg_pad_i398 +, fabric_direct2_cfg_pad_i399, fabric_direct2_cfg_pad_i400, fabric_direct2_cfg_pad_i401, fabric_direct2_cfg_pad_i402, fabric_direct2_cfg_pad_i403, fabric_direct2_cfg_pad_i404, fabric_direct2_cfg_pad_i405, fabric_direct2_cfg_pad_i406, fabric_direct2_cfg_pad_i407, fabric_direct2_cfg_pad_i408, fabric_direct2_cfg_pad_i409, fabric_direct2_cfg_pad_i410, fabric_direct2_cfg_pad_i411, fabric_direct2_cfg_pad_i412, fabric_direct2_cfg_pad_i413, fabric_direct2_cfg_pad_i414, fabric_direct2_cfg_pad_i415, fabric_direct2_cfg_pad_i416, fabric_direct2_cfg_pad_i417, fabric_direct2_cfg_pad_i418, fabric_direct2_cfg_pad_i419 +, fabric_direct2_cfg_pad_i420, fabric_direct2_cfg_pad_i421, fabric_direct2_cfg_pad_i422, fabric_direct2_cfg_pad_i423, fabric_direct2_cfg_pad_i424, fabric_direct2_cfg_pad_i425, fabric_direct2_cfg_pad_i426, fabric_direct2_cfg_pad_i427, fabric_direct2_cfg_pad_i428, fabric_direct2_cfg_pad_i429, fabric_direct2_cfg_pad_i430, fabric_direct2_cfg_pad_i431, fabric_direct2_cfg_pad_i432, fabric_direct2_cfg_pad_i433, fabric_direct2_cfg_pad_i434, fabric_direct2_cfg_pad_i435, fabric_direct2_cfg_pad_i436, fabric_direct2_cfg_pad_i437, fabric_direct2_cfg_pad_i438, fabric_direct2_cfg_pad_i439, fabric_direct2_cfg_pad_i440 +, fabric_direct2_cfg_pad_i441, fabric_direct2_cfg_pad_i442, fabric_direct2_cfg_pad_i443, fabric_direct2_cfg_pad_i444, fabric_direct2_cfg_pad_i445, fabric_direct2_cfg_pad_i446, fabric_direct2_cfg_pad_i447, fabric_direct2_cfg_pad_i448, fabric_direct2_cfg_pad_i449, fabric_direct2_cfg_pad_i450, fabric_direct2_cfg_pad_i451, fabric_direct2_cfg_pad_i452, fabric_direct2_cfg_pad_i453, fabric_direct2_cfg_pad_i454, fabric_direct2_cfg_pad_i455, fabric_direct2_cfg_pad_i456, fabric_direct2_cfg_pad_i457, fabric_direct2_cfg_pad_i458, fabric_direct2_cfg_pad_i459, fabric_direct2_cfg_pad_i460, fabric_direct2_cfg_pad_i461 +, fabric_direct2_cfg_pad_i462, fabric_direct2_cfg_pad_i463, fabric_direct2_cfg_pad_i464, fabric_direct2_cfg_pad_i465, fabric_direct2_cfg_pad_i466, fabric_direct2_cfg_pad_i467, fabric_direct2_cfg_pad_i468, fabric_direct2_cfg_pad_i469, fabric_direct2_cfg_pad_i470, fabric_direct2_cfg_pad_i471, fabric_direct2_cfg_pad_i472, fabric_direct2_cfg_pad_i473, fabric_direct2_cfg_pad_i474, fabric_direct2_cfg_pad_i475, fabric_direct2_cfg_pad_i476, fabric_direct2_cfg_pad_i477, fabric_direct2_cfg_pad_i478, fabric_direct2_cfg_pad_i479, fabric_direct2_cfg_pad_i480, fabric_direct2_cfg_pad_i481, fabric_direct2_cfg_pad_i482 +, fabric_direct2_cfg_pad_i483, fabric_direct2_cfg_pad_i484, fabric_direct2_cfg_pad_i485, fabric_direct2_cfg_pad_i486, fabric_direct2_cfg_pad_i487, fabric_direct2_cfg_pad_i488, fabric_direct2_cfg_pad_i489, fabric_direct2_cfg_pad_i490, fabric_direct2_cfg_pad_i491, fabric_direct2_cfg_pad_i492, fabric_direct2_cfg_pad_i493, fabric_direct2_cfg_pad_i494, fabric_direct2_cfg_pad_i495, fabric_direct2_cfg_pad_i496, fabric_direct2_cfg_pad_i497, fabric_direct2_cfg_pad_i498, fabric_direct2_cfg_pad_i499, fabric_direct2_cfg_pad_i500, fabric_direct2_cfg_pad_i501, fabric_direct2_cfg_pad_i502, fabric_direct2_cfg_pad_i503 +, fabric_direct2_cfg_pad_i504, fabric_direct2_cfg_pad_i505, fabric_direct2_cfg_pad_i506, fabric_direct2_cfg_pad_i507, fabric_direct2_cfg_pad_i508, fabric_direct2_cfg_pad_i509, fabric_direct2_cfg_pad_i510, fabric_direct2_cfg_pad_i511, fabric_direct2_cfg_pad_i512, fabric_direct2_cfg_pad_i513, fabric_direct2_cfg_pad_i514, fabric_direct2_cfg_pad_i515, fabric_direct2_cfg_pad_i516, fabric_direct2_cfg_pad_i517, fabric_direct2_cfg_pad_i518, fabric_direct2_cfg_pad_i519, fabric_direct2_cfg_pad_i520, fabric_direct2_cfg_pad_i521, fabric_direct2_cfg_pad_i522, fabric_direct2_cfg_pad_i523, fabric_direct2_cfg_pad_i524 +, fabric_direct2_cfg_pad_i525, fabric_direct2_cfg_pad_i526, fabric_direct2_cfg_pad_i527, fabric_direct2_cfg_pad_i528, fabric_direct2_cfg_pad_i529, fabric_direct2_cfg_pad_i530, fabric_direct2_cfg_pad_i531, fabric_direct2_cfg_pad_i532, fabric_direct2_cfg_pad_i533, fabric_direct2_cfg_pad_i534, fabric_direct2_cfg_pad_i535, fabric_direct2_cfg_pad_i536, fabric_direct2_cfg_pad_i537, fabric_direct2_cfg_pad_i538, fabric_direct2_cfg_pad_i539, fabric_direct2_cfg_pad_i540, fabric_direct2_cfg_pad_i541, fabric_direct2_cfg_pad_i542, fabric_direct2_cfg_pad_i543, fabric_direct2_cfg_pad_i544, fabric_direct2_cfg_pad_i545 +, fabric_direct2_cfg_pad_i546, fabric_direct2_cfg_pad_i547, fabric_direct2_cfg_pad_i548, fabric_direct2_cfg_pad_i549, fabric_direct2_cfg_pad_i550, fabric_direct2_cfg_pad_i551, fabric_direct2_cfg_pad_i552, fabric_direct2_cfg_pad_i553, fabric_direct2_cfg_pad_i554, fabric_direct2_cfg_pad_i555, fabric_direct2_cfg_pad_i556, fabric_direct2_cfg_pad_i557, fabric_direct2_cfg_pad_i558, fabric_direct2_cfg_pad_i559, fabric_direct2_cfg_pad_i560, fabric_direct2_cfg_pad_i561, fabric_direct2_cfg_pad_i562, fabric_direct2_cfg_pad_i563, fabric_direct2_cfg_pad_i564, fabric_direct2_cfg_pad_i565, fabric_direct2_cfg_pad_i566 +, fabric_direct2_cfg_pad_i567, fabric_direct2_cfg_pad_i568, fabric_direct2_cfg_pad_i569, fabric_direct2_cfg_pad_i570, fabric_direct2_cfg_pad_i571, fabric_direct2_cfg_pad_i572, fabric_direct2_cfg_pad_i573, fabric_direct2_cfg_pad_i574, fabric_direct2_cfg_pad_i575, fabric_direct2_cfg_pad_i576, fabric_direct2_cfg_pad_i577, fabric_direct2_cfg_pad_i578, fabric_direct2_cfg_pad_i579, fabric_direct2_cfg_pad_i580, fabric_direct2_cfg_pad_i581, fabric_direct2_cfg_pad_i582, fabric_direct2_cfg_pad_i583, fabric_direct2_cfg_pad_i584, fabric_direct2_cfg_pad_i585, fabric_direct2_cfg_pad_i586, fabric_direct2_cfg_pad_i587 +, fabric_direct2_cfg_pad_i588, fabric_direct2_cfg_pad_i589, fabric_direct2_cfg_pad_i590, fabric_direct2_cfg_pad_i591, fabric_direct2_cfg_pad_i592, fabric_direct2_cfg_pad_i593, fabric_direct2_cfg_pad_i594, fabric_direct2_cfg_pad_i595, fabric_direct2_cfg_pad_i596, fabric_direct2_cfg_pad_i597, fabric_direct2_cfg_pad_i598, fabric_direct2_cfg_pad_i599, fabric_direct2_cfg_pad_i600, fabric_direct2_cfg_pad_i601, fabric_direct2_cfg_pad_i602, fabric_direct2_cfg_pad_i603, fabric_direct2_cfg_pad_i604, fabric_direct2_cfg_pad_i605, fabric_direct2_cfg_pad_i606, fabric_direct2_cfg_pad_i607, fabric_direct2_cfg_pad_i608 +, fabric_direct2_cfg_pad_i609, fabric_direct2_cfg_pad_i610, fabric_direct2_cfg_pad_i611, fabric_direct2_cfg_pad_i612, fabric_direct2_cfg_pad_i613, fabric_direct2_cfg_pad_i614, fabric_direct2_cfg_pad_i615, fabric_direct2_cfg_pad_i616, fabric_direct2_cfg_pad_i617, fabric_direct2_cfg_pad_i618, fabric_direct2_cfg_pad_i619, fabric_direct2_cfg_pad_i620, fabric_direct2_cfg_pad_i621, fabric_direct2_cfg_pad_i622, fabric_direct2_cfg_pad_i623, fabric_direct2_cfg_pad_i624, fabric_direct2_cfg_pad_i625, fabric_direct2_cfg_pad_i626, fabric_direct2_cfg_pad_i627, fabric_direct2_cfg_pad_i628, fabric_direct2_cfg_pad_i629 +, fabric_direct2_cfg_pad_i630, fabric_direct2_cfg_pad_i631, fabric_direct2_cfg_pad_i632, fabric_direct2_cfg_pad_i633, fabric_direct2_cfg_pad_i634, fabric_direct2_cfg_pad_i635, fabric_direct2_cfg_pad_i636, fabric_direct2_cfg_pad_i637, fabric_direct2_cfg_pad_i638, fabric_direct2_cfg_pad_i639, fabric_direct2_cfg_pad_i640, fabric_direct2_cfg_pad_i641, fabric_direct2_cfg_pad_i642, fabric_direct2_cfg_pad_i643, fabric_direct2_cfg_pad_i644, fabric_direct2_cfg_pad_i645, fabric_direct2_cfg_pad_i646, fabric_direct2_cfg_pad_i647, fabric_direct2_cfg_pad_i648, fabric_direct2_cfg_pad_i649, fabric_direct2_cfg_pad_i650 +, fabric_direct2_cfg_pad_i651, fabric_direct2_cfg_pad_i652, fabric_direct2_cfg_pad_i653, fabric_direct2_cfg_pad_i654, fabric_direct2_cfg_pad_i655, fabric_direct2_cfg_pad_i656, fabric_direct2_cfg_pad_i657, fabric_direct2_cfg_pad_i658, fabric_direct2_cfg_pad_i659, fabric_direct2_cfg_pad_i660, fabric_direct2_cfg_pad_i661, fabric_direct2_cfg_pad_i662, fabric_direct2_cfg_pad_i663, fabric_direct2_cfg_pad_i664, fabric_direct2_cfg_pad_i665, fabric_direct2_cfg_pad_i666, fabric_direct2_cfg_pad_i667, fabric_direct2_cfg_pad_i668, fabric_direct2_cfg_pad_i669, fabric_direct2_cfg_pad_i670, fabric_direct2_cfg_pad_i671 +, fabric_direct2_cfg_pad_i672, fabric_direct2_cfg_pad_i673, fabric_direct2_cfg_pad_i674, fabric_direct2_cfg_pad_i675, fabric_direct2_cfg_pad_i676, fabric_direct2_cfg_pad_i677, fabric_direct2_cfg_pad_i678, fabric_direct2_cfg_pad_i679, fabric_direct2_cfg_pad_i680, fabric_direct2_cfg_pad_i681, fabric_direct2_cfg_pad_i682, fabric_direct2_cfg_pad_i683, fabric_direct2_cfg_pad_i684, fabric_direct2_cfg_pad_i685, fabric_direct2_cfg_pad_i686, fabric_direct2_cfg_pad_i687, fabric_direct2_cfg_pad_i688, fabric_direct2_cfg_pad_i689, fabric_direct2_cfg_pad_i690, fabric_direct2_cfg_pad_i691, fabric_direct2_cfg_pad_i692 +, fabric_direct2_cfg_pad_i693, fabric_direct2_cfg_pad_i694, fabric_direct2_cfg_pad_i695, fabric_direct2_cfg_pad_i696, fabric_direct2_cfg_pad_i697, fabric_direct2_cfg_pad_i698, fabric_direct2_cfg_pad_i699, fabric_direct2_cfg_pad_i700, fabric_direct2_cfg_pad_i701, fabric_direct2_cfg_pad_i702, fabric_direct2_cfg_pad_i703, fabric_direct2_cfg_pad_i704, fabric_direct2_cfg_pad_i705, fabric_direct2_cfg_pad_i706, fabric_direct2_cfg_pad_i707, fabric_direct2_cfg_pad_i708, fabric_direct2_cfg_pad_i709, fabric_direct2_cfg_pad_i710, fabric_direct2_cfg_pad_i711, fabric_direct2_cfg_pad_i712, fabric_direct2_cfg_pad_i713 +, fabric_direct2_cfg_pad_i714, fabric_direct2_cfg_pad_i715, fabric_direct2_cfg_pad_i716, fabric_direct2_cfg_pad_i717, fabric_direct2_cfg_pad_i718, fabric_direct2_cfg_pad_i719, fabric_direct2_cfg_pad_i720, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_clock_fabric_i1, fabric_direct1_clock_fabric_i2, fabric_direct1_clock_fabric_i3, fabric_direct1_clock_fabric_i4, fabric_direct1_oe_i1, fabric_direct1_oe_i2, fabric_direct1_oe_i3, fabric_direct1_oe_i4, fabric_direct1_oe_i5, fabric_direct1_oe_i6, fabric_direct1_oe_i7 +, fabric_direct1_oe_i8, fabric_direct1_oe_i9, fabric_direct1_oe_i10, fabric_direct1_oe_i11, fabric_direct1_oe_i12, fabric_direct1_oe_i13, fabric_direct1_oe_i14, fabric_direct1_oe_i15, fabric_direct1_oe_i16, fabric_direct1_oe_ena_i1, fabric_direct1_oe_ena_i2, fabric_direct1_oe_ena_i3, fabric_direct1_oe_ena_i4, fabric_direct1_oe_ena_i5, fabric_direct1_oe_ena_i6, fabric_direct1_oe_ena_i7, fabric_direct1_oe_ena_i8, fabric_direct1_oe_ena_i9, fabric_direct1_oe_ena_i10, fabric_direct1_oe_ena_i11, fabric_direct1_oe_ena_i12 +, fabric_direct1_oe_ena_i13, fabric_direct1_oe_ena_i14, fabric_direct1_oe_ena_i15, fabric_direct1_oe_ena_i16, fabric_direct1_oe_rs_i1, fabric_direct1_oe_rs_i2, fabric_direct1_oe_rs_i3, fabric_direct1_oe_rs_i4, fabric_direct1_oe_rs_i5, fabric_direct1_oe_rs_i6, fabric_direct1_oe_rs_i7, fabric_direct1_oe_rs_i8, fabric_direct1_oe_rs_i9, fabric_direct1_oe_rs_i10, fabric_direct1_oe_rs_i11, fabric_direct1_oe_rs_i12, fabric_direct1_oe_rs_i13, fabric_direct1_oe_rs_i14, fabric_direct1_oe_rs_i15, fabric_direct1_oe_rs_i16, fabric_direct1_do_i1 +, fabric_direct1_do_i2, fabric_direct1_do_i3, fabric_direct1_do_i4, fabric_direct1_do_i5, fabric_direct1_do_i6, fabric_direct1_do_i7, fabric_direct1_do_i8, fabric_direct1_do_i9, fabric_direct1_do_i10, fabric_direct1_do_i11, fabric_direct1_do_i12, fabric_direct1_do_i13, fabric_direct1_do_i14, fabric_direct1_do_i15, fabric_direct1_do_i16, fabric_direct1_do_ena_i1, fabric_direct1_do_ena_i2, fabric_direct1_do_ena_i3, fabric_direct1_do_ena_i4, fabric_direct1_do_ena_i5, fabric_direct1_do_ena_i6 +, fabric_direct1_do_ena_i7, fabric_direct1_do_ena_i8, fabric_direct1_do_ena_i9, fabric_direct1_do_ena_i10, fabric_direct1_do_ena_i11, fabric_direct1_do_ena_i12, fabric_direct1_do_ena_i13, fabric_direct1_do_ena_i14, fabric_direct1_do_ena_i15, fabric_direct1_do_ena_i16, fabric_direct1_do_rs_i1, fabric_direct1_do_rs_i2, fabric_direct1_do_rs_i3, fabric_direct1_do_rs_i4, fabric_direct1_do_rs_i5, fabric_direct1_do_rs_i6, fabric_direct1_do_rs_i7, fabric_direct1_do_rs_i8, fabric_direct1_do_rs_i9, fabric_direct1_do_rs_i10, fabric_direct1_do_rs_i11 +, fabric_direct1_do_rs_i12, fabric_direct1_do_rs_i13, fabric_direct1_do_rs_i14, fabric_direct1_do_rs_i15, fabric_direct1_do_rs_i16, fabric_direct1_di_o1, fabric_direct1_di_o2, fabric_direct1_di_o3, fabric_direct1_di_o4, fabric_direct1_di_o5, fabric_direct1_di_o6, fabric_direct1_di_o7, fabric_direct1_di_o8, fabric_direct1_di_o9, fabric_direct1_di_o10, fabric_direct1_di_o11, fabric_direct1_di_o12, fabric_direct1_di_o13, fabric_direct1_di_o14, fabric_direct1_di_o15, fabric_direct1_di_o16 +, fabric_direct1_di_ena_i1, fabric_direct1_di_ena_i2, fabric_direct1_di_ena_i3, fabric_direct1_di_ena_i4, fabric_direct1_di_ena_i5, fabric_direct1_di_ena_i6, fabric_direct1_di_ena_i7, fabric_direct1_di_ena_i8, fabric_direct1_di_ena_i9, fabric_direct1_di_ena_i10, fabric_direct1_di_ena_i11, fabric_direct1_di_ena_i12, fabric_direct1_di_ena_i13, fabric_direct1_di_ena_i14, fabric_direct1_di_ena_i15, fabric_direct1_di_ena_i16, fabric_direct1_di_rs_i1, fabric_direct1_di_rs_i2, fabric_direct1_di_rs_i3, fabric_direct1_di_rs_i4, fabric_direct1_di_rs_i5 +, fabric_direct1_di_rs_i6, fabric_direct1_di_rs_i7, fabric_direct1_di_rs_i8, fabric_direct1_di_rs_i9, fabric_direct1_di_rs_i10, fabric_direct1_di_rs_i11, fabric_direct1_di_rs_i12, fabric_direct1_di_rs_i13, fabric_direct1_di_rs_i14, fabric_direct1_di_rs_i15, fabric_direct1_di_rs_i16, fabric_direct1_cfg_bank_i1, fabric_direct1_cfg_bank_i2, fabric_direct1_cfg_bank_i3, fabric_direct1_cfg_bank_i4, fabric_direct1_cfg_pad_i1, fabric_direct1_cfg_pad_i2, fabric_direct1_cfg_pad_i3, fabric_direct1_cfg_pad_i4, fabric_direct1_cfg_pad_i5, fabric_direct1_cfg_pad_i6 +, fabric_direct1_cfg_pad_i7, fabric_direct1_cfg_pad_i8, fabric_direct1_cfg_pad_i9, fabric_direct1_cfg_pad_i10, fabric_direct1_cfg_pad_i11, fabric_direct1_cfg_pad_i12, fabric_direct1_cfg_pad_i13, fabric_direct1_cfg_pad_i14, fabric_direct1_cfg_pad_i15, fabric_direct1_cfg_pad_i16, fabric_direct1_cfg_pad_i17, fabric_direct1_cfg_pad_i18, fabric_direct1_cfg_pad_i19, fabric_direct1_cfg_pad_i20, fabric_direct1_cfg_pad_i21, fabric_direct1_cfg_pad_i22, fabric_direct1_cfg_pad_i23, fabric_direct1_cfg_pad_i24, fabric_direct1_cfg_pad_i25, fabric_direct1_cfg_pad_i26, fabric_direct1_cfg_pad_i27 +, fabric_direct1_cfg_pad_i28, fabric_direct1_cfg_pad_i29, fabric_direct1_cfg_pad_i30, fabric_direct1_cfg_pad_i31, fabric_direct1_cfg_pad_i32, fabric_direct1_cfg_pad_i33, fabric_direct1_cfg_pad_i34, fabric_direct1_cfg_pad_i35, fabric_direct1_cfg_pad_i36, fabric_direct1_cfg_pad_i37, fabric_direct1_cfg_pad_i38, fabric_direct1_cfg_pad_i39, fabric_direct1_cfg_pad_i40, fabric_direct1_cfg_pad_i41, fabric_direct1_cfg_pad_i42, fabric_direct1_cfg_pad_i43, fabric_direct1_cfg_pad_i44, fabric_direct1_cfg_pad_i45, fabric_direct1_cfg_pad_i46, fabric_direct1_cfg_pad_i47, fabric_direct1_cfg_pad_i48 +, fabric_direct1_cfg_pad_i49, fabric_direct1_cfg_pad_i50, fabric_direct1_cfg_pad_i51, fabric_direct1_cfg_pad_i52, fabric_direct1_cfg_pad_i53, fabric_direct1_cfg_pad_i54, fabric_direct1_cfg_pad_i55, fabric_direct1_cfg_pad_i56, fabric_direct1_cfg_pad_i57, fabric_direct1_cfg_pad_i58, fabric_direct1_cfg_pad_i59, fabric_direct1_cfg_pad_i60, fabric_direct1_cfg_pad_i61, fabric_direct1_cfg_pad_i62, fabric_direct1_cfg_pad_i63, fabric_direct1_cfg_pad_i64, fabric_direct1_cfg_pad_i65, fabric_direct1_cfg_pad_i66, fabric_direct1_cfg_pad_i67, fabric_direct1_cfg_pad_i68, fabric_direct1_cfg_pad_i69 +, fabric_direct1_cfg_pad_i70, fabric_direct1_cfg_pad_i71, fabric_direct1_cfg_pad_i72, fabric_direct1_cfg_pad_i73, fabric_direct1_cfg_pad_i74, fabric_direct1_cfg_pad_i75, fabric_direct1_cfg_pad_i76, fabric_direct1_cfg_pad_i77, fabric_direct1_cfg_pad_i78, fabric_direct1_cfg_pad_i79, fabric_direct1_cfg_pad_i80, fabric_direct1_cfg_pad_i81, fabric_direct1_cfg_pad_i82, fabric_direct1_cfg_pad_i83, fabric_direct1_cfg_pad_i84, fabric_direct1_cfg_pad_i85, fabric_direct1_cfg_pad_i86, fabric_direct1_cfg_pad_i87, fabric_direct1_cfg_pad_i88, fabric_direct1_cfg_pad_i89, fabric_direct1_cfg_pad_i90 +, fabric_direct1_cfg_pad_i91, fabric_direct1_cfg_pad_i92, fabric_direct1_cfg_pad_i93, fabric_direct1_cfg_pad_i94, fabric_direct1_cfg_pad_i95, fabric_direct1_cfg_pad_i96, fabric_direct1_cfg_pad_i97, fabric_direct1_cfg_pad_i98, fabric_direct1_cfg_pad_i99, fabric_direct1_cfg_pad_i100, fabric_direct1_cfg_pad_i101, fabric_direct1_cfg_pad_i102, fabric_direct1_cfg_pad_i103, fabric_direct1_cfg_pad_i104, fabric_direct1_cfg_pad_i105, fabric_direct1_cfg_pad_i106, fabric_direct1_cfg_pad_i107, fabric_direct1_cfg_pad_i108, fabric_direct1_cfg_pad_i109, fabric_direct1_cfg_pad_i110, fabric_direct1_cfg_pad_i111 +, fabric_direct1_cfg_pad_i112, fabric_direct1_cfg_pad_i113, fabric_direct1_cfg_pad_i114, fabric_direct1_cfg_pad_i115, fabric_direct1_cfg_pad_i116, fabric_direct1_cfg_pad_i117, fabric_direct1_cfg_pad_i118, fabric_direct1_cfg_pad_i119, fabric_direct1_cfg_pad_i120, fabric_direct1_cfg_pad_i121, fabric_direct1_cfg_pad_i122, fabric_direct1_cfg_pad_i123, fabric_direct1_cfg_pad_i124, fabric_direct1_cfg_pad_i125, fabric_direct1_cfg_pad_i126, fabric_direct1_cfg_pad_i127, fabric_direct1_cfg_pad_i128, fabric_direct1_cfg_pad_i129, fabric_direct1_cfg_pad_i130, fabric_direct1_cfg_pad_i131, fabric_direct1_cfg_pad_i132 +, fabric_direct1_cfg_pad_i133, fabric_direct1_cfg_pad_i134, fabric_direct1_cfg_pad_i135, fabric_direct1_cfg_pad_i136, fabric_direct1_cfg_pad_i137, fabric_direct1_cfg_pad_i138, fabric_direct1_cfg_pad_i139, fabric_direct1_cfg_pad_i140, fabric_direct1_cfg_pad_i141, fabric_direct1_cfg_pad_i142, fabric_direct1_cfg_pad_i143, fabric_direct1_cfg_pad_i144, fabric_direct1_cfg_pad_i145, fabric_direct1_cfg_pad_i146, fabric_direct1_cfg_pad_i147, fabric_direct1_cfg_pad_i148, fabric_direct1_cfg_pad_i149, fabric_direct1_cfg_pad_i150, fabric_direct1_cfg_pad_i151, fabric_direct1_cfg_pad_i152, fabric_direct1_cfg_pad_i153 +, fabric_direct1_cfg_pad_i154, fabric_direct1_cfg_pad_i155, fabric_direct1_cfg_pad_i156, fabric_direct1_cfg_pad_i157, fabric_direct1_cfg_pad_i158, fabric_direct1_cfg_pad_i159, fabric_direct1_cfg_pad_i160, fabric_direct1_cfg_pad_i161, fabric_direct1_cfg_pad_i162, fabric_direct1_cfg_pad_i163, fabric_direct1_cfg_pad_i164, fabric_direct1_cfg_pad_i165, fabric_direct1_cfg_pad_i166, fabric_direct1_cfg_pad_i167, fabric_direct1_cfg_pad_i168, fabric_direct1_cfg_pad_i169, fabric_direct1_cfg_pad_i170, fabric_direct1_cfg_pad_i171, fabric_direct1_cfg_pad_i172, fabric_direct1_cfg_pad_i173, fabric_direct1_cfg_pad_i174 +, fabric_direct1_cfg_pad_i175, fabric_direct1_cfg_pad_i176, fabric_direct1_cfg_pad_i177, fabric_direct1_cfg_pad_i178, fabric_direct1_cfg_pad_i179, fabric_direct1_cfg_pad_i180, fabric_direct1_cfg_pad_i181, fabric_direct1_cfg_pad_i182, fabric_direct1_cfg_pad_i183, fabric_direct1_cfg_pad_i184, fabric_direct1_cfg_pad_i185, fabric_direct1_cfg_pad_i186, fabric_direct1_cfg_pad_i187, fabric_direct1_cfg_pad_i188, fabric_direct1_cfg_pad_i189, fabric_direct1_cfg_pad_i190, fabric_direct1_cfg_pad_i191, fabric_direct1_cfg_pad_i192, fabric_direct1_cfg_pad_i193, fabric_direct1_cfg_pad_i194, fabric_direct1_cfg_pad_i195 +, fabric_direct1_cfg_pad_i196, fabric_direct1_cfg_pad_i197, fabric_direct1_cfg_pad_i198, fabric_direct1_cfg_pad_i199, fabric_direct1_cfg_pad_i200, fabric_direct1_cfg_pad_i201, fabric_direct1_cfg_pad_i202, fabric_direct1_cfg_pad_i203, fabric_direct1_cfg_pad_i204, fabric_direct1_cfg_pad_i205, fabric_direct1_cfg_pad_i206, fabric_direct1_cfg_pad_i207, fabric_direct1_cfg_pad_i208, fabric_direct1_cfg_pad_i209, fabric_direct1_cfg_pad_i210, fabric_direct1_cfg_pad_i211, fabric_direct1_cfg_pad_i212, fabric_direct1_cfg_pad_i213, fabric_direct1_cfg_pad_i214, fabric_direct1_cfg_pad_i215, fabric_direct1_cfg_pad_i216 +, fabric_direct1_cfg_pad_i217, fabric_direct1_cfg_pad_i218, fabric_direct1_cfg_pad_i219, fabric_direct1_cfg_pad_i220, fabric_direct1_cfg_pad_i221, fabric_direct1_cfg_pad_i222, fabric_direct1_cfg_pad_i223, fabric_direct1_cfg_pad_i224, fabric_direct1_cfg_pad_i225, fabric_direct1_cfg_pad_i226, fabric_direct1_cfg_pad_i227, fabric_direct1_cfg_pad_i228, fabric_direct1_cfg_pad_i229, fabric_direct1_cfg_pad_i230, fabric_direct1_cfg_pad_i231, fabric_direct1_cfg_pad_i232, fabric_direct1_cfg_pad_i233, fabric_direct1_cfg_pad_i234, fabric_direct1_cfg_pad_i235, fabric_direct1_cfg_pad_i236, fabric_direct1_cfg_pad_i237 +, fabric_direct1_cfg_pad_i238, fabric_direct1_cfg_pad_i239, fabric_direct1_cfg_pad_i240, fabric_direct1_cfg_pad_i241, fabric_direct1_cfg_pad_i242, fabric_direct1_cfg_pad_i243, fabric_direct1_cfg_pad_i244, fabric_direct1_cfg_pad_i245, fabric_direct1_cfg_pad_i246, fabric_direct1_cfg_pad_i247, fabric_direct1_cfg_pad_i248, fabric_direct1_cfg_pad_i249, fabric_direct1_cfg_pad_i250, fabric_direct1_cfg_pad_i251, fabric_direct1_cfg_pad_i252, fabric_direct1_cfg_pad_i253, fabric_direct1_cfg_pad_i254, fabric_direct1_cfg_pad_i255, fabric_direct1_cfg_pad_i256, fabric_direct1_cfg_pad_i257, fabric_direct1_cfg_pad_i258 +, fabric_direct1_cfg_pad_i259, fabric_direct1_cfg_pad_i260, fabric_direct1_cfg_pad_i261, fabric_direct1_cfg_pad_i262, fabric_direct1_cfg_pad_i263, fabric_direct1_cfg_pad_i264, fabric_direct1_cfg_pad_i265, fabric_direct1_cfg_pad_i266, fabric_direct1_cfg_pad_i267, fabric_direct1_cfg_pad_i268, fabric_direct1_cfg_pad_i269, fabric_direct1_cfg_pad_i270, fabric_direct1_cfg_pad_i271, fabric_direct1_cfg_pad_i272, fabric_direct1_cfg_pad_i273, fabric_direct1_cfg_pad_i274, fabric_direct1_cfg_pad_i275, fabric_direct1_cfg_pad_i276, fabric_direct1_cfg_pad_i277, fabric_direct1_cfg_pad_i278, fabric_direct1_cfg_pad_i279 +, fabric_direct1_cfg_pad_i280, fabric_direct1_cfg_pad_i281, fabric_direct1_cfg_pad_i282, fabric_direct1_cfg_pad_i283, fabric_direct1_cfg_pad_i284, fabric_direct1_cfg_pad_i285, fabric_direct1_cfg_pad_i286, fabric_direct1_cfg_pad_i287, fabric_direct1_cfg_pad_i288, fabric_direct1_cfg_pad_i289, fabric_direct1_cfg_pad_i290, fabric_direct1_cfg_pad_i291, fabric_direct1_cfg_pad_i292, fabric_direct1_cfg_pad_i293, fabric_direct1_cfg_pad_i294, fabric_direct1_cfg_pad_i295, fabric_direct1_cfg_pad_i296, fabric_direct1_cfg_pad_i297, fabric_direct1_cfg_pad_i298, fabric_direct1_cfg_pad_i299, fabric_direct1_cfg_pad_i300 +, fabric_direct1_cfg_pad_i301, fabric_direct1_cfg_pad_i302, fabric_direct1_cfg_pad_i303, fabric_direct1_cfg_pad_i304, fabric_direct1_cfg_pad_i305, fabric_direct1_cfg_pad_i306, fabric_direct1_cfg_pad_i307, fabric_direct1_cfg_pad_i308, fabric_direct1_cfg_pad_i309, fabric_direct1_cfg_pad_i310, fabric_direct1_cfg_pad_i311, fabric_direct1_cfg_pad_i312, fabric_direct1_cfg_pad_i313, fabric_direct1_cfg_pad_i314, fabric_direct1_cfg_pad_i315, fabric_direct1_cfg_pad_i316, fabric_direct1_cfg_pad_i317, fabric_direct1_cfg_pad_i318, fabric_direct1_cfg_pad_i319, fabric_direct1_cfg_pad_i320, fabric_direct1_cfg_pad_i321 +, fabric_direct1_cfg_pad_i322, fabric_direct1_cfg_pad_i323, fabric_direct1_cfg_pad_i324, fabric_direct1_cfg_pad_i325, fabric_direct1_cfg_pad_i326, fabric_direct1_cfg_pad_i327, fabric_direct1_cfg_pad_i328, fabric_direct1_cfg_pad_i329, fabric_direct1_cfg_pad_i330, fabric_direct1_cfg_pad_i331, fabric_direct1_cfg_pad_i332, fabric_direct1_cfg_pad_i333, fabric_direct1_cfg_pad_i334, fabric_direct1_cfg_pad_i335, fabric_direct1_cfg_pad_i336, fabric_direct1_cfg_pad_i337, fabric_direct1_cfg_pad_i338, fabric_direct1_cfg_pad_i339, fabric_direct1_cfg_pad_i340, fabric_direct1_cfg_pad_i341, fabric_direct1_cfg_pad_i342 +, fabric_direct1_cfg_pad_i343, fabric_direct1_cfg_pad_i344, fabric_direct1_cfg_pad_i345, fabric_direct1_cfg_pad_i346, fabric_direct1_cfg_pad_i347, fabric_direct1_cfg_pad_i348, fabric_direct1_cfg_pad_i349, fabric_direct1_cfg_pad_i350, fabric_direct1_cfg_pad_i351, fabric_direct1_cfg_pad_i352, fabric_direct1_cfg_pad_i353, fabric_direct1_cfg_pad_i354, fabric_direct1_cfg_pad_i355, fabric_direct1_cfg_pad_i356, fabric_direct1_cfg_pad_i357, fabric_direct1_cfg_pad_i358, fabric_direct1_cfg_pad_i359, fabric_direct1_cfg_pad_i360, fabric_direct1_cfg_pad_i361, fabric_direct1_cfg_pad_i362, fabric_direct1_cfg_pad_i363 +, fabric_direct1_cfg_pad_i364, fabric_direct1_cfg_pad_i365, fabric_direct1_cfg_pad_i366, fabric_direct1_cfg_pad_i367, fabric_direct1_cfg_pad_i368, fabric_direct1_cfg_pad_i369, fabric_direct1_cfg_pad_i370, fabric_direct1_cfg_pad_i371, fabric_direct1_cfg_pad_i372, fabric_direct1_cfg_pad_i373, fabric_direct1_cfg_pad_i374, fabric_direct1_cfg_pad_i375, fabric_direct1_cfg_pad_i376, fabric_direct1_cfg_pad_i377, fabric_direct1_cfg_pad_i378, fabric_direct1_cfg_pad_i379, fabric_direct1_cfg_pad_i380, fabric_direct1_cfg_pad_i381, fabric_direct1_cfg_pad_i382, fabric_direct1_cfg_pad_i383, fabric_direct1_cfg_pad_i384 +, fabric_direct1_cfg_pad_i385, fabric_direct1_cfg_pad_i386, fabric_direct1_cfg_pad_i387, fabric_direct1_cfg_pad_i388, fabric_direct1_cfg_pad_i389, fabric_direct1_cfg_pad_i390, fabric_direct1_cfg_pad_i391, fabric_direct1_cfg_pad_i392, fabric_direct1_cfg_pad_i393, fabric_direct1_cfg_pad_i394, fabric_direct1_cfg_pad_i395, fabric_direct1_cfg_pad_i396, fabric_direct1_cfg_pad_i397, fabric_direct1_cfg_pad_i398, fabric_direct1_cfg_pad_i399, fabric_direct1_cfg_pad_i400, fabric_direct1_cfg_pad_i401, fabric_direct1_cfg_pad_i402, fabric_direct1_cfg_pad_i403, fabric_direct1_cfg_pad_i404, fabric_direct1_cfg_pad_i405 +, fabric_direct1_cfg_pad_i406, fabric_direct1_cfg_pad_i407, fabric_direct1_cfg_pad_i408, fabric_direct1_cfg_pad_i409, fabric_direct1_cfg_pad_i410, fabric_direct1_cfg_pad_i411, fabric_direct1_cfg_pad_i412, fabric_direct1_cfg_pad_i413, fabric_direct1_cfg_pad_i414, fabric_direct1_cfg_pad_i415, fabric_direct1_cfg_pad_i416, fabric_direct1_cfg_pad_i417, fabric_direct1_cfg_pad_i418, fabric_direct1_cfg_pad_i419, fabric_direct1_cfg_pad_i420, fabric_direct1_cfg_pad_i421, fabric_direct1_cfg_pad_i422, fabric_direct1_cfg_pad_i423, fabric_direct1_cfg_pad_i424, fabric_direct1_cfg_pad_i425, fabric_direct1_cfg_pad_i426 +, fabric_direct1_cfg_pad_i427, fabric_direct1_cfg_pad_i428, fabric_direct1_cfg_pad_i429, fabric_direct1_cfg_pad_i430, fabric_direct1_cfg_pad_i431, fabric_direct1_cfg_pad_i432, fabric_direct1_cfg_pad_i433, fabric_direct1_cfg_pad_i434, fabric_direct1_cfg_pad_i435, fabric_direct1_cfg_pad_i436, fabric_direct1_cfg_pad_i437, fabric_direct1_cfg_pad_i438, fabric_direct1_cfg_pad_i439, fabric_direct1_cfg_pad_i440, fabric_direct1_cfg_pad_i441, fabric_direct1_cfg_pad_i442, fabric_direct1_cfg_pad_i443, fabric_direct1_cfg_pad_i444, fabric_direct1_cfg_pad_i445, fabric_direct1_cfg_pad_i446, fabric_direct1_cfg_pad_i447 +, fabric_direct1_cfg_pad_i448, fabric_direct1_cfg_pad_i449, fabric_direct1_cfg_pad_i450, fabric_direct1_cfg_pad_i451, fabric_direct1_cfg_pad_i452, fabric_direct1_cfg_pad_i453, fabric_direct1_cfg_pad_i454, fabric_direct1_cfg_pad_i455, fabric_direct1_cfg_pad_i456, fabric_direct1_cfg_pad_i457, fabric_direct1_cfg_pad_i458, fabric_direct1_cfg_pad_i459, fabric_direct1_cfg_pad_i460, fabric_direct1_cfg_pad_i461, fabric_direct1_cfg_pad_i462, fabric_direct1_cfg_pad_i463, fabric_direct1_cfg_pad_i464, fabric_direct1_cfg_pad_i465, fabric_direct1_cfg_pad_i466, fabric_direct1_cfg_pad_i467, fabric_direct1_cfg_pad_i468 +, fabric_direct1_cfg_pad_i469, fabric_direct1_cfg_pad_i470, fabric_direct1_cfg_pad_i471, fabric_direct1_cfg_pad_i472, fabric_direct1_cfg_pad_i473, fabric_direct1_cfg_pad_i474, fabric_direct1_cfg_pad_i475, fabric_direct1_cfg_pad_i476, fabric_direct1_cfg_pad_i477, fabric_direct1_cfg_pad_i478, fabric_direct1_cfg_pad_i479, fabric_direct1_cfg_pad_i480, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1 +, fabric_thsens_fm_mode_w_i2, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22 +, fabric_thsens_fm_mode_w_i23, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10 +, fabric_thsens_fm_config_w_i11, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3 +, fabric_thsens_fm_data_o4, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8 +, fabric_thsens_fm_mode_r_o9, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29 +, fabric_thsens_fm_mode_r_o30, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18 +, fabric_thsens_fm_config_r_o19, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_tst_scanenable_i, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o +, fabric_thsens_tst_scanout2_o, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20 +, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2 +, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2 +, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2 +, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11 +, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17 +, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38 +, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11 +, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32 +, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2 +, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2 +, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5 +, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2 +, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23 +, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11 +, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i +, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9 +, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11 +, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1 +, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22 +, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5 +, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1 +, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16 +, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6 +, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27 +, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o); + input fabric_adc0_arst_b_tmr_i1; + input fabric_adc0_arst_b_tmr_i2; + input fabric_adc0_arst_b_tmr_i3; + output fabric_adc0_cal_done_o; + output fabric_adc0_cal_n_overflow_o; + output fabric_adc0_cal_n_underflow_o; + output fabric_adc0_cal_p_overflow_o; + output fabric_adc0_cal_p_underflow_o; + input fabric_adc0_cal_start_i; + input fabric_adc0_clk_i; + input fabric_adc0_dbg_addr_i1; + input fabric_adc0_dbg_addr_i2; + input fabric_adc0_dbg_addr_i3; + input fabric_adc0_dbg_addr_i4; + output fabric_adc0_dbg_data_o1; + output fabric_adc0_dbg_data_o10; + output fabric_adc0_dbg_data_o11; + output fabric_adc0_dbg_data_o12; + output fabric_adc0_dbg_data_o13; + output fabric_adc0_dbg_data_o14; + output fabric_adc0_dbg_data_o15; + output fabric_adc0_dbg_data_o16; + output fabric_adc0_dbg_data_o17; + output fabric_adc0_dbg_data_o18; + output fabric_adc0_dbg_data_o19; + output fabric_adc0_dbg_data_o2; + output fabric_adc0_dbg_data_o20; + output fabric_adc0_dbg_data_o21; + output fabric_adc0_dbg_data_o22; + output fabric_adc0_dbg_data_o23; + output fabric_adc0_dbg_data_o24; + output fabric_adc0_dbg_data_o25; + output fabric_adc0_dbg_data_o26; + output fabric_adc0_dbg_data_o27; + output fabric_adc0_dbg_data_o28; + output fabric_adc0_dbg_data_o29; + output fabric_adc0_dbg_data_o3; + output fabric_adc0_dbg_data_o30; + output fabric_adc0_dbg_data_o31; + output fabric_adc0_dbg_data_o32; + output fabric_adc0_dbg_data_o4; + output fabric_adc0_dbg_data_o5; + output fabric_adc0_dbg_data_o6; + output fabric_adc0_dbg_data_o7; + output fabric_adc0_dbg_data_o8; + output fabric_adc0_dbg_data_o9; + input fabric_adc0_dft_scan_en_i; + input fabric_adc0_dft_si_i1; + input fabric_adc0_dft_si_i10; + input fabric_adc0_dft_si_i11; + input fabric_adc0_dft_si_i12; + input fabric_adc0_dft_si_i2; + input fabric_adc0_dft_si_i3; + input fabric_adc0_dft_si_i4; + input fabric_adc0_dft_si_i5; + input fabric_adc0_dft_si_i6; + input fabric_adc0_dft_si_i7; + input fabric_adc0_dft_si_i8; + input fabric_adc0_dft_si_i9; + input fabric_adc0_dft_test_mode_i1; + input fabric_adc0_dft_test_mode_i2; + input fabric_adc0_pwr_down_b_tmr_i1; + input fabric_adc0_pwr_down_b_tmr_i2; + input fabric_adc0_pwr_down_b_tmr_i3; + input fabric_adc0_spare_i1; + input fabric_adc0_spare_i10; + input fabric_adc0_spare_i11; + input fabric_adc0_spare_i12; + input fabric_adc0_spare_i13; + input fabric_adc0_spare_i14; + input fabric_adc0_spare_i15; + input fabric_adc0_spare_i16; + input fabric_adc0_spare_i2; + input fabric_adc0_spare_i3; + input fabric_adc0_spare_i4; + input fabric_adc0_spare_i5; + input fabric_adc0_spare_i6; + input fabric_adc0_spare_i7; + input fabric_adc0_spare_i8; + input fabric_adc0_spare_i9; + input fabric_adc0_usr_arst_b_tmr_i1; + input fabric_adc0_usr_arst_b_tmr_i2; + input fabric_adc0_usr_arst_b_tmr_i3; + input fabric_adc0_usr_channel_i1; + input fabric_adc0_usr_channel_i2; + input fabric_adc0_usr_channel_i3; + input fabric_adc0_usr_cke_i; + output fabric_adc0_usr_conv_done_o; + input fabric_adc0_usr_conv_start_i; + input fabric_adc0_usr_sample_lsb_i1; + input fabric_adc0_usr_sample_lsb_i2; + input fabric_adc0_usr_sample_lsb_i3; + input fabric_adc0_usr_sample_lsb_i4; + output fabric_adc0_usr_sample_o1; + output fabric_adc0_usr_sample_o10; + output fabric_adc0_usr_sample_o11; + output fabric_adc0_usr_sample_o12; + output fabric_adc0_usr_sample_o2; + output fabric_adc0_usr_sample_o3; + output fabric_adc0_usr_sample_o4; + output fabric_adc0_usr_sample_o5; + output fabric_adc0_usr_sample_o6; + output fabric_adc0_usr_sample_o7; + output fabric_adc0_usr_sample_o8; + output fabric_adc0_usr_sample_o9; + input fabric_adc1_arst_b_tmr_i1; + input fabric_adc1_arst_b_tmr_i2; + input fabric_adc1_arst_b_tmr_i3; + output fabric_adc1_cal_done_o; + output fabric_adc1_cal_n_overflow_o; + output fabric_adc1_cal_n_underflow_o; + output fabric_adc1_cal_p_overflow_o; + output fabric_adc1_cal_p_underflow_o; + input fabric_adc1_cal_start_i; + input fabric_adc1_clk_i; + input fabric_adc1_dbg_addr_i1; + input fabric_adc1_dbg_addr_i2; + input fabric_adc1_dbg_addr_i3; + input fabric_adc1_dbg_addr_i4; + output fabric_adc1_dbg_data_o1; + output fabric_adc1_dbg_data_o10; + output fabric_adc1_dbg_data_o11; + output fabric_adc1_dbg_data_o12; + output fabric_adc1_dbg_data_o13; + output fabric_adc1_dbg_data_o14; + output fabric_adc1_dbg_data_o15; + output fabric_adc1_dbg_data_o16; + output fabric_adc1_dbg_data_o17; + output fabric_adc1_dbg_data_o18; + output fabric_adc1_dbg_data_o19; + output fabric_adc1_dbg_data_o2; + output fabric_adc1_dbg_data_o20; + output fabric_adc1_dbg_data_o21; + output fabric_adc1_dbg_data_o22; + output fabric_adc1_dbg_data_o23; + output fabric_adc1_dbg_data_o24; + output fabric_adc1_dbg_data_o25; + output fabric_adc1_dbg_data_o26; + output fabric_adc1_dbg_data_o27; + output fabric_adc1_dbg_data_o28; + output fabric_adc1_dbg_data_o29; + output fabric_adc1_dbg_data_o3; + output fabric_adc1_dbg_data_o30; + output fabric_adc1_dbg_data_o31; + output fabric_adc1_dbg_data_o32; + output fabric_adc1_dbg_data_o4; + output fabric_adc1_dbg_data_o5; + output fabric_adc1_dbg_data_o6; + output fabric_adc1_dbg_data_o7; + output fabric_adc1_dbg_data_o8; + output fabric_adc1_dbg_data_o9; + input fabric_adc1_dft_scan_en_i; + input fabric_adc1_dft_si_i1; + input fabric_adc1_dft_si_i10; + input fabric_adc1_dft_si_i11; + input fabric_adc1_dft_si_i12; + input fabric_adc1_dft_si_i2; + input fabric_adc1_dft_si_i3; + input fabric_adc1_dft_si_i4; + input fabric_adc1_dft_si_i5; + input fabric_adc1_dft_si_i6; + input fabric_adc1_dft_si_i7; + input fabric_adc1_dft_si_i8; + input fabric_adc1_dft_si_i9; + input fabric_adc1_dft_test_mode_i1; + input fabric_adc1_dft_test_mode_i2; + input fabric_adc1_pwr_down_b_tmr_i1; + input fabric_adc1_pwr_down_b_tmr_i2; + input fabric_adc1_pwr_down_b_tmr_i3; + input fabric_adc1_spare_i1; + input fabric_adc1_spare_i10; + input fabric_adc1_spare_i11; + input fabric_adc1_spare_i12; + input fabric_adc1_spare_i13; + input fabric_adc1_spare_i14; + input fabric_adc1_spare_i15; + input fabric_adc1_spare_i16; + input fabric_adc1_spare_i2; + input fabric_adc1_spare_i3; + input fabric_adc1_spare_i4; + input fabric_adc1_spare_i5; + input fabric_adc1_spare_i6; + input fabric_adc1_spare_i7; + input fabric_adc1_spare_i8; + input fabric_adc1_spare_i9; + input fabric_adc1_usr_arst_b_tmr_i1; + input fabric_adc1_usr_arst_b_tmr_i2; + input fabric_adc1_usr_arst_b_tmr_i3; + input fabric_adc1_usr_channel_i1; + input fabric_adc1_usr_channel_i2; + input fabric_adc1_usr_channel_i3; + input fabric_adc1_usr_cke_i; + output fabric_adc1_usr_conv_done_o; + input fabric_adc1_usr_conv_start_i; + input fabric_adc1_usr_sample_lsb_i1; + input fabric_adc1_usr_sample_lsb_i2; + input fabric_adc1_usr_sample_lsb_i3; + input fabric_adc1_usr_sample_lsb_i4; + output fabric_adc1_usr_sample_o1; + output fabric_adc1_usr_sample_o10; + output fabric_adc1_usr_sample_o11; + output fabric_adc1_usr_sample_o12; + output fabric_adc1_usr_sample_o2; + output fabric_adc1_usr_sample_o3; + output fabric_adc1_usr_sample_o4; + output fabric_adc1_usr_sample_o5; + output fabric_adc1_usr_sample_o6; + output fabric_adc1_usr_sample_o7; + output fabric_adc1_usr_sample_o8; + output fabric_adc1_usr_sample_o9; + input fabric_adc2_arst_b_tmr_i1; + input fabric_adc2_arst_b_tmr_i2; + input fabric_adc2_arst_b_tmr_i3; + output fabric_adc2_cal_done_o; + output fabric_adc2_cal_n_overflow_o; + output fabric_adc2_cal_n_underflow_o; + output fabric_adc2_cal_p_overflow_o; + output fabric_adc2_cal_p_underflow_o; + input fabric_adc2_cal_start_i; + input fabric_adc2_clk_i; + input fabric_adc2_dbg_addr_i1; + input fabric_adc2_dbg_addr_i2; + input fabric_adc2_dbg_addr_i3; + input fabric_adc2_dbg_addr_i4; + output fabric_adc2_dbg_data_o1; + output fabric_adc2_dbg_data_o10; + output fabric_adc2_dbg_data_o11; + output fabric_adc2_dbg_data_o12; + output fabric_adc2_dbg_data_o13; + output fabric_adc2_dbg_data_o14; + output fabric_adc2_dbg_data_o15; + output fabric_adc2_dbg_data_o16; + output fabric_adc2_dbg_data_o17; + output fabric_adc2_dbg_data_o18; + output fabric_adc2_dbg_data_o19; + output fabric_adc2_dbg_data_o2; + output fabric_adc2_dbg_data_o20; + output fabric_adc2_dbg_data_o21; + output fabric_adc2_dbg_data_o22; + output fabric_adc2_dbg_data_o23; + output fabric_adc2_dbg_data_o24; + output fabric_adc2_dbg_data_o25; + output fabric_adc2_dbg_data_o26; + output fabric_adc2_dbg_data_o27; + output fabric_adc2_dbg_data_o28; + output fabric_adc2_dbg_data_o29; + output fabric_adc2_dbg_data_o3; + output fabric_adc2_dbg_data_o30; + output fabric_adc2_dbg_data_o31; + output fabric_adc2_dbg_data_o32; + output fabric_adc2_dbg_data_o4; + output fabric_adc2_dbg_data_o5; + output fabric_adc2_dbg_data_o6; + output fabric_adc2_dbg_data_o7; + output fabric_adc2_dbg_data_o8; + output fabric_adc2_dbg_data_o9; + input fabric_adc2_dft_scan_en_i; + input fabric_adc2_dft_si_i1; + input fabric_adc2_dft_si_i10; + input fabric_adc2_dft_si_i11; + input fabric_adc2_dft_si_i12; + input fabric_adc2_dft_si_i2; + input fabric_adc2_dft_si_i3; + input fabric_adc2_dft_si_i4; + input fabric_adc2_dft_si_i5; + input fabric_adc2_dft_si_i6; + input fabric_adc2_dft_si_i7; + input fabric_adc2_dft_si_i8; + input fabric_adc2_dft_si_i9; + input fabric_adc2_dft_test_mode_i1; + input fabric_adc2_dft_test_mode_i2; + input fabric_adc2_pwr_down_b_tmr_i1; + input fabric_adc2_pwr_down_b_tmr_i2; + input fabric_adc2_pwr_down_b_tmr_i3; + input fabric_adc2_spare_i1; + input fabric_adc2_spare_i10; + input fabric_adc2_spare_i11; + input fabric_adc2_spare_i12; + input fabric_adc2_spare_i13; + input fabric_adc2_spare_i14; + input fabric_adc2_spare_i15; + input fabric_adc2_spare_i16; + input fabric_adc2_spare_i2; + input fabric_adc2_spare_i3; + input fabric_adc2_spare_i4; + input fabric_adc2_spare_i5; + input fabric_adc2_spare_i6; + input fabric_adc2_spare_i7; + input fabric_adc2_spare_i8; + input fabric_adc2_spare_i9; + input fabric_adc2_usr_arst_b_tmr_i1; + input fabric_adc2_usr_arst_b_tmr_i2; + input fabric_adc2_usr_arst_b_tmr_i3; + input fabric_adc2_usr_channel_i1; + input fabric_adc2_usr_channel_i2; + input fabric_adc2_usr_channel_i3; + input fabric_adc2_usr_cke_i; + output fabric_adc2_usr_conv_done_o; + input fabric_adc2_usr_conv_start_i; + input fabric_adc2_usr_sample_lsb_i1; + input fabric_adc2_usr_sample_lsb_i2; + input fabric_adc2_usr_sample_lsb_i3; + input fabric_adc2_usr_sample_lsb_i4; + output fabric_adc2_usr_sample_o1; + output fabric_adc2_usr_sample_o10; + output fabric_adc2_usr_sample_o11; + output fabric_adc2_usr_sample_o12; + output fabric_adc2_usr_sample_o2; + output fabric_adc2_usr_sample_o3; + output fabric_adc2_usr_sample_o4; + output fabric_adc2_usr_sample_o5; + output fabric_adc2_usr_sample_o6; + output fabric_adc2_usr_sample_o7; + output fabric_adc2_usr_sample_o8; + output fabric_adc2_usr_sample_o9; + input fabric_adc3_arst_b_tmr_i1; + input fabric_adc3_arst_b_tmr_i2; + input fabric_adc3_arst_b_tmr_i3; + output fabric_adc3_cal_done_o; + output fabric_adc3_cal_n_overflow_o; + output fabric_adc3_cal_n_underflow_o; + output fabric_adc3_cal_p_overflow_o; + output fabric_adc3_cal_p_underflow_o; + input fabric_adc3_cal_start_i; + input fabric_adc3_clk_i; + input fabric_adc3_dbg_addr_i1; + input fabric_adc3_dbg_addr_i2; + input fabric_adc3_dbg_addr_i3; + input fabric_adc3_dbg_addr_i4; + output fabric_adc3_dbg_data_o1; + output fabric_adc3_dbg_data_o10; + output fabric_adc3_dbg_data_o11; + output fabric_adc3_dbg_data_o12; + output fabric_adc3_dbg_data_o13; + output fabric_adc3_dbg_data_o14; + output fabric_adc3_dbg_data_o15; + output fabric_adc3_dbg_data_o16; + output fabric_adc3_dbg_data_o17; + output fabric_adc3_dbg_data_o18; + output fabric_adc3_dbg_data_o19; + output fabric_adc3_dbg_data_o2; + output fabric_adc3_dbg_data_o20; + output fabric_adc3_dbg_data_o21; + output fabric_adc3_dbg_data_o22; + output fabric_adc3_dbg_data_o23; + output fabric_adc3_dbg_data_o24; + output fabric_adc3_dbg_data_o25; + output fabric_adc3_dbg_data_o26; + output fabric_adc3_dbg_data_o27; + output fabric_adc3_dbg_data_o28; + output fabric_adc3_dbg_data_o29; + output fabric_adc3_dbg_data_o3; + output fabric_adc3_dbg_data_o30; + output fabric_adc3_dbg_data_o31; + output fabric_adc3_dbg_data_o32; + output fabric_adc3_dbg_data_o4; + output fabric_adc3_dbg_data_o5; + output fabric_adc3_dbg_data_o6; + output fabric_adc3_dbg_data_o7; + output fabric_adc3_dbg_data_o8; + output fabric_adc3_dbg_data_o9; + input fabric_adc3_dft_scan_en_i; + input fabric_adc3_dft_si_i1; + input fabric_adc3_dft_si_i10; + input fabric_adc3_dft_si_i11; + input fabric_adc3_dft_si_i12; + input fabric_adc3_dft_si_i2; + input fabric_adc3_dft_si_i3; + input fabric_adc3_dft_si_i4; + input fabric_adc3_dft_si_i5; + input fabric_adc3_dft_si_i6; + input fabric_adc3_dft_si_i7; + input fabric_adc3_dft_si_i8; + input fabric_adc3_dft_si_i9; + input fabric_adc3_dft_test_mode_i1; + input fabric_adc3_dft_test_mode_i2; + input fabric_adc3_pwr_down_b_tmr_i1; + input fabric_adc3_pwr_down_b_tmr_i2; + input fabric_adc3_pwr_down_b_tmr_i3; + input fabric_adc3_spare_i1; + input fabric_adc3_spare_i10; + input fabric_adc3_spare_i11; + input fabric_adc3_spare_i12; + input fabric_adc3_spare_i13; + input fabric_adc3_spare_i14; + input fabric_adc3_spare_i15; + input fabric_adc3_spare_i16; + input fabric_adc3_spare_i2; + input fabric_adc3_spare_i3; + input fabric_adc3_spare_i4; + input fabric_adc3_spare_i5; + input fabric_adc3_spare_i6; + input fabric_adc3_spare_i7; + input fabric_adc3_spare_i8; + input fabric_adc3_spare_i9; + input fabric_adc3_usr_arst_b_tmr_i1; + input fabric_adc3_usr_arst_b_tmr_i2; + input fabric_adc3_usr_arst_b_tmr_i3; + input fabric_adc3_usr_channel_i1; + input fabric_adc3_usr_channel_i2; + input fabric_adc3_usr_channel_i3; + input fabric_adc3_usr_cke_i; + output fabric_adc3_usr_conv_done_o; + input fabric_adc3_usr_conv_start_i; + input fabric_adc3_usr_sample_lsb_i1; + input fabric_adc3_usr_sample_lsb_i2; + input fabric_adc3_usr_sample_lsb_i3; + input fabric_adc3_usr_sample_lsb_i4; + output fabric_adc3_usr_sample_o1; + output fabric_adc3_usr_sample_o10; + output fabric_adc3_usr_sample_o11; + output fabric_adc3_usr_sample_o12; + output fabric_adc3_usr_sample_o2; + output fabric_adc3_usr_sample_o3; + output fabric_adc3_usr_sample_o4; + output fabric_adc3_usr_sample_o5; + output fabric_adc3_usr_sample_o6; + output fabric_adc3_usr_sample_o7; + output fabric_adc3_usr_sample_o8; + output fabric_adc3_usr_sample_o9; + input fabric_cfg_adc0_clk_cal_div_ratio_i1; + input fabric_cfg_adc0_clk_cal_div_ratio_i2; + input fabric_cfg_adc0_clk_cal_div_ratio_i3; + input fabric_cfg_adc0_clk_cal_div_ratio_i4; + input fabric_cfg_adc0_clk_cal_div_ratio_i5; + input fabric_cfg_adc0_conv_done_delayed_i; + input fabric_cfg_adc0_use_cdc_i; + input fabric_cfg_adc1_clk_cal_div_ratio_i1; + input fabric_cfg_adc1_clk_cal_div_ratio_i2; + input fabric_cfg_adc1_clk_cal_div_ratio_i3; + input fabric_cfg_adc1_clk_cal_div_ratio_i4; + input fabric_cfg_adc1_clk_cal_div_ratio_i5; + input fabric_cfg_adc1_conv_done_delayed_i; + input fabric_cfg_adc1_use_cdc_i; + input fabric_cfg_adc2_clk_cal_div_ratio_i1; + input fabric_cfg_adc2_clk_cal_div_ratio_i2; + input fabric_cfg_adc2_clk_cal_div_ratio_i3; + input fabric_cfg_adc2_clk_cal_div_ratio_i4; + input fabric_cfg_adc2_clk_cal_div_ratio_i5; + input fabric_cfg_adc2_conv_done_delayed_i; + input fabric_cfg_adc2_use_cdc_i; + input fabric_cfg_adc3_clk_cal_div_ratio_i1; + input fabric_cfg_adc3_clk_cal_div_ratio_i2; + input fabric_cfg_adc3_clk_cal_div_ratio_i3; + input fabric_cfg_adc3_clk_cal_div_ratio_i4; + input fabric_cfg_adc3_clk_cal_div_ratio_i5; + input fabric_cfg_adc3_conv_done_delayed_i; + input fabric_cfg_adc3_use_cdc_i; + input fabric_cfg_dac0_reg_cm_select_i; + input fabric_cfg_dac0_reg_res_i1; + input fabric_cfg_dac0_reg_res_i2; + input fabric_cfg_dac0_reg_vref_select_i; + input fabric_cfg_dac0_sync_i; + input fabric_cfg_dac1_reg_cm_select_i; + input fabric_cfg_dac1_reg_res_i1; + input fabric_cfg_dac1_reg_res_i2; + input fabric_cfg_dac1_reg_vref_select_i; + input fabric_cfg_dac1_sync_i; + input fabric_cfg_dac2_reg_cm_select_i; + input fabric_cfg_dac2_reg_res_i1; + input fabric_cfg_dac2_reg_res_i2; + input fabric_cfg_dac2_reg_vref_select_i; + input fabric_cfg_dac2_sync_i; + input fabric_cfg_dac3_reg_cm_select_i; + input fabric_cfg_dac3_reg_res_i1; + input fabric_cfg_dac3_reg_res_i2; + input fabric_cfg_dac3_reg_vref_select_i; + input fabric_cfg_dac3_sync_i; + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_clk_bsm_o; + output fabric_clk_otp_mrepair_o; + input fabric_clk_otp_mux_i; + output fabric_clk_otp_o; + output fabric_clk_user0_o; + output fabric_clk_user1_o; + input fabric_dac0_clk_en_i; + input fabric_dac0_clk_i; + input fabric_dac0_comp_en_i; + input fabric_dac0_comp_hyst_en_i; + input fabric_dac0_comp_in_sel_i1; + input fabric_dac0_comp_in_sel_i2; + input fabric_dac0_comp_in_sel_i3; + input fabric_dac0_comp_in_sel_i4; + output fabric_dac0_comp_out_o; + input fabric_dac0_comp_ref_sel_i; + input fabric_dac0_din_i1; + input fabric_dac0_din_i10; + input fabric_dac0_din_i11; + input fabric_dac0_din_i12; + input fabric_dac0_din_i13; + input fabric_dac0_din_i2; + input fabric_dac0_din_i3; + input fabric_dac0_din_i4; + input fabric_dac0_din_i5; + input fabric_dac0_din_i6; + input fabric_dac0_din_i7; + input fabric_dac0_din_i8; + input fabric_dac0_din_i9; + input fabric_dac0_filt_en_i; + input fabric_dac0_op_en_i; + input fabric_dac0_reg_pwr_down_n_i; + input fabric_dac0_rstn_i; + input fabric_dac1_clk_en_i; + input fabric_dac1_clk_i; + input fabric_dac1_comp_en_i; + input fabric_dac1_comp_hyst_en_i; + input fabric_dac1_comp_in_sel_i1; + input fabric_dac1_comp_in_sel_i2; + input fabric_dac1_comp_in_sel_i3; + input fabric_dac1_comp_in_sel_i4; + output fabric_dac1_comp_out_o; + input fabric_dac1_comp_ref_sel_i; + input fabric_dac1_din_i1; + input fabric_dac1_din_i10; + input fabric_dac1_din_i11; + input fabric_dac1_din_i12; + input fabric_dac1_din_i13; + input fabric_dac1_din_i2; + input fabric_dac1_din_i3; + input fabric_dac1_din_i4; + input fabric_dac1_din_i5; + input fabric_dac1_din_i6; + input fabric_dac1_din_i7; + input fabric_dac1_din_i8; + input fabric_dac1_din_i9; + input fabric_dac1_filt_en_i; + input fabric_dac1_op_en_i; + input fabric_dac1_reg_pwr_down_n_i; + input fabric_dac1_rstn_i; + input fabric_dac2_clk_en_i; + input fabric_dac2_clk_i; + input fabric_dac2_comp_en_i; + input fabric_dac2_comp_hyst_en_i; + input fabric_dac2_comp_in_sel_i1; + input fabric_dac2_comp_in_sel_i10; + input fabric_dac2_comp_in_sel_i11; + input fabric_dac2_comp_in_sel_i12; + input fabric_dac2_comp_in_sel_i13; + input fabric_dac2_comp_in_sel_i2; + input fabric_dac2_comp_in_sel_i3; + input fabric_dac2_comp_in_sel_i4; + input fabric_dac2_comp_in_sel_i5; + input fabric_dac2_comp_in_sel_i6; + input fabric_dac2_comp_in_sel_i7; + input fabric_dac2_comp_in_sel_i8; + input fabric_dac2_comp_in_sel_i9; + output fabric_dac2_comp_out_o; + input fabric_dac2_comp_ref_sel_i; + input fabric_dac2_din_i1; + input fabric_dac2_din_i10; + input fabric_dac2_din_i11; + input fabric_dac2_din_i12; + input fabric_dac2_din_i13; + input fabric_dac2_din_i2; + input fabric_dac2_din_i3; + input fabric_dac2_din_i4; + input fabric_dac2_din_i5; + input fabric_dac2_din_i6; + input fabric_dac2_din_i7; + input fabric_dac2_din_i8; + input fabric_dac2_din_i9; + input fabric_dac2_filt_en_i; + input fabric_dac2_op_en_i; + input fabric_dac2_reg_pwr_down_n_i; + input fabric_dac2_rstn_i; + input fabric_dac3_clk_en_i; + input fabric_dac3_clk_i; + input fabric_dac3_comp_en_i; + input fabric_dac3_comp_hyst_en_i; + input fabric_dac3_comp_in_sel_i1; + input fabric_dac3_comp_in_sel_i2; + input fabric_dac3_comp_in_sel_i3; + input fabric_dac3_comp_in_sel_i4; + output fabric_dac3_comp_out_o; + input fabric_dac3_comp_ref_sel_i; + input fabric_dac3_din_i1; + input fabric_dac3_din_i10; + input fabric_dac3_din_i11; + input fabric_dac3_din_i12; + input fabric_dac3_din_i13; + input fabric_dac3_din_i2; + input fabric_dac3_din_i3; + input fabric_dac3_din_i4; + input fabric_dac3_din_i5; + input fabric_dac3_din_i6; + input fabric_dac3_din_i7; + input fabric_dac3_din_i8; + input fabric_dac3_din_i9; + input fabric_dac3_filt_en_i; + input fabric_dac3_op_en_i; + input fabric_dac3_reg_pwr_down_n_i; + input fabric_dac3_rstn_i; + output fabric_debug_access_reg_data_ready_o; + output fabric_debug_bsec_core_status_o1; + output fabric_debug_bsec_core_status_o10; + output fabric_debug_bsec_core_status_o11; + output fabric_debug_bsec_core_status_o12; + output fabric_debug_bsec_core_status_o13; + output fabric_debug_bsec_core_status_o14; + output fabric_debug_bsec_core_status_o15; + output fabric_debug_bsec_core_status_o16; + output fabric_debug_bsec_core_status_o17; + output fabric_debug_bsec_core_status_o18; + output fabric_debug_bsec_core_status_o19; + output fabric_debug_bsec_core_status_o2; + output fabric_debug_bsec_core_status_o20; + output fabric_debug_bsec_core_status_o21; + output fabric_debug_bsec_core_status_o22; + output fabric_debug_bsec_core_status_o23; + output fabric_debug_bsec_core_status_o24; + output fabric_debug_bsec_core_status_o25; + output fabric_debug_bsec_core_status_o26; + output fabric_debug_bsec_core_status_o27; + output fabric_debug_bsec_core_status_o28; + output fabric_debug_bsec_core_status_o29; + output fabric_debug_bsec_core_status_o3; + output fabric_debug_bsec_core_status_o30; + output fabric_debug_bsec_core_status_o31; + output fabric_debug_bsec_core_status_o32; + output fabric_debug_bsec_core_status_o4; + output fabric_debug_bsec_core_status_o5; + output fabric_debug_bsec_core_status_o6; + output fabric_debug_bsec_core_status_o7; + output fabric_debug_bsec_core_status_o8; + output fabric_debug_bsec_core_status_o9; + output fabric_debug_cpt_retry_o1; + output fabric_debug_cpt_retry_o2; + output fabric_debug_cpt_retry_o3; + output fabric_debug_cpt_retry_o4; + output fabric_debug_direct_permission_read_o1; + output fabric_debug_direct_permission_read_o2; + output fabric_debug_direct_permission_read_o3; + output fabric_debug_direct_permission_read_o4; + output fabric_debug_direct_permission_write_o1; + output fabric_debug_direct_permission_write_o2; + output fabric_debug_direct_permission_write_o3; + output fabric_debug_direct_permission_write_o4; + output fabric_debug_error_o; + output fabric_debug_frame_permission_frame_o1; + output fabric_debug_frame_permission_frame_o2; + output fabric_debug_frame_permission_frame_o3; + output fabric_debug_frame_permission_frame_o4; + output fabric_debug_frame_use_encryption_o; + output fabric_debug_fsm_state_o1; + output fabric_debug_fsm_state_o2; + output fabric_debug_fsm_state_o3; + output fabric_debug_key_correct_o; + output fabric_debug_lifecycle_o1; + output fabric_debug_lifecycle_o2; + output fabric_debug_lifecycle_o3; + output fabric_debug_lifecycle_o4; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output fabric_debug_otpapb_state_o1; + output fabric_debug_otpapb_state_o2; + output fabric_debug_otpapb_state_o3; + output fabric_debug_otpboot_curr_addr_o1; + output fabric_debug_otpboot_curr_addr_o2; + output fabric_debug_otpboot_curr_addr_o3; + output fabric_debug_otpboot_curr_addr_o4; + output fabric_debug_otpboot_curr_addr_o5; + output fabric_debug_otpboot_curr_addr_o6; + output fabric_debug_otpboot_curr_addr_o7; + output fabric_debug_otpboot_curr_addr_o8; + output fabric_debug_otpboot_state_o1; + output fabric_debug_otpboot_state_o2; + output fabric_debug_otpboot_state_o3; + output fabric_debug_otpmgmt_state_o1; + output fabric_debug_otpmgmt_state_o2; + output fabric_debug_otpmgmt_state_o3; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + input fabric_direct0_cfg_bank_i1; + input fabric_direct0_cfg_bank_i2; + input fabric_direct0_cfg_bank_i3; + input fabric_direct0_cfg_bank_i4; + input fabric_direct0_cfg_pad_i1; + input fabric_direct0_cfg_pad_i10; + input fabric_direct0_cfg_pad_i100; + input fabric_direct0_cfg_pad_i101; + input fabric_direct0_cfg_pad_i102; + input fabric_direct0_cfg_pad_i103; + input fabric_direct0_cfg_pad_i104; + input fabric_direct0_cfg_pad_i105; + input fabric_direct0_cfg_pad_i106; + input fabric_direct0_cfg_pad_i107; + input fabric_direct0_cfg_pad_i108; + input fabric_direct0_cfg_pad_i109; + input fabric_direct0_cfg_pad_i11; + input fabric_direct0_cfg_pad_i110; + input fabric_direct0_cfg_pad_i111; + input fabric_direct0_cfg_pad_i112; + input fabric_direct0_cfg_pad_i113; + input fabric_direct0_cfg_pad_i114; + input fabric_direct0_cfg_pad_i115; + input fabric_direct0_cfg_pad_i116; + input fabric_direct0_cfg_pad_i117; + input fabric_direct0_cfg_pad_i118; + input fabric_direct0_cfg_pad_i119; + input fabric_direct0_cfg_pad_i12; + input fabric_direct0_cfg_pad_i120; + input fabric_direct0_cfg_pad_i121; + input fabric_direct0_cfg_pad_i122; + input fabric_direct0_cfg_pad_i123; + input fabric_direct0_cfg_pad_i124; + input fabric_direct0_cfg_pad_i125; + input fabric_direct0_cfg_pad_i126; + input fabric_direct0_cfg_pad_i127; + input fabric_direct0_cfg_pad_i128; + input fabric_direct0_cfg_pad_i129; + input fabric_direct0_cfg_pad_i13; + input fabric_direct0_cfg_pad_i130; + input fabric_direct0_cfg_pad_i131; + input fabric_direct0_cfg_pad_i132; + input fabric_direct0_cfg_pad_i133; + input fabric_direct0_cfg_pad_i134; + input fabric_direct0_cfg_pad_i135; + input fabric_direct0_cfg_pad_i136; + input fabric_direct0_cfg_pad_i137; + input fabric_direct0_cfg_pad_i138; + input fabric_direct0_cfg_pad_i139; + input fabric_direct0_cfg_pad_i14; + input fabric_direct0_cfg_pad_i140; + input fabric_direct0_cfg_pad_i141; + input fabric_direct0_cfg_pad_i142; + input fabric_direct0_cfg_pad_i143; + input fabric_direct0_cfg_pad_i144; + input fabric_direct0_cfg_pad_i145; + input fabric_direct0_cfg_pad_i146; + input fabric_direct0_cfg_pad_i147; + input fabric_direct0_cfg_pad_i148; + input fabric_direct0_cfg_pad_i149; + input fabric_direct0_cfg_pad_i15; + input fabric_direct0_cfg_pad_i150; + input fabric_direct0_cfg_pad_i151; + input fabric_direct0_cfg_pad_i152; + input fabric_direct0_cfg_pad_i153; + input fabric_direct0_cfg_pad_i154; + input fabric_direct0_cfg_pad_i155; + input fabric_direct0_cfg_pad_i156; + input fabric_direct0_cfg_pad_i157; + input fabric_direct0_cfg_pad_i158; + input fabric_direct0_cfg_pad_i159; + input fabric_direct0_cfg_pad_i16; + input fabric_direct0_cfg_pad_i160; + input fabric_direct0_cfg_pad_i161; + input fabric_direct0_cfg_pad_i162; + input fabric_direct0_cfg_pad_i163; + input fabric_direct0_cfg_pad_i164; + input fabric_direct0_cfg_pad_i165; + input fabric_direct0_cfg_pad_i166; + input fabric_direct0_cfg_pad_i167; + input fabric_direct0_cfg_pad_i168; + input fabric_direct0_cfg_pad_i169; + input fabric_direct0_cfg_pad_i17; + input fabric_direct0_cfg_pad_i170; + input fabric_direct0_cfg_pad_i171; + input fabric_direct0_cfg_pad_i172; + input fabric_direct0_cfg_pad_i173; + input fabric_direct0_cfg_pad_i174; + input fabric_direct0_cfg_pad_i175; + input fabric_direct0_cfg_pad_i176; + input fabric_direct0_cfg_pad_i177; + input fabric_direct0_cfg_pad_i178; + input fabric_direct0_cfg_pad_i179; + input fabric_direct0_cfg_pad_i18; + input fabric_direct0_cfg_pad_i180; + input fabric_direct0_cfg_pad_i181; + input fabric_direct0_cfg_pad_i182; + input fabric_direct0_cfg_pad_i183; + input fabric_direct0_cfg_pad_i184; + input fabric_direct0_cfg_pad_i185; + input fabric_direct0_cfg_pad_i186; + input fabric_direct0_cfg_pad_i187; + input fabric_direct0_cfg_pad_i188; + input fabric_direct0_cfg_pad_i189; + input fabric_direct0_cfg_pad_i19; + input fabric_direct0_cfg_pad_i190; + input fabric_direct0_cfg_pad_i191; + input fabric_direct0_cfg_pad_i192; + input fabric_direct0_cfg_pad_i193; + input fabric_direct0_cfg_pad_i194; + input fabric_direct0_cfg_pad_i195; + input fabric_direct0_cfg_pad_i196; + input fabric_direct0_cfg_pad_i197; + input fabric_direct0_cfg_pad_i198; + input fabric_direct0_cfg_pad_i199; + input fabric_direct0_cfg_pad_i2; + input fabric_direct0_cfg_pad_i20; + input fabric_direct0_cfg_pad_i200; + input fabric_direct0_cfg_pad_i201; + input fabric_direct0_cfg_pad_i202; + input fabric_direct0_cfg_pad_i203; + input fabric_direct0_cfg_pad_i204; + input fabric_direct0_cfg_pad_i205; + input fabric_direct0_cfg_pad_i206; + input fabric_direct0_cfg_pad_i207; + input fabric_direct0_cfg_pad_i208; + input fabric_direct0_cfg_pad_i209; + input fabric_direct0_cfg_pad_i21; + input fabric_direct0_cfg_pad_i210; + input fabric_direct0_cfg_pad_i211; + input fabric_direct0_cfg_pad_i212; + input fabric_direct0_cfg_pad_i213; + input fabric_direct0_cfg_pad_i214; + input fabric_direct0_cfg_pad_i215; + input fabric_direct0_cfg_pad_i216; + input fabric_direct0_cfg_pad_i217; + input fabric_direct0_cfg_pad_i218; + input fabric_direct0_cfg_pad_i219; + input fabric_direct0_cfg_pad_i22; + input fabric_direct0_cfg_pad_i220; + input fabric_direct0_cfg_pad_i221; + input fabric_direct0_cfg_pad_i222; + input fabric_direct0_cfg_pad_i223; + input fabric_direct0_cfg_pad_i224; + input fabric_direct0_cfg_pad_i225; + input fabric_direct0_cfg_pad_i226; + input fabric_direct0_cfg_pad_i227; + input fabric_direct0_cfg_pad_i228; + input fabric_direct0_cfg_pad_i229; + input fabric_direct0_cfg_pad_i23; + input fabric_direct0_cfg_pad_i230; + input fabric_direct0_cfg_pad_i231; + input fabric_direct0_cfg_pad_i232; + input fabric_direct0_cfg_pad_i233; + input fabric_direct0_cfg_pad_i234; + input fabric_direct0_cfg_pad_i235; + input fabric_direct0_cfg_pad_i236; + input fabric_direct0_cfg_pad_i237; + input fabric_direct0_cfg_pad_i238; + input fabric_direct0_cfg_pad_i239; + input fabric_direct0_cfg_pad_i24; + input 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fabric_direct0_cfg_pad_i654; + input fabric_direct0_cfg_pad_i655; + input fabric_direct0_cfg_pad_i656; + input fabric_direct0_cfg_pad_i657; + input fabric_direct0_cfg_pad_i658; + input fabric_direct0_cfg_pad_i659; + input fabric_direct0_cfg_pad_i66; + input fabric_direct0_cfg_pad_i660; + input fabric_direct0_cfg_pad_i661; + input fabric_direct0_cfg_pad_i662; + input fabric_direct0_cfg_pad_i663; + input fabric_direct0_cfg_pad_i664; + input fabric_direct0_cfg_pad_i665; + input fabric_direct0_cfg_pad_i666; + input fabric_direct0_cfg_pad_i667; + input fabric_direct0_cfg_pad_i668; + input fabric_direct0_cfg_pad_i669; + input fabric_direct0_cfg_pad_i67; + input fabric_direct0_cfg_pad_i670; + input fabric_direct0_cfg_pad_i671; + input fabric_direct0_cfg_pad_i672; + input fabric_direct0_cfg_pad_i673; + input fabric_direct0_cfg_pad_i674; + input fabric_direct0_cfg_pad_i675; + input fabric_direct0_cfg_pad_i676; + input fabric_direct0_cfg_pad_i677; + input fabric_direct0_cfg_pad_i678; + input fabric_direct0_cfg_pad_i679; + input fabric_direct0_cfg_pad_i68; + input fabric_direct0_cfg_pad_i680; + input fabric_direct0_cfg_pad_i681; + input fabric_direct0_cfg_pad_i682; + input fabric_direct0_cfg_pad_i683; + input fabric_direct0_cfg_pad_i684; + input fabric_direct0_cfg_pad_i685; + input fabric_direct0_cfg_pad_i686; + input fabric_direct0_cfg_pad_i687; + input fabric_direct0_cfg_pad_i688; + input fabric_direct0_cfg_pad_i689; + input fabric_direct0_cfg_pad_i69; + input fabric_direct0_cfg_pad_i690; + input fabric_direct0_cfg_pad_i691; + input fabric_direct0_cfg_pad_i692; + input fabric_direct0_cfg_pad_i693; + input fabric_direct0_cfg_pad_i694; + input fabric_direct0_cfg_pad_i695; + input fabric_direct0_cfg_pad_i696; + input fabric_direct0_cfg_pad_i697; + input fabric_direct0_cfg_pad_i698; + input fabric_direct0_cfg_pad_i699; + input fabric_direct0_cfg_pad_i7; + input fabric_direct0_cfg_pad_i70; + input fabric_direct0_cfg_pad_i700; + input fabric_direct0_cfg_pad_i701; + input fabric_direct0_cfg_pad_i702; + input fabric_direct0_cfg_pad_i703; + input fabric_direct0_cfg_pad_i704; + input fabric_direct0_cfg_pad_i705; + input fabric_direct0_cfg_pad_i706; + input fabric_direct0_cfg_pad_i707; + input fabric_direct0_cfg_pad_i708; + input fabric_direct0_cfg_pad_i709; + input fabric_direct0_cfg_pad_i71; + input fabric_direct0_cfg_pad_i710; + input fabric_direct0_cfg_pad_i711; + input fabric_direct0_cfg_pad_i712; + input fabric_direct0_cfg_pad_i713; + input fabric_direct0_cfg_pad_i714; + input fabric_direct0_cfg_pad_i715; + input fabric_direct0_cfg_pad_i716; + input fabric_direct0_cfg_pad_i717; + input fabric_direct0_cfg_pad_i718; + input fabric_direct0_cfg_pad_i719; + input fabric_direct0_cfg_pad_i72; + input fabric_direct0_cfg_pad_i720; + input fabric_direct0_cfg_pad_i73; + input fabric_direct0_cfg_pad_i74; + input fabric_direct0_cfg_pad_i75; + input fabric_direct0_cfg_pad_i76; + input fabric_direct0_cfg_pad_i77; + input fabric_direct0_cfg_pad_i78; + input fabric_direct0_cfg_pad_i79; + input fabric_direct0_cfg_pad_i8; + input fabric_direct0_cfg_pad_i80; + input fabric_direct0_cfg_pad_i81; + input fabric_direct0_cfg_pad_i82; + input fabric_direct0_cfg_pad_i83; + input fabric_direct0_cfg_pad_i84; + input fabric_direct0_cfg_pad_i85; + input fabric_direct0_cfg_pad_i86; + input fabric_direct0_cfg_pad_i87; + input fabric_direct0_cfg_pad_i88; + input fabric_direct0_cfg_pad_i89; + input fabric_direct0_cfg_pad_i9; + input fabric_direct0_cfg_pad_i90; + input fabric_direct0_cfg_pad_i91; + input fabric_direct0_cfg_pad_i92; + input fabric_direct0_cfg_pad_i93; + input fabric_direct0_cfg_pad_i94; + input fabric_direct0_cfg_pad_i95; + input fabric_direct0_cfg_pad_i96; + input fabric_direct0_cfg_pad_i97; + input fabric_direct0_cfg_pad_i98; + input fabric_direct0_cfg_pad_i99; + input fabric_direct0_clock_fabric_i1; + input fabric_direct0_clock_fabric_i2; + input fabric_direct0_clock_fabric_i3; + input fabric_direct0_clock_fabric_i4; + input fabric_direct0_di_ena_i1; + input fabric_direct0_di_ena_i10; + input fabric_direct0_di_ena_i11; + input fabric_direct0_di_ena_i12; + input fabric_direct0_di_ena_i13; + input fabric_direct0_di_ena_i14; + input fabric_direct0_di_ena_i15; + input fabric_direct0_di_ena_i16; + input fabric_direct0_di_ena_i17; + input fabric_direct0_di_ena_i18; + input fabric_direct0_di_ena_i19; + input fabric_direct0_di_ena_i2; + input fabric_direct0_di_ena_i20; + input fabric_direct0_di_ena_i21; + input fabric_direct0_di_ena_i22; + input fabric_direct0_di_ena_i23; + input fabric_direct0_di_ena_i24; + input fabric_direct0_di_ena_i3; + input fabric_direct0_di_ena_i4; + input fabric_direct0_di_ena_i5; + input fabric_direct0_di_ena_i6; + input fabric_direct0_di_ena_i7; + input fabric_direct0_di_ena_i8; + input fabric_direct0_di_ena_i9; + output fabric_direct0_di_o1; + output fabric_direct0_di_o10; + output fabric_direct0_di_o11; + output fabric_direct0_di_o12; + output fabric_direct0_di_o13; + output fabric_direct0_di_o14; + output fabric_direct0_di_o15; + output fabric_direct0_di_o16; + output fabric_direct0_di_o17; + output fabric_direct0_di_o18; + output fabric_direct0_di_o19; + output fabric_direct0_di_o2; + output fabric_direct0_di_o20; + output fabric_direct0_di_o21; + output fabric_direct0_di_o22; + output fabric_direct0_di_o23; + output fabric_direct0_di_o24; + output fabric_direct0_di_o3; + output fabric_direct0_di_o4; + output fabric_direct0_di_o5; + output fabric_direct0_di_o6; + output fabric_direct0_di_o7; + output fabric_direct0_di_o8; + output fabric_direct0_di_o9; + input fabric_direct0_di_rs_i1; + input fabric_direct0_di_rs_i10; + input fabric_direct0_di_rs_i11; + input fabric_direct0_di_rs_i12; + input fabric_direct0_di_rs_i13; + input fabric_direct0_di_rs_i14; + input fabric_direct0_di_rs_i15; + input fabric_direct0_di_rs_i16; + input fabric_direct0_di_rs_i17; + input fabric_direct0_di_rs_i18; + input fabric_direct0_di_rs_i19; + input fabric_direct0_di_rs_i2; + input fabric_direct0_di_rs_i20; + input fabric_direct0_di_rs_i21; + input fabric_direct0_di_rs_i22; + input fabric_direct0_di_rs_i23; + input fabric_direct0_di_rs_i24; + input fabric_direct0_di_rs_i3; + input fabric_direct0_di_rs_i4; + input fabric_direct0_di_rs_i5; + input fabric_direct0_di_rs_i6; + input fabric_direct0_di_rs_i7; + input fabric_direct0_di_rs_i8; + input fabric_direct0_di_rs_i9; + input fabric_direct0_do_ena_i1; + input fabric_direct0_do_ena_i10; + input fabric_direct0_do_ena_i11; + input fabric_direct0_do_ena_i12; + input fabric_direct0_do_ena_i13; + input fabric_direct0_do_ena_i14; + input fabric_direct0_do_ena_i15; + input fabric_direct0_do_ena_i16; + input fabric_direct0_do_ena_i17; + input fabric_direct0_do_ena_i18; + input fabric_direct0_do_ena_i19; + input fabric_direct0_do_ena_i2; + input fabric_direct0_do_ena_i20; + input fabric_direct0_do_ena_i21; + input fabric_direct0_do_ena_i22; + input fabric_direct0_do_ena_i23; + input fabric_direct0_do_ena_i24; + input fabric_direct0_do_ena_i3; + input fabric_direct0_do_ena_i4; + input fabric_direct0_do_ena_i5; + input fabric_direct0_do_ena_i6; + input fabric_direct0_do_ena_i7; + input fabric_direct0_do_ena_i8; + input fabric_direct0_do_ena_i9; + input fabric_direct0_do_i1; + input fabric_direct0_do_i10; + input fabric_direct0_do_i11; + input fabric_direct0_do_i12; + input fabric_direct0_do_i13; + input fabric_direct0_do_i14; + input fabric_direct0_do_i15; + input fabric_direct0_do_i16; + input fabric_direct0_do_i17; + input fabric_direct0_do_i18; + input fabric_direct0_do_i19; + input fabric_direct0_do_i2; + input fabric_direct0_do_i20; + input fabric_direct0_do_i21; + input fabric_direct0_do_i22; + input fabric_direct0_do_i23; + input fabric_direct0_do_i24; + input fabric_direct0_do_i3; + input fabric_direct0_do_i4; + input fabric_direct0_do_i5; + input fabric_direct0_do_i6; + input fabric_direct0_do_i7; + input fabric_direct0_do_i8; + input fabric_direct0_do_i9; + input fabric_direct0_do_rs_i1; + input fabric_direct0_do_rs_i10; + input fabric_direct0_do_rs_i11; + input fabric_direct0_do_rs_i12; + input fabric_direct0_do_rs_i13; + input fabric_direct0_do_rs_i14; + input fabric_direct0_do_rs_i15; + input fabric_direct0_do_rs_i16; + input fabric_direct0_do_rs_i17; + input fabric_direct0_do_rs_i18; + input fabric_direct0_do_rs_i19; + input fabric_direct0_do_rs_i2; + input fabric_direct0_do_rs_i20; + input fabric_direct0_do_rs_i21; + input fabric_direct0_do_rs_i22; + input fabric_direct0_do_rs_i23; + input fabric_direct0_do_rs_i24; + input fabric_direct0_do_rs_i3; + input fabric_direct0_do_rs_i4; + input fabric_direct0_do_rs_i5; + input fabric_direct0_do_rs_i6; + input fabric_direct0_do_rs_i7; + input fabric_direct0_do_rs_i8; + input fabric_direct0_do_rs_i9; + input fabric_direct0_loopback_en_i; + input fabric_direct0_loopback_mux_i; + input fabric_direct0_oe_ena_i1; + input fabric_direct0_oe_ena_i10; + input fabric_direct0_oe_ena_i11; + input fabric_direct0_oe_ena_i12; + input fabric_direct0_oe_ena_i13; + input fabric_direct0_oe_ena_i14; + input fabric_direct0_oe_ena_i15; + input fabric_direct0_oe_ena_i16; + input fabric_direct0_oe_ena_i17; + input fabric_direct0_oe_ena_i18; + input fabric_direct0_oe_ena_i19; + input fabric_direct0_oe_ena_i2; + input fabric_direct0_oe_ena_i20; + input fabric_direct0_oe_ena_i21; + input fabric_direct0_oe_ena_i22; + input fabric_direct0_oe_ena_i23; + input fabric_direct0_oe_ena_i24; + input fabric_direct0_oe_ena_i3; + input fabric_direct0_oe_ena_i4; + input fabric_direct0_oe_ena_i5; + input fabric_direct0_oe_ena_i6; + input fabric_direct0_oe_ena_i7; + input fabric_direct0_oe_ena_i8; + input fabric_direct0_oe_ena_i9; + input fabric_direct0_oe_i1; + input fabric_direct0_oe_i10; + input fabric_direct0_oe_i11; + input fabric_direct0_oe_i12; + input fabric_direct0_oe_i13; + input fabric_direct0_oe_i14; + input fabric_direct0_oe_i15; + input fabric_direct0_oe_i16; + input fabric_direct0_oe_i17; + input fabric_direct0_oe_i18; + input fabric_direct0_oe_i19; + input fabric_direct0_oe_i2; + input fabric_direct0_oe_i20; + input fabric_direct0_oe_i21; + input fabric_direct0_oe_i22; + input fabric_direct0_oe_i23; + input fabric_direct0_oe_i24; + input fabric_direct0_oe_i3; + input fabric_direct0_oe_i4; + input fabric_direct0_oe_i5; + input fabric_direct0_oe_i6; + input fabric_direct0_oe_i7; + input fabric_direct0_oe_i8; + input fabric_direct0_oe_i9; + input fabric_direct0_oe_rs_i1; + input fabric_direct0_oe_rs_i10; + input fabric_direct0_oe_rs_i11; + input fabric_direct0_oe_rs_i12; + input fabric_direct0_oe_rs_i13; + input fabric_direct0_oe_rs_i14; + input fabric_direct0_oe_rs_i15; + input fabric_direct0_oe_rs_i16; + input fabric_direct0_oe_rs_i17; + input fabric_direct0_oe_rs_i18; + input fabric_direct0_oe_rs_i19; + input fabric_direct0_oe_rs_i2; + input fabric_direct0_oe_rs_i20; + input fabric_direct0_oe_rs_i21; + input fabric_direct0_oe_rs_i22; + input fabric_direct0_oe_rs_i23; + input fabric_direct0_oe_rs_i24; + input fabric_direct0_oe_rs_i3; + input fabric_direct0_oe_rs_i4; + input fabric_direct0_oe_rs_i5; + input fabric_direct0_oe_rs_i6; + input fabric_direct0_oe_rs_i7; + input fabric_direct0_oe_rs_i8; + input fabric_direct0_oe_rs_i9; + input fabric_direct0_scan_en_i; + input fabric_direct1_cfg_bank_i1; + input fabric_direct1_cfg_bank_i2; + input fabric_direct1_cfg_bank_i3; + input fabric_direct1_cfg_bank_i4; + input fabric_direct1_cfg_pad_i1; + input fabric_direct1_cfg_pad_i10; + input fabric_direct1_cfg_pad_i100; + input fabric_direct1_cfg_pad_i101; + input fabric_direct1_cfg_pad_i102; + input fabric_direct1_cfg_pad_i103; + input fabric_direct1_cfg_pad_i104; + input fabric_direct1_cfg_pad_i105; + input fabric_direct1_cfg_pad_i106; + input fabric_direct1_cfg_pad_i107; + input fabric_direct1_cfg_pad_i108; + input fabric_direct1_cfg_pad_i109; + input fabric_direct1_cfg_pad_i11; + input fabric_direct1_cfg_pad_i110; + input fabric_direct1_cfg_pad_i111; + input fabric_direct1_cfg_pad_i112; + input fabric_direct1_cfg_pad_i113; + input fabric_direct1_cfg_pad_i114; + input fabric_direct1_cfg_pad_i115; + input fabric_direct1_cfg_pad_i116; + input fabric_direct1_cfg_pad_i117; + input fabric_direct1_cfg_pad_i118; + input fabric_direct1_cfg_pad_i119; + input fabric_direct1_cfg_pad_i12; + input fabric_direct1_cfg_pad_i120; + input fabric_direct1_cfg_pad_i121; + input fabric_direct1_cfg_pad_i122; + input fabric_direct1_cfg_pad_i123; + input fabric_direct1_cfg_pad_i124; + input fabric_direct1_cfg_pad_i125; + input fabric_direct1_cfg_pad_i126; + input fabric_direct1_cfg_pad_i127; + input fabric_direct1_cfg_pad_i128; + input fabric_direct1_cfg_pad_i129; + input fabric_direct1_cfg_pad_i13; + input fabric_direct1_cfg_pad_i130; + input fabric_direct1_cfg_pad_i131; + input fabric_direct1_cfg_pad_i132; + input fabric_direct1_cfg_pad_i133; + input fabric_direct1_cfg_pad_i134; + input fabric_direct1_cfg_pad_i135; + input fabric_direct1_cfg_pad_i136; + input fabric_direct1_cfg_pad_i137; + input fabric_direct1_cfg_pad_i138; + input fabric_direct1_cfg_pad_i139; + input fabric_direct1_cfg_pad_i14; + input fabric_direct1_cfg_pad_i140; + input fabric_direct1_cfg_pad_i141; + input fabric_direct1_cfg_pad_i142; + input fabric_direct1_cfg_pad_i143; + input fabric_direct1_cfg_pad_i144; + input fabric_direct1_cfg_pad_i145; + input fabric_direct1_cfg_pad_i146; + input fabric_direct1_cfg_pad_i147; + input fabric_direct1_cfg_pad_i148; + input fabric_direct1_cfg_pad_i149; + input fabric_direct1_cfg_pad_i15; + input fabric_direct1_cfg_pad_i150; + input fabric_direct1_cfg_pad_i151; + input fabric_direct1_cfg_pad_i152; + input fabric_direct1_cfg_pad_i153; + input fabric_direct1_cfg_pad_i154; + input fabric_direct1_cfg_pad_i155; + input fabric_direct1_cfg_pad_i156; + input fabric_direct1_cfg_pad_i157; + input fabric_direct1_cfg_pad_i158; + input fabric_direct1_cfg_pad_i159; + input fabric_direct1_cfg_pad_i16; + input fabric_direct1_cfg_pad_i160; + input fabric_direct1_cfg_pad_i161; + input fabric_direct1_cfg_pad_i162; + input fabric_direct1_cfg_pad_i163; + input fabric_direct1_cfg_pad_i164; + input fabric_direct1_cfg_pad_i165; + input fabric_direct1_cfg_pad_i166; + input fabric_direct1_cfg_pad_i167; + input fabric_direct1_cfg_pad_i168; + input fabric_direct1_cfg_pad_i169; + input fabric_direct1_cfg_pad_i17; + input fabric_direct1_cfg_pad_i170; + input fabric_direct1_cfg_pad_i171; + input fabric_direct1_cfg_pad_i172; + input fabric_direct1_cfg_pad_i173; + input fabric_direct1_cfg_pad_i174; + input fabric_direct1_cfg_pad_i175; + input fabric_direct1_cfg_pad_i176; + input fabric_direct1_cfg_pad_i177; + input fabric_direct1_cfg_pad_i178; + input fabric_direct1_cfg_pad_i179; + input fabric_direct1_cfg_pad_i18; + input fabric_direct1_cfg_pad_i180; + input fabric_direct1_cfg_pad_i181; + input fabric_direct1_cfg_pad_i182; + input fabric_direct1_cfg_pad_i183; + input fabric_direct1_cfg_pad_i184; + input fabric_direct1_cfg_pad_i185; + input fabric_direct1_cfg_pad_i186; + input fabric_direct1_cfg_pad_i187; + input fabric_direct1_cfg_pad_i188; + input fabric_direct1_cfg_pad_i189; + input fabric_direct1_cfg_pad_i19; + input fabric_direct1_cfg_pad_i190; + input fabric_direct1_cfg_pad_i191; + input fabric_direct1_cfg_pad_i192; + input fabric_direct1_cfg_pad_i193; + input fabric_direct1_cfg_pad_i194; + input fabric_direct1_cfg_pad_i195; + input fabric_direct1_cfg_pad_i196; + input fabric_direct1_cfg_pad_i197; + input fabric_direct1_cfg_pad_i198; + input fabric_direct1_cfg_pad_i199; + input fabric_direct1_cfg_pad_i2; + input fabric_direct1_cfg_pad_i20; + input fabric_direct1_cfg_pad_i200; + input fabric_direct1_cfg_pad_i201; + input fabric_direct1_cfg_pad_i202; + input fabric_direct1_cfg_pad_i203; + input fabric_direct1_cfg_pad_i204; + input fabric_direct1_cfg_pad_i205; + input fabric_direct1_cfg_pad_i206; + input fabric_direct1_cfg_pad_i207; + input fabric_direct1_cfg_pad_i208; + input fabric_direct1_cfg_pad_i209; + input fabric_direct1_cfg_pad_i21; + input fabric_direct1_cfg_pad_i210; + input fabric_direct1_cfg_pad_i211; + input fabric_direct1_cfg_pad_i212; + input fabric_direct1_cfg_pad_i213; + input fabric_direct1_cfg_pad_i214; + input fabric_direct1_cfg_pad_i215; + input fabric_direct1_cfg_pad_i216; + input fabric_direct1_cfg_pad_i217; + input fabric_direct1_cfg_pad_i218; + input fabric_direct1_cfg_pad_i219; + input fabric_direct1_cfg_pad_i22; + input fabric_direct1_cfg_pad_i220; + input fabric_direct1_cfg_pad_i221; + input fabric_direct1_cfg_pad_i222; + input fabric_direct1_cfg_pad_i223; + input fabric_direct1_cfg_pad_i224; + input fabric_direct1_cfg_pad_i225; + input fabric_direct1_cfg_pad_i226; + input fabric_direct1_cfg_pad_i227; + input fabric_direct1_cfg_pad_i228; + input fabric_direct1_cfg_pad_i229; + input fabric_direct1_cfg_pad_i23; + input fabric_direct1_cfg_pad_i230; + input fabric_direct1_cfg_pad_i231; + input fabric_direct1_cfg_pad_i232; + input fabric_direct1_cfg_pad_i233; + input fabric_direct1_cfg_pad_i234; + input fabric_direct1_cfg_pad_i235; + input fabric_direct1_cfg_pad_i236; + input fabric_direct1_cfg_pad_i237; + input fabric_direct1_cfg_pad_i238; + input fabric_direct1_cfg_pad_i239; + input fabric_direct1_cfg_pad_i24; + input fabric_direct1_cfg_pad_i240; + input fabric_direct1_cfg_pad_i241; + input fabric_direct1_cfg_pad_i242; + input fabric_direct1_cfg_pad_i243; + input fabric_direct1_cfg_pad_i244; + input fabric_direct1_cfg_pad_i245; + input fabric_direct1_cfg_pad_i246; + input fabric_direct1_cfg_pad_i247; + input fabric_direct1_cfg_pad_i248; + input fabric_direct1_cfg_pad_i249; + input fabric_direct1_cfg_pad_i25; + input fabric_direct1_cfg_pad_i250; + input fabric_direct1_cfg_pad_i251; + input fabric_direct1_cfg_pad_i252; + input fabric_direct1_cfg_pad_i253; + input fabric_direct1_cfg_pad_i254; + input fabric_direct1_cfg_pad_i255; + input fabric_direct1_cfg_pad_i256; + input fabric_direct1_cfg_pad_i257; + input fabric_direct1_cfg_pad_i258; + input fabric_direct1_cfg_pad_i259; + input fabric_direct1_cfg_pad_i26; + input fabric_direct1_cfg_pad_i260; + input fabric_direct1_cfg_pad_i261; + input fabric_direct1_cfg_pad_i262; + input fabric_direct1_cfg_pad_i263; + input fabric_direct1_cfg_pad_i264; + input fabric_direct1_cfg_pad_i265; + input fabric_direct1_cfg_pad_i266; + input fabric_direct1_cfg_pad_i267; + input fabric_direct1_cfg_pad_i268; + input fabric_direct1_cfg_pad_i269; + input fabric_direct1_cfg_pad_i27; + input fabric_direct1_cfg_pad_i270; + input fabric_direct1_cfg_pad_i271; + input fabric_direct1_cfg_pad_i272; + input fabric_direct1_cfg_pad_i273; + input fabric_direct1_cfg_pad_i274; + input fabric_direct1_cfg_pad_i275; + input fabric_direct1_cfg_pad_i276; + input fabric_direct1_cfg_pad_i277; + input fabric_direct1_cfg_pad_i278; + input fabric_direct1_cfg_pad_i279; + input fabric_direct1_cfg_pad_i28; + input fabric_direct1_cfg_pad_i280; + input fabric_direct1_cfg_pad_i281; + input fabric_direct1_cfg_pad_i282; + input fabric_direct1_cfg_pad_i283; + input fabric_direct1_cfg_pad_i284; + input fabric_direct1_cfg_pad_i285; + input fabric_direct1_cfg_pad_i286; + input fabric_direct1_cfg_pad_i287; + input fabric_direct1_cfg_pad_i288; + input fabric_direct1_cfg_pad_i289; + input fabric_direct1_cfg_pad_i29; + input fabric_direct1_cfg_pad_i290; + input fabric_direct1_cfg_pad_i291; + input fabric_direct1_cfg_pad_i292; + input fabric_direct1_cfg_pad_i293; + input fabric_direct1_cfg_pad_i294; + input fabric_direct1_cfg_pad_i295; + input fabric_direct1_cfg_pad_i296; + input fabric_direct1_cfg_pad_i297; + input fabric_direct1_cfg_pad_i298; + input fabric_direct1_cfg_pad_i299; + input fabric_direct1_cfg_pad_i3; + input fabric_direct1_cfg_pad_i30; + input fabric_direct1_cfg_pad_i300; + input fabric_direct1_cfg_pad_i301; + input fabric_direct1_cfg_pad_i302; + input fabric_direct1_cfg_pad_i303; + input fabric_direct1_cfg_pad_i304; + input fabric_direct1_cfg_pad_i305; + input fabric_direct1_cfg_pad_i306; + input fabric_direct1_cfg_pad_i307; + input fabric_direct1_cfg_pad_i308; + input fabric_direct1_cfg_pad_i309; + input fabric_direct1_cfg_pad_i31; + input fabric_direct1_cfg_pad_i310; + input fabric_direct1_cfg_pad_i311; + input fabric_direct1_cfg_pad_i312; + input fabric_direct1_cfg_pad_i313; + input fabric_direct1_cfg_pad_i314; + input fabric_direct1_cfg_pad_i315; + input fabric_direct1_cfg_pad_i316; + input fabric_direct1_cfg_pad_i317; + input fabric_direct1_cfg_pad_i318; + input fabric_direct1_cfg_pad_i319; + input fabric_direct1_cfg_pad_i32; + input fabric_direct1_cfg_pad_i320; + input fabric_direct1_cfg_pad_i321; + input fabric_direct1_cfg_pad_i322; + input fabric_direct1_cfg_pad_i323; + input fabric_direct1_cfg_pad_i324; + input fabric_direct1_cfg_pad_i325; + input fabric_direct1_cfg_pad_i326; + input fabric_direct1_cfg_pad_i327; + input fabric_direct1_cfg_pad_i328; + input fabric_direct1_cfg_pad_i329; + input fabric_direct1_cfg_pad_i33; + input fabric_direct1_cfg_pad_i330; + input fabric_direct1_cfg_pad_i331; + input fabric_direct1_cfg_pad_i332; + input fabric_direct1_cfg_pad_i333; + input fabric_direct1_cfg_pad_i334; + input fabric_direct1_cfg_pad_i335; + input fabric_direct1_cfg_pad_i336; + input fabric_direct1_cfg_pad_i337; + input fabric_direct1_cfg_pad_i338; + input fabric_direct1_cfg_pad_i339; + input fabric_direct1_cfg_pad_i34; + input fabric_direct1_cfg_pad_i340; + input fabric_direct1_cfg_pad_i341; + input fabric_direct1_cfg_pad_i342; + input fabric_direct1_cfg_pad_i343; + input fabric_direct1_cfg_pad_i344; + input fabric_direct1_cfg_pad_i345; + input fabric_direct1_cfg_pad_i346; + input fabric_direct1_cfg_pad_i347; + input fabric_direct1_cfg_pad_i348; + input fabric_direct1_cfg_pad_i349; + input fabric_direct1_cfg_pad_i35; + input fabric_direct1_cfg_pad_i350; + input fabric_direct1_cfg_pad_i351; + input fabric_direct1_cfg_pad_i352; + input fabric_direct1_cfg_pad_i353; + input fabric_direct1_cfg_pad_i354; + input fabric_direct1_cfg_pad_i355; + input fabric_direct1_cfg_pad_i356; + input fabric_direct1_cfg_pad_i357; + input fabric_direct1_cfg_pad_i358; + input fabric_direct1_cfg_pad_i359; + input fabric_direct1_cfg_pad_i36; + input fabric_direct1_cfg_pad_i360; + input fabric_direct1_cfg_pad_i361; + input fabric_direct1_cfg_pad_i362; + input fabric_direct1_cfg_pad_i363; + input fabric_direct1_cfg_pad_i364; + input fabric_direct1_cfg_pad_i365; + input fabric_direct1_cfg_pad_i366; + input fabric_direct1_cfg_pad_i367; + input fabric_direct1_cfg_pad_i368; + input fabric_direct1_cfg_pad_i369; + input fabric_direct1_cfg_pad_i37; + input fabric_direct1_cfg_pad_i370; + input fabric_direct1_cfg_pad_i371; + input fabric_direct1_cfg_pad_i372; + input fabric_direct1_cfg_pad_i373; + input fabric_direct1_cfg_pad_i374; + input fabric_direct1_cfg_pad_i375; + input fabric_direct1_cfg_pad_i376; + input fabric_direct1_cfg_pad_i377; + input fabric_direct1_cfg_pad_i378; + input fabric_direct1_cfg_pad_i379; + input fabric_direct1_cfg_pad_i38; + input fabric_direct1_cfg_pad_i380; + input fabric_direct1_cfg_pad_i381; + input fabric_direct1_cfg_pad_i382; + input fabric_direct1_cfg_pad_i383; + input fabric_direct1_cfg_pad_i384; + input fabric_direct1_cfg_pad_i385; + input fabric_direct1_cfg_pad_i386; + input fabric_direct1_cfg_pad_i387; + input fabric_direct1_cfg_pad_i388; + input fabric_direct1_cfg_pad_i389; + input fabric_direct1_cfg_pad_i39; + input fabric_direct1_cfg_pad_i390; + input fabric_direct1_cfg_pad_i391; + input fabric_direct1_cfg_pad_i392; + input fabric_direct1_cfg_pad_i393; + input fabric_direct1_cfg_pad_i394; + input fabric_direct1_cfg_pad_i395; + input fabric_direct1_cfg_pad_i396; + input fabric_direct1_cfg_pad_i397; + input fabric_direct1_cfg_pad_i398; + input fabric_direct1_cfg_pad_i399; + input fabric_direct1_cfg_pad_i4; + input fabric_direct1_cfg_pad_i40; + input fabric_direct1_cfg_pad_i400; + input fabric_direct1_cfg_pad_i401; + input fabric_direct1_cfg_pad_i402; + input fabric_direct1_cfg_pad_i403; + input fabric_direct1_cfg_pad_i404; + input fabric_direct1_cfg_pad_i405; + input fabric_direct1_cfg_pad_i406; + input fabric_direct1_cfg_pad_i407; + input fabric_direct1_cfg_pad_i408; + input fabric_direct1_cfg_pad_i409; + input fabric_direct1_cfg_pad_i41; + input fabric_direct1_cfg_pad_i410; + input fabric_direct1_cfg_pad_i411; + input fabric_direct1_cfg_pad_i412; + input fabric_direct1_cfg_pad_i413; + input fabric_direct1_cfg_pad_i414; + input fabric_direct1_cfg_pad_i415; + input fabric_direct1_cfg_pad_i416; + input fabric_direct1_cfg_pad_i417; + input fabric_direct1_cfg_pad_i418; + input fabric_direct1_cfg_pad_i419; + input fabric_direct1_cfg_pad_i42; + input fabric_direct1_cfg_pad_i420; + input fabric_direct1_cfg_pad_i421; + input fabric_direct1_cfg_pad_i422; + input fabric_direct1_cfg_pad_i423; + input fabric_direct1_cfg_pad_i424; + input fabric_direct1_cfg_pad_i425; + input fabric_direct1_cfg_pad_i426; + input fabric_direct1_cfg_pad_i427; + input fabric_direct1_cfg_pad_i428; + input fabric_direct1_cfg_pad_i429; + input fabric_direct1_cfg_pad_i43; + input fabric_direct1_cfg_pad_i430; + input fabric_direct1_cfg_pad_i431; + input fabric_direct1_cfg_pad_i432; + input fabric_direct1_cfg_pad_i433; + input fabric_direct1_cfg_pad_i434; + input fabric_direct1_cfg_pad_i435; + input fabric_direct1_cfg_pad_i436; + input fabric_direct1_cfg_pad_i437; + input fabric_direct1_cfg_pad_i438; + input fabric_direct1_cfg_pad_i439; + input fabric_direct1_cfg_pad_i44; + input fabric_direct1_cfg_pad_i440; + input fabric_direct1_cfg_pad_i441; + input fabric_direct1_cfg_pad_i442; + input fabric_direct1_cfg_pad_i443; + input fabric_direct1_cfg_pad_i444; + input fabric_direct1_cfg_pad_i445; + input fabric_direct1_cfg_pad_i446; + input fabric_direct1_cfg_pad_i447; + input fabric_direct1_cfg_pad_i448; + input fabric_direct1_cfg_pad_i449; + input fabric_direct1_cfg_pad_i45; + input fabric_direct1_cfg_pad_i450; + input fabric_direct1_cfg_pad_i451; + input fabric_direct1_cfg_pad_i452; + input fabric_direct1_cfg_pad_i453; + input fabric_direct1_cfg_pad_i454; + input fabric_direct1_cfg_pad_i455; + input fabric_direct1_cfg_pad_i456; + input fabric_direct1_cfg_pad_i457; + input fabric_direct1_cfg_pad_i458; + input fabric_direct1_cfg_pad_i459; + input fabric_direct1_cfg_pad_i46; + input fabric_direct1_cfg_pad_i460; + input fabric_direct1_cfg_pad_i461; + input fabric_direct1_cfg_pad_i462; + input fabric_direct1_cfg_pad_i463; + input fabric_direct1_cfg_pad_i464; + input fabric_direct1_cfg_pad_i465; + input fabric_direct1_cfg_pad_i466; + input fabric_direct1_cfg_pad_i467; + input fabric_direct1_cfg_pad_i468; + input fabric_direct1_cfg_pad_i469; + input fabric_direct1_cfg_pad_i47; + input fabric_direct1_cfg_pad_i470; + input fabric_direct1_cfg_pad_i471; + input fabric_direct1_cfg_pad_i472; + input fabric_direct1_cfg_pad_i473; + input fabric_direct1_cfg_pad_i474; + input fabric_direct1_cfg_pad_i475; + input fabric_direct1_cfg_pad_i476; + input fabric_direct1_cfg_pad_i477; + input fabric_direct1_cfg_pad_i478; + input fabric_direct1_cfg_pad_i479; + input fabric_direct1_cfg_pad_i48; + input fabric_direct1_cfg_pad_i480; + input fabric_direct1_cfg_pad_i49; + input fabric_direct1_cfg_pad_i5; + input fabric_direct1_cfg_pad_i50; + input fabric_direct1_cfg_pad_i51; + input fabric_direct1_cfg_pad_i52; + input fabric_direct1_cfg_pad_i53; + input fabric_direct1_cfg_pad_i54; + input fabric_direct1_cfg_pad_i55; + input fabric_direct1_cfg_pad_i56; + input fabric_direct1_cfg_pad_i57; + input fabric_direct1_cfg_pad_i58; + input fabric_direct1_cfg_pad_i59; + input fabric_direct1_cfg_pad_i6; + input fabric_direct1_cfg_pad_i60; + input fabric_direct1_cfg_pad_i61; + input fabric_direct1_cfg_pad_i62; + input fabric_direct1_cfg_pad_i63; + input fabric_direct1_cfg_pad_i64; + input fabric_direct1_cfg_pad_i65; + input fabric_direct1_cfg_pad_i66; + input fabric_direct1_cfg_pad_i67; + input fabric_direct1_cfg_pad_i68; + input fabric_direct1_cfg_pad_i69; + input fabric_direct1_cfg_pad_i7; + input fabric_direct1_cfg_pad_i70; + input fabric_direct1_cfg_pad_i71; + input fabric_direct1_cfg_pad_i72; + input fabric_direct1_cfg_pad_i73; + input fabric_direct1_cfg_pad_i74; + input fabric_direct1_cfg_pad_i75; + input fabric_direct1_cfg_pad_i76; + input fabric_direct1_cfg_pad_i77; + input fabric_direct1_cfg_pad_i78; + input fabric_direct1_cfg_pad_i79; + input fabric_direct1_cfg_pad_i8; + input fabric_direct1_cfg_pad_i80; + input fabric_direct1_cfg_pad_i81; + input fabric_direct1_cfg_pad_i82; + input fabric_direct1_cfg_pad_i83; + input fabric_direct1_cfg_pad_i84; + input fabric_direct1_cfg_pad_i85; + input fabric_direct1_cfg_pad_i86; + input fabric_direct1_cfg_pad_i87; + input fabric_direct1_cfg_pad_i88; + input fabric_direct1_cfg_pad_i89; + input fabric_direct1_cfg_pad_i9; + input fabric_direct1_cfg_pad_i90; + input fabric_direct1_cfg_pad_i91; + input fabric_direct1_cfg_pad_i92; + input fabric_direct1_cfg_pad_i93; + input fabric_direct1_cfg_pad_i94; + input fabric_direct1_cfg_pad_i95; + input fabric_direct1_cfg_pad_i96; + input fabric_direct1_cfg_pad_i97; + input fabric_direct1_cfg_pad_i98; + input fabric_direct1_cfg_pad_i99; + input fabric_direct1_clock_fabric_i1; + input fabric_direct1_clock_fabric_i2; + input fabric_direct1_clock_fabric_i3; + input fabric_direct1_clock_fabric_i4; + input fabric_direct1_di_ena_i1; + input fabric_direct1_di_ena_i10; + input fabric_direct1_di_ena_i11; + input fabric_direct1_di_ena_i12; + input fabric_direct1_di_ena_i13; + input fabric_direct1_di_ena_i14; + input fabric_direct1_di_ena_i15; + input fabric_direct1_di_ena_i16; + input fabric_direct1_di_ena_i2; + input fabric_direct1_di_ena_i3; + input fabric_direct1_di_ena_i4; + input fabric_direct1_di_ena_i5; + input fabric_direct1_di_ena_i6; + input fabric_direct1_di_ena_i7; + input fabric_direct1_di_ena_i8; + input fabric_direct1_di_ena_i9; + output fabric_direct1_di_o1; + output fabric_direct1_di_o10; + output fabric_direct1_di_o11; + output fabric_direct1_di_o12; + output fabric_direct1_di_o13; + output fabric_direct1_di_o14; + output fabric_direct1_di_o15; + output fabric_direct1_di_o16; + output fabric_direct1_di_o2; + output fabric_direct1_di_o3; + output fabric_direct1_di_o4; + output fabric_direct1_di_o5; + output fabric_direct1_di_o6; + output fabric_direct1_di_o7; + output fabric_direct1_di_o8; + output fabric_direct1_di_o9; + input fabric_direct1_di_rs_i1; + input fabric_direct1_di_rs_i10; + input fabric_direct1_di_rs_i11; + input fabric_direct1_di_rs_i12; + input fabric_direct1_di_rs_i13; + input fabric_direct1_di_rs_i14; + input fabric_direct1_di_rs_i15; + input fabric_direct1_di_rs_i16; + input fabric_direct1_di_rs_i2; + input fabric_direct1_di_rs_i3; + input fabric_direct1_di_rs_i4; + input fabric_direct1_di_rs_i5; + input fabric_direct1_di_rs_i6; + input fabric_direct1_di_rs_i7; + input fabric_direct1_di_rs_i8; + input fabric_direct1_di_rs_i9; + input fabric_direct1_do_ena_i1; + input fabric_direct1_do_ena_i10; + input fabric_direct1_do_ena_i11; + input fabric_direct1_do_ena_i12; + input fabric_direct1_do_ena_i13; + input fabric_direct1_do_ena_i14; + input fabric_direct1_do_ena_i15; + input fabric_direct1_do_ena_i16; + input fabric_direct1_do_ena_i2; + input fabric_direct1_do_ena_i3; + input fabric_direct1_do_ena_i4; + input fabric_direct1_do_ena_i5; + input fabric_direct1_do_ena_i6; + input fabric_direct1_do_ena_i7; + input fabric_direct1_do_ena_i8; + input fabric_direct1_do_ena_i9; + input fabric_direct1_do_i1; + input fabric_direct1_do_i10; + input fabric_direct1_do_i11; + input fabric_direct1_do_i12; + input fabric_direct1_do_i13; + input fabric_direct1_do_i14; + input fabric_direct1_do_i15; + input fabric_direct1_do_i16; + input fabric_direct1_do_i2; + input fabric_direct1_do_i3; + input fabric_direct1_do_i4; + input fabric_direct1_do_i5; + input fabric_direct1_do_i6; + input fabric_direct1_do_i7; + input fabric_direct1_do_i8; + input fabric_direct1_do_i9; + input fabric_direct1_do_rs_i1; + input fabric_direct1_do_rs_i10; + input fabric_direct1_do_rs_i11; + input fabric_direct1_do_rs_i12; + input fabric_direct1_do_rs_i13; + input fabric_direct1_do_rs_i14; + input fabric_direct1_do_rs_i15; + input fabric_direct1_do_rs_i16; + input fabric_direct1_do_rs_i2; + input fabric_direct1_do_rs_i3; + input fabric_direct1_do_rs_i4; + input fabric_direct1_do_rs_i5; + input fabric_direct1_do_rs_i6; + input fabric_direct1_do_rs_i7; + input fabric_direct1_do_rs_i8; + input fabric_direct1_do_rs_i9; + input fabric_direct1_loopback_en_i; + input fabric_direct1_loopback_mux_i; + input fabric_direct1_oe_ena_i1; + input fabric_direct1_oe_ena_i10; + input fabric_direct1_oe_ena_i11; + input fabric_direct1_oe_ena_i12; + input fabric_direct1_oe_ena_i13; + input fabric_direct1_oe_ena_i14; + input fabric_direct1_oe_ena_i15; + input fabric_direct1_oe_ena_i16; + input fabric_direct1_oe_ena_i2; + input fabric_direct1_oe_ena_i3; + input fabric_direct1_oe_ena_i4; + input fabric_direct1_oe_ena_i5; + input fabric_direct1_oe_ena_i6; + input fabric_direct1_oe_ena_i7; + input fabric_direct1_oe_ena_i8; + input fabric_direct1_oe_ena_i9; + input fabric_direct1_oe_i1; + input fabric_direct1_oe_i10; + input fabric_direct1_oe_i11; + input fabric_direct1_oe_i12; + input fabric_direct1_oe_i13; + input fabric_direct1_oe_i14; + input fabric_direct1_oe_i15; + input fabric_direct1_oe_i16; + input fabric_direct1_oe_i2; + input fabric_direct1_oe_i3; + input fabric_direct1_oe_i4; + input fabric_direct1_oe_i5; + input fabric_direct1_oe_i6; + input fabric_direct1_oe_i7; + input fabric_direct1_oe_i8; + input fabric_direct1_oe_i9; + input fabric_direct1_oe_rs_i1; + input fabric_direct1_oe_rs_i10; + input fabric_direct1_oe_rs_i11; + input fabric_direct1_oe_rs_i12; + input fabric_direct1_oe_rs_i13; + input fabric_direct1_oe_rs_i14; + input fabric_direct1_oe_rs_i15; + input fabric_direct1_oe_rs_i16; + input fabric_direct1_oe_rs_i2; + input fabric_direct1_oe_rs_i3; + input fabric_direct1_oe_rs_i4; + input fabric_direct1_oe_rs_i5; + input fabric_direct1_oe_rs_i6; + input fabric_direct1_oe_rs_i7; + input fabric_direct1_oe_rs_i8; + input fabric_direct1_oe_rs_i9; + input fabric_direct1_scan_en_i; + input fabric_direct2_cfg_bank_i1; + input fabric_direct2_cfg_bank_i2; + input fabric_direct2_cfg_bank_i3; + input fabric_direct2_cfg_bank_i4; + input fabric_direct2_cfg_pad_i1; + input fabric_direct2_cfg_pad_i10; + input fabric_direct2_cfg_pad_i100; + input fabric_direct2_cfg_pad_i101; + input fabric_direct2_cfg_pad_i102; + input fabric_direct2_cfg_pad_i103; + input fabric_direct2_cfg_pad_i104; + input fabric_direct2_cfg_pad_i105; + input fabric_direct2_cfg_pad_i106; + input fabric_direct2_cfg_pad_i107; + input fabric_direct2_cfg_pad_i108; + input fabric_direct2_cfg_pad_i109; + input fabric_direct2_cfg_pad_i11; + input fabric_direct2_cfg_pad_i110; + input fabric_direct2_cfg_pad_i111; + input fabric_direct2_cfg_pad_i112; + input fabric_direct2_cfg_pad_i113; + input fabric_direct2_cfg_pad_i114; + input fabric_direct2_cfg_pad_i115; + input fabric_direct2_cfg_pad_i116; + input fabric_direct2_cfg_pad_i117; + input fabric_direct2_cfg_pad_i118; + input fabric_direct2_cfg_pad_i119; + input fabric_direct2_cfg_pad_i12; + input fabric_direct2_cfg_pad_i120; + input fabric_direct2_cfg_pad_i121; + input fabric_direct2_cfg_pad_i122; + input fabric_direct2_cfg_pad_i123; + input fabric_direct2_cfg_pad_i124; + input fabric_direct2_cfg_pad_i125; + input fabric_direct2_cfg_pad_i126; + input fabric_direct2_cfg_pad_i127; + input fabric_direct2_cfg_pad_i128; + input fabric_direct2_cfg_pad_i129; + input fabric_direct2_cfg_pad_i13; + input fabric_direct2_cfg_pad_i130; + input fabric_direct2_cfg_pad_i131; + input fabric_direct2_cfg_pad_i132; + input fabric_direct2_cfg_pad_i133; + input fabric_direct2_cfg_pad_i134; + input fabric_direct2_cfg_pad_i135; + input fabric_direct2_cfg_pad_i136; + input fabric_direct2_cfg_pad_i137; + input fabric_direct2_cfg_pad_i138; + input fabric_direct2_cfg_pad_i139; + input fabric_direct2_cfg_pad_i14; + input fabric_direct2_cfg_pad_i140; + input fabric_direct2_cfg_pad_i141; + input fabric_direct2_cfg_pad_i142; + input fabric_direct2_cfg_pad_i143; + input fabric_direct2_cfg_pad_i144; + input fabric_direct2_cfg_pad_i145; + input fabric_direct2_cfg_pad_i146; + input fabric_direct2_cfg_pad_i147; + input fabric_direct2_cfg_pad_i148; + input fabric_direct2_cfg_pad_i149; + input fabric_direct2_cfg_pad_i15; + input fabric_direct2_cfg_pad_i150; + input fabric_direct2_cfg_pad_i151; + input fabric_direct2_cfg_pad_i152; + input fabric_direct2_cfg_pad_i153; + input fabric_direct2_cfg_pad_i154; + input fabric_direct2_cfg_pad_i155; + input fabric_direct2_cfg_pad_i156; + input fabric_direct2_cfg_pad_i157; + input fabric_direct2_cfg_pad_i158; + input fabric_direct2_cfg_pad_i159; + input fabric_direct2_cfg_pad_i16; + input fabric_direct2_cfg_pad_i160; + input fabric_direct2_cfg_pad_i161; + input fabric_direct2_cfg_pad_i162; + input fabric_direct2_cfg_pad_i163; + input fabric_direct2_cfg_pad_i164; + input fabric_direct2_cfg_pad_i165; + input fabric_direct2_cfg_pad_i166; + input fabric_direct2_cfg_pad_i167; + input fabric_direct2_cfg_pad_i168; + input fabric_direct2_cfg_pad_i169; + input fabric_direct2_cfg_pad_i17; + input fabric_direct2_cfg_pad_i170; + input fabric_direct2_cfg_pad_i171; + input fabric_direct2_cfg_pad_i172; + input fabric_direct2_cfg_pad_i173; + input fabric_direct2_cfg_pad_i174; + input fabric_direct2_cfg_pad_i175; + input fabric_direct2_cfg_pad_i176; + input fabric_direct2_cfg_pad_i177; + input fabric_direct2_cfg_pad_i178; + input fabric_direct2_cfg_pad_i179; + input fabric_direct2_cfg_pad_i18; + input fabric_direct2_cfg_pad_i180; + input fabric_direct2_cfg_pad_i181; + input fabric_direct2_cfg_pad_i182; + input fabric_direct2_cfg_pad_i183; + input fabric_direct2_cfg_pad_i184; + input fabric_direct2_cfg_pad_i185; + input fabric_direct2_cfg_pad_i186; + input fabric_direct2_cfg_pad_i187; + input fabric_direct2_cfg_pad_i188; + input fabric_direct2_cfg_pad_i189; + input fabric_direct2_cfg_pad_i19; + input fabric_direct2_cfg_pad_i190; + input fabric_direct2_cfg_pad_i191; + input fabric_direct2_cfg_pad_i192; + input fabric_direct2_cfg_pad_i193; + input fabric_direct2_cfg_pad_i194; + input fabric_direct2_cfg_pad_i195; + input fabric_direct2_cfg_pad_i196; + input fabric_direct2_cfg_pad_i197; + input fabric_direct2_cfg_pad_i198; + input fabric_direct2_cfg_pad_i199; + input fabric_direct2_cfg_pad_i2; + input fabric_direct2_cfg_pad_i20; + input fabric_direct2_cfg_pad_i200; + input fabric_direct2_cfg_pad_i201; + input fabric_direct2_cfg_pad_i202; + input fabric_direct2_cfg_pad_i203; + input fabric_direct2_cfg_pad_i204; + input fabric_direct2_cfg_pad_i205; + input fabric_direct2_cfg_pad_i206; + input fabric_direct2_cfg_pad_i207; + input fabric_direct2_cfg_pad_i208; + input fabric_direct2_cfg_pad_i209; + input fabric_direct2_cfg_pad_i21; + input fabric_direct2_cfg_pad_i210; + input fabric_direct2_cfg_pad_i211; + input fabric_direct2_cfg_pad_i212; + input fabric_direct2_cfg_pad_i213; + input fabric_direct2_cfg_pad_i214; + input fabric_direct2_cfg_pad_i215; + input fabric_direct2_cfg_pad_i216; + input fabric_direct2_cfg_pad_i217; + input fabric_direct2_cfg_pad_i218; + input fabric_direct2_cfg_pad_i219; + input fabric_direct2_cfg_pad_i22; + input fabric_direct2_cfg_pad_i220; + input fabric_direct2_cfg_pad_i221; + input fabric_direct2_cfg_pad_i222; + input fabric_direct2_cfg_pad_i223; + input fabric_direct2_cfg_pad_i224; + input fabric_direct2_cfg_pad_i225; + input fabric_direct2_cfg_pad_i226; + input fabric_direct2_cfg_pad_i227; + input fabric_direct2_cfg_pad_i228; + input fabric_direct2_cfg_pad_i229; + input fabric_direct2_cfg_pad_i23; + input fabric_direct2_cfg_pad_i230; + input fabric_direct2_cfg_pad_i231; + input fabric_direct2_cfg_pad_i232; + input fabric_direct2_cfg_pad_i233; + input fabric_direct2_cfg_pad_i234; + input fabric_direct2_cfg_pad_i235; + input fabric_direct2_cfg_pad_i236; + input fabric_direct2_cfg_pad_i237; + input fabric_direct2_cfg_pad_i238; + input fabric_direct2_cfg_pad_i239; + input fabric_direct2_cfg_pad_i24; + input fabric_direct2_cfg_pad_i240; + input fabric_direct2_cfg_pad_i241; + input fabric_direct2_cfg_pad_i242; + input fabric_direct2_cfg_pad_i243; + input fabric_direct2_cfg_pad_i244; + input fabric_direct2_cfg_pad_i245; + input fabric_direct2_cfg_pad_i246; + input fabric_direct2_cfg_pad_i247; + input fabric_direct2_cfg_pad_i248; + input fabric_direct2_cfg_pad_i249; + input fabric_direct2_cfg_pad_i25; + input fabric_direct2_cfg_pad_i250; + input fabric_direct2_cfg_pad_i251; + input fabric_direct2_cfg_pad_i252; + input fabric_direct2_cfg_pad_i253; + input fabric_direct2_cfg_pad_i254; + input fabric_direct2_cfg_pad_i255; + input fabric_direct2_cfg_pad_i256; + input fabric_direct2_cfg_pad_i257; + input fabric_direct2_cfg_pad_i258; + input fabric_direct2_cfg_pad_i259; + input fabric_direct2_cfg_pad_i26; + input fabric_direct2_cfg_pad_i260; + input fabric_direct2_cfg_pad_i261; + input fabric_direct2_cfg_pad_i262; + input fabric_direct2_cfg_pad_i263; + input fabric_direct2_cfg_pad_i264; + input fabric_direct2_cfg_pad_i265; + input fabric_direct2_cfg_pad_i266; + input fabric_direct2_cfg_pad_i267; + input fabric_direct2_cfg_pad_i268; + input fabric_direct2_cfg_pad_i269; + input fabric_direct2_cfg_pad_i27; + input fabric_direct2_cfg_pad_i270; + input fabric_direct2_cfg_pad_i271; + input fabric_direct2_cfg_pad_i272; + input fabric_direct2_cfg_pad_i273; + input fabric_direct2_cfg_pad_i274; + input fabric_direct2_cfg_pad_i275; + input fabric_direct2_cfg_pad_i276; + input fabric_direct2_cfg_pad_i277; + input fabric_direct2_cfg_pad_i278; + input fabric_direct2_cfg_pad_i279; + input fabric_direct2_cfg_pad_i28; + input fabric_direct2_cfg_pad_i280; + input fabric_direct2_cfg_pad_i281; + input fabric_direct2_cfg_pad_i282; + input fabric_direct2_cfg_pad_i283; + input fabric_direct2_cfg_pad_i284; + input fabric_direct2_cfg_pad_i285; + input fabric_direct2_cfg_pad_i286; + input fabric_direct2_cfg_pad_i287; + input fabric_direct2_cfg_pad_i288; + input fabric_direct2_cfg_pad_i289; + input fabric_direct2_cfg_pad_i29; + input fabric_direct2_cfg_pad_i290; + input fabric_direct2_cfg_pad_i291; + input fabric_direct2_cfg_pad_i292; + input fabric_direct2_cfg_pad_i293; + input fabric_direct2_cfg_pad_i294; + input fabric_direct2_cfg_pad_i295; + input fabric_direct2_cfg_pad_i296; + input fabric_direct2_cfg_pad_i297; + input fabric_direct2_cfg_pad_i298; + input fabric_direct2_cfg_pad_i299; + input fabric_direct2_cfg_pad_i3; + input fabric_direct2_cfg_pad_i30; + input fabric_direct2_cfg_pad_i300; + input fabric_direct2_cfg_pad_i301; + input fabric_direct2_cfg_pad_i302; + input fabric_direct2_cfg_pad_i303; + input fabric_direct2_cfg_pad_i304; + input fabric_direct2_cfg_pad_i305; + input fabric_direct2_cfg_pad_i306; + input fabric_direct2_cfg_pad_i307; + input fabric_direct2_cfg_pad_i308; + input fabric_direct2_cfg_pad_i309; + input fabric_direct2_cfg_pad_i31; + input fabric_direct2_cfg_pad_i310; + input fabric_direct2_cfg_pad_i311; + input fabric_direct2_cfg_pad_i312; + input fabric_direct2_cfg_pad_i313; + input fabric_direct2_cfg_pad_i314; + input fabric_direct2_cfg_pad_i315; + input fabric_direct2_cfg_pad_i316; + input fabric_direct2_cfg_pad_i317; + input fabric_direct2_cfg_pad_i318; + input fabric_direct2_cfg_pad_i319; + input fabric_direct2_cfg_pad_i32; + input fabric_direct2_cfg_pad_i320; + input fabric_direct2_cfg_pad_i321; + input fabric_direct2_cfg_pad_i322; + input fabric_direct2_cfg_pad_i323; + input fabric_direct2_cfg_pad_i324; + input fabric_direct2_cfg_pad_i325; + input fabric_direct2_cfg_pad_i326; + input fabric_direct2_cfg_pad_i327; + input fabric_direct2_cfg_pad_i328; + input fabric_direct2_cfg_pad_i329; + input fabric_direct2_cfg_pad_i33; + input fabric_direct2_cfg_pad_i330; + input fabric_direct2_cfg_pad_i331; + input fabric_direct2_cfg_pad_i332; + input fabric_direct2_cfg_pad_i333; + input fabric_direct2_cfg_pad_i334; + input fabric_direct2_cfg_pad_i335; + input fabric_direct2_cfg_pad_i336; + input fabric_direct2_cfg_pad_i337; + input fabric_direct2_cfg_pad_i338; + input fabric_direct2_cfg_pad_i339; + input fabric_direct2_cfg_pad_i34; + input fabric_direct2_cfg_pad_i340; + input fabric_direct2_cfg_pad_i341; + input fabric_direct2_cfg_pad_i342; + input fabric_direct2_cfg_pad_i343; + input fabric_direct2_cfg_pad_i344; + input fabric_direct2_cfg_pad_i345; + input fabric_direct2_cfg_pad_i346; + input fabric_direct2_cfg_pad_i347; + input fabric_direct2_cfg_pad_i348; + input fabric_direct2_cfg_pad_i349; + input fabric_direct2_cfg_pad_i35; + input fabric_direct2_cfg_pad_i350; + input fabric_direct2_cfg_pad_i351; + input fabric_direct2_cfg_pad_i352; + input fabric_direct2_cfg_pad_i353; + input fabric_direct2_cfg_pad_i354; + input fabric_direct2_cfg_pad_i355; + input fabric_direct2_cfg_pad_i356; + input fabric_direct2_cfg_pad_i357; + input fabric_direct2_cfg_pad_i358; + input fabric_direct2_cfg_pad_i359; + input fabric_direct2_cfg_pad_i36; + input fabric_direct2_cfg_pad_i360; + input fabric_direct2_cfg_pad_i361; + input fabric_direct2_cfg_pad_i362; + input fabric_direct2_cfg_pad_i363; + input fabric_direct2_cfg_pad_i364; + input fabric_direct2_cfg_pad_i365; + input fabric_direct2_cfg_pad_i366; + input fabric_direct2_cfg_pad_i367; + input fabric_direct2_cfg_pad_i368; + input fabric_direct2_cfg_pad_i369; + input fabric_direct2_cfg_pad_i37; + input fabric_direct2_cfg_pad_i370; + input fabric_direct2_cfg_pad_i371; + input fabric_direct2_cfg_pad_i372; + input fabric_direct2_cfg_pad_i373; + input fabric_direct2_cfg_pad_i374; + input fabric_direct2_cfg_pad_i375; + input fabric_direct2_cfg_pad_i376; + input fabric_direct2_cfg_pad_i377; + input fabric_direct2_cfg_pad_i378; + input fabric_direct2_cfg_pad_i379; + input fabric_direct2_cfg_pad_i38; + input fabric_direct2_cfg_pad_i380; + input fabric_direct2_cfg_pad_i381; + input fabric_direct2_cfg_pad_i382; + input fabric_direct2_cfg_pad_i383; + input fabric_direct2_cfg_pad_i384; + input fabric_direct2_cfg_pad_i385; + input fabric_direct2_cfg_pad_i386; + input fabric_direct2_cfg_pad_i387; + input fabric_direct2_cfg_pad_i388; + input fabric_direct2_cfg_pad_i389; + input fabric_direct2_cfg_pad_i39; + input fabric_direct2_cfg_pad_i390; + input fabric_direct2_cfg_pad_i391; + input fabric_direct2_cfg_pad_i392; + input fabric_direct2_cfg_pad_i393; + input fabric_direct2_cfg_pad_i394; + input fabric_direct2_cfg_pad_i395; + input fabric_direct2_cfg_pad_i396; + input fabric_direct2_cfg_pad_i397; + input fabric_direct2_cfg_pad_i398; + input fabric_direct2_cfg_pad_i399; + input fabric_direct2_cfg_pad_i4; + input fabric_direct2_cfg_pad_i40; + input fabric_direct2_cfg_pad_i400; + input fabric_direct2_cfg_pad_i401; + input fabric_direct2_cfg_pad_i402; + input fabric_direct2_cfg_pad_i403; + input fabric_direct2_cfg_pad_i404; + input fabric_direct2_cfg_pad_i405; + input fabric_direct2_cfg_pad_i406; + input fabric_direct2_cfg_pad_i407; + input fabric_direct2_cfg_pad_i408; + input fabric_direct2_cfg_pad_i409; + input fabric_direct2_cfg_pad_i41; + input fabric_direct2_cfg_pad_i410; + input fabric_direct2_cfg_pad_i411; + input fabric_direct2_cfg_pad_i412; + input fabric_direct2_cfg_pad_i413; + input fabric_direct2_cfg_pad_i414; + input fabric_direct2_cfg_pad_i415; + input fabric_direct2_cfg_pad_i416; + input fabric_direct2_cfg_pad_i417; + input fabric_direct2_cfg_pad_i418; + input fabric_direct2_cfg_pad_i419; + input fabric_direct2_cfg_pad_i42; + input fabric_direct2_cfg_pad_i420; + input fabric_direct2_cfg_pad_i421; + input fabric_direct2_cfg_pad_i422; + input fabric_direct2_cfg_pad_i423; + input fabric_direct2_cfg_pad_i424; + input fabric_direct2_cfg_pad_i425; + input fabric_direct2_cfg_pad_i426; + input fabric_direct2_cfg_pad_i427; + input fabric_direct2_cfg_pad_i428; + input fabric_direct2_cfg_pad_i429; + input fabric_direct2_cfg_pad_i43; + input fabric_direct2_cfg_pad_i430; + input fabric_direct2_cfg_pad_i431; + input fabric_direct2_cfg_pad_i432; + input fabric_direct2_cfg_pad_i433; + input fabric_direct2_cfg_pad_i434; + input fabric_direct2_cfg_pad_i435; + input fabric_direct2_cfg_pad_i436; + input fabric_direct2_cfg_pad_i437; + input fabric_direct2_cfg_pad_i438; + input fabric_direct2_cfg_pad_i439; + input fabric_direct2_cfg_pad_i44; + input fabric_direct2_cfg_pad_i440; + input fabric_direct2_cfg_pad_i441; + input fabric_direct2_cfg_pad_i442; + input fabric_direct2_cfg_pad_i443; + input fabric_direct2_cfg_pad_i444; + input fabric_direct2_cfg_pad_i445; + input fabric_direct2_cfg_pad_i446; + input fabric_direct2_cfg_pad_i447; + input fabric_direct2_cfg_pad_i448; + input fabric_direct2_cfg_pad_i449; + input fabric_direct2_cfg_pad_i45; + input fabric_direct2_cfg_pad_i450; + input fabric_direct2_cfg_pad_i451; + input fabric_direct2_cfg_pad_i452; + input fabric_direct2_cfg_pad_i453; + input fabric_direct2_cfg_pad_i454; + input fabric_direct2_cfg_pad_i455; + input fabric_direct2_cfg_pad_i456; + input fabric_direct2_cfg_pad_i457; + input fabric_direct2_cfg_pad_i458; + input fabric_direct2_cfg_pad_i459; + input fabric_direct2_cfg_pad_i46; + input fabric_direct2_cfg_pad_i460; + input fabric_direct2_cfg_pad_i461; + input fabric_direct2_cfg_pad_i462; + input fabric_direct2_cfg_pad_i463; + input fabric_direct2_cfg_pad_i464; + input fabric_direct2_cfg_pad_i465; + input fabric_direct2_cfg_pad_i466; + input fabric_direct2_cfg_pad_i467; + input fabric_direct2_cfg_pad_i468; + input fabric_direct2_cfg_pad_i469; + input fabric_direct2_cfg_pad_i47; + input fabric_direct2_cfg_pad_i470; + input fabric_direct2_cfg_pad_i471; + input fabric_direct2_cfg_pad_i472; + input fabric_direct2_cfg_pad_i473; + input fabric_direct2_cfg_pad_i474; + input fabric_direct2_cfg_pad_i475; + input fabric_direct2_cfg_pad_i476; + input fabric_direct2_cfg_pad_i477; + input fabric_direct2_cfg_pad_i478; + input fabric_direct2_cfg_pad_i479; + input fabric_direct2_cfg_pad_i48; + input fabric_direct2_cfg_pad_i480; + input fabric_direct2_cfg_pad_i481; + input fabric_direct2_cfg_pad_i482; + input fabric_direct2_cfg_pad_i483; + input fabric_direct2_cfg_pad_i484; + input fabric_direct2_cfg_pad_i485; + input fabric_direct2_cfg_pad_i486; + input fabric_direct2_cfg_pad_i487; + input fabric_direct2_cfg_pad_i488; + input fabric_direct2_cfg_pad_i489; + input fabric_direct2_cfg_pad_i49; + input fabric_direct2_cfg_pad_i490; + input fabric_direct2_cfg_pad_i491; + input fabric_direct2_cfg_pad_i492; + input fabric_direct2_cfg_pad_i493; + input fabric_direct2_cfg_pad_i494; + input fabric_direct2_cfg_pad_i495; + input fabric_direct2_cfg_pad_i496; + input fabric_direct2_cfg_pad_i497; + input fabric_direct2_cfg_pad_i498; + input fabric_direct2_cfg_pad_i499; + input fabric_direct2_cfg_pad_i5; + input fabric_direct2_cfg_pad_i50; + input fabric_direct2_cfg_pad_i500; + input fabric_direct2_cfg_pad_i501; + input fabric_direct2_cfg_pad_i502; + input fabric_direct2_cfg_pad_i503; + input fabric_direct2_cfg_pad_i504; + input fabric_direct2_cfg_pad_i505; + input fabric_direct2_cfg_pad_i506; + input fabric_direct2_cfg_pad_i507; + input fabric_direct2_cfg_pad_i508; + input fabric_direct2_cfg_pad_i509; + input fabric_direct2_cfg_pad_i51; + input fabric_direct2_cfg_pad_i510; + input fabric_direct2_cfg_pad_i511; + input fabric_direct2_cfg_pad_i512; + input fabric_direct2_cfg_pad_i513; + input fabric_direct2_cfg_pad_i514; + input fabric_direct2_cfg_pad_i515; + input fabric_direct2_cfg_pad_i516; + input fabric_direct2_cfg_pad_i517; + input fabric_direct2_cfg_pad_i518; + input fabric_direct2_cfg_pad_i519; + input fabric_direct2_cfg_pad_i52; + input fabric_direct2_cfg_pad_i520; + input fabric_direct2_cfg_pad_i521; + input fabric_direct2_cfg_pad_i522; + input fabric_direct2_cfg_pad_i523; + input fabric_direct2_cfg_pad_i524; + input fabric_direct2_cfg_pad_i525; + input fabric_direct2_cfg_pad_i526; + input fabric_direct2_cfg_pad_i527; + input fabric_direct2_cfg_pad_i528; + input fabric_direct2_cfg_pad_i529; + input fabric_direct2_cfg_pad_i53; + input fabric_direct2_cfg_pad_i530; + input fabric_direct2_cfg_pad_i531; + input fabric_direct2_cfg_pad_i532; + input fabric_direct2_cfg_pad_i533; + input fabric_direct2_cfg_pad_i534; + input fabric_direct2_cfg_pad_i535; + input fabric_direct2_cfg_pad_i536; + input fabric_direct2_cfg_pad_i537; + input fabric_direct2_cfg_pad_i538; + input fabric_direct2_cfg_pad_i539; + input fabric_direct2_cfg_pad_i54; + input fabric_direct2_cfg_pad_i540; + input fabric_direct2_cfg_pad_i541; + input fabric_direct2_cfg_pad_i542; + input fabric_direct2_cfg_pad_i543; + input fabric_direct2_cfg_pad_i544; + input fabric_direct2_cfg_pad_i545; + input fabric_direct2_cfg_pad_i546; + input fabric_direct2_cfg_pad_i547; + input fabric_direct2_cfg_pad_i548; + input fabric_direct2_cfg_pad_i549; + input fabric_direct2_cfg_pad_i55; + input fabric_direct2_cfg_pad_i550; + input fabric_direct2_cfg_pad_i551; + input fabric_direct2_cfg_pad_i552; + input fabric_direct2_cfg_pad_i553; + input fabric_direct2_cfg_pad_i554; + input fabric_direct2_cfg_pad_i555; + input fabric_direct2_cfg_pad_i556; + input fabric_direct2_cfg_pad_i557; + input fabric_direct2_cfg_pad_i558; + input fabric_direct2_cfg_pad_i559; + input fabric_direct2_cfg_pad_i56; + input fabric_direct2_cfg_pad_i560; + input fabric_direct2_cfg_pad_i561; + input fabric_direct2_cfg_pad_i562; + input fabric_direct2_cfg_pad_i563; + input fabric_direct2_cfg_pad_i564; + input fabric_direct2_cfg_pad_i565; + input fabric_direct2_cfg_pad_i566; + input fabric_direct2_cfg_pad_i567; + input fabric_direct2_cfg_pad_i568; + input fabric_direct2_cfg_pad_i569; + input fabric_direct2_cfg_pad_i57; + input fabric_direct2_cfg_pad_i570; + input fabric_direct2_cfg_pad_i571; + input fabric_direct2_cfg_pad_i572; + input fabric_direct2_cfg_pad_i573; + input fabric_direct2_cfg_pad_i574; + input fabric_direct2_cfg_pad_i575; + input fabric_direct2_cfg_pad_i576; + input fabric_direct2_cfg_pad_i577; + input fabric_direct2_cfg_pad_i578; + input fabric_direct2_cfg_pad_i579; + input fabric_direct2_cfg_pad_i58; + input fabric_direct2_cfg_pad_i580; + input fabric_direct2_cfg_pad_i581; + input fabric_direct2_cfg_pad_i582; + input fabric_direct2_cfg_pad_i583; + input fabric_direct2_cfg_pad_i584; + input fabric_direct2_cfg_pad_i585; + input fabric_direct2_cfg_pad_i586; + input fabric_direct2_cfg_pad_i587; + input fabric_direct2_cfg_pad_i588; + input fabric_direct2_cfg_pad_i589; + input fabric_direct2_cfg_pad_i59; + input fabric_direct2_cfg_pad_i590; + input fabric_direct2_cfg_pad_i591; + input fabric_direct2_cfg_pad_i592; + input fabric_direct2_cfg_pad_i593; + input fabric_direct2_cfg_pad_i594; + input fabric_direct2_cfg_pad_i595; + input fabric_direct2_cfg_pad_i596; + input fabric_direct2_cfg_pad_i597; + input fabric_direct2_cfg_pad_i598; + input fabric_direct2_cfg_pad_i599; + input fabric_direct2_cfg_pad_i6; + input fabric_direct2_cfg_pad_i60; + input fabric_direct2_cfg_pad_i600; + input fabric_direct2_cfg_pad_i601; + input fabric_direct2_cfg_pad_i602; + input fabric_direct2_cfg_pad_i603; + input fabric_direct2_cfg_pad_i604; + input fabric_direct2_cfg_pad_i605; + input fabric_direct2_cfg_pad_i606; + input fabric_direct2_cfg_pad_i607; + input fabric_direct2_cfg_pad_i608; + input fabric_direct2_cfg_pad_i609; + input fabric_direct2_cfg_pad_i61; + input fabric_direct2_cfg_pad_i610; + input fabric_direct2_cfg_pad_i611; + input fabric_direct2_cfg_pad_i612; + input fabric_direct2_cfg_pad_i613; + input fabric_direct2_cfg_pad_i614; + input fabric_direct2_cfg_pad_i615; + input fabric_direct2_cfg_pad_i616; + input fabric_direct2_cfg_pad_i617; + input fabric_direct2_cfg_pad_i618; + input fabric_direct2_cfg_pad_i619; + input fabric_direct2_cfg_pad_i62; + input fabric_direct2_cfg_pad_i620; + input fabric_direct2_cfg_pad_i621; + input fabric_direct2_cfg_pad_i622; + input fabric_direct2_cfg_pad_i623; + input fabric_direct2_cfg_pad_i624; + input fabric_direct2_cfg_pad_i625; + input fabric_direct2_cfg_pad_i626; + input fabric_direct2_cfg_pad_i627; + input fabric_direct2_cfg_pad_i628; + input fabric_direct2_cfg_pad_i629; + input fabric_direct2_cfg_pad_i63; + input fabric_direct2_cfg_pad_i630; + input fabric_direct2_cfg_pad_i631; + input fabric_direct2_cfg_pad_i632; + input fabric_direct2_cfg_pad_i633; + input fabric_direct2_cfg_pad_i634; + input fabric_direct2_cfg_pad_i635; + input fabric_direct2_cfg_pad_i636; + input fabric_direct2_cfg_pad_i637; + input fabric_direct2_cfg_pad_i638; + input fabric_direct2_cfg_pad_i639; + input fabric_direct2_cfg_pad_i64; + input fabric_direct2_cfg_pad_i640; + input fabric_direct2_cfg_pad_i641; + input fabric_direct2_cfg_pad_i642; + input fabric_direct2_cfg_pad_i643; + input fabric_direct2_cfg_pad_i644; + input fabric_direct2_cfg_pad_i645; + input fabric_direct2_cfg_pad_i646; + input fabric_direct2_cfg_pad_i647; + input fabric_direct2_cfg_pad_i648; + input fabric_direct2_cfg_pad_i649; + input fabric_direct2_cfg_pad_i65; + input fabric_direct2_cfg_pad_i650; + input fabric_direct2_cfg_pad_i651; + input fabric_direct2_cfg_pad_i652; + input fabric_direct2_cfg_pad_i653; + input fabric_direct2_cfg_pad_i654; + input fabric_direct2_cfg_pad_i655; + input fabric_direct2_cfg_pad_i656; + input fabric_direct2_cfg_pad_i657; + input fabric_direct2_cfg_pad_i658; + input fabric_direct2_cfg_pad_i659; + input fabric_direct2_cfg_pad_i66; + input fabric_direct2_cfg_pad_i660; + input fabric_direct2_cfg_pad_i661; + input fabric_direct2_cfg_pad_i662; + input fabric_direct2_cfg_pad_i663; + input fabric_direct2_cfg_pad_i664; + input fabric_direct2_cfg_pad_i665; + input fabric_direct2_cfg_pad_i666; + input fabric_direct2_cfg_pad_i667; + input fabric_direct2_cfg_pad_i668; + input fabric_direct2_cfg_pad_i669; + input fabric_direct2_cfg_pad_i67; + input fabric_direct2_cfg_pad_i670; + input fabric_direct2_cfg_pad_i671; + input fabric_direct2_cfg_pad_i672; + input fabric_direct2_cfg_pad_i673; + input fabric_direct2_cfg_pad_i674; + input fabric_direct2_cfg_pad_i675; + input fabric_direct2_cfg_pad_i676; + input fabric_direct2_cfg_pad_i677; + input fabric_direct2_cfg_pad_i678; + input fabric_direct2_cfg_pad_i679; + input fabric_direct2_cfg_pad_i68; + input fabric_direct2_cfg_pad_i680; + input fabric_direct2_cfg_pad_i681; + input fabric_direct2_cfg_pad_i682; + input fabric_direct2_cfg_pad_i683; + input fabric_direct2_cfg_pad_i684; + input fabric_direct2_cfg_pad_i685; + input fabric_direct2_cfg_pad_i686; + input fabric_direct2_cfg_pad_i687; + input fabric_direct2_cfg_pad_i688; + input fabric_direct2_cfg_pad_i689; + input fabric_direct2_cfg_pad_i69; + input fabric_direct2_cfg_pad_i690; + input fabric_direct2_cfg_pad_i691; + input fabric_direct2_cfg_pad_i692; + input fabric_direct2_cfg_pad_i693; + input fabric_direct2_cfg_pad_i694; + input fabric_direct2_cfg_pad_i695; + input fabric_direct2_cfg_pad_i696; + input fabric_direct2_cfg_pad_i697; + input fabric_direct2_cfg_pad_i698; + input fabric_direct2_cfg_pad_i699; + input fabric_direct2_cfg_pad_i7; + input fabric_direct2_cfg_pad_i70; + input fabric_direct2_cfg_pad_i700; + input fabric_direct2_cfg_pad_i701; + input fabric_direct2_cfg_pad_i702; + input fabric_direct2_cfg_pad_i703; + input fabric_direct2_cfg_pad_i704; + input fabric_direct2_cfg_pad_i705; + input fabric_direct2_cfg_pad_i706; + input fabric_direct2_cfg_pad_i707; + input fabric_direct2_cfg_pad_i708; + input fabric_direct2_cfg_pad_i709; + input fabric_direct2_cfg_pad_i71; + input fabric_direct2_cfg_pad_i710; + input fabric_direct2_cfg_pad_i711; + input fabric_direct2_cfg_pad_i712; + input fabric_direct2_cfg_pad_i713; + input fabric_direct2_cfg_pad_i714; + input fabric_direct2_cfg_pad_i715; + input fabric_direct2_cfg_pad_i716; + input fabric_direct2_cfg_pad_i717; + input fabric_direct2_cfg_pad_i718; + input fabric_direct2_cfg_pad_i719; + input fabric_direct2_cfg_pad_i72; + input fabric_direct2_cfg_pad_i720; + input fabric_direct2_cfg_pad_i73; + input fabric_direct2_cfg_pad_i74; + input fabric_direct2_cfg_pad_i75; + input fabric_direct2_cfg_pad_i76; + input fabric_direct2_cfg_pad_i77; + input fabric_direct2_cfg_pad_i78; + input fabric_direct2_cfg_pad_i79; + input fabric_direct2_cfg_pad_i8; + input fabric_direct2_cfg_pad_i80; + input fabric_direct2_cfg_pad_i81; + input fabric_direct2_cfg_pad_i82; + input fabric_direct2_cfg_pad_i83; + input fabric_direct2_cfg_pad_i84; + input fabric_direct2_cfg_pad_i85; + input fabric_direct2_cfg_pad_i86; + input fabric_direct2_cfg_pad_i87; + input fabric_direct2_cfg_pad_i88; + input fabric_direct2_cfg_pad_i89; + input fabric_direct2_cfg_pad_i9; + input fabric_direct2_cfg_pad_i90; + input fabric_direct2_cfg_pad_i91; + input fabric_direct2_cfg_pad_i92; + input fabric_direct2_cfg_pad_i93; + input fabric_direct2_cfg_pad_i94; + input fabric_direct2_cfg_pad_i95; + input fabric_direct2_cfg_pad_i96; + input fabric_direct2_cfg_pad_i97; + input fabric_direct2_cfg_pad_i98; + input fabric_direct2_cfg_pad_i99; + input fabric_direct2_clock_fabric_i1; + input fabric_direct2_clock_fabric_i2; + input fabric_direct2_clock_fabric_i3; + input fabric_direct2_clock_fabric_i4; + input fabric_direct2_di_ena_i1; + input fabric_direct2_di_ena_i10; + input fabric_direct2_di_ena_i11; + input fabric_direct2_di_ena_i12; + input fabric_direct2_di_ena_i13; + input fabric_direct2_di_ena_i14; + input fabric_direct2_di_ena_i15; + input fabric_direct2_di_ena_i16; + input fabric_direct2_di_ena_i17; + input fabric_direct2_di_ena_i18; + input fabric_direct2_di_ena_i19; + input fabric_direct2_di_ena_i2; + input fabric_direct2_di_ena_i20; + input fabric_direct2_di_ena_i21; + input fabric_direct2_di_ena_i22; + input fabric_direct2_di_ena_i23; + input fabric_direct2_di_ena_i24; + input fabric_direct2_di_ena_i3; + input fabric_direct2_di_ena_i4; + input fabric_direct2_di_ena_i5; + input fabric_direct2_di_ena_i6; + input fabric_direct2_di_ena_i7; + input fabric_direct2_di_ena_i8; + input fabric_direct2_di_ena_i9; + output fabric_direct2_di_o1; + output fabric_direct2_di_o10; + output fabric_direct2_di_o11; + output fabric_direct2_di_o12; + output fabric_direct2_di_o13; + output fabric_direct2_di_o14; + output fabric_direct2_di_o15; + output fabric_direct2_di_o16; + output fabric_direct2_di_o17; + output fabric_direct2_di_o18; + output fabric_direct2_di_o19; + output fabric_direct2_di_o2; + output fabric_direct2_di_o20; + output fabric_direct2_di_o21; + output fabric_direct2_di_o22; + output fabric_direct2_di_o23; + output fabric_direct2_di_o24; + output fabric_direct2_di_o3; + output fabric_direct2_di_o4; + output fabric_direct2_di_o5; + output fabric_direct2_di_o6; + output fabric_direct2_di_o7; + output fabric_direct2_di_o8; + output fabric_direct2_di_o9; + input fabric_direct2_di_rs_i1; + input fabric_direct2_di_rs_i10; + input fabric_direct2_di_rs_i11; + input fabric_direct2_di_rs_i12; + input fabric_direct2_di_rs_i13; + input fabric_direct2_di_rs_i14; + input fabric_direct2_di_rs_i15; + input fabric_direct2_di_rs_i16; + input fabric_direct2_di_rs_i17; + input fabric_direct2_di_rs_i18; + input fabric_direct2_di_rs_i19; + input fabric_direct2_di_rs_i2; + input fabric_direct2_di_rs_i20; + input fabric_direct2_di_rs_i21; + input fabric_direct2_di_rs_i22; + input fabric_direct2_di_rs_i23; + input fabric_direct2_di_rs_i24; + input fabric_direct2_di_rs_i3; + input fabric_direct2_di_rs_i4; + input fabric_direct2_di_rs_i5; + input fabric_direct2_di_rs_i6; + input fabric_direct2_di_rs_i7; + input fabric_direct2_di_rs_i8; + input fabric_direct2_di_rs_i9; + input fabric_direct2_do_ena_i1; + input fabric_direct2_do_ena_i10; + input fabric_direct2_do_ena_i11; + input fabric_direct2_do_ena_i12; + input fabric_direct2_do_ena_i13; + input fabric_direct2_do_ena_i14; + input fabric_direct2_do_ena_i15; + input fabric_direct2_do_ena_i16; + input fabric_direct2_do_ena_i17; + input fabric_direct2_do_ena_i18; + input fabric_direct2_do_ena_i19; + input fabric_direct2_do_ena_i2; + input fabric_direct2_do_ena_i20; + input fabric_direct2_do_ena_i21; + input fabric_direct2_do_ena_i22; + input fabric_direct2_do_ena_i23; + input fabric_direct2_do_ena_i24; + input fabric_direct2_do_ena_i3; + input fabric_direct2_do_ena_i4; + input fabric_direct2_do_ena_i5; + input fabric_direct2_do_ena_i6; + input fabric_direct2_do_ena_i7; + input fabric_direct2_do_ena_i8; + input fabric_direct2_do_ena_i9; + input fabric_direct2_do_i1; + input fabric_direct2_do_i10; + input fabric_direct2_do_i11; + input fabric_direct2_do_i12; + input fabric_direct2_do_i13; + input fabric_direct2_do_i14; + input fabric_direct2_do_i15; + input fabric_direct2_do_i16; + input fabric_direct2_do_i17; + input fabric_direct2_do_i18; + input fabric_direct2_do_i19; + input fabric_direct2_do_i2; + input fabric_direct2_do_i20; + input fabric_direct2_do_i21; + input fabric_direct2_do_i22; + input fabric_direct2_do_i23; + input fabric_direct2_do_i24; + input fabric_direct2_do_i3; + input fabric_direct2_do_i4; + input fabric_direct2_do_i5; + input fabric_direct2_do_i6; + input fabric_direct2_do_i7; + input fabric_direct2_do_i8; + input fabric_direct2_do_i9; + input fabric_direct2_do_rs_i1; + input fabric_direct2_do_rs_i10; + input fabric_direct2_do_rs_i11; + input fabric_direct2_do_rs_i12; + input fabric_direct2_do_rs_i13; + input fabric_direct2_do_rs_i14; + input fabric_direct2_do_rs_i15; + input fabric_direct2_do_rs_i16; + input fabric_direct2_do_rs_i17; + input fabric_direct2_do_rs_i18; + input fabric_direct2_do_rs_i19; + input fabric_direct2_do_rs_i2; + input fabric_direct2_do_rs_i20; + input fabric_direct2_do_rs_i21; + input fabric_direct2_do_rs_i22; + input fabric_direct2_do_rs_i23; + input fabric_direct2_do_rs_i24; + input fabric_direct2_do_rs_i3; + input fabric_direct2_do_rs_i4; + input fabric_direct2_do_rs_i5; + input fabric_direct2_do_rs_i6; + input fabric_direct2_do_rs_i7; + input fabric_direct2_do_rs_i8; + input fabric_direct2_do_rs_i9; + input fabric_direct2_loopback_en_i; + input fabric_direct2_loopback_mux_i; + input fabric_direct2_oe_ena_i1; + input fabric_direct2_oe_ena_i10; + input fabric_direct2_oe_ena_i11; + input fabric_direct2_oe_ena_i12; + input fabric_direct2_oe_ena_i13; + input fabric_direct2_oe_ena_i14; + input fabric_direct2_oe_ena_i15; + input fabric_direct2_oe_ena_i16; + input fabric_direct2_oe_ena_i17; + input fabric_direct2_oe_ena_i18; + input fabric_direct2_oe_ena_i19; + input fabric_direct2_oe_ena_i2; + input fabric_direct2_oe_ena_i20; + input fabric_direct2_oe_ena_i21; + input fabric_direct2_oe_ena_i22; + input fabric_direct2_oe_ena_i23; + input fabric_direct2_oe_ena_i24; + input fabric_direct2_oe_ena_i3; + input fabric_direct2_oe_ena_i4; + input fabric_direct2_oe_ena_i5; + input fabric_direct2_oe_ena_i6; + input fabric_direct2_oe_ena_i7; + input fabric_direct2_oe_ena_i8; + input fabric_direct2_oe_ena_i9; + input fabric_direct2_oe_i1; + input fabric_direct2_oe_i10; + input fabric_direct2_oe_i11; + input fabric_direct2_oe_i12; + input fabric_direct2_oe_i13; + input fabric_direct2_oe_i14; + input fabric_direct2_oe_i15; + input fabric_direct2_oe_i16; + input fabric_direct2_oe_i17; + input fabric_direct2_oe_i18; + input fabric_direct2_oe_i19; + input fabric_direct2_oe_i2; + input fabric_direct2_oe_i20; + input fabric_direct2_oe_i21; + input fabric_direct2_oe_i22; + input fabric_direct2_oe_i23; + input fabric_direct2_oe_i24; + input fabric_direct2_oe_i3; + input fabric_direct2_oe_i4; + input fabric_direct2_oe_i5; + input fabric_direct2_oe_i6; + input fabric_direct2_oe_i7; + input fabric_direct2_oe_i8; + input fabric_direct2_oe_i9; + input fabric_direct2_oe_rs_i1; + input fabric_direct2_oe_rs_i10; + input fabric_direct2_oe_rs_i11; + input fabric_direct2_oe_rs_i12; + input fabric_direct2_oe_rs_i13; + input fabric_direct2_oe_rs_i14; + input fabric_direct2_oe_rs_i15; + input fabric_direct2_oe_rs_i16; + input fabric_direct2_oe_rs_i17; + input fabric_direct2_oe_rs_i18; + input fabric_direct2_oe_rs_i19; + input fabric_direct2_oe_rs_i2; + input fabric_direct2_oe_rs_i20; + input fabric_direct2_oe_rs_i21; + input fabric_direct2_oe_rs_i22; + input fabric_direct2_oe_rs_i23; + input fabric_direct2_oe_rs_i24; + input fabric_direct2_oe_rs_i3; + input fabric_direct2_oe_rs_i4; + input fabric_direct2_oe_rs_i5; + input fabric_direct2_oe_rs_i6; + input fabric_direct2_oe_rs_i7; + input fabric_direct2_oe_rs_i8; + input fabric_direct2_oe_rs_i9; + input fabric_direct2_scan_en_i; + input fabric_direct_data_i1; + input fabric_direct_data_i10; + input fabric_direct_data_i11; + input fabric_direct_data_i12; + input fabric_direct_data_i13; + input fabric_direct_data_i14; + input fabric_direct_data_i15; + input fabric_direct_data_i16; + input fabric_direct_data_i17; + input fabric_direct_data_i18; + input fabric_direct_data_i19; + input fabric_direct_data_i2; + input fabric_direct_data_i20; + input fabric_direct_data_i21; + input fabric_direct_data_i22; + input fabric_direct_data_i23; + input fabric_direct_data_i24; + input fabric_direct_data_i25; + input fabric_direct_data_i26; + input fabric_direct_data_i27; + input fabric_direct_data_i28; + input fabric_direct_data_i29; + input fabric_direct_data_i3; + input fabric_direct_data_i30; + input fabric_direct_data_i31; + input fabric_direct_data_i32; + input fabric_direct_data_i4; + input fabric_direct_data_i5; + input fabric_direct_data_i6; + input fabric_direct_data_i7; + input fabric_direct_data_i8; + input fabric_direct_data_i9; + output fabric_direct_data_o1; + output fabric_direct_data_o10; + output fabric_direct_data_o11; + output fabric_direct_data_o12; + output fabric_direct_data_o13; + output fabric_direct_data_o14; + output fabric_direct_data_o15; + output fabric_direct_data_o16; + output fabric_direct_data_o17; + output fabric_direct_data_o18; + output fabric_direct_data_o19; + output fabric_direct_data_o2; + output fabric_direct_data_o20; + output fabric_direct_data_o21; + output fabric_direct_data_o22; + output fabric_direct_data_o23; + output fabric_direct_data_o24; + output fabric_direct_data_o25; + output fabric_direct_data_o26; + output fabric_direct_data_o27; + output fabric_direct_data_o28; + output fabric_direct_data_o29; + output fabric_direct_data_o3; + output fabric_direct_data_o30; + output fabric_direct_data_o31; + output fabric_direct_data_o32; + output fabric_direct_data_o4; + output fabric_direct_data_o5; + output fabric_direct_data_o6; + output fabric_direct_data_o7; + output fabric_direct_data_o8; + output fabric_direct_data_o9; + input fabric_enable_TMR_i1; + input fabric_enable_TMR_i2; + input fabric_enable_TMR_i3; + output fabric_flag_ready_TMR_o1; + output fabric_flag_ready_TMR_o2; + output fabric_flag_ready_TMR_o3; + output fabric_flag_trigger0_o; + output fabric_flag_trigger1_o; + input fabric_io_in_i1; + input fabric_io_in_i10; + input fabric_io_in_i11; + input fabric_io_in_i12; + input fabric_io_in_i13; + input fabric_io_in_i14; + input fabric_io_in_i15; + input fabric_io_in_i16; + input fabric_io_in_i17; + input fabric_io_in_i18; + input fabric_io_in_i19; + input fabric_io_in_i2; + input fabric_io_in_i20; + input fabric_io_in_i21; + input fabric_io_in_i22; + input fabric_io_in_i23; + input fabric_io_in_i24; + input fabric_io_in_i25; + input fabric_io_in_i26; + input fabric_io_in_i27; + input fabric_io_in_i28; + input fabric_io_in_i29; + input fabric_io_in_i3; + input fabric_io_in_i30; + input fabric_io_in_i31; + input fabric_io_in_i32; + input fabric_io_in_i33; + input fabric_io_in_i34; + input fabric_io_in_i35; + input fabric_io_in_i4; + input fabric_io_in_i5; + input fabric_io_in_i6; + input fabric_io_in_i7; + input fabric_io_in_i8; + input fabric_io_in_i9; + input fabric_io_oe_i1; + input fabric_io_oe_i10; + input fabric_io_oe_i11; + input fabric_io_oe_i12; + input fabric_io_oe_i13; + input fabric_io_oe_i14; + input fabric_io_oe_i15; + input fabric_io_oe_i16; + input fabric_io_oe_i17; + input fabric_io_oe_i18; + input fabric_io_oe_i19; + input fabric_io_oe_i2; + input fabric_io_oe_i20; + input fabric_io_oe_i21; + input fabric_io_oe_i22; + input fabric_io_oe_i23; + input fabric_io_oe_i24; + input fabric_io_oe_i25; + input fabric_io_oe_i26; + input fabric_io_oe_i27; + input fabric_io_oe_i28; + input fabric_io_oe_i29; + input fabric_io_oe_i3; + input fabric_io_oe_i30; + input fabric_io_oe_i31; + input fabric_io_oe_i32; + input fabric_io_oe_i33; + input fabric_io_oe_i34; + input fabric_io_oe_i35; + input fabric_io_oe_i4; + input fabric_io_oe_i5; + input fabric_io_oe_i6; + input fabric_io_oe_i7; + input fabric_io_oe_i8; + input fabric_io_oe_i9; + output fabric_io_out_o1; + output fabric_io_out_o10; + output fabric_io_out_o11; + output fabric_io_out_o12; + output fabric_io_out_o13; + output fabric_io_out_o14; + output fabric_io_out_o15; + output fabric_io_out_o16; + output fabric_io_out_o17; + output fabric_io_out_o18; + output fabric_io_out_o19; + output fabric_io_out_o2; + output fabric_io_out_o20; + output fabric_io_out_o21; + output fabric_io_out_o22; + output fabric_io_out_o23; + output fabric_io_out_o24; + output fabric_io_out_o25; + output fabric_io_out_o26; + output fabric_io_out_o27; + output fabric_io_out_o28; + output fabric_io_out_o29; + output fabric_io_out_o3; + output fabric_io_out_o30; + output fabric_io_out_o31; + output fabric_io_out_o32; + output fabric_io_out_o33; + output fabric_io_out_o34; + output fabric_io_out_o35; + output fabric_io_out_o4; + output fabric_io_out_o5; + output fabric_io_out_o6; + output fabric_io_out_o7; + output fabric_io_out_o8; + output fabric_io_out_o9; + output fabric_jtag_tck_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i1; + input fabric_lowskew_i10; + input fabric_lowskew_i11; + input fabric_lowskew_i12; + input fabric_lowskew_i13; + input fabric_lowskew_i14; + input fabric_lowskew_i15; + input fabric_lowskew_i16; + input fabric_lowskew_i17; + input fabric_lowskew_i18; + input fabric_lowskew_i19; + input fabric_lowskew_i2; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + input fabric_lowskew_i24; + input fabric_lowskew_i25; + input fabric_lowskew_i26; + input fabric_lowskew_i27; + input fabric_lowskew_i28; + input fabric_lowskew_i29; + input fabric_lowskew_i3; + input fabric_lowskew_i30; + input fabric_lowskew_i31; + input fabric_lowskew_i32; + input fabric_lowskew_i33; + input fabric_lowskew_i34; + input fabric_lowskew_i35; + input fabric_lowskew_i36; + input fabric_lowskew_i37; + input fabric_lowskew_i38; + input fabric_lowskew_i39; + input fabric_lowskew_i4; + input fabric_lowskew_i40; + input fabric_lowskew_i5; + input fabric_lowskew_i6; + input fabric_lowskew_i7; + input fabric_lowskew_i8; + input fabric_lowskew_i9; + output fabric_lowskew_o1; + output fabric_lowskew_o2; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + input fabric_mrepair_bend_i; + output fabric_mrepair_bist_mode_o; + output fabric_mrepair_bypass_o; + output fabric_mrepair_chip_status_o1; + output fabric_mrepair_chip_status_o10; + output fabric_mrepair_chip_status_o11; + output fabric_mrepair_chip_status_o12; + output fabric_mrepair_chip_status_o13; + output fabric_mrepair_chip_status_o14; + output fabric_mrepair_chip_status_o15; + output fabric_mrepair_chip_status_o16; + output fabric_mrepair_chip_status_o17; + output fabric_mrepair_chip_status_o18; + output fabric_mrepair_chip_status_o19; + output fabric_mrepair_chip_status_o2; + output fabric_mrepair_chip_status_o20; + output fabric_mrepair_chip_status_o21; + output fabric_mrepair_chip_status_o22; + output fabric_mrepair_chip_status_o23; + output fabric_mrepair_chip_status_o24; + output fabric_mrepair_chip_status_o25; + output fabric_mrepair_chip_status_o26; + output fabric_mrepair_chip_status_o27; + output fabric_mrepair_chip_status_o28; + output fabric_mrepair_chip_status_o29; + output fabric_mrepair_chip_status_o3; + output fabric_mrepair_chip_status_o30; + output fabric_mrepair_chip_status_o31; + output fabric_mrepair_chip_status_o32; + output fabric_mrepair_chip_status_o33; + output fabric_mrepair_chip_status_o34; + output fabric_mrepair_chip_status_o35; + output fabric_mrepair_chip_status_o36; + output fabric_mrepair_chip_status_o37; + output fabric_mrepair_chip_status_o38; + output fabric_mrepair_chip_status_o39; + output fabric_mrepair_chip_status_o4; + output fabric_mrepair_chip_status_o40; + output fabric_mrepair_chip_status_o41; + output fabric_mrepair_chip_status_o42; + output fabric_mrepair_chip_status_o43; + output fabric_mrepair_chip_status_o44; + output fabric_mrepair_chip_status_o45; + output fabric_mrepair_chip_status_o46; + output fabric_mrepair_chip_status_o47; + output fabric_mrepair_chip_status_o48; + output fabric_mrepair_chip_status_o49; + output fabric_mrepair_chip_status_o5; + output fabric_mrepair_chip_status_o50; + output fabric_mrepair_chip_status_o51; + output fabric_mrepair_chip_status_o52; + output fabric_mrepair_chip_status_o53; + output fabric_mrepair_chip_status_o54; + output fabric_mrepair_chip_status_o55; + output fabric_mrepair_chip_status_o56; + output fabric_mrepair_chip_status_o57; + output fabric_mrepair_chip_status_o58; + output fabric_mrepair_chip_status_o59; + output fabric_mrepair_chip_status_o6; + output fabric_mrepair_chip_status_o60; + output fabric_mrepair_chip_status_o61; + output fabric_mrepair_chip_status_o62; + output fabric_mrepair_chip_status_o63; + output fabric_mrepair_chip_status_o64; + output fabric_mrepair_chip_status_o65; + output fabric_mrepair_chip_status_o66; + output fabric_mrepair_chip_status_o67; + output fabric_mrepair_chip_status_o68; + output fabric_mrepair_chip_status_o69; + output fabric_mrepair_chip_status_o7; + output fabric_mrepair_chip_status_o70; + output fabric_mrepair_chip_status_o71; + output fabric_mrepair_chip_status_o72; + output fabric_mrepair_chip_status_o73; + output fabric_mrepair_chip_status_o74; + output fabric_mrepair_chip_status_o75; + output fabric_mrepair_chip_status_o76; + output fabric_mrepair_chip_status_o77; + output fabric_mrepair_chip_status_o78; + output fabric_mrepair_chip_status_o8; + output fabric_mrepair_chip_status_o9; + input fabric_mrepair_cke_force_i; + input fabric_mrepair_cke_i; + input fabric_mrepair_clk_i; + input fabric_mrepair_data_from_bist_i1; + input fabric_mrepair_data_from_bist_i10; + input fabric_mrepair_data_from_bist_i11; + input fabric_mrepair_data_from_bist_i12; + input fabric_mrepair_data_from_bist_i13; + input fabric_mrepair_data_from_bist_i14; + input fabric_mrepair_data_from_bist_i15; + input fabric_mrepair_data_from_bist_i16; + input fabric_mrepair_data_from_bist_i17; + input fabric_mrepair_data_from_bist_i18; + input fabric_mrepair_data_from_bist_i19; + input fabric_mrepair_data_from_bist_i2; + input fabric_mrepair_data_from_bist_i20; + input fabric_mrepair_data_from_bist_i21; + input fabric_mrepair_data_from_bist_i22; + input fabric_mrepair_data_from_bist_i23; + input fabric_mrepair_data_from_bist_i24; + input fabric_mrepair_data_from_bist_i25; + input fabric_mrepair_data_from_bist_i26; + input fabric_mrepair_data_from_bist_i3; + input fabric_mrepair_data_from_bist_i4; + input fabric_mrepair_data_from_bist_i5; + input fabric_mrepair_data_from_bist_i6; + input fabric_mrepair_data_from_bist_i7; + input fabric_mrepair_data_from_bist_i8; + input fabric_mrepair_data_from_bist_i9; + input fabric_mrepair_data_from_system_i; + input fabric_mrepair_data_shift_en_i; + output fabric_mrepair_data_to_bist_o1; + output fabric_mrepair_data_to_bist_o10; + output fabric_mrepair_data_to_bist_o11; + output fabric_mrepair_data_to_bist_o12; + output fabric_mrepair_data_to_bist_o13; + output fabric_mrepair_data_to_bist_o14; + output fabric_mrepair_data_to_bist_o15; + output fabric_mrepair_data_to_bist_o16; + output fabric_mrepair_data_to_bist_o17; + output fabric_mrepair_data_to_bist_o18; + output fabric_mrepair_data_to_bist_o19; + output fabric_mrepair_data_to_bist_o2; + output fabric_mrepair_data_to_bist_o20; + output fabric_mrepair_data_to_bist_o21; + output fabric_mrepair_data_to_bist_o22; + output fabric_mrepair_data_to_bist_o23; + output fabric_mrepair_data_to_bist_o24; + output fabric_mrepair_data_to_bist_o25; + output fabric_mrepair_data_to_bist_o26; + output fabric_mrepair_data_to_bist_o3; + output fabric_mrepair_data_to_bist_o4; + output fabric_mrepair_data_to_bist_o5; + output fabric_mrepair_data_to_bist_o6; + output fabric_mrepair_data_to_bist_o7; + output fabric_mrepair_data_to_bist_o8; + output fabric_mrepair_data_to_bist_o9; + output fabric_mrepair_data_to_system_o; + output fabric_mrepair_decoder_init_ready_o; + input fabric_mrepair_end_encoding_i; + output fabric_mrepair_fuse_ack_o; + input fabric_mrepair_fuse_add_i1; + input fabric_mrepair_fuse_add_i2; + input fabric_mrepair_fuse_add_i3; + input fabric_mrepair_fuse_add_i4; + input fabric_mrepair_fuse_add_i5; + input fabric_mrepair_fuse_add_i6; + input fabric_mrepair_fuse_add_i7; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output fabric_mrepair_fuse_bist1fail_o1; + output fabric_mrepair_fuse_bist1fail_o2; + output fabric_mrepair_fuse_bist1fail_o3; + output fabric_mrepair_fuse_bist1fail_o4; + output fabric_mrepair_fuse_bist1fail_o5; + output fabric_mrepair_fuse_bist1fail_o6; + output fabric_mrepair_fuse_bist1fail_o7; + output fabric_mrepair_fuse_bist1fail_o8; + output fabric_mrepair_fuse_bist2fail_o1; + output fabric_mrepair_fuse_bist2fail_o2; + output fabric_mrepair_fuse_bist2fail_o3; + output fabric_mrepair_fuse_bist2fail_o4; + output fabric_mrepair_fuse_bist2fail_o5; + output fabric_mrepair_fuse_bist2fail_o6; + output fabric_mrepair_fuse_bist2fail_o7; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + output fabric_mrepair_fuse_ded_o; + input fabric_mrepair_fuse_din_i1; + input fabric_mrepair_fuse_din_i10; + input fabric_mrepair_fuse_din_i11; + input fabric_mrepair_fuse_din_i12; + input fabric_mrepair_fuse_din_i13; + input fabric_mrepair_fuse_din_i14; + input fabric_mrepair_fuse_din_i15; + input fabric_mrepair_fuse_din_i16; + input fabric_mrepair_fuse_din_i17; + input fabric_mrepair_fuse_din_i18; + input fabric_mrepair_fuse_din_i19; + input fabric_mrepair_fuse_din_i2; + input fabric_mrepair_fuse_din_i20; + input fabric_mrepair_fuse_din_i21; + input fabric_mrepair_fuse_din_i22; + input fabric_mrepair_fuse_din_i23; + input fabric_mrepair_fuse_din_i24; + input fabric_mrepair_fuse_din_i25; + input fabric_mrepair_fuse_din_i26; + input fabric_mrepair_fuse_din_i27; + input fabric_mrepair_fuse_din_i28; + input fabric_mrepair_fuse_din_i29; + input fabric_mrepair_fuse_din_i3; + input fabric_mrepair_fuse_din_i30; + input fabric_mrepair_fuse_din_i31; + input fabric_mrepair_fuse_din_i32; + input fabric_mrepair_fuse_din_i33; + input fabric_mrepair_fuse_din_i34; + input fabric_mrepair_fuse_din_i35; + input fabric_mrepair_fuse_din_i36; + input fabric_mrepair_fuse_din_i37; + input fabric_mrepair_fuse_din_i38; + input fabric_mrepair_fuse_din_i39; + input fabric_mrepair_fuse_din_i4; + input fabric_mrepair_fuse_din_i5; + input fabric_mrepair_fuse_din_i6; + input fabric_mrepair_fuse_din_i7; + input fabric_mrepair_fuse_din_i8; + input fabric_mrepair_fuse_din_i9; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output fabric_mrepair_fuse_dout_o1; + output fabric_mrepair_fuse_dout_o10; + output fabric_mrepair_fuse_dout_o11; + output fabric_mrepair_fuse_dout_o12; + output fabric_mrepair_fuse_dout_o13; + output fabric_mrepair_fuse_dout_o14; + output fabric_mrepair_fuse_dout_o15; + output fabric_mrepair_fuse_dout_o16; + output fabric_mrepair_fuse_dout_o17; + output fabric_mrepair_fuse_dout_o18; + output fabric_mrepair_fuse_dout_o19; + output fabric_mrepair_fuse_dout_o2; + output fabric_mrepair_fuse_dout_o20; + output fabric_mrepair_fuse_dout_o21; + output fabric_mrepair_fuse_dout_o22; + output fabric_mrepair_fuse_dout_o23; + output fabric_mrepair_fuse_dout_o24; + output fabric_mrepair_fuse_dout_o25; + output fabric_mrepair_fuse_dout_o26; + output fabric_mrepair_fuse_dout_o27; + output fabric_mrepair_fuse_dout_o28; + output fabric_mrepair_fuse_dout_o29; + output fabric_mrepair_fuse_dout_o3; + output fabric_mrepair_fuse_dout_o30; + output fabric_mrepair_fuse_dout_o31; + output fabric_mrepair_fuse_dout_o32; + output fabric_mrepair_fuse_dout_o33; + output fabric_mrepair_fuse_dout_o34; + output fabric_mrepair_fuse_dout_o35; + output fabric_mrepair_fuse_dout_o36; + output fabric_mrepair_fuse_dout_o37; + output fabric_mrepair_fuse_dout_o38; + output fabric_mrepair_fuse_dout_o39; + output fabric_mrepair_fuse_dout_o4; + output fabric_mrepair_fuse_dout_o40; + output fabric_mrepair_fuse_dout_o41; + output fabric_mrepair_fuse_dout_o5; + output fabric_mrepair_fuse_dout_o6; + output fabric_mrepair_fuse_dout_o7; + output fabric_mrepair_fuse_dout_o8; + output fabric_mrepair_fuse_dout_o9; + input fabric_mrepair_fuse_eccbypass_i; + output fabric_mrepair_fuse_flagstate_o1; + output fabric_mrepair_fuse_flagstate_o2; + output fabric_mrepair_fuse_flagstate_o3; + output fabric_mrepair_fuse_flagstate_o4; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input fabric_mrepair_fuse_prgwidth_i1; + input fabric_mrepair_fuse_prgwidth_i2; + input fabric_mrepair_fuse_prgwidth_i3; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output fabric_mrepair_fuse_startword_o1; + output fabric_mrepair_fuse_startword_o10; + output fabric_mrepair_fuse_startword_o11; + output fabric_mrepair_fuse_startword_o12; + output fabric_mrepair_fuse_startword_o13; + output fabric_mrepair_fuse_startword_o14; + output fabric_mrepair_fuse_startword_o15; + output fabric_mrepair_fuse_startword_o16; + output fabric_mrepair_fuse_startword_o2; + output fabric_mrepair_fuse_startword_o3; + output fabric_mrepair_fuse_startword_o4; + output fabric_mrepair_fuse_startword_o5; + output fabric_mrepair_fuse_startword_o6; + output fabric_mrepair_fuse_startword_o7; + output fabric_mrepair_fuse_startword_o8; + output fabric_mrepair_fuse_startword_o9; + output fabric_mrepair_fuse_status_o1; + output fabric_mrepair_fuse_status_o2; + output fabric_mrepair_fuse_status_o3; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input fabric_mrepair_fuse_tst_scanin_i1; + input fabric_mrepair_fuse_tst_scanin_i2; + input fabric_mrepair_fuse_tst_scanin_i3; + input fabric_mrepair_fuse_tst_scanin_i4; + input fabric_mrepair_fuse_tst_scanin_i5; + input fabric_mrepair_fuse_tstscanenable_i; + output fabric_mrepair_fuse_tstscanout_o1; + output fabric_mrepair_fuse_tstscanout_o2; + output fabric_mrepair_fuse_tstscanout_o3; + output fabric_mrepair_fuse_tstscanout_o4; + output fabric_mrepair_fuse_tstscanout_o5; + output fabric_mrepair_fuse_wlromout_o1; + output fabric_mrepair_fuse_wlromout_o10; + output fabric_mrepair_fuse_wlromout_o2; + output fabric_mrepair_fuse_wlromout_o3; + output fabric_mrepair_fuse_wlromout_o4; + output fabric_mrepair_fuse_wlromout_o5; + output fabric_mrepair_fuse_wlromout_o6; + output fabric_mrepair_fuse_wlromout_o7; + output fabric_mrepair_fuse_wlromout_o8; + output fabric_mrepair_fuse_wlromout_o9; + input fabric_mrepair_fuse_wordlock_i; + input fabric_mrepair_global_bbad_i; + output fabric_mrepair_global_chip_status_o1; + output fabric_mrepair_global_chip_status_o2; + output fabric_mrepair_global_chip_status_o3; + input fabric_mrepair_global_repairable_i; + input fabric_mrepair_initn_i; + output fabric_mrepair_mem_atpg_mode_o; + output fabric_mrepair_mem_type_sel_o1; + output fabric_mrepair_mem_type_sel_o2; + output fabric_mrepair_mem_type_sel_o3; + output fabric_mrepair_mem_type_sel_o4; + output fabric_mrepair_mem_type_sel_o5; + output fabric_mrepair_memsafe_o; + input fabric_mrepair_mode_i1; + input fabric_mrepair_mode_i2; + input fabric_mrepair_mode_i3; + input fabric_mrepair_mode_i4; + output fabric_mrepair_mode_sel_o1; + output fabric_mrepair_mode_sel_o2; + output fabric_mrepair_mode_sel_o3; + output fabric_mrepair_mode_sel_o4; + input fabric_mrepair_pd_active_i1; + input fabric_mrepair_pd_active_i10; + input fabric_mrepair_pd_active_i11; + input fabric_mrepair_pd_active_i12; + input fabric_mrepair_pd_active_i13; + input fabric_mrepair_pd_active_i14; + input fabric_mrepair_pd_active_i15; + input fabric_mrepair_pd_active_i16; + input fabric_mrepair_pd_active_i17; + input fabric_mrepair_pd_active_i18; + input fabric_mrepair_pd_active_i19; + input fabric_mrepair_pd_active_i2; + input fabric_mrepair_pd_active_i20; + input fabric_mrepair_pd_active_i21; + input fabric_mrepair_pd_active_i22; + input fabric_mrepair_pd_active_i23; + input fabric_mrepair_pd_active_i24; + input fabric_mrepair_pd_active_i25; + input fabric_mrepair_pd_active_i26; + input fabric_mrepair_pd_active_i3; + input fabric_mrepair_pd_active_i4; + input fabric_mrepair_pd_active_i5; + input fabric_mrepair_pd_active_i6; + input fabric_mrepair_pd_active_i7; + input fabric_mrepair_pd_active_i8; + input fabric_mrepair_pd_active_i9; + output fabric_mrepair_pd_ready_o1; + output fabric_mrepair_pd_ready_o10; + output fabric_mrepair_pd_ready_o11; + output fabric_mrepair_pd_ready_o12; + output fabric_mrepair_pd_ready_o13; + output fabric_mrepair_pd_ready_o14; + output fabric_mrepair_pd_ready_o15; + output fabric_mrepair_pd_ready_o16; + output fabric_mrepair_pd_ready_o17; + output fabric_mrepair_pd_ready_o18; + output fabric_mrepair_pd_ready_o19; + output fabric_mrepair_pd_ready_o2; + output fabric_mrepair_pd_ready_o20; + output fabric_mrepair_pd_ready_o21; + output fabric_mrepair_pd_ready_o22; + output fabric_mrepair_pd_ready_o23; + output fabric_mrepair_pd_ready_o24; + output fabric_mrepair_pd_ready_o25; + output fabric_mrepair_pd_ready_o26; + output fabric_mrepair_pd_ready_o3; + output fabric_mrepair_pd_ready_o4; + output fabric_mrepair_pd_ready_o5; + output fabric_mrepair_pd_ready_o6; + output fabric_mrepair_pd_ready_o7; + output fabric_mrepair_pd_ready_o8; + output fabric_mrepair_pd_ready_o9; + input fabric_mrepair_por_i; + input fabric_mrepair_rst_n_i; + input fabric_mrepair_shift_en_i1; + input fabric_mrepair_shift_en_i10; + input fabric_mrepair_shift_en_i11; + input fabric_mrepair_shift_en_i12; + input fabric_mrepair_shift_en_i13; + input fabric_mrepair_shift_en_i14; + input fabric_mrepair_shift_en_i15; + input fabric_mrepair_shift_en_i16; + input fabric_mrepair_shift_en_i17; + input fabric_mrepair_shift_en_i18; + input fabric_mrepair_shift_en_i19; + input fabric_mrepair_shift_en_i2; + input fabric_mrepair_shift_en_i20; + input fabric_mrepair_shift_en_i21; + input fabric_mrepair_shift_en_i22; + input fabric_mrepair_shift_en_i23; + input fabric_mrepair_shift_en_i24; + input fabric_mrepair_shift_en_i25; + input fabric_mrepair_shift_en_i26; + input fabric_mrepair_shift_en_i3; + input fabric_mrepair_shift_en_i4; + input fabric_mrepair_shift_en_i5; + input fabric_mrepair_shift_en_i6; + input fabric_mrepair_shift_en_i7; + input fabric_mrepair_shift_en_i8; + input fabric_mrepair_shift_en_i9; + output fabric_mrepair_shift_en_to_bist_o1; + output fabric_mrepair_shift_en_to_bist_o10; + output fabric_mrepair_shift_en_to_bist_o11; + output fabric_mrepair_shift_en_to_bist_o12; + output fabric_mrepair_shift_en_to_bist_o13; + output fabric_mrepair_shift_en_to_bist_o14; + output fabric_mrepair_shift_en_to_bist_o15; + output fabric_mrepair_shift_en_to_bist_o16; + output fabric_mrepair_shift_en_to_bist_o17; + output fabric_mrepair_shift_en_to_bist_o18; + output fabric_mrepair_shift_en_to_bist_o19; + output fabric_mrepair_shift_en_to_bist_o2; + output fabric_mrepair_shift_en_to_bist_o20; + output fabric_mrepair_shift_en_to_bist_o21; + output fabric_mrepair_shift_en_to_bist_o22; + output fabric_mrepair_shift_en_to_bist_o23; + output fabric_mrepair_shift_en_to_bist_o24; + output fabric_mrepair_shift_en_to_bist_o25; + output fabric_mrepair_shift_en_to_bist_o26; + output fabric_mrepair_shift_en_to_bist_o3; + output fabric_mrepair_shift_en_to_bist_o4; + output fabric_mrepair_shift_en_to_bist_o5; + output fabric_mrepair_shift_en_to_bist_o6; + output fabric_mrepair_shift_en_to_bist_o7; + output fabric_mrepair_shift_en_to_bist_o8; + output fabric_mrepair_shift_en_to_bist_o9; + input fabric_mrepair_sif_load_en_i1; + input fabric_mrepair_sif_load_en_i10; + input fabric_mrepair_sif_load_en_i11; + input fabric_mrepair_sif_load_en_i12; + input fabric_mrepair_sif_load_en_i13; + input fabric_mrepair_sif_load_en_i14; + input fabric_mrepair_sif_load_en_i15; + input fabric_mrepair_sif_load_en_i16; + input fabric_mrepair_sif_load_en_i17; + input fabric_mrepair_sif_load_en_i18; + input fabric_mrepair_sif_load_en_i19; + input fabric_mrepair_sif_load_en_i2; + input fabric_mrepair_sif_load_en_i20; + input fabric_mrepair_sif_load_en_i21; + input fabric_mrepair_sif_load_en_i22; + input fabric_mrepair_sif_load_en_i23; + input fabric_mrepair_sif_load_en_i24; + input fabric_mrepair_sif_load_en_i25; + input fabric_mrepair_sif_load_en_i26; + input fabric_mrepair_sif_load_en_i3; + input fabric_mrepair_sif_load_en_i4; + input fabric_mrepair_sif_load_en_i5; + input fabric_mrepair_sif_load_en_i6; + input fabric_mrepair_sif_load_en_i7; + input fabric_mrepair_sif_load_en_i8; + input fabric_mrepair_sif_load_en_i9; + output fabric_mrepair_sif_load_en_to_bist_o1; + output fabric_mrepair_sif_load_en_to_bist_o10; + output fabric_mrepair_sif_load_en_to_bist_o11; + output fabric_mrepair_sif_load_en_to_bist_o12; + output fabric_mrepair_sif_load_en_to_bist_o13; + output fabric_mrepair_sif_load_en_to_bist_o14; + output fabric_mrepair_sif_load_en_to_bist_o15; + output fabric_mrepair_sif_load_en_to_bist_o16; + output fabric_mrepair_sif_load_en_to_bist_o17; + output fabric_mrepair_sif_load_en_to_bist_o18; + output fabric_mrepair_sif_load_en_to_bist_o19; + output fabric_mrepair_sif_load_en_to_bist_o2; + output fabric_mrepair_sif_load_en_to_bist_o20; + output fabric_mrepair_sif_load_en_to_bist_o21; + output fabric_mrepair_sif_load_en_to_bist_o22; + output fabric_mrepair_sif_load_en_to_bist_o23; + output fabric_mrepair_sif_load_en_to_bist_o24; + output fabric_mrepair_sif_load_en_to_bist_o25; + output fabric_mrepair_sif_load_en_to_bist_o26; + output fabric_mrepair_sif_load_en_to_bist_o3; + output fabric_mrepair_sif_load_en_to_bist_o4; + output fabric_mrepair_sif_load_en_to_bist_o5; + output fabric_mrepair_sif_load_en_to_bist_o6; + output fabric_mrepair_sif_load_en_to_bist_o7; + output fabric_mrepair_sif_load_en_to_bist_o8; + output fabric_mrepair_sif_load_en_to_bist_o9; + input fabric_mrepair_sif_reg_en_i1; + input fabric_mrepair_sif_reg_en_i10; + input fabric_mrepair_sif_reg_en_i11; + input fabric_mrepair_sif_reg_en_i12; + input fabric_mrepair_sif_reg_en_i13; + input fabric_mrepair_sif_reg_en_i14; + input fabric_mrepair_sif_reg_en_i15; + input fabric_mrepair_sif_reg_en_i16; + input fabric_mrepair_sif_reg_en_i17; + input fabric_mrepair_sif_reg_en_i18; + input fabric_mrepair_sif_reg_en_i19; + input fabric_mrepair_sif_reg_en_i2; + input fabric_mrepair_sif_reg_en_i20; + input fabric_mrepair_sif_reg_en_i21; + input fabric_mrepair_sif_reg_en_i22; + input fabric_mrepair_sif_reg_en_i23; + input fabric_mrepair_sif_reg_en_i24; + input fabric_mrepair_sif_reg_en_i25; + input fabric_mrepair_sif_reg_en_i26; + input fabric_mrepair_sif_reg_en_i3; + input fabric_mrepair_sif_reg_en_i4; + input fabric_mrepair_sif_reg_en_i5; + input fabric_mrepair_sif_reg_en_i6; + input fabric_mrepair_sif_reg_en_i7; + input fabric_mrepair_sif_reg_en_i8; + input fabric_mrepair_sif_reg_en_i9; + output fabric_mrepair_sif_reg_en_to_bist_o1; + output fabric_mrepair_sif_reg_en_to_bist_o10; + output fabric_mrepair_sif_reg_en_to_bist_o11; + output fabric_mrepair_sif_reg_en_to_bist_o12; + output fabric_mrepair_sif_reg_en_to_bist_o13; + output fabric_mrepair_sif_reg_en_to_bist_o14; + output fabric_mrepair_sif_reg_en_to_bist_o15; + output fabric_mrepair_sif_reg_en_to_bist_o16; + output fabric_mrepair_sif_reg_en_to_bist_o17; + output fabric_mrepair_sif_reg_en_to_bist_o18; + output fabric_mrepair_sif_reg_en_to_bist_o19; + output fabric_mrepair_sif_reg_en_to_bist_o2; + output fabric_mrepair_sif_reg_en_to_bist_o20; + output fabric_mrepair_sif_reg_en_to_bist_o21; + output fabric_mrepair_sif_reg_en_to_bist_o22; + output fabric_mrepair_sif_reg_en_to_bist_o23; + output fabric_mrepair_sif_reg_en_to_bist_o24; + output fabric_mrepair_sif_reg_en_to_bist_o25; + output fabric_mrepair_sif_reg_en_to_bist_o26; + output fabric_mrepair_sif_reg_en_to_bist_o3; + output fabric_mrepair_sif_reg_en_to_bist_o4; + output fabric_mrepair_sif_reg_en_to_bist_o5; + output fabric_mrepair_sif_reg_en_to_bist_o6; + output fabric_mrepair_sif_reg_en_to_bist_o7; + output fabric_mrepair_sif_reg_en_to_bist_o8; + output fabric_mrepair_sif_reg_en_to_bist_o9; + input fabric_mrepair_sif_update_en_i1; + input fabric_mrepair_sif_update_en_i10; + input fabric_mrepair_sif_update_en_i11; + input fabric_mrepair_sif_update_en_i12; + input fabric_mrepair_sif_update_en_i13; + input fabric_mrepair_sif_update_en_i14; + input fabric_mrepair_sif_update_en_i15; + input fabric_mrepair_sif_update_en_i16; + input fabric_mrepair_sif_update_en_i17; + input fabric_mrepair_sif_update_en_i18; + input fabric_mrepair_sif_update_en_i19; + input fabric_mrepair_sif_update_en_i2; + input fabric_mrepair_sif_update_en_i20; + input fabric_mrepair_sif_update_en_i21; + input fabric_mrepair_sif_update_en_i22; + input fabric_mrepair_sif_update_en_i23; + input fabric_mrepair_sif_update_en_i24; + input fabric_mrepair_sif_update_en_i25; + input fabric_mrepair_sif_update_en_i26; + input fabric_mrepair_sif_update_en_i3; + input fabric_mrepair_sif_update_en_i4; + input fabric_mrepair_sif_update_en_i5; + input fabric_mrepair_sif_update_en_i6; + input fabric_mrepair_sif_update_en_i7; + input fabric_mrepair_sif_update_en_i8; + input fabric_mrepair_sif_update_en_i9; + output fabric_mrepair_sif_update_en_to_bist_o1; + output fabric_mrepair_sif_update_en_to_bist_o10; + output fabric_mrepair_sif_update_en_to_bist_o11; + output fabric_mrepair_sif_update_en_to_bist_o12; + output fabric_mrepair_sif_update_en_to_bist_o13; + output fabric_mrepair_sif_update_en_to_bist_o14; + output fabric_mrepair_sif_update_en_to_bist_o15; + output fabric_mrepair_sif_update_en_to_bist_o16; + output fabric_mrepair_sif_update_en_to_bist_o17; + output fabric_mrepair_sif_update_en_to_bist_o18; + output fabric_mrepair_sif_update_en_to_bist_o19; + output fabric_mrepair_sif_update_en_to_bist_o2; + output fabric_mrepair_sif_update_en_to_bist_o20; + output fabric_mrepair_sif_update_en_to_bist_o21; + output fabric_mrepair_sif_update_en_to_bist_o22; + output fabric_mrepair_sif_update_en_to_bist_o23; + output fabric_mrepair_sif_update_en_to_bist_o24; + output fabric_mrepair_sif_update_en_to_bist_o25; + output fabric_mrepair_sif_update_en_to_bist_o26; + output fabric_mrepair_sif_update_en_to_bist_o3; + output fabric_mrepair_sif_update_en_to_bist_o4; + output fabric_mrepair_sif_update_en_to_bist_o5; + output fabric_mrepair_sif_update_en_to_bist_o6; + output fabric_mrepair_sif_update_en_to_bist_o7; + output fabric_mrepair_sif_update_en_to_bist_o8; + output fabric_mrepair_sif_update_en_to_bist_o9; + output fabric_mrepair_system_data_from_mem_bist_o1; + output fabric_mrepair_system_data_from_mem_bist_o10; + output fabric_mrepair_system_data_from_mem_bist_o11; + output fabric_mrepair_system_data_from_mem_bist_o12; + output fabric_mrepair_system_data_from_mem_bist_o13; + output fabric_mrepair_system_data_from_mem_bist_o14; + output fabric_mrepair_system_data_from_mem_bist_o15; + output fabric_mrepair_system_data_from_mem_bist_o16; + output fabric_mrepair_system_data_from_mem_bist_o17; + output fabric_mrepair_system_data_from_mem_bist_o18; + output fabric_mrepair_system_data_from_mem_bist_o19; + output fabric_mrepair_system_data_from_mem_bist_o2; + output fabric_mrepair_system_data_from_mem_bist_o20; + output fabric_mrepair_system_data_from_mem_bist_o21; + output fabric_mrepair_system_data_from_mem_bist_o22; + output fabric_mrepair_system_data_from_mem_bist_o23; + output fabric_mrepair_system_data_from_mem_bist_o24; + output fabric_mrepair_system_data_from_mem_bist_o25; + output fabric_mrepair_system_data_from_mem_bist_o26; + output fabric_mrepair_system_data_from_mem_bist_o3; + output fabric_mrepair_system_data_from_mem_bist_o4; + output fabric_mrepair_system_data_from_mem_bist_o5; + output fabric_mrepair_system_data_from_mem_bist_o6; + output fabric_mrepair_system_data_from_mem_bist_o7; + output fabric_mrepair_system_data_from_mem_bist_o8; + output fabric_mrepair_system_data_from_mem_bist_o9; + input fabric_mrepair_system_data_to_mem_bist_i1; + input fabric_mrepair_system_data_to_mem_bist_i10; + input fabric_mrepair_system_data_to_mem_bist_i11; + input fabric_mrepair_system_data_to_mem_bist_i12; + input fabric_mrepair_system_data_to_mem_bist_i13; + input fabric_mrepair_system_data_to_mem_bist_i14; + input fabric_mrepair_system_data_to_mem_bist_i15; + input fabric_mrepair_system_data_to_mem_bist_i16; + input fabric_mrepair_system_data_to_mem_bist_i17; + input fabric_mrepair_system_data_to_mem_bist_i18; + input fabric_mrepair_system_data_to_mem_bist_i19; + input fabric_mrepair_system_data_to_mem_bist_i2; + input fabric_mrepair_system_data_to_mem_bist_i20; + input fabric_mrepair_system_data_to_mem_bist_i21; + input fabric_mrepair_system_data_to_mem_bist_i22; + input fabric_mrepair_system_data_to_mem_bist_i23; + input fabric_mrepair_system_data_to_mem_bist_i24; + input fabric_mrepair_system_data_to_mem_bist_i25; + input fabric_mrepair_system_data_to_mem_bist_i26; + input fabric_mrepair_system_data_to_mem_bist_i3; + input fabric_mrepair_system_data_to_mem_bist_i4; + input fabric_mrepair_system_data_to_mem_bist_i5; + input fabric_mrepair_system_data_to_mem_bist_i6; + input fabric_mrepair_system_data_to_mem_bist_i7; + input fabric_mrepair_system_data_to_mem_bist_i8; + input fabric_mrepair_system_data_to_mem_bist_i9; + output fabric_mrepair_system_dataready_o; + output fabric_mrepair_test_se_o; + input fabric_mrepair_tst_atpg_mrepair_i; + output fabric_mrepair_tst_gatedclock_o; + input fabric_otp_apb_addr_i1; + input fabric_otp_apb_addr_i10; + input fabric_otp_apb_addr_i11; + input fabric_otp_apb_addr_i12; + input fabric_otp_apb_addr_i13; + input fabric_otp_apb_addr_i14; + input fabric_otp_apb_addr_i15; + input fabric_otp_apb_addr_i16; + input fabric_otp_apb_addr_i17; + input fabric_otp_apb_addr_i18; + input fabric_otp_apb_addr_i19; + input fabric_otp_apb_addr_i2; + input fabric_otp_apb_addr_i20; + input fabric_otp_apb_addr_i21; + input fabric_otp_apb_addr_i22; + input fabric_otp_apb_addr_i23; + input fabric_otp_apb_addr_i24; + input fabric_otp_apb_addr_i25; + input fabric_otp_apb_addr_i26; + input fabric_otp_apb_addr_i27; + input fabric_otp_apb_addr_i28; + input fabric_otp_apb_addr_i29; + input fabric_otp_apb_addr_i3; + input fabric_otp_apb_addr_i30; + input fabric_otp_apb_addr_i31; + input fabric_otp_apb_addr_i32; + input fabric_otp_apb_addr_i4; + input fabric_otp_apb_addr_i5; + input fabric_otp_apb_addr_i6; + input fabric_otp_apb_addr_i7; + input fabric_otp_apb_addr_i8; + input fabric_otp_apb_addr_i9; + input fabric_otp_apb_enable_i; + output fabric_otp_apb_rdata_o1; + output fabric_otp_apb_rdata_o10; + output fabric_otp_apb_rdata_o11; + output fabric_otp_apb_rdata_o12; + output fabric_otp_apb_rdata_o13; + output fabric_otp_apb_rdata_o14; + output fabric_otp_apb_rdata_o15; + output fabric_otp_apb_rdata_o16; + output fabric_otp_apb_rdata_o17; + output fabric_otp_apb_rdata_o18; + output fabric_otp_apb_rdata_o19; + output fabric_otp_apb_rdata_o2; + output fabric_otp_apb_rdata_o20; + output fabric_otp_apb_rdata_o21; + output fabric_otp_apb_rdata_o22; + output fabric_otp_apb_rdata_o23; + output fabric_otp_apb_rdata_o24; + output fabric_otp_apb_rdata_o25; + output fabric_otp_apb_rdata_o26; + output fabric_otp_apb_rdata_o27; + output fabric_otp_apb_rdata_o28; + output fabric_otp_apb_rdata_o29; + output fabric_otp_apb_rdata_o3; + output fabric_otp_apb_rdata_o30; + output fabric_otp_apb_rdata_o31; + output fabric_otp_apb_rdata_o32; + output fabric_otp_apb_rdata_o4; + output fabric_otp_apb_rdata_o5; + output fabric_otp_apb_rdata_o6; + output fabric_otp_apb_rdata_o7; + output fabric_otp_apb_rdata_o8; + output fabric_otp_apb_rdata_o9; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input fabric_otp_apb_wdata_i1; + input fabric_otp_apb_wdata_i10; + input fabric_otp_apb_wdata_i11; + input fabric_otp_apb_wdata_i12; + input fabric_otp_apb_wdata_i13; + input fabric_otp_apb_wdata_i14; + input fabric_otp_apb_wdata_i15; + input fabric_otp_apb_wdata_i16; + input fabric_otp_apb_wdata_i17; + input fabric_otp_apb_wdata_i18; + input fabric_otp_apb_wdata_i19; + input fabric_otp_apb_wdata_i2; + input fabric_otp_apb_wdata_i20; + input fabric_otp_apb_wdata_i21; + input fabric_otp_apb_wdata_i22; + input fabric_otp_apb_wdata_i23; + input fabric_otp_apb_wdata_i24; + input fabric_otp_apb_wdata_i25; + input fabric_otp_apb_wdata_i26; + input fabric_otp_apb_wdata_i27; + input fabric_otp_apb_wdata_i28; + input fabric_otp_apb_wdata_i29; + input fabric_otp_apb_wdata_i3; + input fabric_otp_apb_wdata_i30; + input fabric_otp_apb_wdata_i31; + input fabric_otp_apb_wdata_i32; + input fabric_otp_apb_wdata_i4; + input fabric_otp_apb_wdata_i5; + input fabric_otp_apb_wdata_i6; + input fabric_otp_apb_wdata_i7; + input fabric_otp_apb_wdata_i8; + input fabric_otp_apb_wdata_i9; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_clk_i; + input fabric_otp_rst_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output fabric_otp_security_bist_fail1_o1; + output fabric_otp_security_bist_fail1_o2; + output fabric_otp_security_bist_fail1_o3; + output fabric_otp_security_bist_fail1_o4; + output fabric_otp_security_bist_fail1_o5; + output fabric_otp_security_bist_fail1_o6; + output fabric_otp_security_bist_fail1_o7; + output fabric_otp_security_bist_fail2_o1; + output fabric_otp_security_bist_fail2_o2; + output fabric_otp_security_bist_fail2_o3; + output fabric_otp_security_bist_fail2_o4; + output fabric_otp_security_bist_fail2_o5; + output fabric_otp_security_bist_fail2_o6; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input fabric_otp_security_scanin_i1; + input fabric_otp_security_scanin_i2; + input fabric_otp_security_scanin_i3; + input fabric_otp_security_scanin_i4; + output fabric_otp_security_scanout_o1; + output fabric_otp_security_scanout_o2; + output fabric_otp_security_scanout_o3; + output fabric_otp_security_scanout_o4; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input fabric_otp_user_add_i1; + input fabric_otp_user_add_i2; + input fabric_otp_user_add_i3; + input fabric_otp_user_add_i4; + input fabric_otp_user_add_i5; + input fabric_otp_user_add_i6; + input fabric_otp_user_add_i7; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output fabric_otp_user_bist1fail_o1; + output fabric_otp_user_bist1fail_o2; + output fabric_otp_user_bist1fail_o3; + output fabric_otp_user_bist1fail_o4; + output fabric_otp_user_bist1fail_o5; + output fabric_otp_user_bist1fail_o6; + output fabric_otp_user_bist1fail_o7; + output fabric_otp_user_bist1fail_o8; + output fabric_otp_user_bist2fail_o1; + output fabric_otp_user_bist2fail_o2; + output fabric_otp_user_bist2fail_o3; + output fabric_otp_user_bist2fail_o4; + output fabric_otp_user_bist2fail_o5; + output fabric_otp_user_bist2fail_o6; + output fabric_otp_user_bist2fail_o7; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clk_i; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input fabric_otp_user_din_i1; + input fabric_otp_user_din_i10; + input fabric_otp_user_din_i11; + input fabric_otp_user_din_i12; + input fabric_otp_user_din_i13; + input fabric_otp_user_din_i14; + input fabric_otp_user_din_i15; + input fabric_otp_user_din_i16; + input fabric_otp_user_din_i17; + input fabric_otp_user_din_i18; + input fabric_otp_user_din_i19; + input fabric_otp_user_din_i2; + input fabric_otp_user_din_i20; + input fabric_otp_user_din_i21; + input fabric_otp_user_din_i22; + input fabric_otp_user_din_i23; + input fabric_otp_user_din_i24; + input fabric_otp_user_din_i25; + input fabric_otp_user_din_i26; + input fabric_otp_user_din_i27; + input fabric_otp_user_din_i28; + input fabric_otp_user_din_i29; + input fabric_otp_user_din_i3; + input fabric_otp_user_din_i30; + input fabric_otp_user_din_i31; + input fabric_otp_user_din_i32; + input fabric_otp_user_din_i33; + input fabric_otp_user_din_i34; + input fabric_otp_user_din_i35; + input fabric_otp_user_din_i36; + input fabric_otp_user_din_i37; + input fabric_otp_user_din_i38; + input fabric_otp_user_din_i39; + input fabric_otp_user_din_i4; + input fabric_otp_user_din_i5; + input fabric_otp_user_din_i6; + input fabric_otp_user_din_i7; + input fabric_otp_user_din_i8; + input fabric_otp_user_din_i9; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output fabric_otp_user_dout_o1; + output fabric_otp_user_dout_o10; + output fabric_otp_user_dout_o11; + output fabric_otp_user_dout_o12; + output fabric_otp_user_dout_o13; + output fabric_otp_user_dout_o14; + output fabric_otp_user_dout_o15; + output fabric_otp_user_dout_o16; + output fabric_otp_user_dout_o17; + output fabric_otp_user_dout_o18; + output fabric_otp_user_dout_o19; + output fabric_otp_user_dout_o2; + output fabric_otp_user_dout_o20; + output fabric_otp_user_dout_o21; + output fabric_otp_user_dout_o22; + output fabric_otp_user_dout_o23; + output fabric_otp_user_dout_o24; + output fabric_otp_user_dout_o25; + output fabric_otp_user_dout_o26; + output fabric_otp_user_dout_o27; + output fabric_otp_user_dout_o28; + output fabric_otp_user_dout_o29; + output fabric_otp_user_dout_o3; + output fabric_otp_user_dout_o30; + output fabric_otp_user_dout_o31; + output fabric_otp_user_dout_o32; + output fabric_otp_user_dout_o33; + output fabric_otp_user_dout_o34; + output fabric_otp_user_dout_o35; + output fabric_otp_user_dout_o36; + output fabric_otp_user_dout_o37; + output fabric_otp_user_dout_o38; + output fabric_otp_user_dout_o39; + output fabric_otp_user_dout_o4; + output fabric_otp_user_dout_o40; + output fabric_otp_user_dout_o41; + output fabric_otp_user_dout_o5; + output fabric_otp_user_dout_o6; + output fabric_otp_user_dout_o7; + output fabric_otp_user_dout_o8; + output fabric_otp_user_dout_o9; + input fabric_otp_user_eccbypass_i; + output fabric_otp_user_flagstate_o1; + output fabric_otp_user_flagstate_o2; + output fabric_otp_user_flagstate_o3; + output fabric_otp_user_flagstate_o4; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input fabric_otp_user_prgwidth_i1; + input fabric_otp_user_prgwidth_i2; + input fabric_otp_user_prgwidth_i3; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output fabric_otp_user_startword_o1; + output fabric_otp_user_startword_o10; + output fabric_otp_user_startword_o11; + output fabric_otp_user_startword_o12; + output fabric_otp_user_startword_o13; + output fabric_otp_user_startword_o14; + output fabric_otp_user_startword_o15; + output fabric_otp_user_startword_o16; + output fabric_otp_user_startword_o2; + output fabric_otp_user_startword_o3; + output fabric_otp_user_startword_o4; + output fabric_otp_user_startword_o5; + output fabric_otp_user_startword_o6; + output fabric_otp_user_startword_o7; + output fabric_otp_user_startword_o8; + output fabric_otp_user_startword_o9; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input fabric_otp_user_tst_scanin_i1; + input fabric_otp_user_tst_scanin_i2; + input fabric_otp_user_tst_scanin_i3; + input fabric_otp_user_tst_scanin_i4; + input fabric_otp_user_tst_scanin_i5; + output fabric_otp_user_tst_scanout_o1; + output fabric_otp_user_tst_scanout_o2; + output fabric_otp_user_tst_scanout_o3; + output fabric_otp_user_tst_scanout_o4; + output fabric_otp_user_tst_scanout_o5; + output fabric_otp_user_wlromout_o1; + output fabric_otp_user_wlromout_o10; + output fabric_otp_user_wlromout_o2; + output fabric_otp_user_wlromout_o3; + output fabric_otp_user_wlromout_o4; + output fabric_otp_user_wlromout_o5; + output fabric_otp_user_wlromout_o6; + output fabric_otp_user_wlromout_o7; + output fabric_otp_user_wlromout_o8; + output fabric_otp_user_wlromout_o9; + input fabric_otp_user_wordlock_i; + input fabric_parusr_clk_i; + input fabric_parusr_cs_i; + input fabric_parusr_data_i1; + input fabric_parusr_data_i10; + input fabric_parusr_data_i11; + input fabric_parusr_data_i12; + input fabric_parusr_data_i13; + input fabric_parusr_data_i14; + input fabric_parusr_data_i15; + input fabric_parusr_data_i16; + input fabric_parusr_data_i2; + input fabric_parusr_data_i3; + input fabric_parusr_data_i4; + input fabric_parusr_data_i5; + input fabric_parusr_data_i6; + input fabric_parusr_data_i7; + input fabric_parusr_data_i8; + input fabric_parusr_data_i9; + output fabric_parusr_data_o1; + output fabric_parusr_data_o10; + output fabric_parusr_data_o11; + output fabric_parusr_data_o12; + output fabric_parusr_data_o13; + output fabric_parusr_data_o14; + output fabric_parusr_data_o15; + output fabric_parusr_data_o16; + output fabric_parusr_data_o2; + output fabric_parusr_data_o3; + output fabric_parusr_data_o4; + output fabric_parusr_data_o5; + output fabric_parusr_data_o6; + output fabric_parusr_data_o7; + output fabric_parusr_data_o8; + output fabric_parusr_data_o9; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input fabric_parusr_type_i1; + input fabric_parusr_type_i2; + input fabric_spare_i1; + input fabric_spare_i10; + input fabric_spare_i100; + input fabric_spare_i101; + input fabric_spare_i102; + input fabric_spare_i103; + input fabric_spare_i104; + input fabric_spare_i105; + input fabric_spare_i106; + input fabric_spare_i107; + input fabric_spare_i108; + input fabric_spare_i109; + input fabric_spare_i11; + input fabric_spare_i110; + input fabric_spare_i111; + input fabric_spare_i112; + input fabric_spare_i113; + input fabric_spare_i114; + input fabric_spare_i115; + input fabric_spare_i116; + input fabric_spare_i117; + input fabric_spare_i118; + input fabric_spare_i119; + input fabric_spare_i12; + input fabric_spare_i120; + input fabric_spare_i121; + input fabric_spare_i122; + input fabric_spare_i123; + input fabric_spare_i124; + input fabric_spare_i125; + input fabric_spare_i126; + input fabric_spare_i127; + input fabric_spare_i128; + input fabric_spare_i13; + input fabric_spare_i14; + input fabric_spare_i15; + input fabric_spare_i16; + input fabric_spare_i17; + input fabric_spare_i18; + input fabric_spare_i19; + input fabric_spare_i2; + input fabric_spare_i20; + input fabric_spare_i21; + input fabric_spare_i22; + input fabric_spare_i23; + input fabric_spare_i24; + input fabric_spare_i25; + input fabric_spare_i26; + input fabric_spare_i27; + input fabric_spare_i28; + input fabric_spare_i29; + input fabric_spare_i3; + input fabric_spare_i30; + input fabric_spare_i31; + input fabric_spare_i32; + input fabric_spare_i33; + input fabric_spare_i34; + input fabric_spare_i35; + input fabric_spare_i36; + input fabric_spare_i37; + input fabric_spare_i38; + input fabric_spare_i39; + input fabric_spare_i4; + input fabric_spare_i40; + input fabric_spare_i41; + input fabric_spare_i42; + input fabric_spare_i43; + input fabric_spare_i44; + input fabric_spare_i45; + input fabric_spare_i46; + input fabric_spare_i47; + input fabric_spare_i48; + input fabric_spare_i49; + input fabric_spare_i5; + input fabric_spare_i50; + input fabric_spare_i51; + input fabric_spare_i52; + input fabric_spare_i53; + input fabric_spare_i54; + input fabric_spare_i55; + input fabric_spare_i56; + input fabric_spare_i57; + input fabric_spare_i58; + input fabric_spare_i59; + input fabric_spare_i6; + input fabric_spare_i60; + input fabric_spare_i61; + input fabric_spare_i62; + input fabric_spare_i63; + input fabric_spare_i64; + input fabric_spare_i65; + input fabric_spare_i66; + input fabric_spare_i67; + input fabric_spare_i68; + input fabric_spare_i69; + input fabric_spare_i7; + input fabric_spare_i70; + input fabric_spare_i71; + input fabric_spare_i72; + input fabric_spare_i73; + input fabric_spare_i74; + input fabric_spare_i75; + input fabric_spare_i76; + input fabric_spare_i77; + input fabric_spare_i78; + input fabric_spare_i79; + input fabric_spare_i8; + input fabric_spare_i80; + input fabric_spare_i81; + input fabric_spare_i82; + input fabric_spare_i83; + input fabric_spare_i84; + input fabric_spare_i85; + input fabric_spare_i86; + input fabric_spare_i87; + input fabric_spare_i88; + input fabric_spare_i89; + input fabric_spare_i9; + input fabric_spare_i90; + input fabric_spare_i91; + input fabric_spare_i92; + input fabric_spare_i93; + input fabric_spare_i94; + input fabric_spare_i95; + input fabric_spare_i96; + input fabric_spare_i97; + input fabric_spare_i98; + input fabric_spare_i99; + output fabric_spare_o1; + output fabric_spare_o10; + output fabric_spare_o100; + output fabric_spare_o101; + output fabric_spare_o102; + output fabric_spare_o103; + output fabric_spare_o104; + output fabric_spare_o105; + output fabric_spare_o106; + output fabric_spare_o107; + output fabric_spare_o108; + output fabric_spare_o109; + output fabric_spare_o11; + output fabric_spare_o110; + output fabric_spare_o111; + output fabric_spare_o112; + output fabric_spare_o113; + output fabric_spare_o114; + output fabric_spare_o115; + output fabric_spare_o116; + output fabric_spare_o117; + output fabric_spare_o118; + output fabric_spare_o119; + output fabric_spare_o12; + output fabric_spare_o120; + output fabric_spare_o121; + output fabric_spare_o122; + output fabric_spare_o123; + output fabric_spare_o124; + output fabric_spare_o125; + output fabric_spare_o126; + output fabric_spare_o127; + output fabric_spare_o128; + output fabric_spare_o13; + output fabric_spare_o14; + output fabric_spare_o15; + output fabric_spare_o16; + output fabric_spare_o17; + output fabric_spare_o18; + output fabric_spare_o19; + output fabric_spare_o2; + output fabric_spare_o20; + output fabric_spare_o21; + output fabric_spare_o22; + output fabric_spare_o23; + output fabric_spare_o24; + output fabric_spare_o25; + output fabric_spare_o26; + output fabric_spare_o27; + output fabric_spare_o28; + output fabric_spare_o29; + output fabric_spare_o3; + output fabric_spare_o30; + output fabric_spare_o31; + output fabric_spare_o32; + output fabric_spare_o33; + output fabric_spare_o34; + output fabric_spare_o35; + output fabric_spare_o36; + output fabric_spare_o37; + output fabric_spare_o38; + output fabric_spare_o39; + output fabric_spare_o4; + output fabric_spare_o40; + output fabric_spare_o41; + output fabric_spare_o42; + output fabric_spare_o43; + output fabric_spare_o44; + output fabric_spare_o45; + output fabric_spare_o46; + output fabric_spare_o47; + output fabric_spare_o48; + output fabric_spare_o49; + output fabric_spare_o5; + output fabric_spare_o50; + output fabric_spare_o51; + output fabric_spare_o52; + output fabric_spare_o53; + output fabric_spare_o54; + output fabric_spare_o55; + output fabric_spare_o56; + output fabric_spare_o57; + output fabric_spare_o58; + output fabric_spare_o59; + output fabric_spare_o6; + output fabric_spare_o60; + output fabric_spare_o61; + output fabric_spare_o62; + output fabric_spare_o63; + output fabric_spare_o64; + output fabric_spare_o65; + output fabric_spare_o66; + output fabric_spare_o67; + output fabric_spare_o68; + output fabric_spare_o69; + output fabric_spare_o7; + output fabric_spare_o70; + output fabric_spare_o71; + output fabric_spare_o72; + output fabric_spare_o73; + output fabric_spare_o74; + output fabric_spare_o75; + output fabric_spare_o76; + output fabric_spare_o77; + output fabric_spare_o78; + output fabric_spare_o79; + output fabric_spare_o8; + output fabric_spare_o80; + output fabric_spare_o81; + output fabric_spare_o82; + output fabric_spare_o83; + output fabric_spare_o84; + output fabric_spare_o85; + output fabric_spare_o86; + output fabric_spare_o87; + output fabric_spare_o88; + output fabric_spare_o89; + output fabric_spare_o9; + output fabric_spare_o90; + output fabric_spare_o91; + output fabric_spare_o92; + output fabric_spare_o93; + output fabric_spare_o94; + output fabric_spare_o95; + output fabric_spare_o96; + output fabric_spare_o97; + output fabric_spare_o98; + output fabric_spare_o99; + input fabric_spi_arst_tmr_n_i1; + input fabric_spi_arst_tmr_n_i2; + input fabric_spi_arst_tmr_n_i3; + input fabric_spi_arst_tmr_n_i4; + input fabric_spi_arst_tmr_n_i5; + input fabric_spi_arst_tmr_n_i6; + input fabric_spi_arst_tmr_n_i7; + input fabric_spi_arst_tmr_n_i8; + input fabric_spi_arst_tmr_n_i9; + output fabric_spi_bsm_release_o1; + output fabric_spi_bsm_release_o2; + output fabric_spi_bsm_release_o3; + output fabric_spi_busy_o1; + output fabric_spi_busy_o2; + output fabric_spi_busy_o3; + input fabric_spi_clk_i0; + input fabric_spi_clk_i1; + input fabric_spi_clk_i2; + input fabric_spi_cmd_bytes_i1; + input fabric_spi_cmd_bytes_i2; + input fabric_spi_cmd_bytes_i3; + input fabric_spi_cmd_bytes_i4; + input fabric_spi_cmd_bytes_i5; + input fabric_spi_cmd_bytes_i6; + output fabric_spi_cmd_full_o1; + output fabric_spi_cmd_full_o2; + output fabric_spi_cmd_full_o3; + input fabric_spi_cmd_mode_i1; + input fabric_spi_cmd_mode_i2; + input fabric_spi_cmd_mode_i3; + input fabric_spi_cmd_mode_i4; + input fabric_spi_cmd_mode_i5; + input fabric_spi_cmd_mode_i6; + input fabric_spi_cmd_push_i1; + input fabric_spi_cmd_push_i2; + input fabric_spi_cmd_push_i3; + input fabric_spi_cmd_type_i1; + input fabric_spi_cmd_type_i2; + input fabric_spi_cmd_type_i3; + input fabric_spi_cmd_type_i4; + input fabric_spi_cmd_type_i5; + input fabric_spi_cmd_type_i6; + input fabric_spi_cpha_i1; + input fabric_spi_cpha_i2; + input fabric_spi_cpha_i3; + input fabric_spi_cpol_i1; + input fabric_spi_cpol_i2; + input fabric_spi_cpol_i3; + input fabric_spi_cs_holdtime_i1; + input fabric_spi_cs_holdtime_i10; + input fabric_spi_cs_holdtime_i11; + input fabric_spi_cs_holdtime_i12; + input fabric_spi_cs_holdtime_i2; + input fabric_spi_cs_holdtime_i3; + input fabric_spi_cs_holdtime_i4; + input fabric_spi_cs_holdtime_i5; + input fabric_spi_cs_holdtime_i6; + input fabric_spi_cs_holdtime_i7; + input fabric_spi_cs_holdtime_i8; + input fabric_spi_cs_holdtime_i9; + input fabric_spi_cs_offtime_i1; + input fabric_spi_cs_offtime_i10; + input fabric_spi_cs_offtime_i11; + input fabric_spi_cs_offtime_i12; + input fabric_spi_cs_offtime_i2; + input fabric_spi_cs_offtime_i3; + input fabric_spi_cs_offtime_i4; + input fabric_spi_cs_offtime_i5; + input fabric_spi_cs_offtime_i6; + input fabric_spi_cs_offtime_i7; + input fabric_spi_cs_offtime_i8; + input fabric_spi_cs_offtime_i9; + input fabric_spi_cs_setuptime_i1; + input fabric_spi_cs_setuptime_i10; + input fabric_spi_cs_setuptime_i11; + input fabric_spi_cs_setuptime_i12; + input fabric_spi_cs_setuptime_i2; + input fabric_spi_cs_setuptime_i3; + input fabric_spi_cs_setuptime_i4; + input fabric_spi_cs_setuptime_i5; + input fabric_spi_cs_setuptime_i6; + input fabric_spi_cs_setuptime_i7; + input fabric_spi_cs_setuptime_i8; + input fabric_spi_cs_setuptime_i9; + input fabric_spi_data_in_unlimited_i1; + input fabric_spi_data_in_unlimited_i2; + input fabric_spi_data_in_unlimited_i3; + input fabric_spi_enable_i1; + input fabric_spi_enable_i2; + input fabric_spi_enable_i3; + output fabric_spi_error_endianness_o1; + output fabric_spi_error_endianness_o2; + output fabric_spi_error_endianness_o3; + output fabric_spi_error_loopback_o1; + output fabric_spi_error_loopback_o2; + output fabric_spi_error_loopback_o3; + output fabric_spi_error_mode_o1; + output fabric_spi_error_mode_o2; + output fabric_spi_error_mode_o3; + output fabric_spi_error_sel_o1; + output fabric_spi_error_sel_o2; + output fabric_spi_error_sel_o3; + input fabric_spi_fifo_arst_tmr_n_i1; + input fabric_spi_fifo_arst_tmr_n_i2; + input fabric_spi_fifo_arst_tmr_n_i3; + input fabric_spi_fifo_arst_tmr_n_i4; + input fabric_spi_fifo_arst_tmr_n_i5; + input fabric_spi_fifo_arst_tmr_n_i6; + input fabric_spi_fifo_arst_tmr_n_i7; + input fabric_spi_fifo_arst_tmr_n_i8; + input fabric_spi_fifo_arst_tmr_n_i9; + output fabric_spi_init_done_o1; + output fabric_spi_init_done_o2; + output fabric_spi_init_done_o3; + input fabric_spi_legacy_enable_i1; + input fabric_spi_legacy_enable_i2; + input fabric_spi_legacy_enable_i3; + input fabric_spi_legacy_master_i1; + input fabric_spi_legacy_master_i2; + input fabric_spi_legacy_master_i3; + input fabric_spi_loopback_i1; + input fabric_spi_loopback_i2; + input fabric_spi_loopback_i3; + input fabric_spi_lsb_first_i1; + input fabric_spi_lsb_first_i2; + input fabric_spi_lsb_first_i3; + output fabric_spi_miso_data_inv_o1; + output fabric_spi_miso_data_inv_o2; + output fabric_spi_miso_data_inv_o3; + output fabric_spi_miso_data_o1; + output fabric_spi_miso_data_o10; + output fabric_spi_miso_data_o11; + output fabric_spi_miso_data_o12; + output fabric_spi_miso_data_o13; + output fabric_spi_miso_data_o14; + output fabric_spi_miso_data_o15; + output fabric_spi_miso_data_o16; + output fabric_spi_miso_data_o17; + output fabric_spi_miso_data_o18; + output fabric_spi_miso_data_o19; + output fabric_spi_miso_data_o2; + output fabric_spi_miso_data_o20; + output fabric_spi_miso_data_o21; + output fabric_spi_miso_data_o22; + output fabric_spi_miso_data_o23; + output fabric_spi_miso_data_o24; + output fabric_spi_miso_data_o3; + output fabric_spi_miso_data_o4; + output fabric_spi_miso_data_o5; + output fabric_spi_miso_data_o6; + output fabric_spi_miso_data_o7; + output fabric_spi_miso_data_o8; + output fabric_spi_miso_data_o9; + output fabric_spi_miso_empty_o1; + output fabric_spi_miso_empty_o2; + output fabric_spi_miso_empty_o3; + input fabric_spi_miso_pop_i1; + input fabric_spi_miso_pop_i2; + input fabric_spi_miso_pop_i3; + input fabric_spi_mosi_data_i1; + input fabric_spi_mosi_data_i10; + input fabric_spi_mosi_data_i11; + input fabric_spi_mosi_data_i12; + input fabric_spi_mosi_data_i13; + input fabric_spi_mosi_data_i14; + input fabric_spi_mosi_data_i15; + input fabric_spi_mosi_data_i16; + input fabric_spi_mosi_data_i17; + input fabric_spi_mosi_data_i18; + input fabric_spi_mosi_data_i19; + input fabric_spi_mosi_data_i2; + input fabric_spi_mosi_data_i20; + input fabric_spi_mosi_data_i21; + input fabric_spi_mosi_data_i22; + input fabric_spi_mosi_data_i23; + input fabric_spi_mosi_data_i24; + input fabric_spi_mosi_data_i3; + input fabric_spi_mosi_data_i4; + input fabric_spi_mosi_data_i5; + input fabric_spi_mosi_data_i6; + input fabric_spi_mosi_data_i7; + input fabric_spi_mosi_data_i8; + input fabric_spi_mosi_data_i9; + input fabric_spi_mosi_data_inv_i1; + input fabric_spi_mosi_data_inv_i2; + input fabric_spi_mosi_data_inv_i3; + output fabric_spi_mosi_full_o1; + output fabric_spi_mosi_full_o2; + output fabric_spi_mosi_full_o3; + input fabric_spi_mosi_push_i1; + input fabric_spi_mosi_push_i2; + input fabric_spi_mosi_push_i3; + input fabric_spi_needed_i1; + input fabric_spi_needed_i2; + input fabric_spi_needed_i3; + input fabric_spi_powerdown_cycle_i1; + input fabric_spi_powerdown_cycle_i10; + input fabric_spi_powerdown_cycle_i11; + input fabric_spi_powerdown_cycle_i12; + input fabric_spi_powerdown_cycle_i13; + input fabric_spi_powerdown_cycle_i14; + input fabric_spi_powerdown_cycle_i15; + input fabric_spi_powerdown_cycle_i16; + input fabric_spi_powerdown_cycle_i17; + input fabric_spi_powerdown_cycle_i18; + input fabric_spi_powerdown_cycle_i19; + input fabric_spi_powerdown_cycle_i2; + input fabric_spi_powerdown_cycle_i20; + input fabric_spi_powerdown_cycle_i21; + input fabric_spi_powerdown_cycle_i22; + input fabric_spi_powerdown_cycle_i23; + input fabric_spi_powerdown_cycle_i24; + input fabric_spi_powerdown_cycle_i25; + input fabric_spi_powerdown_cycle_i26; + input fabric_spi_powerdown_cycle_i27; + input fabric_spi_powerdown_cycle_i28; + input fabric_spi_powerdown_cycle_i29; + input fabric_spi_powerdown_cycle_i3; + input fabric_spi_powerdown_cycle_i30; + input fabric_spi_powerdown_cycle_i31; + input fabric_spi_powerdown_cycle_i32; + input fabric_spi_powerdown_cycle_i33; + input fabric_spi_powerdown_cycle_i34; + input fabric_spi_powerdown_cycle_i35; + input fabric_spi_powerdown_cycle_i36; + input fabric_spi_powerdown_cycle_i37; + input fabric_spi_powerdown_cycle_i38; + input fabric_spi_powerdown_cycle_i39; + input fabric_spi_powerdown_cycle_i4; + input fabric_spi_powerdown_cycle_i40; + input fabric_spi_powerdown_cycle_i41; + input fabric_spi_powerdown_cycle_i42; + input fabric_spi_powerdown_cycle_i43; + input fabric_spi_powerdown_cycle_i44; + input fabric_spi_powerdown_cycle_i45; + input fabric_spi_powerdown_cycle_i46; + input fabric_spi_powerdown_cycle_i47; + input fabric_spi_powerdown_cycle_i48; + input fabric_spi_powerdown_cycle_i5; + input fabric_spi_powerdown_cycle_i6; + input fabric_spi_powerdown_cycle_i7; + input fabric_spi_powerdown_cycle_i8; + input fabric_spi_powerdown_cycle_i9; + input fabric_spi_powerup_cycle_i1; + input fabric_spi_powerup_cycle_i10; + input fabric_spi_powerup_cycle_i11; + input fabric_spi_powerup_cycle_i12; + input fabric_spi_powerup_cycle_i13; + input fabric_spi_powerup_cycle_i14; + input fabric_spi_powerup_cycle_i15; + input fabric_spi_powerup_cycle_i16; + input fabric_spi_powerup_cycle_i17; + input fabric_spi_powerup_cycle_i18; + input fabric_spi_powerup_cycle_i19; + input fabric_spi_powerup_cycle_i2; + input fabric_spi_powerup_cycle_i20; + input fabric_spi_powerup_cycle_i21; + input fabric_spi_powerup_cycle_i22; + input fabric_spi_powerup_cycle_i23; + input fabric_spi_powerup_cycle_i24; + input fabric_spi_powerup_cycle_i25; + input fabric_spi_powerup_cycle_i26; + input fabric_spi_powerup_cycle_i27; + input fabric_spi_powerup_cycle_i28; + input fabric_spi_powerup_cycle_i29; + input fabric_spi_powerup_cycle_i3; + input fabric_spi_powerup_cycle_i30; + input fabric_spi_powerup_cycle_i31; + input fabric_spi_powerup_cycle_i32; + input fabric_spi_powerup_cycle_i33; + input fabric_spi_powerup_cycle_i34; + input fabric_spi_powerup_cycle_i35; + input fabric_spi_powerup_cycle_i36; + input fabric_spi_powerup_cycle_i37; + input fabric_spi_powerup_cycle_i38; + input fabric_spi_powerup_cycle_i39; + input fabric_spi_powerup_cycle_i4; + input fabric_spi_powerup_cycle_i40; + input fabric_spi_powerup_cycle_i41; + input fabric_spi_powerup_cycle_i42; + input fabric_spi_powerup_cycle_i43; + input fabric_spi_powerup_cycle_i44; + input fabric_spi_powerup_cycle_i45; + input fabric_spi_powerup_cycle_i46; + input fabric_spi_powerup_cycle_i47; + input fabric_spi_powerup_cycle_i48; + input fabric_spi_powerup_cycle_i5; + input fabric_spi_powerup_cycle_i6; + input fabric_spi_powerup_cycle_i7; + input fabric_spi_powerup_cycle_i8; + input fabric_spi_powerup_cycle_i9; + input fabric_spi_rst_n_i1; + input fabric_spi_rst_n_i2; + input fabric_spi_rst_n_i3; + input fabric_spi_sck_i0; + input fabric_spi_sck_i1; + input fabric_spi_sck_i2; + input fabric_spi_vcc_enable_i1; + input fabric_spi_vcc_enable_i2; + input fabric_spi_vcc_enable_i3; + output fabric_spi_vcc_used_o1; + output fabric_spi_vcc_used_o2; + output fabric_spi_vcc_used_o3; + input fabric_spw0_apb_slv_paddr_i1; + input fabric_spw0_apb_slv_paddr_i2; + input fabric_spw0_apb_slv_paddr_i3; + input fabric_spw0_apb_slv_paddr_i4; + input fabric_spw0_apb_slv_paddr_i5; + input fabric_spw0_apb_slv_penable_i; + output fabric_spw0_apb_slv_prdata_o1; + output fabric_spw0_apb_slv_prdata_o10; + output fabric_spw0_apb_slv_prdata_o11; + output fabric_spw0_apb_slv_prdata_o12; + output fabric_spw0_apb_slv_prdata_o13; + output fabric_spw0_apb_slv_prdata_o14; + output fabric_spw0_apb_slv_prdata_o15; + output fabric_spw0_apb_slv_prdata_o16; + output fabric_spw0_apb_slv_prdata_o17; + output fabric_spw0_apb_slv_prdata_o18; + output fabric_spw0_apb_slv_prdata_o19; + output fabric_spw0_apb_slv_prdata_o2; + output fabric_spw0_apb_slv_prdata_o20; + output fabric_spw0_apb_slv_prdata_o21; + output fabric_spw0_apb_slv_prdata_o22; + output fabric_spw0_apb_slv_prdata_o23; + output fabric_spw0_apb_slv_prdata_o24; + output fabric_spw0_apb_slv_prdata_o25; + output fabric_spw0_apb_slv_prdata_o26; + output fabric_spw0_apb_slv_prdata_o27; + output fabric_spw0_apb_slv_prdata_o28; + output fabric_spw0_apb_slv_prdata_o29; + output fabric_spw0_apb_slv_prdata_o3; + output fabric_spw0_apb_slv_prdata_o30; + output fabric_spw0_apb_slv_prdata_o31; + output fabric_spw0_apb_slv_prdata_o4; + output fabric_spw0_apb_slv_prdata_o5; + output fabric_spw0_apb_slv_prdata_o6; + output fabric_spw0_apb_slv_prdata_o7; + output fabric_spw0_apb_slv_prdata_o8; + output fabric_spw0_apb_slv_prdata_o9; + output fabric_spw0_apb_slv_pready_o; + input fabric_spw0_apb_slv_psel_i; + output fabric_spw0_apb_slv_pslverr_o; + input fabric_spw0_apb_slv_pwdata_i1; + input fabric_spw0_apb_slv_pwdata_i10; + input fabric_spw0_apb_slv_pwdata_i11; + input fabric_spw0_apb_slv_pwdata_i12; + input fabric_spw0_apb_slv_pwdata_i13; + input fabric_spw0_apb_slv_pwdata_i14; + input fabric_spw0_apb_slv_pwdata_i15; + input fabric_spw0_apb_slv_pwdata_i16; + input fabric_spw0_apb_slv_pwdata_i17; + input fabric_spw0_apb_slv_pwdata_i18; + input fabric_spw0_apb_slv_pwdata_i19; + input fabric_spw0_apb_slv_pwdata_i2; + input fabric_spw0_apb_slv_pwdata_i20; + input fabric_spw0_apb_slv_pwdata_i21; + input fabric_spw0_apb_slv_pwdata_i22; + input fabric_spw0_apb_slv_pwdata_i23; + input fabric_spw0_apb_slv_pwdata_i24; + input fabric_spw0_apb_slv_pwdata_i25; + input fabric_spw0_apb_slv_pwdata_i26; + input fabric_spw0_apb_slv_pwdata_i27; + input fabric_spw0_apb_slv_pwdata_i28; + input fabric_spw0_apb_slv_pwdata_i29; + input fabric_spw0_apb_slv_pwdata_i3; + input fabric_spw0_apb_slv_pwdata_i30; + input fabric_spw0_apb_slv_pwdata_i31; + input fabric_spw0_apb_slv_pwdata_i4; + input fabric_spw0_apb_slv_pwdata_i5; + input fabric_spw0_apb_slv_pwdata_i6; + input fabric_spw0_apb_slv_pwdata_i7; + input fabric_spw0_apb_slv_pwdata_i8; + input fabric_spw0_apb_slv_pwdata_i9; + input fabric_spw0_apb_slv_pwrite_i; + input fabric_spw0_clk_i; + input fabric_spw0_clk_tx_i; + input fabric_spw0_rst_n_i; + output fabric_spw0_rx_fifo_data_o1; + output fabric_spw0_rx_fifo_data_o2; + output fabric_spw0_rx_fifo_data_o3; + output fabric_spw0_rx_fifo_data_o4; + output fabric_spw0_rx_fifo_data_o5; + output fabric_spw0_rx_fifo_data_o6; + output fabric_spw0_rx_fifo_data_o7; + output fabric_spw0_rx_fifo_data_o8; + output fabric_spw0_rx_fifo_data_o9; + output fabric_spw0_rx_fifo_empty_o; + input fabric_spw0_rx_fifo_read_i; + input fabric_spw0_tick_ctm_i; + output fabric_spw0_tick_ctm_o; + input fabric_spw0_tx_fifo_data_i1; + input fabric_spw0_tx_fifo_data_i2; + input fabric_spw0_tx_fifo_data_i3; + input fabric_spw0_tx_fifo_data_i4; + input fabric_spw0_tx_fifo_data_i5; + input fabric_spw0_tx_fifo_data_i6; + input fabric_spw0_tx_fifo_data_i7; + input fabric_spw0_tx_fifo_data_i8; + input fabric_spw0_tx_fifo_data_i9; + output fabric_spw0_tx_fifo_full_o; + input fabric_spw0_tx_fifo_write_i; + output fabric_spw0_user_shared_o; + input fabric_spw1_apb_slv_paddr_i1; + input fabric_spw1_apb_slv_paddr_i2; + input fabric_spw1_apb_slv_paddr_i3; + input fabric_spw1_apb_slv_paddr_i4; + input fabric_spw1_apb_slv_paddr_i5; + input fabric_spw1_apb_slv_penable_i; + output fabric_spw1_apb_slv_prdata_o1; + output fabric_spw1_apb_slv_prdata_o10; + output fabric_spw1_apb_slv_prdata_o11; + output fabric_spw1_apb_slv_prdata_o12; + output fabric_spw1_apb_slv_prdata_o13; + output fabric_spw1_apb_slv_prdata_o14; + output fabric_spw1_apb_slv_prdata_o15; + output fabric_spw1_apb_slv_prdata_o16; + output fabric_spw1_apb_slv_prdata_o17; + output fabric_spw1_apb_slv_prdata_o18; + output fabric_spw1_apb_slv_prdata_o19; + output fabric_spw1_apb_slv_prdata_o2; + output fabric_spw1_apb_slv_prdata_o20; + output fabric_spw1_apb_slv_prdata_o21; + output fabric_spw1_apb_slv_prdata_o22; + output fabric_spw1_apb_slv_prdata_o23; + output fabric_spw1_apb_slv_prdata_o24; + output fabric_spw1_apb_slv_prdata_o25; + output fabric_spw1_apb_slv_prdata_o26; + output fabric_spw1_apb_slv_prdata_o27; + output fabric_spw1_apb_slv_prdata_o28; + output fabric_spw1_apb_slv_prdata_o29; + output fabric_spw1_apb_slv_prdata_o3; + output fabric_spw1_apb_slv_prdata_o30; + output fabric_spw1_apb_slv_prdata_o31; + output fabric_spw1_apb_slv_prdata_o4; + output fabric_spw1_apb_slv_prdata_o5; + output fabric_spw1_apb_slv_prdata_o6; + output fabric_spw1_apb_slv_prdata_o7; + output fabric_spw1_apb_slv_prdata_o8; + output fabric_spw1_apb_slv_prdata_o9; + output fabric_spw1_apb_slv_pready_o; + input fabric_spw1_apb_slv_psel_i; + output fabric_spw1_apb_slv_pslverr_o; + input fabric_spw1_apb_slv_pwdata_i1; + input fabric_spw1_apb_slv_pwdata_i10; + input fabric_spw1_apb_slv_pwdata_i11; + input fabric_spw1_apb_slv_pwdata_i12; + input fabric_spw1_apb_slv_pwdata_i13; + input fabric_spw1_apb_slv_pwdata_i14; + input fabric_spw1_apb_slv_pwdata_i15; + input fabric_spw1_apb_slv_pwdata_i16; + input fabric_spw1_apb_slv_pwdata_i17; + input fabric_spw1_apb_slv_pwdata_i18; + input fabric_spw1_apb_slv_pwdata_i19; + input fabric_spw1_apb_slv_pwdata_i2; + input fabric_spw1_apb_slv_pwdata_i20; + input fabric_spw1_apb_slv_pwdata_i21; + input fabric_spw1_apb_slv_pwdata_i22; + input fabric_spw1_apb_slv_pwdata_i23; + input fabric_spw1_apb_slv_pwdata_i24; + input fabric_spw1_apb_slv_pwdata_i25; + input fabric_spw1_apb_slv_pwdata_i26; + input fabric_spw1_apb_slv_pwdata_i27; + input fabric_spw1_apb_slv_pwdata_i28; + input fabric_spw1_apb_slv_pwdata_i29; + input fabric_spw1_apb_slv_pwdata_i3; + input fabric_spw1_apb_slv_pwdata_i30; + input fabric_spw1_apb_slv_pwdata_i31; + input fabric_spw1_apb_slv_pwdata_i4; + input fabric_spw1_apb_slv_pwdata_i5; + input fabric_spw1_apb_slv_pwdata_i6; + input fabric_spw1_apb_slv_pwdata_i7; + input fabric_spw1_apb_slv_pwdata_i8; + input fabric_spw1_apb_slv_pwdata_i9; + input fabric_spw1_apb_slv_pwrite_i; + input fabric_spw1_clk_i; + input fabric_spw1_clk_tx_i; + input fabric_spw1_rst_n_i; + output fabric_spw1_rx_fifo_data_o1; + output fabric_spw1_rx_fifo_data_o2; + output fabric_spw1_rx_fifo_data_o3; + output fabric_spw1_rx_fifo_data_o4; + output fabric_spw1_rx_fifo_data_o5; + output fabric_spw1_rx_fifo_data_o6; + output fabric_spw1_rx_fifo_data_o7; + output fabric_spw1_rx_fifo_data_o8; + output fabric_spw1_rx_fifo_data_o9; + output fabric_spw1_rx_fifo_empty_o; + input fabric_spw1_rx_fifo_read_i; + input fabric_spw1_tick_ctm_i; + output fabric_spw1_tick_ctm_o; + input fabric_spw1_tx_fifo_data_i1; + input fabric_spw1_tx_fifo_data_i2; + input fabric_spw1_tx_fifo_data_i3; + input fabric_spw1_tx_fifo_data_i4; + input fabric_spw1_tx_fifo_data_i5; + input fabric_spw1_tx_fifo_data_i6; + input fabric_spw1_tx_fifo_data_i7; + input fabric_spw1_tx_fifo_data_i8; + input fabric_spw1_tx_fifo_data_i9; + output fabric_spw1_tx_fifo_full_o; + input fabric_spw1_tx_fifo_write_i; + output fabric_spw1_user_shared_o; + output fabric_status_cold_start_o; + input fabric_thsens_arst_tmr_n_i1; + input fabric_thsens_arst_tmr_n_i2; + input fabric_thsens_arst_tmr_n_i3; + input fabric_thsens_clk_div_ratio_i1; + input fabric_thsens_clk_div_ratio_i2; + input fabric_thsens_clk_div_ratio_i3; + input fabric_thsens_clk_div_ratio_i4; + input fabric_thsens_clk_div_ratio_i5; + input fabric_thsens_clk_div_ratio_i6; + input fabric_thsens_clk_div_ratio_i7; + input fabric_thsens_clk_div_ratio_i8; + input fabric_thsens_clk_i; + output fabric_thsens_fm_config_r_o1; + output fabric_thsens_fm_config_r_o10; + output fabric_thsens_fm_config_r_o11; + output fabric_thsens_fm_config_r_o12; + output fabric_thsens_fm_config_r_o13; + output fabric_thsens_fm_config_r_o14; + output fabric_thsens_fm_config_r_o15; + output fabric_thsens_fm_config_r_o16; + output fabric_thsens_fm_config_r_o17; + output fabric_thsens_fm_config_r_o18; + output fabric_thsens_fm_config_r_o19; + output fabric_thsens_fm_config_r_o2; + output fabric_thsens_fm_config_r_o20; + output fabric_thsens_fm_config_r_o21; + output fabric_thsens_fm_config_r_o22; + output fabric_thsens_fm_config_r_o23; + output fabric_thsens_fm_config_r_o24; + output fabric_thsens_fm_config_r_o25; + output fabric_thsens_fm_config_r_o26; + output fabric_thsens_fm_config_r_o27; + output fabric_thsens_fm_config_r_o3; + output fabric_thsens_fm_config_r_o4; + output fabric_thsens_fm_config_r_o5; + output fabric_thsens_fm_config_r_o6; + output fabric_thsens_fm_config_r_o7; + output fabric_thsens_fm_config_r_o8; + output fabric_thsens_fm_config_r_o9; + input fabric_thsens_fm_config_w_i1; + input fabric_thsens_fm_config_w_i10; + input fabric_thsens_fm_config_w_i11; + input fabric_thsens_fm_config_w_i12; + input fabric_thsens_fm_config_w_i13; + input fabric_thsens_fm_config_w_i14; + input fabric_thsens_fm_config_w_i15; + input fabric_thsens_fm_config_w_i16; + input fabric_thsens_fm_config_w_i17; + input fabric_thsens_fm_config_w_i18; + input fabric_thsens_fm_config_w_i19; + input fabric_thsens_fm_config_w_i2; + input fabric_thsens_fm_config_w_i20; + input fabric_thsens_fm_config_w_i21; + input fabric_thsens_fm_config_w_i22; + input fabric_thsens_fm_config_w_i23; + input fabric_thsens_fm_config_w_i24; + input fabric_thsens_fm_config_w_i25; + input fabric_thsens_fm_config_w_i26; + input fabric_thsens_fm_config_w_i27; + input fabric_thsens_fm_config_w_i3; + input fabric_thsens_fm_config_w_i4; + input fabric_thsens_fm_config_w_i5; + input fabric_thsens_fm_config_w_i6; + input fabric_thsens_fm_config_w_i7; + input fabric_thsens_fm_config_w_i8; + input fabric_thsens_fm_config_w_i9; + input fabric_thsens_fm_config_wen_i; + output fabric_thsens_fm_data_o1; + output fabric_thsens_fm_data_o10; + output fabric_thsens_fm_data_o11; + output fabric_thsens_fm_data_o12; + output fabric_thsens_fm_data_o13; + output fabric_thsens_fm_data_o14; + output fabric_thsens_fm_data_o2; + output fabric_thsens_fm_data_o3; + output fabric_thsens_fm_data_o4; + output fabric_thsens_fm_data_o5; + output fabric_thsens_fm_data_o6; + output fabric_thsens_fm_data_o7; + output fabric_thsens_fm_data_o8; + output fabric_thsens_fm_data_o9; + input fabric_thsens_fm_enable_i; + output fabric_thsens_fm_mode_r_o1; + output fabric_thsens_fm_mode_r_o10; + output fabric_thsens_fm_mode_r_o11; + output fabric_thsens_fm_mode_r_o12; + output fabric_thsens_fm_mode_r_o13; + output fabric_thsens_fm_mode_r_o14; + output fabric_thsens_fm_mode_r_o15; + output fabric_thsens_fm_mode_r_o16; + output fabric_thsens_fm_mode_r_o17; + output fabric_thsens_fm_mode_r_o18; + output fabric_thsens_fm_mode_r_o19; + output fabric_thsens_fm_mode_r_o2; + output fabric_thsens_fm_mode_r_o20; + output fabric_thsens_fm_mode_r_o21; + output fabric_thsens_fm_mode_r_o22; + output fabric_thsens_fm_mode_r_o23; + output fabric_thsens_fm_mode_r_o24; + output fabric_thsens_fm_mode_r_o25; + output fabric_thsens_fm_mode_r_o26; + output fabric_thsens_fm_mode_r_o27; + output fabric_thsens_fm_mode_r_o28; + output fabric_thsens_fm_mode_r_o29; + output fabric_thsens_fm_mode_r_o3; + output fabric_thsens_fm_mode_r_o30; + output fabric_thsens_fm_mode_r_o31; + output fabric_thsens_fm_mode_r_o32; + output fabric_thsens_fm_mode_r_o4; + output fabric_thsens_fm_mode_r_o5; + output fabric_thsens_fm_mode_r_o6; + output fabric_thsens_fm_mode_r_o7; + output fabric_thsens_fm_mode_r_o8; + output fabric_thsens_fm_mode_r_o9; + input fabric_thsens_fm_mode_w_i1; + input fabric_thsens_fm_mode_w_i10; + input fabric_thsens_fm_mode_w_i11; + input fabric_thsens_fm_mode_w_i12; + input fabric_thsens_fm_mode_w_i13; + input fabric_thsens_fm_mode_w_i14; + input fabric_thsens_fm_mode_w_i15; + input fabric_thsens_fm_mode_w_i16; + input fabric_thsens_fm_mode_w_i17; + input fabric_thsens_fm_mode_w_i18; + input fabric_thsens_fm_mode_w_i19; + input fabric_thsens_fm_mode_w_i2; + input fabric_thsens_fm_mode_w_i20; + input fabric_thsens_fm_mode_w_i21; + input fabric_thsens_fm_mode_w_i22; + input fabric_thsens_fm_mode_w_i23; + input fabric_thsens_fm_mode_w_i24; + input fabric_thsens_fm_mode_w_i25; + input fabric_thsens_fm_mode_w_i26; + input fabric_thsens_fm_mode_w_i27; + input fabric_thsens_fm_mode_w_i28; + input fabric_thsens_fm_mode_w_i29; + input fabric_thsens_fm_mode_w_i3; + input fabric_thsens_fm_mode_w_i30; + input fabric_thsens_fm_mode_w_i31; + input fabric_thsens_fm_mode_w_i32; + input fabric_thsens_fm_mode_w_i4; + input fabric_thsens_fm_mode_w_i5; + input fabric_thsens_fm_mode_w_i6; + input fabric_thsens_fm_mode_w_i7; + input fabric_thsens_fm_mode_w_i8; + input fabric_thsens_fm_mode_w_i9; + input fabric_thsens_fm_mode_wen_i; + output fabric_thsens_fm_overflow_o; + output fabric_thsens_fm_valid_o; + output fabric_thsens_otp_config_o1; + output fabric_thsens_otp_config_o10; + output fabric_thsens_otp_config_o11; + output fabric_thsens_otp_config_o12; + output fabric_thsens_otp_config_o13; + output fabric_thsens_otp_config_o14; + output fabric_thsens_otp_config_o15; + output fabric_thsens_otp_config_o16; + output fabric_thsens_otp_config_o17; + output fabric_thsens_otp_config_o18; + output fabric_thsens_otp_config_o19; + output fabric_thsens_otp_config_o2; + output fabric_thsens_otp_config_o20; + output fabric_thsens_otp_config_o21; + output fabric_thsens_otp_config_o22; + output fabric_thsens_otp_config_o23; + output fabric_thsens_otp_config_o24; + output fabric_thsens_otp_config_o25; + output fabric_thsens_otp_config_o26; + output fabric_thsens_otp_config_o27; + output fabric_thsens_otp_config_o3; + output fabric_thsens_otp_config_o4; + output fabric_thsens_otp_config_o5; + output fabric_thsens_otp_config_o6; + output fabric_thsens_otp_config_o7; + output fabric_thsens_otp_config_o8; + output fabric_thsens_otp_config_o9; + input fabric_thsens_tst_scanenable_i; + input fabric_thsens_tst_scanin1_i; + input fabric_thsens_tst_scanin2_i; + output fabric_thsens_tst_scanout1_o; + output fabric_thsens_tst_scanout2_o; + input fabric_user_clk_i; + input fabric_user_data_i1; + input fabric_user_data_i10; + input fabric_user_data_i11; + input fabric_user_data_i12; + input fabric_user_data_i13; + input fabric_user_data_i14; + input fabric_user_data_i15; + input fabric_user_data_i16; + input fabric_user_data_i17; + input fabric_user_data_i18; + input fabric_user_data_i19; + input fabric_user_data_i2; + input fabric_user_data_i20; + input fabric_user_data_i21; + input fabric_user_data_i22; + input fabric_user_data_i23; + input fabric_user_data_i24; + input fabric_user_data_i25; + input fabric_user_data_i26; + input fabric_user_data_i27; + input fabric_user_data_i28; + input fabric_user_data_i29; + input fabric_user_data_i3; + input fabric_user_data_i30; + input fabric_user_data_i31; + input fabric_user_data_i32; + input fabric_user_data_i4; + input fabric_user_data_i5; + input fabric_user_data_i6; + input fabric_user_data_i7; + input fabric_user_data_i8; + input fabric_user_data_i9; + output fabric_user_data_o1; + output fabric_user_data_o10; + output fabric_user_data_o11; + output fabric_user_data_o12; + output fabric_user_data_o13; + output fabric_user_data_o14; + output fabric_user_data_o15; + output fabric_user_data_o16; + output fabric_user_data_o17; + output fabric_user_data_o18; + output fabric_user_data_o19; + output fabric_user_data_o2; + output fabric_user_data_o20; + output fabric_user_data_o21; + output fabric_user_data_o22; + output fabric_user_data_o23; + output fabric_user_data_o24; + output fabric_user_data_o25; + output fabric_user_data_o26; + output fabric_user_data_o27; + output fabric_user_data_o28; + output fabric_user_data_o29; + output fabric_user_data_o3; + output fabric_user_data_o30; + output fabric_user_data_o31; + output fabric_user_data_o32; + output fabric_user_data_o4; + output fabric_user_data_o5; + output fabric_user_data_o6; + output fabric_user_data_o7; + output fabric_user_data_o8; + output fabric_user_data_o9; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_IF_U_FULL_WRAP(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_bist_mode_o, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_system_dataready_o +, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o +, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i +, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o +, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_ready_o, fabric_otp_cfg_fabric_apb_en_i, fabric_otp_cfg_loader_read_en_i +, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o +, fabric_debug_key_correct_o, fabric_debug_otp_reload_err_o, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i, fabric_dac1_clk_en_i +, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_out_o +, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o +, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_dft_scan_en_i, fabric_adc0_usr_cke_i, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_dft_scan_en_i, fabric_adc1_usr_cke_i, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i +, fabric_adc2_clk_i, fabric_adc2_cal_start_i, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_dft_scan_en_i, fabric_adc2_usr_cke_i, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_dft_scan_en_i +, fabric_adc3_usr_cke_i, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_tst_scanenable_i +, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o, fabric_thsens_tst_scanout2_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i +, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_mrepair_data_to_bist_o, fabric_mrepair_shift_en_to_bist_o +, fabric_mrepair_sif_load_en_to_bist_o, fabric_mrepair_sif_update_en_to_bist_o, fabric_mrepair_sif_reg_en_to_bist_o, fabric_mrepair_system_data_to_mem_bist_i, fabric_mrepair_shift_en_i, fabric_mrepair_sif_load_en_i, fabric_mrepair_sif_update_en_i, fabric_mrepair_sif_reg_en_i, fabric_mrepair_system_data_from_mem_bist_o, fabric_mrepair_mem_type_sel_o, fabric_mrepair_mode_sel_o, fabric_mrepair_mode_i, fabric_mrepair_pd_active_i, fabric_mrepair_chip_status_o, fabric_mrepair_global_chip_status_o, fabric_mrepair_pd_ready_o, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o +, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_mrepair_fuse_status_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o +, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o +, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_dac0_din_i, fabric_dac0_comp_in_sel_i, fabric_cfg_dac0_reg_res_i, fabric_dac1_din_i, fabric_dac1_comp_in_sel_i, fabric_cfg_dac1_reg_res_i, fabric_dac2_din_i, fabric_dac2_comp_in_sel_i, fabric_cfg_dac2_reg_res_i, fabric_dac3_din_i, fabric_dac3_comp_in_sel_i +, fabric_cfg_dac3_reg_res_i, fabric_adc0_arst_b_tmr_i, fabric_adc0_pwr_down_b_tmr_i, fabric_adc0_spare_i, fabric_adc0_dft_test_mode_i, fabric_adc0_dft_si_i, fabric_adc0_usr_arst_b_tmr_i, fabric_adc0_usr_channel_i, fabric_adc0_usr_sample_o, fabric_adc0_usr_sample_lsb_i, fabric_adc0_dbg_addr_i, fabric_adc0_dbg_data_o, fabric_cfg_adc0_clk_cal_div_ratio_i, fabric_adc1_arst_b_tmr_i, fabric_adc1_pwr_down_b_tmr_i, fabric_adc1_spare_i, fabric_adc1_dft_test_mode_i, fabric_adc1_dft_si_i, fabric_adc1_usr_arst_b_tmr_i, fabric_adc1_usr_channel_i, fabric_adc1_usr_sample_o +, fabric_adc1_usr_sample_lsb_i, fabric_adc1_dbg_addr_i, fabric_adc1_dbg_data_o, fabric_cfg_adc1_clk_cal_div_ratio_i, fabric_adc2_arst_b_tmr_i, fabric_adc2_pwr_down_b_tmr_i, fabric_adc2_spare_i, fabric_adc2_dft_test_mode_i, fabric_adc2_dft_si_i, fabric_adc2_usr_arst_b_tmr_i, fabric_adc2_usr_channel_i, fabric_adc2_usr_sample_o, fabric_adc2_usr_sample_lsb_i, fabric_adc2_dbg_addr_i, fabric_adc2_dbg_data_o, fabric_cfg_adc2_clk_cal_div_ratio_i, fabric_adc3_arst_b_tmr_i, fabric_adc3_pwr_down_b_tmr_i, fabric_adc3_spare_i, fabric_adc3_dft_test_mode_i, fabric_adc3_dft_si_i +, fabric_adc3_usr_arst_b_tmr_i, fabric_adc3_usr_channel_i, fabric_adc3_usr_sample_o, fabric_adc3_usr_sample_lsb_i, fabric_adc3_dbg_addr_i, fabric_adc3_dbg_data_o, fabric_cfg_adc3_clk_cal_div_ratio_i, fabric_direct0_clock_fabric_i, fabric_direct0_oe_i, fabric_direct0_oe_ena_i, fabric_direct0_oe_rs_i, fabric_direct0_do_i, fabric_direct0_do_ena_i, fabric_direct0_do_rs_i, fabric_direct0_di_o, fabric_direct0_di_ena_i, fabric_direct0_di_rs_i, fabric_direct0_cfg_bank_i, fabric_direct0_cfg_pad_i, fabric_direct2_clock_fabric_i, fabric_direct2_oe_i +, fabric_direct2_oe_ena_i, fabric_direct2_oe_rs_i, fabric_direct2_do_i, fabric_direct2_do_ena_i, fabric_direct2_do_rs_i, fabric_direct2_di_o, fabric_direct2_di_ena_i, fabric_direct2_di_rs_i, fabric_direct2_cfg_bank_i, fabric_direct2_cfg_pad_i, fabric_direct1_clock_fabric_i, fabric_direct1_oe_i, fabric_direct1_oe_ena_i, fabric_direct1_oe_rs_i, fabric_direct1_do_i, fabric_direct1_do_ena_i, fabric_direct1_do_rs_i, fabric_direct1_di_o, fabric_direct1_di_ena_i, fabric_direct1_di_rs_i, fabric_direct1_cfg_bank_i +, fabric_direct1_cfg_pad_i, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i +, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o +, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o, fabric_mrepair_data_from_bist_i); + input [2:0] fabric_adc0_arst_b_tmr_i; + output fabric_adc0_cal_done_o; + output fabric_adc0_cal_n_overflow_o; + output fabric_adc0_cal_n_underflow_o; + output fabric_adc0_cal_p_overflow_o; + output fabric_adc0_cal_p_underflow_o; + input fabric_adc0_cal_start_i; + input fabric_adc0_clk_i; + input [3:0] fabric_adc0_dbg_addr_i; + output [31:0] fabric_adc0_dbg_data_o; + input fabric_adc0_dft_scan_en_i; + input [11:0] fabric_adc0_dft_si_i; + input [1:0] fabric_adc0_dft_test_mode_i; + input [2:0] fabric_adc0_pwr_down_b_tmr_i; + input [15:0] fabric_adc0_spare_i; + input [2:0] fabric_adc0_usr_arst_b_tmr_i; + input [2:0] fabric_adc0_usr_channel_i; + input fabric_adc0_usr_cke_i; + output fabric_adc0_usr_conv_done_o; + input fabric_adc0_usr_conv_start_i; + input [3:0] fabric_adc0_usr_sample_lsb_i; + output [11:0] fabric_adc0_usr_sample_o; + input [2:0] fabric_adc1_arst_b_tmr_i; + output fabric_adc1_cal_done_o; + output fabric_adc1_cal_n_overflow_o; + output fabric_adc1_cal_n_underflow_o; + output fabric_adc1_cal_p_overflow_o; + output fabric_adc1_cal_p_underflow_o; + input fabric_adc1_cal_start_i; + input fabric_adc1_clk_i; + input [3:0] fabric_adc1_dbg_addr_i; + output [31:0] fabric_adc1_dbg_data_o; + input fabric_adc1_dft_scan_en_i; + input [11:0] fabric_adc1_dft_si_i; + input [1:0] fabric_adc1_dft_test_mode_i; + input [2:0] fabric_adc1_pwr_down_b_tmr_i; + input [15:0] fabric_adc1_spare_i; + input [2:0] fabric_adc1_usr_arst_b_tmr_i; + input [2:0] fabric_adc1_usr_channel_i; + input fabric_adc1_usr_cke_i; + output fabric_adc1_usr_conv_done_o; + input fabric_adc1_usr_conv_start_i; + input [3:0] fabric_adc1_usr_sample_lsb_i; + output [11:0] fabric_adc1_usr_sample_o; + input [2:0] fabric_adc2_arst_b_tmr_i; + output fabric_adc2_cal_done_o; + output fabric_adc2_cal_n_overflow_o; + output fabric_adc2_cal_n_underflow_o; + output fabric_adc2_cal_p_overflow_o; + output fabric_adc2_cal_p_underflow_o; + input fabric_adc2_cal_start_i; + input fabric_adc2_clk_i; + input [3:0] fabric_adc2_dbg_addr_i; + output [31:0] fabric_adc2_dbg_data_o; + input fabric_adc2_dft_scan_en_i; + input [11:0] fabric_adc2_dft_si_i; + input [1:0] fabric_adc2_dft_test_mode_i; + input [2:0] fabric_adc2_pwr_down_b_tmr_i; + input [15:0] fabric_adc2_spare_i; + input [2:0] fabric_adc2_usr_arst_b_tmr_i; + input [2:0] fabric_adc2_usr_channel_i; + input fabric_adc2_usr_cke_i; + output fabric_adc2_usr_conv_done_o; + input fabric_adc2_usr_conv_start_i; + input [3:0] fabric_adc2_usr_sample_lsb_i; + output [11:0] fabric_adc2_usr_sample_o; + input [2:0] fabric_adc3_arst_b_tmr_i; + output fabric_adc3_cal_done_o; + output fabric_adc3_cal_n_overflow_o; + output fabric_adc3_cal_n_underflow_o; + output fabric_adc3_cal_p_overflow_o; + output fabric_adc3_cal_p_underflow_o; + input fabric_adc3_cal_start_i; + input fabric_adc3_clk_i; + input [3:0] fabric_adc3_dbg_addr_i; + output [31:0] fabric_adc3_dbg_data_o; + input fabric_adc3_dft_scan_en_i; + input [11:0] fabric_adc3_dft_si_i; + input [1:0] fabric_adc3_dft_test_mode_i; + input [2:0] fabric_adc3_pwr_down_b_tmr_i; + input [15:0] fabric_adc3_spare_i; + input [2:0] fabric_adc3_usr_arst_b_tmr_i; + input [2:0] fabric_adc3_usr_channel_i; + input fabric_adc3_usr_cke_i; + output fabric_adc3_usr_conv_done_o; + input fabric_adc3_usr_conv_start_i; + input [3:0] fabric_adc3_usr_sample_lsb_i; + output [11:0] fabric_adc3_usr_sample_o; + input [4:0] fabric_cfg_adc0_clk_cal_div_ratio_i; + input fabric_cfg_adc0_conv_done_delayed_i; + input fabric_cfg_adc0_use_cdc_i; + input [4:0] fabric_cfg_adc1_clk_cal_div_ratio_i; + input fabric_cfg_adc1_conv_done_delayed_i; + input fabric_cfg_adc1_use_cdc_i; + input [4:0] fabric_cfg_adc2_clk_cal_div_ratio_i; + input fabric_cfg_adc2_conv_done_delayed_i; + input fabric_cfg_adc2_use_cdc_i; + input [4:0] fabric_cfg_adc3_clk_cal_div_ratio_i; + input fabric_cfg_adc3_conv_done_delayed_i; + input fabric_cfg_adc3_use_cdc_i; + input fabric_cfg_dac0_reg_cm_select_i; + input [1:0] fabric_cfg_dac0_reg_res_i; + input fabric_cfg_dac0_reg_vref_select_i; + input fabric_cfg_dac0_sync_i; + input fabric_cfg_dac1_reg_cm_select_i; + input [1:0] fabric_cfg_dac1_reg_res_i; + input fabric_cfg_dac1_reg_vref_select_i; + input fabric_cfg_dac1_sync_i; + input fabric_cfg_dac2_reg_cm_select_i; + input [1:0] fabric_cfg_dac2_reg_res_i; + input fabric_cfg_dac2_reg_vref_select_i; + input fabric_cfg_dac2_sync_i; + input fabric_cfg_dac3_reg_cm_select_i; + input [1:0] fabric_cfg_dac3_reg_res_i; + input fabric_cfg_dac3_reg_vref_select_i; + input fabric_cfg_dac3_sync_i; + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_clk_bsm_o; + output fabric_clk_otp_mrepair_o; + input fabric_clk_otp_mux_i; + output fabric_clk_otp_o; + output fabric_clk_user0_o; + output fabric_clk_user1_o; + input fabric_dac0_clk_en_i; + input fabric_dac0_clk_i; + input fabric_dac0_comp_en_i; + input fabric_dac0_comp_hyst_en_i; + input [3:0] fabric_dac0_comp_in_sel_i; + output fabric_dac0_comp_out_o; + input fabric_dac0_comp_ref_sel_i; + input [12:0] fabric_dac0_din_i; + input fabric_dac0_filt_en_i; + input fabric_dac0_op_en_i; + input fabric_dac0_reg_pwr_down_n_i; + input fabric_dac0_rstn_i; + input fabric_dac1_clk_en_i; + input fabric_dac1_clk_i; + input fabric_dac1_comp_en_i; + input fabric_dac1_comp_hyst_en_i; + input [3:0] fabric_dac1_comp_in_sel_i; + output fabric_dac1_comp_out_o; + input fabric_dac1_comp_ref_sel_i; + input [12:0] fabric_dac1_din_i; + input fabric_dac1_filt_en_i; + input fabric_dac1_op_en_i; + input fabric_dac1_reg_pwr_down_n_i; + input fabric_dac1_rstn_i; + input fabric_dac2_clk_en_i; + input fabric_dac2_clk_i; + input fabric_dac2_comp_en_i; + input fabric_dac2_comp_hyst_en_i; + input [12:0] fabric_dac2_comp_in_sel_i; + output fabric_dac2_comp_out_o; + input fabric_dac2_comp_ref_sel_i; + input [12:0] fabric_dac2_din_i; + input fabric_dac2_filt_en_i; + input fabric_dac2_op_en_i; + input fabric_dac2_reg_pwr_down_n_i; + input fabric_dac2_rstn_i; + input fabric_dac3_clk_en_i; + input fabric_dac3_clk_i; + input fabric_dac3_comp_en_i; + input fabric_dac3_comp_hyst_en_i; + input [3:0] fabric_dac3_comp_in_sel_i; + output fabric_dac3_comp_out_o; + input fabric_dac3_comp_ref_sel_i; + input [12:0] fabric_dac3_din_i; + input fabric_dac3_filt_en_i; + input fabric_dac3_op_en_i; + input fabric_dac3_reg_pwr_down_n_i; + input fabric_dac3_rstn_i; + output fabric_debug_access_reg_data_ready_o; + output [31:0] fabric_debug_bsec_core_status_o; + output [3:0] fabric_debug_cpt_retry_o; + output [3:0] fabric_debug_direct_permission_read_o; + output [3:0] fabric_debug_direct_permission_write_o; + output fabric_debug_error_o; + output [3:0] fabric_debug_frame_permission_frame_o; + output fabric_debug_frame_use_encryption_o; + output [2:0] fabric_debug_fsm_state_o; + output fabric_debug_key_correct_o; + output [3:0] fabric_debug_lifecycle_o; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output [2:0] fabric_debug_otpapb_state_o; + output [7:0] fabric_debug_otpboot_curr_addr_o; + output [2:0] fabric_debug_otpboot_state_o; + output [2:0] fabric_debug_otpmgmt_state_o; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + input [3:0] fabric_direct0_cfg_bank_i; + input [719:0] fabric_direct0_cfg_pad_i; + input [3:0] fabric_direct0_clock_fabric_i; + input [23:0] fabric_direct0_di_ena_i; + output [23:0] fabric_direct0_di_o; + input [23:0] fabric_direct0_di_rs_i; + input [23:0] fabric_direct0_do_ena_i; + input [23:0] fabric_direct0_do_i; + input [23:0] fabric_direct0_do_rs_i; + input fabric_direct0_loopback_en_i; + input fabric_direct0_loopback_mux_i; + input [23:0] fabric_direct0_oe_ena_i; + input [23:0] fabric_direct0_oe_i; + input [23:0] fabric_direct0_oe_rs_i; + input fabric_direct0_scan_en_i; + input [3:0] fabric_direct1_cfg_bank_i; + input [479:0] fabric_direct1_cfg_pad_i; + input [3:0] fabric_direct1_clock_fabric_i; + input [15:0] fabric_direct1_di_ena_i; + output [15:0] fabric_direct1_di_o; + input [15:0] fabric_direct1_di_rs_i; + input [15:0] fabric_direct1_do_ena_i; + input [15:0] fabric_direct1_do_i; + input [15:0] fabric_direct1_do_rs_i; + input fabric_direct1_loopback_en_i; + input fabric_direct1_loopback_mux_i; + input [15:0] fabric_direct1_oe_ena_i; + input [15:0] fabric_direct1_oe_i; + input [15:0] fabric_direct1_oe_rs_i; + input fabric_direct1_scan_en_i; + input [3:0] fabric_direct2_cfg_bank_i; + input [719:0] fabric_direct2_cfg_pad_i; + input [3:0] fabric_direct2_clock_fabric_i; + input [23:0] fabric_direct2_di_ena_i; + output [23:0] fabric_direct2_di_o; + input [23:0] fabric_direct2_di_rs_i; + input [23:0] fabric_direct2_do_ena_i; + input [23:0] fabric_direct2_do_i; + input [23:0] fabric_direct2_do_rs_i; + input fabric_direct2_loopback_en_i; + input fabric_direct2_loopback_mux_i; + input [23:0] fabric_direct2_oe_ena_i; + input [23:0] fabric_direct2_oe_i; + input [23:0] fabric_direct2_oe_rs_i; + input fabric_direct2_scan_en_i; + input [31:0] fabric_direct_data_i; + output [31:0] fabric_direct_data_o; + input [2:0] fabric_enable_TMR_i; + output [2:0] fabric_flag_ready_TMR_o; + output fabric_flag_trigger0_o; + output fabric_flag_trigger1_o; + input [34:0] fabric_io_in_i; + input [34:0] fabric_io_oe_i; + output [34:0] fabric_io_out_o; + output fabric_jtag_tck_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input [39:0] fabric_lowskew_i; + output [5:0] fabric_lowskew_o; + input fabric_mrepair_bend_i; + output fabric_mrepair_bist_mode_o; + output fabric_mrepair_bypass_o; + output [77:0] fabric_mrepair_chip_status_o; + input fabric_mrepair_cke_force_i; + input fabric_mrepair_cke_i; + input fabric_mrepair_clk_i; + input [25:0] fabric_mrepair_data_from_bist_i; + input fabric_mrepair_data_from_system_i; + input fabric_mrepair_data_shift_en_i; + output [25:0] fabric_mrepair_data_to_bist_o; + output fabric_mrepair_data_to_system_o; + output fabric_mrepair_decoder_init_ready_o; + input fabric_mrepair_end_encoding_i; + output fabric_mrepair_fuse_ack_o; + input [6:0] fabric_mrepair_fuse_add_i; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output [7:0] fabric_mrepair_fuse_bist1fail_o; + output [6:0] fabric_mrepair_fuse_bist2fail_o; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + output fabric_mrepair_fuse_ded_o; + input [38:0] fabric_mrepair_fuse_din_i; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output [40:0] fabric_mrepair_fuse_dout_o; + input fabric_mrepair_fuse_eccbypass_i; + output [3:0] fabric_mrepair_fuse_flagstate_o; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input [2:0] fabric_mrepair_fuse_prgwidth_i; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output [15:0] fabric_mrepair_fuse_startword_o; + output [2:0] fabric_mrepair_fuse_status_o; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input [4:0] fabric_mrepair_fuse_tst_scanin_i; + input fabric_mrepair_fuse_tstscanenable_i; + output [4:0] fabric_mrepair_fuse_tstscanout_o; + output [9:0] fabric_mrepair_fuse_wlromout_o; + input fabric_mrepair_fuse_wordlock_i; + input fabric_mrepair_global_bbad_i; + output [2:0] fabric_mrepair_global_chip_status_o; + input fabric_mrepair_global_repairable_i; + input fabric_mrepair_initn_i; + output fabric_mrepair_mem_atpg_mode_o; + output [4:0] fabric_mrepair_mem_type_sel_o; + output fabric_mrepair_memsafe_o; + input [3:0] fabric_mrepair_mode_i; + output [3:0] fabric_mrepair_mode_sel_o; + input [25:0] fabric_mrepair_pd_active_i; + output [25:0] fabric_mrepair_pd_ready_o; + input fabric_mrepair_por_i; + input fabric_mrepair_rst_n_i; + input [25:0] fabric_mrepair_shift_en_i; + output [25:0] fabric_mrepair_shift_en_to_bist_o; + input [25:0] fabric_mrepair_sif_load_en_i; + output [25:0] fabric_mrepair_sif_load_en_to_bist_o; + input [25:0] fabric_mrepair_sif_reg_en_i; + output [25:0] fabric_mrepair_sif_reg_en_to_bist_o; + input [25:0] fabric_mrepair_sif_update_en_i; + output [25:0] fabric_mrepair_sif_update_en_to_bist_o; + output [25:0] fabric_mrepair_system_data_from_mem_bist_o; + input [25:0] fabric_mrepair_system_data_to_mem_bist_i; + output fabric_mrepair_system_dataready_o; + output fabric_mrepair_test_se_o; + input fabric_mrepair_tst_atpg_mrepair_i; + output fabric_mrepair_tst_gatedclock_o; + input [31:0] fabric_otp_apb_addr_i; + input fabric_otp_apb_enable_i; + output [31:0] fabric_otp_apb_rdata_o; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input [31:0] fabric_otp_apb_wdata_i; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_clk_i; + input fabric_otp_rst_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output [6:0] fabric_otp_security_bist_fail1_o; + output [5:0] fabric_otp_security_bist_fail2_o; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input [3:0] fabric_otp_security_scanin_i; + output [3:0] fabric_otp_security_scanout_o; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input [6:0] fabric_otp_user_add_i; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output [7:0] fabric_otp_user_bist1fail_o; + output [6:0] fabric_otp_user_bist2fail_o; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clk_i; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input [38:0] fabric_otp_user_din_i; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output [40:0] fabric_otp_user_dout_o; + input fabric_otp_user_eccbypass_i; + output [3:0] fabric_otp_user_flagstate_o; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input [2:0] fabric_otp_user_prgwidth_i; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output [15:0] fabric_otp_user_startword_o; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input [4:0] fabric_otp_user_tst_scanin_i; + output [4:0] fabric_otp_user_tst_scanout_o; + output [9:0] fabric_otp_user_wlromout_o; + input fabric_otp_user_wordlock_i; + input fabric_parusr_clk_i; + input fabric_parusr_cs_i; + input [15:0] fabric_parusr_data_i; + output [15:0] fabric_parusr_data_o; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input [1:0] fabric_parusr_type_i; + input [127:0] fabric_spare_i; + output [127:0] fabric_spare_o; + input [8:0] fabric_spi_arst_tmr_n_i; + output [2:0] fabric_spi_bsm_release_o; + output [2:0] fabric_spi_busy_o; + input fabric_spi_clk_i0; + input fabric_spi_clk_i1; + input fabric_spi_clk_i2; + input [5:0] fabric_spi_cmd_bytes_i; + output [2:0] fabric_spi_cmd_full_o; + input [5:0] fabric_spi_cmd_mode_i; + input [2:0] fabric_spi_cmd_push_i; + input [5:0] fabric_spi_cmd_type_i; + input [2:0] fabric_spi_cpha_i; + input [2:0] fabric_spi_cpol_i; + input [11:0] fabric_spi_cs_holdtime_i; + input [11:0] fabric_spi_cs_offtime_i; + input [11:0] fabric_spi_cs_setuptime_i; + input [2:0] fabric_spi_data_in_unlimited_i; + input [2:0] fabric_spi_enable_i; + output [2:0] fabric_spi_error_endianness_o; + output [2:0] fabric_spi_error_loopback_o; + output [2:0] fabric_spi_error_mode_o; + output [2:0] fabric_spi_error_sel_o; + input [8:0] fabric_spi_fifo_arst_tmr_n_i; + output [2:0] fabric_spi_init_done_o; + input [2:0] fabric_spi_legacy_enable_i; + input [2:0] fabric_spi_legacy_master_i; + input [2:0] fabric_spi_loopback_i; + input [2:0] fabric_spi_lsb_first_i; + output [2:0] fabric_spi_miso_data_inv_o; + output [23:0] fabric_spi_miso_data_o; + output [2:0] fabric_spi_miso_empty_o; + input [2:0] fabric_spi_miso_pop_i; + input [23:0] fabric_spi_mosi_data_i; + input [2:0] fabric_spi_mosi_data_inv_i; + output [2:0] fabric_spi_mosi_full_o; + input [2:0] fabric_spi_mosi_push_i; + input [2:0] fabric_spi_needed_i; + input [47:0] fabric_spi_powerdown_cycle_i; + input [47:0] fabric_spi_powerup_cycle_i; + input [2:0] fabric_spi_rst_n_i; + input fabric_spi_sck_i0; + input fabric_spi_sck_i1; + input fabric_spi_sck_i2; + input [2:0] fabric_spi_vcc_enable_i; + output [2:0] fabric_spi_vcc_used_o; + input [6:2] fabric_spw0_apb_slv_paddr_i; + input fabric_spw0_apb_slv_penable_i; + output [30:0] fabric_spw0_apb_slv_prdata_o; + output fabric_spw0_apb_slv_pready_o; + input fabric_spw0_apb_slv_psel_i; + output fabric_spw0_apb_slv_pslverr_o; + input [30:0] fabric_spw0_apb_slv_pwdata_i; + input fabric_spw0_apb_slv_pwrite_i; + input fabric_spw0_clk_i; + input fabric_spw0_clk_tx_i; + input fabric_spw0_rst_n_i; + output [8:0] fabric_spw0_rx_fifo_data_o; + output fabric_spw0_rx_fifo_empty_o; + input fabric_spw0_rx_fifo_read_i; + input fabric_spw0_tick_ctm_i; + output fabric_spw0_tick_ctm_o; + input [8:0] fabric_spw0_tx_fifo_data_i; + output fabric_spw0_tx_fifo_full_o; + input fabric_spw0_tx_fifo_write_i; + output fabric_spw0_user_shared_o; + input [6:2] fabric_spw1_apb_slv_paddr_i; + input fabric_spw1_apb_slv_penable_i; + output [30:0] fabric_spw1_apb_slv_prdata_o; + output fabric_spw1_apb_slv_pready_o; + input fabric_spw1_apb_slv_psel_i; + output fabric_spw1_apb_slv_pslverr_o; + input [30:0] fabric_spw1_apb_slv_pwdata_i; + input fabric_spw1_apb_slv_pwrite_i; + input fabric_spw1_clk_i; + input fabric_spw1_clk_tx_i; + input fabric_spw1_rst_n_i; + output [8:0] fabric_spw1_rx_fifo_data_o; + output fabric_spw1_rx_fifo_empty_o; + input fabric_spw1_rx_fifo_read_i; + input fabric_spw1_tick_ctm_i; + output fabric_spw1_tick_ctm_o; + input [8:0] fabric_spw1_tx_fifo_data_i; + output fabric_spw1_tx_fifo_full_o; + input fabric_spw1_tx_fifo_write_i; + output fabric_spw1_user_shared_o; + output fabric_status_cold_start_o; + input [2:0] fabric_thsens_arst_tmr_n_i; + input [7:0] fabric_thsens_clk_div_ratio_i; + input fabric_thsens_clk_i; + output [26:0] fabric_thsens_fm_config_r_o; + input [26:0] fabric_thsens_fm_config_w_i; + input fabric_thsens_fm_config_wen_i; + output [13:0] fabric_thsens_fm_data_o; + input fabric_thsens_fm_enable_i; + output [31:0] fabric_thsens_fm_mode_r_o; + input [31:0] fabric_thsens_fm_mode_w_i; + input fabric_thsens_fm_mode_wen_i; + output fabric_thsens_fm_overflow_o; + output fabric_thsens_fm_valid_o; + output [26:0] fabric_thsens_otp_config_o; + input fabric_thsens_tst_scanenable_i; + input fabric_thsens_tst_scanin1_i; + input fabric_thsens_tst_scanin2_i; + output fabric_thsens_tst_scanout1_o; + output fabric_thsens_tst_scanout2_o; + input fabric_user_clk_i; + input [31:0] fabric_user_data_i; + output [31:0] fabric_user_data_o; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_IF_U_WRAP(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o +, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o +, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1 +, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o +, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i +, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_flag_ready_TMR_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o +, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o +, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i +, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o); + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_clk_bsm_o; + input fabric_clk_otp_mux_i; + output fabric_clk_otp_o; + output fabric_clk_user0_o; + output fabric_clk_user1_o; + input [2:0] fabric_enable_TMR_i; + output [2:0] fabric_flag_ready_TMR_o; + output fabric_flag_trigger0_o; + output fabric_flag_trigger1_o; + input [34:0] fabric_io_in_i; + input [34:0] fabric_io_oe_i; + output [34:0] fabric_io_out_o; + output fabric_jtag_tck_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input [39:0] fabric_lowskew_i; + output [5:0] fabric_lowskew_o; + output fabric_otp_user_ack_o; + input [6:0] fabric_otp_user_add_i; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output [7:0] fabric_otp_user_bist1fail_o; + output [6:0] fabric_otp_user_bist2fail_o; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clk_i; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input [38:0] fabric_otp_user_din_i; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output [40:0] fabric_otp_user_dout_o; + input fabric_otp_user_eccbypass_i; + output [3:0] fabric_otp_user_flagstate_o; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input [2:0] fabric_otp_user_prgwidth_i; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output [15:0] fabric_otp_user_startword_o; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input [4:0] fabric_otp_user_tst_scanin_i; + output [4:0] fabric_otp_user_tst_scanout_o; + output [9:0] fabric_otp_user_wlromout_o; + input fabric_otp_user_wordlock_i; + input fabric_parusr_clk_i; + input fabric_parusr_cs_i; + input [15:0] fabric_parusr_data_i; + output [15:0] fabric_parusr_data_o; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input [1:0] fabric_parusr_type_i; + input [127:0] fabric_spare_i; + output [127:0] fabric_spare_o; + input [8:0] fabric_spi_arst_tmr_n_i; + output [2:0] fabric_spi_bsm_release_o; + output [2:0] fabric_spi_busy_o; + input fabric_spi_clk_i0; + input fabric_spi_clk_i1; + input fabric_spi_clk_i2; + input [5:0] fabric_spi_cmd_bytes_i; + output [2:0] fabric_spi_cmd_full_o; + input [5:0] fabric_spi_cmd_mode_i; + input [2:0] fabric_spi_cmd_push_i; + input [5:0] fabric_spi_cmd_type_i; + input [2:0] fabric_spi_cpha_i; + input [2:0] fabric_spi_cpol_i; + input [11:0] fabric_spi_cs_holdtime_i; + input [11:0] fabric_spi_cs_offtime_i; + input [11:0] fabric_spi_cs_setuptime_i; + input [2:0] fabric_spi_data_in_unlimited_i; + input [2:0] fabric_spi_enable_i; + output [2:0] fabric_spi_error_endianness_o; + output [2:0] fabric_spi_error_loopback_o; + output [2:0] fabric_spi_error_mode_o; + output [2:0] fabric_spi_error_sel_o; + input [8:0] fabric_spi_fifo_arst_tmr_n_i; + output [2:0] fabric_spi_init_done_o; + input [2:0] fabric_spi_legacy_enable_i; + input [2:0] fabric_spi_legacy_master_i; + input [2:0] fabric_spi_loopback_i; + input [2:0] fabric_spi_lsb_first_i; + output [2:0] fabric_spi_miso_data_inv_o; + output [23:0] fabric_spi_miso_data_o; + output [2:0] fabric_spi_miso_empty_o; + input [2:0] fabric_spi_miso_pop_i; + input [23:0] fabric_spi_mosi_data_i; + input [2:0] fabric_spi_mosi_data_inv_i; + output [2:0] fabric_spi_mosi_full_o; + input [2:0] fabric_spi_mosi_push_i; + input [2:0] fabric_spi_needed_i; + input [47:0] fabric_spi_powerdown_cycle_i; + input [47:0] fabric_spi_powerup_cycle_i; + input [2:0] fabric_spi_rst_n_i; + input fabric_spi_sck_i0; + input fabric_spi_sck_i1; + input fabric_spi_sck_i2; + input [2:0] fabric_spi_vcc_enable_i; + output [2:0] fabric_spi_vcc_used_o; + input [6:2] fabric_spw0_apb_slv_paddr_i; + input fabric_spw0_apb_slv_penable_i; + output [30:0] fabric_spw0_apb_slv_prdata_o; + output fabric_spw0_apb_slv_pready_o; + input fabric_spw0_apb_slv_psel_i; + output fabric_spw0_apb_slv_pslverr_o; + input [30:0] fabric_spw0_apb_slv_pwdata_i; + input fabric_spw0_apb_slv_pwrite_i; + input fabric_spw0_clk_i; + input fabric_spw0_clk_tx_i; + input fabric_spw0_rst_n_i; + output [8:0] fabric_spw0_rx_fifo_data_o; + output fabric_spw0_rx_fifo_empty_o; + input fabric_spw0_rx_fifo_read_i; + input fabric_spw0_tick_ctm_i; + output fabric_spw0_tick_ctm_o; + input [8:0] fabric_spw0_tx_fifo_data_i; + output fabric_spw0_tx_fifo_full_o; + input fabric_spw0_tx_fifo_write_i; + output fabric_spw0_user_shared_o; + input [6:2] fabric_spw1_apb_slv_paddr_i; + input fabric_spw1_apb_slv_penable_i; + output [30:0] fabric_spw1_apb_slv_prdata_o; + output fabric_spw1_apb_slv_pready_o; + input fabric_spw1_apb_slv_psel_i; + output fabric_spw1_apb_slv_pslverr_o; + input [30:0] fabric_spw1_apb_slv_pwdata_i; + input fabric_spw1_apb_slv_pwrite_i; + input fabric_spw1_clk_i; + input fabric_spw1_clk_tx_i; + input fabric_spw1_rst_n_i; + output [8:0] fabric_spw1_rx_fifo_data_o; + output fabric_spw1_rx_fifo_empty_o; + input fabric_spw1_rx_fifo_read_i; + input fabric_spw1_tick_ctm_i; + output fabric_spw1_tick_ctm_o; + input [8:0] fabric_spw1_tx_fifo_data_i; + output fabric_spw1_tx_fifo_full_o; + input fabric_spw1_tx_fifo_write_i; + output fabric_spw1_user_shared_o; + output fabric_status_cold_start_o; + input [2:0] fabric_thsens_arst_tmr_n_i; + input [7:0] fabric_thsens_clk_div_ratio_i; + input fabric_thsens_clk_i; + output [26:0] fabric_thsens_fm_config_r_o; + input [26:0] fabric_thsens_fm_config_w_i; + input fabric_thsens_fm_config_wen_i; + output [13:0] fabric_thsens_fm_data_o; + input fabric_thsens_fm_enable_i; + output [31:0] fabric_thsens_fm_mode_r_o; + input [31:0] fabric_thsens_fm_mode_w_i; + input fabric_thsens_fm_mode_wen_i; + output fabric_thsens_fm_overflow_o; + output fabric_thsens_fm_valid_o; + output [26:0] fabric_thsens_otp_config_o; + input fabric_user_clk_i; + input [31:0] fabric_user_data_i; + output [31:0] fabric_user_data_o; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_U(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17 +, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38 +, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17 +, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i +, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i +, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16 +, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37 +, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58 +, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79 +, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100 +, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i +, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20 +, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13 +, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9 +, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30 +, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16 +, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4 +, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i +, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i +, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19 +, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15 +, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12 +, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33 +, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15 +, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i +, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20 +, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8 +, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4 +, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7 +, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22 +, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13, fabric_sif_update_en_i14 +, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3 +, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5, fabric_sif_update_en_to_bist_o6 +, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o, fabric_debug_frame_permission_frame_o1 +, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13, fabric_data_to_bist_o14 +, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11 +, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15, fabric_ahb_direct_data_o16 +, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5 +, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1, fabric_fuse_status_o2 +, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20 +, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8 +, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29 +, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7 +, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28 +, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5 +, fabric_shift_en_to_bist_o6, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2 +, fabric_sif_reg_en_to_bist_o3, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23 +, fabric_sif_reg_en_to_bist_o24, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44 +, fabric_sif_reg_en_to_bist_o45, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65 +, fabric_sif_reg_en_to_bist_o66, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86 +, fabric_sif_reg_en_to_bist_o87, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107 +, fabric_sif_reg_en_to_bist_o108, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6 +, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12 +, fabric_system_data_from_mem_bist_o13, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9 +, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30 +, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17 +, fabric_chip_status_o18, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38 +, fabric_chip_status_o39, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59 +, fabric_chip_status_o60, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4 +, fabric_pd_ready_o5, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o +, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3 +, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17 +, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o +, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8 +, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2 +, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4 +, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15 +, fabric_sif_load_en_to_bist_o16, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12 +, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8 +, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9 +, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30 +, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1 +, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i); + input fabric_ahb_direct_data_i1; + input fabric_ahb_direct_data_i10; + input fabric_ahb_direct_data_i11; + input fabric_ahb_direct_data_i12; + input fabric_ahb_direct_data_i13; + input fabric_ahb_direct_data_i14; + input fabric_ahb_direct_data_i15; + input fabric_ahb_direct_data_i16; + input fabric_ahb_direct_data_i17; + input fabric_ahb_direct_data_i18; + input fabric_ahb_direct_data_i19; + input fabric_ahb_direct_data_i2; + input fabric_ahb_direct_data_i20; + input fabric_ahb_direct_data_i21; + input fabric_ahb_direct_data_i22; + input fabric_ahb_direct_data_i23; + input fabric_ahb_direct_data_i24; + input fabric_ahb_direct_data_i25; + input fabric_ahb_direct_data_i26; + input fabric_ahb_direct_data_i27; + input fabric_ahb_direct_data_i28; + input fabric_ahb_direct_data_i29; + input fabric_ahb_direct_data_i3; + input fabric_ahb_direct_data_i30; + input fabric_ahb_direct_data_i31; + input fabric_ahb_direct_data_i32; + input fabric_ahb_direct_data_i4; + input fabric_ahb_direct_data_i5; + input fabric_ahb_direct_data_i6; + input fabric_ahb_direct_data_i7; + input fabric_ahb_direct_data_i8; + input fabric_ahb_direct_data_i9; + output fabric_ahb_direct_data_o1; + output fabric_ahb_direct_data_o10; + output fabric_ahb_direct_data_o11; + output fabric_ahb_direct_data_o12; + output fabric_ahb_direct_data_o13; + output fabric_ahb_direct_data_o14; + output fabric_ahb_direct_data_o15; + output fabric_ahb_direct_data_o16; + output fabric_ahb_direct_data_o17; + output fabric_ahb_direct_data_o18; + output fabric_ahb_direct_data_o19; + output fabric_ahb_direct_data_o2; + output fabric_ahb_direct_data_o20; + output fabric_ahb_direct_data_o21; + output fabric_ahb_direct_data_o22; + output fabric_ahb_direct_data_o23; + output fabric_ahb_direct_data_o24; + output fabric_ahb_direct_data_o25; + output fabric_ahb_direct_data_o26; + output fabric_ahb_direct_data_o27; + output fabric_ahb_direct_data_o28; + output fabric_ahb_direct_data_o29; + output fabric_ahb_direct_data_o3; + output fabric_ahb_direct_data_o30; + output fabric_ahb_direct_data_o31; + output fabric_ahb_direct_data_o32; + output fabric_ahb_direct_data_o4; + output fabric_ahb_direct_data_o5; + output fabric_ahb_direct_data_o6; + output fabric_ahb_direct_data_o7; + output fabric_ahb_direct_data_o8; + output fabric_ahb_direct_data_o9; + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_chip_status_o1; + output fabric_chip_status_o10; + output fabric_chip_status_o11; + output fabric_chip_status_o12; + output fabric_chip_status_o13; + output fabric_chip_status_o14; + output fabric_chip_status_o15; + output fabric_chip_status_o16; + output fabric_chip_status_o17; + output fabric_chip_status_o18; + output fabric_chip_status_o19; + output fabric_chip_status_o2; + output fabric_chip_status_o20; + output fabric_chip_status_o21; + output fabric_chip_status_o22; + output fabric_chip_status_o23; + output fabric_chip_status_o24; + output fabric_chip_status_o25; + output fabric_chip_status_o26; + output fabric_chip_status_o27; + output fabric_chip_status_o28; + output fabric_chip_status_o29; + output fabric_chip_status_o3; + output fabric_chip_status_o30; + output fabric_chip_status_o31; + output fabric_chip_status_o32; + output fabric_chip_status_o33; + output fabric_chip_status_o34; + output fabric_chip_status_o35; + output fabric_chip_status_o36; + output fabric_chip_status_o37; + output fabric_chip_status_o38; + output fabric_chip_status_o39; + output fabric_chip_status_o4; + output fabric_chip_status_o40; + output fabric_chip_status_o41; + output fabric_chip_status_o42; + output fabric_chip_status_o43; + output fabric_chip_status_o44; + output fabric_chip_status_o45; + output fabric_chip_status_o46; + output fabric_chip_status_o47; + output fabric_chip_status_o48; + output fabric_chip_status_o49; + output fabric_chip_status_o5; + output fabric_chip_status_o50; + output fabric_chip_status_o51; + output fabric_chip_status_o52; + output fabric_chip_status_o53; + output fabric_chip_status_o54; + output fabric_chip_status_o55; + output fabric_chip_status_o56; + output fabric_chip_status_o57; + output fabric_chip_status_o58; + output fabric_chip_status_o59; + output fabric_chip_status_o6; + output fabric_chip_status_o60; + output fabric_chip_status_o61; + output fabric_chip_status_o62; + output fabric_chip_status_o63; + output fabric_chip_status_o64; + output fabric_chip_status_o65; + output fabric_chip_status_o66; + output fabric_chip_status_o67; + output fabric_chip_status_o68; + output fabric_chip_status_o69; + output fabric_chip_status_o7; + output fabric_chip_status_o70; + output fabric_chip_status_o71; + output fabric_chip_status_o72; + output fabric_chip_status_o8; + output fabric_chip_status_o9; + input fabric_clk_otp_mux_i; + input fabric_data_from_bist_i1; + input fabric_data_from_bist_i10; + input fabric_data_from_bist_i11; + input fabric_data_from_bist_i12; + input fabric_data_from_bist_i13; + input fabric_data_from_bist_i14; + input fabric_data_from_bist_i15; + input fabric_data_from_bist_i16; + input fabric_data_from_bist_i17; + input fabric_data_from_bist_i18; + input fabric_data_from_bist_i19; + input fabric_data_from_bist_i2; + input fabric_data_from_bist_i20; + input fabric_data_from_bist_i21; + input fabric_data_from_bist_i22; + input fabric_data_from_bist_i23; + input fabric_data_from_bist_i24; + input fabric_data_from_bist_i3; + input fabric_data_from_bist_i4; + input fabric_data_from_bist_i5; + input fabric_data_from_bist_i6; + input fabric_data_from_bist_i7; + input fabric_data_from_bist_i8; + input fabric_data_from_bist_i9; + input fabric_data_from_system_i; + input fabric_data_shift_en_i; + output fabric_data_to_bist_o1; + output fabric_data_to_bist_o10; + output fabric_data_to_bist_o11; + output fabric_data_to_bist_o12; + output fabric_data_to_bist_o13; + output fabric_data_to_bist_o14; + output fabric_data_to_bist_o15; + output fabric_data_to_bist_o16; + output fabric_data_to_bist_o17; + output fabric_data_to_bist_o18; + output fabric_data_to_bist_o19; + output fabric_data_to_bist_o2; + output fabric_data_to_bist_o20; + output fabric_data_to_bist_o21; + output fabric_data_to_bist_o22; + output fabric_data_to_bist_o23; + output fabric_data_to_bist_o24; + output fabric_data_to_bist_o3; + output fabric_data_to_bist_o4; + output fabric_data_to_bist_o5; + output fabric_data_to_bist_o6; + output fabric_data_to_bist_o7; + output fabric_data_to_bist_o8; + output fabric_data_to_bist_o9; + output fabric_data_to_system_o; + output fabric_debug_access_reg_data_ready_o; + output fabric_debug_bsec_core_status_o1; + output fabric_debug_bsec_core_status_o10; + output fabric_debug_bsec_core_status_o11; + output fabric_debug_bsec_core_status_o12; + output fabric_debug_bsec_core_status_o13; + output fabric_debug_bsec_core_status_o14; + output fabric_debug_bsec_core_status_o15; + output fabric_debug_bsec_core_status_o16; + output fabric_debug_bsec_core_status_o17; + output fabric_debug_bsec_core_status_o18; + output fabric_debug_bsec_core_status_o19; + output fabric_debug_bsec_core_status_o2; + output fabric_debug_bsec_core_status_o20; + output fabric_debug_bsec_core_status_o21; + output fabric_debug_bsec_core_status_o22; + output fabric_debug_bsec_core_status_o23; + output fabric_debug_bsec_core_status_o24; + output fabric_debug_bsec_core_status_o25; + output fabric_debug_bsec_core_status_o26; + output fabric_debug_bsec_core_status_o27; + output fabric_debug_bsec_core_status_o28; + output fabric_debug_bsec_core_status_o29; + output fabric_debug_bsec_core_status_o3; + output fabric_debug_bsec_core_status_o30; + output fabric_debug_bsec_core_status_o31; + output fabric_debug_bsec_core_status_o32; + output fabric_debug_bsec_core_status_o4; + output fabric_debug_bsec_core_status_o5; + output fabric_debug_bsec_core_status_o6; + output fabric_debug_bsec_core_status_o7; + output fabric_debug_bsec_core_status_o8; + output fabric_debug_bsec_core_status_o9; + output fabric_debug_cpt_retry_o1; + output fabric_debug_cpt_retry_o2; + output fabric_debug_cpt_retry_o3; + output fabric_debug_cpt_retry_o4; + output fabric_debug_direct_permission_read_o1; + output fabric_debug_direct_permission_read_o2; + output fabric_debug_direct_permission_read_o3; + output fabric_debug_direct_permission_read_o4; + output fabric_debug_direct_permission_write_o1; + output fabric_debug_direct_permission_write_o2; + output fabric_debug_direct_permission_write_o3; + output fabric_debug_direct_permission_write_o4; + output fabric_debug_error_o; + output fabric_debug_frame_permission_frame_o1; + output fabric_debug_frame_permission_frame_o2; + output fabric_debug_frame_permission_frame_o3; + output fabric_debug_frame_permission_frame_o4; + output fabric_debug_frame_use_encryption_o; + output fabric_debug_fsm_state_o1; + output fabric_debug_fsm_state_o2; + output fabric_debug_fsm_state_o3; + output fabric_debug_key_correct_o; + output fabric_debug_lifecycle_o1; + output fabric_debug_lifecycle_o2; + output fabric_debug_lifecycle_o3; + output fabric_debug_lifecycle_o4; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output fabric_debug_otpapb_state_o1; + output fabric_debug_otpapb_state_o2; + output fabric_debug_otpapb_state_o3; + output fabric_debug_otpboot_curr_addr_o1; + output fabric_debug_otpboot_curr_addr_o2; + output fabric_debug_otpboot_curr_addr_o3; + output fabric_debug_otpboot_curr_addr_o4; + output fabric_debug_otpboot_curr_addr_o5; + output fabric_debug_otpboot_curr_addr_o6; + output fabric_debug_otpboot_curr_addr_o7; + output fabric_debug_otpboot_curr_addr_o8; + output fabric_debug_otpboot_state_o1; + output fabric_debug_otpboot_state_o2; + output fabric_debug_otpboot_state_o3; + output fabric_debug_otpmgmt_state_o1; + output fabric_debug_otpmgmt_state_o2; + output fabric_debug_otpmgmt_state_o3; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + output fabric_decoder_init_ready_o; + input fabric_direct_data_i1; + input fabric_direct_data_i10; + input fabric_direct_data_i11; + input fabric_direct_data_i12; + input fabric_direct_data_i13; + input fabric_direct_data_i14; + input fabric_direct_data_i15; + input fabric_direct_data_i16; + input fabric_direct_data_i17; + input fabric_direct_data_i18; + input fabric_direct_data_i19; + input fabric_direct_data_i2; + input fabric_direct_data_i20; + input fabric_direct_data_i21; + input fabric_direct_data_i22; + input fabric_direct_data_i23; + input fabric_direct_data_i24; + input fabric_direct_data_i25; + input fabric_direct_data_i26; + input fabric_direct_data_i27; + input fabric_direct_data_i28; + input fabric_direct_data_i29; + input fabric_direct_data_i3; + input fabric_direct_data_i30; + input fabric_direct_data_i31; + input fabric_direct_data_i32; + input fabric_direct_data_i4; + input fabric_direct_data_i5; + input fabric_direct_data_i6; + input fabric_direct_data_i7; + input fabric_direct_data_i8; + input fabric_direct_data_i9; + output fabric_direct_data_o1; + output fabric_direct_data_o10; + output fabric_direct_data_o11; + output fabric_direct_data_o12; + output fabric_direct_data_o13; + output fabric_direct_data_o14; + output fabric_direct_data_o15; + output fabric_direct_data_o16; + output fabric_direct_data_o17; + output fabric_direct_data_o18; + output fabric_direct_data_o19; + output fabric_direct_data_o2; + output fabric_direct_data_o20; + output fabric_direct_data_o21; + output fabric_direct_data_o22; + output fabric_direct_data_o23; + output fabric_direct_data_o24; + output fabric_direct_data_o25; + output fabric_direct_data_o26; + output fabric_direct_data_o27; + output fabric_direct_data_o28; + output fabric_direct_data_o29; + output fabric_direct_data_o3; + output fabric_direct_data_o30; + output fabric_direct_data_o31; + output fabric_direct_data_o32; + output fabric_direct_data_o4; + output fabric_direct_data_o5; + output fabric_direct_data_o6; + output fabric_direct_data_o7; + output fabric_direct_data_o8; + output fabric_direct_data_o9; + input fabric_end_encoding_i; + output fabric_flag_error_o; + output fabric_flag_ready_TMR_o1; + output fabric_flag_ready_TMR_o2; + output fabric_flag_ready_TMR_o3; + output fabric_flag_trigger_o; + output fabric_fuse_status_o1; + output fabric_fuse_status_o2; + output fabric_fuse_status_o3; + output fabric_global_chip_status_o1; + output fabric_global_chip_status_o2; + output fabric_global_chip_status_o3; + input fabric_io_in_i1; + input fabric_io_in_i10; + input fabric_io_in_i11; + input fabric_io_in_i12; + input fabric_io_in_i13; + input fabric_io_in_i14; + input fabric_io_in_i15; + input fabric_io_in_i16; + input fabric_io_in_i17; + input fabric_io_in_i18; + input fabric_io_in_i19; + input fabric_io_in_i2; + input fabric_io_in_i20; + input fabric_io_in_i21; + input fabric_io_in_i22; + input fabric_io_in_i23; + input fabric_io_in_i24; + input fabric_io_in_i25; + input fabric_io_in_i3; + input fabric_io_in_i4; + input fabric_io_in_i5; + input fabric_io_in_i6; + input fabric_io_in_i7; + input fabric_io_in_i8; + input fabric_io_in_i9; + input fabric_io_oe_i1; + input fabric_io_oe_i10; + input fabric_io_oe_i11; + input fabric_io_oe_i12; + input fabric_io_oe_i13; + input fabric_io_oe_i14; + input fabric_io_oe_i15; + input fabric_io_oe_i16; + input fabric_io_oe_i17; + input fabric_io_oe_i18; + input fabric_io_oe_i19; + input fabric_io_oe_i2; + input fabric_io_oe_i20; + input fabric_io_oe_i21; + input fabric_io_oe_i22; + input fabric_io_oe_i23; + input fabric_io_oe_i24; + input fabric_io_oe_i25; + input fabric_io_oe_i3; + input fabric_io_oe_i4; + input fabric_io_oe_i5; + input fabric_io_oe_i6; + input fabric_io_oe_i7; + input fabric_io_oe_i8; + input fabric_io_oe_i9; + output fabric_io_out_o1; + output fabric_io_out_o10; + output fabric_io_out_o11; + output fabric_io_out_o12; + output fabric_io_out_o13; + output fabric_io_out_o14; + output fabric_io_out_o15; + output fabric_io_out_o16; + output fabric_io_out_o17; + output fabric_io_out_o18; + output fabric_io_out_o19; + output fabric_io_out_o2; + output fabric_io_out_o20; + output fabric_io_out_o21; + output fabric_io_out_o22; + output fabric_io_out_o23; + output fabric_io_out_o24; + output fabric_io_out_o25; + output fabric_io_out_o3; + output fabric_io_out_o4; + output fabric_io_out_o5; + output fabric_io_out_o6; + output fabric_io_out_o7; + output fabric_io_out_o8; + output fabric_io_out_o9; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + input fabric_mrepair_cke_force_i; + input fabric_mrepair_cke_i; + output fabric_mrepair_fuse_ack_o; + input fabric_mrepair_fuse_add_i1; + input fabric_mrepair_fuse_add_i2; + input fabric_mrepair_fuse_add_i3; + input fabric_mrepair_fuse_add_i4; + input fabric_mrepair_fuse_add_i5; + input fabric_mrepair_fuse_add_i6; + input fabric_mrepair_fuse_add_i7; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output fabric_mrepair_fuse_bist1fail_o1; + output fabric_mrepair_fuse_bist1fail_o2; + output fabric_mrepair_fuse_bist1fail_o3; + output fabric_mrepair_fuse_bist1fail_o4; + output fabric_mrepair_fuse_bist1fail_o5; + output fabric_mrepair_fuse_bist1fail_o6; + output fabric_mrepair_fuse_bist1fail_o7; + output fabric_mrepair_fuse_bist1fail_o8; + output fabric_mrepair_fuse_bist2fail_o1; + output fabric_mrepair_fuse_bist2fail_o2; + output fabric_mrepair_fuse_bist2fail_o3; + output fabric_mrepair_fuse_bist2fail_o4; + output fabric_mrepair_fuse_bist2fail_o5; + output fabric_mrepair_fuse_bist2fail_o6; + output fabric_mrepair_fuse_bist2fail_o7; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + output fabric_mrepair_fuse_ded_o; + input fabric_mrepair_fuse_din_i1; + input fabric_mrepair_fuse_din_i10; + input fabric_mrepair_fuse_din_i11; + input fabric_mrepair_fuse_din_i12; + input fabric_mrepair_fuse_din_i13; + input fabric_mrepair_fuse_din_i14; + input fabric_mrepair_fuse_din_i15; + input fabric_mrepair_fuse_din_i16; + input fabric_mrepair_fuse_din_i17; + input fabric_mrepair_fuse_din_i18; + input fabric_mrepair_fuse_din_i19; + input fabric_mrepair_fuse_din_i2; + input fabric_mrepair_fuse_din_i20; + input fabric_mrepair_fuse_din_i21; + input fabric_mrepair_fuse_din_i22; + input fabric_mrepair_fuse_din_i23; + input fabric_mrepair_fuse_din_i24; + input fabric_mrepair_fuse_din_i25; + input fabric_mrepair_fuse_din_i26; + input fabric_mrepair_fuse_din_i27; + input fabric_mrepair_fuse_din_i28; + input fabric_mrepair_fuse_din_i29; + input fabric_mrepair_fuse_din_i3; + input fabric_mrepair_fuse_din_i30; + input fabric_mrepair_fuse_din_i31; + input fabric_mrepair_fuse_din_i32; + input fabric_mrepair_fuse_din_i33; + input fabric_mrepair_fuse_din_i34; + input fabric_mrepair_fuse_din_i35; + input fabric_mrepair_fuse_din_i36; + input fabric_mrepair_fuse_din_i37; + input fabric_mrepair_fuse_din_i38; + input fabric_mrepair_fuse_din_i39; + input fabric_mrepair_fuse_din_i4; + input fabric_mrepair_fuse_din_i5; + input fabric_mrepair_fuse_din_i6; + input fabric_mrepair_fuse_din_i7; + input fabric_mrepair_fuse_din_i8; + input fabric_mrepair_fuse_din_i9; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output fabric_mrepair_fuse_dout_o1; + output fabric_mrepair_fuse_dout_o10; + output fabric_mrepair_fuse_dout_o11; + output fabric_mrepair_fuse_dout_o12; + output fabric_mrepair_fuse_dout_o13; + output fabric_mrepair_fuse_dout_o14; + output fabric_mrepair_fuse_dout_o15; + output fabric_mrepair_fuse_dout_o16; + output fabric_mrepair_fuse_dout_o17; + output fabric_mrepair_fuse_dout_o18; + output fabric_mrepair_fuse_dout_o19; + output fabric_mrepair_fuse_dout_o2; + output fabric_mrepair_fuse_dout_o20; + output fabric_mrepair_fuse_dout_o21; + output fabric_mrepair_fuse_dout_o22; + output fabric_mrepair_fuse_dout_o23; + output fabric_mrepair_fuse_dout_o24; + output fabric_mrepair_fuse_dout_o25; + output fabric_mrepair_fuse_dout_o26; + output fabric_mrepair_fuse_dout_o27; + output fabric_mrepair_fuse_dout_o28; + output fabric_mrepair_fuse_dout_o29; + output fabric_mrepair_fuse_dout_o3; + output fabric_mrepair_fuse_dout_o30; + output fabric_mrepair_fuse_dout_o31; + output fabric_mrepair_fuse_dout_o32; + output fabric_mrepair_fuse_dout_o33; + output fabric_mrepair_fuse_dout_o34; + output fabric_mrepair_fuse_dout_o35; + output fabric_mrepair_fuse_dout_o36; + output fabric_mrepair_fuse_dout_o37; + output fabric_mrepair_fuse_dout_o38; + output fabric_mrepair_fuse_dout_o39; + output fabric_mrepair_fuse_dout_o4; + output fabric_mrepair_fuse_dout_o40; + output fabric_mrepair_fuse_dout_o41; + output fabric_mrepair_fuse_dout_o5; + output fabric_mrepair_fuse_dout_o6; + output fabric_mrepair_fuse_dout_o7; + output fabric_mrepair_fuse_dout_o8; + output fabric_mrepair_fuse_dout_o9; + input fabric_mrepair_fuse_eccbypass_i; + output fabric_mrepair_fuse_flagstate_o1; + output fabric_mrepair_fuse_flagstate_o2; + output fabric_mrepair_fuse_flagstate_o3; + output fabric_mrepair_fuse_flagstate_o4; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input fabric_mrepair_fuse_prgwidth_i1; + input fabric_mrepair_fuse_prgwidth_i2; + input fabric_mrepair_fuse_prgwidth_i3; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output fabric_mrepair_fuse_startword_o1; + output fabric_mrepair_fuse_startword_o10; + output fabric_mrepair_fuse_startword_o11; + output fabric_mrepair_fuse_startword_o12; + output fabric_mrepair_fuse_startword_o13; + output fabric_mrepair_fuse_startword_o14; + output fabric_mrepair_fuse_startword_o15; + output fabric_mrepair_fuse_startword_o16; + output fabric_mrepair_fuse_startword_o2; + output fabric_mrepair_fuse_startword_o3; + output fabric_mrepair_fuse_startword_o4; + output fabric_mrepair_fuse_startword_o5; + output fabric_mrepair_fuse_startword_o6; + output fabric_mrepair_fuse_startword_o7; + output fabric_mrepair_fuse_startword_o8; + output fabric_mrepair_fuse_startword_o9; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input fabric_mrepair_fuse_tst_scanin_i1; + input fabric_mrepair_fuse_tst_scanin_i2; + input fabric_mrepair_fuse_tst_scanin_i3; + input fabric_mrepair_fuse_tst_scanin_i4; + input fabric_mrepair_fuse_tst_scanin_i5; + input fabric_mrepair_fuse_tstscanenable_i; + output fabric_mrepair_fuse_tstscanout_o1; + output fabric_mrepair_fuse_tstscanout_o2; + output fabric_mrepair_fuse_tstscanout_o3; + output fabric_mrepair_fuse_tstscanout_o4; + output fabric_mrepair_fuse_tstscanout_o5; + output fabric_mrepair_fuse_wlromout_o1; + output fabric_mrepair_fuse_wlromout_o10; + output fabric_mrepair_fuse_wlromout_o2; + output fabric_mrepair_fuse_wlromout_o3; + output fabric_mrepair_fuse_wlromout_o4; + output fabric_mrepair_fuse_wlromout_o5; + output fabric_mrepair_fuse_wlromout_o6; + output fabric_mrepair_fuse_wlromout_o7; + output fabric_mrepair_fuse_wlromout_o8; + output fabric_mrepair_fuse_wlromout_o9; + input fabric_mrepair_fuse_wordlock_i; + input fabric_mrepair_initn_i; + input fabric_mrepair_mode_i1; + input fabric_mrepair_mode_i2; + input fabric_mrepair_mode_i3; + input fabric_mrepair_mode_i4; + input fabric_mrepair_por_i; + input fabric_mrepair_rst_n_i; + input fabric_otp_apb_addr_i1; + input fabric_otp_apb_addr_i10; + input fabric_otp_apb_addr_i11; + input fabric_otp_apb_addr_i12; + input fabric_otp_apb_addr_i13; + input fabric_otp_apb_addr_i14; + input fabric_otp_apb_addr_i15; + input fabric_otp_apb_addr_i16; + input fabric_otp_apb_addr_i17; + input fabric_otp_apb_addr_i18; + input fabric_otp_apb_addr_i19; + input fabric_otp_apb_addr_i2; + input fabric_otp_apb_addr_i20; + input fabric_otp_apb_addr_i21; + input fabric_otp_apb_addr_i22; + input fabric_otp_apb_addr_i23; + input fabric_otp_apb_addr_i24; + input fabric_otp_apb_addr_i25; + input fabric_otp_apb_addr_i26; + input fabric_otp_apb_addr_i27; + input fabric_otp_apb_addr_i28; + input fabric_otp_apb_addr_i29; + input fabric_otp_apb_addr_i3; + input fabric_otp_apb_addr_i30; + input fabric_otp_apb_addr_i31; + input fabric_otp_apb_addr_i32; + input fabric_otp_apb_addr_i4; + input fabric_otp_apb_addr_i5; + input fabric_otp_apb_addr_i6; + input fabric_otp_apb_addr_i7; + input fabric_otp_apb_addr_i8; + input fabric_otp_apb_addr_i9; + input fabric_otp_apb_enable_i; + output fabric_otp_apb_rdata_o1; + output fabric_otp_apb_rdata_o10; + output fabric_otp_apb_rdata_o11; + output fabric_otp_apb_rdata_o12; + output fabric_otp_apb_rdata_o13; + output fabric_otp_apb_rdata_o14; + output fabric_otp_apb_rdata_o15; + output fabric_otp_apb_rdata_o16; + output fabric_otp_apb_rdata_o17; + output fabric_otp_apb_rdata_o18; + output fabric_otp_apb_rdata_o19; + output fabric_otp_apb_rdata_o2; + output fabric_otp_apb_rdata_o20; + output fabric_otp_apb_rdata_o21; + output fabric_otp_apb_rdata_o22; + output fabric_otp_apb_rdata_o23; + output fabric_otp_apb_rdata_o24; + output fabric_otp_apb_rdata_o25; + output fabric_otp_apb_rdata_o26; + output fabric_otp_apb_rdata_o27; + output fabric_otp_apb_rdata_o28; + output fabric_otp_apb_rdata_o29; + output fabric_otp_apb_rdata_o3; + output fabric_otp_apb_rdata_o30; + output fabric_otp_apb_rdata_o31; + output fabric_otp_apb_rdata_o32; + output fabric_otp_apb_rdata_o4; + output fabric_otp_apb_rdata_o5; + output fabric_otp_apb_rdata_o6; + output fabric_otp_apb_rdata_o7; + output fabric_otp_apb_rdata_o8; + output fabric_otp_apb_rdata_o9; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input fabric_otp_apb_wdata_i1; + input fabric_otp_apb_wdata_i10; + input fabric_otp_apb_wdata_i11; + input fabric_otp_apb_wdata_i12; + input fabric_otp_apb_wdata_i13; + input fabric_otp_apb_wdata_i14; + input fabric_otp_apb_wdata_i15; + input fabric_otp_apb_wdata_i16; + input fabric_otp_apb_wdata_i17; + input fabric_otp_apb_wdata_i18; + input fabric_otp_apb_wdata_i19; + input fabric_otp_apb_wdata_i2; + input fabric_otp_apb_wdata_i20; + input fabric_otp_apb_wdata_i21; + input fabric_otp_apb_wdata_i22; + input fabric_otp_apb_wdata_i23; + input fabric_otp_apb_wdata_i24; + input fabric_otp_apb_wdata_i25; + input fabric_otp_apb_wdata_i26; + input fabric_otp_apb_wdata_i27; + input fabric_otp_apb_wdata_i28; + input fabric_otp_apb_wdata_i29; + input fabric_otp_apb_wdata_i3; + input fabric_otp_apb_wdata_i30; + input fabric_otp_apb_wdata_i31; + input fabric_otp_apb_wdata_i32; + input fabric_otp_apb_wdata_i4; + input fabric_otp_apb_wdata_i5; + input fabric_otp_apb_wdata_i6; + input fabric_otp_apb_wdata_i7; + input fabric_otp_apb_wdata_i8; + input fabric_otp_apb_wdata_i9; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_rst_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output fabric_otp_security_bist_fail1_o1; + output fabric_otp_security_bist_fail1_o2; + output fabric_otp_security_bist_fail1_o3; + output fabric_otp_security_bist_fail1_o4; + output fabric_otp_security_bist_fail1_o5; + output fabric_otp_security_bist_fail1_o6; + output fabric_otp_security_bist_fail1_o7; + output fabric_otp_security_bist_fail1_o8; + output fabric_otp_security_bist_fail2_o1; + output fabric_otp_security_bist_fail2_o2; + output fabric_otp_security_bist_fail2_o3; + output fabric_otp_security_bist_fail2_o4; + output fabric_otp_security_bist_fail2_o5; + output fabric_otp_security_bist_fail2_o6; + output fabric_otp_security_bist_fail2_o7; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input fabric_otp_security_scanin_i1; + input fabric_otp_security_scanin_i2; + input fabric_otp_security_scanin_i3; + input fabric_otp_security_scanin_i4; + input fabric_otp_security_scanin_i5; + output fabric_otp_security_scanout_o1; + output fabric_otp_security_scanout_o2; + output fabric_otp_security_scanout_o3; + output fabric_otp_security_scanout_o4; + output fabric_otp_security_scanout_o5; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input fabric_otp_user_add_i1; + input fabric_otp_user_add_i2; + input fabric_otp_user_add_i3; + input fabric_otp_user_add_i4; + input fabric_otp_user_add_i5; + input fabric_otp_user_add_i6; + input fabric_otp_user_add_i7; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output fabric_otp_user_bist1fail_o1; + output fabric_otp_user_bist1fail_o2; + output fabric_otp_user_bist1fail_o3; + output fabric_otp_user_bist1fail_o4; + output fabric_otp_user_bist1fail_o5; + output fabric_otp_user_bist1fail_o6; + output fabric_otp_user_bist1fail_o7; + output fabric_otp_user_bist1fail_o8; + output fabric_otp_user_bist2fail_o1; + output fabric_otp_user_bist2fail_o2; + output fabric_otp_user_bist2fail_o3; + output fabric_otp_user_bist2fail_o4; + output fabric_otp_user_bist2fail_o5; + output fabric_otp_user_bist2fail_o6; + output fabric_otp_user_bist2fail_o7; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input fabric_otp_user_din_i1; + input fabric_otp_user_din_i10; + input fabric_otp_user_din_i11; + input fabric_otp_user_din_i12; + input fabric_otp_user_din_i13; + input fabric_otp_user_din_i14; + input fabric_otp_user_din_i15; + input fabric_otp_user_din_i16; + input fabric_otp_user_din_i17; + input fabric_otp_user_din_i18; + input fabric_otp_user_din_i19; + input fabric_otp_user_din_i2; + input fabric_otp_user_din_i20; + input fabric_otp_user_din_i21; + input fabric_otp_user_din_i22; + input fabric_otp_user_din_i23; + input fabric_otp_user_din_i24; + input fabric_otp_user_din_i25; + input fabric_otp_user_din_i26; + input fabric_otp_user_din_i27; + input fabric_otp_user_din_i28; + input fabric_otp_user_din_i29; + input fabric_otp_user_din_i3; + input fabric_otp_user_din_i30; + input fabric_otp_user_din_i31; + input fabric_otp_user_din_i32; + input fabric_otp_user_din_i33; + input fabric_otp_user_din_i34; + input fabric_otp_user_din_i35; + input fabric_otp_user_din_i36; + input fabric_otp_user_din_i37; + input fabric_otp_user_din_i38; + input fabric_otp_user_din_i39; + input fabric_otp_user_din_i4; + input fabric_otp_user_din_i5; + input fabric_otp_user_din_i6; + input fabric_otp_user_din_i7; + input fabric_otp_user_din_i8; + input fabric_otp_user_din_i9; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output fabric_otp_user_dout_o1; + output fabric_otp_user_dout_o10; + output fabric_otp_user_dout_o11; + output fabric_otp_user_dout_o12; + output fabric_otp_user_dout_o13; + output fabric_otp_user_dout_o14; + output fabric_otp_user_dout_o15; + output fabric_otp_user_dout_o16; + output fabric_otp_user_dout_o17; + output fabric_otp_user_dout_o18; + output fabric_otp_user_dout_o19; + output fabric_otp_user_dout_o2; + output fabric_otp_user_dout_o20; + output fabric_otp_user_dout_o21; + output fabric_otp_user_dout_o22; + output fabric_otp_user_dout_o23; + output fabric_otp_user_dout_o24; + output fabric_otp_user_dout_o25; + output fabric_otp_user_dout_o26; + output fabric_otp_user_dout_o27; + output fabric_otp_user_dout_o28; + output fabric_otp_user_dout_o29; + output fabric_otp_user_dout_o3; + output fabric_otp_user_dout_o30; + output fabric_otp_user_dout_o31; + output fabric_otp_user_dout_o32; + output fabric_otp_user_dout_o33; + output fabric_otp_user_dout_o34; + output fabric_otp_user_dout_o35; + output fabric_otp_user_dout_o36; + output fabric_otp_user_dout_o37; + output fabric_otp_user_dout_o38; + output fabric_otp_user_dout_o39; + output fabric_otp_user_dout_o4; + output fabric_otp_user_dout_o40; + output fabric_otp_user_dout_o41; + output fabric_otp_user_dout_o5; + output fabric_otp_user_dout_o6; + output fabric_otp_user_dout_o7; + output fabric_otp_user_dout_o8; + output fabric_otp_user_dout_o9; + input fabric_otp_user_eccbypass_i; + output fabric_otp_user_flagstate_o1; + output fabric_otp_user_flagstate_o2; + output fabric_otp_user_flagstate_o3; + output fabric_otp_user_flagstate_o4; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input fabric_otp_user_prgwidth_i1; + input fabric_otp_user_prgwidth_i2; + input fabric_otp_user_prgwidth_i3; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output fabric_otp_user_startword_o1; + output fabric_otp_user_startword_o10; + output fabric_otp_user_startword_o11; + output fabric_otp_user_startword_o12; + output fabric_otp_user_startword_o13; + output fabric_otp_user_startword_o14; + output fabric_otp_user_startword_o15; + output fabric_otp_user_startword_o16; + output fabric_otp_user_startword_o2; + output fabric_otp_user_startword_o3; + output fabric_otp_user_startword_o4; + output fabric_otp_user_startword_o5; + output fabric_otp_user_startword_o6; + output fabric_otp_user_startword_o7; + output fabric_otp_user_startword_o8; + output fabric_otp_user_startword_o9; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input fabric_otp_user_tst_scanin_i1; + input fabric_otp_user_tst_scanin_i2; + input fabric_otp_user_tst_scanin_i3; + input fabric_otp_user_tst_scanin_i4; + input fabric_otp_user_tst_scanin_i5; + output fabric_otp_user_tst_scanout_o1; + output fabric_otp_user_tst_scanout_o2; + output fabric_otp_user_tst_scanout_o3; + output fabric_otp_user_tst_scanout_o4; + output fabric_otp_user_tst_scanout_o5; + output fabric_otp_user_wlromout_o1; + output fabric_otp_user_wlromout_o10; + output fabric_otp_user_wlromout_o2; + output fabric_otp_user_wlromout_o3; + output fabric_otp_user_wlromout_o4; + output fabric_otp_user_wlromout_o5; + output fabric_otp_user_wlromout_o6; + output fabric_otp_user_wlromout_o7; + output fabric_otp_user_wlromout_o8; + output fabric_otp_user_wlromout_o9; + input fabric_otp_user_wordlock_i; + input fabric_parusr_cs_i; + input fabric_parusr_data_i1; + input fabric_parusr_data_i10; + input fabric_parusr_data_i11; + input fabric_parusr_data_i12; + input fabric_parusr_data_i13; + input fabric_parusr_data_i14; + input fabric_parusr_data_i15; + input fabric_parusr_data_i16; + input fabric_parusr_data_i2; + input fabric_parusr_data_i3; + input fabric_parusr_data_i4; + input fabric_parusr_data_i5; + input fabric_parusr_data_i6; + input fabric_parusr_data_i7; + input fabric_parusr_data_i8; + input fabric_parusr_data_i9; + output fabric_parusr_data_o1; + output fabric_parusr_data_o10; + output fabric_parusr_data_o11; + output fabric_parusr_data_o12; + output fabric_parusr_data_o13; + output fabric_parusr_data_o14; + output fabric_parusr_data_o15; + output fabric_parusr_data_o16; + output fabric_parusr_data_o2; + output fabric_parusr_data_o3; + output fabric_parusr_data_o4; + output fabric_parusr_data_o5; + output fabric_parusr_data_o6; + output fabric_parusr_data_o7; + output fabric_parusr_data_o8; + output fabric_parusr_data_o9; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input fabric_parusr_type_i1; + input fabric_parusr_type_i2; + input fabric_pd_active_i1; + input fabric_pd_active_i10; + input fabric_pd_active_i11; + input fabric_pd_active_i12; + input fabric_pd_active_i13; + input fabric_pd_active_i14; + input fabric_pd_active_i15; + input fabric_pd_active_i16; + input fabric_pd_active_i17; + input fabric_pd_active_i18; + input fabric_pd_active_i19; + input fabric_pd_active_i2; + input fabric_pd_active_i20; + input fabric_pd_active_i21; + input fabric_pd_active_i22; + input fabric_pd_active_i23; + input fabric_pd_active_i24; + input fabric_pd_active_i3; + input fabric_pd_active_i4; + input fabric_pd_active_i5; + input fabric_pd_active_i6; + input fabric_pd_active_i7; + input fabric_pd_active_i8; + input fabric_pd_active_i9; + output fabric_pd_ready_o1; + output fabric_pd_ready_o10; + output fabric_pd_ready_o11; + output fabric_pd_ready_o12; + output fabric_pd_ready_o13; + output fabric_pd_ready_o14; + output fabric_pd_ready_o15; + output fabric_pd_ready_o16; + output fabric_pd_ready_o17; + output fabric_pd_ready_o18; + output fabric_pd_ready_o19; + output fabric_pd_ready_o2; + output fabric_pd_ready_o20; + output fabric_pd_ready_o21; + output fabric_pd_ready_o22; + output fabric_pd_ready_o23; + output fabric_pd_ready_o24; + output fabric_pd_ready_o3; + output fabric_pd_ready_o4; + output fabric_pd_ready_o5; + output fabric_pd_ready_o6; + output fabric_pd_ready_o7; + output fabric_pd_ready_o8; + output fabric_pd_ready_o9; + input fabric_shift_en_i1; + input fabric_shift_en_i10; + input fabric_shift_en_i11; + input fabric_shift_en_i12; + input fabric_shift_en_i13; + input fabric_shift_en_i14; + input fabric_shift_en_i15; + input fabric_shift_en_i16; + input fabric_shift_en_i17; + input fabric_shift_en_i18; + input fabric_shift_en_i19; + input fabric_shift_en_i2; + input fabric_shift_en_i20; + input fabric_shift_en_i21; + input fabric_shift_en_i22; + input fabric_shift_en_i23; + input fabric_shift_en_i24; + input fabric_shift_en_i3; + input fabric_shift_en_i4; + input fabric_shift_en_i5; + input fabric_shift_en_i6; + input fabric_shift_en_i7; + input fabric_shift_en_i8; + input fabric_shift_en_i9; + output fabric_shift_en_to_bist_o1; + output fabric_shift_en_to_bist_o10; + output fabric_shift_en_to_bist_o11; + output fabric_shift_en_to_bist_o12; + output fabric_shift_en_to_bist_o13; + output fabric_shift_en_to_bist_o14; + output fabric_shift_en_to_bist_o15; + output fabric_shift_en_to_bist_o16; + output fabric_shift_en_to_bist_o17; + output fabric_shift_en_to_bist_o18; + output fabric_shift_en_to_bist_o19; + output fabric_shift_en_to_bist_o2; + output fabric_shift_en_to_bist_o20; + output fabric_shift_en_to_bist_o21; + output fabric_shift_en_to_bist_o22; + output fabric_shift_en_to_bist_o23; + output fabric_shift_en_to_bist_o24; + output fabric_shift_en_to_bist_o3; + output fabric_shift_en_to_bist_o4; + output fabric_shift_en_to_bist_o5; + output fabric_shift_en_to_bist_o6; + output fabric_shift_en_to_bist_o7; + output fabric_shift_en_to_bist_o8; + output fabric_shift_en_to_bist_o9; + input fabric_sif_load_en_i1; + input fabric_sif_load_en_i10; + input fabric_sif_load_en_i11; + input fabric_sif_load_en_i12; + input fabric_sif_load_en_i13; + input fabric_sif_load_en_i14; + input fabric_sif_load_en_i15; + input fabric_sif_load_en_i16; + input fabric_sif_load_en_i17; + input fabric_sif_load_en_i18; + input fabric_sif_load_en_i19; + input fabric_sif_load_en_i2; + input fabric_sif_load_en_i20; + input fabric_sif_load_en_i21; + input fabric_sif_load_en_i22; + input fabric_sif_load_en_i23; + input fabric_sif_load_en_i24; + input fabric_sif_load_en_i3; + input fabric_sif_load_en_i4; + input fabric_sif_load_en_i5; + input fabric_sif_load_en_i6; + input fabric_sif_load_en_i7; + input fabric_sif_load_en_i8; + input fabric_sif_load_en_i9; + output fabric_sif_load_en_to_bist_o1; + output fabric_sif_load_en_to_bist_o10; + output fabric_sif_load_en_to_bist_o11; + output fabric_sif_load_en_to_bist_o12; + output fabric_sif_load_en_to_bist_o13; + output fabric_sif_load_en_to_bist_o14; + output fabric_sif_load_en_to_bist_o15; + output fabric_sif_load_en_to_bist_o16; + output fabric_sif_load_en_to_bist_o17; + output fabric_sif_load_en_to_bist_o18; + output fabric_sif_load_en_to_bist_o19; + output fabric_sif_load_en_to_bist_o2; + output fabric_sif_load_en_to_bist_o20; + output fabric_sif_load_en_to_bist_o21; + output fabric_sif_load_en_to_bist_o22; + output fabric_sif_load_en_to_bist_o23; + output fabric_sif_load_en_to_bist_o24; + output fabric_sif_load_en_to_bist_o3; + output fabric_sif_load_en_to_bist_o4; + output fabric_sif_load_en_to_bist_o5; + output fabric_sif_load_en_to_bist_o6; + output fabric_sif_load_en_to_bist_o7; + output fabric_sif_load_en_to_bist_o8; + output fabric_sif_load_en_to_bist_o9; + input fabric_sif_reg_en_i1; + input fabric_sif_reg_en_i10; + input fabric_sif_reg_en_i100; + input fabric_sif_reg_en_i101; + input fabric_sif_reg_en_i102; + input fabric_sif_reg_en_i103; + input fabric_sif_reg_en_i104; + input fabric_sif_reg_en_i105; + input fabric_sif_reg_en_i106; + input fabric_sif_reg_en_i107; + input fabric_sif_reg_en_i108; + input fabric_sif_reg_en_i109; + input fabric_sif_reg_en_i11; + input fabric_sif_reg_en_i110; + input fabric_sif_reg_en_i111; + input fabric_sif_reg_en_i112; + input fabric_sif_reg_en_i113; + input fabric_sif_reg_en_i114; + input fabric_sif_reg_en_i115; + input fabric_sif_reg_en_i116; + input fabric_sif_reg_en_i117; + input fabric_sif_reg_en_i118; + input fabric_sif_reg_en_i119; + input fabric_sif_reg_en_i12; + input fabric_sif_reg_en_i120; + input fabric_sif_reg_en_i13; + input fabric_sif_reg_en_i14; + input fabric_sif_reg_en_i15; + input fabric_sif_reg_en_i16; + input fabric_sif_reg_en_i17; + input fabric_sif_reg_en_i18; + input fabric_sif_reg_en_i19; + input fabric_sif_reg_en_i2; + input fabric_sif_reg_en_i20; + input fabric_sif_reg_en_i21; + input fabric_sif_reg_en_i22; + input fabric_sif_reg_en_i23; + input fabric_sif_reg_en_i24; + input fabric_sif_reg_en_i25; + input fabric_sif_reg_en_i26; + input fabric_sif_reg_en_i27; + input fabric_sif_reg_en_i28; + input fabric_sif_reg_en_i29; + input fabric_sif_reg_en_i3; + input fabric_sif_reg_en_i30; + input fabric_sif_reg_en_i31; + input fabric_sif_reg_en_i32; + input fabric_sif_reg_en_i33; + input fabric_sif_reg_en_i34; + input fabric_sif_reg_en_i35; + input fabric_sif_reg_en_i36; + input fabric_sif_reg_en_i37; + input fabric_sif_reg_en_i38; + input fabric_sif_reg_en_i39; + input fabric_sif_reg_en_i4; + input fabric_sif_reg_en_i40; + input fabric_sif_reg_en_i41; + input fabric_sif_reg_en_i42; + input fabric_sif_reg_en_i43; + input fabric_sif_reg_en_i44; + input fabric_sif_reg_en_i45; + input fabric_sif_reg_en_i46; + input fabric_sif_reg_en_i47; + input fabric_sif_reg_en_i48; + input fabric_sif_reg_en_i49; + input fabric_sif_reg_en_i5; + input fabric_sif_reg_en_i50; + input fabric_sif_reg_en_i51; + input fabric_sif_reg_en_i52; + input fabric_sif_reg_en_i53; + input fabric_sif_reg_en_i54; + input fabric_sif_reg_en_i55; + input fabric_sif_reg_en_i56; + input fabric_sif_reg_en_i57; + input fabric_sif_reg_en_i58; + input fabric_sif_reg_en_i59; + input fabric_sif_reg_en_i6; + input fabric_sif_reg_en_i60; + input fabric_sif_reg_en_i61; + input fabric_sif_reg_en_i62; + input fabric_sif_reg_en_i63; + input fabric_sif_reg_en_i64; + input fabric_sif_reg_en_i65; + input fabric_sif_reg_en_i66; + input fabric_sif_reg_en_i67; + input fabric_sif_reg_en_i68; + input fabric_sif_reg_en_i69; + input fabric_sif_reg_en_i7; + input fabric_sif_reg_en_i70; + input fabric_sif_reg_en_i71; + input fabric_sif_reg_en_i72; + input fabric_sif_reg_en_i73; + input fabric_sif_reg_en_i74; + input fabric_sif_reg_en_i75; + input fabric_sif_reg_en_i76; + input fabric_sif_reg_en_i77; + input fabric_sif_reg_en_i78; + input fabric_sif_reg_en_i79; + input fabric_sif_reg_en_i8; + input fabric_sif_reg_en_i80; + input fabric_sif_reg_en_i81; + input fabric_sif_reg_en_i82; + input fabric_sif_reg_en_i83; + input fabric_sif_reg_en_i84; + input fabric_sif_reg_en_i85; + input fabric_sif_reg_en_i86; + input fabric_sif_reg_en_i87; + input fabric_sif_reg_en_i88; + input fabric_sif_reg_en_i89; + input fabric_sif_reg_en_i9; + input fabric_sif_reg_en_i90; + input fabric_sif_reg_en_i91; + input fabric_sif_reg_en_i92; + input fabric_sif_reg_en_i93; + input fabric_sif_reg_en_i94; + input fabric_sif_reg_en_i95; + input fabric_sif_reg_en_i96; + input fabric_sif_reg_en_i97; + input fabric_sif_reg_en_i98; + input fabric_sif_reg_en_i99; + output fabric_sif_reg_en_to_bist_o1; + output fabric_sif_reg_en_to_bist_o10; + output fabric_sif_reg_en_to_bist_o100; + output fabric_sif_reg_en_to_bist_o101; + output fabric_sif_reg_en_to_bist_o102; + output fabric_sif_reg_en_to_bist_o103; + output fabric_sif_reg_en_to_bist_o104; + output fabric_sif_reg_en_to_bist_o105; + output fabric_sif_reg_en_to_bist_o106; + output fabric_sif_reg_en_to_bist_o107; + output fabric_sif_reg_en_to_bist_o108; + output fabric_sif_reg_en_to_bist_o109; + output fabric_sif_reg_en_to_bist_o11; + output fabric_sif_reg_en_to_bist_o110; + output fabric_sif_reg_en_to_bist_o111; + output fabric_sif_reg_en_to_bist_o112; + output fabric_sif_reg_en_to_bist_o113; + output fabric_sif_reg_en_to_bist_o114; + output fabric_sif_reg_en_to_bist_o115; + output fabric_sif_reg_en_to_bist_o116; + output fabric_sif_reg_en_to_bist_o117; + output fabric_sif_reg_en_to_bist_o118; + output fabric_sif_reg_en_to_bist_o119; + output fabric_sif_reg_en_to_bist_o12; + output fabric_sif_reg_en_to_bist_o120; + output fabric_sif_reg_en_to_bist_o13; + output fabric_sif_reg_en_to_bist_o14; + output fabric_sif_reg_en_to_bist_o15; + output fabric_sif_reg_en_to_bist_o16; + output fabric_sif_reg_en_to_bist_o17; + output fabric_sif_reg_en_to_bist_o18; + output fabric_sif_reg_en_to_bist_o19; + output fabric_sif_reg_en_to_bist_o2; + output fabric_sif_reg_en_to_bist_o20; + output fabric_sif_reg_en_to_bist_o21; + output fabric_sif_reg_en_to_bist_o22; + output fabric_sif_reg_en_to_bist_o23; + output fabric_sif_reg_en_to_bist_o24; + output fabric_sif_reg_en_to_bist_o25; + output fabric_sif_reg_en_to_bist_o26; + output fabric_sif_reg_en_to_bist_o27; + output fabric_sif_reg_en_to_bist_o28; + output fabric_sif_reg_en_to_bist_o29; + output fabric_sif_reg_en_to_bist_o3; + output fabric_sif_reg_en_to_bist_o30; + output fabric_sif_reg_en_to_bist_o31; + output fabric_sif_reg_en_to_bist_o32; + output fabric_sif_reg_en_to_bist_o33; + output fabric_sif_reg_en_to_bist_o34; + output fabric_sif_reg_en_to_bist_o35; + output fabric_sif_reg_en_to_bist_o36; + output fabric_sif_reg_en_to_bist_o37; + output fabric_sif_reg_en_to_bist_o38; + output fabric_sif_reg_en_to_bist_o39; + output fabric_sif_reg_en_to_bist_o4; + output fabric_sif_reg_en_to_bist_o40; + output fabric_sif_reg_en_to_bist_o41; + output fabric_sif_reg_en_to_bist_o42; + output fabric_sif_reg_en_to_bist_o43; + output fabric_sif_reg_en_to_bist_o44; + output fabric_sif_reg_en_to_bist_o45; + output fabric_sif_reg_en_to_bist_o46; + output fabric_sif_reg_en_to_bist_o47; + output fabric_sif_reg_en_to_bist_o48; + output fabric_sif_reg_en_to_bist_o49; + output fabric_sif_reg_en_to_bist_o5; + output fabric_sif_reg_en_to_bist_o50; + output fabric_sif_reg_en_to_bist_o51; + output fabric_sif_reg_en_to_bist_o52; + output fabric_sif_reg_en_to_bist_o53; + output fabric_sif_reg_en_to_bist_o54; + output fabric_sif_reg_en_to_bist_o55; + output fabric_sif_reg_en_to_bist_o56; + output fabric_sif_reg_en_to_bist_o57; + output fabric_sif_reg_en_to_bist_o58; + output fabric_sif_reg_en_to_bist_o59; + output fabric_sif_reg_en_to_bist_o6; + output fabric_sif_reg_en_to_bist_o60; + output fabric_sif_reg_en_to_bist_o61; + output fabric_sif_reg_en_to_bist_o62; + output fabric_sif_reg_en_to_bist_o63; + output fabric_sif_reg_en_to_bist_o64; + output fabric_sif_reg_en_to_bist_o65; + output fabric_sif_reg_en_to_bist_o66; + output fabric_sif_reg_en_to_bist_o67; + output fabric_sif_reg_en_to_bist_o68; + output fabric_sif_reg_en_to_bist_o69; + output fabric_sif_reg_en_to_bist_o7; + output fabric_sif_reg_en_to_bist_o70; + output fabric_sif_reg_en_to_bist_o71; + output fabric_sif_reg_en_to_bist_o72; + output fabric_sif_reg_en_to_bist_o73; + output fabric_sif_reg_en_to_bist_o74; + output fabric_sif_reg_en_to_bist_o75; + output fabric_sif_reg_en_to_bist_o76; + output fabric_sif_reg_en_to_bist_o77; + output fabric_sif_reg_en_to_bist_o78; + output fabric_sif_reg_en_to_bist_o79; + output fabric_sif_reg_en_to_bist_o8; + output fabric_sif_reg_en_to_bist_o80; + output fabric_sif_reg_en_to_bist_o81; + output fabric_sif_reg_en_to_bist_o82; + output fabric_sif_reg_en_to_bist_o83; + output fabric_sif_reg_en_to_bist_o84; + output fabric_sif_reg_en_to_bist_o85; + output fabric_sif_reg_en_to_bist_o86; + output fabric_sif_reg_en_to_bist_o87; + output fabric_sif_reg_en_to_bist_o88; + output fabric_sif_reg_en_to_bist_o89; + output fabric_sif_reg_en_to_bist_o9; + output fabric_sif_reg_en_to_bist_o90; + output fabric_sif_reg_en_to_bist_o91; + output fabric_sif_reg_en_to_bist_o92; + output fabric_sif_reg_en_to_bist_o93; + output fabric_sif_reg_en_to_bist_o94; + output fabric_sif_reg_en_to_bist_o95; + output fabric_sif_reg_en_to_bist_o96; + output fabric_sif_reg_en_to_bist_o97; + output fabric_sif_reg_en_to_bist_o98; + output fabric_sif_reg_en_to_bist_o99; + input fabric_sif_update_en_i1; + input fabric_sif_update_en_i10; + input fabric_sif_update_en_i11; + input fabric_sif_update_en_i12; + input fabric_sif_update_en_i13; + input fabric_sif_update_en_i14; + input fabric_sif_update_en_i15; + input fabric_sif_update_en_i16; + input fabric_sif_update_en_i17; + input fabric_sif_update_en_i18; + input fabric_sif_update_en_i19; + input fabric_sif_update_en_i2; + input fabric_sif_update_en_i20; + input fabric_sif_update_en_i21; + input fabric_sif_update_en_i22; + input fabric_sif_update_en_i23; + input fabric_sif_update_en_i24; + input fabric_sif_update_en_i3; + input fabric_sif_update_en_i4; + input fabric_sif_update_en_i5; + input fabric_sif_update_en_i6; + input fabric_sif_update_en_i7; + input fabric_sif_update_en_i8; + input fabric_sif_update_en_i9; + output fabric_sif_update_en_to_bist_o1; + output fabric_sif_update_en_to_bist_o10; + output fabric_sif_update_en_to_bist_o11; + output fabric_sif_update_en_to_bist_o12; + output fabric_sif_update_en_to_bist_o13; + output fabric_sif_update_en_to_bist_o14; + output fabric_sif_update_en_to_bist_o15; + output fabric_sif_update_en_to_bist_o16; + output fabric_sif_update_en_to_bist_o17; + output fabric_sif_update_en_to_bist_o18; + output fabric_sif_update_en_to_bist_o19; + output fabric_sif_update_en_to_bist_o2; + output fabric_sif_update_en_to_bist_o20; + output fabric_sif_update_en_to_bist_o21; + output fabric_sif_update_en_to_bist_o22; + output fabric_sif_update_en_to_bist_o23; + output fabric_sif_update_en_to_bist_o24; + output fabric_sif_update_en_to_bist_o3; + output fabric_sif_update_en_to_bist_o4; + output fabric_sif_update_en_to_bist_o5; + output fabric_sif_update_en_to_bist_o6; + output fabric_sif_update_en_to_bist_o7; + output fabric_sif_update_en_to_bist_o8; + output fabric_sif_update_en_to_bist_o9; + output fabric_status_cold_start_o; + output fabric_system_data_from_mem_bist_o1; + output fabric_system_data_from_mem_bist_o10; + output fabric_system_data_from_mem_bist_o11; + output fabric_system_data_from_mem_bist_o12; + output fabric_system_data_from_mem_bist_o13; + output fabric_system_data_from_mem_bist_o14; + output fabric_system_data_from_mem_bist_o15; + output fabric_system_data_from_mem_bist_o16; + output fabric_system_data_from_mem_bist_o17; + output fabric_system_data_from_mem_bist_o18; + output fabric_system_data_from_mem_bist_o19; + output fabric_system_data_from_mem_bist_o2; + output fabric_system_data_from_mem_bist_o20; + output fabric_system_data_from_mem_bist_o21; + output fabric_system_data_from_mem_bist_o22; + output fabric_system_data_from_mem_bist_o23; + output fabric_system_data_from_mem_bist_o24; + output fabric_system_data_from_mem_bist_o3; + output fabric_system_data_from_mem_bist_o4; + output fabric_system_data_from_mem_bist_o5; + output fabric_system_data_from_mem_bist_o6; + output fabric_system_data_from_mem_bist_o7; + output fabric_system_data_from_mem_bist_o8; + output fabric_system_data_from_mem_bist_o9; + input fabric_system_data_to_mem_bist_i1; + input fabric_system_data_to_mem_bist_i10; + input fabric_system_data_to_mem_bist_i11; + input fabric_system_data_to_mem_bist_i12; + input fabric_system_data_to_mem_bist_i13; + input fabric_system_data_to_mem_bist_i14; + input fabric_system_data_to_mem_bist_i15; + input fabric_system_data_to_mem_bist_i16; + input fabric_system_data_to_mem_bist_i17; + input fabric_system_data_to_mem_bist_i18; + input fabric_system_data_to_mem_bist_i19; + input fabric_system_data_to_mem_bist_i2; + input fabric_system_data_to_mem_bist_i20; + input fabric_system_data_to_mem_bist_i21; + input fabric_system_data_to_mem_bist_i22; + input fabric_system_data_to_mem_bist_i23; + input fabric_system_data_to_mem_bist_i24; + input fabric_system_data_to_mem_bist_i3; + input fabric_system_data_to_mem_bist_i4; + input fabric_system_data_to_mem_bist_i5; + input fabric_system_data_to_mem_bist_i6; + input fabric_system_data_to_mem_bist_i7; + input fabric_system_data_to_mem_bist_i8; + input fabric_system_data_to_mem_bist_i9; + output fabric_system_dataready_o; + input fabric_tst_atpg_mrepair_i; + input fabric_user_data_i1; + input fabric_user_data_i10; + input fabric_user_data_i11; + input fabric_user_data_i12; + input fabric_user_data_i13; + input fabric_user_data_i14; + input fabric_user_data_i15; + input fabric_user_data_i16; + input fabric_user_data_i17; + input fabric_user_data_i18; + input fabric_user_data_i19; + input fabric_user_data_i2; + input fabric_user_data_i20; + input fabric_user_data_i21; + input fabric_user_data_i22; + input fabric_user_data_i23; + input fabric_user_data_i24; + input fabric_user_data_i25; + input fabric_user_data_i26; + input fabric_user_data_i27; + input fabric_user_data_i28; + input fabric_user_data_i29; + input fabric_user_data_i3; + input fabric_user_data_i30; + input fabric_user_data_i31; + input fabric_user_data_i32; + input fabric_user_data_i4; + input fabric_user_data_i5; + input fabric_user_data_i6; + input fabric_user_data_i7; + input fabric_user_data_i8; + input fabric_user_data_i9; + output fabric_user_data_o1; + output fabric_user_data_o10; + output fabric_user_data_o11; + output fabric_user_data_o12; + output fabric_user_data_o13; + output fabric_user_data_o14; + output fabric_user_data_o15; + output fabric_user_data_o16; + output fabric_user_data_o17; + output fabric_user_data_o18; + output fabric_user_data_o19; + output fabric_user_data_o2; + output fabric_user_data_o20; + output fabric_user_data_o21; + output fabric_user_data_o22; + output fabric_user_data_o23; + output fabric_user_data_o24; + output fabric_user_data_o25; + output fabric_user_data_o26; + output fabric_user_data_o27; + output fabric_user_data_o28; + output fabric_user_data_o29; + output fabric_user_data_o3; + output fabric_user_data_o30; + output fabric_user_data_o31; + output fabric_user_data_o32; + output fabric_user_data_o4; + output fabric_user_data_o5; + output fabric_user_data_o6; + output fabric_user_data_o7; + output fabric_user_data_o8; + output fabric_user_data_o9; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_U_V1(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17 +, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38 +, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17 +, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i +, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i +, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16 +, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37 +, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58 +, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79 +, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100 +, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i +, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20 +, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13 +, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9 +, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30 +, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16 +, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4 +, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i +, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i +, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19 +, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15 +, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12 +, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33 +, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15 +, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_configreg_i1, fabric_mrepair_fuse_configreg_i2 +, fabric_mrepair_fuse_configreg_i3, fabric_mrepair_fuse_configreg_i4, fabric_mrepair_fuse_configreg_i5, fabric_mrepair_fuse_configreg_i6, fabric_mrepair_fuse_configreg_i7, fabric_mrepair_fuse_configreg_i8, fabric_mrepair_fuse_configreg_i9, fabric_mrepair_fuse_configreg_i10, fabric_mrepair_fuse_configreg_i11, fabric_mrepair_fuse_configreg_i12, fabric_mrepair_fuse_configreg_i13, fabric_mrepair_fuse_configreg_i14, fabric_mrepair_fuse_configreg_i15, fabric_mrepair_fuse_configreg_i16, fabric_mrepair_fuse_configreg_i17, fabric_mrepair_fuse_configreg_i18, fabric_mrepair_fuse_configreg_i19, fabric_mrepair_fuse_configreg_i20, fabric_mrepair_fuse_configreg_i21, fabric_mrepair_fuse_configreg_i22, fabric_mrepair_fuse_configreg_i23 +, fabric_mrepair_fuse_configreg_i24, fabric_mrepair_fuse_configreg_i25, fabric_mrepair_fuse_configreg_i26, fabric_mrepair_fuse_configreg_i27, fabric_mrepair_fuse_configreg_i28, fabric_mrepair_fuse_configreg_i29, fabric_mrepair_fuse_configreg_i30, fabric_mrepair_fuse_configreg_i31, fabric_mrepair_fuse_configreg_i32, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9 +, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30 +, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18 +, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14 +, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17 +, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_configreg_i1, fabric_otp_user_configreg_i2, fabric_otp_user_configreg_i3, fabric_otp_user_configreg_i4, fabric_otp_user_configreg_i5, fabric_otp_user_configreg_i6, fabric_otp_user_configreg_i7, fabric_otp_user_configreg_i8 +, fabric_otp_user_configreg_i9, fabric_otp_user_configreg_i10, fabric_otp_user_configreg_i11, fabric_otp_user_configreg_i12, fabric_otp_user_configreg_i13, fabric_otp_user_configreg_i14, fabric_otp_user_configreg_i15, fabric_otp_user_configreg_i16, fabric_otp_user_configreg_i17, fabric_otp_user_configreg_i18, fabric_otp_user_configreg_i19, fabric_otp_user_configreg_i20, fabric_otp_user_configreg_i21, fabric_otp_user_configreg_i22, fabric_otp_user_configreg_i23, fabric_otp_user_configreg_i24, fabric_otp_user_configreg_i25, fabric_otp_user_configreg_i26, fabric_otp_user_configreg_i27, fabric_otp_user_configreg_i28, fabric_otp_user_configreg_i29 +, fabric_otp_user_configreg_i30, fabric_otp_user_configreg_i31, fabric_otp_user_configreg_i32, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13 +, fabric_sif_update_en_i14, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2 +, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5 +, fabric_sif_update_en_to_bist_o6, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o +, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13 +, fabric_data_to_bist_o14, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10 +, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15 +, fabric_ahb_direct_data_o16, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4 +, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1 +, fabric_fuse_status_o2, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19 +, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7 +, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28 +, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8 +, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29 +, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5, fabric_shift_en_to_bist_o6 +, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2, fabric_sif_reg_en_to_bist_o3 +, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23, fabric_sif_reg_en_to_bist_o24 +, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44, fabric_sif_reg_en_to_bist_o45 +, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65, fabric_sif_reg_en_to_bist_o66 +, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86, fabric_sif_reg_en_to_bist_o87 +, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107, fabric_sif_reg_en_to_bist_o108 +, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7 +, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12, fabric_system_data_from_mem_bist_o13 +, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9, fabric_direct_data_o10 +, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30, fabric_direct_data_o31 +, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17, fabric_chip_status_o18 +, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38, fabric_chip_status_o39 +, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59, fabric_chip_status_o60 +, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4, fabric_pd_ready_o5 +, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o, fabric_otp_apb_ready_o +, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4 +, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18 +, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_mrepair_fuse_wlromout_o1 +, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_security_bist_fail2_o1 +, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3 +, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5 +, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15, fabric_sif_load_en_to_bist_o16 +, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13 +, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9 +, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10 +, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31 +, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2 +, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4); + input fabric_ahb_direct_data_i1; + input fabric_ahb_direct_data_i10; + input fabric_ahb_direct_data_i11; + input fabric_ahb_direct_data_i12; + input fabric_ahb_direct_data_i13; + input fabric_ahb_direct_data_i14; + input fabric_ahb_direct_data_i15; + input fabric_ahb_direct_data_i16; + input fabric_ahb_direct_data_i17; + input fabric_ahb_direct_data_i18; + input fabric_ahb_direct_data_i19; + input fabric_ahb_direct_data_i2; + input fabric_ahb_direct_data_i20; + input fabric_ahb_direct_data_i21; + input fabric_ahb_direct_data_i22; + input fabric_ahb_direct_data_i23; + input fabric_ahb_direct_data_i24; + input fabric_ahb_direct_data_i25; + input fabric_ahb_direct_data_i26; + input fabric_ahb_direct_data_i27; + input fabric_ahb_direct_data_i28; + input fabric_ahb_direct_data_i29; + input fabric_ahb_direct_data_i3; + input fabric_ahb_direct_data_i30; + input fabric_ahb_direct_data_i31; + input fabric_ahb_direct_data_i32; + input fabric_ahb_direct_data_i4; + input fabric_ahb_direct_data_i5; + input fabric_ahb_direct_data_i6; + input fabric_ahb_direct_data_i7; + input fabric_ahb_direct_data_i8; + input fabric_ahb_direct_data_i9; + output fabric_ahb_direct_data_o1; + output fabric_ahb_direct_data_o10; + output fabric_ahb_direct_data_o11; + output fabric_ahb_direct_data_o12; + output fabric_ahb_direct_data_o13; + output fabric_ahb_direct_data_o14; + output fabric_ahb_direct_data_o15; + output fabric_ahb_direct_data_o16; + output fabric_ahb_direct_data_o17; + output fabric_ahb_direct_data_o18; + output fabric_ahb_direct_data_o19; + output fabric_ahb_direct_data_o2; + output fabric_ahb_direct_data_o20; + output fabric_ahb_direct_data_o21; + output fabric_ahb_direct_data_o22; + output fabric_ahb_direct_data_o23; + output fabric_ahb_direct_data_o24; + output fabric_ahb_direct_data_o25; + output fabric_ahb_direct_data_o26; + output fabric_ahb_direct_data_o27; + output fabric_ahb_direct_data_o28; + output fabric_ahb_direct_data_o29; + output fabric_ahb_direct_data_o3; + output fabric_ahb_direct_data_o30; + output fabric_ahb_direct_data_o31; + output fabric_ahb_direct_data_o32; + output fabric_ahb_direct_data_o4; + output fabric_ahb_direct_data_o5; + output fabric_ahb_direct_data_o6; + output fabric_ahb_direct_data_o7; + output fabric_ahb_direct_data_o8; + output fabric_ahb_direct_data_o9; + output fabric_cfg_fabric_user_flag_o; + output fabric_cfg_fabric_user_unmask_o; + output fabric_chip_status_o1; + output fabric_chip_status_o10; + output fabric_chip_status_o11; + output fabric_chip_status_o12; + output fabric_chip_status_o13; + output fabric_chip_status_o14; + output fabric_chip_status_o15; + output fabric_chip_status_o16; + output fabric_chip_status_o17; + output fabric_chip_status_o18; + output fabric_chip_status_o19; + output fabric_chip_status_o2; + output fabric_chip_status_o20; + output fabric_chip_status_o21; + output fabric_chip_status_o22; + output fabric_chip_status_o23; + output fabric_chip_status_o24; + output fabric_chip_status_o25; + output fabric_chip_status_o26; + output fabric_chip_status_o27; + output fabric_chip_status_o28; + output fabric_chip_status_o29; + output fabric_chip_status_o3; + output fabric_chip_status_o30; + output fabric_chip_status_o31; + output fabric_chip_status_o32; + output fabric_chip_status_o33; + output fabric_chip_status_o34; + output fabric_chip_status_o35; + output fabric_chip_status_o36; + output fabric_chip_status_o37; + output fabric_chip_status_o38; + output fabric_chip_status_o39; + output fabric_chip_status_o4; + output fabric_chip_status_o40; + output fabric_chip_status_o41; + output fabric_chip_status_o42; + output fabric_chip_status_o43; + output fabric_chip_status_o44; + output fabric_chip_status_o45; + output fabric_chip_status_o46; + output fabric_chip_status_o47; + output fabric_chip_status_o48; + output fabric_chip_status_o49; + output fabric_chip_status_o5; + output fabric_chip_status_o50; + output fabric_chip_status_o51; + output fabric_chip_status_o52; + output fabric_chip_status_o53; + output fabric_chip_status_o54; + output fabric_chip_status_o55; + output fabric_chip_status_o56; + output fabric_chip_status_o57; + output fabric_chip_status_o58; + output fabric_chip_status_o59; + output fabric_chip_status_o6; + output fabric_chip_status_o60; + output fabric_chip_status_o61; + output fabric_chip_status_o62; + output fabric_chip_status_o63; + output fabric_chip_status_o64; + output fabric_chip_status_o65; + output fabric_chip_status_o66; + output fabric_chip_status_o67; + output fabric_chip_status_o68; + output fabric_chip_status_o69; + output fabric_chip_status_o7; + output fabric_chip_status_o70; + output fabric_chip_status_o71; + output fabric_chip_status_o72; + output fabric_chip_status_o8; + output fabric_chip_status_o9; + input fabric_data_from_bist_i1; + input fabric_data_from_bist_i10; + input fabric_data_from_bist_i11; + input fabric_data_from_bist_i12; + input fabric_data_from_bist_i13; + input fabric_data_from_bist_i14; + input fabric_data_from_bist_i15; + input fabric_data_from_bist_i16; + input fabric_data_from_bist_i17; + input fabric_data_from_bist_i18; + input fabric_data_from_bist_i19; + input fabric_data_from_bist_i2; + input fabric_data_from_bist_i20; + input fabric_data_from_bist_i21; + input fabric_data_from_bist_i22; + input fabric_data_from_bist_i23; + input fabric_data_from_bist_i24; + input fabric_data_from_bist_i3; + input fabric_data_from_bist_i4; + input fabric_data_from_bist_i5; + input fabric_data_from_bist_i6; + input fabric_data_from_bist_i7; + input fabric_data_from_bist_i8; + input fabric_data_from_bist_i9; + input fabric_data_from_system_i; + input fabric_data_shift_en_i; + output fabric_data_to_bist_o1; + output fabric_data_to_bist_o10; + output fabric_data_to_bist_o11; + output fabric_data_to_bist_o12; + output fabric_data_to_bist_o13; + output fabric_data_to_bist_o14; + output fabric_data_to_bist_o15; + output fabric_data_to_bist_o16; + output fabric_data_to_bist_o17; + output fabric_data_to_bist_o18; + output fabric_data_to_bist_o19; + output fabric_data_to_bist_o2; + output fabric_data_to_bist_o20; + output fabric_data_to_bist_o21; + output fabric_data_to_bist_o22; + output fabric_data_to_bist_o23; + output fabric_data_to_bist_o24; + output fabric_data_to_bist_o3; + output fabric_data_to_bist_o4; + output fabric_data_to_bist_o5; + output fabric_data_to_bist_o6; + output fabric_data_to_bist_o7; + output fabric_data_to_bist_o8; + output fabric_data_to_bist_o9; + output fabric_data_to_system_o; + output fabric_debug_access_reg_data_ready_o; + output fabric_debug_bsec_core_status_o1; + output fabric_debug_bsec_core_status_o10; + output fabric_debug_bsec_core_status_o11; + output fabric_debug_bsec_core_status_o12; + output fabric_debug_bsec_core_status_o13; + output fabric_debug_bsec_core_status_o14; + output fabric_debug_bsec_core_status_o15; + output fabric_debug_bsec_core_status_o16; + output fabric_debug_bsec_core_status_o17; + output fabric_debug_bsec_core_status_o18; + output fabric_debug_bsec_core_status_o19; + output fabric_debug_bsec_core_status_o2; + output fabric_debug_bsec_core_status_o20; + output fabric_debug_bsec_core_status_o21; + output fabric_debug_bsec_core_status_o22; + output fabric_debug_bsec_core_status_o23; + output fabric_debug_bsec_core_status_o24; + output fabric_debug_bsec_core_status_o25; + output fabric_debug_bsec_core_status_o26; + output fabric_debug_bsec_core_status_o27; + output fabric_debug_bsec_core_status_o28; + output fabric_debug_bsec_core_status_o29; + output fabric_debug_bsec_core_status_o3; + output fabric_debug_bsec_core_status_o30; + output fabric_debug_bsec_core_status_o31; + output fabric_debug_bsec_core_status_o32; + output fabric_debug_bsec_core_status_o4; + output fabric_debug_bsec_core_status_o5; + output fabric_debug_bsec_core_status_o6; + output fabric_debug_bsec_core_status_o7; + output fabric_debug_bsec_core_status_o8; + output fabric_debug_bsec_core_status_o9; + output fabric_debug_cpt_retry_o1; + output fabric_debug_cpt_retry_o2; + output fabric_debug_cpt_retry_o3; + output fabric_debug_cpt_retry_o4; + output fabric_debug_direct_permission_read_o1; + output fabric_debug_direct_permission_read_o2; + output fabric_debug_direct_permission_read_o3; + output fabric_debug_direct_permission_read_o4; + output fabric_debug_direct_permission_write_o1; + output fabric_debug_direct_permission_write_o2; + output fabric_debug_direct_permission_write_o3; + output fabric_debug_direct_permission_write_o4; + output fabric_debug_error_o; + output fabric_debug_frame_permission_frame_o1; + output fabric_debug_frame_permission_frame_o2; + output fabric_debug_frame_permission_frame_o3; + output fabric_debug_frame_permission_frame_o4; + output fabric_debug_frame_use_encryption_o; + output fabric_debug_fsm_state_o1; + output fabric_debug_fsm_state_o2; + output fabric_debug_fsm_state_o3; + output fabric_debug_key_correct_o; + output fabric_debug_lifecycle_o1; + output fabric_debug_lifecycle_o2; + output fabric_debug_lifecycle_o3; + output fabric_debug_lifecycle_o4; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output fabric_debug_otpapb_state_o1; + output fabric_debug_otpapb_state_o2; + output fabric_debug_otpapb_state_o3; + output fabric_debug_otpboot_curr_addr_o1; + output fabric_debug_otpboot_curr_addr_o2; + output fabric_debug_otpboot_curr_addr_o3; + output fabric_debug_otpboot_curr_addr_o4; + output fabric_debug_otpboot_curr_addr_o5; + output fabric_debug_otpboot_curr_addr_o6; + output fabric_debug_otpboot_curr_addr_o7; + output fabric_debug_otpboot_curr_addr_o8; + output fabric_debug_otpboot_state_o1; + output fabric_debug_otpboot_state_o2; + output fabric_debug_otpboot_state_o3; + output fabric_debug_otpmgmt_state_o1; + output fabric_debug_otpmgmt_state_o2; + output fabric_debug_otpmgmt_state_o3; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + output fabric_decoder_init_ready_o; + input fabric_direct_data_i1; + input fabric_direct_data_i10; + input fabric_direct_data_i11; + input fabric_direct_data_i12; + input fabric_direct_data_i13; + input fabric_direct_data_i14; + input fabric_direct_data_i15; + input fabric_direct_data_i16; + input fabric_direct_data_i17; + input fabric_direct_data_i18; + input fabric_direct_data_i19; + input fabric_direct_data_i2; + input fabric_direct_data_i20; + input fabric_direct_data_i21; + input fabric_direct_data_i22; + input fabric_direct_data_i23; + input fabric_direct_data_i24; + input fabric_direct_data_i25; + input fabric_direct_data_i26; + input fabric_direct_data_i27; + input fabric_direct_data_i28; + input fabric_direct_data_i29; + input fabric_direct_data_i3; + input fabric_direct_data_i30; + input fabric_direct_data_i31; + input fabric_direct_data_i32; + input fabric_direct_data_i4; + input fabric_direct_data_i5; + input fabric_direct_data_i6; + input fabric_direct_data_i7; + input fabric_direct_data_i8; + input fabric_direct_data_i9; + output fabric_direct_data_o1; + output fabric_direct_data_o10; + output fabric_direct_data_o11; + output fabric_direct_data_o12; + output fabric_direct_data_o13; + output fabric_direct_data_o14; + output fabric_direct_data_o15; + output fabric_direct_data_o16; + output fabric_direct_data_o17; + output fabric_direct_data_o18; + output fabric_direct_data_o19; + output fabric_direct_data_o2; + output fabric_direct_data_o20; + output fabric_direct_data_o21; + output fabric_direct_data_o22; + output fabric_direct_data_o23; + output fabric_direct_data_o24; + output fabric_direct_data_o25; + output fabric_direct_data_o26; + output fabric_direct_data_o27; + output fabric_direct_data_o28; + output fabric_direct_data_o29; + output fabric_direct_data_o3; + output fabric_direct_data_o30; + output fabric_direct_data_o31; + output fabric_direct_data_o32; + output fabric_direct_data_o4; + output fabric_direct_data_o5; + output fabric_direct_data_o6; + output fabric_direct_data_o7; + output fabric_direct_data_o8; + output fabric_direct_data_o9; + input fabric_end_encoding_i; + output fabric_flag_error_o; + output fabric_flag_ready_o; + output fabric_flag_trigger_o; + output fabric_fuse_status_o1; + output fabric_fuse_status_o2; + output fabric_fuse_status_o3; + output fabric_global_chip_status_o1; + output fabric_global_chip_status_o2; + output fabric_global_chip_status_o3; + input fabric_io_in_i1; + input fabric_io_in_i10; + input fabric_io_in_i11; + input fabric_io_in_i12; + input fabric_io_in_i13; + input fabric_io_in_i14; + input fabric_io_in_i15; + input fabric_io_in_i16; + input fabric_io_in_i17; + input fabric_io_in_i18; + input fabric_io_in_i19; + input fabric_io_in_i2; + input fabric_io_in_i20; + input fabric_io_in_i21; + input fabric_io_in_i22; + input fabric_io_in_i23; + input fabric_io_in_i24; + input fabric_io_in_i25; + input fabric_io_in_i3; + input fabric_io_in_i4; + input fabric_io_in_i5; + input fabric_io_in_i6; + input fabric_io_in_i7; + input fabric_io_in_i8; + input fabric_io_in_i9; + input fabric_io_oe_i1; + input fabric_io_oe_i10; + input fabric_io_oe_i11; + input fabric_io_oe_i12; + input fabric_io_oe_i13; + input fabric_io_oe_i14; + input fabric_io_oe_i15; + input fabric_io_oe_i16; + input fabric_io_oe_i17; + input fabric_io_oe_i18; + input fabric_io_oe_i19; + input fabric_io_oe_i2; + input fabric_io_oe_i20; + input fabric_io_oe_i21; + input fabric_io_oe_i22; + input fabric_io_oe_i23; + input fabric_io_oe_i24; + input fabric_io_oe_i25; + input fabric_io_oe_i3; + input fabric_io_oe_i4; + input fabric_io_oe_i5; + input fabric_io_oe_i6; + input fabric_io_oe_i7; + input fabric_io_oe_i8; + input fabric_io_oe_i9; + output fabric_io_out_o1; + output fabric_io_out_o10; + output fabric_io_out_o11; + output fabric_io_out_o12; + output fabric_io_out_o13; + output fabric_io_out_o14; + output fabric_io_out_o15; + output fabric_io_out_o16; + output fabric_io_out_o17; + output fabric_io_out_o18; + output fabric_io_out_o19; + output fabric_io_out_o2; + output fabric_io_out_o20; + output fabric_io_out_o21; + output fabric_io_out_o22; + output fabric_io_out_o23; + output fabric_io_out_o24; + output fabric_io_out_o25; + output fabric_io_out_o3; + output fabric_io_out_o4; + output fabric_io_out_o5; + output fabric_io_out_o6; + output fabric_io_out_o7; + output fabric_io_out_o8; + output fabric_io_out_o9; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + output fabric_mrepair_fuse_ack_o; + input fabric_mrepair_fuse_add_i1; + input fabric_mrepair_fuse_add_i2; + input fabric_mrepair_fuse_add_i3; + input fabric_mrepair_fuse_add_i4; + input fabric_mrepair_fuse_add_i5; + input fabric_mrepair_fuse_add_i6; + input fabric_mrepair_fuse_add_i7; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output fabric_mrepair_fuse_bist1fail_o1; + output fabric_mrepair_fuse_bist1fail_o2; + output fabric_mrepair_fuse_bist1fail_o3; + output fabric_mrepair_fuse_bist1fail_o4; + output fabric_mrepair_fuse_bist1fail_o5; + output fabric_mrepair_fuse_bist1fail_o6; + output fabric_mrepair_fuse_bist1fail_o7; + output fabric_mrepair_fuse_bist1fail_o8; + output fabric_mrepair_fuse_bist2fail_o1; + output fabric_mrepair_fuse_bist2fail_o2; + output fabric_mrepair_fuse_bist2fail_o3; + output fabric_mrepair_fuse_bist2fail_o4; + output fabric_mrepair_fuse_bist2fail_o5; + output fabric_mrepair_fuse_bist2fail_o6; + output fabric_mrepair_fuse_bist2fail_o7; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + input fabric_mrepair_fuse_configreg_i1; + input fabric_mrepair_fuse_configreg_i10; + input fabric_mrepair_fuse_configreg_i11; + input fabric_mrepair_fuse_configreg_i12; + input fabric_mrepair_fuse_configreg_i13; + input fabric_mrepair_fuse_configreg_i14; + input fabric_mrepair_fuse_configreg_i15; + input fabric_mrepair_fuse_configreg_i16; + input fabric_mrepair_fuse_configreg_i17; + input fabric_mrepair_fuse_configreg_i18; + input fabric_mrepair_fuse_configreg_i19; + input fabric_mrepair_fuse_configreg_i2; + input fabric_mrepair_fuse_configreg_i20; + input fabric_mrepair_fuse_configreg_i21; + input fabric_mrepair_fuse_configreg_i22; + input fabric_mrepair_fuse_configreg_i23; + input fabric_mrepair_fuse_configreg_i24; + input fabric_mrepair_fuse_configreg_i25; + input fabric_mrepair_fuse_configreg_i26; + input fabric_mrepair_fuse_configreg_i27; + input fabric_mrepair_fuse_configreg_i28; + input fabric_mrepair_fuse_configreg_i29; + input fabric_mrepair_fuse_configreg_i3; + input fabric_mrepair_fuse_configreg_i30; + input fabric_mrepair_fuse_configreg_i31; + input fabric_mrepair_fuse_configreg_i32; + input fabric_mrepair_fuse_configreg_i4; + input fabric_mrepair_fuse_configreg_i5; + input fabric_mrepair_fuse_configreg_i6; + input fabric_mrepair_fuse_configreg_i7; + input fabric_mrepair_fuse_configreg_i8; + input fabric_mrepair_fuse_configreg_i9; + output fabric_mrepair_fuse_ded_o; + input fabric_mrepair_fuse_din_i1; + input fabric_mrepair_fuse_din_i10; + input fabric_mrepair_fuse_din_i11; + input fabric_mrepair_fuse_din_i12; + input fabric_mrepair_fuse_din_i13; + input fabric_mrepair_fuse_din_i14; + input fabric_mrepair_fuse_din_i15; + input fabric_mrepair_fuse_din_i16; + input fabric_mrepair_fuse_din_i17; + input fabric_mrepair_fuse_din_i18; + input fabric_mrepair_fuse_din_i19; + input fabric_mrepair_fuse_din_i2; + input fabric_mrepair_fuse_din_i20; + input fabric_mrepair_fuse_din_i21; + input fabric_mrepair_fuse_din_i22; + input fabric_mrepair_fuse_din_i23; + input fabric_mrepair_fuse_din_i24; + input fabric_mrepair_fuse_din_i25; + input fabric_mrepair_fuse_din_i26; + input fabric_mrepair_fuse_din_i27; + input fabric_mrepair_fuse_din_i28; + input fabric_mrepair_fuse_din_i29; + input fabric_mrepair_fuse_din_i3; + input fabric_mrepair_fuse_din_i30; + input fabric_mrepair_fuse_din_i31; + input fabric_mrepair_fuse_din_i32; + input fabric_mrepair_fuse_din_i33; + input fabric_mrepair_fuse_din_i34; + input fabric_mrepair_fuse_din_i35; + input fabric_mrepair_fuse_din_i36; + input fabric_mrepair_fuse_din_i37; + input fabric_mrepair_fuse_din_i38; + input fabric_mrepair_fuse_din_i39; + input fabric_mrepair_fuse_din_i4; + input fabric_mrepair_fuse_din_i5; + input fabric_mrepair_fuse_din_i6; + input fabric_mrepair_fuse_din_i7; + input fabric_mrepair_fuse_din_i8; + input fabric_mrepair_fuse_din_i9; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output fabric_mrepair_fuse_dout_o1; + output fabric_mrepair_fuse_dout_o10; + output fabric_mrepair_fuse_dout_o11; + output fabric_mrepair_fuse_dout_o12; + output fabric_mrepair_fuse_dout_o13; + output fabric_mrepair_fuse_dout_o14; + output fabric_mrepair_fuse_dout_o15; + output fabric_mrepair_fuse_dout_o16; + output fabric_mrepair_fuse_dout_o17; + output fabric_mrepair_fuse_dout_o18; + output fabric_mrepair_fuse_dout_o19; + output fabric_mrepair_fuse_dout_o2; + output fabric_mrepair_fuse_dout_o20; + output fabric_mrepair_fuse_dout_o21; + output fabric_mrepair_fuse_dout_o22; + output fabric_mrepair_fuse_dout_o23; + output fabric_mrepair_fuse_dout_o24; + output fabric_mrepair_fuse_dout_o25; + output fabric_mrepair_fuse_dout_o26; + output fabric_mrepair_fuse_dout_o27; + output fabric_mrepair_fuse_dout_o28; + output fabric_mrepair_fuse_dout_o29; + output fabric_mrepair_fuse_dout_o3; + output fabric_mrepair_fuse_dout_o30; + output fabric_mrepair_fuse_dout_o31; + output fabric_mrepair_fuse_dout_o32; + output fabric_mrepair_fuse_dout_o33; + output fabric_mrepair_fuse_dout_o34; + output fabric_mrepair_fuse_dout_o35; + output fabric_mrepair_fuse_dout_o36; + output fabric_mrepair_fuse_dout_o37; + output fabric_mrepair_fuse_dout_o38; + output fabric_mrepair_fuse_dout_o39; + output fabric_mrepair_fuse_dout_o4; + output fabric_mrepair_fuse_dout_o40; + output fabric_mrepair_fuse_dout_o41; + output fabric_mrepair_fuse_dout_o5; + output fabric_mrepair_fuse_dout_o6; + output fabric_mrepair_fuse_dout_o7; + output fabric_mrepair_fuse_dout_o8; + output fabric_mrepair_fuse_dout_o9; + input fabric_mrepair_fuse_eccbypass_i; + output fabric_mrepair_fuse_flagstate_o1; + output fabric_mrepair_fuse_flagstate_o2; + output fabric_mrepair_fuse_flagstate_o3; + output fabric_mrepair_fuse_flagstate_o4; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input fabric_mrepair_fuse_prgwidth_i1; + input fabric_mrepair_fuse_prgwidth_i2; + input fabric_mrepair_fuse_prgwidth_i3; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output fabric_mrepair_fuse_startword_o1; + output fabric_mrepair_fuse_startword_o10; + output fabric_mrepair_fuse_startword_o11; + output fabric_mrepair_fuse_startword_o12; + output fabric_mrepair_fuse_startword_o13; + output fabric_mrepair_fuse_startword_o14; + output fabric_mrepair_fuse_startword_o15; + output fabric_mrepair_fuse_startword_o16; + output fabric_mrepair_fuse_startword_o2; + output fabric_mrepair_fuse_startword_o3; + output fabric_mrepair_fuse_startword_o4; + output fabric_mrepair_fuse_startword_o5; + output fabric_mrepair_fuse_startword_o6; + output fabric_mrepair_fuse_startword_o7; + output fabric_mrepair_fuse_startword_o8; + output fabric_mrepair_fuse_startword_o9; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input fabric_mrepair_fuse_tst_scanin_i1; + input fabric_mrepair_fuse_tst_scanin_i2; + input fabric_mrepair_fuse_tst_scanin_i3; + input fabric_mrepair_fuse_tst_scanin_i4; + input fabric_mrepair_fuse_tst_scanin_i5; + input fabric_mrepair_fuse_tstscanenable_i; + output fabric_mrepair_fuse_tstscanout_o1; + output fabric_mrepair_fuse_tstscanout_o2; + output fabric_mrepair_fuse_tstscanout_o3; + output fabric_mrepair_fuse_tstscanout_o4; + output fabric_mrepair_fuse_tstscanout_o5; + output fabric_mrepair_fuse_wlromout_o1; + output fabric_mrepair_fuse_wlromout_o10; + output fabric_mrepair_fuse_wlromout_o2; + output fabric_mrepair_fuse_wlromout_o3; + output fabric_mrepair_fuse_wlromout_o4; + output fabric_mrepair_fuse_wlromout_o5; + output fabric_mrepair_fuse_wlromout_o6; + output fabric_mrepair_fuse_wlromout_o7; + output fabric_mrepair_fuse_wlromout_o8; + output fabric_mrepair_fuse_wlromout_o9; + input fabric_mrepair_fuse_wordlock_i; + input fabric_mrepair_initn_i; + input fabric_mrepair_mode_i1; + input fabric_mrepair_mode_i2; + input fabric_mrepair_mode_i3; + input fabric_mrepair_mode_i4; + input fabric_mrepair_por_i; + input fabric_mrepair_rst_n_i; + input fabric_otp_apb_addr_i1; + input fabric_otp_apb_addr_i10; + input fabric_otp_apb_addr_i11; + input fabric_otp_apb_addr_i12; + input fabric_otp_apb_addr_i13; + input fabric_otp_apb_addr_i14; + input fabric_otp_apb_addr_i15; + input fabric_otp_apb_addr_i16; + input fabric_otp_apb_addr_i17; + input fabric_otp_apb_addr_i18; + input fabric_otp_apb_addr_i19; + input fabric_otp_apb_addr_i2; + input fabric_otp_apb_addr_i20; + input fabric_otp_apb_addr_i21; + input fabric_otp_apb_addr_i22; + input fabric_otp_apb_addr_i23; + input fabric_otp_apb_addr_i24; + input fabric_otp_apb_addr_i25; + input fabric_otp_apb_addr_i26; + input fabric_otp_apb_addr_i27; + input fabric_otp_apb_addr_i28; + input fabric_otp_apb_addr_i29; + input fabric_otp_apb_addr_i3; + input fabric_otp_apb_addr_i30; + input fabric_otp_apb_addr_i31; + input fabric_otp_apb_addr_i32; + input fabric_otp_apb_addr_i4; + input fabric_otp_apb_addr_i5; + input fabric_otp_apb_addr_i6; + input fabric_otp_apb_addr_i7; + input fabric_otp_apb_addr_i8; + input fabric_otp_apb_addr_i9; + input fabric_otp_apb_enable_i; + output fabric_otp_apb_rdata_o1; + output fabric_otp_apb_rdata_o10; + output fabric_otp_apb_rdata_o11; + output fabric_otp_apb_rdata_o12; + output fabric_otp_apb_rdata_o13; + output fabric_otp_apb_rdata_o14; + output fabric_otp_apb_rdata_o15; + output fabric_otp_apb_rdata_o16; + output fabric_otp_apb_rdata_o17; + output fabric_otp_apb_rdata_o18; + output fabric_otp_apb_rdata_o19; + output fabric_otp_apb_rdata_o2; + output fabric_otp_apb_rdata_o20; + output fabric_otp_apb_rdata_o21; + output fabric_otp_apb_rdata_o22; + output fabric_otp_apb_rdata_o23; + output fabric_otp_apb_rdata_o24; + output fabric_otp_apb_rdata_o25; + output fabric_otp_apb_rdata_o26; + output fabric_otp_apb_rdata_o27; + output fabric_otp_apb_rdata_o28; + output fabric_otp_apb_rdata_o29; + output fabric_otp_apb_rdata_o3; + output fabric_otp_apb_rdata_o30; + output fabric_otp_apb_rdata_o31; + output fabric_otp_apb_rdata_o32; + output fabric_otp_apb_rdata_o4; + output fabric_otp_apb_rdata_o5; + output fabric_otp_apb_rdata_o6; + output fabric_otp_apb_rdata_o7; + output fabric_otp_apb_rdata_o8; + output fabric_otp_apb_rdata_o9; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input fabric_otp_apb_wdata_i1; + input fabric_otp_apb_wdata_i10; + input fabric_otp_apb_wdata_i11; + input fabric_otp_apb_wdata_i12; + input fabric_otp_apb_wdata_i13; + input fabric_otp_apb_wdata_i14; + input fabric_otp_apb_wdata_i15; + input fabric_otp_apb_wdata_i16; + input fabric_otp_apb_wdata_i17; + input fabric_otp_apb_wdata_i18; + input fabric_otp_apb_wdata_i19; + input fabric_otp_apb_wdata_i2; + input fabric_otp_apb_wdata_i20; + input fabric_otp_apb_wdata_i21; + input fabric_otp_apb_wdata_i22; + input fabric_otp_apb_wdata_i23; + input fabric_otp_apb_wdata_i24; + input fabric_otp_apb_wdata_i25; + input fabric_otp_apb_wdata_i26; + input fabric_otp_apb_wdata_i27; + input fabric_otp_apb_wdata_i28; + input fabric_otp_apb_wdata_i29; + input fabric_otp_apb_wdata_i3; + input fabric_otp_apb_wdata_i30; + input fabric_otp_apb_wdata_i31; + input fabric_otp_apb_wdata_i32; + input fabric_otp_apb_wdata_i4; + input fabric_otp_apb_wdata_i5; + input fabric_otp_apb_wdata_i6; + input fabric_otp_apb_wdata_i7; + input fabric_otp_apb_wdata_i8; + input fabric_otp_apb_wdata_i9; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_rstn_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output fabric_otp_security_bist_fail1_o1; + output fabric_otp_security_bist_fail1_o2; + output fabric_otp_security_bist_fail1_o3; + output fabric_otp_security_bist_fail1_o4; + output fabric_otp_security_bist_fail1_o5; + output fabric_otp_security_bist_fail1_o6; + output fabric_otp_security_bist_fail1_o7; + output fabric_otp_security_bist_fail1_o8; + output fabric_otp_security_bist_fail2_o1; + output fabric_otp_security_bist_fail2_o2; + output fabric_otp_security_bist_fail2_o3; + output fabric_otp_security_bist_fail2_o4; + output fabric_otp_security_bist_fail2_o5; + output fabric_otp_security_bist_fail2_o6; + output fabric_otp_security_bist_fail2_o7; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input fabric_otp_security_scanin_i1; + input fabric_otp_security_scanin_i2; + input fabric_otp_security_scanin_i3; + input fabric_otp_security_scanin_i4; + input fabric_otp_security_scanin_i5; + output fabric_otp_security_scanout_o1; + output fabric_otp_security_scanout_o2; + output fabric_otp_security_scanout_o3; + output fabric_otp_security_scanout_o4; + output fabric_otp_security_scanout_o5; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input fabric_otp_user_add_i1; + input fabric_otp_user_add_i2; + input fabric_otp_user_add_i3; + input fabric_otp_user_add_i4; + input fabric_otp_user_add_i5; + input fabric_otp_user_add_i6; + input fabric_otp_user_add_i7; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output fabric_otp_user_bist1fail_o1; + output fabric_otp_user_bist1fail_o2; + output fabric_otp_user_bist1fail_o3; + output fabric_otp_user_bist1fail_o4; + output fabric_otp_user_bist1fail_o5; + output fabric_otp_user_bist1fail_o6; + output fabric_otp_user_bist1fail_o7; + output fabric_otp_user_bist1fail_o8; + output fabric_otp_user_bist2fail_o1; + output fabric_otp_user_bist2fail_o2; + output fabric_otp_user_bist2fail_o3; + output fabric_otp_user_bist2fail_o4; + output fabric_otp_user_bist2fail_o5; + output fabric_otp_user_bist2fail_o6; + output fabric_otp_user_bist2fail_o7; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_configreg_i1; + input fabric_otp_user_configreg_i10; + input fabric_otp_user_configreg_i11; + input fabric_otp_user_configreg_i12; + input fabric_otp_user_configreg_i13; + input fabric_otp_user_configreg_i14; + input fabric_otp_user_configreg_i15; + input fabric_otp_user_configreg_i16; + input fabric_otp_user_configreg_i17; + input fabric_otp_user_configreg_i18; + input fabric_otp_user_configreg_i19; + input fabric_otp_user_configreg_i2; + input fabric_otp_user_configreg_i20; + input fabric_otp_user_configreg_i21; + input fabric_otp_user_configreg_i22; + input fabric_otp_user_configreg_i23; + input fabric_otp_user_configreg_i24; + input fabric_otp_user_configreg_i25; + input fabric_otp_user_configreg_i26; + input fabric_otp_user_configreg_i27; + input fabric_otp_user_configreg_i28; + input fabric_otp_user_configreg_i29; + input fabric_otp_user_configreg_i3; + input fabric_otp_user_configreg_i30; + input fabric_otp_user_configreg_i31; + input fabric_otp_user_configreg_i32; + input fabric_otp_user_configreg_i4; + input fabric_otp_user_configreg_i5; + input fabric_otp_user_configreg_i6; + input fabric_otp_user_configreg_i7; + input fabric_otp_user_configreg_i8; + input fabric_otp_user_configreg_i9; + output fabric_otp_user_ded_o; + input fabric_otp_user_din_i1; + input fabric_otp_user_din_i10; + input fabric_otp_user_din_i11; + input fabric_otp_user_din_i12; + input fabric_otp_user_din_i13; + input fabric_otp_user_din_i14; + input fabric_otp_user_din_i15; + input fabric_otp_user_din_i16; + input fabric_otp_user_din_i17; + input fabric_otp_user_din_i18; + input fabric_otp_user_din_i19; + input fabric_otp_user_din_i2; + input fabric_otp_user_din_i20; + input fabric_otp_user_din_i21; + input fabric_otp_user_din_i22; + input fabric_otp_user_din_i23; + input fabric_otp_user_din_i24; + input fabric_otp_user_din_i25; + input fabric_otp_user_din_i26; + input fabric_otp_user_din_i27; + input fabric_otp_user_din_i28; + input fabric_otp_user_din_i29; + input fabric_otp_user_din_i3; + input fabric_otp_user_din_i30; + input fabric_otp_user_din_i31; + input fabric_otp_user_din_i32; + input fabric_otp_user_din_i33; + input fabric_otp_user_din_i34; + input fabric_otp_user_din_i35; + input fabric_otp_user_din_i36; + input fabric_otp_user_din_i37; + input fabric_otp_user_din_i38; + input fabric_otp_user_din_i39; + input fabric_otp_user_din_i4; + input fabric_otp_user_din_i5; + input fabric_otp_user_din_i6; + input fabric_otp_user_din_i7; + input fabric_otp_user_din_i8; + input fabric_otp_user_din_i9; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output fabric_otp_user_dout_o1; + output fabric_otp_user_dout_o10; + output fabric_otp_user_dout_o11; + output fabric_otp_user_dout_o12; + output fabric_otp_user_dout_o13; + output fabric_otp_user_dout_o14; + output fabric_otp_user_dout_o15; + output fabric_otp_user_dout_o16; + output fabric_otp_user_dout_o17; + output fabric_otp_user_dout_o18; + output fabric_otp_user_dout_o19; + output fabric_otp_user_dout_o2; + output fabric_otp_user_dout_o20; + output fabric_otp_user_dout_o21; + output fabric_otp_user_dout_o22; + output fabric_otp_user_dout_o23; + output fabric_otp_user_dout_o24; + output fabric_otp_user_dout_o25; + output fabric_otp_user_dout_o26; + output fabric_otp_user_dout_o27; + output fabric_otp_user_dout_o28; + output fabric_otp_user_dout_o29; + output fabric_otp_user_dout_o3; + output fabric_otp_user_dout_o30; + output fabric_otp_user_dout_o31; + output fabric_otp_user_dout_o32; + output fabric_otp_user_dout_o33; + output fabric_otp_user_dout_o34; + output fabric_otp_user_dout_o35; + output fabric_otp_user_dout_o36; + output fabric_otp_user_dout_o37; + output fabric_otp_user_dout_o38; + output fabric_otp_user_dout_o39; + output fabric_otp_user_dout_o4; + output fabric_otp_user_dout_o40; + output fabric_otp_user_dout_o41; + output fabric_otp_user_dout_o5; + output fabric_otp_user_dout_o6; + output fabric_otp_user_dout_o7; + output fabric_otp_user_dout_o8; + output fabric_otp_user_dout_o9; + input fabric_otp_user_eccbypass_i; + output fabric_otp_user_flagstate_o1; + output fabric_otp_user_flagstate_o2; + output fabric_otp_user_flagstate_o3; + output fabric_otp_user_flagstate_o4; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input fabric_otp_user_prgwidth_i1; + input fabric_otp_user_prgwidth_i2; + input fabric_otp_user_prgwidth_i3; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output fabric_otp_user_startword_o1; + output fabric_otp_user_startword_o10; + output fabric_otp_user_startword_o11; + output fabric_otp_user_startword_o12; + output fabric_otp_user_startword_o13; + output fabric_otp_user_startword_o14; + output fabric_otp_user_startword_o15; + output fabric_otp_user_startword_o16; + output fabric_otp_user_startword_o2; + output fabric_otp_user_startword_o3; + output fabric_otp_user_startword_o4; + output fabric_otp_user_startword_o5; + output fabric_otp_user_startword_o6; + output fabric_otp_user_startword_o7; + output fabric_otp_user_startword_o8; + output fabric_otp_user_startword_o9; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input fabric_otp_user_tst_scanin_i1; + input fabric_otp_user_tst_scanin_i2; + input fabric_otp_user_tst_scanin_i3; + input fabric_otp_user_tst_scanin_i4; + input fabric_otp_user_tst_scanin_i5; + output fabric_otp_user_tst_scanout_o1; + output fabric_otp_user_tst_scanout_o2; + output fabric_otp_user_tst_scanout_o3; + output fabric_otp_user_tst_scanout_o4; + output fabric_otp_user_tst_scanout_o5; + output fabric_otp_user_wlromout_o1; + output fabric_otp_user_wlromout_o10; + output fabric_otp_user_wlromout_o2; + output fabric_otp_user_wlromout_o3; + output fabric_otp_user_wlromout_o4; + output fabric_otp_user_wlromout_o5; + output fabric_otp_user_wlromout_o6; + output fabric_otp_user_wlromout_o7; + output fabric_otp_user_wlromout_o8; + output fabric_otp_user_wlromout_o9; + input fabric_otp_user_wordlock_i; + input fabric_parusr_cs_i; + input fabric_parusr_data_i1; + input fabric_parusr_data_i10; + input fabric_parusr_data_i11; + input fabric_parusr_data_i12; + input fabric_parusr_data_i13; + input fabric_parusr_data_i14; + input fabric_parusr_data_i15; + input fabric_parusr_data_i16; + input fabric_parusr_data_i2; + input fabric_parusr_data_i3; + input fabric_parusr_data_i4; + input fabric_parusr_data_i5; + input fabric_parusr_data_i6; + input fabric_parusr_data_i7; + input fabric_parusr_data_i8; + input fabric_parusr_data_i9; + output fabric_parusr_data_o1; + output fabric_parusr_data_o10; + output fabric_parusr_data_o11; + output fabric_parusr_data_o12; + output fabric_parusr_data_o13; + output fabric_parusr_data_o14; + output fabric_parusr_data_o15; + output fabric_parusr_data_o16; + output fabric_parusr_data_o2; + output fabric_parusr_data_o3; + output fabric_parusr_data_o4; + output fabric_parusr_data_o5; + output fabric_parusr_data_o6; + output fabric_parusr_data_o7; + output fabric_parusr_data_o8; + output fabric_parusr_data_o9; + output fabric_parusr_data_val_o; + input fabric_parusr_type_i1; + input fabric_parusr_type_i2; + input fabric_pd_active_i1; + input fabric_pd_active_i10; + input fabric_pd_active_i11; + input fabric_pd_active_i12; + input fabric_pd_active_i13; + input fabric_pd_active_i14; + input fabric_pd_active_i15; + input fabric_pd_active_i16; + input fabric_pd_active_i17; + input fabric_pd_active_i18; + input fabric_pd_active_i19; + input fabric_pd_active_i2; + input fabric_pd_active_i20; + input fabric_pd_active_i21; + input fabric_pd_active_i22; + input fabric_pd_active_i23; + input fabric_pd_active_i24; + input fabric_pd_active_i3; + input fabric_pd_active_i4; + input fabric_pd_active_i5; + input fabric_pd_active_i6; + input fabric_pd_active_i7; + input fabric_pd_active_i8; + input fabric_pd_active_i9; + output fabric_pd_ready_o1; + output fabric_pd_ready_o10; + output fabric_pd_ready_o11; + output fabric_pd_ready_o12; + output fabric_pd_ready_o13; + output fabric_pd_ready_o14; + output fabric_pd_ready_o15; + output fabric_pd_ready_o16; + output fabric_pd_ready_o17; + output fabric_pd_ready_o18; + output fabric_pd_ready_o19; + output fabric_pd_ready_o2; + output fabric_pd_ready_o20; + output fabric_pd_ready_o21; + output fabric_pd_ready_o22; + output fabric_pd_ready_o23; + output fabric_pd_ready_o24; + output fabric_pd_ready_o3; + output fabric_pd_ready_o4; + output fabric_pd_ready_o5; + output fabric_pd_ready_o6; + output fabric_pd_ready_o7; + output fabric_pd_ready_o8; + output fabric_pd_ready_o9; + input fabric_shift_en_i1; + input fabric_shift_en_i10; + input fabric_shift_en_i11; + input fabric_shift_en_i12; + input fabric_shift_en_i13; + input fabric_shift_en_i14; + input fabric_shift_en_i15; + input fabric_shift_en_i16; + input fabric_shift_en_i17; + input fabric_shift_en_i18; + input fabric_shift_en_i19; + input fabric_shift_en_i2; + input fabric_shift_en_i20; + input fabric_shift_en_i21; + input fabric_shift_en_i22; + input fabric_shift_en_i23; + input fabric_shift_en_i24; + input fabric_shift_en_i3; + input fabric_shift_en_i4; + input fabric_shift_en_i5; + input fabric_shift_en_i6; + input fabric_shift_en_i7; + input fabric_shift_en_i8; + input fabric_shift_en_i9; + output fabric_shift_en_to_bist_o1; + output fabric_shift_en_to_bist_o10; + output fabric_shift_en_to_bist_o11; + output fabric_shift_en_to_bist_o12; + output fabric_shift_en_to_bist_o13; + output fabric_shift_en_to_bist_o14; + output fabric_shift_en_to_bist_o15; + output fabric_shift_en_to_bist_o16; + output fabric_shift_en_to_bist_o17; + output fabric_shift_en_to_bist_o18; + output fabric_shift_en_to_bist_o19; + output fabric_shift_en_to_bist_o2; + output fabric_shift_en_to_bist_o20; + output fabric_shift_en_to_bist_o21; + output fabric_shift_en_to_bist_o22; + output fabric_shift_en_to_bist_o23; + output fabric_shift_en_to_bist_o24; + output fabric_shift_en_to_bist_o3; + output fabric_shift_en_to_bist_o4; + output fabric_shift_en_to_bist_o5; + output fabric_shift_en_to_bist_o6; + output fabric_shift_en_to_bist_o7; + output fabric_shift_en_to_bist_o8; + output fabric_shift_en_to_bist_o9; + input fabric_sif_load_en_i1; + input fabric_sif_load_en_i10; + input fabric_sif_load_en_i11; + input fabric_sif_load_en_i12; + input fabric_sif_load_en_i13; + input fabric_sif_load_en_i14; + input fabric_sif_load_en_i15; + input fabric_sif_load_en_i16; + input fabric_sif_load_en_i17; + input fabric_sif_load_en_i18; + input fabric_sif_load_en_i19; + input fabric_sif_load_en_i2; + input fabric_sif_load_en_i20; + input fabric_sif_load_en_i21; + input fabric_sif_load_en_i22; + input fabric_sif_load_en_i23; + input fabric_sif_load_en_i24; + input fabric_sif_load_en_i3; + input fabric_sif_load_en_i4; + input fabric_sif_load_en_i5; + input fabric_sif_load_en_i6; + input fabric_sif_load_en_i7; + input fabric_sif_load_en_i8; + input fabric_sif_load_en_i9; + output fabric_sif_load_en_to_bist_o1; + output fabric_sif_load_en_to_bist_o10; + output fabric_sif_load_en_to_bist_o11; + output fabric_sif_load_en_to_bist_o12; + output fabric_sif_load_en_to_bist_o13; + output fabric_sif_load_en_to_bist_o14; + output fabric_sif_load_en_to_bist_o15; + output fabric_sif_load_en_to_bist_o16; + output fabric_sif_load_en_to_bist_o17; + output fabric_sif_load_en_to_bist_o18; + output fabric_sif_load_en_to_bist_o19; + output fabric_sif_load_en_to_bist_o2; + output fabric_sif_load_en_to_bist_o20; + output fabric_sif_load_en_to_bist_o21; + output fabric_sif_load_en_to_bist_o22; + output fabric_sif_load_en_to_bist_o23; + output fabric_sif_load_en_to_bist_o24; + output fabric_sif_load_en_to_bist_o3; + output fabric_sif_load_en_to_bist_o4; + output fabric_sif_load_en_to_bist_o5; + output fabric_sif_load_en_to_bist_o6; + output fabric_sif_load_en_to_bist_o7; + output fabric_sif_load_en_to_bist_o8; + output fabric_sif_load_en_to_bist_o9; + input fabric_sif_reg_en_i1; + input fabric_sif_reg_en_i10; + input fabric_sif_reg_en_i100; + input fabric_sif_reg_en_i101; + input fabric_sif_reg_en_i102; + input fabric_sif_reg_en_i103; + input fabric_sif_reg_en_i104; + input fabric_sif_reg_en_i105; + input fabric_sif_reg_en_i106; + input fabric_sif_reg_en_i107; + input fabric_sif_reg_en_i108; + input fabric_sif_reg_en_i109; + input fabric_sif_reg_en_i11; + input fabric_sif_reg_en_i110; + input fabric_sif_reg_en_i111; + input fabric_sif_reg_en_i112; + input fabric_sif_reg_en_i113; + input fabric_sif_reg_en_i114; + input fabric_sif_reg_en_i115; + input fabric_sif_reg_en_i116; + input fabric_sif_reg_en_i117; + input fabric_sif_reg_en_i118; + input fabric_sif_reg_en_i119; + input fabric_sif_reg_en_i12; + input fabric_sif_reg_en_i120; + input fabric_sif_reg_en_i13; + input fabric_sif_reg_en_i14; + input fabric_sif_reg_en_i15; + input fabric_sif_reg_en_i16; + input fabric_sif_reg_en_i17; + input fabric_sif_reg_en_i18; + input fabric_sif_reg_en_i19; + input fabric_sif_reg_en_i2; + input fabric_sif_reg_en_i20; + input fabric_sif_reg_en_i21; + input fabric_sif_reg_en_i22; + input fabric_sif_reg_en_i23; + input fabric_sif_reg_en_i24; + input fabric_sif_reg_en_i25; + input fabric_sif_reg_en_i26; + input fabric_sif_reg_en_i27; + input fabric_sif_reg_en_i28; + input fabric_sif_reg_en_i29; + input fabric_sif_reg_en_i3; + input fabric_sif_reg_en_i30; + input fabric_sif_reg_en_i31; + input fabric_sif_reg_en_i32; + input fabric_sif_reg_en_i33; + input fabric_sif_reg_en_i34; + input fabric_sif_reg_en_i35; + input fabric_sif_reg_en_i36; + input fabric_sif_reg_en_i37; + input fabric_sif_reg_en_i38; + input fabric_sif_reg_en_i39; + input fabric_sif_reg_en_i4; + input fabric_sif_reg_en_i40; + input fabric_sif_reg_en_i41; + input fabric_sif_reg_en_i42; + input fabric_sif_reg_en_i43; + input fabric_sif_reg_en_i44; + input fabric_sif_reg_en_i45; + input fabric_sif_reg_en_i46; + input fabric_sif_reg_en_i47; + input fabric_sif_reg_en_i48; + input fabric_sif_reg_en_i49; + input fabric_sif_reg_en_i5; + input fabric_sif_reg_en_i50; + input fabric_sif_reg_en_i51; + input fabric_sif_reg_en_i52; + input fabric_sif_reg_en_i53; + input fabric_sif_reg_en_i54; + input fabric_sif_reg_en_i55; + input fabric_sif_reg_en_i56; + input fabric_sif_reg_en_i57; + input fabric_sif_reg_en_i58; + input fabric_sif_reg_en_i59; + input fabric_sif_reg_en_i6; + input fabric_sif_reg_en_i60; + input fabric_sif_reg_en_i61; + input fabric_sif_reg_en_i62; + input fabric_sif_reg_en_i63; + input fabric_sif_reg_en_i64; + input fabric_sif_reg_en_i65; + input fabric_sif_reg_en_i66; + input fabric_sif_reg_en_i67; + input fabric_sif_reg_en_i68; + input fabric_sif_reg_en_i69; + input fabric_sif_reg_en_i7; + input fabric_sif_reg_en_i70; + input fabric_sif_reg_en_i71; + input fabric_sif_reg_en_i72; + input fabric_sif_reg_en_i73; + input fabric_sif_reg_en_i74; + input fabric_sif_reg_en_i75; + input fabric_sif_reg_en_i76; + input fabric_sif_reg_en_i77; + input fabric_sif_reg_en_i78; + input fabric_sif_reg_en_i79; + input fabric_sif_reg_en_i8; + input fabric_sif_reg_en_i80; + input fabric_sif_reg_en_i81; + input fabric_sif_reg_en_i82; + input fabric_sif_reg_en_i83; + input fabric_sif_reg_en_i84; + input fabric_sif_reg_en_i85; + input fabric_sif_reg_en_i86; + input fabric_sif_reg_en_i87; + input fabric_sif_reg_en_i88; + input fabric_sif_reg_en_i89; + input fabric_sif_reg_en_i9; + input fabric_sif_reg_en_i90; + input fabric_sif_reg_en_i91; + input fabric_sif_reg_en_i92; + input fabric_sif_reg_en_i93; + input fabric_sif_reg_en_i94; + input fabric_sif_reg_en_i95; + input fabric_sif_reg_en_i96; + input fabric_sif_reg_en_i97; + input fabric_sif_reg_en_i98; + input fabric_sif_reg_en_i99; + output fabric_sif_reg_en_to_bist_o1; + output fabric_sif_reg_en_to_bist_o10; + output fabric_sif_reg_en_to_bist_o100; + output fabric_sif_reg_en_to_bist_o101; + output fabric_sif_reg_en_to_bist_o102; + output fabric_sif_reg_en_to_bist_o103; + output fabric_sif_reg_en_to_bist_o104; + output fabric_sif_reg_en_to_bist_o105; + output fabric_sif_reg_en_to_bist_o106; + output fabric_sif_reg_en_to_bist_o107; + output fabric_sif_reg_en_to_bist_o108; + output fabric_sif_reg_en_to_bist_o109; + output fabric_sif_reg_en_to_bist_o11; + output fabric_sif_reg_en_to_bist_o110; + output fabric_sif_reg_en_to_bist_o111; + output fabric_sif_reg_en_to_bist_o112; + output fabric_sif_reg_en_to_bist_o113; + output fabric_sif_reg_en_to_bist_o114; + output fabric_sif_reg_en_to_bist_o115; + output fabric_sif_reg_en_to_bist_o116; + output fabric_sif_reg_en_to_bist_o117; + output fabric_sif_reg_en_to_bist_o118; + output fabric_sif_reg_en_to_bist_o119; + output fabric_sif_reg_en_to_bist_o12; + output fabric_sif_reg_en_to_bist_o120; + output fabric_sif_reg_en_to_bist_o13; + output fabric_sif_reg_en_to_bist_o14; + output fabric_sif_reg_en_to_bist_o15; + output fabric_sif_reg_en_to_bist_o16; + output fabric_sif_reg_en_to_bist_o17; + output fabric_sif_reg_en_to_bist_o18; + output fabric_sif_reg_en_to_bist_o19; + output fabric_sif_reg_en_to_bist_o2; + output fabric_sif_reg_en_to_bist_o20; + output fabric_sif_reg_en_to_bist_o21; + output fabric_sif_reg_en_to_bist_o22; + output fabric_sif_reg_en_to_bist_o23; + output fabric_sif_reg_en_to_bist_o24; + output fabric_sif_reg_en_to_bist_o25; + output fabric_sif_reg_en_to_bist_o26; + output fabric_sif_reg_en_to_bist_o27; + output fabric_sif_reg_en_to_bist_o28; + output fabric_sif_reg_en_to_bist_o29; + output fabric_sif_reg_en_to_bist_o3; + output fabric_sif_reg_en_to_bist_o30; + output fabric_sif_reg_en_to_bist_o31; + output fabric_sif_reg_en_to_bist_o32; + output fabric_sif_reg_en_to_bist_o33; + output fabric_sif_reg_en_to_bist_o34; + output fabric_sif_reg_en_to_bist_o35; + output fabric_sif_reg_en_to_bist_o36; + output fabric_sif_reg_en_to_bist_o37; + output fabric_sif_reg_en_to_bist_o38; + output fabric_sif_reg_en_to_bist_o39; + output fabric_sif_reg_en_to_bist_o4; + output fabric_sif_reg_en_to_bist_o40; + output fabric_sif_reg_en_to_bist_o41; + output fabric_sif_reg_en_to_bist_o42; + output fabric_sif_reg_en_to_bist_o43; + output fabric_sif_reg_en_to_bist_o44; + output fabric_sif_reg_en_to_bist_o45; + output fabric_sif_reg_en_to_bist_o46; + output fabric_sif_reg_en_to_bist_o47; + output fabric_sif_reg_en_to_bist_o48; + output fabric_sif_reg_en_to_bist_o49; + output fabric_sif_reg_en_to_bist_o5; + output fabric_sif_reg_en_to_bist_o50; + output fabric_sif_reg_en_to_bist_o51; + output fabric_sif_reg_en_to_bist_o52; + output fabric_sif_reg_en_to_bist_o53; + output fabric_sif_reg_en_to_bist_o54; + output fabric_sif_reg_en_to_bist_o55; + output fabric_sif_reg_en_to_bist_o56; + output fabric_sif_reg_en_to_bist_o57; + output fabric_sif_reg_en_to_bist_o58; + output fabric_sif_reg_en_to_bist_o59; + output fabric_sif_reg_en_to_bist_o6; + output fabric_sif_reg_en_to_bist_o60; + output fabric_sif_reg_en_to_bist_o61; + output fabric_sif_reg_en_to_bist_o62; + output fabric_sif_reg_en_to_bist_o63; + output fabric_sif_reg_en_to_bist_o64; + output fabric_sif_reg_en_to_bist_o65; + output fabric_sif_reg_en_to_bist_o66; + output fabric_sif_reg_en_to_bist_o67; + output fabric_sif_reg_en_to_bist_o68; + output fabric_sif_reg_en_to_bist_o69; + output fabric_sif_reg_en_to_bist_o7; + output fabric_sif_reg_en_to_bist_o70; + output fabric_sif_reg_en_to_bist_o71; + output fabric_sif_reg_en_to_bist_o72; + output fabric_sif_reg_en_to_bist_o73; + output fabric_sif_reg_en_to_bist_o74; + output fabric_sif_reg_en_to_bist_o75; + output fabric_sif_reg_en_to_bist_o76; + output fabric_sif_reg_en_to_bist_o77; + output fabric_sif_reg_en_to_bist_o78; + output fabric_sif_reg_en_to_bist_o79; + output fabric_sif_reg_en_to_bist_o8; + output fabric_sif_reg_en_to_bist_o80; + output fabric_sif_reg_en_to_bist_o81; + output fabric_sif_reg_en_to_bist_o82; + output fabric_sif_reg_en_to_bist_o83; + output fabric_sif_reg_en_to_bist_o84; + output fabric_sif_reg_en_to_bist_o85; + output fabric_sif_reg_en_to_bist_o86; + output fabric_sif_reg_en_to_bist_o87; + output fabric_sif_reg_en_to_bist_o88; + output fabric_sif_reg_en_to_bist_o89; + output fabric_sif_reg_en_to_bist_o9; + output fabric_sif_reg_en_to_bist_o90; + output fabric_sif_reg_en_to_bist_o91; + output fabric_sif_reg_en_to_bist_o92; + output fabric_sif_reg_en_to_bist_o93; + output fabric_sif_reg_en_to_bist_o94; + output fabric_sif_reg_en_to_bist_o95; + output fabric_sif_reg_en_to_bist_o96; + output fabric_sif_reg_en_to_bist_o97; + output fabric_sif_reg_en_to_bist_o98; + output fabric_sif_reg_en_to_bist_o99; + input fabric_sif_update_en_i1; + input fabric_sif_update_en_i10; + input fabric_sif_update_en_i11; + input fabric_sif_update_en_i12; + input fabric_sif_update_en_i13; + input fabric_sif_update_en_i14; + input fabric_sif_update_en_i15; + input fabric_sif_update_en_i16; + input fabric_sif_update_en_i17; + input fabric_sif_update_en_i18; + input fabric_sif_update_en_i19; + input fabric_sif_update_en_i2; + input fabric_sif_update_en_i20; + input fabric_sif_update_en_i21; + input fabric_sif_update_en_i22; + input fabric_sif_update_en_i23; + input fabric_sif_update_en_i24; + input fabric_sif_update_en_i3; + input fabric_sif_update_en_i4; + input fabric_sif_update_en_i5; + input fabric_sif_update_en_i6; + input fabric_sif_update_en_i7; + input fabric_sif_update_en_i8; + input fabric_sif_update_en_i9; + output fabric_sif_update_en_to_bist_o1; + output fabric_sif_update_en_to_bist_o10; + output fabric_sif_update_en_to_bist_o11; + output fabric_sif_update_en_to_bist_o12; + output fabric_sif_update_en_to_bist_o13; + output fabric_sif_update_en_to_bist_o14; + output fabric_sif_update_en_to_bist_o15; + output fabric_sif_update_en_to_bist_o16; + output fabric_sif_update_en_to_bist_o17; + output fabric_sif_update_en_to_bist_o18; + output fabric_sif_update_en_to_bist_o19; + output fabric_sif_update_en_to_bist_o2; + output fabric_sif_update_en_to_bist_o20; + output fabric_sif_update_en_to_bist_o21; + output fabric_sif_update_en_to_bist_o22; + output fabric_sif_update_en_to_bist_o23; + output fabric_sif_update_en_to_bist_o24; + output fabric_sif_update_en_to_bist_o3; + output fabric_sif_update_en_to_bist_o4; + output fabric_sif_update_en_to_bist_o5; + output fabric_sif_update_en_to_bist_o6; + output fabric_sif_update_en_to_bist_o7; + output fabric_sif_update_en_to_bist_o8; + output fabric_sif_update_en_to_bist_o9; + input fabric_spare_i1; + input fabric_spare_i2; + input fabric_spare_i3; + output fabric_status_cold_start_o; + output fabric_system_data_from_mem_bist_o1; + output fabric_system_data_from_mem_bist_o10; + output fabric_system_data_from_mem_bist_o11; + output fabric_system_data_from_mem_bist_o12; + output fabric_system_data_from_mem_bist_o13; + output fabric_system_data_from_mem_bist_o14; + output fabric_system_data_from_mem_bist_o15; + output fabric_system_data_from_mem_bist_o16; + output fabric_system_data_from_mem_bist_o17; + output fabric_system_data_from_mem_bist_o18; + output fabric_system_data_from_mem_bist_o19; + output fabric_system_data_from_mem_bist_o2; + output fabric_system_data_from_mem_bist_o20; + output fabric_system_data_from_mem_bist_o21; + output fabric_system_data_from_mem_bist_o22; + output fabric_system_data_from_mem_bist_o23; + output fabric_system_data_from_mem_bist_o24; + output fabric_system_data_from_mem_bist_o3; + output fabric_system_data_from_mem_bist_o4; + output fabric_system_data_from_mem_bist_o5; + output fabric_system_data_from_mem_bist_o6; + output fabric_system_data_from_mem_bist_o7; + output fabric_system_data_from_mem_bist_o8; + output fabric_system_data_from_mem_bist_o9; + input fabric_system_data_to_mem_bist_i1; + input fabric_system_data_to_mem_bist_i10; + input fabric_system_data_to_mem_bist_i11; + input fabric_system_data_to_mem_bist_i12; + input fabric_system_data_to_mem_bist_i13; + input fabric_system_data_to_mem_bist_i14; + input fabric_system_data_to_mem_bist_i15; + input fabric_system_data_to_mem_bist_i16; + input fabric_system_data_to_mem_bist_i17; + input fabric_system_data_to_mem_bist_i18; + input fabric_system_data_to_mem_bist_i19; + input fabric_system_data_to_mem_bist_i2; + input fabric_system_data_to_mem_bist_i20; + input fabric_system_data_to_mem_bist_i21; + input fabric_system_data_to_mem_bist_i22; + input fabric_system_data_to_mem_bist_i23; + input fabric_system_data_to_mem_bist_i24; + input fabric_system_data_to_mem_bist_i3; + input fabric_system_data_to_mem_bist_i4; + input fabric_system_data_to_mem_bist_i5; + input fabric_system_data_to_mem_bist_i6; + input fabric_system_data_to_mem_bist_i7; + input fabric_system_data_to_mem_bist_i8; + input fabric_system_data_to_mem_bist_i9; + output fabric_system_dataready_o; + input fabric_tst_atpg_mrepair_i; + input fabric_user_data_i1; + input fabric_user_data_i10; + input fabric_user_data_i11; + input fabric_user_data_i12; + input fabric_user_data_i13; + input fabric_user_data_i14; + input fabric_user_data_i15; + input fabric_user_data_i16; + input fabric_user_data_i17; + input fabric_user_data_i18; + input fabric_user_data_i19; + input fabric_user_data_i2; + input fabric_user_data_i20; + input fabric_user_data_i21; + input fabric_user_data_i22; + input fabric_user_data_i23; + input fabric_user_data_i24; + input fabric_user_data_i25; + input fabric_user_data_i26; + input fabric_user_data_i27; + input fabric_user_data_i28; + input fabric_user_data_i29; + input fabric_user_data_i3; + input fabric_user_data_i30; + input fabric_user_data_i31; + input fabric_user_data_i32; + input fabric_user_data_i4; + input fabric_user_data_i5; + input fabric_user_data_i6; + input fabric_user_data_i7; + input fabric_user_data_i8; + input fabric_user_data_i9; + output fabric_user_data_o1; + output fabric_user_data_o10; + output fabric_user_data_o11; + output fabric_user_data_o12; + output fabric_user_data_o13; + output fabric_user_data_o14; + output fabric_user_data_o15; + output fabric_user_data_o16; + output fabric_user_data_o17; + output fabric_user_data_o18; + output fabric_user_data_o19; + output fabric_user_data_o2; + output fabric_user_data_o20; + output fabric_user_data_o21; + output fabric_user_data_o22; + output fabric_user_data_o23; + output fabric_user_data_o24; + output fabric_user_data_o25; + output fabric_user_data_o26; + output fabric_user_data_o27; + output fabric_user_data_o28; + output fabric_user_data_o29; + output fabric_user_data_o3; + output fabric_user_data_o30; + output fabric_user_data_o31; + output fabric_user_data_o32; + output fabric_user_data_o4; + output fabric_user_data_o5; + output fabric_user_data_o6; + output fabric_user_data_o7; + output fabric_user_data_o8; + output fabric_user_data_o9; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_U_V1_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i +, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i +, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o +, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_flag_ready_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o +, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o +, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o +, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o +, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_spare_i +, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_mrepair_fuse_configreg_i, fabric_system_data_to_mem_bist_i, fabric_otp_user_configreg_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o +); + input [31:0] fabric_ahb_direct_data_i; + output [31:0] fabric_ahb_direct_data_o; + output fabric_cfg_fabric_user_flag_o; + output fabric_cfg_fabric_user_unmask_o; + output [71:0] fabric_chip_status_o; + input [23:0] fabric_data_from_bist_i; + input fabric_data_from_system_i; + input fabric_data_shift_en_i; + output [23:0] fabric_data_to_bist_o; + output fabric_data_to_system_o; + output fabric_debug_access_reg_data_ready_o; + output [31:0] fabric_debug_bsec_core_status_o; + output [3:0] fabric_debug_cpt_retry_o; + output [3:0] fabric_debug_direct_permission_read_o; + output [3:0] fabric_debug_direct_permission_write_o; + output fabric_debug_error_o; + output [3:0] fabric_debug_frame_permission_frame_o; + output fabric_debug_frame_use_encryption_o; + output [2:0] fabric_debug_fsm_state_o; + output fabric_debug_key_correct_o; + output [3:0] fabric_debug_lifecycle_o; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output [2:0] fabric_debug_otpapb_state_o; + output [7:0] fabric_debug_otpboot_curr_addr_o; + output [2:0] fabric_debug_otpboot_state_o; + output [2:0] fabric_debug_otpmgmt_state_o; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + output fabric_decoder_init_ready_o; + input [31:0] fabric_direct_data_i; + output [31:0] fabric_direct_data_o; + input fabric_end_encoding_i; + output fabric_flag_error_o; + output fabric_flag_ready_o; + output fabric_flag_trigger_o; + output [2:0] fabric_fuse_status_o; + output [2:0] fabric_global_chip_status_o; + input [24:0] fabric_io_in_i; + input [24:0] fabric_io_oe_i; + output [24:0] fabric_io_out_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + output fabric_mrepair_fuse_ack_o; + input [6:0] fabric_mrepair_fuse_add_i; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output [7:0] fabric_mrepair_fuse_bist1fail_o; + output [6:0] fabric_mrepair_fuse_bist2fail_o; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + input [31:0] fabric_mrepair_fuse_configreg_i; + output fabric_mrepair_fuse_ded_o; + input [38:0] fabric_mrepair_fuse_din_i; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output [40:0] fabric_mrepair_fuse_dout_o; + input fabric_mrepair_fuse_eccbypass_i; + output [3:0] fabric_mrepair_fuse_flagstate_o; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input [2:0] fabric_mrepair_fuse_prgwidth_i; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output [15:0] fabric_mrepair_fuse_startword_o; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input [4:0] fabric_mrepair_fuse_tst_scanin_i; + input fabric_mrepair_fuse_tstscanenable_i; + output [4:0] fabric_mrepair_fuse_tstscanout_o; + output [9:0] fabric_mrepair_fuse_wlromout_o; + input fabric_mrepair_fuse_wordlock_i; + input fabric_mrepair_initn_i; + input [3:0] fabric_mrepair_mode_i; + input fabric_mrepair_por_i; + input fabric_mrepair_rst_n_i; + input [31:0] fabric_otp_apb_addr_i; + input fabric_otp_apb_enable_i; + output [31:0] fabric_otp_apb_rdata_o; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input [31:0] fabric_otp_apb_wdata_i; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_rstn_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output [7:0] fabric_otp_security_bist_fail1_o; + output [6:0] fabric_otp_security_bist_fail2_o; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input [4:0] fabric_otp_security_scanin_i; + output [4:0] fabric_otp_security_scanout_o; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input [6:0] fabric_otp_user_add_i; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output [7:0] fabric_otp_user_bist1fail_o; + output [6:0] fabric_otp_user_bist2fail_o; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input [31:0] fabric_otp_user_configreg_i; + output fabric_otp_user_ded_o; + input [38:0] fabric_otp_user_din_i; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output [40:0] fabric_otp_user_dout_o; + input fabric_otp_user_eccbypass_i; + output [3:0] fabric_otp_user_flagstate_o; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input [2:0] fabric_otp_user_prgwidth_i; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output [15:0] fabric_otp_user_startword_o; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input [4:0] fabric_otp_user_tst_scanin_i; + output [4:0] fabric_otp_user_tst_scanout_o; + output [9:0] fabric_otp_user_wlromout_o; + input fabric_otp_user_wordlock_i; + input fabric_parusr_cs_i; + input [15:0] fabric_parusr_data_i; + output [15:0] fabric_parusr_data_o; + output fabric_parusr_data_val_o; + input [1:0] fabric_parusr_type_i; + input [23:0] fabric_pd_active_i; + output [23:0] fabric_pd_ready_o; + input [23:0] fabric_shift_en_i; + output [23:0] fabric_shift_en_to_bist_o; + input [23:0] fabric_sif_load_en_i; + output [23:0] fabric_sif_load_en_to_bist_o; + input [119:0] fabric_sif_reg_en_i; + output [119:0] fabric_sif_reg_en_to_bist_o; + input [23:0] fabric_sif_update_en_i; + output [23:0] fabric_sif_update_en_to_bist_o; + input [2:0] fabric_spare_i; + output fabric_status_cold_start_o; + output [23:0] fabric_system_data_from_mem_bist_o; + input [23:0] fabric_system_data_to_mem_bist_i; + output fabric_system_dataready_o; + input fabric_tst_atpg_mrepair_i; + input [31:0] fabric_user_data_i; + output [31:0] fabric_user_data_o; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SERVICE_U_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i +, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i +, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o +, fabric_otp_security_bist_bad_o, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o +, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o +, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o +, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i +, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o +, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_system_data_to_mem_bist_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o +); + input [31:0] fabric_ahb_direct_data_i; + output [31:0] fabric_ahb_direct_data_o; + output fabric_cfg_fabric_user_enable_o; + output fabric_cfg_fabric_user_flag_o; + output [71:0] fabric_chip_status_o; + input fabric_clk_otp_mux_i; + input [23:0] fabric_data_from_bist_i; + input fabric_data_from_system_i; + input fabric_data_shift_en_i; + output [23:0] fabric_data_to_bist_o; + output fabric_data_to_system_o; + output fabric_debug_access_reg_data_ready_o; + output [31:0] fabric_debug_bsec_core_status_o; + output [3:0] fabric_debug_cpt_retry_o; + output [3:0] fabric_debug_direct_permission_read_o; + output [3:0] fabric_debug_direct_permission_write_o; + output fabric_debug_error_o; + output [3:0] fabric_debug_frame_permission_frame_o; + output fabric_debug_frame_use_encryption_o; + output [2:0] fabric_debug_fsm_state_o; + output fabric_debug_key_correct_o; + output [3:0] fabric_debug_lifecycle_o; + output fabric_debug_lock_reg_o; + output fabric_debug_otp_manager_read_done_o; + output fabric_debug_otp_manager_read_otp_o; + output fabric_debug_otp_reload_err_o; + output [2:0] fabric_debug_otpapb_state_o; + output [7:0] fabric_debug_otpboot_curr_addr_o; + output [2:0] fabric_debug_otpboot_state_o; + output [2:0] fabric_debug_otpmgmt_state_o; + output fabric_debug_rst_soft_o; + output fabric_debug_security_boot_done_o; + output fabric_debug_security_error_read_o; + output fabric_decoder_init_ready_o; + input [31:0] fabric_direct_data_i; + output [31:0] fabric_direct_data_o; + input fabric_end_encoding_i; + output fabric_flag_error_o; + output [2:0] fabric_flag_ready_TMR_o; + output fabric_flag_trigger_o; + output [2:0] fabric_fuse_status_o; + output [2:0] fabric_global_chip_status_o; + input [24:0] fabric_io_in_i; + input [24:0] fabric_io_oe_i; + output [24:0] fabric_io_out_o; + output fabric_jtag_tdi_o; + input fabric_jtag_tdo_usr1_i; + input fabric_jtag_tdo_usr2_i; + output fabric_jtag_tms_o; + output fabric_jtag_trst_n_o; + output fabric_jtag_usr1_o; + output fabric_jtag_usr2_o; + input fabric_lowskew_i20; + input fabric_lowskew_i21; + input fabric_lowskew_i22; + input fabric_lowskew_i23; + output fabric_lowskew_o3; + output fabric_lowskew_o4; + output fabric_lowskew_o5; + output fabric_lowskew_o6; + input fabric_mrepair_cke_force_i; + input fabric_mrepair_cke_i; + output fabric_mrepair_fuse_ack_o; + input [6:0] fabric_mrepair_fuse_add_i; + output fabric_mrepair_fuse_bbad_o; + output fabric_mrepair_fuse_bend1_o; + output fabric_mrepair_fuse_bend2_o; + output [7:0] fabric_mrepair_fuse_bist1fail_o; + output [6:0] fabric_mrepair_fuse_bist2fail_o; + input fabric_mrepair_fuse_bistmode_i; + output fabric_mrepair_fuse_calibrated_o; + output fabric_mrepair_fuse_ded_o; + input [38:0] fabric_mrepair_fuse_din_i; + input fabric_mrepair_fuse_disturbchecked_i; + output fabric_mrepair_fuse_disturbed_o; + output [40:0] fabric_mrepair_fuse_dout_o; + input fabric_mrepair_fuse_eccbypass_i; + output [3:0] fabric_mrepair_fuse_flagstate_o; + output fabric_mrepair_fuse_locked_o; + input fabric_mrepair_fuse_pdn_i; + output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; + input [2:0] fabric_mrepair_fuse_prgwidth_i; + input fabric_mrepair_fuse_prog_i; + output fabric_mrepair_fuse_progfail_o; + output fabric_mrepair_fuse_pwok_o; + input fabric_mrepair_fuse_rbact1_i; + input fabric_mrepair_fuse_rbact2_i; + input fabric_mrepair_fuse_read_i; + output fabric_mrepair_fuse_ready_o; + input fabric_mrepair_fuse_redbypass_i; + output fabric_mrepair_fuse_sec_o; + output [15:0] fabric_mrepair_fuse_startword_o; + input fabric_mrepair_fuse_suppadd_i; + input fabric_mrepair_fuse_tm_i; + input [4:0] fabric_mrepair_fuse_tst_scanin_i; + input fabric_mrepair_fuse_tstscanenable_i; + output [4:0] fabric_mrepair_fuse_tstscanout_o; + output [9:0] fabric_mrepair_fuse_wlromout_o; + input fabric_mrepair_fuse_wordlock_i; + input [3:0] fabric_mrepair_mode_i; + input fabric_mrepair_por_i; + input [31:0] fabric_otp_apb_addr_i; + input fabric_otp_apb_enable_i; + output [31:0] fabric_otp_apb_rdata_o; + output fabric_otp_apb_ready_o; + input fabric_otp_apb_sel_i; + input [31:0] fabric_otp_apb_wdata_i; + input fabric_otp_apb_write_i; + input fabric_otp_cfg_clk_fab_en_i; + input fabric_otp_cfg_clk_otpm_disable_i; + input fabric_otp_cfg_fabric_apb_en_i; + input fabric_otp_cfg_loader_read_en_i; + input fabric_otp_cfg_loader_write_en_i; + input fabric_otp_rst_i; + output fabric_otp_security_ack_o; + output fabric_otp_security_bist_bad_o; + output fabric_otp_security_bist_end1_o; + output fabric_otp_security_bist_end2_o; + output [7:0] fabric_otp_security_bist_fail1_o; + output [6:0] fabric_otp_security_bist_fail2_o; + input fabric_otp_security_bistmode_i; + input fabric_otp_security_force_pdn1_i; + input fabric_otp_security_rbact1_i; + input fabric_otp_security_rbact2_i; + input fabric_otp_security_scanenable_i; + input [4:0] fabric_otp_security_scanin_i; + output [4:0] fabric_otp_security_scanout_o; + input fabric_otp_security_testmode_i; + output fabric_otp_user_ack_o; + input [6:0] fabric_otp_user_add_i; + output fabric_otp_user_bbad_o; + output fabric_otp_user_bend1_o; + output fabric_otp_user_bend2_o; + output [7:0] fabric_otp_user_bist1fail_o; + output [6:0] fabric_otp_user_bist2fail_o; + input fabric_otp_user_bistmode_i; + output fabric_otp_user_calibrated_o; + input fabric_otp_user_clock_frequency_range_i; + output fabric_otp_user_ded_o; + input [38:0] fabric_otp_user_din_i; + input fabric_otp_user_disturbcheck_i; + output fabric_otp_user_disturbed_o; + output [40:0] fabric_otp_user_dout_o; + input fabric_otp_user_eccbypass_i; + output [3:0] fabric_otp_user_flagstate_o; + output fabric_otp_user_locked_o; + input fabric_otp_user_pdn_i; + input [2:0] fabric_otp_user_prgwidth_i; + input fabric_otp_user_prog_i; + output fabric_otp_user_progfail_o; + output fabric_otp_user_pwok_o; + input fabric_otp_user_rbact1_i; + input fabric_otp_user_rbact2_i; + input fabric_otp_user_read_i; + input fabric_otp_user_redbypass_i; + output fabric_otp_user_sec_o; + output [15:0] fabric_otp_user_startword_o; + input fabric_otp_user_suppadd_i; + input fabric_otp_user_tm_i; + input fabric_otp_user_tst_scanenable_i; + input [4:0] fabric_otp_user_tst_scanin_i; + output [4:0] fabric_otp_user_tst_scanout_o; + output [9:0] fabric_otp_user_wlromout_o; + input fabric_otp_user_wordlock_i; + input fabric_parusr_cs_i; + input [15:0] fabric_parusr_data_i; + output [15:0] fabric_parusr_data_o; + output fabric_parusr_data_val_o; + input fabric_parusr_enable_i; + input [1:0] fabric_parusr_type_i; + input [23:0] fabric_pd_active_i; + output [23:0] fabric_pd_ready_o; + input [23:0] fabric_shift_en_i; + output [23:0] fabric_shift_en_to_bist_o; + input [23:0] fabric_sif_load_en_i; + output [23:0] fabric_sif_load_en_to_bist_o; + input [119:0] fabric_sif_reg_en_i; + output [119:0] fabric_sif_reg_en_to_bist_o; + input [23:0] fabric_sif_update_en_i; + output [23:0] fabric_sif_update_en_to_bist_o; + output fabric_status_cold_start_o; + output [23:0] fabric_system_data_from_mem_bist_o; + input [23:0] fabric_system_data_to_mem_bist_i; + output fabric_system_dataready_o; + input fabric_tst_atpg_mrepair_i; + input [31:0] fabric_user_data_i; + output [31:0] fabric_user_data_o; + output fabric_user_read_cycle_o; + output fabric_user_write_cycle_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SOC_INTERFACE(fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2 +, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3 +, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16 +, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37 +, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58 +, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79 +, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100 +, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i +, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21 +, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42 +, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3 +, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24 +, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3 +, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8 +, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5 +, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26 +, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1 +, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1 +, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6 +, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27 +, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48 +, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69 +, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90 +, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111 +, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3 +, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4 +, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10 +, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31 +, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52 +, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73 +, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94 +, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115 +, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8 +, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12 +, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33 +, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8 +, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1 +, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14 +, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35 +, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10 +, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3 +, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15 +, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36 +, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57 +, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, fabric_fpga_wdata_axi_s2_o68, fabric_fpga_wdata_axi_s2_o69, fabric_fpga_wdata_axi_s2_o70, fabric_fpga_wdata_axi_s2_o71, fabric_fpga_wdata_axi_s2_o72, fabric_fpga_wdata_axi_s2_o73, fabric_fpga_wdata_axi_s2_o74, fabric_fpga_wdata_axi_s2_o75, fabric_fpga_wdata_axi_s2_o76, fabric_fpga_wdata_axi_s2_o77, fabric_fpga_wdata_axi_s2_o78 +, fabric_fpga_wdata_axi_s2_o79, fabric_fpga_wdata_axi_s2_o80, fabric_fpga_wdata_axi_s2_o81, fabric_fpga_wdata_axi_s2_o82, fabric_fpga_wdata_axi_s2_o83, fabric_fpga_wdata_axi_s2_o84, fabric_fpga_wdata_axi_s2_o85, fabric_fpga_wdata_axi_s2_o86, fabric_fpga_wdata_axi_s2_o87, fabric_fpga_wdata_axi_s2_o88, fabric_fpga_wdata_axi_s2_o89, fabric_fpga_wdata_axi_s2_o90, fabric_fpga_wdata_axi_s2_o91, fabric_fpga_wdata_axi_s2_o92, fabric_fpga_wdata_axi_s2_o93, fabric_fpga_wdata_axi_s2_o94, fabric_fpga_wdata_axi_s2_o95, fabric_fpga_wdata_axi_s2_o96, fabric_fpga_wdata_axi_s2_o97, fabric_fpga_wdata_axi_s2_o98, fabric_fpga_wdata_axi_s2_o99 +, fabric_fpga_wdata_axi_s2_o100, fabric_fpga_wdata_axi_s2_o101, fabric_fpga_wdata_axi_s2_o102, fabric_fpga_wdata_axi_s2_o103, fabric_fpga_wdata_axi_s2_o104, fabric_fpga_wdata_axi_s2_o105, fabric_fpga_wdata_axi_s2_o106, fabric_fpga_wdata_axi_s2_o107, fabric_fpga_wdata_axi_s2_o108, fabric_fpga_wdata_axi_s2_o109, fabric_fpga_wdata_axi_s2_o110, fabric_fpga_wdata_axi_s2_o111, fabric_fpga_wdata_axi_s2_o112, fabric_fpga_wdata_axi_s2_o113, fabric_fpga_wdata_axi_s2_o114, fabric_fpga_wdata_axi_s2_o115, fabric_fpga_wdata_axi_s2_o116, fabric_fpga_wdata_axi_s2_o117, fabric_fpga_wdata_axi_s2_o118, fabric_fpga_wdata_axi_s2_o119, fabric_fpga_wdata_axi_s2_o120 +, fabric_fpga_wdata_axi_s2_o121, fabric_fpga_wdata_axi_s2_o122, fabric_fpga_wdata_axi_s2_o123, fabric_fpga_wdata_axi_s2_o124, fabric_fpga_wdata_axi_s2_o125, fabric_fpga_wdata_axi_s2_o126, fabric_fpga_wdata_axi_s2_o127, fabric_fpga_wdata_axi_s2_o128, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wstrb_axi_s2_o1, fabric_fpga_wstrb_axi_s2_o2, fabric_fpga_wstrb_axi_s2_o3, fabric_fpga_wstrb_axi_s2_o4, fabric_fpga_wstrb_axi_s2_o5, fabric_fpga_wstrb_axi_s2_o6, fabric_fpga_wstrb_axi_s2_o7, fabric_fpga_wstrb_axi_s2_o8, fabric_fpga_wstrb_axi_s2_o9, fabric_fpga_wstrb_axi_s2_o10, fabric_fpga_wstrb_axi_s2_o11, fabric_fpga_wstrb_axi_s2_o12 +, fabric_fpga_wstrb_axi_s2_o13, fabric_fpga_wstrb_axi_s2_o14, fabric_fpga_wstrb_axi_s2_o15, fabric_fpga_wstrb_axi_s2_o16, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bid_axi_s2_i1, fabric_fpga_bid_axi_s2_i2, fabric_fpga_bid_axi_s2_i3, fabric_fpga_bid_axi_s2_i4, fabric_fpga_bid_axi_s2_i5, fabric_fpga_bid_axi_s2_i6, fabric_fpga_bid_axi_s2_i7, fabric_fpga_bid_axi_s2_i8, fabric_fpga_bid_axi_s2_i9, fabric_fpga_bid_axi_s2_i10, fabric_fpga_bid_axi_s2_i11, fabric_fpga_bid_axi_s2_i12, fabric_fpga_bresp_axi_s2_i1 +, fabric_fpga_bresp_axi_s2_i2, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rdata_axi_s2_i1, fabric_fpga_rdata_axi_s2_i2, fabric_fpga_rdata_axi_s2_i3, fabric_fpga_rdata_axi_s2_i4, fabric_fpga_rdata_axi_s2_i5, fabric_fpga_rdata_axi_s2_i6, fabric_fpga_rdata_axi_s2_i7, fabric_fpga_rdata_axi_s2_i8, fabric_fpga_rdata_axi_s2_i9, fabric_fpga_rdata_axi_s2_i10, fabric_fpga_rdata_axi_s2_i11, fabric_fpga_rdata_axi_s2_i12, fabric_fpga_rdata_axi_s2_i13, fabric_fpga_rdata_axi_s2_i14, fabric_fpga_rdata_axi_s2_i15, fabric_fpga_rdata_axi_s2_i16, fabric_fpga_rdata_axi_s2_i17, fabric_fpga_rdata_axi_s2_i18, fabric_fpga_rdata_axi_s2_i19 +, fabric_fpga_rdata_axi_s2_i20, fabric_fpga_rdata_axi_s2_i21, fabric_fpga_rdata_axi_s2_i22, fabric_fpga_rdata_axi_s2_i23, fabric_fpga_rdata_axi_s2_i24, fabric_fpga_rdata_axi_s2_i25, fabric_fpga_rdata_axi_s2_i26, fabric_fpga_rdata_axi_s2_i27, fabric_fpga_rdata_axi_s2_i28, fabric_fpga_rdata_axi_s2_i29, fabric_fpga_rdata_axi_s2_i30, fabric_fpga_rdata_axi_s2_i31, fabric_fpga_rdata_axi_s2_i32, fabric_fpga_rdata_axi_s2_i33, fabric_fpga_rdata_axi_s2_i34, fabric_fpga_rdata_axi_s2_i35, fabric_fpga_rdata_axi_s2_i36, fabric_fpga_rdata_axi_s2_i37, fabric_fpga_rdata_axi_s2_i38, fabric_fpga_rdata_axi_s2_i39, fabric_fpga_rdata_axi_s2_i40 +, fabric_fpga_rdata_axi_s2_i41, fabric_fpga_rdata_axi_s2_i42, fabric_fpga_rdata_axi_s2_i43, fabric_fpga_rdata_axi_s2_i44, fabric_fpga_rdata_axi_s2_i45, fabric_fpga_rdata_axi_s2_i46, fabric_fpga_rdata_axi_s2_i47, fabric_fpga_rdata_axi_s2_i48, fabric_fpga_rdata_axi_s2_i49, fabric_fpga_rdata_axi_s2_i50, fabric_fpga_rdata_axi_s2_i51, fabric_fpga_rdata_axi_s2_i52, fabric_fpga_rdata_axi_s2_i53, fabric_fpga_rdata_axi_s2_i54, fabric_fpga_rdata_axi_s2_i55, fabric_fpga_rdata_axi_s2_i56, fabric_fpga_rdata_axi_s2_i57, fabric_fpga_rdata_axi_s2_i58, fabric_fpga_rdata_axi_s2_i59, fabric_fpga_rdata_axi_s2_i60, fabric_fpga_rdata_axi_s2_i61 +, fabric_fpga_rdata_axi_s2_i62, fabric_fpga_rdata_axi_s2_i63, fabric_fpga_rdata_axi_s2_i64, fabric_fpga_rdata_axi_s2_i65, fabric_fpga_rdata_axi_s2_i66, fabric_fpga_rdata_axi_s2_i67, fabric_fpga_rdata_axi_s2_i68, fabric_fpga_rdata_axi_s2_i69, fabric_fpga_rdata_axi_s2_i70, fabric_fpga_rdata_axi_s2_i71, fabric_fpga_rdata_axi_s2_i72, fabric_fpga_rdata_axi_s2_i73, fabric_fpga_rdata_axi_s2_i74, fabric_fpga_rdata_axi_s2_i75, fabric_fpga_rdata_axi_s2_i76, fabric_fpga_rdata_axi_s2_i77, fabric_fpga_rdata_axi_s2_i78, fabric_fpga_rdata_axi_s2_i79, fabric_fpga_rdata_axi_s2_i80, fabric_fpga_rdata_axi_s2_i81, fabric_fpga_rdata_axi_s2_i82 +, fabric_fpga_rdata_axi_s2_i83, fabric_fpga_rdata_axi_s2_i84, fabric_fpga_rdata_axi_s2_i85, fabric_fpga_rdata_axi_s2_i86, fabric_fpga_rdata_axi_s2_i87, fabric_fpga_rdata_axi_s2_i88, fabric_fpga_rdata_axi_s2_i89, fabric_fpga_rdata_axi_s2_i90, fabric_fpga_rdata_axi_s2_i91, fabric_fpga_rdata_axi_s2_i92, fabric_fpga_rdata_axi_s2_i93, fabric_fpga_rdata_axi_s2_i94, fabric_fpga_rdata_axi_s2_i95, fabric_fpga_rdata_axi_s2_i96, fabric_fpga_rdata_axi_s2_i97, fabric_fpga_rdata_axi_s2_i98, fabric_fpga_rdata_axi_s2_i99, fabric_fpga_rdata_axi_s2_i100, fabric_fpga_rdata_axi_s2_i101, fabric_fpga_rdata_axi_s2_i102, fabric_fpga_rdata_axi_s2_i103 +, fabric_fpga_rdata_axi_s2_i104, fabric_fpga_rdata_axi_s2_i105, fabric_fpga_rdata_axi_s2_i106, fabric_fpga_rdata_axi_s2_i107, fabric_fpga_rdata_axi_s2_i108, fabric_fpga_rdata_axi_s2_i109, fabric_fpga_rdata_axi_s2_i110, fabric_fpga_rdata_axi_s2_i111, fabric_fpga_rdata_axi_s2_i112, fabric_fpga_rdata_axi_s2_i113, fabric_fpga_rdata_axi_s2_i114, fabric_fpga_rdata_axi_s2_i115, fabric_fpga_rdata_axi_s2_i116, fabric_fpga_rdata_axi_s2_i117, fabric_fpga_rdata_axi_s2_i118, fabric_fpga_rdata_axi_s2_i119, fabric_fpga_rdata_axi_s2_i120, fabric_fpga_rdata_axi_s2_i121, fabric_fpga_rdata_axi_s2_i122, fabric_fpga_rdata_axi_s2_i123, fabric_fpga_rdata_axi_s2_i124 +, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i +, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bid_axi_m1_o1, fabric_fpga_bid_axi_m1_o2, fabric_fpga_bid_axi_m1_o3, fabric_fpga_bid_axi_m1_o4, fabric_fpga_bid_axi_m1_o5, fabric_fpga_bresp_axi_m1_o1, fabric_fpga_bresp_axi_m1_o2, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_dma_ack_m1_o1, fabric_fpga_dma_ack_m1_o2, fabric_fpga_dma_ack_m1_o3, fabric_fpga_dma_ack_m1_o4, fabric_fpga_dma_ack_m1_o5, fabric_fpga_dma_ack_m1_o6, fabric_fpga_dma_finish_m1_o1, fabric_fpga_dma_finish_m1_o2, fabric_fpga_dma_finish_m1_o3, fabric_fpga_dma_finish_m1_o4, fabric_fpga_dma_finish_m1_o5 +, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20 +, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41 +, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62 +, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83 +, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104 +, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125 +, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8 +, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29 +, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4 +, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i +, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21 +, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2 +, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3 +, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6 +, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14 +, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35 +, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56 +, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77 +, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98 +, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119 +, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11 +, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5 +, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14 +, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35 +, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56 +, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77 +, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98 +, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119 +, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2 +, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23 +, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2 +, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2 +, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15 +, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36 +, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6 +, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6 +, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8 +, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29 +, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50 +, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71 +, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92 +, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113 +, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5 +, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2 +, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20 +, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41 +, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62 +, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83 +, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104 +, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125 +, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8 +, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29 +, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4 +, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i +, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21 +, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2 +, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3 +, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11 +, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32 +, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53 +, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74 +, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95 +, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116 +, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8 +, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12 +, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o +, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20 +, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8 +, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29 +, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16 +, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3 +, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8 +, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9 +, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30 +, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1 +, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o +, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21 +, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2 +, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8 +, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29 +, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1 +, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22 +, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5 +, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s_o1, fabric_llpp1_arqos_s_o2 +, fabric_llpp1_arqos_s_o3, fabric_llpp1_arqos_s_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15 +, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2 +, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7 +, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6 +, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27 +, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8 +, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14 +, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3 +, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7 +, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28 +, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11 +, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o +, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21 +, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4 +, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1 +, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12 +, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o +, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2 +, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20 +, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9 +, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13 +, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2 +, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5 +, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6 +, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27 +, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10 +, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3 +, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18 +, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i +, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5 +, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26 +, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2 +, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19 +, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6 +, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27 +, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15 +, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o +, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20 +, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7 +, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28 +, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13 +, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o +, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21 +, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4 +, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25 +, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46 +, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67 +, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88 +, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109 +, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2 +, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13 +, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2 +, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23 +, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44 +, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1 +, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22 +, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4 +, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25 +, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46 +, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67 +, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88 +, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109 +, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2 +, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15 +, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i +, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i +, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_spw_interrupts_toggle_o1 +, fabric_spw_interrupts_toggle_o2, fabric_spw_interrupts_toggle_o3, fabric_spw_interrupts_o1, fabric_spw_interrupts_o2, fabric_spw_interrupts_o3, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_fpga_dma_hs_rstn_i1, fabric_fpga_dma_hs_rstn_i2, fabric_fpga_dma_hs_rstn_i3, fabric_fpga_dma_hs_rstn_i4, fabric_fpga_dma_hs_rstn_i5, fabric_fpga_dma_hs_rstn_i6); + input fabric_enable_TMR_i1; + input fabric_enable_TMR_i2; + input fabric_enable_TMR_i3; + input fabric_erom_fpga_cpu0_dbgen_i; + input fabric_erom_fpga_cpu0_hiden_i; + input fabric_erom_fpga_cpu0_hniden_i; + input fabric_erom_fpga_cpu0_niden_i; + input fabric_erom_fpga_cpu1_dbgen_i; + input fabric_erom_fpga_cpu1_hiden_i; + input fabric_erom_fpga_cpu1_hniden_i; + input fabric_erom_fpga_cpu1_niden_i; + input fabric_erom_fpga_cpu2_dbgen_i; + input fabric_erom_fpga_cpu2_hiden_i; + input fabric_erom_fpga_cpu2_hniden_i; + input fabric_erom_fpga_cpu2_niden_i; + input fabric_erom_fpga_cpu3_dbgen_i; + input fabric_erom_fpga_cpu3_hiden_i; + input fabric_erom_fpga_cpu3_hniden_i; + input fabric_erom_fpga_cpu3_niden_i; + input fabric_erom_fpga_cs_dbgen_i; + input fabric_erom_fpga_cs_deviceen_i; + input fabric_erom_fpga_cs_niden_i; + input fabric_erom_fpga_cs_rst_n_i; + input fabric_erom_fpga_debug_en_i; + output fabric_flash_irq_o; + output fabric_flash_irq_toggle_o; + input fabric_fpga_araddr_axi_m1_i1; + input fabric_fpga_araddr_axi_m1_i10; + input fabric_fpga_araddr_axi_m1_i11; + input fabric_fpga_araddr_axi_m1_i12; + input fabric_fpga_araddr_axi_m1_i13; + input fabric_fpga_araddr_axi_m1_i14; + input fabric_fpga_araddr_axi_m1_i15; + input fabric_fpga_araddr_axi_m1_i16; + input fabric_fpga_araddr_axi_m1_i17; + input fabric_fpga_araddr_axi_m1_i18; + input fabric_fpga_araddr_axi_m1_i19; + input fabric_fpga_araddr_axi_m1_i2; + input fabric_fpga_araddr_axi_m1_i20; + input fabric_fpga_araddr_axi_m1_i21; + input fabric_fpga_araddr_axi_m1_i22; + input fabric_fpga_araddr_axi_m1_i23; + input fabric_fpga_araddr_axi_m1_i24; + input fabric_fpga_araddr_axi_m1_i25; + input fabric_fpga_araddr_axi_m1_i26; + input fabric_fpga_araddr_axi_m1_i27; + input fabric_fpga_araddr_axi_m1_i28; + input fabric_fpga_araddr_axi_m1_i29; + input fabric_fpga_araddr_axi_m1_i3; + input fabric_fpga_araddr_axi_m1_i30; + input fabric_fpga_araddr_axi_m1_i31; + input fabric_fpga_araddr_axi_m1_i32; + input fabric_fpga_araddr_axi_m1_i33; + input fabric_fpga_araddr_axi_m1_i34; + input fabric_fpga_araddr_axi_m1_i35; + input fabric_fpga_araddr_axi_m1_i36; + input fabric_fpga_araddr_axi_m1_i37; + input fabric_fpga_araddr_axi_m1_i38; + input fabric_fpga_araddr_axi_m1_i39; + input fabric_fpga_araddr_axi_m1_i4; + input fabric_fpga_araddr_axi_m1_i40; + input fabric_fpga_araddr_axi_m1_i5; + input fabric_fpga_araddr_axi_m1_i6; + input fabric_fpga_araddr_axi_m1_i7; + input fabric_fpga_araddr_axi_m1_i8; + input fabric_fpga_araddr_axi_m1_i9; + input fabric_fpga_araddr_axi_m2_i1; + input fabric_fpga_araddr_axi_m2_i10; + input fabric_fpga_araddr_axi_m2_i11; + input fabric_fpga_araddr_axi_m2_i12; + input fabric_fpga_araddr_axi_m2_i13; + input fabric_fpga_araddr_axi_m2_i14; + input fabric_fpga_araddr_axi_m2_i15; + input fabric_fpga_araddr_axi_m2_i16; + input fabric_fpga_araddr_axi_m2_i17; + input fabric_fpga_araddr_axi_m2_i18; + input fabric_fpga_araddr_axi_m2_i19; + input fabric_fpga_araddr_axi_m2_i2; + input fabric_fpga_araddr_axi_m2_i20; + input fabric_fpga_araddr_axi_m2_i21; + input fabric_fpga_araddr_axi_m2_i22; + input fabric_fpga_araddr_axi_m2_i23; + input fabric_fpga_araddr_axi_m2_i24; + input fabric_fpga_araddr_axi_m2_i25; + input fabric_fpga_araddr_axi_m2_i26; + input fabric_fpga_araddr_axi_m2_i27; + input fabric_fpga_araddr_axi_m2_i28; + input fabric_fpga_araddr_axi_m2_i29; + input fabric_fpga_araddr_axi_m2_i3; + input fabric_fpga_araddr_axi_m2_i30; + input fabric_fpga_araddr_axi_m2_i31; + input fabric_fpga_araddr_axi_m2_i32; + input fabric_fpga_araddr_axi_m2_i33; + input fabric_fpga_araddr_axi_m2_i34; + input fabric_fpga_araddr_axi_m2_i35; + input fabric_fpga_araddr_axi_m2_i36; + input fabric_fpga_araddr_axi_m2_i37; + input fabric_fpga_araddr_axi_m2_i38; + input fabric_fpga_araddr_axi_m2_i39; + input fabric_fpga_araddr_axi_m2_i4; + input fabric_fpga_araddr_axi_m2_i40; + input fabric_fpga_araddr_axi_m2_i5; + input fabric_fpga_araddr_axi_m2_i6; + input fabric_fpga_araddr_axi_m2_i7; + input fabric_fpga_araddr_axi_m2_i8; + input fabric_fpga_araddr_axi_m2_i9; + output fabric_fpga_araddr_axi_s1_o1; + output fabric_fpga_araddr_axi_s1_o10; + output fabric_fpga_araddr_axi_s1_o11; + output fabric_fpga_araddr_axi_s1_o12; + output fabric_fpga_araddr_axi_s1_o13; + output fabric_fpga_araddr_axi_s1_o14; + output fabric_fpga_araddr_axi_s1_o15; + output fabric_fpga_araddr_axi_s1_o16; + output fabric_fpga_araddr_axi_s1_o17; + output fabric_fpga_araddr_axi_s1_o18; + output fabric_fpga_araddr_axi_s1_o19; + output fabric_fpga_araddr_axi_s1_o2; + output fabric_fpga_araddr_axi_s1_o20; + output fabric_fpga_araddr_axi_s1_o21; + output fabric_fpga_araddr_axi_s1_o22; + output fabric_fpga_araddr_axi_s1_o23; + output fabric_fpga_araddr_axi_s1_o24; + output fabric_fpga_araddr_axi_s1_o25; + output fabric_fpga_araddr_axi_s1_o26; + output fabric_fpga_araddr_axi_s1_o27; + output fabric_fpga_araddr_axi_s1_o28; + output fabric_fpga_araddr_axi_s1_o29; + output fabric_fpga_araddr_axi_s1_o3; + output fabric_fpga_araddr_axi_s1_o30; + output fabric_fpga_araddr_axi_s1_o31; + output fabric_fpga_araddr_axi_s1_o32; + output fabric_fpga_araddr_axi_s1_o33; + output fabric_fpga_araddr_axi_s1_o34; + output fabric_fpga_araddr_axi_s1_o35; + output fabric_fpga_araddr_axi_s1_o36; + output fabric_fpga_araddr_axi_s1_o37; + output fabric_fpga_araddr_axi_s1_o38; + output fabric_fpga_araddr_axi_s1_o39; + output fabric_fpga_araddr_axi_s1_o4; + output fabric_fpga_araddr_axi_s1_o40; + output fabric_fpga_araddr_axi_s1_o5; + output fabric_fpga_araddr_axi_s1_o6; + output fabric_fpga_araddr_axi_s1_o7; + output fabric_fpga_araddr_axi_s1_o8; + output fabric_fpga_araddr_axi_s1_o9; + output fabric_fpga_araddr_axi_s2_o1; + output fabric_fpga_araddr_axi_s2_o10; + output fabric_fpga_araddr_axi_s2_o11; + output fabric_fpga_araddr_axi_s2_o12; + output fabric_fpga_araddr_axi_s2_o13; + output fabric_fpga_araddr_axi_s2_o14; + output fabric_fpga_araddr_axi_s2_o15; + output fabric_fpga_araddr_axi_s2_o16; + output fabric_fpga_araddr_axi_s2_o17; + output fabric_fpga_araddr_axi_s2_o18; + output fabric_fpga_araddr_axi_s2_o19; + output fabric_fpga_araddr_axi_s2_o2; + output fabric_fpga_araddr_axi_s2_o20; + output fabric_fpga_araddr_axi_s2_o21; + output fabric_fpga_araddr_axi_s2_o22; + output fabric_fpga_araddr_axi_s2_o23; + output fabric_fpga_araddr_axi_s2_o24; + output fabric_fpga_araddr_axi_s2_o25; + output fabric_fpga_araddr_axi_s2_o26; + output fabric_fpga_araddr_axi_s2_o27; + output fabric_fpga_araddr_axi_s2_o28; + output fabric_fpga_araddr_axi_s2_o29; + output fabric_fpga_araddr_axi_s2_o3; + output fabric_fpga_araddr_axi_s2_o30; + output fabric_fpga_araddr_axi_s2_o31; + output fabric_fpga_araddr_axi_s2_o32; + output fabric_fpga_araddr_axi_s2_o33; + output fabric_fpga_araddr_axi_s2_o34; + output fabric_fpga_araddr_axi_s2_o35; + output fabric_fpga_araddr_axi_s2_o36; + output fabric_fpga_araddr_axi_s2_o37; + output fabric_fpga_araddr_axi_s2_o38; + output fabric_fpga_araddr_axi_s2_o39; + output fabric_fpga_araddr_axi_s2_o4; + output fabric_fpga_araddr_axi_s2_o40; + output fabric_fpga_araddr_axi_s2_o5; + output fabric_fpga_araddr_axi_s2_o6; + output fabric_fpga_araddr_axi_s2_o7; + output fabric_fpga_araddr_axi_s2_o8; + output fabric_fpga_araddr_axi_s2_o9; + input fabric_fpga_arburst_axi_m1_i1; + input fabric_fpga_arburst_axi_m1_i2; + input fabric_fpga_arburst_axi_m2_i1; + input fabric_fpga_arburst_axi_m2_i2; + output fabric_fpga_arburst_axi_s1_o1; + output fabric_fpga_arburst_axi_s1_o2; + output fabric_fpga_arburst_axi_s2_o1; + output fabric_fpga_arburst_axi_s2_o2; + input fabric_fpga_arcache_axi_m1_i1; + input fabric_fpga_arcache_axi_m1_i2; + input fabric_fpga_arcache_axi_m1_i3; + input fabric_fpga_arcache_axi_m1_i4; + input fabric_fpga_arcache_axi_m2_i1; + input fabric_fpga_arcache_axi_m2_i2; + input fabric_fpga_arcache_axi_m2_i3; + input fabric_fpga_arcache_axi_m2_i4; + output fabric_fpga_arcache_axi_s1_o1; + output fabric_fpga_arcache_axi_s1_o2; + output fabric_fpga_arcache_axi_s1_o3; + output fabric_fpga_arcache_axi_s1_o4; + output fabric_fpga_arcache_axi_s2_o1; + output fabric_fpga_arcache_axi_s2_o2; + output fabric_fpga_arcache_axi_s2_o3; + output fabric_fpga_arcache_axi_s2_o4; + input fabric_fpga_arid_axi_m1_i1; + input fabric_fpga_arid_axi_m1_i2; + input fabric_fpga_arid_axi_m1_i3; + input fabric_fpga_arid_axi_m1_i4; + input fabric_fpga_arid_axi_m1_i5; + input fabric_fpga_arid_axi_m2_i1; + input fabric_fpga_arid_axi_m2_i2; + input fabric_fpga_arid_axi_m2_i3; + input fabric_fpga_arid_axi_m2_i4; + input fabric_fpga_arid_axi_m2_i5; + output fabric_fpga_arid_axi_s1_o1; + output fabric_fpga_arid_axi_s1_o10; + output fabric_fpga_arid_axi_s1_o11; + output fabric_fpga_arid_axi_s1_o12; + output fabric_fpga_arid_axi_s1_o2; + output fabric_fpga_arid_axi_s1_o3; + output fabric_fpga_arid_axi_s1_o4; + output fabric_fpga_arid_axi_s1_o5; + output fabric_fpga_arid_axi_s1_o6; + output fabric_fpga_arid_axi_s1_o7; + output fabric_fpga_arid_axi_s1_o8; + output fabric_fpga_arid_axi_s1_o9; + output fabric_fpga_arid_axi_s2_o1; + output fabric_fpga_arid_axi_s2_o10; + output fabric_fpga_arid_axi_s2_o11; + output fabric_fpga_arid_axi_s2_o12; + output fabric_fpga_arid_axi_s2_o2; + output fabric_fpga_arid_axi_s2_o3; + output fabric_fpga_arid_axi_s2_o4; + output fabric_fpga_arid_axi_s2_o5; + output fabric_fpga_arid_axi_s2_o6; + output fabric_fpga_arid_axi_s2_o7; + output fabric_fpga_arid_axi_s2_o8; + output fabric_fpga_arid_axi_s2_o9; + input fabric_fpga_arlen_axi_m1_i1; + input fabric_fpga_arlen_axi_m1_i2; + input fabric_fpga_arlen_axi_m1_i3; + input fabric_fpga_arlen_axi_m1_i4; + input fabric_fpga_arlen_axi_m1_i5; + input fabric_fpga_arlen_axi_m1_i6; + input fabric_fpga_arlen_axi_m1_i7; + input fabric_fpga_arlen_axi_m1_i8; + input fabric_fpga_arlen_axi_m2_i1; + input fabric_fpga_arlen_axi_m2_i2; + input fabric_fpga_arlen_axi_m2_i3; + input fabric_fpga_arlen_axi_m2_i4; + input fabric_fpga_arlen_axi_m2_i5; + input fabric_fpga_arlen_axi_m2_i6; + input fabric_fpga_arlen_axi_m2_i7; + input fabric_fpga_arlen_axi_m2_i8; + output fabric_fpga_arlen_axi_s1_o1; + output fabric_fpga_arlen_axi_s1_o2; + output fabric_fpga_arlen_axi_s1_o3; + output fabric_fpga_arlen_axi_s1_o4; + output fabric_fpga_arlen_axi_s1_o5; + output fabric_fpga_arlen_axi_s1_o6; + output fabric_fpga_arlen_axi_s1_o7; + output fabric_fpga_arlen_axi_s1_o8; + output fabric_fpga_arlen_axi_s2_o1; + output fabric_fpga_arlen_axi_s2_o2; + output fabric_fpga_arlen_axi_s2_o3; + output fabric_fpga_arlen_axi_s2_o4; + output fabric_fpga_arlen_axi_s2_o5; + output fabric_fpga_arlen_axi_s2_o6; + output fabric_fpga_arlen_axi_s2_o7; + output fabric_fpga_arlen_axi_s2_o8; + input fabric_fpga_arlock_axi_m1_i; + input fabric_fpga_arlock_axi_m2_i; + output fabric_fpga_arlock_axi_s1_o; + output fabric_fpga_arlock_axi_s2_o; + input fabric_fpga_arprot_axi_m1_i1; + input fabric_fpga_arprot_axi_m1_i2; + input fabric_fpga_arprot_axi_m1_i3; + input fabric_fpga_arprot_axi_m2_i1; + input fabric_fpga_arprot_axi_m2_i2; + input fabric_fpga_arprot_axi_m2_i3; + output fabric_fpga_arprot_axi_s1_o1; + output fabric_fpga_arprot_axi_s1_o2; + output fabric_fpga_arprot_axi_s1_o3; + output fabric_fpga_arprot_axi_s2_o1; + output fabric_fpga_arprot_axi_s2_o2; + output fabric_fpga_arprot_axi_s2_o3; + input fabric_fpga_arqos_axi_m1_i1; + input fabric_fpga_arqos_axi_m1_i2; + input fabric_fpga_arqos_axi_m1_i3; + input fabric_fpga_arqos_axi_m1_i4; + input fabric_fpga_arqos_axi_m2_i1; + input fabric_fpga_arqos_axi_m2_i2; + input fabric_fpga_arqos_axi_m2_i3; + input fabric_fpga_arqos_axi_m2_i4; + output fabric_fpga_arqos_axi_s1_o1; + output fabric_fpga_arqos_axi_s1_o2; + output fabric_fpga_arqos_axi_s1_o3; + output fabric_fpga_arqos_axi_s1_o4; + output fabric_fpga_arqos_axi_s2_o1; + output fabric_fpga_arqos_axi_s2_o2; + output fabric_fpga_arqos_axi_s2_o3; + output fabric_fpga_arqos_axi_s2_o4; + output fabric_fpga_arready_axi_m1_o; + output fabric_fpga_arready_axi_m2_o; + input fabric_fpga_arready_axi_s1_i; + input fabric_fpga_arready_axi_s2_i; + output fabric_fpga_arregion_axi_s1_o1; + output fabric_fpga_arregion_axi_s1_o2; + output fabric_fpga_arregion_axi_s1_o3; + output fabric_fpga_arregion_axi_s1_o4; + output fabric_fpga_arregion_axi_s2_o1; + output fabric_fpga_arregion_axi_s2_o2; + output fabric_fpga_arregion_axi_s2_o3; + output fabric_fpga_arregion_axi_s2_o4; + input fabric_fpga_arsize_axi_m1_i1; + input fabric_fpga_arsize_axi_m1_i2; + input fabric_fpga_arsize_axi_m1_i3; + input fabric_fpga_arsize_axi_m2_i1; + input fabric_fpga_arsize_axi_m2_i2; + input fabric_fpga_arsize_axi_m2_i3; + output fabric_fpga_arsize_axi_s1_o1; + output fabric_fpga_arsize_axi_s1_o2; + output fabric_fpga_arsize_axi_s1_o3; + output fabric_fpga_arsize_axi_s2_o1; + output fabric_fpga_arsize_axi_s2_o2; + output fabric_fpga_arsize_axi_s2_o3; + input fabric_fpga_arvalid_axi_m1_i; + input fabric_fpga_arvalid_axi_m2_i; + output fabric_fpga_arvalid_axi_s1_o; + output fabric_fpga_arvalid_axi_s2_o; + input fabric_fpga_awaddr_axi_m1_i1; + input fabric_fpga_awaddr_axi_m1_i10; + input fabric_fpga_awaddr_axi_m1_i11; + input fabric_fpga_awaddr_axi_m1_i12; + input fabric_fpga_awaddr_axi_m1_i13; + input fabric_fpga_awaddr_axi_m1_i14; + input fabric_fpga_awaddr_axi_m1_i15; + input fabric_fpga_awaddr_axi_m1_i16; + input fabric_fpga_awaddr_axi_m1_i17; + input fabric_fpga_awaddr_axi_m1_i18; + input fabric_fpga_awaddr_axi_m1_i19; + input fabric_fpga_awaddr_axi_m1_i2; + input fabric_fpga_awaddr_axi_m1_i20; + input fabric_fpga_awaddr_axi_m1_i21; + input fabric_fpga_awaddr_axi_m1_i22; + input fabric_fpga_awaddr_axi_m1_i23; + input fabric_fpga_awaddr_axi_m1_i24; + input fabric_fpga_awaddr_axi_m1_i25; + input fabric_fpga_awaddr_axi_m1_i26; + input fabric_fpga_awaddr_axi_m1_i27; + input fabric_fpga_awaddr_axi_m1_i28; + input fabric_fpga_awaddr_axi_m1_i29; + input fabric_fpga_awaddr_axi_m1_i3; + input fabric_fpga_awaddr_axi_m1_i30; + input fabric_fpga_awaddr_axi_m1_i31; + input fabric_fpga_awaddr_axi_m1_i32; + input fabric_fpga_awaddr_axi_m1_i33; + input fabric_fpga_awaddr_axi_m1_i34; + input fabric_fpga_awaddr_axi_m1_i35; + input fabric_fpga_awaddr_axi_m1_i36; + input fabric_fpga_awaddr_axi_m1_i37; + input fabric_fpga_awaddr_axi_m1_i38; + input fabric_fpga_awaddr_axi_m1_i39; + input fabric_fpga_awaddr_axi_m1_i4; + input fabric_fpga_awaddr_axi_m1_i40; + input fabric_fpga_awaddr_axi_m1_i5; + input fabric_fpga_awaddr_axi_m1_i6; + input fabric_fpga_awaddr_axi_m1_i7; + input fabric_fpga_awaddr_axi_m1_i8; + input fabric_fpga_awaddr_axi_m1_i9; + input fabric_fpga_awaddr_axi_m2_i1; + input fabric_fpga_awaddr_axi_m2_i10; + input fabric_fpga_awaddr_axi_m2_i11; + input fabric_fpga_awaddr_axi_m2_i12; + input fabric_fpga_awaddr_axi_m2_i13; + input fabric_fpga_awaddr_axi_m2_i14; + input fabric_fpga_awaddr_axi_m2_i15; + input fabric_fpga_awaddr_axi_m2_i16; + input fabric_fpga_awaddr_axi_m2_i17; + input fabric_fpga_awaddr_axi_m2_i18; + input fabric_fpga_awaddr_axi_m2_i19; + input fabric_fpga_awaddr_axi_m2_i2; + input fabric_fpga_awaddr_axi_m2_i20; + input fabric_fpga_awaddr_axi_m2_i21; + input fabric_fpga_awaddr_axi_m2_i22; + input fabric_fpga_awaddr_axi_m2_i23; + input fabric_fpga_awaddr_axi_m2_i24; + input fabric_fpga_awaddr_axi_m2_i25; + input fabric_fpga_awaddr_axi_m2_i26; + input fabric_fpga_awaddr_axi_m2_i27; + input fabric_fpga_awaddr_axi_m2_i28; + input fabric_fpga_awaddr_axi_m2_i29; + input fabric_fpga_awaddr_axi_m2_i3; + input fabric_fpga_awaddr_axi_m2_i30; + input fabric_fpga_awaddr_axi_m2_i31; + input fabric_fpga_awaddr_axi_m2_i32; + input fabric_fpga_awaddr_axi_m2_i33; + input fabric_fpga_awaddr_axi_m2_i34; + input fabric_fpga_awaddr_axi_m2_i35; + input fabric_fpga_awaddr_axi_m2_i36; + input fabric_fpga_awaddr_axi_m2_i37; + input fabric_fpga_awaddr_axi_m2_i38; + input fabric_fpga_awaddr_axi_m2_i39; + input fabric_fpga_awaddr_axi_m2_i4; + input fabric_fpga_awaddr_axi_m2_i40; + input fabric_fpga_awaddr_axi_m2_i5; + input fabric_fpga_awaddr_axi_m2_i6; + input fabric_fpga_awaddr_axi_m2_i7; + input fabric_fpga_awaddr_axi_m2_i8; + input fabric_fpga_awaddr_axi_m2_i9; + output fabric_fpga_awaddr_axi_s1_o1; + output fabric_fpga_awaddr_axi_s1_o10; + output fabric_fpga_awaddr_axi_s1_o11; + output fabric_fpga_awaddr_axi_s1_o12; + output fabric_fpga_awaddr_axi_s1_o13; + output fabric_fpga_awaddr_axi_s1_o14; + output fabric_fpga_awaddr_axi_s1_o15; + output fabric_fpga_awaddr_axi_s1_o16; + output fabric_fpga_awaddr_axi_s1_o17; + output fabric_fpga_awaddr_axi_s1_o18; + output fabric_fpga_awaddr_axi_s1_o19; + output fabric_fpga_awaddr_axi_s1_o2; + output fabric_fpga_awaddr_axi_s1_o20; + output fabric_fpga_awaddr_axi_s1_o21; + output fabric_fpga_awaddr_axi_s1_o22; + output fabric_fpga_awaddr_axi_s1_o23; + output fabric_fpga_awaddr_axi_s1_o24; + output fabric_fpga_awaddr_axi_s1_o25; + output fabric_fpga_awaddr_axi_s1_o26; + output fabric_fpga_awaddr_axi_s1_o27; + output fabric_fpga_awaddr_axi_s1_o28; + output fabric_fpga_awaddr_axi_s1_o29; + output fabric_fpga_awaddr_axi_s1_o3; + output fabric_fpga_awaddr_axi_s1_o30; + output fabric_fpga_awaddr_axi_s1_o31; + output fabric_fpga_awaddr_axi_s1_o32; + output fabric_fpga_awaddr_axi_s1_o33; + output fabric_fpga_awaddr_axi_s1_o34; + output fabric_fpga_awaddr_axi_s1_o35; + output fabric_fpga_awaddr_axi_s1_o36; + output fabric_fpga_awaddr_axi_s1_o37; + output fabric_fpga_awaddr_axi_s1_o38; + output fabric_fpga_awaddr_axi_s1_o39; + output fabric_fpga_awaddr_axi_s1_o4; + output fabric_fpga_awaddr_axi_s1_o40; + output fabric_fpga_awaddr_axi_s1_o5; + output fabric_fpga_awaddr_axi_s1_o6; + output fabric_fpga_awaddr_axi_s1_o7; + output fabric_fpga_awaddr_axi_s1_o8; + output fabric_fpga_awaddr_axi_s1_o9; + output fabric_fpga_awaddr_axi_s2_o1; + output fabric_fpga_awaddr_axi_s2_o10; + output fabric_fpga_awaddr_axi_s2_o11; + output fabric_fpga_awaddr_axi_s2_o12; + output fabric_fpga_awaddr_axi_s2_o13; + output fabric_fpga_awaddr_axi_s2_o14; + output fabric_fpga_awaddr_axi_s2_o15; + output fabric_fpga_awaddr_axi_s2_o16; + output fabric_fpga_awaddr_axi_s2_o17; + output fabric_fpga_awaddr_axi_s2_o18; + output fabric_fpga_awaddr_axi_s2_o19; + output fabric_fpga_awaddr_axi_s2_o2; + output fabric_fpga_awaddr_axi_s2_o20; + output fabric_fpga_awaddr_axi_s2_o21; + output fabric_fpga_awaddr_axi_s2_o22; + output fabric_fpga_awaddr_axi_s2_o23; + output fabric_fpga_awaddr_axi_s2_o24; + output fabric_fpga_awaddr_axi_s2_o25; + output fabric_fpga_awaddr_axi_s2_o26; + output fabric_fpga_awaddr_axi_s2_o27; + output fabric_fpga_awaddr_axi_s2_o28; + output fabric_fpga_awaddr_axi_s2_o29; + output fabric_fpga_awaddr_axi_s2_o3; + output fabric_fpga_awaddr_axi_s2_o30; + output fabric_fpga_awaddr_axi_s2_o31; + output fabric_fpga_awaddr_axi_s2_o32; + output fabric_fpga_awaddr_axi_s2_o33; + output fabric_fpga_awaddr_axi_s2_o34; + output fabric_fpga_awaddr_axi_s2_o35; + output fabric_fpga_awaddr_axi_s2_o36; + output fabric_fpga_awaddr_axi_s2_o37; + output fabric_fpga_awaddr_axi_s2_o38; + output fabric_fpga_awaddr_axi_s2_o39; + output fabric_fpga_awaddr_axi_s2_o4; + output fabric_fpga_awaddr_axi_s2_o40; + output fabric_fpga_awaddr_axi_s2_o5; + output fabric_fpga_awaddr_axi_s2_o6; + output fabric_fpga_awaddr_axi_s2_o7; + output fabric_fpga_awaddr_axi_s2_o8; + output fabric_fpga_awaddr_axi_s2_o9; + input fabric_fpga_awburst_axi_m1_i1; + input fabric_fpga_awburst_axi_m1_i2; + input fabric_fpga_awburst_axi_m2_i1; + input fabric_fpga_awburst_axi_m2_i2; + output fabric_fpga_awburst_axi_s1_o1; + output fabric_fpga_awburst_axi_s1_o2; + output fabric_fpga_awburst_axi_s2_o1; + output fabric_fpga_awburst_axi_s2_o2; + input fabric_fpga_awcache_axi_m1_i1; + input fabric_fpga_awcache_axi_m1_i2; + input fabric_fpga_awcache_axi_m1_i3; + input fabric_fpga_awcache_axi_m1_i4; + input fabric_fpga_awcache_axi_m2_i1; + input fabric_fpga_awcache_axi_m2_i2; + input fabric_fpga_awcache_axi_m2_i3; + input fabric_fpga_awcache_axi_m2_i4; + output fabric_fpga_awcache_axi_s1_o1; + output fabric_fpga_awcache_axi_s1_o2; + output fabric_fpga_awcache_axi_s1_o3; + output fabric_fpga_awcache_axi_s1_o4; + output fabric_fpga_awcache_axi_s2_o1; + output fabric_fpga_awcache_axi_s2_o2; + output fabric_fpga_awcache_axi_s2_o3; + output fabric_fpga_awcache_axi_s2_o4; + input fabric_fpga_awid_axi_m1_i1; + input fabric_fpga_awid_axi_m1_i2; + input fabric_fpga_awid_axi_m1_i3; + input fabric_fpga_awid_axi_m1_i4; + input fabric_fpga_awid_axi_m1_i5; + input fabric_fpga_awid_axi_m2_i1; + input fabric_fpga_awid_axi_m2_i2; + input fabric_fpga_awid_axi_m2_i3; + input fabric_fpga_awid_axi_m2_i4; + input fabric_fpga_awid_axi_m2_i5; + output fabric_fpga_awid_axi_s1_o1; + output fabric_fpga_awid_axi_s1_o10; + output fabric_fpga_awid_axi_s1_o11; + output fabric_fpga_awid_axi_s1_o12; + output fabric_fpga_awid_axi_s1_o2; + output fabric_fpga_awid_axi_s1_o3; + output fabric_fpga_awid_axi_s1_o4; + output fabric_fpga_awid_axi_s1_o5; + output fabric_fpga_awid_axi_s1_o6; + output fabric_fpga_awid_axi_s1_o7; + output fabric_fpga_awid_axi_s1_o8; + output fabric_fpga_awid_axi_s1_o9; + output fabric_fpga_awid_axi_s2_o1; + output fabric_fpga_awid_axi_s2_o10; + output fabric_fpga_awid_axi_s2_o11; + output fabric_fpga_awid_axi_s2_o12; + output fabric_fpga_awid_axi_s2_o2; + output fabric_fpga_awid_axi_s2_o3; + output fabric_fpga_awid_axi_s2_o4; + output fabric_fpga_awid_axi_s2_o5; + output fabric_fpga_awid_axi_s2_o6; + output fabric_fpga_awid_axi_s2_o7; + output fabric_fpga_awid_axi_s2_o8; + output fabric_fpga_awid_axi_s2_o9; + input fabric_fpga_awlen_axi_m1_i1; + input fabric_fpga_awlen_axi_m1_i2; + input fabric_fpga_awlen_axi_m1_i3; + input fabric_fpga_awlen_axi_m1_i4; + input fabric_fpga_awlen_axi_m1_i5; + input fabric_fpga_awlen_axi_m1_i6; + input fabric_fpga_awlen_axi_m1_i7; + input fabric_fpga_awlen_axi_m1_i8; + input fabric_fpga_awlen_axi_m2_i1; + input fabric_fpga_awlen_axi_m2_i2; + input fabric_fpga_awlen_axi_m2_i3; + input fabric_fpga_awlen_axi_m2_i4; + input fabric_fpga_awlen_axi_m2_i5; + input fabric_fpga_awlen_axi_m2_i6; + input fabric_fpga_awlen_axi_m2_i7; + input fabric_fpga_awlen_axi_m2_i8; + output fabric_fpga_awlen_axi_s1_o1; + output fabric_fpga_awlen_axi_s1_o2; + output fabric_fpga_awlen_axi_s1_o3; + output fabric_fpga_awlen_axi_s1_o4; + output fabric_fpga_awlen_axi_s1_o5; + output fabric_fpga_awlen_axi_s1_o6; + output fabric_fpga_awlen_axi_s1_o7; + output fabric_fpga_awlen_axi_s1_o8; + output fabric_fpga_awlen_axi_s2_o1; + output fabric_fpga_awlen_axi_s2_o2; + output fabric_fpga_awlen_axi_s2_o3; + output fabric_fpga_awlen_axi_s2_o4; + output fabric_fpga_awlen_axi_s2_o5; + output fabric_fpga_awlen_axi_s2_o6; + output fabric_fpga_awlen_axi_s2_o7; + output fabric_fpga_awlen_axi_s2_o8; + input fabric_fpga_awlock_axi_m1_i; + input fabric_fpga_awlock_axi_m2_i; + output fabric_fpga_awlock_axi_s1_o; + output fabric_fpga_awlock_axi_s2_o; + input fabric_fpga_awprot_axi_m1_i1; + input fabric_fpga_awprot_axi_m1_i2; + input fabric_fpga_awprot_axi_m1_i3; + input fabric_fpga_awprot_axi_m2_i1; + input fabric_fpga_awprot_axi_m2_i2; + input fabric_fpga_awprot_axi_m2_i3; + output fabric_fpga_awprot_axi_s1_o1; + output fabric_fpga_awprot_axi_s1_o2; + output fabric_fpga_awprot_axi_s1_o3; + output fabric_fpga_awprot_axi_s2_o1; + output fabric_fpga_awprot_axi_s2_o2; + output fabric_fpga_awprot_axi_s2_o3; + input fabric_fpga_awqos_axi_m1_i1; + input fabric_fpga_awqos_axi_m1_i2; + input fabric_fpga_awqos_axi_m1_i3; + input fabric_fpga_awqos_axi_m1_i4; + input fabric_fpga_awqos_axi_m2_i1; + input fabric_fpga_awqos_axi_m2_i2; + input fabric_fpga_awqos_axi_m2_i3; + input fabric_fpga_awqos_axi_m2_i4; + output fabric_fpga_awqos_axi_s1_o1; + output fabric_fpga_awqos_axi_s1_o2; + output fabric_fpga_awqos_axi_s1_o3; + output fabric_fpga_awqos_axi_s1_o4; + output fabric_fpga_awqos_axi_s2_o1; + output fabric_fpga_awqos_axi_s2_o2; + output fabric_fpga_awqos_axi_s2_o3; + output fabric_fpga_awqos_axi_s2_o4; + output fabric_fpga_awready_axi_m1_o; + output fabric_fpga_awready_axi_m2_o; + input fabric_fpga_awready_axi_s1_i; + input fabric_fpga_awready_axi_s2_i; + output fabric_fpga_awregion_axi_s1_o1; + output fabric_fpga_awregion_axi_s1_o2; + output fabric_fpga_awregion_axi_s1_o3; + output fabric_fpga_awregion_axi_s1_o4; + output fabric_fpga_awregion_axi_s2_o1; + output fabric_fpga_awregion_axi_s2_o2; + output fabric_fpga_awregion_axi_s2_o3; + output fabric_fpga_awregion_axi_s2_o4; + input fabric_fpga_awsize_axi_m1_i1; + input fabric_fpga_awsize_axi_m1_i2; + input fabric_fpga_awsize_axi_m1_i3; + input fabric_fpga_awsize_axi_m2_i1; + input fabric_fpga_awsize_axi_m2_i2; + input fabric_fpga_awsize_axi_m2_i3; + output fabric_fpga_awsize_axi_s1_o1; + output fabric_fpga_awsize_axi_s1_o2; + output fabric_fpga_awsize_axi_s1_o3; + output fabric_fpga_awsize_axi_s2_o1; + output fabric_fpga_awsize_axi_s2_o2; + output fabric_fpga_awsize_axi_s2_o3; + input fabric_fpga_awvalid_axi_m1_i; + input fabric_fpga_awvalid_axi_m2_i; + output fabric_fpga_awvalid_axi_s1_o; + output fabric_fpga_awvalid_axi_s2_o; + output fabric_fpga_bid_axi_m1_o1; + output fabric_fpga_bid_axi_m1_o2; + output fabric_fpga_bid_axi_m1_o3; + output fabric_fpga_bid_axi_m1_o4; + output fabric_fpga_bid_axi_m1_o5; + output fabric_fpga_bid_axi_m2_o1; + output fabric_fpga_bid_axi_m2_o2; + output fabric_fpga_bid_axi_m2_o3; + output fabric_fpga_bid_axi_m2_o4; + output fabric_fpga_bid_axi_m2_o5; + input fabric_fpga_bid_axi_s1_i1; + input fabric_fpga_bid_axi_s1_i10; + input fabric_fpga_bid_axi_s1_i11; + input fabric_fpga_bid_axi_s1_i12; + input fabric_fpga_bid_axi_s1_i2; + input fabric_fpga_bid_axi_s1_i3; + input fabric_fpga_bid_axi_s1_i4; + input fabric_fpga_bid_axi_s1_i5; + input fabric_fpga_bid_axi_s1_i6; + input fabric_fpga_bid_axi_s1_i7; + input fabric_fpga_bid_axi_s1_i8; + input fabric_fpga_bid_axi_s1_i9; + input fabric_fpga_bid_axi_s2_i1; + input fabric_fpga_bid_axi_s2_i10; + input fabric_fpga_bid_axi_s2_i11; + input fabric_fpga_bid_axi_s2_i12; + input fabric_fpga_bid_axi_s2_i2; + input fabric_fpga_bid_axi_s2_i3; + input fabric_fpga_bid_axi_s2_i4; + input fabric_fpga_bid_axi_s2_i5; + input fabric_fpga_bid_axi_s2_i6; + input fabric_fpga_bid_axi_s2_i7; + input fabric_fpga_bid_axi_s2_i8; + input fabric_fpga_bid_axi_s2_i9; + input fabric_fpga_bready_axi_m1_i; + input fabric_fpga_bready_axi_m2_i; + output fabric_fpga_bready_axi_s1_o; + output fabric_fpga_bready_axi_s2_o; + output fabric_fpga_bresp_axi_m1_o1; + output fabric_fpga_bresp_axi_m1_o2; + output fabric_fpga_bresp_axi_m2_o1; + output fabric_fpga_bresp_axi_m2_o2; + input fabric_fpga_bresp_axi_s1_i1; + input fabric_fpga_bresp_axi_s1_i2; + input fabric_fpga_bresp_axi_s2_i1; + input fabric_fpga_bresp_axi_s2_i2; + output fabric_fpga_bvalid_axi_m1_o; + output fabric_fpga_bvalid_axi_m2_o; + input fabric_fpga_bvalid_axi_s1_i; + input fabric_fpga_bvalid_axi_s2_i; + input fabric_fpga_ddr0_araddr_i1; + input fabric_fpga_ddr0_araddr_i10; + input fabric_fpga_ddr0_araddr_i11; + input fabric_fpga_ddr0_araddr_i12; + input fabric_fpga_ddr0_araddr_i13; + input fabric_fpga_ddr0_araddr_i14; + input fabric_fpga_ddr0_araddr_i15; + input fabric_fpga_ddr0_araddr_i16; + input fabric_fpga_ddr0_araddr_i17; + input fabric_fpga_ddr0_araddr_i18; + input fabric_fpga_ddr0_araddr_i19; + input fabric_fpga_ddr0_araddr_i2; + input fabric_fpga_ddr0_araddr_i20; + input fabric_fpga_ddr0_araddr_i21; + input fabric_fpga_ddr0_araddr_i22; + input fabric_fpga_ddr0_araddr_i23; + input fabric_fpga_ddr0_araddr_i24; + input fabric_fpga_ddr0_araddr_i25; + input fabric_fpga_ddr0_araddr_i26; + input fabric_fpga_ddr0_araddr_i27; + input fabric_fpga_ddr0_araddr_i28; + input fabric_fpga_ddr0_araddr_i29; + input fabric_fpga_ddr0_araddr_i3; + input fabric_fpga_ddr0_araddr_i30; + input fabric_fpga_ddr0_araddr_i31; + input fabric_fpga_ddr0_araddr_i32; + input fabric_fpga_ddr0_araddr_i33; + input fabric_fpga_ddr0_araddr_i34; + input fabric_fpga_ddr0_araddr_i35; + input fabric_fpga_ddr0_araddr_i36; + input fabric_fpga_ddr0_araddr_i37; + input fabric_fpga_ddr0_araddr_i38; + input fabric_fpga_ddr0_araddr_i39; + input fabric_fpga_ddr0_araddr_i4; + input fabric_fpga_ddr0_araddr_i40; + input fabric_fpga_ddr0_araddr_i5; + input fabric_fpga_ddr0_araddr_i6; + input fabric_fpga_ddr0_araddr_i7; + input fabric_fpga_ddr0_araddr_i8; + input fabric_fpga_ddr0_araddr_i9; + input fabric_fpga_ddr0_arburst_i1; + input fabric_fpga_ddr0_arburst_i2; + input fabric_fpga_ddr0_arcache_i1; + input fabric_fpga_ddr0_arcache_i2; + input fabric_fpga_ddr0_arcache_i3; + input fabric_fpga_ddr0_arcache_i4; + input fabric_fpga_ddr0_arid_i1; + input fabric_fpga_ddr0_arid_i2; + input fabric_fpga_ddr0_arid_i3; + input fabric_fpga_ddr0_arid_i4; + input fabric_fpga_ddr0_arid_i5; + input fabric_fpga_ddr0_arlen_i1; + input fabric_fpga_ddr0_arlen_i2; + input fabric_fpga_ddr0_arlen_i3; + input fabric_fpga_ddr0_arlen_i4; + input fabric_fpga_ddr0_arlen_i5; + input fabric_fpga_ddr0_arlen_i6; + input fabric_fpga_ddr0_arlen_i7; + input fabric_fpga_ddr0_arlen_i8; + input fabric_fpga_ddr0_arlock_i; + input fabric_fpga_ddr0_arprot_i1; + input fabric_fpga_ddr0_arprot_i2; + input fabric_fpga_ddr0_arprot_i3; + input fabric_fpga_ddr0_arqos_i1; + input fabric_fpga_ddr0_arqos_i2; + input fabric_fpga_ddr0_arqos_i3; + input fabric_fpga_ddr0_arqos_i4; + output fabric_fpga_ddr0_arready_o; + input fabric_fpga_ddr0_arsize_i1; + input fabric_fpga_ddr0_arsize_i2; + input fabric_fpga_ddr0_arsize_i3; + input fabric_fpga_ddr0_arvalid_i; + input fabric_fpga_ddr0_awaddr_i1; + input fabric_fpga_ddr0_awaddr_i10; + input fabric_fpga_ddr0_awaddr_i11; + input fabric_fpga_ddr0_awaddr_i12; + input fabric_fpga_ddr0_awaddr_i13; + input fabric_fpga_ddr0_awaddr_i14; + input fabric_fpga_ddr0_awaddr_i15; + input fabric_fpga_ddr0_awaddr_i16; + input fabric_fpga_ddr0_awaddr_i17; + input fabric_fpga_ddr0_awaddr_i18; + input fabric_fpga_ddr0_awaddr_i19; + input fabric_fpga_ddr0_awaddr_i2; + input fabric_fpga_ddr0_awaddr_i20; + input fabric_fpga_ddr0_awaddr_i21; + input fabric_fpga_ddr0_awaddr_i22; + input fabric_fpga_ddr0_awaddr_i23; + input fabric_fpga_ddr0_awaddr_i24; + input fabric_fpga_ddr0_awaddr_i25; + input fabric_fpga_ddr0_awaddr_i26; + input fabric_fpga_ddr0_awaddr_i27; + input fabric_fpga_ddr0_awaddr_i28; + input fabric_fpga_ddr0_awaddr_i29; + input fabric_fpga_ddr0_awaddr_i3; + input fabric_fpga_ddr0_awaddr_i30; + input fabric_fpga_ddr0_awaddr_i31; + input fabric_fpga_ddr0_awaddr_i32; + input fabric_fpga_ddr0_awaddr_i33; + input fabric_fpga_ddr0_awaddr_i34; + input fabric_fpga_ddr0_awaddr_i35; + input fabric_fpga_ddr0_awaddr_i36; + input fabric_fpga_ddr0_awaddr_i37; + input fabric_fpga_ddr0_awaddr_i38; + input fabric_fpga_ddr0_awaddr_i39; + input fabric_fpga_ddr0_awaddr_i4; + input fabric_fpga_ddr0_awaddr_i40; + input fabric_fpga_ddr0_awaddr_i5; + input fabric_fpga_ddr0_awaddr_i6; + input fabric_fpga_ddr0_awaddr_i7; + input fabric_fpga_ddr0_awaddr_i8; + input fabric_fpga_ddr0_awaddr_i9; + input fabric_fpga_ddr0_awburst_i1; + input fabric_fpga_ddr0_awburst_i2; + input fabric_fpga_ddr0_awcache_i1; + input fabric_fpga_ddr0_awcache_i2; + input fabric_fpga_ddr0_awcache_i3; + input fabric_fpga_ddr0_awcache_i4; + input fabric_fpga_ddr0_awid_i1; + input fabric_fpga_ddr0_awid_i2; + input fabric_fpga_ddr0_awid_i3; + input fabric_fpga_ddr0_awid_i4; + input fabric_fpga_ddr0_awid_i5; + input fabric_fpga_ddr0_awlen_i1; + input fabric_fpga_ddr0_awlen_i2; + input fabric_fpga_ddr0_awlen_i3; + input fabric_fpga_ddr0_awlen_i4; + input fabric_fpga_ddr0_awlen_i5; + input fabric_fpga_ddr0_awlen_i6; + input fabric_fpga_ddr0_awlen_i7; + input fabric_fpga_ddr0_awlen_i8; + input fabric_fpga_ddr0_awlock_i; + input fabric_fpga_ddr0_awprot_i1; + input fabric_fpga_ddr0_awprot_i2; + input fabric_fpga_ddr0_awprot_i3; + input fabric_fpga_ddr0_awqos_i1; + input fabric_fpga_ddr0_awqos_i2; + input fabric_fpga_ddr0_awqos_i3; + input fabric_fpga_ddr0_awqos_i4; + output fabric_fpga_ddr0_awready_o; + input fabric_fpga_ddr0_awsize_i1; + input fabric_fpga_ddr0_awsize_i2; + input fabric_fpga_ddr0_awsize_i3; + input fabric_fpga_ddr0_awvalid_i; + output fabric_fpga_ddr0_bid_o1; + output fabric_fpga_ddr0_bid_o2; + output fabric_fpga_ddr0_bid_o3; + output fabric_fpga_ddr0_bid_o4; + output fabric_fpga_ddr0_bid_o5; + input fabric_fpga_ddr0_bready_i; + output fabric_fpga_ddr0_bresp_o1; + output fabric_fpga_ddr0_bresp_o2; + output fabric_fpga_ddr0_bvalid_o; + output fabric_fpga_ddr0_rdata_o1; + output fabric_fpga_ddr0_rdata_o10; + output fabric_fpga_ddr0_rdata_o100; + output fabric_fpga_ddr0_rdata_o101; + output fabric_fpga_ddr0_rdata_o102; + output fabric_fpga_ddr0_rdata_o103; + output fabric_fpga_ddr0_rdata_o104; + output fabric_fpga_ddr0_rdata_o105; + output fabric_fpga_ddr0_rdata_o106; + output fabric_fpga_ddr0_rdata_o107; + output fabric_fpga_ddr0_rdata_o108; + output fabric_fpga_ddr0_rdata_o109; + output fabric_fpga_ddr0_rdata_o11; + output fabric_fpga_ddr0_rdata_o110; + output fabric_fpga_ddr0_rdata_o111; + output fabric_fpga_ddr0_rdata_o112; + output fabric_fpga_ddr0_rdata_o113; + output fabric_fpga_ddr0_rdata_o114; + output fabric_fpga_ddr0_rdata_o115; + output fabric_fpga_ddr0_rdata_o116; + output fabric_fpga_ddr0_rdata_o117; + output fabric_fpga_ddr0_rdata_o118; + output fabric_fpga_ddr0_rdata_o119; + output fabric_fpga_ddr0_rdata_o12; + output fabric_fpga_ddr0_rdata_o120; + output fabric_fpga_ddr0_rdata_o121; + output fabric_fpga_ddr0_rdata_o122; + output fabric_fpga_ddr0_rdata_o123; + output fabric_fpga_ddr0_rdata_o124; + output fabric_fpga_ddr0_rdata_o125; + output fabric_fpga_ddr0_rdata_o126; + output fabric_fpga_ddr0_rdata_o127; + output fabric_fpga_ddr0_rdata_o128; + output fabric_fpga_ddr0_rdata_o13; + output fabric_fpga_ddr0_rdata_o14; + output fabric_fpga_ddr0_rdata_o15; + output fabric_fpga_ddr0_rdata_o16; + output fabric_fpga_ddr0_rdata_o17; + output fabric_fpga_ddr0_rdata_o18; + output fabric_fpga_ddr0_rdata_o19; + output fabric_fpga_ddr0_rdata_o2; + output fabric_fpga_ddr0_rdata_o20; + output fabric_fpga_ddr0_rdata_o21; + output fabric_fpga_ddr0_rdata_o22; + output fabric_fpga_ddr0_rdata_o23; + output fabric_fpga_ddr0_rdata_o24; + output fabric_fpga_ddr0_rdata_o25; + output fabric_fpga_ddr0_rdata_o26; + output fabric_fpga_ddr0_rdata_o27; + output fabric_fpga_ddr0_rdata_o28; + output fabric_fpga_ddr0_rdata_o29; + output fabric_fpga_ddr0_rdata_o3; + output fabric_fpga_ddr0_rdata_o30; + output fabric_fpga_ddr0_rdata_o31; + output fabric_fpga_ddr0_rdata_o32; + output fabric_fpga_ddr0_rdata_o33; + output fabric_fpga_ddr0_rdata_o34; + output fabric_fpga_ddr0_rdata_o35; + output fabric_fpga_ddr0_rdata_o36; + output fabric_fpga_ddr0_rdata_o37; + output fabric_fpga_ddr0_rdata_o38; + output fabric_fpga_ddr0_rdata_o39; + output fabric_fpga_ddr0_rdata_o4; + output fabric_fpga_ddr0_rdata_o40; + output fabric_fpga_ddr0_rdata_o41; + output fabric_fpga_ddr0_rdata_o42; + output fabric_fpga_ddr0_rdata_o43; + output fabric_fpga_ddr0_rdata_o44; + output fabric_fpga_ddr0_rdata_o45; + output fabric_fpga_ddr0_rdata_o46; + output fabric_fpga_ddr0_rdata_o47; + output fabric_fpga_ddr0_rdata_o48; + output fabric_fpga_ddr0_rdata_o49; + output fabric_fpga_ddr0_rdata_o5; + output fabric_fpga_ddr0_rdata_o50; + output fabric_fpga_ddr0_rdata_o51; + output fabric_fpga_ddr0_rdata_o52; + output fabric_fpga_ddr0_rdata_o53; + output fabric_fpga_ddr0_rdata_o54; + output fabric_fpga_ddr0_rdata_o55; + output fabric_fpga_ddr0_rdata_o56; + output fabric_fpga_ddr0_rdata_o57; + output fabric_fpga_ddr0_rdata_o58; + output fabric_fpga_ddr0_rdata_o59; + output fabric_fpga_ddr0_rdata_o6; + output fabric_fpga_ddr0_rdata_o60; + output fabric_fpga_ddr0_rdata_o61; + output fabric_fpga_ddr0_rdata_o62; + output fabric_fpga_ddr0_rdata_o63; + output fabric_fpga_ddr0_rdata_o64; + output fabric_fpga_ddr0_rdata_o65; + output fabric_fpga_ddr0_rdata_o66; + output fabric_fpga_ddr0_rdata_o67; + output fabric_fpga_ddr0_rdata_o68; + output fabric_fpga_ddr0_rdata_o69; + output fabric_fpga_ddr0_rdata_o7; + output fabric_fpga_ddr0_rdata_o70; + output fabric_fpga_ddr0_rdata_o71; + output fabric_fpga_ddr0_rdata_o72; + output fabric_fpga_ddr0_rdata_o73; + output fabric_fpga_ddr0_rdata_o74; + output fabric_fpga_ddr0_rdata_o75; + output fabric_fpga_ddr0_rdata_o76; + output fabric_fpga_ddr0_rdata_o77; + output fabric_fpga_ddr0_rdata_o78; + output fabric_fpga_ddr0_rdata_o79; + output fabric_fpga_ddr0_rdata_o8; + output fabric_fpga_ddr0_rdata_o80; + output fabric_fpga_ddr0_rdata_o81; + output fabric_fpga_ddr0_rdata_o82; + output fabric_fpga_ddr0_rdata_o83; + output fabric_fpga_ddr0_rdata_o84; + output fabric_fpga_ddr0_rdata_o85; + output fabric_fpga_ddr0_rdata_o86; + output fabric_fpga_ddr0_rdata_o87; + output fabric_fpga_ddr0_rdata_o88; + output fabric_fpga_ddr0_rdata_o89; + output fabric_fpga_ddr0_rdata_o9; + output fabric_fpga_ddr0_rdata_o90; + output fabric_fpga_ddr0_rdata_o91; + output fabric_fpga_ddr0_rdata_o92; + output fabric_fpga_ddr0_rdata_o93; + output fabric_fpga_ddr0_rdata_o94; + output fabric_fpga_ddr0_rdata_o95; + output fabric_fpga_ddr0_rdata_o96; + output fabric_fpga_ddr0_rdata_o97; + output fabric_fpga_ddr0_rdata_o98; + output fabric_fpga_ddr0_rdata_o99; + output fabric_fpga_ddr0_rid_o1; + output fabric_fpga_ddr0_rid_o2; + output fabric_fpga_ddr0_rid_o3; + output fabric_fpga_ddr0_rid_o4; + output fabric_fpga_ddr0_rid_o5; + output fabric_fpga_ddr0_rlast_o; + input fabric_fpga_ddr0_rready_i; + output fabric_fpga_ddr0_rresp_o1; + output fabric_fpga_ddr0_rresp_o2; + output fabric_fpga_ddr0_rvalid_o; + input fabric_fpga_ddr0_wdata_i1; + input fabric_fpga_ddr0_wdata_i10; + input fabric_fpga_ddr0_wdata_i100; + input fabric_fpga_ddr0_wdata_i101; + input fabric_fpga_ddr0_wdata_i102; + input fabric_fpga_ddr0_wdata_i103; + input fabric_fpga_ddr0_wdata_i104; + input fabric_fpga_ddr0_wdata_i105; + input fabric_fpga_ddr0_wdata_i106; + input fabric_fpga_ddr0_wdata_i107; + input fabric_fpga_ddr0_wdata_i108; + input fabric_fpga_ddr0_wdata_i109; + input fabric_fpga_ddr0_wdata_i11; + input fabric_fpga_ddr0_wdata_i110; + input fabric_fpga_ddr0_wdata_i111; + input fabric_fpga_ddr0_wdata_i112; + input fabric_fpga_ddr0_wdata_i113; + input fabric_fpga_ddr0_wdata_i114; + input fabric_fpga_ddr0_wdata_i115; + input fabric_fpga_ddr0_wdata_i116; + input fabric_fpga_ddr0_wdata_i117; + input fabric_fpga_ddr0_wdata_i118; + input fabric_fpga_ddr0_wdata_i119; + input fabric_fpga_ddr0_wdata_i12; + input fabric_fpga_ddr0_wdata_i120; + input fabric_fpga_ddr0_wdata_i121; + input fabric_fpga_ddr0_wdata_i122; + input fabric_fpga_ddr0_wdata_i123; + input fabric_fpga_ddr0_wdata_i124; + input fabric_fpga_ddr0_wdata_i125; + input fabric_fpga_ddr0_wdata_i126; + input fabric_fpga_ddr0_wdata_i127; + input fabric_fpga_ddr0_wdata_i128; + input fabric_fpga_ddr0_wdata_i13; + input fabric_fpga_ddr0_wdata_i14; + input fabric_fpga_ddr0_wdata_i15; + input fabric_fpga_ddr0_wdata_i16; + input fabric_fpga_ddr0_wdata_i17; + input fabric_fpga_ddr0_wdata_i18; + input fabric_fpga_ddr0_wdata_i19; + input fabric_fpga_ddr0_wdata_i2; + input fabric_fpga_ddr0_wdata_i20; + input fabric_fpga_ddr0_wdata_i21; + input fabric_fpga_ddr0_wdata_i22; + input fabric_fpga_ddr0_wdata_i23; + input fabric_fpga_ddr0_wdata_i24; + input fabric_fpga_ddr0_wdata_i25; + input fabric_fpga_ddr0_wdata_i26; + input fabric_fpga_ddr0_wdata_i27; + input fabric_fpga_ddr0_wdata_i28; + input fabric_fpga_ddr0_wdata_i29; + input fabric_fpga_ddr0_wdata_i3; + input fabric_fpga_ddr0_wdata_i30; + input fabric_fpga_ddr0_wdata_i31; + input fabric_fpga_ddr0_wdata_i32; + input fabric_fpga_ddr0_wdata_i33; + input fabric_fpga_ddr0_wdata_i34; + input fabric_fpga_ddr0_wdata_i35; + input fabric_fpga_ddr0_wdata_i36; + input fabric_fpga_ddr0_wdata_i37; + input fabric_fpga_ddr0_wdata_i38; + input fabric_fpga_ddr0_wdata_i39; + input fabric_fpga_ddr0_wdata_i4; + input fabric_fpga_ddr0_wdata_i40; + input fabric_fpga_ddr0_wdata_i41; + input fabric_fpga_ddr0_wdata_i42; + input fabric_fpga_ddr0_wdata_i43; + input fabric_fpga_ddr0_wdata_i44; + input fabric_fpga_ddr0_wdata_i45; + input fabric_fpga_ddr0_wdata_i46; + input fabric_fpga_ddr0_wdata_i47; + input fabric_fpga_ddr0_wdata_i48; + input fabric_fpga_ddr0_wdata_i49; + input fabric_fpga_ddr0_wdata_i5; + input fabric_fpga_ddr0_wdata_i50; + input fabric_fpga_ddr0_wdata_i51; + input fabric_fpga_ddr0_wdata_i52; + input fabric_fpga_ddr0_wdata_i53; + input fabric_fpga_ddr0_wdata_i54; + input fabric_fpga_ddr0_wdata_i55; + input fabric_fpga_ddr0_wdata_i56; + input fabric_fpga_ddr0_wdata_i57; + input fabric_fpga_ddr0_wdata_i58; + input fabric_fpga_ddr0_wdata_i59; + input fabric_fpga_ddr0_wdata_i6; + input fabric_fpga_ddr0_wdata_i60; + input fabric_fpga_ddr0_wdata_i61; + input fabric_fpga_ddr0_wdata_i62; + input fabric_fpga_ddr0_wdata_i63; + input fabric_fpga_ddr0_wdata_i64; + input fabric_fpga_ddr0_wdata_i65; + input fabric_fpga_ddr0_wdata_i66; + input fabric_fpga_ddr0_wdata_i67; + input fabric_fpga_ddr0_wdata_i68; + input fabric_fpga_ddr0_wdata_i69; + input fabric_fpga_ddr0_wdata_i7; + input fabric_fpga_ddr0_wdata_i70; + input fabric_fpga_ddr0_wdata_i71; + input fabric_fpga_ddr0_wdata_i72; + input fabric_fpga_ddr0_wdata_i73; + input fabric_fpga_ddr0_wdata_i74; + input fabric_fpga_ddr0_wdata_i75; + input fabric_fpga_ddr0_wdata_i76; + input fabric_fpga_ddr0_wdata_i77; + input fabric_fpga_ddr0_wdata_i78; + input fabric_fpga_ddr0_wdata_i79; + input fabric_fpga_ddr0_wdata_i8; + input fabric_fpga_ddr0_wdata_i80; + input fabric_fpga_ddr0_wdata_i81; + input fabric_fpga_ddr0_wdata_i82; + input fabric_fpga_ddr0_wdata_i83; + input fabric_fpga_ddr0_wdata_i84; + input fabric_fpga_ddr0_wdata_i85; + input fabric_fpga_ddr0_wdata_i86; + input fabric_fpga_ddr0_wdata_i87; + input fabric_fpga_ddr0_wdata_i88; + input fabric_fpga_ddr0_wdata_i89; + input fabric_fpga_ddr0_wdata_i9; + input fabric_fpga_ddr0_wdata_i90; + input fabric_fpga_ddr0_wdata_i91; + input fabric_fpga_ddr0_wdata_i92; + input fabric_fpga_ddr0_wdata_i93; + input fabric_fpga_ddr0_wdata_i94; + input fabric_fpga_ddr0_wdata_i95; + input fabric_fpga_ddr0_wdata_i96; + input fabric_fpga_ddr0_wdata_i97; + input fabric_fpga_ddr0_wdata_i98; + input fabric_fpga_ddr0_wdata_i99; + input fabric_fpga_ddr0_wlast_i; + output fabric_fpga_ddr0_wready_o; + input fabric_fpga_ddr0_wstrb_i1; + input fabric_fpga_ddr0_wstrb_i10; + input fabric_fpga_ddr0_wstrb_i11; + input fabric_fpga_ddr0_wstrb_i12; + input fabric_fpga_ddr0_wstrb_i13; + input fabric_fpga_ddr0_wstrb_i14; + input fabric_fpga_ddr0_wstrb_i15; + input fabric_fpga_ddr0_wstrb_i16; + input fabric_fpga_ddr0_wstrb_i2; + input fabric_fpga_ddr0_wstrb_i3; + input fabric_fpga_ddr0_wstrb_i4; + input fabric_fpga_ddr0_wstrb_i5; + input fabric_fpga_ddr0_wstrb_i6; + input fabric_fpga_ddr0_wstrb_i7; + input fabric_fpga_ddr0_wstrb_i8; + input fabric_fpga_ddr0_wstrb_i9; + input fabric_fpga_ddr0_wvalid_i; + output fabric_fpga_dma_ack_m1_o1; + output fabric_fpga_dma_ack_m1_o2; + output fabric_fpga_dma_ack_m1_o3; + output fabric_fpga_dma_ack_m1_o4; + output fabric_fpga_dma_ack_m1_o5; + output fabric_fpga_dma_ack_m1_o6; + output fabric_fpga_dma_ack_m2_o1; + output fabric_fpga_dma_ack_m2_o2; + output fabric_fpga_dma_ack_m2_o3; + output fabric_fpga_dma_ack_m2_o4; + output fabric_fpga_dma_ack_m2_o5; + output fabric_fpga_dma_ack_m2_o6; + output fabric_fpga_dma_finish_m1_o1; + output fabric_fpga_dma_finish_m1_o2; + output fabric_fpga_dma_finish_m1_o3; + output fabric_fpga_dma_finish_m1_o4; + output fabric_fpga_dma_finish_m1_o5; + output fabric_fpga_dma_finish_m1_o6; + output fabric_fpga_dma_finish_m2_o1; + output fabric_fpga_dma_finish_m2_o2; + output fabric_fpga_dma_finish_m2_o3; + output fabric_fpga_dma_finish_m2_o4; + output fabric_fpga_dma_finish_m2_o5; + output fabric_fpga_dma_finish_m2_o6; + input fabric_fpga_dma_hs_rstn_i1; + input fabric_fpga_dma_hs_rstn_i2; + input fabric_fpga_dma_hs_rstn_i3; + input fabric_fpga_dma_hs_rstn_i4; + input fabric_fpga_dma_hs_rstn_i5; + input fabric_fpga_dma_hs_rstn_i6; + input fabric_fpga_dma_last_m1_i1; + input fabric_fpga_dma_last_m1_i2; + input fabric_fpga_dma_last_m1_i3; + input fabric_fpga_dma_last_m1_i4; + input fabric_fpga_dma_last_m1_i5; + input fabric_fpga_dma_last_m1_i6; + input fabric_fpga_dma_last_m2_i1; + input fabric_fpga_dma_last_m2_i2; + input fabric_fpga_dma_last_m2_i3; + input fabric_fpga_dma_last_m2_i4; + input fabric_fpga_dma_last_m2_i5; + input fabric_fpga_dma_last_m2_i6; + input fabric_fpga_dma_req_m1_i1; + input fabric_fpga_dma_req_m1_i2; + input fabric_fpga_dma_req_m1_i3; + input fabric_fpga_dma_req_m1_i4; + input fabric_fpga_dma_req_m1_i5; + input fabric_fpga_dma_req_m1_i6; + input fabric_fpga_dma_req_m2_i1; + input fabric_fpga_dma_req_m2_i2; + input fabric_fpga_dma_req_m2_i3; + input fabric_fpga_dma_req_m2_i4; + input fabric_fpga_dma_req_m2_i5; + input fabric_fpga_dma_req_m2_i6; + input fabric_fpga_dma_single_m1_i1; + input fabric_fpga_dma_single_m1_i2; + input fabric_fpga_dma_single_m1_i3; + input fabric_fpga_dma_single_m1_i4; + input fabric_fpga_dma_single_m1_i5; + input fabric_fpga_dma_single_m1_i6; + input fabric_fpga_dma_single_m2_i1; + input fabric_fpga_dma_single_m2_i2; + input fabric_fpga_dma_single_m2_i3; + input fabric_fpga_dma_single_m2_i4; + input fabric_fpga_dma_single_m2_i5; + input fabric_fpga_dma_single_m2_i6; + input fabric_fpga_events60_i1; + input fabric_fpga_events60_i10; + input fabric_fpga_events60_i11; + input fabric_fpga_events60_i12; + input fabric_fpga_events60_i13; + input fabric_fpga_events60_i14; + input fabric_fpga_events60_i15; + input fabric_fpga_events60_i16; + input fabric_fpga_events60_i17; + input fabric_fpga_events60_i18; + input fabric_fpga_events60_i19; + input fabric_fpga_events60_i2; + input fabric_fpga_events60_i20; + input fabric_fpga_events60_i21; + input fabric_fpga_events60_i22; + input fabric_fpga_events60_i23; + input fabric_fpga_events60_i24; + input fabric_fpga_events60_i25; + input fabric_fpga_events60_i26; + input fabric_fpga_events60_i27; + input fabric_fpga_events60_i28; + input fabric_fpga_events60_i29; + input fabric_fpga_events60_i3; + input fabric_fpga_events60_i30; + input fabric_fpga_events60_i31; + input fabric_fpga_events60_i32; + input fabric_fpga_events60_i33; + input fabric_fpga_events60_i34; + input fabric_fpga_events60_i35; + input fabric_fpga_events60_i36; + input fabric_fpga_events60_i37; + input fabric_fpga_events60_i38; + input fabric_fpga_events60_i39; + input fabric_fpga_events60_i4; + input fabric_fpga_events60_i40; + input fabric_fpga_events60_i41; + input fabric_fpga_events60_i42; + input fabric_fpga_events60_i43; + input fabric_fpga_events60_i44; + input fabric_fpga_events60_i45; + input fabric_fpga_events60_i46; + input fabric_fpga_events60_i47; + input fabric_fpga_events60_i48; + input fabric_fpga_events60_i49; + input fabric_fpga_events60_i5; + input fabric_fpga_events60_i50; + input fabric_fpga_events60_i51; + input fabric_fpga_events60_i52; + input fabric_fpga_events60_i53; + input fabric_fpga_events60_i54; + input fabric_fpga_events60_i55; + input fabric_fpga_events60_i56; + input fabric_fpga_events60_i57; + input fabric_fpga_events60_i58; + input fabric_fpga_events60_i59; + input fabric_fpga_events60_i6; + input fabric_fpga_events60_i60; + input fabric_fpga_events60_i7; + input fabric_fpga_events60_i8; + input fabric_fpga_events60_i9; + input fabric_fpga_interrupt_in_i1; + input fabric_fpga_interrupt_in_i10; + input fabric_fpga_interrupt_in_i100; + input fabric_fpga_interrupt_in_i101; + input fabric_fpga_interrupt_in_i102; + input fabric_fpga_interrupt_in_i103; + input fabric_fpga_interrupt_in_i104; + input fabric_fpga_interrupt_in_i105; + input fabric_fpga_interrupt_in_i106; + input fabric_fpga_interrupt_in_i107; + input fabric_fpga_interrupt_in_i108; + input fabric_fpga_interrupt_in_i109; + input fabric_fpga_interrupt_in_i11; + input fabric_fpga_interrupt_in_i110; + input fabric_fpga_interrupt_in_i111; + input fabric_fpga_interrupt_in_i112; + input fabric_fpga_interrupt_in_i113; + input fabric_fpga_interrupt_in_i114; + input fabric_fpga_interrupt_in_i115; + input fabric_fpga_interrupt_in_i116; + input fabric_fpga_interrupt_in_i117; + input fabric_fpga_interrupt_in_i118; + input fabric_fpga_interrupt_in_i119; + input fabric_fpga_interrupt_in_i12; + input fabric_fpga_interrupt_in_i120; + input fabric_fpga_interrupt_in_i13; + input fabric_fpga_interrupt_in_i14; + input fabric_fpga_interrupt_in_i15; + input fabric_fpga_interrupt_in_i16; + input fabric_fpga_interrupt_in_i17; + input fabric_fpga_interrupt_in_i18; + input fabric_fpga_interrupt_in_i19; + input fabric_fpga_interrupt_in_i2; + input fabric_fpga_interrupt_in_i20; + input fabric_fpga_interrupt_in_i21; + input fabric_fpga_interrupt_in_i22; + input fabric_fpga_interrupt_in_i23; + input fabric_fpga_interrupt_in_i24; + input fabric_fpga_interrupt_in_i25; + input fabric_fpga_interrupt_in_i26; + input fabric_fpga_interrupt_in_i27; + input fabric_fpga_interrupt_in_i28; + input fabric_fpga_interrupt_in_i29; + input fabric_fpga_interrupt_in_i3; + input fabric_fpga_interrupt_in_i30; + input fabric_fpga_interrupt_in_i31; + input fabric_fpga_interrupt_in_i32; + input fabric_fpga_interrupt_in_i33; + input fabric_fpga_interrupt_in_i34; + input fabric_fpga_interrupt_in_i35; + input fabric_fpga_interrupt_in_i36; + input fabric_fpga_interrupt_in_i37; + input fabric_fpga_interrupt_in_i38; + input fabric_fpga_interrupt_in_i39; + input fabric_fpga_interrupt_in_i4; + input fabric_fpga_interrupt_in_i40; + input fabric_fpga_interrupt_in_i41; + input fabric_fpga_interrupt_in_i42; + input fabric_fpga_interrupt_in_i43; + input fabric_fpga_interrupt_in_i44; + input fabric_fpga_interrupt_in_i45; + input fabric_fpga_interrupt_in_i46; + input fabric_fpga_interrupt_in_i47; + input fabric_fpga_interrupt_in_i48; + input fabric_fpga_interrupt_in_i49; + input fabric_fpga_interrupt_in_i5; + input fabric_fpga_interrupt_in_i50; + input fabric_fpga_interrupt_in_i51; + input fabric_fpga_interrupt_in_i52; + input fabric_fpga_interrupt_in_i53; + input fabric_fpga_interrupt_in_i54; + input fabric_fpga_interrupt_in_i55; + input fabric_fpga_interrupt_in_i56; + input fabric_fpga_interrupt_in_i57; + input fabric_fpga_interrupt_in_i58; + input fabric_fpga_interrupt_in_i59; + input fabric_fpga_interrupt_in_i6; + input fabric_fpga_interrupt_in_i60; + input fabric_fpga_interrupt_in_i61; + input fabric_fpga_interrupt_in_i62; + input fabric_fpga_interrupt_in_i63; + input fabric_fpga_interrupt_in_i64; + input fabric_fpga_interrupt_in_i65; + input fabric_fpga_interrupt_in_i66; + input fabric_fpga_interrupt_in_i67; + input fabric_fpga_interrupt_in_i68; + input fabric_fpga_interrupt_in_i69; + input fabric_fpga_interrupt_in_i7; + input fabric_fpga_interrupt_in_i70; + input fabric_fpga_interrupt_in_i71; + input fabric_fpga_interrupt_in_i72; + input fabric_fpga_interrupt_in_i73; + input fabric_fpga_interrupt_in_i74; + input fabric_fpga_interrupt_in_i75; + input fabric_fpga_interrupt_in_i76; + input fabric_fpga_interrupt_in_i77; + input fabric_fpga_interrupt_in_i78; + input fabric_fpga_interrupt_in_i79; + input fabric_fpga_interrupt_in_i8; + input fabric_fpga_interrupt_in_i80; + input fabric_fpga_interrupt_in_i81; + input fabric_fpga_interrupt_in_i82; + input fabric_fpga_interrupt_in_i83; + input fabric_fpga_interrupt_in_i84; + input fabric_fpga_interrupt_in_i85; + input fabric_fpga_interrupt_in_i86; + input fabric_fpga_interrupt_in_i87; + input fabric_fpga_interrupt_in_i88; + input fabric_fpga_interrupt_in_i89; + input fabric_fpga_interrupt_in_i9; + input fabric_fpga_interrupt_in_i90; + input fabric_fpga_interrupt_in_i91; + input fabric_fpga_interrupt_in_i92; + input fabric_fpga_interrupt_in_i93; + input fabric_fpga_interrupt_in_i94; + input fabric_fpga_interrupt_in_i95; + input fabric_fpga_interrupt_in_i96; + input fabric_fpga_interrupt_in_i97; + input fabric_fpga_interrupt_in_i98; + input fabric_fpga_interrupt_in_i99; + input fabric_fpga_nic_rstn_i1; + input fabric_fpga_nic_rstn_i10; + input fabric_fpga_nic_rstn_i2; + input fabric_fpga_nic_rstn_i3; + input fabric_fpga_nic_rstn_i4; + input fabric_fpga_nic_rstn_i5; + input fabric_fpga_nic_rstn_i6; + input fabric_fpga_nic_rstn_i7; + input fabric_fpga_nic_rstn_i8; + input fabric_fpga_nic_rstn_i9; + output fabric_fpga_paddr_apb_o1; + output fabric_fpga_paddr_apb_o10; + output fabric_fpga_paddr_apb_o11; + output fabric_fpga_paddr_apb_o12; + output fabric_fpga_paddr_apb_o13; + output fabric_fpga_paddr_apb_o14; + output fabric_fpga_paddr_apb_o15; + output fabric_fpga_paddr_apb_o16; + output fabric_fpga_paddr_apb_o17; + output fabric_fpga_paddr_apb_o18; + output fabric_fpga_paddr_apb_o19; + output fabric_fpga_paddr_apb_o2; + output fabric_fpga_paddr_apb_o20; + output fabric_fpga_paddr_apb_o21; + output fabric_fpga_paddr_apb_o22; + output fabric_fpga_paddr_apb_o23; + output fabric_fpga_paddr_apb_o24; + output fabric_fpga_paddr_apb_o25; + output fabric_fpga_paddr_apb_o26; + output fabric_fpga_paddr_apb_o27; + output fabric_fpga_paddr_apb_o28; + output fabric_fpga_paddr_apb_o29; + output fabric_fpga_paddr_apb_o3; + output fabric_fpga_paddr_apb_o30; + output fabric_fpga_paddr_apb_o31; + output fabric_fpga_paddr_apb_o32; + output fabric_fpga_paddr_apb_o4; + output fabric_fpga_paddr_apb_o5; + output fabric_fpga_paddr_apb_o6; + output fabric_fpga_paddr_apb_o7; + output fabric_fpga_paddr_apb_o8; + output fabric_fpga_paddr_apb_o9; + output fabric_fpga_penable_apb_o; + input fabric_fpga_pmrstn_i; + input fabric_fpga_prdata_apb_i1; + input fabric_fpga_prdata_apb_i10; + input fabric_fpga_prdata_apb_i11; + input fabric_fpga_prdata_apb_i12; + input fabric_fpga_prdata_apb_i13; + input fabric_fpga_prdata_apb_i14; + input fabric_fpga_prdata_apb_i15; + input fabric_fpga_prdata_apb_i16; + input fabric_fpga_prdata_apb_i17; + input fabric_fpga_prdata_apb_i18; + input fabric_fpga_prdata_apb_i19; + input fabric_fpga_prdata_apb_i2; + input fabric_fpga_prdata_apb_i20; + input fabric_fpga_prdata_apb_i21; + input fabric_fpga_prdata_apb_i22; + input fabric_fpga_prdata_apb_i23; + input fabric_fpga_prdata_apb_i24; + input fabric_fpga_prdata_apb_i25; + input fabric_fpga_prdata_apb_i26; + input fabric_fpga_prdata_apb_i27; + input fabric_fpga_prdata_apb_i28; + input fabric_fpga_prdata_apb_i29; + input fabric_fpga_prdata_apb_i3; + input fabric_fpga_prdata_apb_i30; + input fabric_fpga_prdata_apb_i31; + input fabric_fpga_prdata_apb_i32; + input fabric_fpga_prdata_apb_i4; + input fabric_fpga_prdata_apb_i5; + input fabric_fpga_prdata_apb_i6; + input fabric_fpga_prdata_apb_i7; + input fabric_fpga_prdata_apb_i8; + input fabric_fpga_prdata_apb_i9; + input fabric_fpga_pready_apb_i; + output fabric_fpga_psel_apb_o; + input fabric_fpga_pslverr_apb_i; + output fabric_fpga_pwdata_apb_o1; + output fabric_fpga_pwdata_apb_o10; + output fabric_fpga_pwdata_apb_o11; + output fabric_fpga_pwdata_apb_o12; + output fabric_fpga_pwdata_apb_o13; + output fabric_fpga_pwdata_apb_o14; + output fabric_fpga_pwdata_apb_o15; + output fabric_fpga_pwdata_apb_o16; + output fabric_fpga_pwdata_apb_o17; + output fabric_fpga_pwdata_apb_o18; + output fabric_fpga_pwdata_apb_o19; + output fabric_fpga_pwdata_apb_o2; + output fabric_fpga_pwdata_apb_o20; + output fabric_fpga_pwdata_apb_o21; + output fabric_fpga_pwdata_apb_o22; + output fabric_fpga_pwdata_apb_o23; + output fabric_fpga_pwdata_apb_o24; + output fabric_fpga_pwdata_apb_o25; + output fabric_fpga_pwdata_apb_o26; + output fabric_fpga_pwdata_apb_o27; + output fabric_fpga_pwdata_apb_o28; + output fabric_fpga_pwdata_apb_o29; + output fabric_fpga_pwdata_apb_o3; + output fabric_fpga_pwdata_apb_o30; + output fabric_fpga_pwdata_apb_o31; + output fabric_fpga_pwdata_apb_o32; + output fabric_fpga_pwdata_apb_o4; + output fabric_fpga_pwdata_apb_o5; + output fabric_fpga_pwdata_apb_o6; + output fabric_fpga_pwdata_apb_o7; + output fabric_fpga_pwdata_apb_o8; + output fabric_fpga_pwdata_apb_o9; + output fabric_fpga_pwrite_apb_o; + output fabric_fpga_rdata_axi_m1_o1; + output fabric_fpga_rdata_axi_m1_o10; + output fabric_fpga_rdata_axi_m1_o100; + output fabric_fpga_rdata_axi_m1_o101; + output fabric_fpga_rdata_axi_m1_o102; + output fabric_fpga_rdata_axi_m1_o103; + output fabric_fpga_rdata_axi_m1_o104; + output fabric_fpga_rdata_axi_m1_o105; + output fabric_fpga_rdata_axi_m1_o106; + output fabric_fpga_rdata_axi_m1_o107; + output fabric_fpga_rdata_axi_m1_o108; + output fabric_fpga_rdata_axi_m1_o109; + output fabric_fpga_rdata_axi_m1_o11; + output fabric_fpga_rdata_axi_m1_o110; + output fabric_fpga_rdata_axi_m1_o111; + output fabric_fpga_rdata_axi_m1_o112; + output fabric_fpga_rdata_axi_m1_o113; + output fabric_fpga_rdata_axi_m1_o114; + output fabric_fpga_rdata_axi_m1_o115; + output fabric_fpga_rdata_axi_m1_o116; + output fabric_fpga_rdata_axi_m1_o117; + output fabric_fpga_rdata_axi_m1_o118; + output fabric_fpga_rdata_axi_m1_o119; + output fabric_fpga_rdata_axi_m1_o12; + output fabric_fpga_rdata_axi_m1_o120; + output fabric_fpga_rdata_axi_m1_o121; + output fabric_fpga_rdata_axi_m1_o122; + output fabric_fpga_rdata_axi_m1_o123; + output fabric_fpga_rdata_axi_m1_o124; + output fabric_fpga_rdata_axi_m1_o125; + output fabric_fpga_rdata_axi_m1_o126; + output fabric_fpga_rdata_axi_m1_o127; + output fabric_fpga_rdata_axi_m1_o128; + output fabric_fpga_rdata_axi_m1_o13; + output fabric_fpga_rdata_axi_m1_o14; + output fabric_fpga_rdata_axi_m1_o15; + output fabric_fpga_rdata_axi_m1_o16; + output fabric_fpga_rdata_axi_m1_o17; + output fabric_fpga_rdata_axi_m1_o18; + output fabric_fpga_rdata_axi_m1_o19; + output fabric_fpga_rdata_axi_m1_o2; + output fabric_fpga_rdata_axi_m1_o20; + output fabric_fpga_rdata_axi_m1_o21; + output fabric_fpga_rdata_axi_m1_o22; + output fabric_fpga_rdata_axi_m1_o23; + output fabric_fpga_rdata_axi_m1_o24; + output fabric_fpga_rdata_axi_m1_o25; + output fabric_fpga_rdata_axi_m1_o26; + output fabric_fpga_rdata_axi_m1_o27; + output fabric_fpga_rdata_axi_m1_o28; + output fabric_fpga_rdata_axi_m1_o29; + output fabric_fpga_rdata_axi_m1_o3; + output fabric_fpga_rdata_axi_m1_o30; + output fabric_fpga_rdata_axi_m1_o31; + output fabric_fpga_rdata_axi_m1_o32; + output fabric_fpga_rdata_axi_m1_o33; + output fabric_fpga_rdata_axi_m1_o34; + output fabric_fpga_rdata_axi_m1_o35; + output fabric_fpga_rdata_axi_m1_o36; + output fabric_fpga_rdata_axi_m1_o37; + output fabric_fpga_rdata_axi_m1_o38; + output fabric_fpga_rdata_axi_m1_o39; + output fabric_fpga_rdata_axi_m1_o4; + output fabric_fpga_rdata_axi_m1_o40; + output fabric_fpga_rdata_axi_m1_o41; + output fabric_fpga_rdata_axi_m1_o42; + output fabric_fpga_rdata_axi_m1_o43; + output fabric_fpga_rdata_axi_m1_o44; + output fabric_fpga_rdata_axi_m1_o45; + output fabric_fpga_rdata_axi_m1_o46; + output fabric_fpga_rdata_axi_m1_o47; + output fabric_fpga_rdata_axi_m1_o48; + output fabric_fpga_rdata_axi_m1_o49; + output fabric_fpga_rdata_axi_m1_o5; + output fabric_fpga_rdata_axi_m1_o50; + output fabric_fpga_rdata_axi_m1_o51; + output fabric_fpga_rdata_axi_m1_o52; + output fabric_fpga_rdata_axi_m1_o53; + output fabric_fpga_rdata_axi_m1_o54; + output fabric_fpga_rdata_axi_m1_o55; + output fabric_fpga_rdata_axi_m1_o56; + output fabric_fpga_rdata_axi_m1_o57; + output fabric_fpga_rdata_axi_m1_o58; + output fabric_fpga_rdata_axi_m1_o59; + output fabric_fpga_rdata_axi_m1_o6; + output fabric_fpga_rdata_axi_m1_o60; + output fabric_fpga_rdata_axi_m1_o61; + output fabric_fpga_rdata_axi_m1_o62; + output fabric_fpga_rdata_axi_m1_o63; + output fabric_fpga_rdata_axi_m1_o64; + output fabric_fpga_rdata_axi_m1_o65; + output fabric_fpga_rdata_axi_m1_o66; + output fabric_fpga_rdata_axi_m1_o67; + output fabric_fpga_rdata_axi_m1_o68; + output fabric_fpga_rdata_axi_m1_o69; + output fabric_fpga_rdata_axi_m1_o7; + output fabric_fpga_rdata_axi_m1_o70; + output fabric_fpga_rdata_axi_m1_o71; + output fabric_fpga_rdata_axi_m1_o72; + output fabric_fpga_rdata_axi_m1_o73; + output fabric_fpga_rdata_axi_m1_o74; + output fabric_fpga_rdata_axi_m1_o75; + output fabric_fpga_rdata_axi_m1_o76; + output fabric_fpga_rdata_axi_m1_o77; + output fabric_fpga_rdata_axi_m1_o78; + output fabric_fpga_rdata_axi_m1_o79; + output fabric_fpga_rdata_axi_m1_o8; + output fabric_fpga_rdata_axi_m1_o80; + output fabric_fpga_rdata_axi_m1_o81; + output fabric_fpga_rdata_axi_m1_o82; + output fabric_fpga_rdata_axi_m1_o83; + output fabric_fpga_rdata_axi_m1_o84; + output fabric_fpga_rdata_axi_m1_o85; + output fabric_fpga_rdata_axi_m1_o86; + output fabric_fpga_rdata_axi_m1_o87; + output fabric_fpga_rdata_axi_m1_o88; + output fabric_fpga_rdata_axi_m1_o89; + output fabric_fpga_rdata_axi_m1_o9; + output fabric_fpga_rdata_axi_m1_o90; + output fabric_fpga_rdata_axi_m1_o91; + output fabric_fpga_rdata_axi_m1_o92; + output fabric_fpga_rdata_axi_m1_o93; + output fabric_fpga_rdata_axi_m1_o94; + output fabric_fpga_rdata_axi_m1_o95; + output fabric_fpga_rdata_axi_m1_o96; + output fabric_fpga_rdata_axi_m1_o97; + output fabric_fpga_rdata_axi_m1_o98; + output fabric_fpga_rdata_axi_m1_o99; + output fabric_fpga_rdata_axi_m2_o1; + output fabric_fpga_rdata_axi_m2_o10; + output fabric_fpga_rdata_axi_m2_o100; + output fabric_fpga_rdata_axi_m2_o101; + output fabric_fpga_rdata_axi_m2_o102; + output fabric_fpga_rdata_axi_m2_o103; + output fabric_fpga_rdata_axi_m2_o104; + output fabric_fpga_rdata_axi_m2_o105; + output fabric_fpga_rdata_axi_m2_o106; + output fabric_fpga_rdata_axi_m2_o107; + output fabric_fpga_rdata_axi_m2_o108; + output fabric_fpga_rdata_axi_m2_o109; + output fabric_fpga_rdata_axi_m2_o11; + output fabric_fpga_rdata_axi_m2_o110; + output fabric_fpga_rdata_axi_m2_o111; + output fabric_fpga_rdata_axi_m2_o112; + output fabric_fpga_rdata_axi_m2_o113; + output fabric_fpga_rdata_axi_m2_o114; + output fabric_fpga_rdata_axi_m2_o115; + output fabric_fpga_rdata_axi_m2_o116; + output fabric_fpga_rdata_axi_m2_o117; + output fabric_fpga_rdata_axi_m2_o118; + output fabric_fpga_rdata_axi_m2_o119; + output fabric_fpga_rdata_axi_m2_o12; + output fabric_fpga_rdata_axi_m2_o120; + output fabric_fpga_rdata_axi_m2_o121; + output fabric_fpga_rdata_axi_m2_o122; + output fabric_fpga_rdata_axi_m2_o123; + output fabric_fpga_rdata_axi_m2_o124; + output fabric_fpga_rdata_axi_m2_o125; + output fabric_fpga_rdata_axi_m2_o126; + output fabric_fpga_rdata_axi_m2_o127; + output fabric_fpga_rdata_axi_m2_o128; + output fabric_fpga_rdata_axi_m2_o13; + output fabric_fpga_rdata_axi_m2_o14; + output fabric_fpga_rdata_axi_m2_o15; + output fabric_fpga_rdata_axi_m2_o16; + output fabric_fpga_rdata_axi_m2_o17; + output fabric_fpga_rdata_axi_m2_o18; + output fabric_fpga_rdata_axi_m2_o19; + output fabric_fpga_rdata_axi_m2_o2; + output fabric_fpga_rdata_axi_m2_o20; + output fabric_fpga_rdata_axi_m2_o21; + output fabric_fpga_rdata_axi_m2_o22; + output fabric_fpga_rdata_axi_m2_o23; + output fabric_fpga_rdata_axi_m2_o24; + output fabric_fpga_rdata_axi_m2_o25; + output fabric_fpga_rdata_axi_m2_o26; + output fabric_fpga_rdata_axi_m2_o27; + output fabric_fpga_rdata_axi_m2_o28; + output fabric_fpga_rdata_axi_m2_o29; + output fabric_fpga_rdata_axi_m2_o3; + output fabric_fpga_rdata_axi_m2_o30; + output fabric_fpga_rdata_axi_m2_o31; + output fabric_fpga_rdata_axi_m2_o32; + output fabric_fpga_rdata_axi_m2_o33; + output fabric_fpga_rdata_axi_m2_o34; + output fabric_fpga_rdata_axi_m2_o35; + output fabric_fpga_rdata_axi_m2_o36; + output fabric_fpga_rdata_axi_m2_o37; + output fabric_fpga_rdata_axi_m2_o38; + output fabric_fpga_rdata_axi_m2_o39; + output fabric_fpga_rdata_axi_m2_o4; + output fabric_fpga_rdata_axi_m2_o40; + output fabric_fpga_rdata_axi_m2_o41; + output fabric_fpga_rdata_axi_m2_o42; + output fabric_fpga_rdata_axi_m2_o43; + output fabric_fpga_rdata_axi_m2_o44; + output fabric_fpga_rdata_axi_m2_o45; + output fabric_fpga_rdata_axi_m2_o46; + output fabric_fpga_rdata_axi_m2_o47; + output fabric_fpga_rdata_axi_m2_o48; + output fabric_fpga_rdata_axi_m2_o49; + output fabric_fpga_rdata_axi_m2_o5; + output fabric_fpga_rdata_axi_m2_o50; + output fabric_fpga_rdata_axi_m2_o51; + output fabric_fpga_rdata_axi_m2_o52; + output fabric_fpga_rdata_axi_m2_o53; + output fabric_fpga_rdata_axi_m2_o54; + output fabric_fpga_rdata_axi_m2_o55; + output fabric_fpga_rdata_axi_m2_o56; + output fabric_fpga_rdata_axi_m2_o57; + output fabric_fpga_rdata_axi_m2_o58; + output fabric_fpga_rdata_axi_m2_o59; + output fabric_fpga_rdata_axi_m2_o6; + output fabric_fpga_rdata_axi_m2_o60; + output fabric_fpga_rdata_axi_m2_o61; + output fabric_fpga_rdata_axi_m2_o62; + output fabric_fpga_rdata_axi_m2_o63; + output fabric_fpga_rdata_axi_m2_o64; + output fabric_fpga_rdata_axi_m2_o65; + output fabric_fpga_rdata_axi_m2_o66; + output fabric_fpga_rdata_axi_m2_o67; + output fabric_fpga_rdata_axi_m2_o68; + output fabric_fpga_rdata_axi_m2_o69; + output fabric_fpga_rdata_axi_m2_o7; + output fabric_fpga_rdata_axi_m2_o70; + output fabric_fpga_rdata_axi_m2_o71; + output fabric_fpga_rdata_axi_m2_o72; + output fabric_fpga_rdata_axi_m2_o73; + output fabric_fpga_rdata_axi_m2_o74; + output fabric_fpga_rdata_axi_m2_o75; + output fabric_fpga_rdata_axi_m2_o76; + output fabric_fpga_rdata_axi_m2_o77; + output fabric_fpga_rdata_axi_m2_o78; + output fabric_fpga_rdata_axi_m2_o79; + output fabric_fpga_rdata_axi_m2_o8; + output fabric_fpga_rdata_axi_m2_o80; + output fabric_fpga_rdata_axi_m2_o81; + output fabric_fpga_rdata_axi_m2_o82; + output fabric_fpga_rdata_axi_m2_o83; + output fabric_fpga_rdata_axi_m2_o84; + output fabric_fpga_rdata_axi_m2_o85; + output fabric_fpga_rdata_axi_m2_o86; + output fabric_fpga_rdata_axi_m2_o87; + output fabric_fpga_rdata_axi_m2_o88; + output fabric_fpga_rdata_axi_m2_o89; + output fabric_fpga_rdata_axi_m2_o9; + output fabric_fpga_rdata_axi_m2_o90; + output fabric_fpga_rdata_axi_m2_o91; + output fabric_fpga_rdata_axi_m2_o92; + output fabric_fpga_rdata_axi_m2_o93; + output fabric_fpga_rdata_axi_m2_o94; + output fabric_fpga_rdata_axi_m2_o95; + output fabric_fpga_rdata_axi_m2_o96; + output fabric_fpga_rdata_axi_m2_o97; + output fabric_fpga_rdata_axi_m2_o98; + output fabric_fpga_rdata_axi_m2_o99; + input fabric_fpga_rdata_axi_s1_i1; + input fabric_fpga_rdata_axi_s1_i10; + input fabric_fpga_rdata_axi_s1_i100; + input fabric_fpga_rdata_axi_s1_i101; + input fabric_fpga_rdata_axi_s1_i102; + input fabric_fpga_rdata_axi_s1_i103; + input fabric_fpga_rdata_axi_s1_i104; + input fabric_fpga_rdata_axi_s1_i105; + input fabric_fpga_rdata_axi_s1_i106; + input fabric_fpga_rdata_axi_s1_i107; + input fabric_fpga_rdata_axi_s1_i108; + input fabric_fpga_rdata_axi_s1_i109; + input fabric_fpga_rdata_axi_s1_i11; + input fabric_fpga_rdata_axi_s1_i110; + input fabric_fpga_rdata_axi_s1_i111; + input fabric_fpga_rdata_axi_s1_i112; + input fabric_fpga_rdata_axi_s1_i113; + input fabric_fpga_rdata_axi_s1_i114; + input fabric_fpga_rdata_axi_s1_i115; + input fabric_fpga_rdata_axi_s1_i116; + input fabric_fpga_rdata_axi_s1_i117; + input fabric_fpga_rdata_axi_s1_i118; + input fabric_fpga_rdata_axi_s1_i119; + input fabric_fpga_rdata_axi_s1_i12; + input fabric_fpga_rdata_axi_s1_i120; + input fabric_fpga_rdata_axi_s1_i121; + input fabric_fpga_rdata_axi_s1_i122; + input fabric_fpga_rdata_axi_s1_i123; + input fabric_fpga_rdata_axi_s1_i124; + input fabric_fpga_rdata_axi_s1_i125; + input fabric_fpga_rdata_axi_s1_i126; + input fabric_fpga_rdata_axi_s1_i127; + input fabric_fpga_rdata_axi_s1_i128; + input fabric_fpga_rdata_axi_s1_i13; + input fabric_fpga_rdata_axi_s1_i14; + input fabric_fpga_rdata_axi_s1_i15; + input fabric_fpga_rdata_axi_s1_i16; + input fabric_fpga_rdata_axi_s1_i17; + input fabric_fpga_rdata_axi_s1_i18; + input fabric_fpga_rdata_axi_s1_i19; + input fabric_fpga_rdata_axi_s1_i2; + input fabric_fpga_rdata_axi_s1_i20; + input fabric_fpga_rdata_axi_s1_i21; + input fabric_fpga_rdata_axi_s1_i22; + input fabric_fpga_rdata_axi_s1_i23; + input fabric_fpga_rdata_axi_s1_i24; + input fabric_fpga_rdata_axi_s1_i25; + input fabric_fpga_rdata_axi_s1_i26; + input fabric_fpga_rdata_axi_s1_i27; + input fabric_fpga_rdata_axi_s1_i28; + input fabric_fpga_rdata_axi_s1_i29; + input fabric_fpga_rdata_axi_s1_i3; + input fabric_fpga_rdata_axi_s1_i30; + input fabric_fpga_rdata_axi_s1_i31; + input fabric_fpga_rdata_axi_s1_i32; + input fabric_fpga_rdata_axi_s1_i33; + input fabric_fpga_rdata_axi_s1_i34; + input fabric_fpga_rdata_axi_s1_i35; + input fabric_fpga_rdata_axi_s1_i36; + input fabric_fpga_rdata_axi_s1_i37; + input fabric_fpga_rdata_axi_s1_i38; + input fabric_fpga_rdata_axi_s1_i39; + input fabric_fpga_rdata_axi_s1_i4; + input fabric_fpga_rdata_axi_s1_i40; + input fabric_fpga_rdata_axi_s1_i41; + input fabric_fpga_rdata_axi_s1_i42; + input fabric_fpga_rdata_axi_s1_i43; + input fabric_fpga_rdata_axi_s1_i44; + input fabric_fpga_rdata_axi_s1_i45; + input fabric_fpga_rdata_axi_s1_i46; + input fabric_fpga_rdata_axi_s1_i47; + input fabric_fpga_rdata_axi_s1_i48; + input fabric_fpga_rdata_axi_s1_i49; + input fabric_fpga_rdata_axi_s1_i5; + input fabric_fpga_rdata_axi_s1_i50; + input fabric_fpga_rdata_axi_s1_i51; + input fabric_fpga_rdata_axi_s1_i52; + input fabric_fpga_rdata_axi_s1_i53; + input fabric_fpga_rdata_axi_s1_i54; + input fabric_fpga_rdata_axi_s1_i55; + input fabric_fpga_rdata_axi_s1_i56; + input fabric_fpga_rdata_axi_s1_i57; + input fabric_fpga_rdata_axi_s1_i58; + input fabric_fpga_rdata_axi_s1_i59; + input fabric_fpga_rdata_axi_s1_i6; + input fabric_fpga_rdata_axi_s1_i60; + input fabric_fpga_rdata_axi_s1_i61; + input fabric_fpga_rdata_axi_s1_i62; + input fabric_fpga_rdata_axi_s1_i63; + input fabric_fpga_rdata_axi_s1_i64; + input fabric_fpga_rdata_axi_s1_i65; + input fabric_fpga_rdata_axi_s1_i66; + input fabric_fpga_rdata_axi_s1_i67; + input fabric_fpga_rdata_axi_s1_i68; + input fabric_fpga_rdata_axi_s1_i69; + input fabric_fpga_rdata_axi_s1_i7; + input fabric_fpga_rdata_axi_s1_i70; + input fabric_fpga_rdata_axi_s1_i71; + input fabric_fpga_rdata_axi_s1_i72; + input fabric_fpga_rdata_axi_s1_i73; + input fabric_fpga_rdata_axi_s1_i74; + input fabric_fpga_rdata_axi_s1_i75; + input fabric_fpga_rdata_axi_s1_i76; + input fabric_fpga_rdata_axi_s1_i77; + input fabric_fpga_rdata_axi_s1_i78; + input fabric_fpga_rdata_axi_s1_i79; + input fabric_fpga_rdata_axi_s1_i8; + input fabric_fpga_rdata_axi_s1_i80; + input fabric_fpga_rdata_axi_s1_i81; + input fabric_fpga_rdata_axi_s1_i82; + input fabric_fpga_rdata_axi_s1_i83; + input fabric_fpga_rdata_axi_s1_i84; + input fabric_fpga_rdata_axi_s1_i85; + input fabric_fpga_rdata_axi_s1_i86; + input fabric_fpga_rdata_axi_s1_i87; + input fabric_fpga_rdata_axi_s1_i88; + input fabric_fpga_rdata_axi_s1_i89; + input fabric_fpga_rdata_axi_s1_i9; + input fabric_fpga_rdata_axi_s1_i90; + input fabric_fpga_rdata_axi_s1_i91; + input fabric_fpga_rdata_axi_s1_i92; + input fabric_fpga_rdata_axi_s1_i93; + input fabric_fpga_rdata_axi_s1_i94; + input fabric_fpga_rdata_axi_s1_i95; + input fabric_fpga_rdata_axi_s1_i96; + input fabric_fpga_rdata_axi_s1_i97; + input fabric_fpga_rdata_axi_s1_i98; + input fabric_fpga_rdata_axi_s1_i99; + input fabric_fpga_rdata_axi_s2_i1; + input fabric_fpga_rdata_axi_s2_i10; + input fabric_fpga_rdata_axi_s2_i100; + input fabric_fpga_rdata_axi_s2_i101; + input fabric_fpga_rdata_axi_s2_i102; + input fabric_fpga_rdata_axi_s2_i103; + input fabric_fpga_rdata_axi_s2_i104; + input fabric_fpga_rdata_axi_s2_i105; + input fabric_fpga_rdata_axi_s2_i106; + input fabric_fpga_rdata_axi_s2_i107; + input fabric_fpga_rdata_axi_s2_i108; + input fabric_fpga_rdata_axi_s2_i109; + input fabric_fpga_rdata_axi_s2_i11; + input fabric_fpga_rdata_axi_s2_i110; + input fabric_fpga_rdata_axi_s2_i111; + input fabric_fpga_rdata_axi_s2_i112; + input fabric_fpga_rdata_axi_s2_i113; + input fabric_fpga_rdata_axi_s2_i114; + input fabric_fpga_rdata_axi_s2_i115; + input fabric_fpga_rdata_axi_s2_i116; + input fabric_fpga_rdata_axi_s2_i117; + input fabric_fpga_rdata_axi_s2_i118; + input fabric_fpga_rdata_axi_s2_i119; + input fabric_fpga_rdata_axi_s2_i12; + input fabric_fpga_rdata_axi_s2_i120; + input fabric_fpga_rdata_axi_s2_i121; + input fabric_fpga_rdata_axi_s2_i122; + input fabric_fpga_rdata_axi_s2_i123; + input fabric_fpga_rdata_axi_s2_i124; + input fabric_fpga_rdata_axi_s2_i125; + input fabric_fpga_rdata_axi_s2_i126; + input fabric_fpga_rdata_axi_s2_i127; + input fabric_fpga_rdata_axi_s2_i128; + input fabric_fpga_rdata_axi_s2_i13; + input fabric_fpga_rdata_axi_s2_i14; + input fabric_fpga_rdata_axi_s2_i15; + input fabric_fpga_rdata_axi_s2_i16; + input fabric_fpga_rdata_axi_s2_i17; + input fabric_fpga_rdata_axi_s2_i18; + input fabric_fpga_rdata_axi_s2_i19; + input fabric_fpga_rdata_axi_s2_i2; + input fabric_fpga_rdata_axi_s2_i20; + input fabric_fpga_rdata_axi_s2_i21; + input fabric_fpga_rdata_axi_s2_i22; + input fabric_fpga_rdata_axi_s2_i23; + input fabric_fpga_rdata_axi_s2_i24; + input fabric_fpga_rdata_axi_s2_i25; + input fabric_fpga_rdata_axi_s2_i26; + input fabric_fpga_rdata_axi_s2_i27; + input fabric_fpga_rdata_axi_s2_i28; + input fabric_fpga_rdata_axi_s2_i29; + input fabric_fpga_rdata_axi_s2_i3; + input fabric_fpga_rdata_axi_s2_i30; + input fabric_fpga_rdata_axi_s2_i31; + input fabric_fpga_rdata_axi_s2_i32; + input fabric_fpga_rdata_axi_s2_i33; + input fabric_fpga_rdata_axi_s2_i34; + input fabric_fpga_rdata_axi_s2_i35; + input fabric_fpga_rdata_axi_s2_i36; + input fabric_fpga_rdata_axi_s2_i37; + input fabric_fpga_rdata_axi_s2_i38; + input fabric_fpga_rdata_axi_s2_i39; + input fabric_fpga_rdata_axi_s2_i4; + input fabric_fpga_rdata_axi_s2_i40; + input fabric_fpga_rdata_axi_s2_i41; + input fabric_fpga_rdata_axi_s2_i42; + input fabric_fpga_rdata_axi_s2_i43; + input fabric_fpga_rdata_axi_s2_i44; + input fabric_fpga_rdata_axi_s2_i45; + input fabric_fpga_rdata_axi_s2_i46; + input fabric_fpga_rdata_axi_s2_i47; + input fabric_fpga_rdata_axi_s2_i48; + input fabric_fpga_rdata_axi_s2_i49; + input fabric_fpga_rdata_axi_s2_i5; + input fabric_fpga_rdata_axi_s2_i50; + input fabric_fpga_rdata_axi_s2_i51; + input fabric_fpga_rdata_axi_s2_i52; + input fabric_fpga_rdata_axi_s2_i53; + input fabric_fpga_rdata_axi_s2_i54; + input fabric_fpga_rdata_axi_s2_i55; + input fabric_fpga_rdata_axi_s2_i56; + input fabric_fpga_rdata_axi_s2_i57; + input fabric_fpga_rdata_axi_s2_i58; + input fabric_fpga_rdata_axi_s2_i59; + input fabric_fpga_rdata_axi_s2_i6; + input fabric_fpga_rdata_axi_s2_i60; + input fabric_fpga_rdata_axi_s2_i61; + input fabric_fpga_rdata_axi_s2_i62; + input fabric_fpga_rdata_axi_s2_i63; + input fabric_fpga_rdata_axi_s2_i64; + input fabric_fpga_rdata_axi_s2_i65; + input fabric_fpga_rdata_axi_s2_i66; + input fabric_fpga_rdata_axi_s2_i67; + input fabric_fpga_rdata_axi_s2_i68; + input fabric_fpga_rdata_axi_s2_i69; + input fabric_fpga_rdata_axi_s2_i7; + input fabric_fpga_rdata_axi_s2_i70; + input fabric_fpga_rdata_axi_s2_i71; + input fabric_fpga_rdata_axi_s2_i72; + input fabric_fpga_rdata_axi_s2_i73; + input fabric_fpga_rdata_axi_s2_i74; + input fabric_fpga_rdata_axi_s2_i75; + input fabric_fpga_rdata_axi_s2_i76; + input fabric_fpga_rdata_axi_s2_i77; + input fabric_fpga_rdata_axi_s2_i78; + input fabric_fpga_rdata_axi_s2_i79; + input fabric_fpga_rdata_axi_s2_i8; + input fabric_fpga_rdata_axi_s2_i80; + input fabric_fpga_rdata_axi_s2_i81; + input fabric_fpga_rdata_axi_s2_i82; + input fabric_fpga_rdata_axi_s2_i83; + input fabric_fpga_rdata_axi_s2_i84; + input fabric_fpga_rdata_axi_s2_i85; + input fabric_fpga_rdata_axi_s2_i86; + input fabric_fpga_rdata_axi_s2_i87; + input fabric_fpga_rdata_axi_s2_i88; + input fabric_fpga_rdata_axi_s2_i89; + input fabric_fpga_rdata_axi_s2_i9; + input fabric_fpga_rdata_axi_s2_i90; + input fabric_fpga_rdata_axi_s2_i91; + input fabric_fpga_rdata_axi_s2_i92; + input fabric_fpga_rdata_axi_s2_i93; + input fabric_fpga_rdata_axi_s2_i94; + input fabric_fpga_rdata_axi_s2_i95; + input fabric_fpga_rdata_axi_s2_i96; + input fabric_fpga_rdata_axi_s2_i97; + input fabric_fpga_rdata_axi_s2_i98; + input fabric_fpga_rdata_axi_s2_i99; + output fabric_fpga_rid_axi_m1_o1; + output fabric_fpga_rid_axi_m1_o2; + output fabric_fpga_rid_axi_m1_o3; + output fabric_fpga_rid_axi_m1_o4; + output fabric_fpga_rid_axi_m1_o5; + output fabric_fpga_rid_axi_m2_o1; + output fabric_fpga_rid_axi_m2_o2; + output fabric_fpga_rid_axi_m2_o3; + output fabric_fpga_rid_axi_m2_o4; + output fabric_fpga_rid_axi_m2_o5; + input fabric_fpga_rid_axi_s1_i1; + input fabric_fpga_rid_axi_s1_i10; + input fabric_fpga_rid_axi_s1_i11; + input fabric_fpga_rid_axi_s1_i12; + input fabric_fpga_rid_axi_s1_i2; + input fabric_fpga_rid_axi_s1_i3; + input fabric_fpga_rid_axi_s1_i4; + input fabric_fpga_rid_axi_s1_i5; + input fabric_fpga_rid_axi_s1_i6; + input fabric_fpga_rid_axi_s1_i7; + input fabric_fpga_rid_axi_s1_i8; + input fabric_fpga_rid_axi_s1_i9; + input fabric_fpga_rid_axi_s2_i1; + input fabric_fpga_rid_axi_s2_i10; + input fabric_fpga_rid_axi_s2_i11; + input fabric_fpga_rid_axi_s2_i12; + input fabric_fpga_rid_axi_s2_i2; + input fabric_fpga_rid_axi_s2_i3; + input fabric_fpga_rid_axi_s2_i4; + input fabric_fpga_rid_axi_s2_i5; + input fabric_fpga_rid_axi_s2_i6; + input fabric_fpga_rid_axi_s2_i7; + input fabric_fpga_rid_axi_s2_i8; + input fabric_fpga_rid_axi_s2_i9; + output fabric_fpga_rlast_axi_m1_o; + output fabric_fpga_rlast_axi_m2_o; + input fabric_fpga_rlast_axi_s1_i; + input fabric_fpga_rlast_axi_s2_i; + input fabric_fpga_rready_axi_m1_i; + input fabric_fpga_rready_axi_m2_i; + output fabric_fpga_rready_axi_s1_o; + output fabric_fpga_rready_axi_s2_o; + output fabric_fpga_rresp_axi_m1_o1; + output fabric_fpga_rresp_axi_m1_o2; + output fabric_fpga_rresp_axi_m2_o1; + output fabric_fpga_rresp_axi_m2_o2; + input fabric_fpga_rresp_axi_s1_i1; + input fabric_fpga_rresp_axi_s1_i2; + input fabric_fpga_rresp_axi_s2_i1; + input fabric_fpga_rresp_axi_s2_i2; + output fabric_fpga_rvalid_axi_m1_o; + output fabric_fpga_rvalid_axi_m2_o; + input fabric_fpga_rvalid_axi_s1_i; + input fabric_fpga_rvalid_axi_s2_i; + input fabric_fpga_sysrstn_i; + output fabric_fpga_trigger_in_o1; + output fabric_fpga_trigger_in_o2; + output fabric_fpga_trigger_in_o3; + output fabric_fpga_trigger_in_o4; + output fabric_fpga_trigger_in_o5; + output fabric_fpga_trigger_in_o6; + output fabric_fpga_trigger_in_o7; + output fabric_fpga_trigger_in_o8; + input fabric_fpga_trigger_out_i1; + input fabric_fpga_trigger_out_i2; + input fabric_fpga_trigger_out_i3; + input fabric_fpga_trigger_out_i4; + input fabric_fpga_trigger_out_i5; + input fabric_fpga_trigger_out_i6; + input fabric_fpga_trigger_out_i7; + input fabric_fpga_trigger_out_i8; + input fabric_fpga_wdata_axi_m1_i1; + input fabric_fpga_wdata_axi_m1_i10; + input fabric_fpga_wdata_axi_m1_i100; + input fabric_fpga_wdata_axi_m1_i101; + input fabric_fpga_wdata_axi_m1_i102; + input fabric_fpga_wdata_axi_m1_i103; + input fabric_fpga_wdata_axi_m1_i104; + input fabric_fpga_wdata_axi_m1_i105; + input fabric_fpga_wdata_axi_m1_i106; + input fabric_fpga_wdata_axi_m1_i107; + input fabric_fpga_wdata_axi_m1_i108; + input fabric_fpga_wdata_axi_m1_i109; + input fabric_fpga_wdata_axi_m1_i11; + input fabric_fpga_wdata_axi_m1_i110; + input fabric_fpga_wdata_axi_m1_i111; + input fabric_fpga_wdata_axi_m1_i112; + input fabric_fpga_wdata_axi_m1_i113; + input fabric_fpga_wdata_axi_m1_i114; + input fabric_fpga_wdata_axi_m1_i115; + input fabric_fpga_wdata_axi_m1_i116; + input fabric_fpga_wdata_axi_m1_i117; + input fabric_fpga_wdata_axi_m1_i118; + input fabric_fpga_wdata_axi_m1_i119; + input fabric_fpga_wdata_axi_m1_i12; + input fabric_fpga_wdata_axi_m1_i120; + input fabric_fpga_wdata_axi_m1_i121; + input fabric_fpga_wdata_axi_m1_i122; + input fabric_fpga_wdata_axi_m1_i123; + input fabric_fpga_wdata_axi_m1_i124; + input fabric_fpga_wdata_axi_m1_i125; + input fabric_fpga_wdata_axi_m1_i126; + input fabric_fpga_wdata_axi_m1_i127; + input fabric_fpga_wdata_axi_m1_i128; + input fabric_fpga_wdata_axi_m1_i13; + input fabric_fpga_wdata_axi_m1_i14; + input fabric_fpga_wdata_axi_m1_i15; + input fabric_fpga_wdata_axi_m1_i16; + input fabric_fpga_wdata_axi_m1_i17; + input fabric_fpga_wdata_axi_m1_i18; + input fabric_fpga_wdata_axi_m1_i19; + input fabric_fpga_wdata_axi_m1_i2; + input fabric_fpga_wdata_axi_m1_i20; + input fabric_fpga_wdata_axi_m1_i21; + input fabric_fpga_wdata_axi_m1_i22; + input fabric_fpga_wdata_axi_m1_i23; + input fabric_fpga_wdata_axi_m1_i24; + input fabric_fpga_wdata_axi_m1_i25; + input fabric_fpga_wdata_axi_m1_i26; + input fabric_fpga_wdata_axi_m1_i27; + input fabric_fpga_wdata_axi_m1_i28; + input fabric_fpga_wdata_axi_m1_i29; + input fabric_fpga_wdata_axi_m1_i3; + input fabric_fpga_wdata_axi_m1_i30; + input fabric_fpga_wdata_axi_m1_i31; + input fabric_fpga_wdata_axi_m1_i32; + input fabric_fpga_wdata_axi_m1_i33; + input fabric_fpga_wdata_axi_m1_i34; + input fabric_fpga_wdata_axi_m1_i35; + input fabric_fpga_wdata_axi_m1_i36; + input fabric_fpga_wdata_axi_m1_i37; + input fabric_fpga_wdata_axi_m1_i38; + input fabric_fpga_wdata_axi_m1_i39; + input fabric_fpga_wdata_axi_m1_i4; + input fabric_fpga_wdata_axi_m1_i40; + input fabric_fpga_wdata_axi_m1_i41; + input fabric_fpga_wdata_axi_m1_i42; + input fabric_fpga_wdata_axi_m1_i43; + input fabric_fpga_wdata_axi_m1_i44; + input fabric_fpga_wdata_axi_m1_i45; + input fabric_fpga_wdata_axi_m1_i46; + input fabric_fpga_wdata_axi_m1_i47; + input fabric_fpga_wdata_axi_m1_i48; + input fabric_fpga_wdata_axi_m1_i49; + input fabric_fpga_wdata_axi_m1_i5; + input fabric_fpga_wdata_axi_m1_i50; + input fabric_fpga_wdata_axi_m1_i51; + input fabric_fpga_wdata_axi_m1_i52; + input fabric_fpga_wdata_axi_m1_i53; + input fabric_fpga_wdata_axi_m1_i54; + input fabric_fpga_wdata_axi_m1_i55; + input fabric_fpga_wdata_axi_m1_i56; + input fabric_fpga_wdata_axi_m1_i57; + input fabric_fpga_wdata_axi_m1_i58; + input fabric_fpga_wdata_axi_m1_i59; + input fabric_fpga_wdata_axi_m1_i6; + input fabric_fpga_wdata_axi_m1_i60; + input fabric_fpga_wdata_axi_m1_i61; + input fabric_fpga_wdata_axi_m1_i62; + input fabric_fpga_wdata_axi_m1_i63; + input fabric_fpga_wdata_axi_m1_i64; + input fabric_fpga_wdata_axi_m1_i65; + input fabric_fpga_wdata_axi_m1_i66; + input fabric_fpga_wdata_axi_m1_i67; + input fabric_fpga_wdata_axi_m1_i68; + input fabric_fpga_wdata_axi_m1_i69; + input fabric_fpga_wdata_axi_m1_i7; + input fabric_fpga_wdata_axi_m1_i70; + input fabric_fpga_wdata_axi_m1_i71; + input fabric_fpga_wdata_axi_m1_i72; + input fabric_fpga_wdata_axi_m1_i73; + input fabric_fpga_wdata_axi_m1_i74; + input fabric_fpga_wdata_axi_m1_i75; + input fabric_fpga_wdata_axi_m1_i76; + input fabric_fpga_wdata_axi_m1_i77; + input fabric_fpga_wdata_axi_m1_i78; + input fabric_fpga_wdata_axi_m1_i79; + input fabric_fpga_wdata_axi_m1_i8; + input fabric_fpga_wdata_axi_m1_i80; + input fabric_fpga_wdata_axi_m1_i81; + input fabric_fpga_wdata_axi_m1_i82; + input fabric_fpga_wdata_axi_m1_i83; + input fabric_fpga_wdata_axi_m1_i84; + input fabric_fpga_wdata_axi_m1_i85; + input fabric_fpga_wdata_axi_m1_i86; + input fabric_fpga_wdata_axi_m1_i87; + input fabric_fpga_wdata_axi_m1_i88; + input fabric_fpga_wdata_axi_m1_i89; + input fabric_fpga_wdata_axi_m1_i9; + input fabric_fpga_wdata_axi_m1_i90; + input fabric_fpga_wdata_axi_m1_i91; + input fabric_fpga_wdata_axi_m1_i92; + input fabric_fpga_wdata_axi_m1_i93; + input fabric_fpga_wdata_axi_m1_i94; + input fabric_fpga_wdata_axi_m1_i95; + input fabric_fpga_wdata_axi_m1_i96; + input fabric_fpga_wdata_axi_m1_i97; + input fabric_fpga_wdata_axi_m1_i98; + input fabric_fpga_wdata_axi_m1_i99; + input fabric_fpga_wdata_axi_m2_i1; + input fabric_fpga_wdata_axi_m2_i10; + input fabric_fpga_wdata_axi_m2_i100; + input fabric_fpga_wdata_axi_m2_i101; + input fabric_fpga_wdata_axi_m2_i102; + input fabric_fpga_wdata_axi_m2_i103; + input fabric_fpga_wdata_axi_m2_i104; + input fabric_fpga_wdata_axi_m2_i105; + input fabric_fpga_wdata_axi_m2_i106; + input fabric_fpga_wdata_axi_m2_i107; + input fabric_fpga_wdata_axi_m2_i108; + input fabric_fpga_wdata_axi_m2_i109; + input fabric_fpga_wdata_axi_m2_i11; + input fabric_fpga_wdata_axi_m2_i110; + input fabric_fpga_wdata_axi_m2_i111; + input fabric_fpga_wdata_axi_m2_i112; + input fabric_fpga_wdata_axi_m2_i113; + input fabric_fpga_wdata_axi_m2_i114; + input fabric_fpga_wdata_axi_m2_i115; + input fabric_fpga_wdata_axi_m2_i116; + input fabric_fpga_wdata_axi_m2_i117; + input fabric_fpga_wdata_axi_m2_i118; + input fabric_fpga_wdata_axi_m2_i119; + input fabric_fpga_wdata_axi_m2_i12; + input fabric_fpga_wdata_axi_m2_i120; + input fabric_fpga_wdata_axi_m2_i121; + input fabric_fpga_wdata_axi_m2_i122; + input fabric_fpga_wdata_axi_m2_i123; + input fabric_fpga_wdata_axi_m2_i124; + input fabric_fpga_wdata_axi_m2_i125; + input fabric_fpga_wdata_axi_m2_i126; + input fabric_fpga_wdata_axi_m2_i127; + input fabric_fpga_wdata_axi_m2_i128; + input fabric_fpga_wdata_axi_m2_i13; + input fabric_fpga_wdata_axi_m2_i14; + input fabric_fpga_wdata_axi_m2_i15; + input fabric_fpga_wdata_axi_m2_i16; + input fabric_fpga_wdata_axi_m2_i17; + input fabric_fpga_wdata_axi_m2_i18; + input fabric_fpga_wdata_axi_m2_i19; + input fabric_fpga_wdata_axi_m2_i2; + input fabric_fpga_wdata_axi_m2_i20; + input fabric_fpga_wdata_axi_m2_i21; + input fabric_fpga_wdata_axi_m2_i22; + input fabric_fpga_wdata_axi_m2_i23; + input fabric_fpga_wdata_axi_m2_i24; + input fabric_fpga_wdata_axi_m2_i25; + input fabric_fpga_wdata_axi_m2_i26; + input fabric_fpga_wdata_axi_m2_i27; + input fabric_fpga_wdata_axi_m2_i28; + input fabric_fpga_wdata_axi_m2_i29; + input fabric_fpga_wdata_axi_m2_i3; + input fabric_fpga_wdata_axi_m2_i30; + input fabric_fpga_wdata_axi_m2_i31; + input fabric_fpga_wdata_axi_m2_i32; + input fabric_fpga_wdata_axi_m2_i33; + input fabric_fpga_wdata_axi_m2_i34; + input fabric_fpga_wdata_axi_m2_i35; + input fabric_fpga_wdata_axi_m2_i36; + input fabric_fpga_wdata_axi_m2_i37; + input fabric_fpga_wdata_axi_m2_i38; + input fabric_fpga_wdata_axi_m2_i39; + input fabric_fpga_wdata_axi_m2_i4; + input fabric_fpga_wdata_axi_m2_i40; + input fabric_fpga_wdata_axi_m2_i41; + input fabric_fpga_wdata_axi_m2_i42; + input fabric_fpga_wdata_axi_m2_i43; + input fabric_fpga_wdata_axi_m2_i44; + input fabric_fpga_wdata_axi_m2_i45; + input fabric_fpga_wdata_axi_m2_i46; + input fabric_fpga_wdata_axi_m2_i47; + input fabric_fpga_wdata_axi_m2_i48; + input fabric_fpga_wdata_axi_m2_i49; + input fabric_fpga_wdata_axi_m2_i5; + input fabric_fpga_wdata_axi_m2_i50; + input fabric_fpga_wdata_axi_m2_i51; + input fabric_fpga_wdata_axi_m2_i52; + input fabric_fpga_wdata_axi_m2_i53; + input fabric_fpga_wdata_axi_m2_i54; + input fabric_fpga_wdata_axi_m2_i55; + input fabric_fpga_wdata_axi_m2_i56; + input fabric_fpga_wdata_axi_m2_i57; + input fabric_fpga_wdata_axi_m2_i58; + input fabric_fpga_wdata_axi_m2_i59; + input fabric_fpga_wdata_axi_m2_i6; + input fabric_fpga_wdata_axi_m2_i60; + input fabric_fpga_wdata_axi_m2_i61; + input fabric_fpga_wdata_axi_m2_i62; + input fabric_fpga_wdata_axi_m2_i63; + input fabric_fpga_wdata_axi_m2_i64; + input fabric_fpga_wdata_axi_m2_i65; + input fabric_fpga_wdata_axi_m2_i66; + input fabric_fpga_wdata_axi_m2_i67; + input fabric_fpga_wdata_axi_m2_i68; + input fabric_fpga_wdata_axi_m2_i69; + input fabric_fpga_wdata_axi_m2_i7; + input fabric_fpga_wdata_axi_m2_i70; + input fabric_fpga_wdata_axi_m2_i71; + input fabric_fpga_wdata_axi_m2_i72; + input fabric_fpga_wdata_axi_m2_i73; + input fabric_fpga_wdata_axi_m2_i74; + input fabric_fpga_wdata_axi_m2_i75; + input fabric_fpga_wdata_axi_m2_i76; + input fabric_fpga_wdata_axi_m2_i77; + input fabric_fpga_wdata_axi_m2_i78; + input fabric_fpga_wdata_axi_m2_i79; + input fabric_fpga_wdata_axi_m2_i8; + input fabric_fpga_wdata_axi_m2_i80; + input fabric_fpga_wdata_axi_m2_i81; + input fabric_fpga_wdata_axi_m2_i82; + input fabric_fpga_wdata_axi_m2_i83; + input fabric_fpga_wdata_axi_m2_i84; + input fabric_fpga_wdata_axi_m2_i85; + input fabric_fpga_wdata_axi_m2_i86; + input fabric_fpga_wdata_axi_m2_i87; + input fabric_fpga_wdata_axi_m2_i88; + input fabric_fpga_wdata_axi_m2_i89; + input fabric_fpga_wdata_axi_m2_i9; + input fabric_fpga_wdata_axi_m2_i90; + input fabric_fpga_wdata_axi_m2_i91; + input fabric_fpga_wdata_axi_m2_i92; + input fabric_fpga_wdata_axi_m2_i93; + input fabric_fpga_wdata_axi_m2_i94; + input fabric_fpga_wdata_axi_m2_i95; + input fabric_fpga_wdata_axi_m2_i96; + input fabric_fpga_wdata_axi_m2_i97; + input fabric_fpga_wdata_axi_m2_i98; + input fabric_fpga_wdata_axi_m2_i99; + output fabric_fpga_wdata_axi_s1_o1; + output fabric_fpga_wdata_axi_s1_o10; + output fabric_fpga_wdata_axi_s1_o100; + output fabric_fpga_wdata_axi_s1_o101; + output fabric_fpga_wdata_axi_s1_o102; + output fabric_fpga_wdata_axi_s1_o103; + output fabric_fpga_wdata_axi_s1_o104; + output fabric_fpga_wdata_axi_s1_o105; + output fabric_fpga_wdata_axi_s1_o106; + output fabric_fpga_wdata_axi_s1_o107; + output fabric_fpga_wdata_axi_s1_o108; + output fabric_fpga_wdata_axi_s1_o109; + output fabric_fpga_wdata_axi_s1_o11; + output fabric_fpga_wdata_axi_s1_o110; + output fabric_fpga_wdata_axi_s1_o111; + output fabric_fpga_wdata_axi_s1_o112; + output fabric_fpga_wdata_axi_s1_o113; + output fabric_fpga_wdata_axi_s1_o114; + output fabric_fpga_wdata_axi_s1_o115; + output fabric_fpga_wdata_axi_s1_o116; + output fabric_fpga_wdata_axi_s1_o117; + output fabric_fpga_wdata_axi_s1_o118; + output fabric_fpga_wdata_axi_s1_o119; + output fabric_fpga_wdata_axi_s1_o12; + output fabric_fpga_wdata_axi_s1_o120; + output fabric_fpga_wdata_axi_s1_o121; + output fabric_fpga_wdata_axi_s1_o122; + output fabric_fpga_wdata_axi_s1_o123; + output fabric_fpga_wdata_axi_s1_o124; + output fabric_fpga_wdata_axi_s1_o125; + output fabric_fpga_wdata_axi_s1_o126; + output fabric_fpga_wdata_axi_s1_o127; + output fabric_fpga_wdata_axi_s1_o128; + output fabric_fpga_wdata_axi_s1_o13; + output fabric_fpga_wdata_axi_s1_o14; + output fabric_fpga_wdata_axi_s1_o15; + output fabric_fpga_wdata_axi_s1_o16; + output fabric_fpga_wdata_axi_s1_o17; + output fabric_fpga_wdata_axi_s1_o18; + output fabric_fpga_wdata_axi_s1_o19; + output fabric_fpga_wdata_axi_s1_o2; + output fabric_fpga_wdata_axi_s1_o20; + output fabric_fpga_wdata_axi_s1_o21; + output fabric_fpga_wdata_axi_s1_o22; + output fabric_fpga_wdata_axi_s1_o23; + output fabric_fpga_wdata_axi_s1_o24; + output fabric_fpga_wdata_axi_s1_o25; + output fabric_fpga_wdata_axi_s1_o26; + output fabric_fpga_wdata_axi_s1_o27; + output fabric_fpga_wdata_axi_s1_o28; + output fabric_fpga_wdata_axi_s1_o29; + output fabric_fpga_wdata_axi_s1_o3; + output fabric_fpga_wdata_axi_s1_o30; + output fabric_fpga_wdata_axi_s1_o31; + output fabric_fpga_wdata_axi_s1_o32; + output fabric_fpga_wdata_axi_s1_o33; + output fabric_fpga_wdata_axi_s1_o34; + output fabric_fpga_wdata_axi_s1_o35; + output fabric_fpga_wdata_axi_s1_o36; + output fabric_fpga_wdata_axi_s1_o37; + output fabric_fpga_wdata_axi_s1_o38; + output fabric_fpga_wdata_axi_s1_o39; + output fabric_fpga_wdata_axi_s1_o4; + output fabric_fpga_wdata_axi_s1_o40; + output fabric_fpga_wdata_axi_s1_o41; + output fabric_fpga_wdata_axi_s1_o42; + output fabric_fpga_wdata_axi_s1_o43; + output fabric_fpga_wdata_axi_s1_o44; + output fabric_fpga_wdata_axi_s1_o45; + output fabric_fpga_wdata_axi_s1_o46; + output fabric_fpga_wdata_axi_s1_o47; + output fabric_fpga_wdata_axi_s1_o48; + output fabric_fpga_wdata_axi_s1_o49; + output fabric_fpga_wdata_axi_s1_o5; + output fabric_fpga_wdata_axi_s1_o50; + output fabric_fpga_wdata_axi_s1_o51; + output fabric_fpga_wdata_axi_s1_o52; + output fabric_fpga_wdata_axi_s1_o53; + output fabric_fpga_wdata_axi_s1_o54; + output fabric_fpga_wdata_axi_s1_o55; + output fabric_fpga_wdata_axi_s1_o56; + output fabric_fpga_wdata_axi_s1_o57; + output fabric_fpga_wdata_axi_s1_o58; + output fabric_fpga_wdata_axi_s1_o59; + output fabric_fpga_wdata_axi_s1_o6; + output fabric_fpga_wdata_axi_s1_o60; + output fabric_fpga_wdata_axi_s1_o61; + output fabric_fpga_wdata_axi_s1_o62; + output fabric_fpga_wdata_axi_s1_o63; + output fabric_fpga_wdata_axi_s1_o64; + output fabric_fpga_wdata_axi_s1_o65; + output fabric_fpga_wdata_axi_s1_o66; + output fabric_fpga_wdata_axi_s1_o67; + output fabric_fpga_wdata_axi_s1_o68; + output fabric_fpga_wdata_axi_s1_o69; + output fabric_fpga_wdata_axi_s1_o7; + output fabric_fpga_wdata_axi_s1_o70; + output fabric_fpga_wdata_axi_s1_o71; + output fabric_fpga_wdata_axi_s1_o72; + output fabric_fpga_wdata_axi_s1_o73; + output fabric_fpga_wdata_axi_s1_o74; + output fabric_fpga_wdata_axi_s1_o75; + output fabric_fpga_wdata_axi_s1_o76; + output fabric_fpga_wdata_axi_s1_o77; + output fabric_fpga_wdata_axi_s1_o78; + output fabric_fpga_wdata_axi_s1_o79; + output fabric_fpga_wdata_axi_s1_o8; + output fabric_fpga_wdata_axi_s1_o80; + output fabric_fpga_wdata_axi_s1_o81; + output fabric_fpga_wdata_axi_s1_o82; + output fabric_fpga_wdata_axi_s1_o83; + output fabric_fpga_wdata_axi_s1_o84; + output fabric_fpga_wdata_axi_s1_o85; + output fabric_fpga_wdata_axi_s1_o86; + output fabric_fpga_wdata_axi_s1_o87; + output fabric_fpga_wdata_axi_s1_o88; + output fabric_fpga_wdata_axi_s1_o89; + output fabric_fpga_wdata_axi_s1_o9; + output fabric_fpga_wdata_axi_s1_o90; + output fabric_fpga_wdata_axi_s1_o91; + output fabric_fpga_wdata_axi_s1_o92; + output fabric_fpga_wdata_axi_s1_o93; + output fabric_fpga_wdata_axi_s1_o94; + output fabric_fpga_wdata_axi_s1_o95; + output fabric_fpga_wdata_axi_s1_o96; + output fabric_fpga_wdata_axi_s1_o97; + output fabric_fpga_wdata_axi_s1_o98; + output fabric_fpga_wdata_axi_s1_o99; + output fabric_fpga_wdata_axi_s2_o1; + output fabric_fpga_wdata_axi_s2_o10; + output fabric_fpga_wdata_axi_s2_o100; + output fabric_fpga_wdata_axi_s2_o101; + output fabric_fpga_wdata_axi_s2_o102; + output fabric_fpga_wdata_axi_s2_o103; + output fabric_fpga_wdata_axi_s2_o104; + output fabric_fpga_wdata_axi_s2_o105; + output fabric_fpga_wdata_axi_s2_o106; + output fabric_fpga_wdata_axi_s2_o107; + output fabric_fpga_wdata_axi_s2_o108; + output fabric_fpga_wdata_axi_s2_o109; + output fabric_fpga_wdata_axi_s2_o11; + output fabric_fpga_wdata_axi_s2_o110; + output fabric_fpga_wdata_axi_s2_o111; + output fabric_fpga_wdata_axi_s2_o112; + output fabric_fpga_wdata_axi_s2_o113; + output fabric_fpga_wdata_axi_s2_o114; + output fabric_fpga_wdata_axi_s2_o115; + output fabric_fpga_wdata_axi_s2_o116; + output fabric_fpga_wdata_axi_s2_o117; + output fabric_fpga_wdata_axi_s2_o118; + output fabric_fpga_wdata_axi_s2_o119; + output fabric_fpga_wdata_axi_s2_o12; + output fabric_fpga_wdata_axi_s2_o120; + output fabric_fpga_wdata_axi_s2_o121; + output fabric_fpga_wdata_axi_s2_o122; + output fabric_fpga_wdata_axi_s2_o123; + output fabric_fpga_wdata_axi_s2_o124; + output fabric_fpga_wdata_axi_s2_o125; + output fabric_fpga_wdata_axi_s2_o126; + output fabric_fpga_wdata_axi_s2_o127; + output fabric_fpga_wdata_axi_s2_o128; + output fabric_fpga_wdata_axi_s2_o13; + output fabric_fpga_wdata_axi_s2_o14; + output fabric_fpga_wdata_axi_s2_o15; + output fabric_fpga_wdata_axi_s2_o16; + output fabric_fpga_wdata_axi_s2_o17; + output fabric_fpga_wdata_axi_s2_o18; + output fabric_fpga_wdata_axi_s2_o19; + output fabric_fpga_wdata_axi_s2_o2; + output fabric_fpga_wdata_axi_s2_o20; + output fabric_fpga_wdata_axi_s2_o21; + output fabric_fpga_wdata_axi_s2_o22; + output fabric_fpga_wdata_axi_s2_o23; + output fabric_fpga_wdata_axi_s2_o24; + output fabric_fpga_wdata_axi_s2_o25; + output fabric_fpga_wdata_axi_s2_o26; + output fabric_fpga_wdata_axi_s2_o27; + output fabric_fpga_wdata_axi_s2_o28; + output fabric_fpga_wdata_axi_s2_o29; + output fabric_fpga_wdata_axi_s2_o3; + output fabric_fpga_wdata_axi_s2_o30; + output fabric_fpga_wdata_axi_s2_o31; + output fabric_fpga_wdata_axi_s2_o32; + output fabric_fpga_wdata_axi_s2_o33; + output fabric_fpga_wdata_axi_s2_o34; + output fabric_fpga_wdata_axi_s2_o35; + output fabric_fpga_wdata_axi_s2_o36; + output fabric_fpga_wdata_axi_s2_o37; + output fabric_fpga_wdata_axi_s2_o38; + output fabric_fpga_wdata_axi_s2_o39; + output fabric_fpga_wdata_axi_s2_o4; + output fabric_fpga_wdata_axi_s2_o40; + output fabric_fpga_wdata_axi_s2_o41; + output fabric_fpga_wdata_axi_s2_o42; + output fabric_fpga_wdata_axi_s2_o43; + output fabric_fpga_wdata_axi_s2_o44; + output fabric_fpga_wdata_axi_s2_o45; + output fabric_fpga_wdata_axi_s2_o46; + output fabric_fpga_wdata_axi_s2_o47; + output fabric_fpga_wdata_axi_s2_o48; + output fabric_fpga_wdata_axi_s2_o49; + output fabric_fpga_wdata_axi_s2_o5; + output fabric_fpga_wdata_axi_s2_o50; + output fabric_fpga_wdata_axi_s2_o51; + output fabric_fpga_wdata_axi_s2_o52; + output fabric_fpga_wdata_axi_s2_o53; + output fabric_fpga_wdata_axi_s2_o54; + output fabric_fpga_wdata_axi_s2_o55; + output fabric_fpga_wdata_axi_s2_o56; + output fabric_fpga_wdata_axi_s2_o57; + output fabric_fpga_wdata_axi_s2_o58; + output fabric_fpga_wdata_axi_s2_o59; + output fabric_fpga_wdata_axi_s2_o6; + output fabric_fpga_wdata_axi_s2_o60; + output fabric_fpga_wdata_axi_s2_o61; + output fabric_fpga_wdata_axi_s2_o62; + output fabric_fpga_wdata_axi_s2_o63; + output fabric_fpga_wdata_axi_s2_o64; + output fabric_fpga_wdata_axi_s2_o65; + output fabric_fpga_wdata_axi_s2_o66; + output fabric_fpga_wdata_axi_s2_o67; + output fabric_fpga_wdata_axi_s2_o68; + output fabric_fpga_wdata_axi_s2_o69; + output fabric_fpga_wdata_axi_s2_o7; + output fabric_fpga_wdata_axi_s2_o70; + output fabric_fpga_wdata_axi_s2_o71; + output fabric_fpga_wdata_axi_s2_o72; + output fabric_fpga_wdata_axi_s2_o73; + output fabric_fpga_wdata_axi_s2_o74; + output fabric_fpga_wdata_axi_s2_o75; + output fabric_fpga_wdata_axi_s2_o76; + output fabric_fpga_wdata_axi_s2_o77; + output fabric_fpga_wdata_axi_s2_o78; + output fabric_fpga_wdata_axi_s2_o79; + output fabric_fpga_wdata_axi_s2_o8; + output fabric_fpga_wdata_axi_s2_o80; + output fabric_fpga_wdata_axi_s2_o81; + output fabric_fpga_wdata_axi_s2_o82; + output fabric_fpga_wdata_axi_s2_o83; + output fabric_fpga_wdata_axi_s2_o84; + output fabric_fpga_wdata_axi_s2_o85; + output fabric_fpga_wdata_axi_s2_o86; + output fabric_fpga_wdata_axi_s2_o87; + output fabric_fpga_wdata_axi_s2_o88; + output fabric_fpga_wdata_axi_s2_o89; + output fabric_fpga_wdata_axi_s2_o9; + output fabric_fpga_wdata_axi_s2_o90; + output fabric_fpga_wdata_axi_s2_o91; + output fabric_fpga_wdata_axi_s2_o92; + output fabric_fpga_wdata_axi_s2_o93; + output fabric_fpga_wdata_axi_s2_o94; + output fabric_fpga_wdata_axi_s2_o95; + output fabric_fpga_wdata_axi_s2_o96; + output fabric_fpga_wdata_axi_s2_o97; + output fabric_fpga_wdata_axi_s2_o98; + output fabric_fpga_wdata_axi_s2_o99; + input fabric_fpga_wlast_axi_m1_i; + input fabric_fpga_wlast_axi_m2_i; + output fabric_fpga_wlast_axi_s1_o; + output fabric_fpga_wlast_axi_s2_o; + output fabric_fpga_wready_axi_m1_o; + output fabric_fpga_wready_axi_m2_o; + input fabric_fpga_wready_axi_s1_i; + input fabric_fpga_wready_axi_s2_i; + input fabric_fpga_wstrb_axi_m1_i1; + input fabric_fpga_wstrb_axi_m1_i10; + input fabric_fpga_wstrb_axi_m1_i11; + input fabric_fpga_wstrb_axi_m1_i12; + input fabric_fpga_wstrb_axi_m1_i13; + input fabric_fpga_wstrb_axi_m1_i14; + input fabric_fpga_wstrb_axi_m1_i15; + input fabric_fpga_wstrb_axi_m1_i16; + input fabric_fpga_wstrb_axi_m1_i2; + input fabric_fpga_wstrb_axi_m1_i3; + input fabric_fpga_wstrb_axi_m1_i4; + input fabric_fpga_wstrb_axi_m1_i5; + input fabric_fpga_wstrb_axi_m1_i6; + input fabric_fpga_wstrb_axi_m1_i7; + input fabric_fpga_wstrb_axi_m1_i8; + input fabric_fpga_wstrb_axi_m1_i9; + input fabric_fpga_wstrb_axi_m2_i1; + input fabric_fpga_wstrb_axi_m2_i10; + input fabric_fpga_wstrb_axi_m2_i11; + input fabric_fpga_wstrb_axi_m2_i12; + input fabric_fpga_wstrb_axi_m2_i13; + input fabric_fpga_wstrb_axi_m2_i14; + input fabric_fpga_wstrb_axi_m2_i15; + input fabric_fpga_wstrb_axi_m2_i16; + input fabric_fpga_wstrb_axi_m2_i2; + input fabric_fpga_wstrb_axi_m2_i3; + input fabric_fpga_wstrb_axi_m2_i4; + input fabric_fpga_wstrb_axi_m2_i5; + input fabric_fpga_wstrb_axi_m2_i6; + input fabric_fpga_wstrb_axi_m2_i7; + input fabric_fpga_wstrb_axi_m2_i8; + input fabric_fpga_wstrb_axi_m2_i9; + output fabric_fpga_wstrb_axi_s1_o1; + output fabric_fpga_wstrb_axi_s1_o10; + output fabric_fpga_wstrb_axi_s1_o11; + output fabric_fpga_wstrb_axi_s1_o12; + output fabric_fpga_wstrb_axi_s1_o13; + output fabric_fpga_wstrb_axi_s1_o14; + output fabric_fpga_wstrb_axi_s1_o15; + output fabric_fpga_wstrb_axi_s1_o16; + output fabric_fpga_wstrb_axi_s1_o2; + output fabric_fpga_wstrb_axi_s1_o3; + output fabric_fpga_wstrb_axi_s1_o4; + output fabric_fpga_wstrb_axi_s1_o5; + output fabric_fpga_wstrb_axi_s1_o6; + output fabric_fpga_wstrb_axi_s1_o7; + output fabric_fpga_wstrb_axi_s1_o8; + output fabric_fpga_wstrb_axi_s1_o9; + output fabric_fpga_wstrb_axi_s2_o1; + output fabric_fpga_wstrb_axi_s2_o10; + output fabric_fpga_wstrb_axi_s2_o11; + output fabric_fpga_wstrb_axi_s2_o12; + output fabric_fpga_wstrb_axi_s2_o13; + output fabric_fpga_wstrb_axi_s2_o14; + output fabric_fpga_wstrb_axi_s2_o15; + output fabric_fpga_wstrb_axi_s2_o16; + output fabric_fpga_wstrb_axi_s2_o2; + output fabric_fpga_wstrb_axi_s2_o3; + output fabric_fpga_wstrb_axi_s2_o4; + output fabric_fpga_wstrb_axi_s2_o5; + output fabric_fpga_wstrb_axi_s2_o6; + output fabric_fpga_wstrb_axi_s2_o7; + output fabric_fpga_wstrb_axi_s2_o8; + output fabric_fpga_wstrb_axi_s2_o9; + input fabric_fpga_wvalid_axi_m1_i; + input fabric_fpga_wvalid_axi_m2_i; + output fabric_fpga_wvalid_axi_s1_o; + output fabric_fpga_wvalid_axi_s2_o; + output fabric_llpp0_araddr_s_o1; + output fabric_llpp0_araddr_s_o10; + output fabric_llpp0_araddr_s_o11; + output fabric_llpp0_araddr_s_o12; + output fabric_llpp0_araddr_s_o13; + output fabric_llpp0_araddr_s_o14; + output fabric_llpp0_araddr_s_o15; + output fabric_llpp0_araddr_s_o16; + output fabric_llpp0_araddr_s_o17; + output fabric_llpp0_araddr_s_o18; + output fabric_llpp0_araddr_s_o19; + output fabric_llpp0_araddr_s_o2; + output fabric_llpp0_araddr_s_o20; + output fabric_llpp0_araddr_s_o21; + output fabric_llpp0_araddr_s_o22; + output fabric_llpp0_araddr_s_o23; + output fabric_llpp0_araddr_s_o24; + output fabric_llpp0_araddr_s_o25; + output fabric_llpp0_araddr_s_o26; + output fabric_llpp0_araddr_s_o27; + output fabric_llpp0_araddr_s_o28; + output fabric_llpp0_araddr_s_o29; + output fabric_llpp0_araddr_s_o3; + output fabric_llpp0_araddr_s_o30; + output fabric_llpp0_araddr_s_o31; + output fabric_llpp0_araddr_s_o32; + output fabric_llpp0_araddr_s_o4; + output fabric_llpp0_araddr_s_o5; + output fabric_llpp0_araddr_s_o6; + output fabric_llpp0_araddr_s_o7; + output fabric_llpp0_araddr_s_o8; + output fabric_llpp0_araddr_s_o9; + output fabric_llpp0_arburst_s_o1; + output fabric_llpp0_arburst_s_o2; + output fabric_llpp0_arcache_s_o1; + output fabric_llpp0_arcache_s_o2; + output fabric_llpp0_arcache_s_o3; + output fabric_llpp0_arcache_s_o4; + output fabric_llpp0_arid_s_o1; + output fabric_llpp0_arid_s_o10; + output fabric_llpp0_arid_s_o11; + output fabric_llpp0_arid_s_o12; + output fabric_llpp0_arid_s_o2; + output fabric_llpp0_arid_s_o3; + output fabric_llpp0_arid_s_o4; + output fabric_llpp0_arid_s_o5; + output fabric_llpp0_arid_s_o6; + output fabric_llpp0_arid_s_o7; + output fabric_llpp0_arid_s_o8; + output fabric_llpp0_arid_s_o9; + output fabric_llpp0_arlen_s_o1; + output fabric_llpp0_arlen_s_o2; + output fabric_llpp0_arlen_s_o3; + output fabric_llpp0_arlen_s_o4; + output fabric_llpp0_arlen_s_o5; + output fabric_llpp0_arlen_s_o6; + output fabric_llpp0_arlen_s_o7; + output fabric_llpp0_arlen_s_o8; + output fabric_llpp0_arlock_s_o; + output fabric_llpp0_arprot_s_o1; + output fabric_llpp0_arprot_s_o2; + output fabric_llpp0_arprot_s_o3; + output fabric_llpp0_arqos_s_o1; + output fabric_llpp0_arqos_s_o2; + output fabric_llpp0_arqos_s_o3; + output fabric_llpp0_arqos_s_o4; + input fabric_llpp0_arready_s_i; + output fabric_llpp0_arsize_s_o1; + output fabric_llpp0_arsize_s_o2; + output fabric_llpp0_arsize_s_o3; + output fabric_llpp0_arvalid_s_o; + output fabric_llpp0_awaddr_s_o1; + output fabric_llpp0_awaddr_s_o10; + output fabric_llpp0_awaddr_s_o11; + output fabric_llpp0_awaddr_s_o12; + output fabric_llpp0_awaddr_s_o13; + output fabric_llpp0_awaddr_s_o14; + output fabric_llpp0_awaddr_s_o15; + output fabric_llpp0_awaddr_s_o16; + output fabric_llpp0_awaddr_s_o17; + output fabric_llpp0_awaddr_s_o18; + output fabric_llpp0_awaddr_s_o19; + output fabric_llpp0_awaddr_s_o2; + output fabric_llpp0_awaddr_s_o20; + output fabric_llpp0_awaddr_s_o21; + output fabric_llpp0_awaddr_s_o22; + output fabric_llpp0_awaddr_s_o23; + output fabric_llpp0_awaddr_s_o24; + output fabric_llpp0_awaddr_s_o25; + output fabric_llpp0_awaddr_s_o26; + output fabric_llpp0_awaddr_s_o27; + output fabric_llpp0_awaddr_s_o28; + output fabric_llpp0_awaddr_s_o29; + output fabric_llpp0_awaddr_s_o3; + output fabric_llpp0_awaddr_s_o30; + output fabric_llpp0_awaddr_s_o31; + output fabric_llpp0_awaddr_s_o32; + output fabric_llpp0_awaddr_s_o4; + output fabric_llpp0_awaddr_s_o5; + output fabric_llpp0_awaddr_s_o6; + output fabric_llpp0_awaddr_s_o7; + output fabric_llpp0_awaddr_s_o8; + output fabric_llpp0_awaddr_s_o9; + output fabric_llpp0_awburst_s_o1; + output fabric_llpp0_awburst_s_o2; + output fabric_llpp0_awcache_s_o1; + output fabric_llpp0_awcache_s_o2; + output fabric_llpp0_awcache_s_o3; + output fabric_llpp0_awcache_s_o4; + output fabric_llpp0_awid_s_o1; + output fabric_llpp0_awid_s_o10; + output fabric_llpp0_awid_s_o11; + output fabric_llpp0_awid_s_o12; + output fabric_llpp0_awid_s_o2; + output fabric_llpp0_awid_s_o3; + output fabric_llpp0_awid_s_o4; + output fabric_llpp0_awid_s_o5; + output fabric_llpp0_awid_s_o6; + output fabric_llpp0_awid_s_o7; + output fabric_llpp0_awid_s_o8; + output fabric_llpp0_awid_s_o9; + output fabric_llpp0_awlen_s_o1; + output fabric_llpp0_awlen_s_o2; + output fabric_llpp0_awlen_s_o3; + output fabric_llpp0_awlen_s_o4; + output fabric_llpp0_awlen_s_o5; + output fabric_llpp0_awlen_s_o6; + output fabric_llpp0_awlen_s_o7; + output fabric_llpp0_awlen_s_o8; + output fabric_llpp0_awlock_s_o; + output fabric_llpp0_awprot_s_o1; + output fabric_llpp0_awprot_s_o2; + output fabric_llpp0_awprot_s_o3; + output fabric_llpp0_awqos_s_o1; + output fabric_llpp0_awqos_s_o2; + output fabric_llpp0_awqos_s_o3; + output fabric_llpp0_awqos_s_o4; + input fabric_llpp0_awready_s_i; + output fabric_llpp0_awsize_s_o1; + output fabric_llpp0_awsize_s_o2; + output fabric_llpp0_awsize_s_o3; + output fabric_llpp0_awvalid_s_o; + input fabric_llpp0_bid_s_i1; + input fabric_llpp0_bid_s_i10; + input fabric_llpp0_bid_s_i11; + input fabric_llpp0_bid_s_i12; + input fabric_llpp0_bid_s_i2; + input fabric_llpp0_bid_s_i3; + input fabric_llpp0_bid_s_i4; + input fabric_llpp0_bid_s_i5; + input fabric_llpp0_bid_s_i6; + input fabric_llpp0_bid_s_i7; + input fabric_llpp0_bid_s_i8; + input fabric_llpp0_bid_s_i9; + output fabric_llpp0_bready_s_o; + input fabric_llpp0_bresp_s_i1; + input fabric_llpp0_bresp_s_i2; + input fabric_llpp0_bvalid_s_i; + input fabric_llpp0_rdata_s_i1; + input fabric_llpp0_rdata_s_i10; + input fabric_llpp0_rdata_s_i11; + input fabric_llpp0_rdata_s_i12; + input fabric_llpp0_rdata_s_i13; + input fabric_llpp0_rdata_s_i14; + input fabric_llpp0_rdata_s_i15; + input fabric_llpp0_rdata_s_i16; + input fabric_llpp0_rdata_s_i17; + input fabric_llpp0_rdata_s_i18; + input fabric_llpp0_rdata_s_i19; + input fabric_llpp0_rdata_s_i2; + input fabric_llpp0_rdata_s_i20; + input fabric_llpp0_rdata_s_i21; + input fabric_llpp0_rdata_s_i22; + input fabric_llpp0_rdata_s_i23; + input fabric_llpp0_rdata_s_i24; + input fabric_llpp0_rdata_s_i25; + input fabric_llpp0_rdata_s_i26; + input fabric_llpp0_rdata_s_i27; + input fabric_llpp0_rdata_s_i28; + input fabric_llpp0_rdata_s_i29; + input fabric_llpp0_rdata_s_i3; + input fabric_llpp0_rdata_s_i30; + input fabric_llpp0_rdata_s_i31; + input fabric_llpp0_rdata_s_i32; + input fabric_llpp0_rdata_s_i4; + input fabric_llpp0_rdata_s_i5; + input fabric_llpp0_rdata_s_i6; + input fabric_llpp0_rdata_s_i7; + input fabric_llpp0_rdata_s_i8; + input fabric_llpp0_rdata_s_i9; + input fabric_llpp0_rid_s_i1; + input fabric_llpp0_rid_s_i10; + input fabric_llpp0_rid_s_i11; + input fabric_llpp0_rid_s_i12; + input fabric_llpp0_rid_s_i2; + input fabric_llpp0_rid_s_i3; + input fabric_llpp0_rid_s_i4; + input fabric_llpp0_rid_s_i5; + input fabric_llpp0_rid_s_i6; + input fabric_llpp0_rid_s_i7; + input fabric_llpp0_rid_s_i8; + input fabric_llpp0_rid_s_i9; + input fabric_llpp0_rlast_s_i; + output fabric_llpp0_rready_s_o; + input fabric_llpp0_rresp_s_i1; + input fabric_llpp0_rresp_s_i2; + input fabric_llpp0_rvalid_s_i; + output fabric_llpp0_wdata_s_o1; + output fabric_llpp0_wdata_s_o10; + output fabric_llpp0_wdata_s_o11; + output fabric_llpp0_wdata_s_o12; + output fabric_llpp0_wdata_s_o13; + output fabric_llpp0_wdata_s_o14; + output fabric_llpp0_wdata_s_o15; + output fabric_llpp0_wdata_s_o16; + output fabric_llpp0_wdata_s_o17; + output fabric_llpp0_wdata_s_o18; + output fabric_llpp0_wdata_s_o19; + output fabric_llpp0_wdata_s_o2; + output fabric_llpp0_wdata_s_o20; + output fabric_llpp0_wdata_s_o21; + output fabric_llpp0_wdata_s_o22; + output fabric_llpp0_wdata_s_o23; + output fabric_llpp0_wdata_s_o24; + output fabric_llpp0_wdata_s_o25; + output fabric_llpp0_wdata_s_o26; + output fabric_llpp0_wdata_s_o27; + output fabric_llpp0_wdata_s_o28; + output fabric_llpp0_wdata_s_o29; + output fabric_llpp0_wdata_s_o3; + output fabric_llpp0_wdata_s_o30; + output fabric_llpp0_wdata_s_o31; + output fabric_llpp0_wdata_s_o32; + output fabric_llpp0_wdata_s_o4; + output fabric_llpp0_wdata_s_o5; + output fabric_llpp0_wdata_s_o6; + output fabric_llpp0_wdata_s_o7; + output fabric_llpp0_wdata_s_o8; + output fabric_llpp0_wdata_s_o9; + output fabric_llpp0_wlast_s_o; + input fabric_llpp0_wready_s_i; + output fabric_llpp0_wstrb_s_o1; + output fabric_llpp0_wstrb_s_o2; + output fabric_llpp0_wstrb_s_o3; + output fabric_llpp0_wstrb_s_o4; + output fabric_llpp0_wvalid_s_o; + output fabric_llpp1_araddr_s_o1; + output fabric_llpp1_araddr_s_o10; + output fabric_llpp1_araddr_s_o11; + output fabric_llpp1_araddr_s_o12; + output fabric_llpp1_araddr_s_o13; + output fabric_llpp1_araddr_s_o14; + output fabric_llpp1_araddr_s_o15; + output fabric_llpp1_araddr_s_o16; + output fabric_llpp1_araddr_s_o17; + output fabric_llpp1_araddr_s_o18; + output fabric_llpp1_araddr_s_o19; + output fabric_llpp1_araddr_s_o2; + output fabric_llpp1_araddr_s_o20; + output fabric_llpp1_araddr_s_o21; + output fabric_llpp1_araddr_s_o22; + output fabric_llpp1_araddr_s_o23; + output fabric_llpp1_araddr_s_o24; + output fabric_llpp1_araddr_s_o25; + output fabric_llpp1_araddr_s_o26; + output fabric_llpp1_araddr_s_o27; + output fabric_llpp1_araddr_s_o28; + output fabric_llpp1_araddr_s_o29; + output fabric_llpp1_araddr_s_o3; + output fabric_llpp1_araddr_s_o30; + output fabric_llpp1_araddr_s_o31; + output fabric_llpp1_araddr_s_o32; + output fabric_llpp1_araddr_s_o4; + output fabric_llpp1_araddr_s_o5; + output fabric_llpp1_araddr_s_o6; + output fabric_llpp1_araddr_s_o7; + output fabric_llpp1_araddr_s_o8; + output fabric_llpp1_araddr_s_o9; + output fabric_llpp1_arburst_s_o1; + output fabric_llpp1_arburst_s_o2; + output fabric_llpp1_arcache_s_o1; + output fabric_llpp1_arcache_s_o2; + output fabric_llpp1_arcache_s_o3; + output fabric_llpp1_arcache_s_o4; + output fabric_llpp1_arid_s_o1; + output fabric_llpp1_arid_s_o10; + output fabric_llpp1_arid_s_o11; + output fabric_llpp1_arid_s_o12; + output fabric_llpp1_arid_s_o2; + output fabric_llpp1_arid_s_o3; + output fabric_llpp1_arid_s_o4; + output fabric_llpp1_arid_s_o5; + output fabric_llpp1_arid_s_o6; + output fabric_llpp1_arid_s_o7; + output fabric_llpp1_arid_s_o8; + output fabric_llpp1_arid_s_o9; + output fabric_llpp1_arlen_s_o1; + output fabric_llpp1_arlen_s_o2; + output fabric_llpp1_arlen_s_o3; + output fabric_llpp1_arlen_s_o4; + output fabric_llpp1_arlen_s_o5; + output fabric_llpp1_arlen_s_o6; + output fabric_llpp1_arlen_s_o7; + output fabric_llpp1_arlen_s_o8; + output fabric_llpp1_arlock_s_o; + output fabric_llpp1_arprot_s_o1; + output fabric_llpp1_arprot_s_o2; + output fabric_llpp1_arprot_s_o3; + output fabric_llpp1_arqos_s_o1; + output fabric_llpp1_arqos_s_o2; + output fabric_llpp1_arqos_s_o3; + output fabric_llpp1_arqos_s_o4; + input fabric_llpp1_arready_s_i; + output fabric_llpp1_arsize_s_o1; + output fabric_llpp1_arsize_s_o2; + output fabric_llpp1_arsize_s_o3; + output fabric_llpp1_arvalid_s_o; + output fabric_llpp1_awaddr_s_o1; + output fabric_llpp1_awaddr_s_o10; + output fabric_llpp1_awaddr_s_o11; + output fabric_llpp1_awaddr_s_o12; + output fabric_llpp1_awaddr_s_o13; + output fabric_llpp1_awaddr_s_o14; + output fabric_llpp1_awaddr_s_o15; + output fabric_llpp1_awaddr_s_o16; + output fabric_llpp1_awaddr_s_o17; + output fabric_llpp1_awaddr_s_o18; + output fabric_llpp1_awaddr_s_o19; + output fabric_llpp1_awaddr_s_o2; + output fabric_llpp1_awaddr_s_o20; + output fabric_llpp1_awaddr_s_o21; + output fabric_llpp1_awaddr_s_o22; + output fabric_llpp1_awaddr_s_o23; + output fabric_llpp1_awaddr_s_o24; + output fabric_llpp1_awaddr_s_o25; + output fabric_llpp1_awaddr_s_o26; + output fabric_llpp1_awaddr_s_o27; + output fabric_llpp1_awaddr_s_o28; + output fabric_llpp1_awaddr_s_o29; + output fabric_llpp1_awaddr_s_o3; + output fabric_llpp1_awaddr_s_o30; + output fabric_llpp1_awaddr_s_o31; + output fabric_llpp1_awaddr_s_o32; + output fabric_llpp1_awaddr_s_o4; + output fabric_llpp1_awaddr_s_o5; + output fabric_llpp1_awaddr_s_o6; + output fabric_llpp1_awaddr_s_o7; + output fabric_llpp1_awaddr_s_o8; + output fabric_llpp1_awaddr_s_o9; + output fabric_llpp1_awburst_s_o1; + output fabric_llpp1_awburst_s_o2; + output fabric_llpp1_awcache_s_o1; + output fabric_llpp1_awcache_s_o2; + output fabric_llpp1_awcache_s_o3; + output fabric_llpp1_awcache_s_o4; + output fabric_llpp1_awid_s_o1; + output fabric_llpp1_awid_s_o10; + output fabric_llpp1_awid_s_o11; + output fabric_llpp1_awid_s_o12; + output fabric_llpp1_awid_s_o2; + output fabric_llpp1_awid_s_o3; + output fabric_llpp1_awid_s_o4; + output fabric_llpp1_awid_s_o5; + output fabric_llpp1_awid_s_o6; + output fabric_llpp1_awid_s_o7; + output fabric_llpp1_awid_s_o8; + output fabric_llpp1_awid_s_o9; + output fabric_llpp1_awlen_s_o1; + output fabric_llpp1_awlen_s_o2; + output fabric_llpp1_awlen_s_o3; + output fabric_llpp1_awlen_s_o4; + output fabric_llpp1_awlen_s_o5; + output fabric_llpp1_awlen_s_o6; + output fabric_llpp1_awlen_s_o7; + output fabric_llpp1_awlen_s_o8; + output fabric_llpp1_awlock_s_o; + output fabric_llpp1_awprot_s_o1; + output fabric_llpp1_awprot_s_o2; + output fabric_llpp1_awprot_s_o3; + output fabric_llpp1_awqos_s_o1; + output fabric_llpp1_awqos_s_o2; + output fabric_llpp1_awqos_s_o3; + output fabric_llpp1_awqos_s_o4; + input fabric_llpp1_awready_s_i; + output fabric_llpp1_awsize_s_o1; + output fabric_llpp1_awsize_s_o2; + output fabric_llpp1_awsize_s_o3; + output fabric_llpp1_awvalid_s_o; + input fabric_llpp1_bid_s_i1; + input fabric_llpp1_bid_s_i10; + input fabric_llpp1_bid_s_i11; + input fabric_llpp1_bid_s_i12; + input fabric_llpp1_bid_s_i2; + input fabric_llpp1_bid_s_i3; + input fabric_llpp1_bid_s_i4; + input fabric_llpp1_bid_s_i5; + input fabric_llpp1_bid_s_i6; + input fabric_llpp1_bid_s_i7; + input fabric_llpp1_bid_s_i8; + input fabric_llpp1_bid_s_i9; + output fabric_llpp1_bready_s_o; + input fabric_llpp1_bresp_s_i1; + input fabric_llpp1_bresp_s_i2; + input fabric_llpp1_bvalid_s_i; + input fabric_llpp1_rdata_s_i1; + input fabric_llpp1_rdata_s_i10; + input fabric_llpp1_rdata_s_i11; + input fabric_llpp1_rdata_s_i12; + input fabric_llpp1_rdata_s_i13; + input fabric_llpp1_rdata_s_i14; + input fabric_llpp1_rdata_s_i15; + input fabric_llpp1_rdata_s_i16; + input fabric_llpp1_rdata_s_i17; + input fabric_llpp1_rdata_s_i18; + input fabric_llpp1_rdata_s_i19; + input fabric_llpp1_rdata_s_i2; + input fabric_llpp1_rdata_s_i20; + input fabric_llpp1_rdata_s_i21; + input fabric_llpp1_rdata_s_i22; + input fabric_llpp1_rdata_s_i23; + input fabric_llpp1_rdata_s_i24; + input fabric_llpp1_rdata_s_i25; + input fabric_llpp1_rdata_s_i26; + input fabric_llpp1_rdata_s_i27; + input fabric_llpp1_rdata_s_i28; + input fabric_llpp1_rdata_s_i29; + input fabric_llpp1_rdata_s_i3; + input fabric_llpp1_rdata_s_i30; + input fabric_llpp1_rdata_s_i31; + input fabric_llpp1_rdata_s_i32; + input fabric_llpp1_rdata_s_i4; + input fabric_llpp1_rdata_s_i5; + input fabric_llpp1_rdata_s_i6; + input fabric_llpp1_rdata_s_i7; + input fabric_llpp1_rdata_s_i8; + input fabric_llpp1_rdata_s_i9; + input fabric_llpp1_rid_s_i1; + input fabric_llpp1_rid_s_i10; + input fabric_llpp1_rid_s_i11; + input fabric_llpp1_rid_s_i12; + input fabric_llpp1_rid_s_i2; + input fabric_llpp1_rid_s_i3; + input fabric_llpp1_rid_s_i4; + input fabric_llpp1_rid_s_i5; + input fabric_llpp1_rid_s_i6; + input fabric_llpp1_rid_s_i7; + input fabric_llpp1_rid_s_i8; + input fabric_llpp1_rid_s_i9; + input fabric_llpp1_rlast_s_i; + output fabric_llpp1_rready_s_o; + input fabric_llpp1_rresp_s_i1; + input fabric_llpp1_rresp_s_i2; + input fabric_llpp1_rvalid_s_i; + output fabric_llpp1_wdata_s_o1; + output fabric_llpp1_wdata_s_o10; + output fabric_llpp1_wdata_s_o11; + output fabric_llpp1_wdata_s_o12; + output fabric_llpp1_wdata_s_o13; + output fabric_llpp1_wdata_s_o14; + output fabric_llpp1_wdata_s_o15; + output fabric_llpp1_wdata_s_o16; + output fabric_llpp1_wdata_s_o17; + output fabric_llpp1_wdata_s_o18; + output fabric_llpp1_wdata_s_o19; + output fabric_llpp1_wdata_s_o2; + output fabric_llpp1_wdata_s_o20; + output fabric_llpp1_wdata_s_o21; + output fabric_llpp1_wdata_s_o22; + output fabric_llpp1_wdata_s_o23; + output fabric_llpp1_wdata_s_o24; + output fabric_llpp1_wdata_s_o25; + output fabric_llpp1_wdata_s_o26; + output fabric_llpp1_wdata_s_o27; + output fabric_llpp1_wdata_s_o28; + output fabric_llpp1_wdata_s_o29; + output fabric_llpp1_wdata_s_o3; + output fabric_llpp1_wdata_s_o30; + output fabric_llpp1_wdata_s_o31; + output fabric_llpp1_wdata_s_o32; + output fabric_llpp1_wdata_s_o4; + output fabric_llpp1_wdata_s_o5; + output fabric_llpp1_wdata_s_o6; + output fabric_llpp1_wdata_s_o7; + output fabric_llpp1_wdata_s_o8; + output fabric_llpp1_wdata_s_o9; + output fabric_llpp1_wlast_s_o; + input fabric_llpp1_wready_s_i; + output fabric_llpp1_wstrb_s_o1; + output fabric_llpp1_wstrb_s_o2; + output fabric_llpp1_wstrb_s_o3; + output fabric_llpp1_wstrb_s_o4; + output fabric_llpp1_wvalid_s_o; + output fabric_llpp2_araddr_s_o1; + output fabric_llpp2_araddr_s_o10; + output fabric_llpp2_araddr_s_o11; + output fabric_llpp2_araddr_s_o12; + output fabric_llpp2_araddr_s_o13; + output fabric_llpp2_araddr_s_o14; + output fabric_llpp2_araddr_s_o15; + output fabric_llpp2_araddr_s_o16; + output fabric_llpp2_araddr_s_o17; + output fabric_llpp2_araddr_s_o18; + output fabric_llpp2_araddr_s_o19; + output fabric_llpp2_araddr_s_o2; + output fabric_llpp2_araddr_s_o20; + output fabric_llpp2_araddr_s_o21; + output fabric_llpp2_araddr_s_o22; + output fabric_llpp2_araddr_s_o23; + output fabric_llpp2_araddr_s_o24; + output fabric_llpp2_araddr_s_o25; + output fabric_llpp2_araddr_s_o26; + output fabric_llpp2_araddr_s_o27; + output fabric_llpp2_araddr_s_o28; + output fabric_llpp2_araddr_s_o29; + output fabric_llpp2_araddr_s_o3; + output fabric_llpp2_araddr_s_o30; + output fabric_llpp2_araddr_s_o31; + output fabric_llpp2_araddr_s_o32; + output fabric_llpp2_araddr_s_o4; + output fabric_llpp2_araddr_s_o5; + output fabric_llpp2_araddr_s_o6; + output fabric_llpp2_araddr_s_o7; + output fabric_llpp2_araddr_s_o8; + output fabric_llpp2_araddr_s_o9; + output fabric_llpp2_arburst_s_o1; + output fabric_llpp2_arburst_s_o2; + output fabric_llpp2_arcache_s_o1; + output fabric_llpp2_arcache_s_o2; + output fabric_llpp2_arcache_s_o3; + output fabric_llpp2_arcache_s_o4; + output fabric_llpp2_arid_s_o1; + output fabric_llpp2_arid_s_o10; + output fabric_llpp2_arid_s_o11; + output fabric_llpp2_arid_s_o12; + output fabric_llpp2_arid_s_o2; + output fabric_llpp2_arid_s_o3; + output fabric_llpp2_arid_s_o4; + output fabric_llpp2_arid_s_o5; + output fabric_llpp2_arid_s_o6; + output fabric_llpp2_arid_s_o7; + output fabric_llpp2_arid_s_o8; + output fabric_llpp2_arid_s_o9; + output fabric_llpp2_arlen_s_o1; + output fabric_llpp2_arlen_s_o2; + output fabric_llpp2_arlen_s_o3; + output fabric_llpp2_arlen_s_o4; + output fabric_llpp2_arlen_s_o5; + output fabric_llpp2_arlen_s_o6; + output fabric_llpp2_arlen_s_o7; + output fabric_llpp2_arlen_s_o8; + output fabric_llpp2_arlock_s_o; + output fabric_llpp2_arprot_s_o1; + output fabric_llpp2_arprot_s_o2; + output fabric_llpp2_arprot_s_o3; + output fabric_llpp2_arqos_s_o1; + output fabric_llpp2_arqos_s_o2; + output fabric_llpp2_arqos_s_o3; + output fabric_llpp2_arqos_s_o4; + input fabric_llpp2_arready_s_i; + output fabric_llpp2_arsize_s_o1; + output fabric_llpp2_arsize_s_o2; + output fabric_llpp2_arsize_s_o3; + output fabric_llpp2_arvalid_s_o; + output fabric_llpp2_awaddr_s_o1; + output fabric_llpp2_awaddr_s_o10; + output fabric_llpp2_awaddr_s_o11; + output fabric_llpp2_awaddr_s_o12; + output fabric_llpp2_awaddr_s_o13; + output fabric_llpp2_awaddr_s_o14; + output fabric_llpp2_awaddr_s_o15; + output fabric_llpp2_awaddr_s_o16; + output fabric_llpp2_awaddr_s_o17; + output fabric_llpp2_awaddr_s_o18; + output fabric_llpp2_awaddr_s_o19; + output fabric_llpp2_awaddr_s_o2; + output fabric_llpp2_awaddr_s_o20; + output fabric_llpp2_awaddr_s_o21; + output fabric_llpp2_awaddr_s_o22; + output fabric_llpp2_awaddr_s_o23; + output fabric_llpp2_awaddr_s_o24; + output fabric_llpp2_awaddr_s_o25; + output fabric_llpp2_awaddr_s_o26; + output fabric_llpp2_awaddr_s_o27; + output fabric_llpp2_awaddr_s_o28; + output fabric_llpp2_awaddr_s_o29; + output fabric_llpp2_awaddr_s_o3; + output fabric_llpp2_awaddr_s_o30; + output fabric_llpp2_awaddr_s_o31; + output fabric_llpp2_awaddr_s_o32; + output fabric_llpp2_awaddr_s_o4; + output fabric_llpp2_awaddr_s_o5; + output fabric_llpp2_awaddr_s_o6; + output fabric_llpp2_awaddr_s_o7; + output fabric_llpp2_awaddr_s_o8; + output fabric_llpp2_awaddr_s_o9; + output fabric_llpp2_awburst_s_o1; + output fabric_llpp2_awburst_s_o2; + output fabric_llpp2_awcache_s_o1; + output fabric_llpp2_awcache_s_o2; + output fabric_llpp2_awcache_s_o3; + output fabric_llpp2_awcache_s_o4; + output fabric_llpp2_awid_s_o1; + output fabric_llpp2_awid_s_o10; + output fabric_llpp2_awid_s_o11; + output fabric_llpp2_awid_s_o12; + output fabric_llpp2_awid_s_o2; + output fabric_llpp2_awid_s_o3; + output fabric_llpp2_awid_s_o4; + output fabric_llpp2_awid_s_o5; + output fabric_llpp2_awid_s_o6; + output fabric_llpp2_awid_s_o7; + output fabric_llpp2_awid_s_o8; + output fabric_llpp2_awid_s_o9; + output fabric_llpp2_awlen_s_o1; + output fabric_llpp2_awlen_s_o2; + output fabric_llpp2_awlen_s_o3; + output fabric_llpp2_awlen_s_o4; + output fabric_llpp2_awlen_s_o5; + output fabric_llpp2_awlen_s_o6; + output fabric_llpp2_awlen_s_o7; + output fabric_llpp2_awlen_s_o8; + output fabric_llpp2_awlock_s_o; + output fabric_llpp2_awprot_s_o1; + output fabric_llpp2_awprot_s_o2; + output fabric_llpp2_awprot_s_o3; + output fabric_llpp2_awqos_s_o1; + output fabric_llpp2_awqos_s_o2; + output fabric_llpp2_awqos_s_o3; + output fabric_llpp2_awqos_s_o4; + input fabric_llpp2_awready_s_i; + output fabric_llpp2_awsize_s_o1; + output fabric_llpp2_awsize_s_o2; + output fabric_llpp2_awsize_s_o3; + output fabric_llpp2_awvalid_s_o; + input fabric_llpp2_bid_s_i1; + input fabric_llpp2_bid_s_i10; + input fabric_llpp2_bid_s_i11; + input fabric_llpp2_bid_s_i12; + input fabric_llpp2_bid_s_i2; + input fabric_llpp2_bid_s_i3; + input fabric_llpp2_bid_s_i4; + input fabric_llpp2_bid_s_i5; + input fabric_llpp2_bid_s_i6; + input fabric_llpp2_bid_s_i7; + input fabric_llpp2_bid_s_i8; + input fabric_llpp2_bid_s_i9; + output fabric_llpp2_bready_s_o; + input fabric_llpp2_bresp_s_i1; + input fabric_llpp2_bresp_s_i2; + input fabric_llpp2_bvalid_s_i; + input fabric_llpp2_rdata_s_i1; + input fabric_llpp2_rdata_s_i10; + input fabric_llpp2_rdata_s_i11; + input fabric_llpp2_rdata_s_i12; + input fabric_llpp2_rdata_s_i13; + input fabric_llpp2_rdata_s_i14; + input fabric_llpp2_rdata_s_i15; + input fabric_llpp2_rdata_s_i16; + input fabric_llpp2_rdata_s_i17; + input fabric_llpp2_rdata_s_i18; + input fabric_llpp2_rdata_s_i19; + input fabric_llpp2_rdata_s_i2; + input fabric_llpp2_rdata_s_i20; + input fabric_llpp2_rdata_s_i21; + input fabric_llpp2_rdata_s_i22; + input fabric_llpp2_rdata_s_i23; + input fabric_llpp2_rdata_s_i24; + input fabric_llpp2_rdata_s_i25; + input fabric_llpp2_rdata_s_i26; + input fabric_llpp2_rdata_s_i27; + input fabric_llpp2_rdata_s_i28; + input fabric_llpp2_rdata_s_i29; + input fabric_llpp2_rdata_s_i3; + input fabric_llpp2_rdata_s_i30; + input fabric_llpp2_rdata_s_i31; + input fabric_llpp2_rdata_s_i32; + input fabric_llpp2_rdata_s_i4; + input fabric_llpp2_rdata_s_i5; + input fabric_llpp2_rdata_s_i6; + input fabric_llpp2_rdata_s_i7; + input fabric_llpp2_rdata_s_i8; + input fabric_llpp2_rdata_s_i9; + input fabric_llpp2_rid_s_i1; + input fabric_llpp2_rid_s_i10; + input fabric_llpp2_rid_s_i11; + input fabric_llpp2_rid_s_i12; + input fabric_llpp2_rid_s_i2; + input fabric_llpp2_rid_s_i3; + input fabric_llpp2_rid_s_i4; + input fabric_llpp2_rid_s_i5; + input fabric_llpp2_rid_s_i6; + input fabric_llpp2_rid_s_i7; + input fabric_llpp2_rid_s_i8; + input fabric_llpp2_rid_s_i9; + input fabric_llpp2_rlast_s_i; + output fabric_llpp2_rready_s_o; + input fabric_llpp2_rresp_s_i1; + input fabric_llpp2_rresp_s_i2; + input fabric_llpp2_rvalid_s_i; + output fabric_llpp2_wdata_s_o1; + output fabric_llpp2_wdata_s_o10; + output fabric_llpp2_wdata_s_o11; + output fabric_llpp2_wdata_s_o12; + output fabric_llpp2_wdata_s_o13; + output fabric_llpp2_wdata_s_o14; + output fabric_llpp2_wdata_s_o15; + output fabric_llpp2_wdata_s_o16; + output fabric_llpp2_wdata_s_o17; + output fabric_llpp2_wdata_s_o18; + output fabric_llpp2_wdata_s_o19; + output fabric_llpp2_wdata_s_o2; + output fabric_llpp2_wdata_s_o20; + output fabric_llpp2_wdata_s_o21; + output fabric_llpp2_wdata_s_o22; + output fabric_llpp2_wdata_s_o23; + output fabric_llpp2_wdata_s_o24; + output fabric_llpp2_wdata_s_o25; + output fabric_llpp2_wdata_s_o26; + output fabric_llpp2_wdata_s_o27; + output fabric_llpp2_wdata_s_o28; + output fabric_llpp2_wdata_s_o29; + output fabric_llpp2_wdata_s_o3; + output fabric_llpp2_wdata_s_o30; + output fabric_llpp2_wdata_s_o31; + output fabric_llpp2_wdata_s_o32; + output fabric_llpp2_wdata_s_o4; + output fabric_llpp2_wdata_s_o5; + output fabric_llpp2_wdata_s_o6; + output fabric_llpp2_wdata_s_o7; + output fabric_llpp2_wdata_s_o8; + output fabric_llpp2_wdata_s_o9; + output fabric_llpp2_wlast_s_o; + input fabric_llpp2_wready_s_i; + output fabric_llpp2_wstrb_s_o1; + output fabric_llpp2_wstrb_s_o2; + output fabric_llpp2_wstrb_s_o3; + output fabric_llpp2_wstrb_s_o4; + output fabric_llpp2_wvalid_s_o; + output fabric_llpp3_araddr_s_o1; + output fabric_llpp3_araddr_s_o10; + output fabric_llpp3_araddr_s_o11; + output fabric_llpp3_araddr_s_o12; + output fabric_llpp3_araddr_s_o13; + output fabric_llpp3_araddr_s_o14; + output fabric_llpp3_araddr_s_o15; + output fabric_llpp3_araddr_s_o16; + output fabric_llpp3_araddr_s_o17; + output fabric_llpp3_araddr_s_o18; + output fabric_llpp3_araddr_s_o19; + output fabric_llpp3_araddr_s_o2; + output fabric_llpp3_araddr_s_o20; + output fabric_llpp3_araddr_s_o21; + output fabric_llpp3_araddr_s_o22; + output fabric_llpp3_araddr_s_o23; + output fabric_llpp3_araddr_s_o24; + output fabric_llpp3_araddr_s_o25; + output fabric_llpp3_araddr_s_o26; + output fabric_llpp3_araddr_s_o27; + output fabric_llpp3_araddr_s_o28; + output fabric_llpp3_araddr_s_o29; + output fabric_llpp3_araddr_s_o3; + output fabric_llpp3_araddr_s_o30; + output fabric_llpp3_araddr_s_o31; + output fabric_llpp3_araddr_s_o32; + output fabric_llpp3_araddr_s_o4; + output fabric_llpp3_araddr_s_o5; + output fabric_llpp3_araddr_s_o6; + output fabric_llpp3_araddr_s_o7; + output fabric_llpp3_araddr_s_o8; + output fabric_llpp3_araddr_s_o9; + output fabric_llpp3_arburst_s_o1; + output fabric_llpp3_arburst_s_o2; + output fabric_llpp3_arcache_s_o1; + output fabric_llpp3_arcache_s_o2; + output fabric_llpp3_arcache_s_o3; + output fabric_llpp3_arcache_s_o4; + output fabric_llpp3_arid_s_o1; + output fabric_llpp3_arid_s_o10; + output fabric_llpp3_arid_s_o11; + output fabric_llpp3_arid_s_o12; + output fabric_llpp3_arid_s_o2; + output fabric_llpp3_arid_s_o3; + output fabric_llpp3_arid_s_o4; + output fabric_llpp3_arid_s_o5; + output fabric_llpp3_arid_s_o6; + output fabric_llpp3_arid_s_o7; + output fabric_llpp3_arid_s_o8; + output fabric_llpp3_arid_s_o9; + output fabric_llpp3_arlen_s_o1; + output fabric_llpp3_arlen_s_o2; + output fabric_llpp3_arlen_s_o3; + output fabric_llpp3_arlen_s_o4; + output fabric_llpp3_arlen_s_o5; + output fabric_llpp3_arlen_s_o6; + output fabric_llpp3_arlen_s_o7; + output fabric_llpp3_arlen_s_o8; + output fabric_llpp3_arlock_s_o; + output fabric_llpp3_arprot_s_o1; + output fabric_llpp3_arprot_s_o2; + output fabric_llpp3_arprot_s_o3; + output fabric_llpp3_arqos_s_o1; + output fabric_llpp3_arqos_s_o2; + output fabric_llpp3_arqos_s_o3; + output fabric_llpp3_arqos_s_o4; + input fabric_llpp3_arready_s_i; + output fabric_llpp3_arsize_s_o1; + output fabric_llpp3_arsize_s_o2; + output fabric_llpp3_arsize_s_o3; + output fabric_llpp3_arvalid_s_o; + output fabric_llpp3_awaddr_s_o1; + output fabric_llpp3_awaddr_s_o10; + output fabric_llpp3_awaddr_s_o11; + output fabric_llpp3_awaddr_s_o12; + output fabric_llpp3_awaddr_s_o13; + output fabric_llpp3_awaddr_s_o14; + output fabric_llpp3_awaddr_s_o15; + output fabric_llpp3_awaddr_s_o16; + output fabric_llpp3_awaddr_s_o17; + output fabric_llpp3_awaddr_s_o18; + output fabric_llpp3_awaddr_s_o19; + output fabric_llpp3_awaddr_s_o2; + output fabric_llpp3_awaddr_s_o20; + output fabric_llpp3_awaddr_s_o21; + output fabric_llpp3_awaddr_s_o22; + output fabric_llpp3_awaddr_s_o23; + output fabric_llpp3_awaddr_s_o24; + output fabric_llpp3_awaddr_s_o25; + output fabric_llpp3_awaddr_s_o26; + output fabric_llpp3_awaddr_s_o27; + output fabric_llpp3_awaddr_s_o28; + output fabric_llpp3_awaddr_s_o29; + output fabric_llpp3_awaddr_s_o3; + output fabric_llpp3_awaddr_s_o30; + output fabric_llpp3_awaddr_s_o31; + output fabric_llpp3_awaddr_s_o32; + output fabric_llpp3_awaddr_s_o4; + output fabric_llpp3_awaddr_s_o5; + output fabric_llpp3_awaddr_s_o6; + output fabric_llpp3_awaddr_s_o7; + output fabric_llpp3_awaddr_s_o8; + output fabric_llpp3_awaddr_s_o9; + output fabric_llpp3_awburst_s_o1; + output fabric_llpp3_awburst_s_o2; + output fabric_llpp3_awcache_s_o1; + output fabric_llpp3_awcache_s_o2; + output fabric_llpp3_awcache_s_o3; + output fabric_llpp3_awcache_s_o4; + output fabric_llpp3_awid_s_o1; + output fabric_llpp3_awid_s_o10; + output fabric_llpp3_awid_s_o11; + output fabric_llpp3_awid_s_o12; + output fabric_llpp3_awid_s_o2; + output fabric_llpp3_awid_s_o3; + output fabric_llpp3_awid_s_o4; + output fabric_llpp3_awid_s_o5; + output fabric_llpp3_awid_s_o6; + output fabric_llpp3_awid_s_o7; + output fabric_llpp3_awid_s_o8; + output fabric_llpp3_awid_s_o9; + output fabric_llpp3_awlen_s_o1; + output fabric_llpp3_awlen_s_o2; + output fabric_llpp3_awlen_s_o3; + output fabric_llpp3_awlen_s_o4; + output fabric_llpp3_awlen_s_o5; + output fabric_llpp3_awlen_s_o6; + output fabric_llpp3_awlen_s_o7; + output fabric_llpp3_awlen_s_o8; + output fabric_llpp3_awlock_s_o; + output fabric_llpp3_awprot_s_o1; + output fabric_llpp3_awprot_s_o2; + output fabric_llpp3_awprot_s_o3; + output fabric_llpp3_awqos_s_o1; + output fabric_llpp3_awqos_s_o2; + output fabric_llpp3_awqos_s_o3; + output fabric_llpp3_awqos_s_o4; + input fabric_llpp3_awready_s_i; + output fabric_llpp3_awsize_s_o1; + output fabric_llpp3_awsize_s_o2; + output fabric_llpp3_awsize_s_o3; + output fabric_llpp3_awvalid_s_o; + input fabric_llpp3_bid_s_i1; + input fabric_llpp3_bid_s_i10; + input fabric_llpp3_bid_s_i11; + input fabric_llpp3_bid_s_i12; + input fabric_llpp3_bid_s_i2; + input fabric_llpp3_bid_s_i3; + input fabric_llpp3_bid_s_i4; + input fabric_llpp3_bid_s_i5; + input fabric_llpp3_bid_s_i6; + input fabric_llpp3_bid_s_i7; + input fabric_llpp3_bid_s_i8; + input fabric_llpp3_bid_s_i9; + output fabric_llpp3_bready_s_o; + input fabric_llpp3_bresp_s_i1; + input fabric_llpp3_bresp_s_i2; + input fabric_llpp3_bvalid_s_i; + input fabric_llpp3_rdata_s_i1; + input fabric_llpp3_rdata_s_i10; + input fabric_llpp3_rdata_s_i11; + input fabric_llpp3_rdata_s_i12; + input fabric_llpp3_rdata_s_i13; + input fabric_llpp3_rdata_s_i14; + input fabric_llpp3_rdata_s_i15; + input fabric_llpp3_rdata_s_i16; + input fabric_llpp3_rdata_s_i17; + input fabric_llpp3_rdata_s_i18; + input fabric_llpp3_rdata_s_i19; + input fabric_llpp3_rdata_s_i2; + input fabric_llpp3_rdata_s_i20; + input fabric_llpp3_rdata_s_i21; + input fabric_llpp3_rdata_s_i22; + input fabric_llpp3_rdata_s_i23; + input fabric_llpp3_rdata_s_i24; + input fabric_llpp3_rdata_s_i25; + input fabric_llpp3_rdata_s_i26; + input fabric_llpp3_rdata_s_i27; + input fabric_llpp3_rdata_s_i28; + input fabric_llpp3_rdata_s_i29; + input fabric_llpp3_rdata_s_i3; + input fabric_llpp3_rdata_s_i30; + input fabric_llpp3_rdata_s_i31; + input fabric_llpp3_rdata_s_i32; + input fabric_llpp3_rdata_s_i4; + input fabric_llpp3_rdata_s_i5; + input fabric_llpp3_rdata_s_i6; + input fabric_llpp3_rdata_s_i7; + input fabric_llpp3_rdata_s_i8; + input fabric_llpp3_rdata_s_i9; + input fabric_llpp3_rid_s_i1; + input fabric_llpp3_rid_s_i10; + input fabric_llpp3_rid_s_i11; + input fabric_llpp3_rid_s_i12; + input fabric_llpp3_rid_s_i2; + input fabric_llpp3_rid_s_i3; + input fabric_llpp3_rid_s_i4; + input fabric_llpp3_rid_s_i5; + input fabric_llpp3_rid_s_i6; + input fabric_llpp3_rid_s_i7; + input fabric_llpp3_rid_s_i8; + input fabric_llpp3_rid_s_i9; + input fabric_llpp3_rlast_s_i; + output fabric_llpp3_rready_s_o; + input fabric_llpp3_rresp_s_i1; + input fabric_llpp3_rresp_s_i2; + input fabric_llpp3_rvalid_s_i; + output fabric_llpp3_wdata_s_o1; + output fabric_llpp3_wdata_s_o10; + output fabric_llpp3_wdata_s_o11; + output fabric_llpp3_wdata_s_o12; + output fabric_llpp3_wdata_s_o13; + output fabric_llpp3_wdata_s_o14; + output fabric_llpp3_wdata_s_o15; + output fabric_llpp3_wdata_s_o16; + output fabric_llpp3_wdata_s_o17; + output fabric_llpp3_wdata_s_o18; + output fabric_llpp3_wdata_s_o19; + output fabric_llpp3_wdata_s_o2; + output fabric_llpp3_wdata_s_o20; + output fabric_llpp3_wdata_s_o21; + output fabric_llpp3_wdata_s_o22; + output fabric_llpp3_wdata_s_o23; + output fabric_llpp3_wdata_s_o24; + output fabric_llpp3_wdata_s_o25; + output fabric_llpp3_wdata_s_o26; + output fabric_llpp3_wdata_s_o27; + output fabric_llpp3_wdata_s_o28; + output fabric_llpp3_wdata_s_o29; + output fabric_llpp3_wdata_s_o3; + output fabric_llpp3_wdata_s_o30; + output fabric_llpp3_wdata_s_o31; + output fabric_llpp3_wdata_s_o32; + output fabric_llpp3_wdata_s_o4; + output fabric_llpp3_wdata_s_o5; + output fabric_llpp3_wdata_s_o6; + output fabric_llpp3_wdata_s_o7; + output fabric_llpp3_wdata_s_o8; + output fabric_llpp3_wdata_s_o9; + output fabric_llpp3_wlast_s_o; + input fabric_llpp3_wready_s_i; + output fabric_llpp3_wstrb_s_o1; + output fabric_llpp3_wstrb_s_o2; + output fabric_llpp3_wstrb_s_o3; + output fabric_llpp3_wstrb_s_o4; + output fabric_llpp3_wvalid_s_o; + input fabric_lowskew_i10; + input fabric_lowskew_i11; + input fabric_lowskew_i12; + input fabric_lowskew_i13; + input fabric_lowskew_i14; + input fabric_lowskew_i15; + input fabric_lowskew_i16; + input fabric_lowskew_i17; + input fabric_lowskew_i18; + input fabric_lowskew_i19; + input fabric_lowskew_i3; + input fabric_lowskew_i4; + input fabric_lowskew_i5; + input fabric_lowskew_i6; + input fabric_lowskew_i7; + input fabric_lowskew_i8; + input fabric_lowskew_i9; + output fabric_lowskew_o1; + output fabric_lowskew_o2; + input fabric_qos_ppaddr_i1; + input fabric_qos_ppaddr_i10; + input fabric_qos_ppaddr_i11; + input fabric_qos_ppaddr_i12; + input fabric_qos_ppaddr_i13; + input fabric_qos_ppaddr_i14; + input fabric_qos_ppaddr_i15; + input fabric_qos_ppaddr_i16; + input fabric_qos_ppaddr_i17; + input fabric_qos_ppaddr_i18; + input fabric_qos_ppaddr_i19; + input fabric_qos_ppaddr_i2; + input fabric_qos_ppaddr_i20; + input fabric_qos_ppaddr_i21; + input fabric_qos_ppaddr_i22; + input fabric_qos_ppaddr_i23; + input fabric_qos_ppaddr_i24; + input fabric_qos_ppaddr_i25; + input fabric_qos_ppaddr_i26; + input fabric_qos_ppaddr_i27; + input fabric_qos_ppaddr_i28; + input fabric_qos_ppaddr_i29; + input fabric_qos_ppaddr_i3; + input fabric_qos_ppaddr_i30; + input fabric_qos_ppaddr_i31; + input fabric_qos_ppaddr_i32; + input fabric_qos_ppaddr_i4; + input fabric_qos_ppaddr_i5; + input fabric_qos_ppaddr_i6; + input fabric_qos_ppaddr_i7; + input fabric_qos_ppaddr_i8; + input fabric_qos_ppaddr_i9; + input fabric_qos_ppenable_i; + output fabric_qos_pprdata_o1; + output fabric_qos_pprdata_o10; + output fabric_qos_pprdata_o11; + output fabric_qos_pprdata_o12; + output fabric_qos_pprdata_o13; + output fabric_qos_pprdata_o14; + output fabric_qos_pprdata_o15; + output fabric_qos_pprdata_o16; + output fabric_qos_pprdata_o17; + output fabric_qos_pprdata_o18; + output fabric_qos_pprdata_o19; + output fabric_qos_pprdata_o2; + output fabric_qos_pprdata_o20; + output fabric_qos_pprdata_o21; + output fabric_qos_pprdata_o22; + output fabric_qos_pprdata_o23; + output fabric_qos_pprdata_o24; + output fabric_qos_pprdata_o25; + output fabric_qos_pprdata_o26; + output fabric_qos_pprdata_o27; + output fabric_qos_pprdata_o28; + output fabric_qos_pprdata_o29; + output fabric_qos_pprdata_o3; + output fabric_qos_pprdata_o30; + output fabric_qos_pprdata_o31; + output fabric_qos_pprdata_o32; + output fabric_qos_pprdata_o4; + output fabric_qos_pprdata_o5; + output fabric_qos_pprdata_o6; + output fabric_qos_pprdata_o7; + output fabric_qos_pprdata_o8; + output fabric_qos_pprdata_o9; + output fabric_qos_ppready_o; + output fabric_qos_ppslverr_o; + input fabric_qos_ppwdata_i1; + input fabric_qos_ppwdata_i10; + input fabric_qos_ppwdata_i11; + input fabric_qos_ppwdata_i12; + input fabric_qos_ppwdata_i13; + input fabric_qos_ppwdata_i14; + input fabric_qos_ppwdata_i15; + input fabric_qos_ppwdata_i16; + input fabric_qos_ppwdata_i17; + input fabric_qos_ppwdata_i18; + input fabric_qos_ppwdata_i19; + input fabric_qos_ppwdata_i2; + input fabric_qos_ppwdata_i20; + input fabric_qos_ppwdata_i21; + input fabric_qos_ppwdata_i22; + input fabric_qos_ppwdata_i23; + input fabric_qos_ppwdata_i24; + input fabric_qos_ppwdata_i25; + input fabric_qos_ppwdata_i26; + input fabric_qos_ppwdata_i27; + input fabric_qos_ppwdata_i28; + input fabric_qos_ppwdata_i29; + input fabric_qos_ppwdata_i3; + input fabric_qos_ppwdata_i30; + input fabric_qos_ppwdata_i31; + input fabric_qos_ppwdata_i32; + input fabric_qos_ppwdata_i4; + input fabric_qos_ppwdata_i5; + input fabric_qos_ppwdata_i6; + input fabric_qos_ppwdata_i7; + input fabric_qos_ppwdata_i8; + input fabric_qos_ppwdata_i9; + input fabric_qos_ppwrite_i; + input fabric_qos_presetn_i; + input fabric_qos_psel_i; + output fabric_soc_mon_sensor_alarm_o; + output fabric_spw_interrupts_o1; + output fabric_spw_interrupts_o2; + output fabric_spw_interrupts_o3; + output fabric_spw_interrupts_toggle_o1; + output fabric_spw_interrupts_toggle_o2; + output fabric_spw_interrupts_toggle_o3; + input fabric_sysc_hold_on_debug_i; + output fabric_tnd_fpga_apb_master_paddr_o1; + output fabric_tnd_fpga_apb_master_paddr_o10; + output fabric_tnd_fpga_apb_master_paddr_o11; + output fabric_tnd_fpga_apb_master_paddr_o12; + output fabric_tnd_fpga_apb_master_paddr_o13; + output fabric_tnd_fpga_apb_master_paddr_o14; + output fabric_tnd_fpga_apb_master_paddr_o15; + output fabric_tnd_fpga_apb_master_paddr_o16; + output fabric_tnd_fpga_apb_master_paddr_o17; + output fabric_tnd_fpga_apb_master_paddr_o18; + output fabric_tnd_fpga_apb_master_paddr_o19; + output fabric_tnd_fpga_apb_master_paddr_o2; + output fabric_tnd_fpga_apb_master_paddr_o20; + output fabric_tnd_fpga_apb_master_paddr_o21; + output fabric_tnd_fpga_apb_master_paddr_o22; + output fabric_tnd_fpga_apb_master_paddr_o23; + output fabric_tnd_fpga_apb_master_paddr_o24; + output fabric_tnd_fpga_apb_master_paddr_o25; + output fabric_tnd_fpga_apb_master_paddr_o26; + output fabric_tnd_fpga_apb_master_paddr_o27; + output fabric_tnd_fpga_apb_master_paddr_o28; + output fabric_tnd_fpga_apb_master_paddr_o29; + output fabric_tnd_fpga_apb_master_paddr_o3; + output fabric_tnd_fpga_apb_master_paddr_o30; + output fabric_tnd_fpga_apb_master_paddr_o31; + output fabric_tnd_fpga_apb_master_paddr_o32; + output fabric_tnd_fpga_apb_master_paddr_o4; + output fabric_tnd_fpga_apb_master_paddr_o5; + output fabric_tnd_fpga_apb_master_paddr_o6; + output fabric_tnd_fpga_apb_master_paddr_o7; + output fabric_tnd_fpga_apb_master_paddr_o8; + output fabric_tnd_fpga_apb_master_paddr_o9; + output fabric_tnd_fpga_apb_master_penable_o; + input fabric_tnd_fpga_apb_master_prdata_i1; + input fabric_tnd_fpga_apb_master_prdata_i10; + input fabric_tnd_fpga_apb_master_prdata_i11; + input fabric_tnd_fpga_apb_master_prdata_i12; + input fabric_tnd_fpga_apb_master_prdata_i13; + input fabric_tnd_fpga_apb_master_prdata_i14; + input fabric_tnd_fpga_apb_master_prdata_i15; + input fabric_tnd_fpga_apb_master_prdata_i16; + input fabric_tnd_fpga_apb_master_prdata_i17; + input fabric_tnd_fpga_apb_master_prdata_i18; + input fabric_tnd_fpga_apb_master_prdata_i19; + input fabric_tnd_fpga_apb_master_prdata_i2; + input fabric_tnd_fpga_apb_master_prdata_i20; + input fabric_tnd_fpga_apb_master_prdata_i21; + input fabric_tnd_fpga_apb_master_prdata_i22; + input fabric_tnd_fpga_apb_master_prdata_i23; + input fabric_tnd_fpga_apb_master_prdata_i24; + input fabric_tnd_fpga_apb_master_prdata_i25; + input fabric_tnd_fpga_apb_master_prdata_i26; + input fabric_tnd_fpga_apb_master_prdata_i27; + input fabric_tnd_fpga_apb_master_prdata_i28; + input fabric_tnd_fpga_apb_master_prdata_i29; + input fabric_tnd_fpga_apb_master_prdata_i3; + input fabric_tnd_fpga_apb_master_prdata_i30; + input fabric_tnd_fpga_apb_master_prdata_i31; + input fabric_tnd_fpga_apb_master_prdata_i32; + input fabric_tnd_fpga_apb_master_prdata_i4; + input fabric_tnd_fpga_apb_master_prdata_i5; + input fabric_tnd_fpga_apb_master_prdata_i6; + input fabric_tnd_fpga_apb_master_prdata_i7; + input fabric_tnd_fpga_apb_master_prdata_i8; + input fabric_tnd_fpga_apb_master_prdata_i9; + input fabric_tnd_fpga_apb_master_pready_i; + output fabric_tnd_fpga_apb_master_psel_o; + input fabric_tnd_fpga_apb_master_pslverr_i; + output fabric_tnd_fpga_apb_master_pwdata_o1; + output fabric_tnd_fpga_apb_master_pwdata_o10; + output fabric_tnd_fpga_apb_master_pwdata_o11; + output fabric_tnd_fpga_apb_master_pwdata_o12; + output fabric_tnd_fpga_apb_master_pwdata_o13; + output fabric_tnd_fpga_apb_master_pwdata_o14; + output fabric_tnd_fpga_apb_master_pwdata_o15; + output fabric_tnd_fpga_apb_master_pwdata_o16; + output fabric_tnd_fpga_apb_master_pwdata_o17; + output fabric_tnd_fpga_apb_master_pwdata_o18; + output fabric_tnd_fpga_apb_master_pwdata_o19; + output fabric_tnd_fpga_apb_master_pwdata_o2; + output fabric_tnd_fpga_apb_master_pwdata_o20; + output fabric_tnd_fpga_apb_master_pwdata_o21; + output fabric_tnd_fpga_apb_master_pwdata_o22; + output fabric_tnd_fpga_apb_master_pwdata_o23; + output fabric_tnd_fpga_apb_master_pwdata_o24; + output fabric_tnd_fpga_apb_master_pwdata_o25; + output fabric_tnd_fpga_apb_master_pwdata_o26; + output fabric_tnd_fpga_apb_master_pwdata_o27; + output fabric_tnd_fpga_apb_master_pwdata_o28; + output fabric_tnd_fpga_apb_master_pwdata_o29; + output fabric_tnd_fpga_apb_master_pwdata_o3; + output fabric_tnd_fpga_apb_master_pwdata_o30; + output fabric_tnd_fpga_apb_master_pwdata_o31; + output fabric_tnd_fpga_apb_master_pwdata_o32; + output fabric_tnd_fpga_apb_master_pwdata_o4; + output fabric_tnd_fpga_apb_master_pwdata_o5; + output fabric_tnd_fpga_apb_master_pwdata_o6; + output fabric_tnd_fpga_apb_master_pwdata_o7; + output fabric_tnd_fpga_apb_master_pwdata_o8; + output fabric_tnd_fpga_apb_master_pwdata_o9; + output fabric_tnd_fpga_apb_master_pwrite_o; + input fabric_tnd_fpga_atb_master_afready_i; + output fabric_tnd_fpga_atb_master_afvalid_o; + input fabric_tnd_fpga_atb_master_atbytes_i1; + input fabric_tnd_fpga_atb_master_atbytes_i2; + input fabric_tnd_fpga_atb_master_atbytes_i3; + input fabric_tnd_fpga_atb_master_atbytes_i4; + input fabric_tnd_fpga_atb_master_atdata_i1; + input fabric_tnd_fpga_atb_master_atdata_i10; + input fabric_tnd_fpga_atb_master_atdata_i100; + input fabric_tnd_fpga_atb_master_atdata_i101; + input fabric_tnd_fpga_atb_master_atdata_i102; + input fabric_tnd_fpga_atb_master_atdata_i103; + input fabric_tnd_fpga_atb_master_atdata_i104; + input fabric_tnd_fpga_atb_master_atdata_i105; + input fabric_tnd_fpga_atb_master_atdata_i106; + input fabric_tnd_fpga_atb_master_atdata_i107; + input fabric_tnd_fpga_atb_master_atdata_i108; + input fabric_tnd_fpga_atb_master_atdata_i109; + input fabric_tnd_fpga_atb_master_atdata_i11; + input fabric_tnd_fpga_atb_master_atdata_i110; + input fabric_tnd_fpga_atb_master_atdata_i111; + input fabric_tnd_fpga_atb_master_atdata_i112; + input fabric_tnd_fpga_atb_master_atdata_i113; + input fabric_tnd_fpga_atb_master_atdata_i114; + input fabric_tnd_fpga_atb_master_atdata_i115; + input fabric_tnd_fpga_atb_master_atdata_i116; + input fabric_tnd_fpga_atb_master_atdata_i117; + input fabric_tnd_fpga_atb_master_atdata_i118; + input fabric_tnd_fpga_atb_master_atdata_i119; + input fabric_tnd_fpga_atb_master_atdata_i12; + input fabric_tnd_fpga_atb_master_atdata_i120; + input fabric_tnd_fpga_atb_master_atdata_i121; + input fabric_tnd_fpga_atb_master_atdata_i122; + input fabric_tnd_fpga_atb_master_atdata_i123; + input fabric_tnd_fpga_atb_master_atdata_i124; + input fabric_tnd_fpga_atb_master_atdata_i125; + input fabric_tnd_fpga_atb_master_atdata_i126; + input fabric_tnd_fpga_atb_master_atdata_i127; + input fabric_tnd_fpga_atb_master_atdata_i128; + input fabric_tnd_fpga_atb_master_atdata_i13; + input fabric_tnd_fpga_atb_master_atdata_i14; + input fabric_tnd_fpga_atb_master_atdata_i15; + input fabric_tnd_fpga_atb_master_atdata_i16; + input fabric_tnd_fpga_atb_master_atdata_i17; + input fabric_tnd_fpga_atb_master_atdata_i18; + input fabric_tnd_fpga_atb_master_atdata_i19; + input fabric_tnd_fpga_atb_master_atdata_i2; + input fabric_tnd_fpga_atb_master_atdata_i20; + input fabric_tnd_fpga_atb_master_atdata_i21; + input fabric_tnd_fpga_atb_master_atdata_i22; + input fabric_tnd_fpga_atb_master_atdata_i23; + input fabric_tnd_fpga_atb_master_atdata_i24; + input fabric_tnd_fpga_atb_master_atdata_i25; + input fabric_tnd_fpga_atb_master_atdata_i26; + input fabric_tnd_fpga_atb_master_atdata_i27; + input fabric_tnd_fpga_atb_master_atdata_i28; + input fabric_tnd_fpga_atb_master_atdata_i29; + input fabric_tnd_fpga_atb_master_atdata_i3; + input fabric_tnd_fpga_atb_master_atdata_i30; + input fabric_tnd_fpga_atb_master_atdata_i31; + input fabric_tnd_fpga_atb_master_atdata_i32; + input fabric_tnd_fpga_atb_master_atdata_i33; + input fabric_tnd_fpga_atb_master_atdata_i34; + input fabric_tnd_fpga_atb_master_atdata_i35; + input fabric_tnd_fpga_atb_master_atdata_i36; + input fabric_tnd_fpga_atb_master_atdata_i37; + input fabric_tnd_fpga_atb_master_atdata_i38; + input fabric_tnd_fpga_atb_master_atdata_i39; + input fabric_tnd_fpga_atb_master_atdata_i4; + input fabric_tnd_fpga_atb_master_atdata_i40; + input fabric_tnd_fpga_atb_master_atdata_i41; + input fabric_tnd_fpga_atb_master_atdata_i42; + input fabric_tnd_fpga_atb_master_atdata_i43; + input fabric_tnd_fpga_atb_master_atdata_i44; + input fabric_tnd_fpga_atb_master_atdata_i45; + input fabric_tnd_fpga_atb_master_atdata_i46; + input fabric_tnd_fpga_atb_master_atdata_i47; + input fabric_tnd_fpga_atb_master_atdata_i48; + input fabric_tnd_fpga_atb_master_atdata_i49; + input fabric_tnd_fpga_atb_master_atdata_i5; + input fabric_tnd_fpga_atb_master_atdata_i50; + input fabric_tnd_fpga_atb_master_atdata_i51; + input fabric_tnd_fpga_atb_master_atdata_i52; + input fabric_tnd_fpga_atb_master_atdata_i53; + input fabric_tnd_fpga_atb_master_atdata_i54; + input fabric_tnd_fpga_atb_master_atdata_i55; + input fabric_tnd_fpga_atb_master_atdata_i56; + input fabric_tnd_fpga_atb_master_atdata_i57; + input fabric_tnd_fpga_atb_master_atdata_i58; + input fabric_tnd_fpga_atb_master_atdata_i59; + input fabric_tnd_fpga_atb_master_atdata_i6; + input fabric_tnd_fpga_atb_master_atdata_i60; + input fabric_tnd_fpga_atb_master_atdata_i61; + input fabric_tnd_fpga_atb_master_atdata_i62; + input fabric_tnd_fpga_atb_master_atdata_i63; + input fabric_tnd_fpga_atb_master_atdata_i64; + input fabric_tnd_fpga_atb_master_atdata_i65; + input fabric_tnd_fpga_atb_master_atdata_i66; + input fabric_tnd_fpga_atb_master_atdata_i67; + input fabric_tnd_fpga_atb_master_atdata_i68; + input fabric_tnd_fpga_atb_master_atdata_i69; + input fabric_tnd_fpga_atb_master_atdata_i7; + input fabric_tnd_fpga_atb_master_atdata_i70; + input fabric_tnd_fpga_atb_master_atdata_i71; + input fabric_tnd_fpga_atb_master_atdata_i72; + input fabric_tnd_fpga_atb_master_atdata_i73; + input fabric_tnd_fpga_atb_master_atdata_i74; + input fabric_tnd_fpga_atb_master_atdata_i75; + input fabric_tnd_fpga_atb_master_atdata_i76; + input fabric_tnd_fpga_atb_master_atdata_i77; + input fabric_tnd_fpga_atb_master_atdata_i78; + input fabric_tnd_fpga_atb_master_atdata_i79; + input fabric_tnd_fpga_atb_master_atdata_i8; + input fabric_tnd_fpga_atb_master_atdata_i80; + input fabric_tnd_fpga_atb_master_atdata_i81; + input fabric_tnd_fpga_atb_master_atdata_i82; + input fabric_tnd_fpga_atb_master_atdata_i83; + input fabric_tnd_fpga_atb_master_atdata_i84; + input fabric_tnd_fpga_atb_master_atdata_i85; + input fabric_tnd_fpga_atb_master_atdata_i86; + input fabric_tnd_fpga_atb_master_atdata_i87; + input fabric_tnd_fpga_atb_master_atdata_i88; + input fabric_tnd_fpga_atb_master_atdata_i89; + input fabric_tnd_fpga_atb_master_atdata_i9; + input fabric_tnd_fpga_atb_master_atdata_i90; + input fabric_tnd_fpga_atb_master_atdata_i91; + input fabric_tnd_fpga_atb_master_atdata_i92; + input fabric_tnd_fpga_atb_master_atdata_i93; + input fabric_tnd_fpga_atb_master_atdata_i94; + input fabric_tnd_fpga_atb_master_atdata_i95; + input fabric_tnd_fpga_atb_master_atdata_i96; + input fabric_tnd_fpga_atb_master_atdata_i97; + input fabric_tnd_fpga_atb_master_atdata_i98; + input fabric_tnd_fpga_atb_master_atdata_i99; + input fabric_tnd_fpga_atb_master_atid_i1; + input fabric_tnd_fpga_atb_master_atid_i2; + input fabric_tnd_fpga_atb_master_atid_i3; + input fabric_tnd_fpga_atb_master_atid_i4; + input fabric_tnd_fpga_atb_master_atid_i5; + input fabric_tnd_fpga_atb_master_atid_i6; + input fabric_tnd_fpga_atb_master_atid_i7; + output fabric_tnd_fpga_atb_master_atready_o; + input fabric_tnd_fpga_atb_master_atvalid_i; + output fabric_tnd_fpga_atb_master_syncreq_o; + output fabric_tnd_hssl_apb_master_paddr_o1; + output fabric_tnd_hssl_apb_master_paddr_o10; + output fabric_tnd_hssl_apb_master_paddr_o11; + output fabric_tnd_hssl_apb_master_paddr_o12; + output fabric_tnd_hssl_apb_master_paddr_o13; + output fabric_tnd_hssl_apb_master_paddr_o14; + output fabric_tnd_hssl_apb_master_paddr_o15; + output fabric_tnd_hssl_apb_master_paddr_o16; + output fabric_tnd_hssl_apb_master_paddr_o17; + output fabric_tnd_hssl_apb_master_paddr_o18; + output fabric_tnd_hssl_apb_master_paddr_o19; + output fabric_tnd_hssl_apb_master_paddr_o2; + output fabric_tnd_hssl_apb_master_paddr_o20; + output fabric_tnd_hssl_apb_master_paddr_o21; + output fabric_tnd_hssl_apb_master_paddr_o22; + output fabric_tnd_hssl_apb_master_paddr_o23; + output fabric_tnd_hssl_apb_master_paddr_o24; + output fabric_tnd_hssl_apb_master_paddr_o25; + output fabric_tnd_hssl_apb_master_paddr_o26; + output fabric_tnd_hssl_apb_master_paddr_o27; + output fabric_tnd_hssl_apb_master_paddr_o28; + output fabric_tnd_hssl_apb_master_paddr_o29; + output fabric_tnd_hssl_apb_master_paddr_o3; + output fabric_tnd_hssl_apb_master_paddr_o30; + output fabric_tnd_hssl_apb_master_paddr_o31; + output fabric_tnd_hssl_apb_master_paddr_o32; + output fabric_tnd_hssl_apb_master_paddr_o4; + output fabric_tnd_hssl_apb_master_paddr_o5; + output fabric_tnd_hssl_apb_master_paddr_o6; + output fabric_tnd_hssl_apb_master_paddr_o7; + output fabric_tnd_hssl_apb_master_paddr_o8; + output fabric_tnd_hssl_apb_master_paddr_o9; + output fabric_tnd_hssl_apb_master_penable_o; + input fabric_tnd_hssl_apb_master_prdata_i1; + input fabric_tnd_hssl_apb_master_prdata_i10; + input fabric_tnd_hssl_apb_master_prdata_i11; + input fabric_tnd_hssl_apb_master_prdata_i12; + input fabric_tnd_hssl_apb_master_prdata_i13; + input fabric_tnd_hssl_apb_master_prdata_i14; + input fabric_tnd_hssl_apb_master_prdata_i15; + input fabric_tnd_hssl_apb_master_prdata_i16; + input fabric_tnd_hssl_apb_master_prdata_i17; + input fabric_tnd_hssl_apb_master_prdata_i18; + input fabric_tnd_hssl_apb_master_prdata_i19; + input fabric_tnd_hssl_apb_master_prdata_i2; + input fabric_tnd_hssl_apb_master_prdata_i20; + input fabric_tnd_hssl_apb_master_prdata_i21; + input fabric_tnd_hssl_apb_master_prdata_i22; + input fabric_tnd_hssl_apb_master_prdata_i23; + input fabric_tnd_hssl_apb_master_prdata_i24; + input fabric_tnd_hssl_apb_master_prdata_i25; + input fabric_tnd_hssl_apb_master_prdata_i26; + input fabric_tnd_hssl_apb_master_prdata_i27; + input fabric_tnd_hssl_apb_master_prdata_i28; + input fabric_tnd_hssl_apb_master_prdata_i29; + input fabric_tnd_hssl_apb_master_prdata_i3; + input fabric_tnd_hssl_apb_master_prdata_i30; + input fabric_tnd_hssl_apb_master_prdata_i31; + input fabric_tnd_hssl_apb_master_prdata_i32; + input fabric_tnd_hssl_apb_master_prdata_i4; + input fabric_tnd_hssl_apb_master_prdata_i5; + input fabric_tnd_hssl_apb_master_prdata_i6; + input fabric_tnd_hssl_apb_master_prdata_i7; + input fabric_tnd_hssl_apb_master_prdata_i8; + input fabric_tnd_hssl_apb_master_prdata_i9; + input fabric_tnd_hssl_apb_master_pready_i; + output fabric_tnd_hssl_apb_master_psel_o; + input fabric_tnd_hssl_apb_master_pslverr_i; + output fabric_tnd_hssl_apb_master_pwdata_o1; + output fabric_tnd_hssl_apb_master_pwdata_o10; + output fabric_tnd_hssl_apb_master_pwdata_o11; + output fabric_tnd_hssl_apb_master_pwdata_o12; + output fabric_tnd_hssl_apb_master_pwdata_o13; + output fabric_tnd_hssl_apb_master_pwdata_o14; + output fabric_tnd_hssl_apb_master_pwdata_o15; + output fabric_tnd_hssl_apb_master_pwdata_o16; + output fabric_tnd_hssl_apb_master_pwdata_o17; + output fabric_tnd_hssl_apb_master_pwdata_o18; + output fabric_tnd_hssl_apb_master_pwdata_o19; + output fabric_tnd_hssl_apb_master_pwdata_o2; + output fabric_tnd_hssl_apb_master_pwdata_o20; + output fabric_tnd_hssl_apb_master_pwdata_o21; + output fabric_tnd_hssl_apb_master_pwdata_o22; + output fabric_tnd_hssl_apb_master_pwdata_o23; + output fabric_tnd_hssl_apb_master_pwdata_o24; + output fabric_tnd_hssl_apb_master_pwdata_o25; + output fabric_tnd_hssl_apb_master_pwdata_o26; + output fabric_tnd_hssl_apb_master_pwdata_o27; + output fabric_tnd_hssl_apb_master_pwdata_o28; + output fabric_tnd_hssl_apb_master_pwdata_o29; + output fabric_tnd_hssl_apb_master_pwdata_o3; + output fabric_tnd_hssl_apb_master_pwdata_o30; + output fabric_tnd_hssl_apb_master_pwdata_o31; + output fabric_tnd_hssl_apb_master_pwdata_o32; + output fabric_tnd_hssl_apb_master_pwdata_o4; + output fabric_tnd_hssl_apb_master_pwdata_o5; + output fabric_tnd_hssl_apb_master_pwdata_o6; + output fabric_tnd_hssl_apb_master_pwdata_o7; + output fabric_tnd_hssl_apb_master_pwdata_o8; + output fabric_tnd_hssl_apb_master_pwdata_o9; + output fabric_tnd_hssl_apb_master_pwrite_o; + output fabric_tnd_hssl_atb_master_afready_o; + input fabric_tnd_hssl_atb_master_afvalid_i; + output fabric_tnd_hssl_atb_master_atbytes_o1; + output fabric_tnd_hssl_atb_master_atbytes_o2; + output fabric_tnd_hssl_atb_master_atbytes_o3; + output fabric_tnd_hssl_atb_master_atbytes_o4; + output fabric_tnd_hssl_atb_master_atdata_o1; + output fabric_tnd_hssl_atb_master_atdata_o10; + output fabric_tnd_hssl_atb_master_atdata_o100; + output fabric_tnd_hssl_atb_master_atdata_o101; + output fabric_tnd_hssl_atb_master_atdata_o102; + output fabric_tnd_hssl_atb_master_atdata_o103; + output fabric_tnd_hssl_atb_master_atdata_o104; + output fabric_tnd_hssl_atb_master_atdata_o105; + output fabric_tnd_hssl_atb_master_atdata_o106; + output fabric_tnd_hssl_atb_master_atdata_o107; + output fabric_tnd_hssl_atb_master_atdata_o108; + output fabric_tnd_hssl_atb_master_atdata_o109; + output fabric_tnd_hssl_atb_master_atdata_o11; + output fabric_tnd_hssl_atb_master_atdata_o110; + output fabric_tnd_hssl_atb_master_atdata_o111; + output fabric_tnd_hssl_atb_master_atdata_o112; + output fabric_tnd_hssl_atb_master_atdata_o113; + output fabric_tnd_hssl_atb_master_atdata_o114; + output fabric_tnd_hssl_atb_master_atdata_o115; + output fabric_tnd_hssl_atb_master_atdata_o116; + output fabric_tnd_hssl_atb_master_atdata_o117; + output fabric_tnd_hssl_atb_master_atdata_o118; + output fabric_tnd_hssl_atb_master_atdata_o119; + output fabric_tnd_hssl_atb_master_atdata_o12; + output fabric_tnd_hssl_atb_master_atdata_o120; + output fabric_tnd_hssl_atb_master_atdata_o121; + output fabric_tnd_hssl_atb_master_atdata_o122; + output fabric_tnd_hssl_atb_master_atdata_o123; + output fabric_tnd_hssl_atb_master_atdata_o124; + output fabric_tnd_hssl_atb_master_atdata_o125; + output fabric_tnd_hssl_atb_master_atdata_o126; + output fabric_tnd_hssl_atb_master_atdata_o127; + output fabric_tnd_hssl_atb_master_atdata_o128; + output fabric_tnd_hssl_atb_master_atdata_o13; + output fabric_tnd_hssl_atb_master_atdata_o14; + output fabric_tnd_hssl_atb_master_atdata_o15; + output fabric_tnd_hssl_atb_master_atdata_o16; + output fabric_tnd_hssl_atb_master_atdata_o17; + output fabric_tnd_hssl_atb_master_atdata_o18; + output fabric_tnd_hssl_atb_master_atdata_o19; + output fabric_tnd_hssl_atb_master_atdata_o2; + output fabric_tnd_hssl_atb_master_atdata_o20; + output fabric_tnd_hssl_atb_master_atdata_o21; + output fabric_tnd_hssl_atb_master_atdata_o22; + output fabric_tnd_hssl_atb_master_atdata_o23; + output fabric_tnd_hssl_atb_master_atdata_o24; + output fabric_tnd_hssl_atb_master_atdata_o25; + output fabric_tnd_hssl_atb_master_atdata_o26; + output fabric_tnd_hssl_atb_master_atdata_o27; + output fabric_tnd_hssl_atb_master_atdata_o28; + output fabric_tnd_hssl_atb_master_atdata_o29; + output fabric_tnd_hssl_atb_master_atdata_o3; + output fabric_tnd_hssl_atb_master_atdata_o30; + output fabric_tnd_hssl_atb_master_atdata_o31; + output fabric_tnd_hssl_atb_master_atdata_o32; + output fabric_tnd_hssl_atb_master_atdata_o33; + output fabric_tnd_hssl_atb_master_atdata_o34; + output fabric_tnd_hssl_atb_master_atdata_o35; + output fabric_tnd_hssl_atb_master_atdata_o36; + output fabric_tnd_hssl_atb_master_atdata_o37; + output fabric_tnd_hssl_atb_master_atdata_o38; + output fabric_tnd_hssl_atb_master_atdata_o39; + output fabric_tnd_hssl_atb_master_atdata_o4; + output fabric_tnd_hssl_atb_master_atdata_o40; + output fabric_tnd_hssl_atb_master_atdata_o41; + output fabric_tnd_hssl_atb_master_atdata_o42; + output fabric_tnd_hssl_atb_master_atdata_o43; + output fabric_tnd_hssl_atb_master_atdata_o44; + output fabric_tnd_hssl_atb_master_atdata_o45; + output fabric_tnd_hssl_atb_master_atdata_o46; + output fabric_tnd_hssl_atb_master_atdata_o47; + output fabric_tnd_hssl_atb_master_atdata_o48; + output fabric_tnd_hssl_atb_master_atdata_o49; + output fabric_tnd_hssl_atb_master_atdata_o5; + output fabric_tnd_hssl_atb_master_atdata_o50; + output fabric_tnd_hssl_atb_master_atdata_o51; + output fabric_tnd_hssl_atb_master_atdata_o52; + output fabric_tnd_hssl_atb_master_atdata_o53; + output fabric_tnd_hssl_atb_master_atdata_o54; + output fabric_tnd_hssl_atb_master_atdata_o55; + output fabric_tnd_hssl_atb_master_atdata_o56; + output fabric_tnd_hssl_atb_master_atdata_o57; + output fabric_tnd_hssl_atb_master_atdata_o58; + output fabric_tnd_hssl_atb_master_atdata_o59; + output fabric_tnd_hssl_atb_master_atdata_o6; + output fabric_tnd_hssl_atb_master_atdata_o60; + output fabric_tnd_hssl_atb_master_atdata_o61; + output fabric_tnd_hssl_atb_master_atdata_o62; + output fabric_tnd_hssl_atb_master_atdata_o63; + output fabric_tnd_hssl_atb_master_atdata_o64; + output fabric_tnd_hssl_atb_master_atdata_o65; + output fabric_tnd_hssl_atb_master_atdata_o66; + output fabric_tnd_hssl_atb_master_atdata_o67; + output fabric_tnd_hssl_atb_master_atdata_o68; + output fabric_tnd_hssl_atb_master_atdata_o69; + output fabric_tnd_hssl_atb_master_atdata_o7; + output fabric_tnd_hssl_atb_master_atdata_o70; + output fabric_tnd_hssl_atb_master_atdata_o71; + output fabric_tnd_hssl_atb_master_atdata_o72; + output fabric_tnd_hssl_atb_master_atdata_o73; + output fabric_tnd_hssl_atb_master_atdata_o74; + output fabric_tnd_hssl_atb_master_atdata_o75; + output fabric_tnd_hssl_atb_master_atdata_o76; + output fabric_tnd_hssl_atb_master_atdata_o77; + output fabric_tnd_hssl_atb_master_atdata_o78; + output fabric_tnd_hssl_atb_master_atdata_o79; + output fabric_tnd_hssl_atb_master_atdata_o8; + output fabric_tnd_hssl_atb_master_atdata_o80; + output fabric_tnd_hssl_atb_master_atdata_o81; + output fabric_tnd_hssl_atb_master_atdata_o82; + output fabric_tnd_hssl_atb_master_atdata_o83; + output fabric_tnd_hssl_atb_master_atdata_o84; + output fabric_tnd_hssl_atb_master_atdata_o85; + output fabric_tnd_hssl_atb_master_atdata_o86; + output fabric_tnd_hssl_atb_master_atdata_o87; + output fabric_tnd_hssl_atb_master_atdata_o88; + output fabric_tnd_hssl_atb_master_atdata_o89; + output fabric_tnd_hssl_atb_master_atdata_o9; + output fabric_tnd_hssl_atb_master_atdata_o90; + output fabric_tnd_hssl_atb_master_atdata_o91; + output fabric_tnd_hssl_atb_master_atdata_o92; + output fabric_tnd_hssl_atb_master_atdata_o93; + output fabric_tnd_hssl_atb_master_atdata_o94; + output fabric_tnd_hssl_atb_master_atdata_o95; + output fabric_tnd_hssl_atb_master_atdata_o96; + output fabric_tnd_hssl_atb_master_atdata_o97; + output fabric_tnd_hssl_atb_master_atdata_o98; + output fabric_tnd_hssl_atb_master_atdata_o99; + output fabric_tnd_hssl_atb_master_atid_o1; + output fabric_tnd_hssl_atb_master_atid_o2; + output fabric_tnd_hssl_atb_master_atid_o3; + output fabric_tnd_hssl_atb_master_atid_o4; + output fabric_tnd_hssl_atb_master_atid_o5; + output fabric_tnd_hssl_atb_master_atid_o6; + output fabric_tnd_hssl_atb_master_atid_o7; + input fabric_tnd_hssl_atb_master_atready_i; + output fabric_tnd_hssl_atb_master_atvalid_o; + input fabric_tnd_hssl_atb_master_syncreq_i; + output fabric_tnd_hssl_flushin_o; + output fabric_tnd_hssl_trigin_o; + output fabric_tnd_trace_clk_traceoutportintf_o; + output fabric_tnd_trace_ctl_traceoutportintf_o; + output fabric_tnd_trace_data_traceoutportintf_o1; + output fabric_tnd_trace_data_traceoutportintf_o10; + output fabric_tnd_trace_data_traceoutportintf_o11; + output fabric_tnd_trace_data_traceoutportintf_o12; + output fabric_tnd_trace_data_traceoutportintf_o13; + output fabric_tnd_trace_data_traceoutportintf_o14; + output fabric_tnd_trace_data_traceoutportintf_o15; + output fabric_tnd_trace_data_traceoutportintf_o16; + output fabric_tnd_trace_data_traceoutportintf_o17; + output fabric_tnd_trace_data_traceoutportintf_o18; + output fabric_tnd_trace_data_traceoutportintf_o19; + output fabric_tnd_trace_data_traceoutportintf_o2; + output fabric_tnd_trace_data_traceoutportintf_o20; + output fabric_tnd_trace_data_traceoutportintf_o21; + output fabric_tnd_trace_data_traceoutportintf_o22; + output fabric_tnd_trace_data_traceoutportintf_o23; + output fabric_tnd_trace_data_traceoutportintf_o24; + output fabric_tnd_trace_data_traceoutportintf_o25; + output fabric_tnd_trace_data_traceoutportintf_o26; + output fabric_tnd_trace_data_traceoutportintf_o27; + output fabric_tnd_trace_data_traceoutportintf_o28; + output fabric_tnd_trace_data_traceoutportintf_o29; + output fabric_tnd_trace_data_traceoutportintf_o3; + output fabric_tnd_trace_data_traceoutportintf_o30; + output fabric_tnd_trace_data_traceoutportintf_o31; + output fabric_tnd_trace_data_traceoutportintf_o32; + output fabric_tnd_trace_data_traceoutportintf_o4; + output fabric_tnd_trace_data_traceoutportintf_o5; + output fabric_tnd_trace_data_traceoutportintf_o6; + output fabric_tnd_trace_data_traceoutportintf_o7; + output fabric_tnd_trace_data_traceoutportintf_o8; + output fabric_tnd_trace_data_traceoutportintf_o9; + output fabric_tst_pll_lock_o1; + output fabric_tst_pll_lock_o2; + output fabric_tst_pll_lock_o3; + output fabric_tst_pll_lock_o4; + output fabric_tst_pll_lock_o5; + output fabric_tst_pll_lock_o6; + output fabric_tst_pll_lock_o7; + output fabric_tsvalue_tsgen_fpga_o1; + output fabric_tsvalue_tsgen_fpga_o10; + output fabric_tsvalue_tsgen_fpga_o11; + output fabric_tsvalue_tsgen_fpga_o12; + output fabric_tsvalue_tsgen_fpga_o13; + output fabric_tsvalue_tsgen_fpga_o14; + output fabric_tsvalue_tsgen_fpga_o15; + output fabric_tsvalue_tsgen_fpga_o16; + output fabric_tsvalue_tsgen_fpga_o17; + output fabric_tsvalue_tsgen_fpga_o18; + output fabric_tsvalue_tsgen_fpga_o19; + output fabric_tsvalue_tsgen_fpga_o2; + output fabric_tsvalue_tsgen_fpga_o20; + output fabric_tsvalue_tsgen_fpga_o21; + output fabric_tsvalue_tsgen_fpga_o22; + output fabric_tsvalue_tsgen_fpga_o23; + output fabric_tsvalue_tsgen_fpga_o24; + output fabric_tsvalue_tsgen_fpga_o25; + output fabric_tsvalue_tsgen_fpga_o26; + output fabric_tsvalue_tsgen_fpga_o27; + output fabric_tsvalue_tsgen_fpga_o28; + output fabric_tsvalue_tsgen_fpga_o29; + output fabric_tsvalue_tsgen_fpga_o3; + output fabric_tsvalue_tsgen_fpga_o30; + output fabric_tsvalue_tsgen_fpga_o31; + output fabric_tsvalue_tsgen_fpga_o32; + output fabric_tsvalue_tsgen_fpga_o33; + output fabric_tsvalue_tsgen_fpga_o34; + output fabric_tsvalue_tsgen_fpga_o35; + output fabric_tsvalue_tsgen_fpga_o36; + output fabric_tsvalue_tsgen_fpga_o37; + output fabric_tsvalue_tsgen_fpga_o38; + output fabric_tsvalue_tsgen_fpga_o39; + output fabric_tsvalue_tsgen_fpga_o4; + output fabric_tsvalue_tsgen_fpga_o40; + output fabric_tsvalue_tsgen_fpga_o41; + output fabric_tsvalue_tsgen_fpga_o42; + output fabric_tsvalue_tsgen_fpga_o43; + output fabric_tsvalue_tsgen_fpga_o44; + output fabric_tsvalue_tsgen_fpga_o45; + output fabric_tsvalue_tsgen_fpga_o46; + output fabric_tsvalue_tsgen_fpga_o47; + output fabric_tsvalue_tsgen_fpga_o48; + output fabric_tsvalue_tsgen_fpga_o49; + output fabric_tsvalue_tsgen_fpga_o5; + output fabric_tsvalue_tsgen_fpga_o50; + output fabric_tsvalue_tsgen_fpga_o51; + output fabric_tsvalue_tsgen_fpga_o52; + output fabric_tsvalue_tsgen_fpga_o53; + output fabric_tsvalue_tsgen_fpga_o54; + output fabric_tsvalue_tsgen_fpga_o55; + output fabric_tsvalue_tsgen_fpga_o56; + output fabric_tsvalue_tsgen_fpga_o57; + output fabric_tsvalue_tsgen_fpga_o58; + output fabric_tsvalue_tsgen_fpga_o59; + output fabric_tsvalue_tsgen_fpga_o6; + output fabric_tsvalue_tsgen_fpga_o60; + output fabric_tsvalue_tsgen_fpga_o61; + output fabric_tsvalue_tsgen_fpga_o62; + output fabric_tsvalue_tsgen_fpga_o63; + output fabric_tsvalue_tsgen_fpga_o64; + output fabric_tsvalue_tsgen_fpga_o7; + output fabric_tsvalue_tsgen_fpga_o8; + output fabric_tsvalue_tsgen_fpga_o9; + output fabric_watchdog0_signal_0_o; + output fabric_watchdog0_signal_1_o; + output fabric_watchdog1_signal_0_o; + output fabric_watchdog1_signal_1_o; + output fabric_watchdog2_signal_0_o; + output fabric_watchdog2_signal_1_o; + output fabric_watchdog3_signal_0_o; + output fabric_watchdog3_signal_1_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SOC_INTERFACE_V1(fabric_lowskew_o1, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_o2, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9 +, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2 +, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23 +, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44 +, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65 +, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86 +, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107 +, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7 +, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28 +, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49 +, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10 +, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31 +, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6 +, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3 +, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12 +, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33 +, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8 +, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1 +, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13 +, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34 +, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55 +, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76 +, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97 +, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118 +, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10 +, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11 +, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17 +, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38 +, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59 +, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80 +, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101 +, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122 +, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2 +, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19 +, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40 +, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3 +, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o +, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21 +, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2 +, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5 +, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1 +, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22 +, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43 +, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64 +, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, fabric_fpga_wdata_axi_s2_o68, fabric_fpga_wdata_axi_s2_o69, fabric_fpga_wdata_axi_s2_o70, fabric_fpga_wdata_axi_s2_o71, fabric_fpga_wdata_axi_s2_o72, fabric_fpga_wdata_axi_s2_o73, fabric_fpga_wdata_axi_s2_o74, fabric_fpga_wdata_axi_s2_o75, fabric_fpga_wdata_axi_s2_o76, fabric_fpga_wdata_axi_s2_o77, fabric_fpga_wdata_axi_s2_o78, fabric_fpga_wdata_axi_s2_o79, fabric_fpga_wdata_axi_s2_o80, fabric_fpga_wdata_axi_s2_o81, fabric_fpga_wdata_axi_s2_o82, fabric_fpga_wdata_axi_s2_o83, fabric_fpga_wdata_axi_s2_o84, fabric_fpga_wdata_axi_s2_o85 +, fabric_fpga_wdata_axi_s2_o86, fabric_fpga_wdata_axi_s2_o87, fabric_fpga_wdata_axi_s2_o88, fabric_fpga_wdata_axi_s2_o89, fabric_fpga_wdata_axi_s2_o90, fabric_fpga_wdata_axi_s2_o91, fabric_fpga_wdata_axi_s2_o92, fabric_fpga_wdata_axi_s2_o93, fabric_fpga_wdata_axi_s2_o94, fabric_fpga_wdata_axi_s2_o95, fabric_fpga_wdata_axi_s2_o96, fabric_fpga_wdata_axi_s2_o97, fabric_fpga_wdata_axi_s2_o98, fabric_fpga_wdata_axi_s2_o99, fabric_fpga_wdata_axi_s2_o100, fabric_fpga_wdata_axi_s2_o101, fabric_fpga_wdata_axi_s2_o102, fabric_fpga_wdata_axi_s2_o103, fabric_fpga_wdata_axi_s2_o104, fabric_fpga_wdata_axi_s2_o105, fabric_fpga_wdata_axi_s2_o106 +, fabric_fpga_wdata_axi_s2_o107, fabric_fpga_wdata_axi_s2_o108, fabric_fpga_wdata_axi_s2_o109, fabric_fpga_wdata_axi_s2_o110, fabric_fpga_wdata_axi_s2_o111, fabric_fpga_wdata_axi_s2_o112, fabric_fpga_wdata_axi_s2_o113, fabric_fpga_wdata_axi_s2_o114, fabric_fpga_wdata_axi_s2_o115, fabric_fpga_wdata_axi_s2_o116, fabric_fpga_wdata_axi_s2_o117, fabric_fpga_wdata_axi_s2_o118, fabric_fpga_wdata_axi_s2_o119, fabric_fpga_wdata_axi_s2_o120, fabric_fpga_wdata_axi_s2_o121, fabric_fpga_wdata_axi_s2_o122, fabric_fpga_wdata_axi_s2_o123, fabric_fpga_wdata_axi_s2_o124, fabric_fpga_wdata_axi_s2_o125, fabric_fpga_wdata_axi_s2_o126, fabric_fpga_wdata_axi_s2_o127 +, fabric_fpga_wdata_axi_s2_o128, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wstrb_axi_s2_o1, fabric_fpga_wstrb_axi_s2_o2, fabric_fpga_wstrb_axi_s2_o3, fabric_fpga_wstrb_axi_s2_o4, fabric_fpga_wstrb_axi_s2_o5, fabric_fpga_wstrb_axi_s2_o6, fabric_fpga_wstrb_axi_s2_o7, fabric_fpga_wstrb_axi_s2_o8, fabric_fpga_wstrb_axi_s2_o9, fabric_fpga_wstrb_axi_s2_o10, fabric_fpga_wstrb_axi_s2_o11, fabric_fpga_wstrb_axi_s2_o12, fabric_fpga_wstrb_axi_s2_o13, fabric_fpga_wstrb_axi_s2_o14, fabric_fpga_wstrb_axi_s2_o15, fabric_fpga_wstrb_axi_s2_o16, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i +, fabric_fpga_awready_axi_s2_i, fabric_fpga_bid_axi_s2_i1, fabric_fpga_bid_axi_s2_i2, fabric_fpga_bid_axi_s2_i3, fabric_fpga_bid_axi_s2_i4, fabric_fpga_bid_axi_s2_i5, fabric_fpga_bid_axi_s2_i6, fabric_fpga_bid_axi_s2_i7, fabric_fpga_bid_axi_s2_i8, fabric_fpga_bid_axi_s2_i9, fabric_fpga_bid_axi_s2_i10, fabric_fpga_bid_axi_s2_i11, fabric_fpga_bid_axi_s2_i12, fabric_fpga_bresp_axi_s2_i1, fabric_fpga_bresp_axi_s2_i2, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rdata_axi_s2_i1, fabric_fpga_rdata_axi_s2_i2, fabric_fpga_rdata_axi_s2_i3, fabric_fpga_rdata_axi_s2_i4, fabric_fpga_rdata_axi_s2_i5 +, fabric_fpga_rdata_axi_s2_i6, fabric_fpga_rdata_axi_s2_i7, fabric_fpga_rdata_axi_s2_i8, fabric_fpga_rdata_axi_s2_i9, fabric_fpga_rdata_axi_s2_i10, fabric_fpga_rdata_axi_s2_i11, fabric_fpga_rdata_axi_s2_i12, fabric_fpga_rdata_axi_s2_i13, fabric_fpga_rdata_axi_s2_i14, fabric_fpga_rdata_axi_s2_i15, fabric_fpga_rdata_axi_s2_i16, fabric_fpga_rdata_axi_s2_i17, fabric_fpga_rdata_axi_s2_i18, fabric_fpga_rdata_axi_s2_i19, fabric_fpga_rdata_axi_s2_i20, fabric_fpga_rdata_axi_s2_i21, fabric_fpga_rdata_axi_s2_i22, fabric_fpga_rdata_axi_s2_i23, fabric_fpga_rdata_axi_s2_i24, fabric_fpga_rdata_axi_s2_i25, fabric_fpga_rdata_axi_s2_i26 +, fabric_fpga_rdata_axi_s2_i27, fabric_fpga_rdata_axi_s2_i28, fabric_fpga_rdata_axi_s2_i29, fabric_fpga_rdata_axi_s2_i30, fabric_fpga_rdata_axi_s2_i31, fabric_fpga_rdata_axi_s2_i32, fabric_fpga_rdata_axi_s2_i33, fabric_fpga_rdata_axi_s2_i34, fabric_fpga_rdata_axi_s2_i35, fabric_fpga_rdata_axi_s2_i36, fabric_fpga_rdata_axi_s2_i37, fabric_fpga_rdata_axi_s2_i38, fabric_fpga_rdata_axi_s2_i39, fabric_fpga_rdata_axi_s2_i40, fabric_fpga_rdata_axi_s2_i41, fabric_fpga_rdata_axi_s2_i42, fabric_fpga_rdata_axi_s2_i43, fabric_fpga_rdata_axi_s2_i44, fabric_fpga_rdata_axi_s2_i45, fabric_fpga_rdata_axi_s2_i46, fabric_fpga_rdata_axi_s2_i47 +, fabric_fpga_rdata_axi_s2_i48, fabric_fpga_rdata_axi_s2_i49, fabric_fpga_rdata_axi_s2_i50, fabric_fpga_rdata_axi_s2_i51, fabric_fpga_rdata_axi_s2_i52, fabric_fpga_rdata_axi_s2_i53, fabric_fpga_rdata_axi_s2_i54, fabric_fpga_rdata_axi_s2_i55, fabric_fpga_rdata_axi_s2_i56, fabric_fpga_rdata_axi_s2_i57, fabric_fpga_rdata_axi_s2_i58, fabric_fpga_rdata_axi_s2_i59, fabric_fpga_rdata_axi_s2_i60, fabric_fpga_rdata_axi_s2_i61, fabric_fpga_rdata_axi_s2_i62, fabric_fpga_rdata_axi_s2_i63, fabric_fpga_rdata_axi_s2_i64, fabric_fpga_rdata_axi_s2_i65, fabric_fpga_rdata_axi_s2_i66, fabric_fpga_rdata_axi_s2_i67, fabric_fpga_rdata_axi_s2_i68 +, fabric_fpga_rdata_axi_s2_i69, fabric_fpga_rdata_axi_s2_i70, fabric_fpga_rdata_axi_s2_i71, fabric_fpga_rdata_axi_s2_i72, fabric_fpga_rdata_axi_s2_i73, fabric_fpga_rdata_axi_s2_i74, fabric_fpga_rdata_axi_s2_i75, fabric_fpga_rdata_axi_s2_i76, fabric_fpga_rdata_axi_s2_i77, fabric_fpga_rdata_axi_s2_i78, fabric_fpga_rdata_axi_s2_i79, fabric_fpga_rdata_axi_s2_i80, fabric_fpga_rdata_axi_s2_i81, fabric_fpga_rdata_axi_s2_i82, fabric_fpga_rdata_axi_s2_i83, fabric_fpga_rdata_axi_s2_i84, fabric_fpga_rdata_axi_s2_i85, fabric_fpga_rdata_axi_s2_i86, fabric_fpga_rdata_axi_s2_i87, fabric_fpga_rdata_axi_s2_i88, fabric_fpga_rdata_axi_s2_i89 +, fabric_fpga_rdata_axi_s2_i90, fabric_fpga_rdata_axi_s2_i91, fabric_fpga_rdata_axi_s2_i92, fabric_fpga_rdata_axi_s2_i93, fabric_fpga_rdata_axi_s2_i94, fabric_fpga_rdata_axi_s2_i95, fabric_fpga_rdata_axi_s2_i96, fabric_fpga_rdata_axi_s2_i97, fabric_fpga_rdata_axi_s2_i98, fabric_fpga_rdata_axi_s2_i99, fabric_fpga_rdata_axi_s2_i100, fabric_fpga_rdata_axi_s2_i101, fabric_fpga_rdata_axi_s2_i102, fabric_fpga_rdata_axi_s2_i103, fabric_fpga_rdata_axi_s2_i104, fabric_fpga_rdata_axi_s2_i105, fabric_fpga_rdata_axi_s2_i106, fabric_fpga_rdata_axi_s2_i107, fabric_fpga_rdata_axi_s2_i108, fabric_fpga_rdata_axi_s2_i109, fabric_fpga_rdata_axi_s2_i110 +, fabric_fpga_rdata_axi_s2_i111, fabric_fpga_rdata_axi_s2_i112, fabric_fpga_rdata_axi_s2_i113, fabric_fpga_rdata_axi_s2_i114, fabric_fpga_rdata_axi_s2_i115, fabric_fpga_rdata_axi_s2_i116, fabric_fpga_rdata_axi_s2_i117, fabric_fpga_rdata_axi_s2_i118, fabric_fpga_rdata_axi_s2_i119, fabric_fpga_rdata_axi_s2_i120, fabric_fpga_rdata_axi_s2_i121, fabric_fpga_rdata_axi_s2_i122, fabric_fpga_rdata_axi_s2_i123, fabric_fpga_rdata_axi_s2_i124, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3 +, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bid_axi_m1_o1, fabric_fpga_bid_axi_m1_o2, fabric_fpga_bid_axi_m1_o3, fabric_fpga_bid_axi_m1_o4, fabric_fpga_bid_axi_m1_o5 +, fabric_fpga_bresp_axi_m1_o1, fabric_fpga_bresp_axi_m1_o2, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_dma_ack_m1_o1, fabric_fpga_dma_ack_m1_o2, fabric_fpga_dma_ack_m1_o3, fabric_fpga_dma_ack_m1_o4, fabric_fpga_dma_ack_m1_o5, fabric_fpga_dma_ack_m1_o6, fabric_fpga_dma_finish_m1_o1, fabric_fpga_dma_finish_m1_o2, fabric_fpga_dma_finish_m1_o3, fabric_fpga_dma_finish_m1_o4, fabric_fpga_dma_finish_m1_o5, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6 +, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27 +, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48 +, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69 +, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90 +, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111 +, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4 +, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15 +, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36 +, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6 +, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7 +, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28 +, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3 +, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3 +, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i +, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21 +, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42 +, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63 +, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84 +, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105 +, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126 +, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o +, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6 +, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21 +, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42 +, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63 +, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84 +, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105 +, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126 +, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9 +, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30 +, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5 +, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1 +, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22 +, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1 +, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1 +, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1 +, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15 +, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36 +, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57 +, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78 +, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99 +, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120 +, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12 +, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6 +, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27 +, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48 +, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69 +, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90 +, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111 +, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4 +, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15 +, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36 +, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6 +, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7 +, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28 +, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3 +, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3 +, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18 +, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39 +, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60 +, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81 +, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102 +, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123 +, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15 +, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19 +, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6 +, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27 +, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15 +, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2 +, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23 +, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6 +, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3 +, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16 +, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3 +, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8 +, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7 +, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28 +, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9 +, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15 +, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4 +, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8 +, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29 +, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12 +, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s1_o1, fabric_llpp1_arqos_s1_o2, fabric_llpp1_arqos_s1_o3, fabric_llpp1_arqos_s1_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1 +, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22 +, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5 +, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2 +, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13 +, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1 +, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i +, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21 +, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10 +, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14 +, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1 +, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6 +, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7 +, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28 +, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11 +, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o +, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19 +, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i +, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6 +, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27 +, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i +, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20 +, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3 +, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3 +, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13 +, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2 +, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5 +, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4 +, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25 +, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6 +, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12 +, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1 +, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5 +, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26 +, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12 +, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i +, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21 +, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5 +, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26 +, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13 +, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o +, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19 +, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6 +, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27 +, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10 +, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31 +, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52 +, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73 +, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94 +, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115 +, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o +, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19 +, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8 +, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29 +, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50 +, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7 +, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28 +, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10 +, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31 +, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52 +, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73 +, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94 +, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115 +, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i +, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21 +, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o +, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i +, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3); + input fabric_enable_TMR_i1; + input fabric_enable_TMR_i2; + input fabric_enable_TMR_i3; + input fabric_erom_fpga_cpu0_dbgen_i; + input fabric_erom_fpga_cpu0_hiden_i; + input fabric_erom_fpga_cpu0_hniden_i; + input fabric_erom_fpga_cpu0_niden_i; + input fabric_erom_fpga_cpu1_dbgen_i; + input fabric_erom_fpga_cpu1_hiden_i; + input fabric_erom_fpga_cpu1_hniden_i; + input fabric_erom_fpga_cpu1_niden_i; + input fabric_erom_fpga_cpu2_dbgen_i; + input fabric_erom_fpga_cpu2_hiden_i; + input fabric_erom_fpga_cpu2_hniden_i; + input fabric_erom_fpga_cpu2_niden_i; + input fabric_erom_fpga_cpu3_dbgen_i; + input fabric_erom_fpga_cpu3_hiden_i; + input fabric_erom_fpga_cpu3_hniden_i; + input fabric_erom_fpga_cpu3_niden_i; + input fabric_erom_fpga_cs_dbgen_i; + input fabric_erom_fpga_cs_deviceen_i; + input fabric_erom_fpga_cs_niden_i; + input fabric_erom_fpga_cs_rst_n_i; + input fabric_erom_fpga_debug_en_i; + input fabric_fpga_araddr_axi_m1_i1; + input fabric_fpga_araddr_axi_m1_i10; + input fabric_fpga_araddr_axi_m1_i11; + input fabric_fpga_araddr_axi_m1_i12; + input fabric_fpga_araddr_axi_m1_i13; + input fabric_fpga_araddr_axi_m1_i14; + input fabric_fpga_araddr_axi_m1_i15; + input fabric_fpga_araddr_axi_m1_i16; + input fabric_fpga_araddr_axi_m1_i17; + input fabric_fpga_araddr_axi_m1_i18; + input fabric_fpga_araddr_axi_m1_i19; + input fabric_fpga_araddr_axi_m1_i2; + input fabric_fpga_araddr_axi_m1_i20; + input fabric_fpga_araddr_axi_m1_i21; + input fabric_fpga_araddr_axi_m1_i22; + input fabric_fpga_araddr_axi_m1_i23; + input fabric_fpga_araddr_axi_m1_i24; + input fabric_fpga_araddr_axi_m1_i25; + input fabric_fpga_araddr_axi_m1_i26; + input fabric_fpga_araddr_axi_m1_i27; + input fabric_fpga_araddr_axi_m1_i28; + input fabric_fpga_araddr_axi_m1_i29; + input fabric_fpga_araddr_axi_m1_i3; + input fabric_fpga_araddr_axi_m1_i30; + input fabric_fpga_araddr_axi_m1_i31; + input fabric_fpga_araddr_axi_m1_i32; + input fabric_fpga_araddr_axi_m1_i33; + input fabric_fpga_araddr_axi_m1_i34; + input fabric_fpga_araddr_axi_m1_i35; + input fabric_fpga_araddr_axi_m1_i36; + input fabric_fpga_araddr_axi_m1_i37; + input fabric_fpga_araddr_axi_m1_i38; + input fabric_fpga_araddr_axi_m1_i39; + input fabric_fpga_araddr_axi_m1_i4; + input fabric_fpga_araddr_axi_m1_i40; + input fabric_fpga_araddr_axi_m1_i5; + input fabric_fpga_araddr_axi_m1_i6; + input fabric_fpga_araddr_axi_m1_i7; + input fabric_fpga_araddr_axi_m1_i8; + input fabric_fpga_araddr_axi_m1_i9; + input fabric_fpga_araddr_axi_m2_i1; + input fabric_fpga_araddr_axi_m2_i10; + input fabric_fpga_araddr_axi_m2_i11; + input fabric_fpga_araddr_axi_m2_i12; + input fabric_fpga_araddr_axi_m2_i13; + input fabric_fpga_araddr_axi_m2_i14; + input fabric_fpga_araddr_axi_m2_i15; + input fabric_fpga_araddr_axi_m2_i16; + input fabric_fpga_araddr_axi_m2_i17; + input fabric_fpga_araddr_axi_m2_i18; + input fabric_fpga_araddr_axi_m2_i19; + input fabric_fpga_araddr_axi_m2_i2; + input fabric_fpga_araddr_axi_m2_i20; + input fabric_fpga_araddr_axi_m2_i21; + input fabric_fpga_araddr_axi_m2_i22; + input fabric_fpga_araddr_axi_m2_i23; + input fabric_fpga_araddr_axi_m2_i24; + input fabric_fpga_araddr_axi_m2_i25; + input fabric_fpga_araddr_axi_m2_i26; + input fabric_fpga_araddr_axi_m2_i27; + input fabric_fpga_araddr_axi_m2_i28; + input fabric_fpga_araddr_axi_m2_i29; + input fabric_fpga_araddr_axi_m2_i3; + input fabric_fpga_araddr_axi_m2_i30; + input fabric_fpga_araddr_axi_m2_i31; + input fabric_fpga_araddr_axi_m2_i32; + input fabric_fpga_araddr_axi_m2_i33; + input fabric_fpga_araddr_axi_m2_i34; + input fabric_fpga_araddr_axi_m2_i35; + input fabric_fpga_araddr_axi_m2_i36; + input fabric_fpga_araddr_axi_m2_i37; + input fabric_fpga_araddr_axi_m2_i38; + input fabric_fpga_araddr_axi_m2_i39; + input fabric_fpga_araddr_axi_m2_i4; + input fabric_fpga_araddr_axi_m2_i40; + input fabric_fpga_araddr_axi_m2_i5; + input fabric_fpga_araddr_axi_m2_i6; + input fabric_fpga_araddr_axi_m2_i7; + input fabric_fpga_araddr_axi_m2_i8; + input fabric_fpga_araddr_axi_m2_i9; + output fabric_fpga_araddr_axi_s1_o1; + output fabric_fpga_araddr_axi_s1_o10; + output fabric_fpga_araddr_axi_s1_o11; + output fabric_fpga_araddr_axi_s1_o12; + output fabric_fpga_araddr_axi_s1_o13; + output fabric_fpga_araddr_axi_s1_o14; + output fabric_fpga_araddr_axi_s1_o15; + output fabric_fpga_araddr_axi_s1_o16; + output fabric_fpga_araddr_axi_s1_o17; + output fabric_fpga_araddr_axi_s1_o18; + output fabric_fpga_araddr_axi_s1_o19; + output fabric_fpga_araddr_axi_s1_o2; + output fabric_fpga_araddr_axi_s1_o20; + output fabric_fpga_araddr_axi_s1_o21; + output fabric_fpga_araddr_axi_s1_o22; + output fabric_fpga_araddr_axi_s1_o23; + output fabric_fpga_araddr_axi_s1_o24; + output fabric_fpga_araddr_axi_s1_o25; + output fabric_fpga_araddr_axi_s1_o26; + output fabric_fpga_araddr_axi_s1_o27; + output fabric_fpga_araddr_axi_s1_o28; + output fabric_fpga_araddr_axi_s1_o29; + output fabric_fpga_araddr_axi_s1_o3; + output fabric_fpga_araddr_axi_s1_o30; + output fabric_fpga_araddr_axi_s1_o31; + output fabric_fpga_araddr_axi_s1_o32; + output fabric_fpga_araddr_axi_s1_o33; + output fabric_fpga_araddr_axi_s1_o34; + output fabric_fpga_araddr_axi_s1_o35; + output fabric_fpga_araddr_axi_s1_o36; + output fabric_fpga_araddr_axi_s1_o37; + output fabric_fpga_araddr_axi_s1_o38; + output fabric_fpga_araddr_axi_s1_o39; + output fabric_fpga_araddr_axi_s1_o4; + output fabric_fpga_araddr_axi_s1_o40; + output fabric_fpga_araddr_axi_s1_o5; + output fabric_fpga_araddr_axi_s1_o6; + output fabric_fpga_araddr_axi_s1_o7; + output fabric_fpga_araddr_axi_s1_o8; + output fabric_fpga_araddr_axi_s1_o9; + output fabric_fpga_araddr_axi_s2_o1; + output fabric_fpga_araddr_axi_s2_o10; + output fabric_fpga_araddr_axi_s2_o11; + output fabric_fpga_araddr_axi_s2_o12; + output fabric_fpga_araddr_axi_s2_o13; + output fabric_fpga_araddr_axi_s2_o14; + output fabric_fpga_araddr_axi_s2_o15; + output fabric_fpga_araddr_axi_s2_o16; + output fabric_fpga_araddr_axi_s2_o17; + output fabric_fpga_araddr_axi_s2_o18; + output fabric_fpga_araddr_axi_s2_o19; + output fabric_fpga_araddr_axi_s2_o2; + output fabric_fpga_araddr_axi_s2_o20; + output fabric_fpga_araddr_axi_s2_o21; + output fabric_fpga_araddr_axi_s2_o22; + output fabric_fpga_araddr_axi_s2_o23; + output fabric_fpga_araddr_axi_s2_o24; + output fabric_fpga_araddr_axi_s2_o25; + output fabric_fpga_araddr_axi_s2_o26; + output fabric_fpga_araddr_axi_s2_o27; + output fabric_fpga_araddr_axi_s2_o28; + output fabric_fpga_araddr_axi_s2_o29; + output fabric_fpga_araddr_axi_s2_o3; + output fabric_fpga_araddr_axi_s2_o30; + output fabric_fpga_araddr_axi_s2_o31; + output fabric_fpga_araddr_axi_s2_o32; + output fabric_fpga_araddr_axi_s2_o33; + output fabric_fpga_araddr_axi_s2_o34; + output fabric_fpga_araddr_axi_s2_o35; + output fabric_fpga_araddr_axi_s2_o36; + output fabric_fpga_araddr_axi_s2_o37; + output fabric_fpga_araddr_axi_s2_o38; + output fabric_fpga_araddr_axi_s2_o39; + output fabric_fpga_araddr_axi_s2_o4; + output fabric_fpga_araddr_axi_s2_o40; + output fabric_fpga_araddr_axi_s2_o5; + output fabric_fpga_araddr_axi_s2_o6; + output fabric_fpga_araddr_axi_s2_o7; + output fabric_fpga_araddr_axi_s2_o8; + output fabric_fpga_araddr_axi_s2_o9; + input fabric_fpga_arburst_axi_m1_i1; + input fabric_fpga_arburst_axi_m1_i2; + input fabric_fpga_arburst_axi_m2_i1; + input fabric_fpga_arburst_axi_m2_i2; + output fabric_fpga_arburst_axi_s1_o1; + output fabric_fpga_arburst_axi_s1_o2; + output fabric_fpga_arburst_axi_s2_o1; + output fabric_fpga_arburst_axi_s2_o2; + input fabric_fpga_arcache_axi_m1_i1; + input fabric_fpga_arcache_axi_m1_i2; + input fabric_fpga_arcache_axi_m1_i3; + input fabric_fpga_arcache_axi_m1_i4; + input fabric_fpga_arcache_axi_m2_i1; + input fabric_fpga_arcache_axi_m2_i2; + input fabric_fpga_arcache_axi_m2_i3; + input fabric_fpga_arcache_axi_m2_i4; + output fabric_fpga_arcache_axi_s1_o1; + output fabric_fpga_arcache_axi_s1_o2; + output fabric_fpga_arcache_axi_s1_o3; + output fabric_fpga_arcache_axi_s1_o4; + output fabric_fpga_arcache_axi_s2_o1; + output fabric_fpga_arcache_axi_s2_o2; + output fabric_fpga_arcache_axi_s2_o3; + output fabric_fpga_arcache_axi_s2_o4; + input fabric_fpga_arid_axi_m1_i1; + input fabric_fpga_arid_axi_m1_i2; + input fabric_fpga_arid_axi_m1_i3; + input fabric_fpga_arid_axi_m1_i4; + input fabric_fpga_arid_axi_m1_i5; + input fabric_fpga_arid_axi_m2_i1; + input fabric_fpga_arid_axi_m2_i2; + input fabric_fpga_arid_axi_m2_i3; + input fabric_fpga_arid_axi_m2_i4; + input fabric_fpga_arid_axi_m2_i5; + output fabric_fpga_arid_axi_s1_o1; + output fabric_fpga_arid_axi_s1_o10; + output fabric_fpga_arid_axi_s1_o11; + output fabric_fpga_arid_axi_s1_o12; + output fabric_fpga_arid_axi_s1_o2; + output fabric_fpga_arid_axi_s1_o3; + output fabric_fpga_arid_axi_s1_o4; + output fabric_fpga_arid_axi_s1_o5; + output fabric_fpga_arid_axi_s1_o6; + output fabric_fpga_arid_axi_s1_o7; + output fabric_fpga_arid_axi_s1_o8; + output fabric_fpga_arid_axi_s1_o9; + output fabric_fpga_arid_axi_s2_o1; + output fabric_fpga_arid_axi_s2_o10; + output fabric_fpga_arid_axi_s2_o11; + output fabric_fpga_arid_axi_s2_o12; + output fabric_fpga_arid_axi_s2_o2; + output fabric_fpga_arid_axi_s2_o3; + output fabric_fpga_arid_axi_s2_o4; + output fabric_fpga_arid_axi_s2_o5; + output fabric_fpga_arid_axi_s2_o6; + output fabric_fpga_arid_axi_s2_o7; + output fabric_fpga_arid_axi_s2_o8; + output fabric_fpga_arid_axi_s2_o9; + input fabric_fpga_arlen_axi_m1_i1; + input fabric_fpga_arlen_axi_m1_i2; + input fabric_fpga_arlen_axi_m1_i3; + input fabric_fpga_arlen_axi_m1_i4; + input fabric_fpga_arlen_axi_m1_i5; + input fabric_fpga_arlen_axi_m1_i6; + input fabric_fpga_arlen_axi_m1_i7; + input fabric_fpga_arlen_axi_m1_i8; + input fabric_fpga_arlen_axi_m2_i1; + input fabric_fpga_arlen_axi_m2_i2; + input fabric_fpga_arlen_axi_m2_i3; + input fabric_fpga_arlen_axi_m2_i4; + input fabric_fpga_arlen_axi_m2_i5; + input fabric_fpga_arlen_axi_m2_i6; + input fabric_fpga_arlen_axi_m2_i7; + input fabric_fpga_arlen_axi_m2_i8; + output fabric_fpga_arlen_axi_s1_o1; + output fabric_fpga_arlen_axi_s1_o2; + output fabric_fpga_arlen_axi_s1_o3; + output fabric_fpga_arlen_axi_s1_o4; + output fabric_fpga_arlen_axi_s1_o5; + output fabric_fpga_arlen_axi_s1_o6; + output fabric_fpga_arlen_axi_s1_o7; + output fabric_fpga_arlen_axi_s1_o8; + output fabric_fpga_arlen_axi_s2_o1; + output fabric_fpga_arlen_axi_s2_o2; + output fabric_fpga_arlen_axi_s2_o3; + output fabric_fpga_arlen_axi_s2_o4; + output fabric_fpga_arlen_axi_s2_o5; + output fabric_fpga_arlen_axi_s2_o6; + output fabric_fpga_arlen_axi_s2_o7; + output fabric_fpga_arlen_axi_s2_o8; + input fabric_fpga_arlock_axi_m1_i; + input fabric_fpga_arlock_axi_m2_i; + output fabric_fpga_arlock_axi_s1_o; + output fabric_fpga_arlock_axi_s2_o; + input fabric_fpga_arprot_axi_m1_i1; + input fabric_fpga_arprot_axi_m1_i2; + input fabric_fpga_arprot_axi_m1_i3; + input fabric_fpga_arprot_axi_m2_i1; + input fabric_fpga_arprot_axi_m2_i2; + input fabric_fpga_arprot_axi_m2_i3; + output fabric_fpga_arprot_axi_s1_o1; + output fabric_fpga_arprot_axi_s1_o2; + output fabric_fpga_arprot_axi_s1_o3; + output fabric_fpga_arprot_axi_s2_o1; + output fabric_fpga_arprot_axi_s2_o2; + output fabric_fpga_arprot_axi_s2_o3; + input fabric_fpga_arqos_axi_m1_i1; + input fabric_fpga_arqos_axi_m1_i2; + input fabric_fpga_arqos_axi_m1_i3; + input fabric_fpga_arqos_axi_m1_i4; + input fabric_fpga_arqos_axi_m2_i1; + input fabric_fpga_arqos_axi_m2_i2; + input fabric_fpga_arqos_axi_m2_i3; + input fabric_fpga_arqos_axi_m2_i4; + output fabric_fpga_arqos_axi_s1_o1; + output fabric_fpga_arqos_axi_s1_o2; + output fabric_fpga_arqos_axi_s1_o3; + output fabric_fpga_arqos_axi_s1_o4; + output fabric_fpga_arqos_axi_s2_o1; + output fabric_fpga_arqos_axi_s2_o2; + output fabric_fpga_arqos_axi_s2_o3; + output fabric_fpga_arqos_axi_s2_o4; + output fabric_fpga_arready_axi_m1_o; + output fabric_fpga_arready_axi_m2_o; + input fabric_fpga_arready_axi_s1_i; + input fabric_fpga_arready_axi_s2_i; + output fabric_fpga_arregion_axi_s1_o1; + output fabric_fpga_arregion_axi_s1_o2; + output fabric_fpga_arregion_axi_s1_o3; + output fabric_fpga_arregion_axi_s1_o4; + output fabric_fpga_arregion_axi_s2_o1; + output fabric_fpga_arregion_axi_s2_o2; + output fabric_fpga_arregion_axi_s2_o3; + output fabric_fpga_arregion_axi_s2_o4; + input fabric_fpga_arsize_axi_m1_i1; + input fabric_fpga_arsize_axi_m1_i2; + input fabric_fpga_arsize_axi_m1_i3; + input fabric_fpga_arsize_axi_m2_i1; + input fabric_fpga_arsize_axi_m2_i2; + input fabric_fpga_arsize_axi_m2_i3; + output fabric_fpga_arsize_axi_s1_o1; + output fabric_fpga_arsize_axi_s1_o2; + output fabric_fpga_arsize_axi_s1_o3; + output fabric_fpga_arsize_axi_s2_o1; + output fabric_fpga_arsize_axi_s2_o2; + output fabric_fpga_arsize_axi_s2_o3; + input fabric_fpga_arvalid_axi_m1_i; + input fabric_fpga_arvalid_axi_m2_i; + output fabric_fpga_arvalid_axi_s1_o; + output fabric_fpga_arvalid_axi_s2_o; + input fabric_fpga_awaddr_axi_m1_i1; + input fabric_fpga_awaddr_axi_m1_i10; + input fabric_fpga_awaddr_axi_m1_i11; + input fabric_fpga_awaddr_axi_m1_i12; + input fabric_fpga_awaddr_axi_m1_i13; + input fabric_fpga_awaddr_axi_m1_i14; + input fabric_fpga_awaddr_axi_m1_i15; + input fabric_fpga_awaddr_axi_m1_i16; + input fabric_fpga_awaddr_axi_m1_i17; + input fabric_fpga_awaddr_axi_m1_i18; + input fabric_fpga_awaddr_axi_m1_i19; + input fabric_fpga_awaddr_axi_m1_i2; + input fabric_fpga_awaddr_axi_m1_i20; + input fabric_fpga_awaddr_axi_m1_i21; + input fabric_fpga_awaddr_axi_m1_i22; + input fabric_fpga_awaddr_axi_m1_i23; + input fabric_fpga_awaddr_axi_m1_i24; + input fabric_fpga_awaddr_axi_m1_i25; + input fabric_fpga_awaddr_axi_m1_i26; + input fabric_fpga_awaddr_axi_m1_i27; + input fabric_fpga_awaddr_axi_m1_i28; + input fabric_fpga_awaddr_axi_m1_i29; + input fabric_fpga_awaddr_axi_m1_i3; + input fabric_fpga_awaddr_axi_m1_i30; + input fabric_fpga_awaddr_axi_m1_i31; + input fabric_fpga_awaddr_axi_m1_i32; + input fabric_fpga_awaddr_axi_m1_i33; + input fabric_fpga_awaddr_axi_m1_i34; + input fabric_fpga_awaddr_axi_m1_i35; + input fabric_fpga_awaddr_axi_m1_i36; + input fabric_fpga_awaddr_axi_m1_i37; + input fabric_fpga_awaddr_axi_m1_i38; + input fabric_fpga_awaddr_axi_m1_i39; + input fabric_fpga_awaddr_axi_m1_i4; + input fabric_fpga_awaddr_axi_m1_i40; + input fabric_fpga_awaddr_axi_m1_i5; + input fabric_fpga_awaddr_axi_m1_i6; + input fabric_fpga_awaddr_axi_m1_i7; + input fabric_fpga_awaddr_axi_m1_i8; + input fabric_fpga_awaddr_axi_m1_i9; + input fabric_fpga_awaddr_axi_m2_i1; + input fabric_fpga_awaddr_axi_m2_i10; + input fabric_fpga_awaddr_axi_m2_i11; + input fabric_fpga_awaddr_axi_m2_i12; + input fabric_fpga_awaddr_axi_m2_i13; + input fabric_fpga_awaddr_axi_m2_i14; + input fabric_fpga_awaddr_axi_m2_i15; + input fabric_fpga_awaddr_axi_m2_i16; + input fabric_fpga_awaddr_axi_m2_i17; + input fabric_fpga_awaddr_axi_m2_i18; + input fabric_fpga_awaddr_axi_m2_i19; + input fabric_fpga_awaddr_axi_m2_i2; + input fabric_fpga_awaddr_axi_m2_i20; + input fabric_fpga_awaddr_axi_m2_i21; + input fabric_fpga_awaddr_axi_m2_i22; + input fabric_fpga_awaddr_axi_m2_i23; + input fabric_fpga_awaddr_axi_m2_i24; + input fabric_fpga_awaddr_axi_m2_i25; + input fabric_fpga_awaddr_axi_m2_i26; + input fabric_fpga_awaddr_axi_m2_i27; + input fabric_fpga_awaddr_axi_m2_i28; + input fabric_fpga_awaddr_axi_m2_i29; + input fabric_fpga_awaddr_axi_m2_i3; + input fabric_fpga_awaddr_axi_m2_i30; + input fabric_fpga_awaddr_axi_m2_i31; + input fabric_fpga_awaddr_axi_m2_i32; + input fabric_fpga_awaddr_axi_m2_i33; + input fabric_fpga_awaddr_axi_m2_i34; + input fabric_fpga_awaddr_axi_m2_i35; + input fabric_fpga_awaddr_axi_m2_i36; + input fabric_fpga_awaddr_axi_m2_i37; + input fabric_fpga_awaddr_axi_m2_i38; + input fabric_fpga_awaddr_axi_m2_i39; + input fabric_fpga_awaddr_axi_m2_i4; + input fabric_fpga_awaddr_axi_m2_i40; + input fabric_fpga_awaddr_axi_m2_i5; + input fabric_fpga_awaddr_axi_m2_i6; + input fabric_fpga_awaddr_axi_m2_i7; + input fabric_fpga_awaddr_axi_m2_i8; + input fabric_fpga_awaddr_axi_m2_i9; + output fabric_fpga_awaddr_axi_s1_o1; + output fabric_fpga_awaddr_axi_s1_o10; + output fabric_fpga_awaddr_axi_s1_o11; + output fabric_fpga_awaddr_axi_s1_o12; + output fabric_fpga_awaddr_axi_s1_o13; + output fabric_fpga_awaddr_axi_s1_o14; + output fabric_fpga_awaddr_axi_s1_o15; + output fabric_fpga_awaddr_axi_s1_o16; + output fabric_fpga_awaddr_axi_s1_o17; + output fabric_fpga_awaddr_axi_s1_o18; + output fabric_fpga_awaddr_axi_s1_o19; + output fabric_fpga_awaddr_axi_s1_o2; + output fabric_fpga_awaddr_axi_s1_o20; + output fabric_fpga_awaddr_axi_s1_o21; + output fabric_fpga_awaddr_axi_s1_o22; + output fabric_fpga_awaddr_axi_s1_o23; + output fabric_fpga_awaddr_axi_s1_o24; + output fabric_fpga_awaddr_axi_s1_o25; + output fabric_fpga_awaddr_axi_s1_o26; + output fabric_fpga_awaddr_axi_s1_o27; + output fabric_fpga_awaddr_axi_s1_o28; + output fabric_fpga_awaddr_axi_s1_o29; + output fabric_fpga_awaddr_axi_s1_o3; + output fabric_fpga_awaddr_axi_s1_o30; + output fabric_fpga_awaddr_axi_s1_o31; + output fabric_fpga_awaddr_axi_s1_o32; + output fabric_fpga_awaddr_axi_s1_o33; + output fabric_fpga_awaddr_axi_s1_o34; + output fabric_fpga_awaddr_axi_s1_o35; + output fabric_fpga_awaddr_axi_s1_o36; + output fabric_fpga_awaddr_axi_s1_o37; + output fabric_fpga_awaddr_axi_s1_o38; + output fabric_fpga_awaddr_axi_s1_o39; + output fabric_fpga_awaddr_axi_s1_o4; + output fabric_fpga_awaddr_axi_s1_o40; + output fabric_fpga_awaddr_axi_s1_o5; + output fabric_fpga_awaddr_axi_s1_o6; + output fabric_fpga_awaddr_axi_s1_o7; + output fabric_fpga_awaddr_axi_s1_o8; + output fabric_fpga_awaddr_axi_s1_o9; + output fabric_fpga_awaddr_axi_s2_o1; + output fabric_fpga_awaddr_axi_s2_o10; + output fabric_fpga_awaddr_axi_s2_o11; + output fabric_fpga_awaddr_axi_s2_o12; + output fabric_fpga_awaddr_axi_s2_o13; + output fabric_fpga_awaddr_axi_s2_o14; + output fabric_fpga_awaddr_axi_s2_o15; + output fabric_fpga_awaddr_axi_s2_o16; + output fabric_fpga_awaddr_axi_s2_o17; + output fabric_fpga_awaddr_axi_s2_o18; + output fabric_fpga_awaddr_axi_s2_o19; + output fabric_fpga_awaddr_axi_s2_o2; + output fabric_fpga_awaddr_axi_s2_o20; + output fabric_fpga_awaddr_axi_s2_o21; + output fabric_fpga_awaddr_axi_s2_o22; + output fabric_fpga_awaddr_axi_s2_o23; + output fabric_fpga_awaddr_axi_s2_o24; + output fabric_fpga_awaddr_axi_s2_o25; + output fabric_fpga_awaddr_axi_s2_o26; + output fabric_fpga_awaddr_axi_s2_o27; + output fabric_fpga_awaddr_axi_s2_o28; + output fabric_fpga_awaddr_axi_s2_o29; + output fabric_fpga_awaddr_axi_s2_o3; + output fabric_fpga_awaddr_axi_s2_o30; + output fabric_fpga_awaddr_axi_s2_o31; + output fabric_fpga_awaddr_axi_s2_o32; + output fabric_fpga_awaddr_axi_s2_o33; + output fabric_fpga_awaddr_axi_s2_o34; + output fabric_fpga_awaddr_axi_s2_o35; + output fabric_fpga_awaddr_axi_s2_o36; + output fabric_fpga_awaddr_axi_s2_o37; + output fabric_fpga_awaddr_axi_s2_o38; + output fabric_fpga_awaddr_axi_s2_o39; + output fabric_fpga_awaddr_axi_s2_o4; + output fabric_fpga_awaddr_axi_s2_o40; + output fabric_fpga_awaddr_axi_s2_o5; + output fabric_fpga_awaddr_axi_s2_o6; + output fabric_fpga_awaddr_axi_s2_o7; + output fabric_fpga_awaddr_axi_s2_o8; + output fabric_fpga_awaddr_axi_s2_o9; + input fabric_fpga_awburst_axi_m1_i1; + input fabric_fpga_awburst_axi_m1_i2; + input fabric_fpga_awburst_axi_m2_i1; + input fabric_fpga_awburst_axi_m2_i2; + output fabric_fpga_awburst_axi_s1_o1; + output fabric_fpga_awburst_axi_s1_o2; + output fabric_fpga_awburst_axi_s2_o1; + output fabric_fpga_awburst_axi_s2_o2; + input fabric_fpga_awcache_axi_m1_i1; + input fabric_fpga_awcache_axi_m1_i2; + input fabric_fpga_awcache_axi_m1_i3; + input fabric_fpga_awcache_axi_m1_i4; + input fabric_fpga_awcache_axi_m2_i1; + input fabric_fpga_awcache_axi_m2_i2; + input fabric_fpga_awcache_axi_m2_i3; + input fabric_fpga_awcache_axi_m2_i4; + output fabric_fpga_awcache_axi_s1_o1; + output fabric_fpga_awcache_axi_s1_o2; + output fabric_fpga_awcache_axi_s1_o3; + output fabric_fpga_awcache_axi_s1_o4; + output fabric_fpga_awcache_axi_s2_o1; + output fabric_fpga_awcache_axi_s2_o2; + output fabric_fpga_awcache_axi_s2_o3; + output fabric_fpga_awcache_axi_s2_o4; + input fabric_fpga_awid_axi_m1_i1; + input fabric_fpga_awid_axi_m1_i2; + input fabric_fpga_awid_axi_m1_i3; + input fabric_fpga_awid_axi_m1_i4; + input fabric_fpga_awid_axi_m1_i5; + input fabric_fpga_awid_axi_m2_i1; + input fabric_fpga_awid_axi_m2_i2; + input fabric_fpga_awid_axi_m2_i3; + input fabric_fpga_awid_axi_m2_i4; + input fabric_fpga_awid_axi_m2_i5; + output fabric_fpga_awid_axi_s1_o1; + output fabric_fpga_awid_axi_s1_o10; + output fabric_fpga_awid_axi_s1_o11; + output fabric_fpga_awid_axi_s1_o12; + output fabric_fpga_awid_axi_s1_o2; + output fabric_fpga_awid_axi_s1_o3; + output fabric_fpga_awid_axi_s1_o4; + output fabric_fpga_awid_axi_s1_o5; + output fabric_fpga_awid_axi_s1_o6; + output fabric_fpga_awid_axi_s1_o7; + output fabric_fpga_awid_axi_s1_o8; + output fabric_fpga_awid_axi_s1_o9; + output fabric_fpga_awid_axi_s2_o1; + output fabric_fpga_awid_axi_s2_o10; + output fabric_fpga_awid_axi_s2_o11; + output fabric_fpga_awid_axi_s2_o12; + output fabric_fpga_awid_axi_s2_o2; + output fabric_fpga_awid_axi_s2_o3; + output fabric_fpga_awid_axi_s2_o4; + output fabric_fpga_awid_axi_s2_o5; + output fabric_fpga_awid_axi_s2_o6; + output fabric_fpga_awid_axi_s2_o7; + output fabric_fpga_awid_axi_s2_o8; + output fabric_fpga_awid_axi_s2_o9; + input fabric_fpga_awlen_axi_m1_i1; + input fabric_fpga_awlen_axi_m1_i2; + input fabric_fpga_awlen_axi_m1_i3; + input fabric_fpga_awlen_axi_m1_i4; + input fabric_fpga_awlen_axi_m1_i5; + input fabric_fpga_awlen_axi_m1_i6; + input fabric_fpga_awlen_axi_m1_i7; + input fabric_fpga_awlen_axi_m1_i8; + input fabric_fpga_awlen_axi_m2_i1; + input fabric_fpga_awlen_axi_m2_i2; + input fabric_fpga_awlen_axi_m2_i3; + input fabric_fpga_awlen_axi_m2_i4; + input fabric_fpga_awlen_axi_m2_i5; + input fabric_fpga_awlen_axi_m2_i6; + input fabric_fpga_awlen_axi_m2_i7; + input fabric_fpga_awlen_axi_m2_i8; + output fabric_fpga_awlen_axi_s1_o1; + output fabric_fpga_awlen_axi_s1_o2; + output fabric_fpga_awlen_axi_s1_o3; + output fabric_fpga_awlen_axi_s1_o4; + output fabric_fpga_awlen_axi_s1_o5; + output fabric_fpga_awlen_axi_s1_o6; + output fabric_fpga_awlen_axi_s1_o7; + output fabric_fpga_awlen_axi_s1_o8; + output fabric_fpga_awlen_axi_s2_o1; + output fabric_fpga_awlen_axi_s2_o2; + output fabric_fpga_awlen_axi_s2_o3; + output fabric_fpga_awlen_axi_s2_o4; + output fabric_fpga_awlen_axi_s2_o5; + output fabric_fpga_awlen_axi_s2_o6; + output fabric_fpga_awlen_axi_s2_o7; + output fabric_fpga_awlen_axi_s2_o8; + input fabric_fpga_awlock_axi_m1_i; + input fabric_fpga_awlock_axi_m2_i; + output fabric_fpga_awlock_axi_s1_o; + output fabric_fpga_awlock_axi_s2_o; + input fabric_fpga_awprot_axi_m1_i1; + input fabric_fpga_awprot_axi_m1_i2; + input fabric_fpga_awprot_axi_m1_i3; + input fabric_fpga_awprot_axi_m2_i1; + input fabric_fpga_awprot_axi_m2_i2; + input fabric_fpga_awprot_axi_m2_i3; + output fabric_fpga_awprot_axi_s1_o1; + output fabric_fpga_awprot_axi_s1_o2; + output fabric_fpga_awprot_axi_s1_o3; + output fabric_fpga_awprot_axi_s2_o1; + output fabric_fpga_awprot_axi_s2_o2; + output fabric_fpga_awprot_axi_s2_o3; + input fabric_fpga_awqos_axi_m1_i1; + input fabric_fpga_awqos_axi_m1_i2; + input fabric_fpga_awqos_axi_m1_i3; + input fabric_fpga_awqos_axi_m1_i4; + input fabric_fpga_awqos_axi_m2_i1; + input fabric_fpga_awqos_axi_m2_i2; + input fabric_fpga_awqos_axi_m2_i3; + input fabric_fpga_awqos_axi_m2_i4; + output fabric_fpga_awqos_axi_s1_o1; + output fabric_fpga_awqos_axi_s1_o2; + output fabric_fpga_awqos_axi_s1_o3; + output fabric_fpga_awqos_axi_s1_o4; + output fabric_fpga_awqos_axi_s2_o1; + output fabric_fpga_awqos_axi_s2_o2; + output fabric_fpga_awqos_axi_s2_o3; + output fabric_fpga_awqos_axi_s2_o4; + output fabric_fpga_awready_axi_m1_o; + output fabric_fpga_awready_axi_m2_o; + input fabric_fpga_awready_axi_s1_i; + input fabric_fpga_awready_axi_s2_i; + output fabric_fpga_awregion_axi_s1_o1; + output fabric_fpga_awregion_axi_s1_o2; + output fabric_fpga_awregion_axi_s1_o3; + output fabric_fpga_awregion_axi_s1_o4; + output fabric_fpga_awregion_axi_s2_o1; + output fabric_fpga_awregion_axi_s2_o2; + output fabric_fpga_awregion_axi_s2_o3; + output fabric_fpga_awregion_axi_s2_o4; + input fabric_fpga_awsize_axi_m1_i1; + input fabric_fpga_awsize_axi_m1_i2; + input fabric_fpga_awsize_axi_m1_i3; + input fabric_fpga_awsize_axi_m2_i1; + input fabric_fpga_awsize_axi_m2_i2; + input fabric_fpga_awsize_axi_m2_i3; + output fabric_fpga_awsize_axi_s1_o1; + output fabric_fpga_awsize_axi_s1_o2; + output fabric_fpga_awsize_axi_s1_o3; + output fabric_fpga_awsize_axi_s2_o1; + output fabric_fpga_awsize_axi_s2_o2; + output fabric_fpga_awsize_axi_s2_o3; + input fabric_fpga_awvalid_axi_m1_i; + input fabric_fpga_awvalid_axi_m2_i; + output fabric_fpga_awvalid_axi_s1_o; + output fabric_fpga_awvalid_axi_s2_o; + output fabric_fpga_bid_axi_m1_o1; + output fabric_fpga_bid_axi_m1_o2; + output fabric_fpga_bid_axi_m1_o3; + output fabric_fpga_bid_axi_m1_o4; + output fabric_fpga_bid_axi_m1_o5; + output fabric_fpga_bid_axi_m2_o1; + output fabric_fpga_bid_axi_m2_o2; + output fabric_fpga_bid_axi_m2_o3; + output fabric_fpga_bid_axi_m2_o4; + output fabric_fpga_bid_axi_m2_o5; + input fabric_fpga_bid_axi_s1_i1; + input fabric_fpga_bid_axi_s1_i10; + input fabric_fpga_bid_axi_s1_i11; + input fabric_fpga_bid_axi_s1_i12; + input fabric_fpga_bid_axi_s1_i2; + input fabric_fpga_bid_axi_s1_i3; + input fabric_fpga_bid_axi_s1_i4; + input fabric_fpga_bid_axi_s1_i5; + input fabric_fpga_bid_axi_s1_i6; + input fabric_fpga_bid_axi_s1_i7; + input fabric_fpga_bid_axi_s1_i8; + input fabric_fpga_bid_axi_s1_i9; + input fabric_fpga_bid_axi_s2_i1; + input fabric_fpga_bid_axi_s2_i10; + input fabric_fpga_bid_axi_s2_i11; + input fabric_fpga_bid_axi_s2_i12; + input fabric_fpga_bid_axi_s2_i2; + input fabric_fpga_bid_axi_s2_i3; + input fabric_fpga_bid_axi_s2_i4; + input fabric_fpga_bid_axi_s2_i5; + input fabric_fpga_bid_axi_s2_i6; + input fabric_fpga_bid_axi_s2_i7; + input fabric_fpga_bid_axi_s2_i8; + input fabric_fpga_bid_axi_s2_i9; + input fabric_fpga_bready_axi_m1_i; + input fabric_fpga_bready_axi_m2_i; + output fabric_fpga_bready_axi_s1_o; + output fabric_fpga_bready_axi_s2_o; + output fabric_fpga_bresp_axi_m1_o1; + output fabric_fpga_bresp_axi_m1_o2; + output fabric_fpga_bresp_axi_m2_o1; + output fabric_fpga_bresp_axi_m2_o2; + input fabric_fpga_bresp_axi_s1_i1; + input fabric_fpga_bresp_axi_s1_i2; + input fabric_fpga_bresp_axi_s2_i1; + input fabric_fpga_bresp_axi_s2_i2; + output fabric_fpga_bvalid_axi_m1_o; + output fabric_fpga_bvalid_axi_m2_o; + input fabric_fpga_bvalid_axi_s1_i; + input fabric_fpga_bvalid_axi_s2_i; + input fabric_fpga_ddr0_araddr_i1; + input fabric_fpga_ddr0_araddr_i10; + input fabric_fpga_ddr0_araddr_i11; + input fabric_fpga_ddr0_araddr_i12; + input fabric_fpga_ddr0_araddr_i13; + input fabric_fpga_ddr0_araddr_i14; + input fabric_fpga_ddr0_araddr_i15; + input fabric_fpga_ddr0_araddr_i16; + input fabric_fpga_ddr0_araddr_i17; + input fabric_fpga_ddr0_araddr_i18; + input fabric_fpga_ddr0_araddr_i19; + input fabric_fpga_ddr0_araddr_i2; + input fabric_fpga_ddr0_araddr_i20; + input fabric_fpga_ddr0_araddr_i21; + input fabric_fpga_ddr0_araddr_i22; + input fabric_fpga_ddr0_araddr_i23; + input fabric_fpga_ddr0_araddr_i24; + input fabric_fpga_ddr0_araddr_i25; + input fabric_fpga_ddr0_araddr_i26; + input fabric_fpga_ddr0_araddr_i27; + input fabric_fpga_ddr0_araddr_i28; + input fabric_fpga_ddr0_araddr_i29; + input fabric_fpga_ddr0_araddr_i3; + input fabric_fpga_ddr0_araddr_i30; + input fabric_fpga_ddr0_araddr_i31; + input fabric_fpga_ddr0_araddr_i32; + input fabric_fpga_ddr0_araddr_i33; + input fabric_fpga_ddr0_araddr_i34; + input fabric_fpga_ddr0_araddr_i35; + input fabric_fpga_ddr0_araddr_i36; + input fabric_fpga_ddr0_araddr_i37; + input fabric_fpga_ddr0_araddr_i38; + input fabric_fpga_ddr0_araddr_i39; + input fabric_fpga_ddr0_araddr_i4; + input fabric_fpga_ddr0_araddr_i40; + input fabric_fpga_ddr0_araddr_i5; + input fabric_fpga_ddr0_araddr_i6; + input fabric_fpga_ddr0_araddr_i7; + input fabric_fpga_ddr0_araddr_i8; + input fabric_fpga_ddr0_araddr_i9; + input fabric_fpga_ddr0_arburst_i1; + input fabric_fpga_ddr0_arburst_i2; + input fabric_fpga_ddr0_arcache_i1; + input fabric_fpga_ddr0_arcache_i2; + input fabric_fpga_ddr0_arcache_i3; + input fabric_fpga_ddr0_arcache_i4; + input fabric_fpga_ddr0_arid_i1; + input fabric_fpga_ddr0_arid_i2; + input fabric_fpga_ddr0_arid_i3; + input fabric_fpga_ddr0_arid_i4; + input fabric_fpga_ddr0_arid_i5; + input fabric_fpga_ddr0_arlen_i1; + input fabric_fpga_ddr0_arlen_i2; + input fabric_fpga_ddr0_arlen_i3; + input fabric_fpga_ddr0_arlen_i4; + input fabric_fpga_ddr0_arlen_i5; + input fabric_fpga_ddr0_arlen_i6; + input fabric_fpga_ddr0_arlen_i7; + input fabric_fpga_ddr0_arlen_i8; + input fabric_fpga_ddr0_arlock_i; + input fabric_fpga_ddr0_arprot_i1; + input fabric_fpga_ddr0_arprot_i2; + input fabric_fpga_ddr0_arprot_i3; + input fabric_fpga_ddr0_arqos_i1; + input fabric_fpga_ddr0_arqos_i2; + input fabric_fpga_ddr0_arqos_i3; + input fabric_fpga_ddr0_arqos_i4; + output fabric_fpga_ddr0_arready_o; + input fabric_fpga_ddr0_arsize_i1; + input fabric_fpga_ddr0_arsize_i2; + input fabric_fpga_ddr0_arsize_i3; + input fabric_fpga_ddr0_arvalid_i; + input fabric_fpga_ddr0_awaddr_i1; + input fabric_fpga_ddr0_awaddr_i10; + input fabric_fpga_ddr0_awaddr_i11; + input fabric_fpga_ddr0_awaddr_i12; + input fabric_fpga_ddr0_awaddr_i13; + input fabric_fpga_ddr0_awaddr_i14; + input fabric_fpga_ddr0_awaddr_i15; + input fabric_fpga_ddr0_awaddr_i16; + input fabric_fpga_ddr0_awaddr_i17; + input fabric_fpga_ddr0_awaddr_i18; + input fabric_fpga_ddr0_awaddr_i19; + input fabric_fpga_ddr0_awaddr_i2; + input fabric_fpga_ddr0_awaddr_i20; + input fabric_fpga_ddr0_awaddr_i21; + input fabric_fpga_ddr0_awaddr_i22; + input fabric_fpga_ddr0_awaddr_i23; + input fabric_fpga_ddr0_awaddr_i24; + input fabric_fpga_ddr0_awaddr_i25; + input fabric_fpga_ddr0_awaddr_i26; + input fabric_fpga_ddr0_awaddr_i27; + input fabric_fpga_ddr0_awaddr_i28; + input fabric_fpga_ddr0_awaddr_i29; + input fabric_fpga_ddr0_awaddr_i3; + input fabric_fpga_ddr0_awaddr_i30; + input fabric_fpga_ddr0_awaddr_i31; + input fabric_fpga_ddr0_awaddr_i32; + input fabric_fpga_ddr0_awaddr_i33; + input fabric_fpga_ddr0_awaddr_i34; + input fabric_fpga_ddr0_awaddr_i35; + input fabric_fpga_ddr0_awaddr_i36; + input fabric_fpga_ddr0_awaddr_i37; + input fabric_fpga_ddr0_awaddr_i38; + input fabric_fpga_ddr0_awaddr_i39; + input fabric_fpga_ddr0_awaddr_i4; + input fabric_fpga_ddr0_awaddr_i40; + input fabric_fpga_ddr0_awaddr_i5; + input fabric_fpga_ddr0_awaddr_i6; + input fabric_fpga_ddr0_awaddr_i7; + input fabric_fpga_ddr0_awaddr_i8; + input fabric_fpga_ddr0_awaddr_i9; + input fabric_fpga_ddr0_awburst_i1; + input fabric_fpga_ddr0_awburst_i2; + input fabric_fpga_ddr0_awcache_i1; + input fabric_fpga_ddr0_awcache_i2; + input fabric_fpga_ddr0_awcache_i3; + input fabric_fpga_ddr0_awcache_i4; + input fabric_fpga_ddr0_awid_i1; + input fabric_fpga_ddr0_awid_i2; + input fabric_fpga_ddr0_awid_i3; + input fabric_fpga_ddr0_awid_i4; + input fabric_fpga_ddr0_awid_i5; + input fabric_fpga_ddr0_awlen_i1; + input fabric_fpga_ddr0_awlen_i2; + input fabric_fpga_ddr0_awlen_i3; + input fabric_fpga_ddr0_awlen_i4; + input fabric_fpga_ddr0_awlen_i5; + input fabric_fpga_ddr0_awlen_i6; + input fabric_fpga_ddr0_awlen_i7; + input fabric_fpga_ddr0_awlen_i8; + input fabric_fpga_ddr0_awlock_i; + input fabric_fpga_ddr0_awprot_i1; + input fabric_fpga_ddr0_awprot_i2; + input fabric_fpga_ddr0_awprot_i3; + input fabric_fpga_ddr0_awqos_i1; + input fabric_fpga_ddr0_awqos_i2; + input fabric_fpga_ddr0_awqos_i3; + input fabric_fpga_ddr0_awqos_i4; + output fabric_fpga_ddr0_awready_o; + input fabric_fpga_ddr0_awsize_i1; + input fabric_fpga_ddr0_awsize_i2; + input fabric_fpga_ddr0_awsize_i3; + input fabric_fpga_ddr0_awvalid_i; + output fabric_fpga_ddr0_bid_o1; + output fabric_fpga_ddr0_bid_o2; + output fabric_fpga_ddr0_bid_o3; + output fabric_fpga_ddr0_bid_o4; + output fabric_fpga_ddr0_bid_o5; + input fabric_fpga_ddr0_bready_i; + output fabric_fpga_ddr0_bresp_o1; + output fabric_fpga_ddr0_bresp_o2; + output fabric_fpga_ddr0_bvalid_o; + output fabric_fpga_ddr0_rdata_o1; + output fabric_fpga_ddr0_rdata_o10; + output fabric_fpga_ddr0_rdata_o100; + output fabric_fpga_ddr0_rdata_o101; + output fabric_fpga_ddr0_rdata_o102; + output fabric_fpga_ddr0_rdata_o103; + output fabric_fpga_ddr0_rdata_o104; + output fabric_fpga_ddr0_rdata_o105; + output fabric_fpga_ddr0_rdata_o106; + output fabric_fpga_ddr0_rdata_o107; + output fabric_fpga_ddr0_rdata_o108; + output fabric_fpga_ddr0_rdata_o109; + output fabric_fpga_ddr0_rdata_o11; + output fabric_fpga_ddr0_rdata_o110; + output fabric_fpga_ddr0_rdata_o111; + output fabric_fpga_ddr0_rdata_o112; + output fabric_fpga_ddr0_rdata_o113; + output fabric_fpga_ddr0_rdata_o114; + output fabric_fpga_ddr0_rdata_o115; + output fabric_fpga_ddr0_rdata_o116; + output fabric_fpga_ddr0_rdata_o117; + output fabric_fpga_ddr0_rdata_o118; + output fabric_fpga_ddr0_rdata_o119; + output fabric_fpga_ddr0_rdata_o12; + output fabric_fpga_ddr0_rdata_o120; + output fabric_fpga_ddr0_rdata_o121; + output fabric_fpga_ddr0_rdata_o122; + output fabric_fpga_ddr0_rdata_o123; + output fabric_fpga_ddr0_rdata_o124; + output fabric_fpga_ddr0_rdata_o125; + output fabric_fpga_ddr0_rdata_o126; + output fabric_fpga_ddr0_rdata_o127; + output fabric_fpga_ddr0_rdata_o128; + output fabric_fpga_ddr0_rdata_o13; + output fabric_fpga_ddr0_rdata_o14; + output fabric_fpga_ddr0_rdata_o15; + output fabric_fpga_ddr0_rdata_o16; + output fabric_fpga_ddr0_rdata_o17; + output fabric_fpga_ddr0_rdata_o18; + output fabric_fpga_ddr0_rdata_o19; + output fabric_fpga_ddr0_rdata_o2; + output fabric_fpga_ddr0_rdata_o20; + output fabric_fpga_ddr0_rdata_o21; + output fabric_fpga_ddr0_rdata_o22; + output fabric_fpga_ddr0_rdata_o23; + output fabric_fpga_ddr0_rdata_o24; + output fabric_fpga_ddr0_rdata_o25; + output fabric_fpga_ddr0_rdata_o26; + output fabric_fpga_ddr0_rdata_o27; + output fabric_fpga_ddr0_rdata_o28; + output fabric_fpga_ddr0_rdata_o29; + output fabric_fpga_ddr0_rdata_o3; + output fabric_fpga_ddr0_rdata_o30; + output fabric_fpga_ddr0_rdata_o31; + output fabric_fpga_ddr0_rdata_o32; + output fabric_fpga_ddr0_rdata_o33; + output fabric_fpga_ddr0_rdata_o34; + output fabric_fpga_ddr0_rdata_o35; + output fabric_fpga_ddr0_rdata_o36; + output fabric_fpga_ddr0_rdata_o37; + output fabric_fpga_ddr0_rdata_o38; + output fabric_fpga_ddr0_rdata_o39; + output fabric_fpga_ddr0_rdata_o4; + output fabric_fpga_ddr0_rdata_o40; + output fabric_fpga_ddr0_rdata_o41; + output fabric_fpga_ddr0_rdata_o42; + output fabric_fpga_ddr0_rdata_o43; + output fabric_fpga_ddr0_rdata_o44; + output fabric_fpga_ddr0_rdata_o45; + output fabric_fpga_ddr0_rdata_o46; + output fabric_fpga_ddr0_rdata_o47; + output fabric_fpga_ddr0_rdata_o48; + output fabric_fpga_ddr0_rdata_o49; + output fabric_fpga_ddr0_rdata_o5; + output fabric_fpga_ddr0_rdata_o50; + output fabric_fpga_ddr0_rdata_o51; + output fabric_fpga_ddr0_rdata_o52; + output fabric_fpga_ddr0_rdata_o53; + output fabric_fpga_ddr0_rdata_o54; + output fabric_fpga_ddr0_rdata_o55; + output fabric_fpga_ddr0_rdata_o56; + output fabric_fpga_ddr0_rdata_o57; + output fabric_fpga_ddr0_rdata_o58; + output fabric_fpga_ddr0_rdata_o59; + output fabric_fpga_ddr0_rdata_o6; + output fabric_fpga_ddr0_rdata_o60; + output fabric_fpga_ddr0_rdata_o61; + output fabric_fpga_ddr0_rdata_o62; + output fabric_fpga_ddr0_rdata_o63; + output fabric_fpga_ddr0_rdata_o64; + output fabric_fpga_ddr0_rdata_o65; + output fabric_fpga_ddr0_rdata_o66; + output fabric_fpga_ddr0_rdata_o67; + output fabric_fpga_ddr0_rdata_o68; + output fabric_fpga_ddr0_rdata_o69; + output fabric_fpga_ddr0_rdata_o7; + output fabric_fpga_ddr0_rdata_o70; + output fabric_fpga_ddr0_rdata_o71; + output fabric_fpga_ddr0_rdata_o72; + output fabric_fpga_ddr0_rdata_o73; + output fabric_fpga_ddr0_rdata_o74; + output fabric_fpga_ddr0_rdata_o75; + output fabric_fpga_ddr0_rdata_o76; + output fabric_fpga_ddr0_rdata_o77; + output fabric_fpga_ddr0_rdata_o78; + output fabric_fpga_ddr0_rdata_o79; + output fabric_fpga_ddr0_rdata_o8; + output fabric_fpga_ddr0_rdata_o80; + output fabric_fpga_ddr0_rdata_o81; + output fabric_fpga_ddr0_rdata_o82; + output fabric_fpga_ddr0_rdata_o83; + output fabric_fpga_ddr0_rdata_o84; + output fabric_fpga_ddr0_rdata_o85; + output fabric_fpga_ddr0_rdata_o86; + output fabric_fpga_ddr0_rdata_o87; + output fabric_fpga_ddr0_rdata_o88; + output fabric_fpga_ddr0_rdata_o89; + output fabric_fpga_ddr0_rdata_o9; + output fabric_fpga_ddr0_rdata_o90; + output fabric_fpga_ddr0_rdata_o91; + output fabric_fpga_ddr0_rdata_o92; + output fabric_fpga_ddr0_rdata_o93; + output fabric_fpga_ddr0_rdata_o94; + output fabric_fpga_ddr0_rdata_o95; + output fabric_fpga_ddr0_rdata_o96; + output fabric_fpga_ddr0_rdata_o97; + output fabric_fpga_ddr0_rdata_o98; + output fabric_fpga_ddr0_rdata_o99; + output fabric_fpga_ddr0_rid_o1; + output fabric_fpga_ddr0_rid_o2; + output fabric_fpga_ddr0_rid_o3; + output fabric_fpga_ddr0_rid_o4; + output fabric_fpga_ddr0_rid_o5; + output fabric_fpga_ddr0_rlast_o; + input fabric_fpga_ddr0_rready_i; + output fabric_fpga_ddr0_rresp_o1; + output fabric_fpga_ddr0_rresp_o2; + output fabric_fpga_ddr0_rvalid_o; + input fabric_fpga_ddr0_wdata_i1; + input fabric_fpga_ddr0_wdata_i10; + input fabric_fpga_ddr0_wdata_i100; + input fabric_fpga_ddr0_wdata_i101; + input fabric_fpga_ddr0_wdata_i102; + input fabric_fpga_ddr0_wdata_i103; + input fabric_fpga_ddr0_wdata_i104; + input fabric_fpga_ddr0_wdata_i105; + input fabric_fpga_ddr0_wdata_i106; + input fabric_fpga_ddr0_wdata_i107; + input fabric_fpga_ddr0_wdata_i108; + input fabric_fpga_ddr0_wdata_i109; + input fabric_fpga_ddr0_wdata_i11; + input fabric_fpga_ddr0_wdata_i110; + input fabric_fpga_ddr0_wdata_i111; + input fabric_fpga_ddr0_wdata_i112; + input fabric_fpga_ddr0_wdata_i113; + input fabric_fpga_ddr0_wdata_i114; + input fabric_fpga_ddr0_wdata_i115; + input fabric_fpga_ddr0_wdata_i116; + input fabric_fpga_ddr0_wdata_i117; + input fabric_fpga_ddr0_wdata_i118; + input fabric_fpga_ddr0_wdata_i119; + input fabric_fpga_ddr0_wdata_i12; + input fabric_fpga_ddr0_wdata_i120; + input fabric_fpga_ddr0_wdata_i121; + input fabric_fpga_ddr0_wdata_i122; + input fabric_fpga_ddr0_wdata_i123; + input fabric_fpga_ddr0_wdata_i124; + input fabric_fpga_ddr0_wdata_i125; + input fabric_fpga_ddr0_wdata_i126; + input fabric_fpga_ddr0_wdata_i127; + input fabric_fpga_ddr0_wdata_i128; + input fabric_fpga_ddr0_wdata_i13; + input fabric_fpga_ddr0_wdata_i14; + input fabric_fpga_ddr0_wdata_i15; + input fabric_fpga_ddr0_wdata_i16; + input fabric_fpga_ddr0_wdata_i17; + input fabric_fpga_ddr0_wdata_i18; + input fabric_fpga_ddr0_wdata_i19; + input fabric_fpga_ddr0_wdata_i2; + input fabric_fpga_ddr0_wdata_i20; + input fabric_fpga_ddr0_wdata_i21; + input fabric_fpga_ddr0_wdata_i22; + input fabric_fpga_ddr0_wdata_i23; + input fabric_fpga_ddr0_wdata_i24; + input fabric_fpga_ddr0_wdata_i25; + input fabric_fpga_ddr0_wdata_i26; + input fabric_fpga_ddr0_wdata_i27; + input fabric_fpga_ddr0_wdata_i28; + input fabric_fpga_ddr0_wdata_i29; + input fabric_fpga_ddr0_wdata_i3; + input fabric_fpga_ddr0_wdata_i30; + input fabric_fpga_ddr0_wdata_i31; + input fabric_fpga_ddr0_wdata_i32; + input fabric_fpga_ddr0_wdata_i33; + input fabric_fpga_ddr0_wdata_i34; + input fabric_fpga_ddr0_wdata_i35; + input fabric_fpga_ddr0_wdata_i36; + input fabric_fpga_ddr0_wdata_i37; + input fabric_fpga_ddr0_wdata_i38; + input fabric_fpga_ddr0_wdata_i39; + input fabric_fpga_ddr0_wdata_i4; + input fabric_fpga_ddr0_wdata_i40; + input fabric_fpga_ddr0_wdata_i41; + input fabric_fpga_ddr0_wdata_i42; + input fabric_fpga_ddr0_wdata_i43; + input fabric_fpga_ddr0_wdata_i44; + input fabric_fpga_ddr0_wdata_i45; + input fabric_fpga_ddr0_wdata_i46; + input fabric_fpga_ddr0_wdata_i47; + input fabric_fpga_ddr0_wdata_i48; + input fabric_fpga_ddr0_wdata_i49; + input fabric_fpga_ddr0_wdata_i5; + input fabric_fpga_ddr0_wdata_i50; + input fabric_fpga_ddr0_wdata_i51; + input fabric_fpga_ddr0_wdata_i52; + input fabric_fpga_ddr0_wdata_i53; + input fabric_fpga_ddr0_wdata_i54; + input fabric_fpga_ddr0_wdata_i55; + input fabric_fpga_ddr0_wdata_i56; + input fabric_fpga_ddr0_wdata_i57; + input fabric_fpga_ddr0_wdata_i58; + input fabric_fpga_ddr0_wdata_i59; + input fabric_fpga_ddr0_wdata_i6; + input fabric_fpga_ddr0_wdata_i60; + input fabric_fpga_ddr0_wdata_i61; + input fabric_fpga_ddr0_wdata_i62; + input fabric_fpga_ddr0_wdata_i63; + input fabric_fpga_ddr0_wdata_i64; + input fabric_fpga_ddr0_wdata_i65; + input fabric_fpga_ddr0_wdata_i66; + input fabric_fpga_ddr0_wdata_i67; + input fabric_fpga_ddr0_wdata_i68; + input fabric_fpga_ddr0_wdata_i69; + input fabric_fpga_ddr0_wdata_i7; + input fabric_fpga_ddr0_wdata_i70; + input fabric_fpga_ddr0_wdata_i71; + input fabric_fpga_ddr0_wdata_i72; + input fabric_fpga_ddr0_wdata_i73; + input fabric_fpga_ddr0_wdata_i74; + input fabric_fpga_ddr0_wdata_i75; + input fabric_fpga_ddr0_wdata_i76; + input fabric_fpga_ddr0_wdata_i77; + input fabric_fpga_ddr0_wdata_i78; + input fabric_fpga_ddr0_wdata_i79; + input fabric_fpga_ddr0_wdata_i8; + input fabric_fpga_ddr0_wdata_i80; + input fabric_fpga_ddr0_wdata_i81; + input fabric_fpga_ddr0_wdata_i82; + input fabric_fpga_ddr0_wdata_i83; + input fabric_fpga_ddr0_wdata_i84; + input fabric_fpga_ddr0_wdata_i85; + input fabric_fpga_ddr0_wdata_i86; + input fabric_fpga_ddr0_wdata_i87; + input fabric_fpga_ddr0_wdata_i88; + input fabric_fpga_ddr0_wdata_i89; + input fabric_fpga_ddr0_wdata_i9; + input fabric_fpga_ddr0_wdata_i90; + input fabric_fpga_ddr0_wdata_i91; + input fabric_fpga_ddr0_wdata_i92; + input fabric_fpga_ddr0_wdata_i93; + input fabric_fpga_ddr0_wdata_i94; + input fabric_fpga_ddr0_wdata_i95; + input fabric_fpga_ddr0_wdata_i96; + input fabric_fpga_ddr0_wdata_i97; + input fabric_fpga_ddr0_wdata_i98; + input fabric_fpga_ddr0_wdata_i99; + input fabric_fpga_ddr0_wlast_i; + output fabric_fpga_ddr0_wready_o; + input fabric_fpga_ddr0_wstrb_i1; + input fabric_fpga_ddr0_wstrb_i10; + input fabric_fpga_ddr0_wstrb_i11; + input fabric_fpga_ddr0_wstrb_i12; + input fabric_fpga_ddr0_wstrb_i13; + input fabric_fpga_ddr0_wstrb_i14; + input fabric_fpga_ddr0_wstrb_i15; + input fabric_fpga_ddr0_wstrb_i16; + input fabric_fpga_ddr0_wstrb_i2; + input fabric_fpga_ddr0_wstrb_i3; + input fabric_fpga_ddr0_wstrb_i4; + input fabric_fpga_ddr0_wstrb_i5; + input fabric_fpga_ddr0_wstrb_i6; + input fabric_fpga_ddr0_wstrb_i7; + input fabric_fpga_ddr0_wstrb_i8; + input fabric_fpga_ddr0_wstrb_i9; + input fabric_fpga_ddr0_wvalid_i; + output fabric_fpga_dma_ack_m1_o1; + output fabric_fpga_dma_ack_m1_o2; + output fabric_fpga_dma_ack_m1_o3; + output fabric_fpga_dma_ack_m1_o4; + output fabric_fpga_dma_ack_m1_o5; + output fabric_fpga_dma_ack_m1_o6; + output fabric_fpga_dma_ack_m2_o1; + output fabric_fpga_dma_ack_m2_o2; + output fabric_fpga_dma_ack_m2_o3; + output fabric_fpga_dma_ack_m2_o4; + output fabric_fpga_dma_ack_m2_o5; + output fabric_fpga_dma_ack_m2_o6; + output fabric_fpga_dma_finish_m1_o1; + output fabric_fpga_dma_finish_m1_o2; + output fabric_fpga_dma_finish_m1_o3; + output fabric_fpga_dma_finish_m1_o4; + output fabric_fpga_dma_finish_m1_o5; + output fabric_fpga_dma_finish_m1_o6; + output fabric_fpga_dma_finish_m2_o1; + output fabric_fpga_dma_finish_m2_o2; + output fabric_fpga_dma_finish_m2_o3; + output fabric_fpga_dma_finish_m2_o4; + output fabric_fpga_dma_finish_m2_o5; + output fabric_fpga_dma_finish_m2_o6; + input fabric_fpga_dma_last_m1_i1; + input fabric_fpga_dma_last_m1_i2; + input fabric_fpga_dma_last_m1_i3; + input fabric_fpga_dma_last_m1_i4; + input fabric_fpga_dma_last_m1_i5; + input fabric_fpga_dma_last_m1_i6; + input fabric_fpga_dma_last_m2_i1; + input fabric_fpga_dma_last_m2_i2; + input fabric_fpga_dma_last_m2_i3; + input fabric_fpga_dma_last_m2_i4; + input fabric_fpga_dma_last_m2_i5; + input fabric_fpga_dma_last_m2_i6; + input fabric_fpga_dma_req_m1_i1; + input fabric_fpga_dma_req_m1_i2; + input fabric_fpga_dma_req_m1_i3; + input fabric_fpga_dma_req_m1_i4; + input fabric_fpga_dma_req_m1_i5; + input fabric_fpga_dma_req_m1_i6; + input fabric_fpga_dma_req_m2_i1; + input fabric_fpga_dma_req_m2_i2; + input fabric_fpga_dma_req_m2_i3; + input fabric_fpga_dma_req_m2_i4; + input fabric_fpga_dma_req_m2_i5; + input fabric_fpga_dma_req_m2_i6; + input fabric_fpga_dma_single_m1_i1; + input fabric_fpga_dma_single_m1_i2; + input fabric_fpga_dma_single_m1_i3; + input fabric_fpga_dma_single_m1_i4; + input fabric_fpga_dma_single_m1_i5; + input fabric_fpga_dma_single_m1_i6; + input fabric_fpga_dma_single_m2_i1; + input fabric_fpga_dma_single_m2_i2; + input fabric_fpga_dma_single_m2_i3; + input fabric_fpga_dma_single_m2_i4; + input fabric_fpga_dma_single_m2_i5; + input fabric_fpga_dma_single_m2_i6; + input fabric_fpga_events60_i1; + input fabric_fpga_events60_i10; + input fabric_fpga_events60_i11; + input fabric_fpga_events60_i12; + input fabric_fpga_events60_i13; + input fabric_fpga_events60_i14; + input fabric_fpga_events60_i15; + input fabric_fpga_events60_i16; + input fabric_fpga_events60_i17; + input fabric_fpga_events60_i18; + input fabric_fpga_events60_i19; + input fabric_fpga_events60_i2; + input fabric_fpga_events60_i20; + input fabric_fpga_events60_i21; + input fabric_fpga_events60_i22; + input fabric_fpga_events60_i23; + input fabric_fpga_events60_i24; + input fabric_fpga_events60_i25; + input fabric_fpga_events60_i26; + input fabric_fpga_events60_i27; + input fabric_fpga_events60_i28; + input fabric_fpga_events60_i29; + input fabric_fpga_events60_i3; + input fabric_fpga_events60_i30; + input fabric_fpga_events60_i31; + input fabric_fpga_events60_i32; + input fabric_fpga_events60_i33; + input fabric_fpga_events60_i34; + input fabric_fpga_events60_i35; + input fabric_fpga_events60_i36; + input fabric_fpga_events60_i37; + input fabric_fpga_events60_i38; + input fabric_fpga_events60_i39; + input fabric_fpga_events60_i4; + input fabric_fpga_events60_i40; + input fabric_fpga_events60_i41; + input fabric_fpga_events60_i42; + input fabric_fpga_events60_i43; + input fabric_fpga_events60_i44; + input fabric_fpga_events60_i45; + input fabric_fpga_events60_i46; + input fabric_fpga_events60_i47; + input fabric_fpga_events60_i48; + input fabric_fpga_events60_i49; + input fabric_fpga_events60_i5; + input fabric_fpga_events60_i50; + input fabric_fpga_events60_i51; + input fabric_fpga_events60_i52; + input fabric_fpga_events60_i53; + input fabric_fpga_events60_i54; + input fabric_fpga_events60_i55; + input fabric_fpga_events60_i56; + input fabric_fpga_events60_i57; + input fabric_fpga_events60_i58; + input fabric_fpga_events60_i59; + input fabric_fpga_events60_i6; + input fabric_fpga_events60_i60; + input fabric_fpga_events60_i7; + input fabric_fpga_events60_i8; + input fabric_fpga_events60_i9; + input fabric_fpga_interrupt_in_i1; + input fabric_fpga_interrupt_in_i10; + input fabric_fpga_interrupt_in_i100; + input fabric_fpga_interrupt_in_i101; + input fabric_fpga_interrupt_in_i102; + input fabric_fpga_interrupt_in_i103; + input fabric_fpga_interrupt_in_i104; + input fabric_fpga_interrupt_in_i105; + input fabric_fpga_interrupt_in_i106; + input fabric_fpga_interrupt_in_i107; + input fabric_fpga_interrupt_in_i108; + input fabric_fpga_interrupt_in_i109; + input fabric_fpga_interrupt_in_i11; + input fabric_fpga_interrupt_in_i110; + input fabric_fpga_interrupt_in_i111; + input fabric_fpga_interrupt_in_i112; + input fabric_fpga_interrupt_in_i113; + input fabric_fpga_interrupt_in_i114; + input fabric_fpga_interrupt_in_i115; + input fabric_fpga_interrupt_in_i116; + input fabric_fpga_interrupt_in_i117; + input fabric_fpga_interrupt_in_i118; + input fabric_fpga_interrupt_in_i119; + input fabric_fpga_interrupt_in_i12; + input fabric_fpga_interrupt_in_i120; + input fabric_fpga_interrupt_in_i13; + input fabric_fpga_interrupt_in_i14; + input fabric_fpga_interrupt_in_i15; + input fabric_fpga_interrupt_in_i16; + input fabric_fpga_interrupt_in_i17; + input fabric_fpga_interrupt_in_i18; + input fabric_fpga_interrupt_in_i19; + input fabric_fpga_interrupt_in_i2; + input fabric_fpga_interrupt_in_i20; + input fabric_fpga_interrupt_in_i21; + input fabric_fpga_interrupt_in_i22; + input fabric_fpga_interrupt_in_i23; + input fabric_fpga_interrupt_in_i24; + input fabric_fpga_interrupt_in_i25; + input fabric_fpga_interrupt_in_i26; + input fabric_fpga_interrupt_in_i27; + input fabric_fpga_interrupt_in_i28; + input fabric_fpga_interrupt_in_i29; + input fabric_fpga_interrupt_in_i3; + input fabric_fpga_interrupt_in_i30; + input fabric_fpga_interrupt_in_i31; + input fabric_fpga_interrupt_in_i32; + input fabric_fpga_interrupt_in_i33; + input fabric_fpga_interrupt_in_i34; + input fabric_fpga_interrupt_in_i35; + input fabric_fpga_interrupt_in_i36; + input fabric_fpga_interrupt_in_i37; + input fabric_fpga_interrupt_in_i38; + input fabric_fpga_interrupt_in_i39; + input fabric_fpga_interrupt_in_i4; + input fabric_fpga_interrupt_in_i40; + input fabric_fpga_interrupt_in_i41; + input fabric_fpga_interrupt_in_i42; + input fabric_fpga_interrupt_in_i43; + input fabric_fpga_interrupt_in_i44; + input fabric_fpga_interrupt_in_i45; + input fabric_fpga_interrupt_in_i46; + input fabric_fpga_interrupt_in_i47; + input fabric_fpga_interrupt_in_i48; + input fabric_fpga_interrupt_in_i49; + input fabric_fpga_interrupt_in_i5; + input fabric_fpga_interrupt_in_i50; + input fabric_fpga_interrupt_in_i51; + input fabric_fpga_interrupt_in_i52; + input fabric_fpga_interrupt_in_i53; + input fabric_fpga_interrupt_in_i54; + input fabric_fpga_interrupt_in_i55; + input fabric_fpga_interrupt_in_i56; + input fabric_fpga_interrupt_in_i57; + input fabric_fpga_interrupt_in_i58; + input fabric_fpga_interrupt_in_i59; + input fabric_fpga_interrupt_in_i6; + input fabric_fpga_interrupt_in_i60; + input fabric_fpga_interrupt_in_i61; + input fabric_fpga_interrupt_in_i62; + input fabric_fpga_interrupt_in_i63; + input fabric_fpga_interrupt_in_i64; + input fabric_fpga_interrupt_in_i65; + input fabric_fpga_interrupt_in_i66; + input fabric_fpga_interrupt_in_i67; + input fabric_fpga_interrupt_in_i68; + input fabric_fpga_interrupt_in_i69; + input fabric_fpga_interrupt_in_i7; + input fabric_fpga_interrupt_in_i70; + input fabric_fpga_interrupt_in_i71; + input fabric_fpga_interrupt_in_i72; + input fabric_fpga_interrupt_in_i73; + input fabric_fpga_interrupt_in_i74; + input fabric_fpga_interrupt_in_i75; + input fabric_fpga_interrupt_in_i76; + input fabric_fpga_interrupt_in_i77; + input fabric_fpga_interrupt_in_i78; + input fabric_fpga_interrupt_in_i79; + input fabric_fpga_interrupt_in_i8; + input fabric_fpga_interrupt_in_i80; + input fabric_fpga_interrupt_in_i81; + input fabric_fpga_interrupt_in_i82; + input fabric_fpga_interrupt_in_i83; + input fabric_fpga_interrupt_in_i84; + input fabric_fpga_interrupt_in_i85; + input fabric_fpga_interrupt_in_i86; + input fabric_fpga_interrupt_in_i87; + input fabric_fpga_interrupt_in_i88; + input fabric_fpga_interrupt_in_i89; + input fabric_fpga_interrupt_in_i9; + input fabric_fpga_interrupt_in_i90; + input fabric_fpga_interrupt_in_i91; + input fabric_fpga_interrupt_in_i92; + input fabric_fpga_interrupt_in_i93; + input fabric_fpga_interrupt_in_i94; + input fabric_fpga_interrupt_in_i95; + input fabric_fpga_interrupt_in_i96; + input fabric_fpga_interrupt_in_i97; + input fabric_fpga_interrupt_in_i98; + input fabric_fpga_interrupt_in_i99; + input fabric_fpga_nic_rstn_i1; + input fabric_fpga_nic_rstn_i10; + input fabric_fpga_nic_rstn_i2; + input fabric_fpga_nic_rstn_i3; + input fabric_fpga_nic_rstn_i4; + input fabric_fpga_nic_rstn_i5; + input fabric_fpga_nic_rstn_i6; + input fabric_fpga_nic_rstn_i7; + input fabric_fpga_nic_rstn_i8; + input fabric_fpga_nic_rstn_i9; + output fabric_fpga_paddr_apb_o1; + output fabric_fpga_paddr_apb_o10; + output fabric_fpga_paddr_apb_o11; + output fabric_fpga_paddr_apb_o12; + output fabric_fpga_paddr_apb_o13; + output fabric_fpga_paddr_apb_o14; + output fabric_fpga_paddr_apb_o15; + output fabric_fpga_paddr_apb_o16; + output fabric_fpga_paddr_apb_o17; + output fabric_fpga_paddr_apb_o18; + output fabric_fpga_paddr_apb_o19; + output fabric_fpga_paddr_apb_o2; + output fabric_fpga_paddr_apb_o20; + output fabric_fpga_paddr_apb_o21; + output fabric_fpga_paddr_apb_o22; + output fabric_fpga_paddr_apb_o23; + output fabric_fpga_paddr_apb_o24; + output fabric_fpga_paddr_apb_o25; + output fabric_fpga_paddr_apb_o26; + output fabric_fpga_paddr_apb_o27; + output fabric_fpga_paddr_apb_o28; + output fabric_fpga_paddr_apb_o29; + output fabric_fpga_paddr_apb_o3; + output fabric_fpga_paddr_apb_o30; + output fabric_fpga_paddr_apb_o31; + output fabric_fpga_paddr_apb_o32; + output fabric_fpga_paddr_apb_o4; + output fabric_fpga_paddr_apb_o5; + output fabric_fpga_paddr_apb_o6; + output fabric_fpga_paddr_apb_o7; + output fabric_fpga_paddr_apb_o8; + output fabric_fpga_paddr_apb_o9; + output fabric_fpga_penable_apb_o; + input fabric_fpga_pmrstn_i; + input fabric_fpga_prdata_apb_i1; + input fabric_fpga_prdata_apb_i10; + input fabric_fpga_prdata_apb_i11; + input fabric_fpga_prdata_apb_i12; + input fabric_fpga_prdata_apb_i13; + input fabric_fpga_prdata_apb_i14; + input fabric_fpga_prdata_apb_i15; + input fabric_fpga_prdata_apb_i16; + input fabric_fpga_prdata_apb_i17; + input fabric_fpga_prdata_apb_i18; + input fabric_fpga_prdata_apb_i19; + input fabric_fpga_prdata_apb_i2; + input fabric_fpga_prdata_apb_i20; + input fabric_fpga_prdata_apb_i21; + input fabric_fpga_prdata_apb_i22; + input fabric_fpga_prdata_apb_i23; + input fabric_fpga_prdata_apb_i24; + input fabric_fpga_prdata_apb_i25; + input fabric_fpga_prdata_apb_i26; + input fabric_fpga_prdata_apb_i27; + input fabric_fpga_prdata_apb_i28; + input fabric_fpga_prdata_apb_i29; + input fabric_fpga_prdata_apb_i3; + input fabric_fpga_prdata_apb_i30; + input fabric_fpga_prdata_apb_i31; + input fabric_fpga_prdata_apb_i32; + input fabric_fpga_prdata_apb_i4; + input fabric_fpga_prdata_apb_i5; + input fabric_fpga_prdata_apb_i6; + input fabric_fpga_prdata_apb_i7; + input fabric_fpga_prdata_apb_i8; + input fabric_fpga_prdata_apb_i9; + input fabric_fpga_pready_apb_i; + output fabric_fpga_psel_apb_o; + input fabric_fpga_pslverr_apb_i; + output fabric_fpga_pwdata_apb_o1; + output fabric_fpga_pwdata_apb_o10; + output fabric_fpga_pwdata_apb_o11; + output fabric_fpga_pwdata_apb_o12; + output fabric_fpga_pwdata_apb_o13; + output fabric_fpga_pwdata_apb_o14; + output fabric_fpga_pwdata_apb_o15; + output fabric_fpga_pwdata_apb_o16; + output fabric_fpga_pwdata_apb_o17; + output fabric_fpga_pwdata_apb_o18; + output fabric_fpga_pwdata_apb_o19; + output fabric_fpga_pwdata_apb_o2; + output fabric_fpga_pwdata_apb_o20; + output fabric_fpga_pwdata_apb_o21; + output fabric_fpga_pwdata_apb_o22; + output fabric_fpga_pwdata_apb_o23; + output fabric_fpga_pwdata_apb_o24; + output fabric_fpga_pwdata_apb_o25; + output fabric_fpga_pwdata_apb_o26; + output fabric_fpga_pwdata_apb_o27; + output fabric_fpga_pwdata_apb_o28; + output fabric_fpga_pwdata_apb_o29; + output fabric_fpga_pwdata_apb_o3; + output fabric_fpga_pwdata_apb_o30; + output fabric_fpga_pwdata_apb_o31; + output fabric_fpga_pwdata_apb_o32; + output fabric_fpga_pwdata_apb_o4; + output fabric_fpga_pwdata_apb_o5; + output fabric_fpga_pwdata_apb_o6; + output fabric_fpga_pwdata_apb_o7; + output fabric_fpga_pwdata_apb_o8; + output fabric_fpga_pwdata_apb_o9; + output fabric_fpga_pwrite_apb_o; + output fabric_fpga_rdata_axi_m1_o1; + output fabric_fpga_rdata_axi_m1_o10; + output fabric_fpga_rdata_axi_m1_o100; + output fabric_fpga_rdata_axi_m1_o101; + output fabric_fpga_rdata_axi_m1_o102; + output fabric_fpga_rdata_axi_m1_o103; + output fabric_fpga_rdata_axi_m1_o104; + output fabric_fpga_rdata_axi_m1_o105; + output fabric_fpga_rdata_axi_m1_o106; + output fabric_fpga_rdata_axi_m1_o107; + output fabric_fpga_rdata_axi_m1_o108; + output fabric_fpga_rdata_axi_m1_o109; + output fabric_fpga_rdata_axi_m1_o11; + output fabric_fpga_rdata_axi_m1_o110; + output fabric_fpga_rdata_axi_m1_o111; + output fabric_fpga_rdata_axi_m1_o112; + output fabric_fpga_rdata_axi_m1_o113; + output fabric_fpga_rdata_axi_m1_o114; + output fabric_fpga_rdata_axi_m1_o115; + output fabric_fpga_rdata_axi_m1_o116; + output fabric_fpga_rdata_axi_m1_o117; + output fabric_fpga_rdata_axi_m1_o118; + output fabric_fpga_rdata_axi_m1_o119; + output fabric_fpga_rdata_axi_m1_o12; + output fabric_fpga_rdata_axi_m1_o120; + output fabric_fpga_rdata_axi_m1_o121; + output fabric_fpga_rdata_axi_m1_o122; + output fabric_fpga_rdata_axi_m1_o123; + output fabric_fpga_rdata_axi_m1_o124; + output fabric_fpga_rdata_axi_m1_o125; + output fabric_fpga_rdata_axi_m1_o126; + output fabric_fpga_rdata_axi_m1_o127; + output fabric_fpga_rdata_axi_m1_o128; + output fabric_fpga_rdata_axi_m1_o13; + output fabric_fpga_rdata_axi_m1_o14; + output fabric_fpga_rdata_axi_m1_o15; + output fabric_fpga_rdata_axi_m1_o16; + output fabric_fpga_rdata_axi_m1_o17; + output fabric_fpga_rdata_axi_m1_o18; + output fabric_fpga_rdata_axi_m1_o19; + output fabric_fpga_rdata_axi_m1_o2; + output fabric_fpga_rdata_axi_m1_o20; + output fabric_fpga_rdata_axi_m1_o21; + output fabric_fpga_rdata_axi_m1_o22; + output fabric_fpga_rdata_axi_m1_o23; + output fabric_fpga_rdata_axi_m1_o24; + output fabric_fpga_rdata_axi_m1_o25; + output fabric_fpga_rdata_axi_m1_o26; + output fabric_fpga_rdata_axi_m1_o27; + output fabric_fpga_rdata_axi_m1_o28; + output fabric_fpga_rdata_axi_m1_o29; + output fabric_fpga_rdata_axi_m1_o3; + output fabric_fpga_rdata_axi_m1_o30; + output fabric_fpga_rdata_axi_m1_o31; + output fabric_fpga_rdata_axi_m1_o32; + output fabric_fpga_rdata_axi_m1_o33; + output fabric_fpga_rdata_axi_m1_o34; + output fabric_fpga_rdata_axi_m1_o35; + output fabric_fpga_rdata_axi_m1_o36; + output fabric_fpga_rdata_axi_m1_o37; + output fabric_fpga_rdata_axi_m1_o38; + output fabric_fpga_rdata_axi_m1_o39; + output fabric_fpga_rdata_axi_m1_o4; + output fabric_fpga_rdata_axi_m1_o40; + output fabric_fpga_rdata_axi_m1_o41; + output fabric_fpga_rdata_axi_m1_o42; + output fabric_fpga_rdata_axi_m1_o43; + output fabric_fpga_rdata_axi_m1_o44; + output fabric_fpga_rdata_axi_m1_o45; + output fabric_fpga_rdata_axi_m1_o46; + output fabric_fpga_rdata_axi_m1_o47; + output fabric_fpga_rdata_axi_m1_o48; + output fabric_fpga_rdata_axi_m1_o49; + output fabric_fpga_rdata_axi_m1_o5; + output fabric_fpga_rdata_axi_m1_o50; + output fabric_fpga_rdata_axi_m1_o51; + output fabric_fpga_rdata_axi_m1_o52; + output fabric_fpga_rdata_axi_m1_o53; + output fabric_fpga_rdata_axi_m1_o54; + output fabric_fpga_rdata_axi_m1_o55; + output fabric_fpga_rdata_axi_m1_o56; + output fabric_fpga_rdata_axi_m1_o57; + output fabric_fpga_rdata_axi_m1_o58; + output fabric_fpga_rdata_axi_m1_o59; + output fabric_fpga_rdata_axi_m1_o6; + output fabric_fpga_rdata_axi_m1_o60; + output fabric_fpga_rdata_axi_m1_o61; + output fabric_fpga_rdata_axi_m1_o62; + output fabric_fpga_rdata_axi_m1_o63; + output fabric_fpga_rdata_axi_m1_o64; + output fabric_fpga_rdata_axi_m1_o65; + output fabric_fpga_rdata_axi_m1_o66; + output fabric_fpga_rdata_axi_m1_o67; + output fabric_fpga_rdata_axi_m1_o68; + output fabric_fpga_rdata_axi_m1_o69; + output fabric_fpga_rdata_axi_m1_o7; + output fabric_fpga_rdata_axi_m1_o70; + output fabric_fpga_rdata_axi_m1_o71; + output fabric_fpga_rdata_axi_m1_o72; + output fabric_fpga_rdata_axi_m1_o73; + output fabric_fpga_rdata_axi_m1_o74; + output fabric_fpga_rdata_axi_m1_o75; + output fabric_fpga_rdata_axi_m1_o76; + output fabric_fpga_rdata_axi_m1_o77; + output fabric_fpga_rdata_axi_m1_o78; + output fabric_fpga_rdata_axi_m1_o79; + output fabric_fpga_rdata_axi_m1_o8; + output fabric_fpga_rdata_axi_m1_o80; + output fabric_fpga_rdata_axi_m1_o81; + output fabric_fpga_rdata_axi_m1_o82; + output fabric_fpga_rdata_axi_m1_o83; + output fabric_fpga_rdata_axi_m1_o84; + output fabric_fpga_rdata_axi_m1_o85; + output fabric_fpga_rdata_axi_m1_o86; + output fabric_fpga_rdata_axi_m1_o87; + output fabric_fpga_rdata_axi_m1_o88; + output fabric_fpga_rdata_axi_m1_o89; + output fabric_fpga_rdata_axi_m1_o9; + output fabric_fpga_rdata_axi_m1_o90; + output fabric_fpga_rdata_axi_m1_o91; + output fabric_fpga_rdata_axi_m1_o92; + output fabric_fpga_rdata_axi_m1_o93; + output fabric_fpga_rdata_axi_m1_o94; + output fabric_fpga_rdata_axi_m1_o95; + output fabric_fpga_rdata_axi_m1_o96; + output fabric_fpga_rdata_axi_m1_o97; + output fabric_fpga_rdata_axi_m1_o98; + output fabric_fpga_rdata_axi_m1_o99; + output fabric_fpga_rdata_axi_m2_o1; + output fabric_fpga_rdata_axi_m2_o10; + output fabric_fpga_rdata_axi_m2_o100; + output fabric_fpga_rdata_axi_m2_o101; + output fabric_fpga_rdata_axi_m2_o102; + output fabric_fpga_rdata_axi_m2_o103; + output fabric_fpga_rdata_axi_m2_o104; + output fabric_fpga_rdata_axi_m2_o105; + output fabric_fpga_rdata_axi_m2_o106; + output fabric_fpga_rdata_axi_m2_o107; + output fabric_fpga_rdata_axi_m2_o108; + output fabric_fpga_rdata_axi_m2_o109; + output fabric_fpga_rdata_axi_m2_o11; + output fabric_fpga_rdata_axi_m2_o110; + output fabric_fpga_rdata_axi_m2_o111; + output fabric_fpga_rdata_axi_m2_o112; + output fabric_fpga_rdata_axi_m2_o113; + output fabric_fpga_rdata_axi_m2_o114; + output fabric_fpga_rdata_axi_m2_o115; + output fabric_fpga_rdata_axi_m2_o116; + output fabric_fpga_rdata_axi_m2_o117; + output fabric_fpga_rdata_axi_m2_o118; + output fabric_fpga_rdata_axi_m2_o119; + output fabric_fpga_rdata_axi_m2_o12; + output fabric_fpga_rdata_axi_m2_o120; + output fabric_fpga_rdata_axi_m2_o121; + output fabric_fpga_rdata_axi_m2_o122; + output fabric_fpga_rdata_axi_m2_o123; + output fabric_fpga_rdata_axi_m2_o124; + output fabric_fpga_rdata_axi_m2_o125; + output fabric_fpga_rdata_axi_m2_o126; + output fabric_fpga_rdata_axi_m2_o127; + output fabric_fpga_rdata_axi_m2_o128; + output fabric_fpga_rdata_axi_m2_o13; + output fabric_fpga_rdata_axi_m2_o14; + output fabric_fpga_rdata_axi_m2_o15; + output fabric_fpga_rdata_axi_m2_o16; + output fabric_fpga_rdata_axi_m2_o17; + output fabric_fpga_rdata_axi_m2_o18; + output fabric_fpga_rdata_axi_m2_o19; + output fabric_fpga_rdata_axi_m2_o2; + output fabric_fpga_rdata_axi_m2_o20; + output fabric_fpga_rdata_axi_m2_o21; + output fabric_fpga_rdata_axi_m2_o22; + output fabric_fpga_rdata_axi_m2_o23; + output fabric_fpga_rdata_axi_m2_o24; + output fabric_fpga_rdata_axi_m2_o25; + output fabric_fpga_rdata_axi_m2_o26; + output fabric_fpga_rdata_axi_m2_o27; + output fabric_fpga_rdata_axi_m2_o28; + output fabric_fpga_rdata_axi_m2_o29; + output fabric_fpga_rdata_axi_m2_o3; + output fabric_fpga_rdata_axi_m2_o30; + output fabric_fpga_rdata_axi_m2_o31; + output fabric_fpga_rdata_axi_m2_o32; + output fabric_fpga_rdata_axi_m2_o33; + output fabric_fpga_rdata_axi_m2_o34; + output fabric_fpga_rdata_axi_m2_o35; + output fabric_fpga_rdata_axi_m2_o36; + output fabric_fpga_rdata_axi_m2_o37; + output fabric_fpga_rdata_axi_m2_o38; + output fabric_fpga_rdata_axi_m2_o39; + output fabric_fpga_rdata_axi_m2_o4; + output fabric_fpga_rdata_axi_m2_o40; + output fabric_fpga_rdata_axi_m2_o41; + output fabric_fpga_rdata_axi_m2_o42; + output fabric_fpga_rdata_axi_m2_o43; + output fabric_fpga_rdata_axi_m2_o44; + output fabric_fpga_rdata_axi_m2_o45; + output fabric_fpga_rdata_axi_m2_o46; + output fabric_fpga_rdata_axi_m2_o47; + output fabric_fpga_rdata_axi_m2_o48; + output fabric_fpga_rdata_axi_m2_o49; + output fabric_fpga_rdata_axi_m2_o5; + output fabric_fpga_rdata_axi_m2_o50; + output fabric_fpga_rdata_axi_m2_o51; + output fabric_fpga_rdata_axi_m2_o52; + output fabric_fpga_rdata_axi_m2_o53; + output fabric_fpga_rdata_axi_m2_o54; + output fabric_fpga_rdata_axi_m2_o55; + output fabric_fpga_rdata_axi_m2_o56; + output fabric_fpga_rdata_axi_m2_o57; + output fabric_fpga_rdata_axi_m2_o58; + output fabric_fpga_rdata_axi_m2_o59; + output fabric_fpga_rdata_axi_m2_o6; + output fabric_fpga_rdata_axi_m2_o60; + output fabric_fpga_rdata_axi_m2_o61; + output fabric_fpga_rdata_axi_m2_o62; + output fabric_fpga_rdata_axi_m2_o63; + output fabric_fpga_rdata_axi_m2_o64; + output fabric_fpga_rdata_axi_m2_o65; + output fabric_fpga_rdata_axi_m2_o66; + output fabric_fpga_rdata_axi_m2_o67; + output fabric_fpga_rdata_axi_m2_o68; + output fabric_fpga_rdata_axi_m2_o69; + output fabric_fpga_rdata_axi_m2_o7; + output fabric_fpga_rdata_axi_m2_o70; + output fabric_fpga_rdata_axi_m2_o71; + output fabric_fpga_rdata_axi_m2_o72; + output fabric_fpga_rdata_axi_m2_o73; + output fabric_fpga_rdata_axi_m2_o74; + output fabric_fpga_rdata_axi_m2_o75; + output fabric_fpga_rdata_axi_m2_o76; + output fabric_fpga_rdata_axi_m2_o77; + output fabric_fpga_rdata_axi_m2_o78; + output fabric_fpga_rdata_axi_m2_o79; + output fabric_fpga_rdata_axi_m2_o8; + output fabric_fpga_rdata_axi_m2_o80; + output fabric_fpga_rdata_axi_m2_o81; + output fabric_fpga_rdata_axi_m2_o82; + output fabric_fpga_rdata_axi_m2_o83; + output fabric_fpga_rdata_axi_m2_o84; + output fabric_fpga_rdata_axi_m2_o85; + output fabric_fpga_rdata_axi_m2_o86; + output fabric_fpga_rdata_axi_m2_o87; + output fabric_fpga_rdata_axi_m2_o88; + output fabric_fpga_rdata_axi_m2_o89; + output fabric_fpga_rdata_axi_m2_o9; + output fabric_fpga_rdata_axi_m2_o90; + output fabric_fpga_rdata_axi_m2_o91; + output fabric_fpga_rdata_axi_m2_o92; + output fabric_fpga_rdata_axi_m2_o93; + output fabric_fpga_rdata_axi_m2_o94; + output fabric_fpga_rdata_axi_m2_o95; + output fabric_fpga_rdata_axi_m2_o96; + output fabric_fpga_rdata_axi_m2_o97; + output fabric_fpga_rdata_axi_m2_o98; + output fabric_fpga_rdata_axi_m2_o99; + input fabric_fpga_rdata_axi_s1_i1; + input fabric_fpga_rdata_axi_s1_i10; + input fabric_fpga_rdata_axi_s1_i100; + input fabric_fpga_rdata_axi_s1_i101; + input fabric_fpga_rdata_axi_s1_i102; + input fabric_fpga_rdata_axi_s1_i103; + input fabric_fpga_rdata_axi_s1_i104; + input fabric_fpga_rdata_axi_s1_i105; + input fabric_fpga_rdata_axi_s1_i106; + input fabric_fpga_rdata_axi_s1_i107; + input fabric_fpga_rdata_axi_s1_i108; + input fabric_fpga_rdata_axi_s1_i109; + input fabric_fpga_rdata_axi_s1_i11; + input fabric_fpga_rdata_axi_s1_i110; + input fabric_fpga_rdata_axi_s1_i111; + input fabric_fpga_rdata_axi_s1_i112; + input fabric_fpga_rdata_axi_s1_i113; + input fabric_fpga_rdata_axi_s1_i114; + input fabric_fpga_rdata_axi_s1_i115; + input fabric_fpga_rdata_axi_s1_i116; + input fabric_fpga_rdata_axi_s1_i117; + input fabric_fpga_rdata_axi_s1_i118; + input fabric_fpga_rdata_axi_s1_i119; + input fabric_fpga_rdata_axi_s1_i12; + input fabric_fpga_rdata_axi_s1_i120; + input fabric_fpga_rdata_axi_s1_i121; + input fabric_fpga_rdata_axi_s1_i122; + input fabric_fpga_rdata_axi_s1_i123; + input fabric_fpga_rdata_axi_s1_i124; + input fabric_fpga_rdata_axi_s1_i125; + input fabric_fpga_rdata_axi_s1_i126; + input fabric_fpga_rdata_axi_s1_i127; + input fabric_fpga_rdata_axi_s1_i128; + input fabric_fpga_rdata_axi_s1_i13; + input fabric_fpga_rdata_axi_s1_i14; + input fabric_fpga_rdata_axi_s1_i15; + input fabric_fpga_rdata_axi_s1_i16; + input fabric_fpga_rdata_axi_s1_i17; + input fabric_fpga_rdata_axi_s1_i18; + input fabric_fpga_rdata_axi_s1_i19; + input fabric_fpga_rdata_axi_s1_i2; + input fabric_fpga_rdata_axi_s1_i20; + input fabric_fpga_rdata_axi_s1_i21; + input fabric_fpga_rdata_axi_s1_i22; + input fabric_fpga_rdata_axi_s1_i23; + input fabric_fpga_rdata_axi_s1_i24; + input fabric_fpga_rdata_axi_s1_i25; + input fabric_fpga_rdata_axi_s1_i26; + input fabric_fpga_rdata_axi_s1_i27; + input fabric_fpga_rdata_axi_s1_i28; + input fabric_fpga_rdata_axi_s1_i29; + input fabric_fpga_rdata_axi_s1_i3; + input fabric_fpga_rdata_axi_s1_i30; + input fabric_fpga_rdata_axi_s1_i31; + input fabric_fpga_rdata_axi_s1_i32; + input fabric_fpga_rdata_axi_s1_i33; + input fabric_fpga_rdata_axi_s1_i34; + input fabric_fpga_rdata_axi_s1_i35; + input fabric_fpga_rdata_axi_s1_i36; + input fabric_fpga_rdata_axi_s1_i37; + input fabric_fpga_rdata_axi_s1_i38; + input fabric_fpga_rdata_axi_s1_i39; + input fabric_fpga_rdata_axi_s1_i4; + input fabric_fpga_rdata_axi_s1_i40; + input fabric_fpga_rdata_axi_s1_i41; + input fabric_fpga_rdata_axi_s1_i42; + input fabric_fpga_rdata_axi_s1_i43; + input fabric_fpga_rdata_axi_s1_i44; + input fabric_fpga_rdata_axi_s1_i45; + input fabric_fpga_rdata_axi_s1_i46; + input fabric_fpga_rdata_axi_s1_i47; + input fabric_fpga_rdata_axi_s1_i48; + input fabric_fpga_rdata_axi_s1_i49; + input fabric_fpga_rdata_axi_s1_i5; + input fabric_fpga_rdata_axi_s1_i50; + input fabric_fpga_rdata_axi_s1_i51; + input fabric_fpga_rdata_axi_s1_i52; + input fabric_fpga_rdata_axi_s1_i53; + input fabric_fpga_rdata_axi_s1_i54; + input fabric_fpga_rdata_axi_s1_i55; + input fabric_fpga_rdata_axi_s1_i56; + input fabric_fpga_rdata_axi_s1_i57; + input fabric_fpga_rdata_axi_s1_i58; + input fabric_fpga_rdata_axi_s1_i59; + input fabric_fpga_rdata_axi_s1_i6; + input fabric_fpga_rdata_axi_s1_i60; + input fabric_fpga_rdata_axi_s1_i61; + input fabric_fpga_rdata_axi_s1_i62; + input fabric_fpga_rdata_axi_s1_i63; + input fabric_fpga_rdata_axi_s1_i64; + input fabric_fpga_rdata_axi_s1_i65; + input fabric_fpga_rdata_axi_s1_i66; + input fabric_fpga_rdata_axi_s1_i67; + input fabric_fpga_rdata_axi_s1_i68; + input fabric_fpga_rdata_axi_s1_i69; + input fabric_fpga_rdata_axi_s1_i7; + input fabric_fpga_rdata_axi_s1_i70; + input fabric_fpga_rdata_axi_s1_i71; + input fabric_fpga_rdata_axi_s1_i72; + input fabric_fpga_rdata_axi_s1_i73; + input fabric_fpga_rdata_axi_s1_i74; + input fabric_fpga_rdata_axi_s1_i75; + input fabric_fpga_rdata_axi_s1_i76; + input fabric_fpga_rdata_axi_s1_i77; + input fabric_fpga_rdata_axi_s1_i78; + input fabric_fpga_rdata_axi_s1_i79; + input fabric_fpga_rdata_axi_s1_i8; + input fabric_fpga_rdata_axi_s1_i80; + input fabric_fpga_rdata_axi_s1_i81; + input fabric_fpga_rdata_axi_s1_i82; + input fabric_fpga_rdata_axi_s1_i83; + input fabric_fpga_rdata_axi_s1_i84; + input fabric_fpga_rdata_axi_s1_i85; + input fabric_fpga_rdata_axi_s1_i86; + input fabric_fpga_rdata_axi_s1_i87; + input fabric_fpga_rdata_axi_s1_i88; + input fabric_fpga_rdata_axi_s1_i89; + input fabric_fpga_rdata_axi_s1_i9; + input fabric_fpga_rdata_axi_s1_i90; + input fabric_fpga_rdata_axi_s1_i91; + input fabric_fpga_rdata_axi_s1_i92; + input fabric_fpga_rdata_axi_s1_i93; + input fabric_fpga_rdata_axi_s1_i94; + input fabric_fpga_rdata_axi_s1_i95; + input fabric_fpga_rdata_axi_s1_i96; + input fabric_fpga_rdata_axi_s1_i97; + input fabric_fpga_rdata_axi_s1_i98; + input fabric_fpga_rdata_axi_s1_i99; + input fabric_fpga_rdata_axi_s2_i1; + input fabric_fpga_rdata_axi_s2_i10; + input fabric_fpga_rdata_axi_s2_i100; + input fabric_fpga_rdata_axi_s2_i101; + input fabric_fpga_rdata_axi_s2_i102; + input fabric_fpga_rdata_axi_s2_i103; + input fabric_fpga_rdata_axi_s2_i104; + input fabric_fpga_rdata_axi_s2_i105; + input fabric_fpga_rdata_axi_s2_i106; + input fabric_fpga_rdata_axi_s2_i107; + input fabric_fpga_rdata_axi_s2_i108; + input fabric_fpga_rdata_axi_s2_i109; + input fabric_fpga_rdata_axi_s2_i11; + input fabric_fpga_rdata_axi_s2_i110; + input fabric_fpga_rdata_axi_s2_i111; + input fabric_fpga_rdata_axi_s2_i112; + input fabric_fpga_rdata_axi_s2_i113; + input fabric_fpga_rdata_axi_s2_i114; + input fabric_fpga_rdata_axi_s2_i115; + input fabric_fpga_rdata_axi_s2_i116; + input fabric_fpga_rdata_axi_s2_i117; + input fabric_fpga_rdata_axi_s2_i118; + input fabric_fpga_rdata_axi_s2_i119; + input fabric_fpga_rdata_axi_s2_i12; + input fabric_fpga_rdata_axi_s2_i120; + input fabric_fpga_rdata_axi_s2_i121; + input fabric_fpga_rdata_axi_s2_i122; + input fabric_fpga_rdata_axi_s2_i123; + input fabric_fpga_rdata_axi_s2_i124; + input fabric_fpga_rdata_axi_s2_i125; + input fabric_fpga_rdata_axi_s2_i126; + input fabric_fpga_rdata_axi_s2_i127; + input fabric_fpga_rdata_axi_s2_i128; + input fabric_fpga_rdata_axi_s2_i13; + input fabric_fpga_rdata_axi_s2_i14; + input fabric_fpga_rdata_axi_s2_i15; + input fabric_fpga_rdata_axi_s2_i16; + input fabric_fpga_rdata_axi_s2_i17; + input fabric_fpga_rdata_axi_s2_i18; + input fabric_fpga_rdata_axi_s2_i19; + input fabric_fpga_rdata_axi_s2_i2; + input fabric_fpga_rdata_axi_s2_i20; + input fabric_fpga_rdata_axi_s2_i21; + input fabric_fpga_rdata_axi_s2_i22; + input fabric_fpga_rdata_axi_s2_i23; + input fabric_fpga_rdata_axi_s2_i24; + input fabric_fpga_rdata_axi_s2_i25; + input fabric_fpga_rdata_axi_s2_i26; + input fabric_fpga_rdata_axi_s2_i27; + input fabric_fpga_rdata_axi_s2_i28; + input fabric_fpga_rdata_axi_s2_i29; + input fabric_fpga_rdata_axi_s2_i3; + input fabric_fpga_rdata_axi_s2_i30; + input fabric_fpga_rdata_axi_s2_i31; + input fabric_fpga_rdata_axi_s2_i32; + input fabric_fpga_rdata_axi_s2_i33; + input fabric_fpga_rdata_axi_s2_i34; + input fabric_fpga_rdata_axi_s2_i35; + input fabric_fpga_rdata_axi_s2_i36; + input fabric_fpga_rdata_axi_s2_i37; + input fabric_fpga_rdata_axi_s2_i38; + input fabric_fpga_rdata_axi_s2_i39; + input fabric_fpga_rdata_axi_s2_i4; + input fabric_fpga_rdata_axi_s2_i40; + input fabric_fpga_rdata_axi_s2_i41; + input fabric_fpga_rdata_axi_s2_i42; + input fabric_fpga_rdata_axi_s2_i43; + input fabric_fpga_rdata_axi_s2_i44; + input fabric_fpga_rdata_axi_s2_i45; + input fabric_fpga_rdata_axi_s2_i46; + input fabric_fpga_rdata_axi_s2_i47; + input fabric_fpga_rdata_axi_s2_i48; + input fabric_fpga_rdata_axi_s2_i49; + input fabric_fpga_rdata_axi_s2_i5; + input fabric_fpga_rdata_axi_s2_i50; + input fabric_fpga_rdata_axi_s2_i51; + input fabric_fpga_rdata_axi_s2_i52; + input fabric_fpga_rdata_axi_s2_i53; + input fabric_fpga_rdata_axi_s2_i54; + input fabric_fpga_rdata_axi_s2_i55; + input fabric_fpga_rdata_axi_s2_i56; + input fabric_fpga_rdata_axi_s2_i57; + input fabric_fpga_rdata_axi_s2_i58; + input fabric_fpga_rdata_axi_s2_i59; + input fabric_fpga_rdata_axi_s2_i6; + input fabric_fpga_rdata_axi_s2_i60; + input fabric_fpga_rdata_axi_s2_i61; + input fabric_fpga_rdata_axi_s2_i62; + input fabric_fpga_rdata_axi_s2_i63; + input fabric_fpga_rdata_axi_s2_i64; + input fabric_fpga_rdata_axi_s2_i65; + input fabric_fpga_rdata_axi_s2_i66; + input fabric_fpga_rdata_axi_s2_i67; + input fabric_fpga_rdata_axi_s2_i68; + input fabric_fpga_rdata_axi_s2_i69; + input fabric_fpga_rdata_axi_s2_i7; + input fabric_fpga_rdata_axi_s2_i70; + input fabric_fpga_rdata_axi_s2_i71; + input fabric_fpga_rdata_axi_s2_i72; + input fabric_fpga_rdata_axi_s2_i73; + input fabric_fpga_rdata_axi_s2_i74; + input fabric_fpga_rdata_axi_s2_i75; + input fabric_fpga_rdata_axi_s2_i76; + input fabric_fpga_rdata_axi_s2_i77; + input fabric_fpga_rdata_axi_s2_i78; + input fabric_fpga_rdata_axi_s2_i79; + input fabric_fpga_rdata_axi_s2_i8; + input fabric_fpga_rdata_axi_s2_i80; + input fabric_fpga_rdata_axi_s2_i81; + input fabric_fpga_rdata_axi_s2_i82; + input fabric_fpga_rdata_axi_s2_i83; + input fabric_fpga_rdata_axi_s2_i84; + input fabric_fpga_rdata_axi_s2_i85; + input fabric_fpga_rdata_axi_s2_i86; + input fabric_fpga_rdata_axi_s2_i87; + input fabric_fpga_rdata_axi_s2_i88; + input fabric_fpga_rdata_axi_s2_i89; + input fabric_fpga_rdata_axi_s2_i9; + input fabric_fpga_rdata_axi_s2_i90; + input fabric_fpga_rdata_axi_s2_i91; + input fabric_fpga_rdata_axi_s2_i92; + input fabric_fpga_rdata_axi_s2_i93; + input fabric_fpga_rdata_axi_s2_i94; + input fabric_fpga_rdata_axi_s2_i95; + input fabric_fpga_rdata_axi_s2_i96; + input fabric_fpga_rdata_axi_s2_i97; + input fabric_fpga_rdata_axi_s2_i98; + input fabric_fpga_rdata_axi_s2_i99; + output fabric_fpga_rid_axi_m1_o1; + output fabric_fpga_rid_axi_m1_o2; + output fabric_fpga_rid_axi_m1_o3; + output fabric_fpga_rid_axi_m1_o4; + output fabric_fpga_rid_axi_m1_o5; + output fabric_fpga_rid_axi_m2_o1; + output fabric_fpga_rid_axi_m2_o2; + output fabric_fpga_rid_axi_m2_o3; + output fabric_fpga_rid_axi_m2_o4; + output fabric_fpga_rid_axi_m2_o5; + input fabric_fpga_rid_axi_s1_i1; + input fabric_fpga_rid_axi_s1_i10; + input fabric_fpga_rid_axi_s1_i11; + input fabric_fpga_rid_axi_s1_i12; + input fabric_fpga_rid_axi_s1_i2; + input fabric_fpga_rid_axi_s1_i3; + input fabric_fpga_rid_axi_s1_i4; + input fabric_fpga_rid_axi_s1_i5; + input fabric_fpga_rid_axi_s1_i6; + input fabric_fpga_rid_axi_s1_i7; + input fabric_fpga_rid_axi_s1_i8; + input fabric_fpga_rid_axi_s1_i9; + input fabric_fpga_rid_axi_s2_i1; + input fabric_fpga_rid_axi_s2_i10; + input fabric_fpga_rid_axi_s2_i11; + input fabric_fpga_rid_axi_s2_i12; + input fabric_fpga_rid_axi_s2_i2; + input fabric_fpga_rid_axi_s2_i3; + input fabric_fpga_rid_axi_s2_i4; + input fabric_fpga_rid_axi_s2_i5; + input fabric_fpga_rid_axi_s2_i6; + input fabric_fpga_rid_axi_s2_i7; + input fabric_fpga_rid_axi_s2_i8; + input fabric_fpga_rid_axi_s2_i9; + output fabric_fpga_rlast_axi_m1_o; + output fabric_fpga_rlast_axi_m2_o; + input fabric_fpga_rlast_axi_s1_i; + input fabric_fpga_rlast_axi_s2_i; + input fabric_fpga_rready_axi_m1_i; + input fabric_fpga_rready_axi_m2_i; + output fabric_fpga_rready_axi_s1_o; + output fabric_fpga_rready_axi_s2_o; + output fabric_fpga_rresp_axi_m1_o1; + output fabric_fpga_rresp_axi_m1_o2; + output fabric_fpga_rresp_axi_m2_o1; + output fabric_fpga_rresp_axi_m2_o2; + input fabric_fpga_rresp_axi_s1_i1; + input fabric_fpga_rresp_axi_s1_i2; + input fabric_fpga_rresp_axi_s2_i1; + input fabric_fpga_rresp_axi_s2_i2; + output fabric_fpga_rvalid_axi_m1_o; + output fabric_fpga_rvalid_axi_m2_o; + input fabric_fpga_rvalid_axi_s1_i; + input fabric_fpga_rvalid_axi_s2_i; + input fabric_fpga_sysrstn_i; + output fabric_fpga_trigger_in_o1; + output fabric_fpga_trigger_in_o2; + output fabric_fpga_trigger_in_o3; + output fabric_fpga_trigger_in_o4; + output fabric_fpga_trigger_in_o5; + output fabric_fpga_trigger_in_o6; + output fabric_fpga_trigger_in_o7; + output fabric_fpga_trigger_in_o8; + input fabric_fpga_trigger_out_i1; + input fabric_fpga_trigger_out_i2; + input fabric_fpga_trigger_out_i3; + input fabric_fpga_trigger_out_i4; + input fabric_fpga_trigger_out_i5; + input fabric_fpga_trigger_out_i6; + input fabric_fpga_trigger_out_i7; + input fabric_fpga_trigger_out_i8; + input fabric_fpga_wdata_axi_m1_i1; + input fabric_fpga_wdata_axi_m1_i10; + input fabric_fpga_wdata_axi_m1_i100; + input fabric_fpga_wdata_axi_m1_i101; + input fabric_fpga_wdata_axi_m1_i102; + input fabric_fpga_wdata_axi_m1_i103; + input fabric_fpga_wdata_axi_m1_i104; + input fabric_fpga_wdata_axi_m1_i105; + input fabric_fpga_wdata_axi_m1_i106; + input fabric_fpga_wdata_axi_m1_i107; + input fabric_fpga_wdata_axi_m1_i108; + input fabric_fpga_wdata_axi_m1_i109; + input fabric_fpga_wdata_axi_m1_i11; + input fabric_fpga_wdata_axi_m1_i110; + input fabric_fpga_wdata_axi_m1_i111; + input fabric_fpga_wdata_axi_m1_i112; + input fabric_fpga_wdata_axi_m1_i113; + input fabric_fpga_wdata_axi_m1_i114; + input fabric_fpga_wdata_axi_m1_i115; + input fabric_fpga_wdata_axi_m1_i116; + input fabric_fpga_wdata_axi_m1_i117; + input fabric_fpga_wdata_axi_m1_i118; + input fabric_fpga_wdata_axi_m1_i119; + input fabric_fpga_wdata_axi_m1_i12; + input fabric_fpga_wdata_axi_m1_i120; + input fabric_fpga_wdata_axi_m1_i121; + input fabric_fpga_wdata_axi_m1_i122; + input fabric_fpga_wdata_axi_m1_i123; + input fabric_fpga_wdata_axi_m1_i124; + input fabric_fpga_wdata_axi_m1_i125; + input fabric_fpga_wdata_axi_m1_i126; + input fabric_fpga_wdata_axi_m1_i127; + input fabric_fpga_wdata_axi_m1_i128; + input fabric_fpga_wdata_axi_m1_i13; + input fabric_fpga_wdata_axi_m1_i14; + input fabric_fpga_wdata_axi_m1_i15; + input fabric_fpga_wdata_axi_m1_i16; + input fabric_fpga_wdata_axi_m1_i17; + input fabric_fpga_wdata_axi_m1_i18; + input fabric_fpga_wdata_axi_m1_i19; + input fabric_fpga_wdata_axi_m1_i2; + input fabric_fpga_wdata_axi_m1_i20; + input fabric_fpga_wdata_axi_m1_i21; + input fabric_fpga_wdata_axi_m1_i22; + input fabric_fpga_wdata_axi_m1_i23; + input fabric_fpga_wdata_axi_m1_i24; + input fabric_fpga_wdata_axi_m1_i25; + input fabric_fpga_wdata_axi_m1_i26; + input fabric_fpga_wdata_axi_m1_i27; + input fabric_fpga_wdata_axi_m1_i28; + input fabric_fpga_wdata_axi_m1_i29; + input fabric_fpga_wdata_axi_m1_i3; + input fabric_fpga_wdata_axi_m1_i30; + input fabric_fpga_wdata_axi_m1_i31; + input fabric_fpga_wdata_axi_m1_i32; + input fabric_fpga_wdata_axi_m1_i33; + input fabric_fpga_wdata_axi_m1_i34; + input fabric_fpga_wdata_axi_m1_i35; + input fabric_fpga_wdata_axi_m1_i36; + input fabric_fpga_wdata_axi_m1_i37; + input fabric_fpga_wdata_axi_m1_i38; + input fabric_fpga_wdata_axi_m1_i39; + input fabric_fpga_wdata_axi_m1_i4; + input fabric_fpga_wdata_axi_m1_i40; + input fabric_fpga_wdata_axi_m1_i41; + input fabric_fpga_wdata_axi_m1_i42; + input fabric_fpga_wdata_axi_m1_i43; + input fabric_fpga_wdata_axi_m1_i44; + input fabric_fpga_wdata_axi_m1_i45; + input fabric_fpga_wdata_axi_m1_i46; + input fabric_fpga_wdata_axi_m1_i47; + input fabric_fpga_wdata_axi_m1_i48; + input fabric_fpga_wdata_axi_m1_i49; + input fabric_fpga_wdata_axi_m1_i5; + input fabric_fpga_wdata_axi_m1_i50; + input fabric_fpga_wdata_axi_m1_i51; + input fabric_fpga_wdata_axi_m1_i52; + input fabric_fpga_wdata_axi_m1_i53; + input fabric_fpga_wdata_axi_m1_i54; + input fabric_fpga_wdata_axi_m1_i55; + input fabric_fpga_wdata_axi_m1_i56; + input fabric_fpga_wdata_axi_m1_i57; + input fabric_fpga_wdata_axi_m1_i58; + input fabric_fpga_wdata_axi_m1_i59; + input fabric_fpga_wdata_axi_m1_i6; + input fabric_fpga_wdata_axi_m1_i60; + input fabric_fpga_wdata_axi_m1_i61; + input fabric_fpga_wdata_axi_m1_i62; + input fabric_fpga_wdata_axi_m1_i63; + input fabric_fpga_wdata_axi_m1_i64; + input fabric_fpga_wdata_axi_m1_i65; + input fabric_fpga_wdata_axi_m1_i66; + input fabric_fpga_wdata_axi_m1_i67; + input fabric_fpga_wdata_axi_m1_i68; + input fabric_fpga_wdata_axi_m1_i69; + input fabric_fpga_wdata_axi_m1_i7; + input fabric_fpga_wdata_axi_m1_i70; + input fabric_fpga_wdata_axi_m1_i71; + input fabric_fpga_wdata_axi_m1_i72; + input fabric_fpga_wdata_axi_m1_i73; + input fabric_fpga_wdata_axi_m1_i74; + input fabric_fpga_wdata_axi_m1_i75; + input fabric_fpga_wdata_axi_m1_i76; + input fabric_fpga_wdata_axi_m1_i77; + input fabric_fpga_wdata_axi_m1_i78; + input fabric_fpga_wdata_axi_m1_i79; + input fabric_fpga_wdata_axi_m1_i8; + input fabric_fpga_wdata_axi_m1_i80; + input fabric_fpga_wdata_axi_m1_i81; + input fabric_fpga_wdata_axi_m1_i82; + input fabric_fpga_wdata_axi_m1_i83; + input fabric_fpga_wdata_axi_m1_i84; + input fabric_fpga_wdata_axi_m1_i85; + input fabric_fpga_wdata_axi_m1_i86; + input fabric_fpga_wdata_axi_m1_i87; + input fabric_fpga_wdata_axi_m1_i88; + input fabric_fpga_wdata_axi_m1_i89; + input fabric_fpga_wdata_axi_m1_i9; + input fabric_fpga_wdata_axi_m1_i90; + input fabric_fpga_wdata_axi_m1_i91; + input fabric_fpga_wdata_axi_m1_i92; + input fabric_fpga_wdata_axi_m1_i93; + input fabric_fpga_wdata_axi_m1_i94; + input fabric_fpga_wdata_axi_m1_i95; + input fabric_fpga_wdata_axi_m1_i96; + input fabric_fpga_wdata_axi_m1_i97; + input fabric_fpga_wdata_axi_m1_i98; + input fabric_fpga_wdata_axi_m1_i99; + input fabric_fpga_wdata_axi_m2_i1; + input fabric_fpga_wdata_axi_m2_i10; + input fabric_fpga_wdata_axi_m2_i100; + input fabric_fpga_wdata_axi_m2_i101; + input fabric_fpga_wdata_axi_m2_i102; + input fabric_fpga_wdata_axi_m2_i103; + input fabric_fpga_wdata_axi_m2_i104; + input fabric_fpga_wdata_axi_m2_i105; + input fabric_fpga_wdata_axi_m2_i106; + input fabric_fpga_wdata_axi_m2_i107; + input fabric_fpga_wdata_axi_m2_i108; + input fabric_fpga_wdata_axi_m2_i109; + input fabric_fpga_wdata_axi_m2_i11; + input fabric_fpga_wdata_axi_m2_i110; + input fabric_fpga_wdata_axi_m2_i111; + input fabric_fpga_wdata_axi_m2_i112; + input fabric_fpga_wdata_axi_m2_i113; + input fabric_fpga_wdata_axi_m2_i114; + input fabric_fpga_wdata_axi_m2_i115; + input fabric_fpga_wdata_axi_m2_i116; + input fabric_fpga_wdata_axi_m2_i117; + input fabric_fpga_wdata_axi_m2_i118; + input fabric_fpga_wdata_axi_m2_i119; + input fabric_fpga_wdata_axi_m2_i12; + input fabric_fpga_wdata_axi_m2_i120; + input fabric_fpga_wdata_axi_m2_i121; + input fabric_fpga_wdata_axi_m2_i122; + input fabric_fpga_wdata_axi_m2_i123; + input fabric_fpga_wdata_axi_m2_i124; + input fabric_fpga_wdata_axi_m2_i125; + input fabric_fpga_wdata_axi_m2_i126; + input fabric_fpga_wdata_axi_m2_i127; + input fabric_fpga_wdata_axi_m2_i128; + input fabric_fpga_wdata_axi_m2_i13; + input fabric_fpga_wdata_axi_m2_i14; + input fabric_fpga_wdata_axi_m2_i15; + input fabric_fpga_wdata_axi_m2_i16; + input fabric_fpga_wdata_axi_m2_i17; + input fabric_fpga_wdata_axi_m2_i18; + input fabric_fpga_wdata_axi_m2_i19; + input fabric_fpga_wdata_axi_m2_i2; + input fabric_fpga_wdata_axi_m2_i20; + input fabric_fpga_wdata_axi_m2_i21; + input fabric_fpga_wdata_axi_m2_i22; + input fabric_fpga_wdata_axi_m2_i23; + input fabric_fpga_wdata_axi_m2_i24; + input fabric_fpga_wdata_axi_m2_i25; + input fabric_fpga_wdata_axi_m2_i26; + input fabric_fpga_wdata_axi_m2_i27; + input fabric_fpga_wdata_axi_m2_i28; + input fabric_fpga_wdata_axi_m2_i29; + input fabric_fpga_wdata_axi_m2_i3; + input fabric_fpga_wdata_axi_m2_i30; + input fabric_fpga_wdata_axi_m2_i31; + input fabric_fpga_wdata_axi_m2_i32; + input fabric_fpga_wdata_axi_m2_i33; + input fabric_fpga_wdata_axi_m2_i34; + input fabric_fpga_wdata_axi_m2_i35; + input fabric_fpga_wdata_axi_m2_i36; + input fabric_fpga_wdata_axi_m2_i37; + input fabric_fpga_wdata_axi_m2_i38; + input fabric_fpga_wdata_axi_m2_i39; + input fabric_fpga_wdata_axi_m2_i4; + input fabric_fpga_wdata_axi_m2_i40; + input fabric_fpga_wdata_axi_m2_i41; + input fabric_fpga_wdata_axi_m2_i42; + input fabric_fpga_wdata_axi_m2_i43; + input fabric_fpga_wdata_axi_m2_i44; + input fabric_fpga_wdata_axi_m2_i45; + input fabric_fpga_wdata_axi_m2_i46; + input fabric_fpga_wdata_axi_m2_i47; + input fabric_fpga_wdata_axi_m2_i48; + input fabric_fpga_wdata_axi_m2_i49; + input fabric_fpga_wdata_axi_m2_i5; + input fabric_fpga_wdata_axi_m2_i50; + input fabric_fpga_wdata_axi_m2_i51; + input fabric_fpga_wdata_axi_m2_i52; + input fabric_fpga_wdata_axi_m2_i53; + input fabric_fpga_wdata_axi_m2_i54; + input fabric_fpga_wdata_axi_m2_i55; + input fabric_fpga_wdata_axi_m2_i56; + input fabric_fpga_wdata_axi_m2_i57; + input fabric_fpga_wdata_axi_m2_i58; + input fabric_fpga_wdata_axi_m2_i59; + input fabric_fpga_wdata_axi_m2_i6; + input fabric_fpga_wdata_axi_m2_i60; + input fabric_fpga_wdata_axi_m2_i61; + input fabric_fpga_wdata_axi_m2_i62; + input fabric_fpga_wdata_axi_m2_i63; + input fabric_fpga_wdata_axi_m2_i64; + input fabric_fpga_wdata_axi_m2_i65; + input fabric_fpga_wdata_axi_m2_i66; + input fabric_fpga_wdata_axi_m2_i67; + input fabric_fpga_wdata_axi_m2_i68; + input fabric_fpga_wdata_axi_m2_i69; + input fabric_fpga_wdata_axi_m2_i7; + input fabric_fpga_wdata_axi_m2_i70; + input fabric_fpga_wdata_axi_m2_i71; + input fabric_fpga_wdata_axi_m2_i72; + input fabric_fpga_wdata_axi_m2_i73; + input fabric_fpga_wdata_axi_m2_i74; + input fabric_fpga_wdata_axi_m2_i75; + input fabric_fpga_wdata_axi_m2_i76; + input fabric_fpga_wdata_axi_m2_i77; + input fabric_fpga_wdata_axi_m2_i78; + input fabric_fpga_wdata_axi_m2_i79; + input fabric_fpga_wdata_axi_m2_i8; + input fabric_fpga_wdata_axi_m2_i80; + input fabric_fpga_wdata_axi_m2_i81; + input fabric_fpga_wdata_axi_m2_i82; + input fabric_fpga_wdata_axi_m2_i83; + input fabric_fpga_wdata_axi_m2_i84; + input fabric_fpga_wdata_axi_m2_i85; + input fabric_fpga_wdata_axi_m2_i86; + input fabric_fpga_wdata_axi_m2_i87; + input fabric_fpga_wdata_axi_m2_i88; + input fabric_fpga_wdata_axi_m2_i89; + input fabric_fpga_wdata_axi_m2_i9; + input fabric_fpga_wdata_axi_m2_i90; + input fabric_fpga_wdata_axi_m2_i91; + input fabric_fpga_wdata_axi_m2_i92; + input fabric_fpga_wdata_axi_m2_i93; + input fabric_fpga_wdata_axi_m2_i94; + input fabric_fpga_wdata_axi_m2_i95; + input fabric_fpga_wdata_axi_m2_i96; + input fabric_fpga_wdata_axi_m2_i97; + input fabric_fpga_wdata_axi_m2_i98; + input fabric_fpga_wdata_axi_m2_i99; + output fabric_fpga_wdata_axi_s1_o1; + output fabric_fpga_wdata_axi_s1_o10; + output fabric_fpga_wdata_axi_s1_o100; + output fabric_fpga_wdata_axi_s1_o101; + output fabric_fpga_wdata_axi_s1_o102; + output fabric_fpga_wdata_axi_s1_o103; + output fabric_fpga_wdata_axi_s1_o104; + output fabric_fpga_wdata_axi_s1_o105; + output fabric_fpga_wdata_axi_s1_o106; + output fabric_fpga_wdata_axi_s1_o107; + output fabric_fpga_wdata_axi_s1_o108; + output fabric_fpga_wdata_axi_s1_o109; + output fabric_fpga_wdata_axi_s1_o11; + output fabric_fpga_wdata_axi_s1_o110; + output fabric_fpga_wdata_axi_s1_o111; + output fabric_fpga_wdata_axi_s1_o112; + output fabric_fpga_wdata_axi_s1_o113; + output fabric_fpga_wdata_axi_s1_o114; + output fabric_fpga_wdata_axi_s1_o115; + output fabric_fpga_wdata_axi_s1_o116; + output fabric_fpga_wdata_axi_s1_o117; + output fabric_fpga_wdata_axi_s1_o118; + output fabric_fpga_wdata_axi_s1_o119; + output fabric_fpga_wdata_axi_s1_o12; + output fabric_fpga_wdata_axi_s1_o120; + output fabric_fpga_wdata_axi_s1_o121; + output fabric_fpga_wdata_axi_s1_o122; + output fabric_fpga_wdata_axi_s1_o123; + output fabric_fpga_wdata_axi_s1_o124; + output fabric_fpga_wdata_axi_s1_o125; + output fabric_fpga_wdata_axi_s1_o126; + output fabric_fpga_wdata_axi_s1_o127; + output fabric_fpga_wdata_axi_s1_o128; + output fabric_fpga_wdata_axi_s1_o13; + output fabric_fpga_wdata_axi_s1_o14; + output fabric_fpga_wdata_axi_s1_o15; + output fabric_fpga_wdata_axi_s1_o16; + output fabric_fpga_wdata_axi_s1_o17; + output fabric_fpga_wdata_axi_s1_o18; + output fabric_fpga_wdata_axi_s1_o19; + output fabric_fpga_wdata_axi_s1_o2; + output fabric_fpga_wdata_axi_s1_o20; + output fabric_fpga_wdata_axi_s1_o21; + output fabric_fpga_wdata_axi_s1_o22; + output fabric_fpga_wdata_axi_s1_o23; + output fabric_fpga_wdata_axi_s1_o24; + output fabric_fpga_wdata_axi_s1_o25; + output fabric_fpga_wdata_axi_s1_o26; + output fabric_fpga_wdata_axi_s1_o27; + output fabric_fpga_wdata_axi_s1_o28; + output fabric_fpga_wdata_axi_s1_o29; + output fabric_fpga_wdata_axi_s1_o3; + output fabric_fpga_wdata_axi_s1_o30; + output fabric_fpga_wdata_axi_s1_o31; + output fabric_fpga_wdata_axi_s1_o32; + output fabric_fpga_wdata_axi_s1_o33; + output fabric_fpga_wdata_axi_s1_o34; + output fabric_fpga_wdata_axi_s1_o35; + output fabric_fpga_wdata_axi_s1_o36; + output fabric_fpga_wdata_axi_s1_o37; + output fabric_fpga_wdata_axi_s1_o38; + output fabric_fpga_wdata_axi_s1_o39; + output fabric_fpga_wdata_axi_s1_o4; + output fabric_fpga_wdata_axi_s1_o40; + output fabric_fpga_wdata_axi_s1_o41; + output fabric_fpga_wdata_axi_s1_o42; + output fabric_fpga_wdata_axi_s1_o43; + output fabric_fpga_wdata_axi_s1_o44; + output fabric_fpga_wdata_axi_s1_o45; + output fabric_fpga_wdata_axi_s1_o46; + output fabric_fpga_wdata_axi_s1_o47; + output fabric_fpga_wdata_axi_s1_o48; + output fabric_fpga_wdata_axi_s1_o49; + output fabric_fpga_wdata_axi_s1_o5; + output fabric_fpga_wdata_axi_s1_o50; + output fabric_fpga_wdata_axi_s1_o51; + output fabric_fpga_wdata_axi_s1_o52; + output fabric_fpga_wdata_axi_s1_o53; + output fabric_fpga_wdata_axi_s1_o54; + output fabric_fpga_wdata_axi_s1_o55; + output fabric_fpga_wdata_axi_s1_o56; + output fabric_fpga_wdata_axi_s1_o57; + output fabric_fpga_wdata_axi_s1_o58; + output fabric_fpga_wdata_axi_s1_o59; + output fabric_fpga_wdata_axi_s1_o6; + output fabric_fpga_wdata_axi_s1_o60; + output fabric_fpga_wdata_axi_s1_o61; + output fabric_fpga_wdata_axi_s1_o62; + output fabric_fpga_wdata_axi_s1_o63; + output fabric_fpga_wdata_axi_s1_o64; + output fabric_fpga_wdata_axi_s1_o65; + output fabric_fpga_wdata_axi_s1_o66; + output fabric_fpga_wdata_axi_s1_o67; + output fabric_fpga_wdata_axi_s1_o68; + output fabric_fpga_wdata_axi_s1_o69; + output fabric_fpga_wdata_axi_s1_o7; + output fabric_fpga_wdata_axi_s1_o70; + output fabric_fpga_wdata_axi_s1_o71; + output fabric_fpga_wdata_axi_s1_o72; + output fabric_fpga_wdata_axi_s1_o73; + output fabric_fpga_wdata_axi_s1_o74; + output fabric_fpga_wdata_axi_s1_o75; + output fabric_fpga_wdata_axi_s1_o76; + output fabric_fpga_wdata_axi_s1_o77; + output fabric_fpga_wdata_axi_s1_o78; + output fabric_fpga_wdata_axi_s1_o79; + output fabric_fpga_wdata_axi_s1_o8; + output fabric_fpga_wdata_axi_s1_o80; + output fabric_fpga_wdata_axi_s1_o81; + output fabric_fpga_wdata_axi_s1_o82; + output fabric_fpga_wdata_axi_s1_o83; + output fabric_fpga_wdata_axi_s1_o84; + output fabric_fpga_wdata_axi_s1_o85; + output fabric_fpga_wdata_axi_s1_o86; + output fabric_fpga_wdata_axi_s1_o87; + output fabric_fpga_wdata_axi_s1_o88; + output fabric_fpga_wdata_axi_s1_o89; + output fabric_fpga_wdata_axi_s1_o9; + output fabric_fpga_wdata_axi_s1_o90; + output fabric_fpga_wdata_axi_s1_o91; + output fabric_fpga_wdata_axi_s1_o92; + output fabric_fpga_wdata_axi_s1_o93; + output fabric_fpga_wdata_axi_s1_o94; + output fabric_fpga_wdata_axi_s1_o95; + output fabric_fpga_wdata_axi_s1_o96; + output fabric_fpga_wdata_axi_s1_o97; + output fabric_fpga_wdata_axi_s1_o98; + output fabric_fpga_wdata_axi_s1_o99; + output fabric_fpga_wdata_axi_s2_o1; + output fabric_fpga_wdata_axi_s2_o10; + output fabric_fpga_wdata_axi_s2_o100; + output fabric_fpga_wdata_axi_s2_o101; + output fabric_fpga_wdata_axi_s2_o102; + output fabric_fpga_wdata_axi_s2_o103; + output fabric_fpga_wdata_axi_s2_o104; + output fabric_fpga_wdata_axi_s2_o105; + output fabric_fpga_wdata_axi_s2_o106; + output fabric_fpga_wdata_axi_s2_o107; + output fabric_fpga_wdata_axi_s2_o108; + output fabric_fpga_wdata_axi_s2_o109; + output fabric_fpga_wdata_axi_s2_o11; + output fabric_fpga_wdata_axi_s2_o110; + output fabric_fpga_wdata_axi_s2_o111; + output fabric_fpga_wdata_axi_s2_o112; + output fabric_fpga_wdata_axi_s2_o113; + output fabric_fpga_wdata_axi_s2_o114; + output fabric_fpga_wdata_axi_s2_o115; + output fabric_fpga_wdata_axi_s2_o116; + output fabric_fpga_wdata_axi_s2_o117; + output fabric_fpga_wdata_axi_s2_o118; + output fabric_fpga_wdata_axi_s2_o119; + output fabric_fpga_wdata_axi_s2_o12; + output fabric_fpga_wdata_axi_s2_o120; + output fabric_fpga_wdata_axi_s2_o121; + output fabric_fpga_wdata_axi_s2_o122; + output fabric_fpga_wdata_axi_s2_o123; + output fabric_fpga_wdata_axi_s2_o124; + output fabric_fpga_wdata_axi_s2_o125; + output fabric_fpga_wdata_axi_s2_o126; + output fabric_fpga_wdata_axi_s2_o127; + output fabric_fpga_wdata_axi_s2_o128; + output fabric_fpga_wdata_axi_s2_o13; + output fabric_fpga_wdata_axi_s2_o14; + output fabric_fpga_wdata_axi_s2_o15; + output fabric_fpga_wdata_axi_s2_o16; + output fabric_fpga_wdata_axi_s2_o17; + output fabric_fpga_wdata_axi_s2_o18; + output fabric_fpga_wdata_axi_s2_o19; + output fabric_fpga_wdata_axi_s2_o2; + output fabric_fpga_wdata_axi_s2_o20; + output fabric_fpga_wdata_axi_s2_o21; + output fabric_fpga_wdata_axi_s2_o22; + output fabric_fpga_wdata_axi_s2_o23; + output fabric_fpga_wdata_axi_s2_o24; + output fabric_fpga_wdata_axi_s2_o25; + output fabric_fpga_wdata_axi_s2_o26; + output fabric_fpga_wdata_axi_s2_o27; + output fabric_fpga_wdata_axi_s2_o28; + output fabric_fpga_wdata_axi_s2_o29; + output fabric_fpga_wdata_axi_s2_o3; + output fabric_fpga_wdata_axi_s2_o30; + output fabric_fpga_wdata_axi_s2_o31; + output fabric_fpga_wdata_axi_s2_o32; + output fabric_fpga_wdata_axi_s2_o33; + output fabric_fpga_wdata_axi_s2_o34; + output fabric_fpga_wdata_axi_s2_o35; + output fabric_fpga_wdata_axi_s2_o36; + output fabric_fpga_wdata_axi_s2_o37; + output fabric_fpga_wdata_axi_s2_o38; + output fabric_fpga_wdata_axi_s2_o39; + output fabric_fpga_wdata_axi_s2_o4; + output fabric_fpga_wdata_axi_s2_o40; + output fabric_fpga_wdata_axi_s2_o41; + output fabric_fpga_wdata_axi_s2_o42; + output fabric_fpga_wdata_axi_s2_o43; + output fabric_fpga_wdata_axi_s2_o44; + output fabric_fpga_wdata_axi_s2_o45; + output fabric_fpga_wdata_axi_s2_o46; + output fabric_fpga_wdata_axi_s2_o47; + output fabric_fpga_wdata_axi_s2_o48; + output fabric_fpga_wdata_axi_s2_o49; + output fabric_fpga_wdata_axi_s2_o5; + output fabric_fpga_wdata_axi_s2_o50; + output fabric_fpga_wdata_axi_s2_o51; + output fabric_fpga_wdata_axi_s2_o52; + output fabric_fpga_wdata_axi_s2_o53; + output fabric_fpga_wdata_axi_s2_o54; + output fabric_fpga_wdata_axi_s2_o55; + output fabric_fpga_wdata_axi_s2_o56; + output fabric_fpga_wdata_axi_s2_o57; + output fabric_fpga_wdata_axi_s2_o58; + output fabric_fpga_wdata_axi_s2_o59; + output fabric_fpga_wdata_axi_s2_o6; + output fabric_fpga_wdata_axi_s2_o60; + output fabric_fpga_wdata_axi_s2_o61; + output fabric_fpga_wdata_axi_s2_o62; + output fabric_fpga_wdata_axi_s2_o63; + output fabric_fpga_wdata_axi_s2_o64; + output fabric_fpga_wdata_axi_s2_o65; + output fabric_fpga_wdata_axi_s2_o66; + output fabric_fpga_wdata_axi_s2_o67; + output fabric_fpga_wdata_axi_s2_o68; + output fabric_fpga_wdata_axi_s2_o69; + output fabric_fpga_wdata_axi_s2_o7; + output fabric_fpga_wdata_axi_s2_o70; + output fabric_fpga_wdata_axi_s2_o71; + output fabric_fpga_wdata_axi_s2_o72; + output fabric_fpga_wdata_axi_s2_o73; + output fabric_fpga_wdata_axi_s2_o74; + output fabric_fpga_wdata_axi_s2_o75; + output fabric_fpga_wdata_axi_s2_o76; + output fabric_fpga_wdata_axi_s2_o77; + output fabric_fpga_wdata_axi_s2_o78; + output fabric_fpga_wdata_axi_s2_o79; + output fabric_fpga_wdata_axi_s2_o8; + output fabric_fpga_wdata_axi_s2_o80; + output fabric_fpga_wdata_axi_s2_o81; + output fabric_fpga_wdata_axi_s2_o82; + output fabric_fpga_wdata_axi_s2_o83; + output fabric_fpga_wdata_axi_s2_o84; + output fabric_fpga_wdata_axi_s2_o85; + output fabric_fpga_wdata_axi_s2_o86; + output fabric_fpga_wdata_axi_s2_o87; + output fabric_fpga_wdata_axi_s2_o88; + output fabric_fpga_wdata_axi_s2_o89; + output fabric_fpga_wdata_axi_s2_o9; + output fabric_fpga_wdata_axi_s2_o90; + output fabric_fpga_wdata_axi_s2_o91; + output fabric_fpga_wdata_axi_s2_o92; + output fabric_fpga_wdata_axi_s2_o93; + output fabric_fpga_wdata_axi_s2_o94; + output fabric_fpga_wdata_axi_s2_o95; + output fabric_fpga_wdata_axi_s2_o96; + output fabric_fpga_wdata_axi_s2_o97; + output fabric_fpga_wdata_axi_s2_o98; + output fabric_fpga_wdata_axi_s2_o99; + input fabric_fpga_wlast_axi_m1_i; + input fabric_fpga_wlast_axi_m2_i; + output fabric_fpga_wlast_axi_s1_o; + output fabric_fpga_wlast_axi_s2_o; + output fabric_fpga_wready_axi_m1_o; + output fabric_fpga_wready_axi_m2_o; + input fabric_fpga_wready_axi_s1_i; + input fabric_fpga_wready_axi_s2_i; + input fabric_fpga_wstrb_axi_m1_i1; + input fabric_fpga_wstrb_axi_m1_i10; + input fabric_fpga_wstrb_axi_m1_i11; + input fabric_fpga_wstrb_axi_m1_i12; + input fabric_fpga_wstrb_axi_m1_i13; + input fabric_fpga_wstrb_axi_m1_i14; + input fabric_fpga_wstrb_axi_m1_i15; + input fabric_fpga_wstrb_axi_m1_i16; + input fabric_fpga_wstrb_axi_m1_i2; + input fabric_fpga_wstrb_axi_m1_i3; + input fabric_fpga_wstrb_axi_m1_i4; + input fabric_fpga_wstrb_axi_m1_i5; + input fabric_fpga_wstrb_axi_m1_i6; + input fabric_fpga_wstrb_axi_m1_i7; + input fabric_fpga_wstrb_axi_m1_i8; + input fabric_fpga_wstrb_axi_m1_i9; + input fabric_fpga_wstrb_axi_m2_i1; + input fabric_fpga_wstrb_axi_m2_i10; + input fabric_fpga_wstrb_axi_m2_i11; + input fabric_fpga_wstrb_axi_m2_i12; + input fabric_fpga_wstrb_axi_m2_i13; + input fabric_fpga_wstrb_axi_m2_i14; + input fabric_fpga_wstrb_axi_m2_i15; + input fabric_fpga_wstrb_axi_m2_i16; + input fabric_fpga_wstrb_axi_m2_i2; + input fabric_fpga_wstrb_axi_m2_i3; + input fabric_fpga_wstrb_axi_m2_i4; + input fabric_fpga_wstrb_axi_m2_i5; + input fabric_fpga_wstrb_axi_m2_i6; + input fabric_fpga_wstrb_axi_m2_i7; + input fabric_fpga_wstrb_axi_m2_i8; + input fabric_fpga_wstrb_axi_m2_i9; + output fabric_fpga_wstrb_axi_s1_o1; + output fabric_fpga_wstrb_axi_s1_o10; + output fabric_fpga_wstrb_axi_s1_o11; + output fabric_fpga_wstrb_axi_s1_o12; + output fabric_fpga_wstrb_axi_s1_o13; + output fabric_fpga_wstrb_axi_s1_o14; + output fabric_fpga_wstrb_axi_s1_o15; + output fabric_fpga_wstrb_axi_s1_o16; + output fabric_fpga_wstrb_axi_s1_o2; + output fabric_fpga_wstrb_axi_s1_o3; + output fabric_fpga_wstrb_axi_s1_o4; + output fabric_fpga_wstrb_axi_s1_o5; + output fabric_fpga_wstrb_axi_s1_o6; + output fabric_fpga_wstrb_axi_s1_o7; + output fabric_fpga_wstrb_axi_s1_o8; + output fabric_fpga_wstrb_axi_s1_o9; + output fabric_fpga_wstrb_axi_s2_o1; + output fabric_fpga_wstrb_axi_s2_o10; + output fabric_fpga_wstrb_axi_s2_o11; + output fabric_fpga_wstrb_axi_s2_o12; + output fabric_fpga_wstrb_axi_s2_o13; + output fabric_fpga_wstrb_axi_s2_o14; + output fabric_fpga_wstrb_axi_s2_o15; + output fabric_fpga_wstrb_axi_s2_o16; + output fabric_fpga_wstrb_axi_s2_o2; + output fabric_fpga_wstrb_axi_s2_o3; + output fabric_fpga_wstrb_axi_s2_o4; + output fabric_fpga_wstrb_axi_s2_o5; + output fabric_fpga_wstrb_axi_s2_o6; + output fabric_fpga_wstrb_axi_s2_o7; + output fabric_fpga_wstrb_axi_s2_o8; + output fabric_fpga_wstrb_axi_s2_o9; + input fabric_fpga_wvalid_axi_m1_i; + input fabric_fpga_wvalid_axi_m2_i; + output fabric_fpga_wvalid_axi_s1_o; + output fabric_fpga_wvalid_axi_s2_o; + output fabric_llpp0_araddr_s_o1; + output fabric_llpp0_araddr_s_o10; + output fabric_llpp0_araddr_s_o11; + output fabric_llpp0_araddr_s_o12; + output fabric_llpp0_araddr_s_o13; + output fabric_llpp0_araddr_s_o14; + output fabric_llpp0_araddr_s_o15; + output fabric_llpp0_araddr_s_o16; + output fabric_llpp0_araddr_s_o17; + output fabric_llpp0_araddr_s_o18; + output fabric_llpp0_araddr_s_o19; + output fabric_llpp0_araddr_s_o2; + output fabric_llpp0_araddr_s_o20; + output fabric_llpp0_araddr_s_o21; + output fabric_llpp0_araddr_s_o22; + output fabric_llpp0_araddr_s_o23; + output fabric_llpp0_araddr_s_o24; + output fabric_llpp0_araddr_s_o25; + output fabric_llpp0_araddr_s_o26; + output fabric_llpp0_araddr_s_o27; + output fabric_llpp0_araddr_s_o28; + output fabric_llpp0_araddr_s_o29; + output fabric_llpp0_araddr_s_o3; + output fabric_llpp0_araddr_s_o30; + output fabric_llpp0_araddr_s_o31; + output fabric_llpp0_araddr_s_o32; + output fabric_llpp0_araddr_s_o4; + output fabric_llpp0_araddr_s_o5; + output fabric_llpp0_araddr_s_o6; + output fabric_llpp0_araddr_s_o7; + output fabric_llpp0_araddr_s_o8; + output fabric_llpp0_araddr_s_o9; + output fabric_llpp0_arburst_s_o1; + output fabric_llpp0_arburst_s_o2; + output fabric_llpp0_arcache_s_o1; + output fabric_llpp0_arcache_s_o2; + output fabric_llpp0_arcache_s_o3; + output fabric_llpp0_arcache_s_o4; + output fabric_llpp0_arid_s_o1; + output fabric_llpp0_arid_s_o10; + output fabric_llpp0_arid_s_o11; + output fabric_llpp0_arid_s_o12; + output fabric_llpp0_arid_s_o2; + output fabric_llpp0_arid_s_o3; + output fabric_llpp0_arid_s_o4; + output fabric_llpp0_arid_s_o5; + output fabric_llpp0_arid_s_o6; + output fabric_llpp0_arid_s_o7; + output fabric_llpp0_arid_s_o8; + output fabric_llpp0_arid_s_o9; + output fabric_llpp0_arlen_s_o1; + output fabric_llpp0_arlen_s_o2; + output fabric_llpp0_arlen_s_o3; + output fabric_llpp0_arlen_s_o4; + output fabric_llpp0_arlen_s_o5; + output fabric_llpp0_arlen_s_o6; + output fabric_llpp0_arlen_s_o7; + output fabric_llpp0_arlen_s_o8; + output fabric_llpp0_arlock_s_o; + output fabric_llpp0_arprot_s_o1; + output fabric_llpp0_arprot_s_o2; + output fabric_llpp0_arprot_s_o3; + output fabric_llpp0_arqos_s_o1; + output fabric_llpp0_arqos_s_o2; + output fabric_llpp0_arqos_s_o3; + output fabric_llpp0_arqos_s_o4; + input fabric_llpp0_arready_s_i; + output fabric_llpp0_arsize_s_o1; + output fabric_llpp0_arsize_s_o2; + output fabric_llpp0_arsize_s_o3; + output fabric_llpp0_arvalid_s_o; + output fabric_llpp0_awaddr_s_o1; + output fabric_llpp0_awaddr_s_o10; + output fabric_llpp0_awaddr_s_o11; + output fabric_llpp0_awaddr_s_o12; + output fabric_llpp0_awaddr_s_o13; + output fabric_llpp0_awaddr_s_o14; + output fabric_llpp0_awaddr_s_o15; + output fabric_llpp0_awaddr_s_o16; + output fabric_llpp0_awaddr_s_o17; + output fabric_llpp0_awaddr_s_o18; + output fabric_llpp0_awaddr_s_o19; + output fabric_llpp0_awaddr_s_o2; + output fabric_llpp0_awaddr_s_o20; + output fabric_llpp0_awaddr_s_o21; + output fabric_llpp0_awaddr_s_o22; + output fabric_llpp0_awaddr_s_o23; + output fabric_llpp0_awaddr_s_o24; + output fabric_llpp0_awaddr_s_o25; + output fabric_llpp0_awaddr_s_o26; + output fabric_llpp0_awaddr_s_o27; + output fabric_llpp0_awaddr_s_o28; + output fabric_llpp0_awaddr_s_o29; + output fabric_llpp0_awaddr_s_o3; + output fabric_llpp0_awaddr_s_o30; + output fabric_llpp0_awaddr_s_o31; + output fabric_llpp0_awaddr_s_o32; + output fabric_llpp0_awaddr_s_o4; + output fabric_llpp0_awaddr_s_o5; + output fabric_llpp0_awaddr_s_o6; + output fabric_llpp0_awaddr_s_o7; + output fabric_llpp0_awaddr_s_o8; + output fabric_llpp0_awaddr_s_o9; + output fabric_llpp0_awburst_s_o1; + output fabric_llpp0_awburst_s_o2; + output fabric_llpp0_awcache_s_o1; + output fabric_llpp0_awcache_s_o2; + output fabric_llpp0_awcache_s_o3; + output fabric_llpp0_awcache_s_o4; + output fabric_llpp0_awid_s_o1; + output fabric_llpp0_awid_s_o10; + output fabric_llpp0_awid_s_o11; + output fabric_llpp0_awid_s_o12; + output fabric_llpp0_awid_s_o2; + output fabric_llpp0_awid_s_o3; + output fabric_llpp0_awid_s_o4; + output fabric_llpp0_awid_s_o5; + output fabric_llpp0_awid_s_o6; + output fabric_llpp0_awid_s_o7; + output fabric_llpp0_awid_s_o8; + output fabric_llpp0_awid_s_o9; + output fabric_llpp0_awlen_s_o1; + output fabric_llpp0_awlen_s_o2; + output fabric_llpp0_awlen_s_o3; + output fabric_llpp0_awlen_s_o4; + output fabric_llpp0_awlen_s_o5; + output fabric_llpp0_awlen_s_o6; + output fabric_llpp0_awlen_s_o7; + output fabric_llpp0_awlen_s_o8; + output fabric_llpp0_awlock_s_o; + output fabric_llpp0_awprot_s_o1; + output fabric_llpp0_awprot_s_o2; + output fabric_llpp0_awprot_s_o3; + output fabric_llpp0_awqos_s_o1; + output fabric_llpp0_awqos_s_o2; + output fabric_llpp0_awqos_s_o3; + output fabric_llpp0_awqos_s_o4; + input fabric_llpp0_awready_s_i; + output fabric_llpp0_awsize_s_o1; + output fabric_llpp0_awsize_s_o2; + output fabric_llpp0_awsize_s_o3; + output fabric_llpp0_awvalid_s_o; + input fabric_llpp0_bid_s_i1; + input fabric_llpp0_bid_s_i10; + input fabric_llpp0_bid_s_i11; + input fabric_llpp0_bid_s_i12; + input fabric_llpp0_bid_s_i2; + input fabric_llpp0_bid_s_i3; + input fabric_llpp0_bid_s_i4; + input fabric_llpp0_bid_s_i5; + input fabric_llpp0_bid_s_i6; + input fabric_llpp0_bid_s_i7; + input fabric_llpp0_bid_s_i8; + input fabric_llpp0_bid_s_i9; + output fabric_llpp0_bready_s_o; + input fabric_llpp0_bresp_s_i1; + input fabric_llpp0_bresp_s_i2; + input fabric_llpp0_bvalid_s_i; + input fabric_llpp0_rdata_s_i1; + input fabric_llpp0_rdata_s_i10; + input fabric_llpp0_rdata_s_i11; + input fabric_llpp0_rdata_s_i12; + input fabric_llpp0_rdata_s_i13; + input fabric_llpp0_rdata_s_i14; + input fabric_llpp0_rdata_s_i15; + input fabric_llpp0_rdata_s_i16; + input fabric_llpp0_rdata_s_i17; + input fabric_llpp0_rdata_s_i18; + input fabric_llpp0_rdata_s_i19; + input fabric_llpp0_rdata_s_i2; + input fabric_llpp0_rdata_s_i20; + input fabric_llpp0_rdata_s_i21; + input fabric_llpp0_rdata_s_i22; + input fabric_llpp0_rdata_s_i23; + input fabric_llpp0_rdata_s_i24; + input fabric_llpp0_rdata_s_i25; + input fabric_llpp0_rdata_s_i26; + input fabric_llpp0_rdata_s_i27; + input fabric_llpp0_rdata_s_i28; + input fabric_llpp0_rdata_s_i29; + input fabric_llpp0_rdata_s_i3; + input fabric_llpp0_rdata_s_i30; + input fabric_llpp0_rdata_s_i31; + input fabric_llpp0_rdata_s_i32; + input fabric_llpp0_rdata_s_i4; + input fabric_llpp0_rdata_s_i5; + input fabric_llpp0_rdata_s_i6; + input fabric_llpp0_rdata_s_i7; + input fabric_llpp0_rdata_s_i8; + input fabric_llpp0_rdata_s_i9; + input fabric_llpp0_rid_s_i1; + input fabric_llpp0_rid_s_i10; + input fabric_llpp0_rid_s_i11; + input fabric_llpp0_rid_s_i12; + input fabric_llpp0_rid_s_i2; + input fabric_llpp0_rid_s_i3; + input fabric_llpp0_rid_s_i4; + input fabric_llpp0_rid_s_i5; + input fabric_llpp0_rid_s_i6; + input fabric_llpp0_rid_s_i7; + input fabric_llpp0_rid_s_i8; + input fabric_llpp0_rid_s_i9; + input fabric_llpp0_rlast_s_i; + output fabric_llpp0_rready_s_o; + input fabric_llpp0_rresp_s_i1; + input fabric_llpp0_rresp_s_i2; + input fabric_llpp0_rvalid_s_i; + output fabric_llpp0_wdata_s_o1; + output fabric_llpp0_wdata_s_o10; + output fabric_llpp0_wdata_s_o11; + output fabric_llpp0_wdata_s_o12; + output fabric_llpp0_wdata_s_o13; + output fabric_llpp0_wdata_s_o14; + output fabric_llpp0_wdata_s_o15; + output fabric_llpp0_wdata_s_o16; + output fabric_llpp0_wdata_s_o17; + output fabric_llpp0_wdata_s_o18; + output fabric_llpp0_wdata_s_o19; + output fabric_llpp0_wdata_s_o2; + output fabric_llpp0_wdata_s_o20; + output fabric_llpp0_wdata_s_o21; + output fabric_llpp0_wdata_s_o22; + output fabric_llpp0_wdata_s_o23; + output fabric_llpp0_wdata_s_o24; + output fabric_llpp0_wdata_s_o25; + output fabric_llpp0_wdata_s_o26; + output fabric_llpp0_wdata_s_o27; + output fabric_llpp0_wdata_s_o28; + output fabric_llpp0_wdata_s_o29; + output fabric_llpp0_wdata_s_o3; + output fabric_llpp0_wdata_s_o30; + output fabric_llpp0_wdata_s_o31; + output fabric_llpp0_wdata_s_o32; + output fabric_llpp0_wdata_s_o4; + output fabric_llpp0_wdata_s_o5; + output fabric_llpp0_wdata_s_o6; + output fabric_llpp0_wdata_s_o7; + output fabric_llpp0_wdata_s_o8; + output fabric_llpp0_wdata_s_o9; + output fabric_llpp0_wlast_s_o; + input fabric_llpp0_wready_s_i; + output fabric_llpp0_wstrb_s_o1; + output fabric_llpp0_wstrb_s_o2; + output fabric_llpp0_wstrb_s_o3; + output fabric_llpp0_wstrb_s_o4; + output fabric_llpp0_wvalid_s_o; + output fabric_llpp1_araddr_s_o1; + output fabric_llpp1_araddr_s_o10; + output fabric_llpp1_araddr_s_o11; + output fabric_llpp1_araddr_s_o12; + output fabric_llpp1_araddr_s_o13; + output fabric_llpp1_araddr_s_o14; + output fabric_llpp1_araddr_s_o15; + output fabric_llpp1_araddr_s_o16; + output fabric_llpp1_araddr_s_o17; + output fabric_llpp1_araddr_s_o18; + output fabric_llpp1_araddr_s_o19; + output fabric_llpp1_araddr_s_o2; + output fabric_llpp1_araddr_s_o20; + output fabric_llpp1_araddr_s_o21; + output fabric_llpp1_araddr_s_o22; + output fabric_llpp1_araddr_s_o23; + output fabric_llpp1_araddr_s_o24; + output fabric_llpp1_araddr_s_o25; + output fabric_llpp1_araddr_s_o26; + output fabric_llpp1_araddr_s_o27; + output fabric_llpp1_araddr_s_o28; + output fabric_llpp1_araddr_s_o29; + output fabric_llpp1_araddr_s_o3; + output fabric_llpp1_araddr_s_o30; + output fabric_llpp1_araddr_s_o31; + output fabric_llpp1_araddr_s_o32; + output fabric_llpp1_araddr_s_o4; + output fabric_llpp1_araddr_s_o5; + output fabric_llpp1_araddr_s_o6; + output fabric_llpp1_araddr_s_o7; + output fabric_llpp1_araddr_s_o8; + output fabric_llpp1_araddr_s_o9; + output fabric_llpp1_arburst_s_o1; + output fabric_llpp1_arburst_s_o2; + output fabric_llpp1_arcache_s_o1; + output fabric_llpp1_arcache_s_o2; + output fabric_llpp1_arcache_s_o3; + output fabric_llpp1_arcache_s_o4; + output fabric_llpp1_arid_s_o1; + output fabric_llpp1_arid_s_o10; + output fabric_llpp1_arid_s_o11; + output fabric_llpp1_arid_s_o12; + output fabric_llpp1_arid_s_o2; + output fabric_llpp1_arid_s_o3; + output fabric_llpp1_arid_s_o4; + output fabric_llpp1_arid_s_o5; + output fabric_llpp1_arid_s_o6; + output fabric_llpp1_arid_s_o7; + output fabric_llpp1_arid_s_o8; + output fabric_llpp1_arid_s_o9; + output fabric_llpp1_arlen_s_o1; + output fabric_llpp1_arlen_s_o2; + output fabric_llpp1_arlen_s_o3; + output fabric_llpp1_arlen_s_o4; + output fabric_llpp1_arlen_s_o5; + output fabric_llpp1_arlen_s_o6; + output fabric_llpp1_arlen_s_o7; + output fabric_llpp1_arlen_s_o8; + output fabric_llpp1_arlock_s_o; + output fabric_llpp1_arprot_s_o1; + output fabric_llpp1_arprot_s_o2; + output fabric_llpp1_arprot_s_o3; + output fabric_llpp1_arqos_s1_o1; + output fabric_llpp1_arqos_s1_o2; + output fabric_llpp1_arqos_s1_o3; + output fabric_llpp1_arqos_s1_o4; + input fabric_llpp1_arready_s_i; + output fabric_llpp1_arsize_s_o1; + output fabric_llpp1_arsize_s_o2; + output fabric_llpp1_arsize_s_o3; + output fabric_llpp1_arvalid_s_o; + output fabric_llpp1_awaddr_s_o1; + output fabric_llpp1_awaddr_s_o10; + output fabric_llpp1_awaddr_s_o11; + output fabric_llpp1_awaddr_s_o12; + output fabric_llpp1_awaddr_s_o13; + output fabric_llpp1_awaddr_s_o14; + output fabric_llpp1_awaddr_s_o15; + output fabric_llpp1_awaddr_s_o16; + output fabric_llpp1_awaddr_s_o17; + output fabric_llpp1_awaddr_s_o18; + output fabric_llpp1_awaddr_s_o19; + output fabric_llpp1_awaddr_s_o2; + output fabric_llpp1_awaddr_s_o20; + output fabric_llpp1_awaddr_s_o21; + output fabric_llpp1_awaddr_s_o22; + output fabric_llpp1_awaddr_s_o23; + output fabric_llpp1_awaddr_s_o24; + output fabric_llpp1_awaddr_s_o25; + output fabric_llpp1_awaddr_s_o26; + output fabric_llpp1_awaddr_s_o27; + output fabric_llpp1_awaddr_s_o28; + output fabric_llpp1_awaddr_s_o29; + output fabric_llpp1_awaddr_s_o3; + output fabric_llpp1_awaddr_s_o30; + output fabric_llpp1_awaddr_s_o31; + output fabric_llpp1_awaddr_s_o32; + output fabric_llpp1_awaddr_s_o4; + output fabric_llpp1_awaddr_s_o5; + output fabric_llpp1_awaddr_s_o6; + output fabric_llpp1_awaddr_s_o7; + output fabric_llpp1_awaddr_s_o8; + output fabric_llpp1_awaddr_s_o9; + output fabric_llpp1_awburst_s_o1; + output fabric_llpp1_awburst_s_o2; + output fabric_llpp1_awcache_s_o1; + output fabric_llpp1_awcache_s_o2; + output fabric_llpp1_awcache_s_o3; + output fabric_llpp1_awcache_s_o4; + output fabric_llpp1_awid_s_o1; + output fabric_llpp1_awid_s_o10; + output fabric_llpp1_awid_s_o11; + output fabric_llpp1_awid_s_o12; + output fabric_llpp1_awid_s_o2; + output fabric_llpp1_awid_s_o3; + output fabric_llpp1_awid_s_o4; + output fabric_llpp1_awid_s_o5; + output fabric_llpp1_awid_s_o6; + output fabric_llpp1_awid_s_o7; + output fabric_llpp1_awid_s_o8; + output fabric_llpp1_awid_s_o9; + output fabric_llpp1_awlen_s_o1; + output fabric_llpp1_awlen_s_o2; + output fabric_llpp1_awlen_s_o3; + output fabric_llpp1_awlen_s_o4; + output fabric_llpp1_awlen_s_o5; + output fabric_llpp1_awlen_s_o6; + output fabric_llpp1_awlen_s_o7; + output fabric_llpp1_awlen_s_o8; + output fabric_llpp1_awlock_s_o; + output fabric_llpp1_awprot_s_o1; + output fabric_llpp1_awprot_s_o2; + output fabric_llpp1_awprot_s_o3; + output fabric_llpp1_awqos_s_o1; + output fabric_llpp1_awqos_s_o2; + output fabric_llpp1_awqos_s_o3; + output fabric_llpp1_awqos_s_o4; + input fabric_llpp1_awready_s_i; + output fabric_llpp1_awsize_s_o1; + output fabric_llpp1_awsize_s_o2; + output fabric_llpp1_awsize_s_o3; + output fabric_llpp1_awvalid_s_o; + input fabric_llpp1_bid_s_i1; + input fabric_llpp1_bid_s_i10; + input fabric_llpp1_bid_s_i11; + input fabric_llpp1_bid_s_i12; + input fabric_llpp1_bid_s_i2; + input fabric_llpp1_bid_s_i3; + input fabric_llpp1_bid_s_i4; + input fabric_llpp1_bid_s_i5; + input fabric_llpp1_bid_s_i6; + input fabric_llpp1_bid_s_i7; + input fabric_llpp1_bid_s_i8; + input fabric_llpp1_bid_s_i9; + output fabric_llpp1_bready_s_o; + input fabric_llpp1_bresp_s_i1; + input fabric_llpp1_bresp_s_i2; + input fabric_llpp1_bvalid_s_i; + input fabric_llpp1_rdata_s_i1; + input fabric_llpp1_rdata_s_i10; + input fabric_llpp1_rdata_s_i11; + input fabric_llpp1_rdata_s_i12; + input fabric_llpp1_rdata_s_i13; + input fabric_llpp1_rdata_s_i14; + input fabric_llpp1_rdata_s_i15; + input fabric_llpp1_rdata_s_i16; + input fabric_llpp1_rdata_s_i17; + input fabric_llpp1_rdata_s_i18; + input fabric_llpp1_rdata_s_i19; + input fabric_llpp1_rdata_s_i2; + input fabric_llpp1_rdata_s_i20; + input fabric_llpp1_rdata_s_i21; + input fabric_llpp1_rdata_s_i22; + input fabric_llpp1_rdata_s_i23; + input fabric_llpp1_rdata_s_i24; + input fabric_llpp1_rdata_s_i25; + input fabric_llpp1_rdata_s_i26; + input fabric_llpp1_rdata_s_i27; + input fabric_llpp1_rdata_s_i28; + input fabric_llpp1_rdata_s_i29; + input fabric_llpp1_rdata_s_i3; + input fabric_llpp1_rdata_s_i30; + input fabric_llpp1_rdata_s_i31; + input fabric_llpp1_rdata_s_i32; + input fabric_llpp1_rdata_s_i4; + input fabric_llpp1_rdata_s_i5; + input fabric_llpp1_rdata_s_i6; + input fabric_llpp1_rdata_s_i7; + input fabric_llpp1_rdata_s_i8; + input fabric_llpp1_rdata_s_i9; + input fabric_llpp1_rid_s_i1; + input fabric_llpp1_rid_s_i10; + input fabric_llpp1_rid_s_i11; + input fabric_llpp1_rid_s_i12; + input fabric_llpp1_rid_s_i2; + input fabric_llpp1_rid_s_i3; + input fabric_llpp1_rid_s_i4; + input fabric_llpp1_rid_s_i5; + input fabric_llpp1_rid_s_i6; + input fabric_llpp1_rid_s_i7; + input fabric_llpp1_rid_s_i8; + input fabric_llpp1_rid_s_i9; + input fabric_llpp1_rlast_s_i; + output fabric_llpp1_rready_s_o; + input fabric_llpp1_rresp_s_i1; + input fabric_llpp1_rresp_s_i2; + input fabric_llpp1_rvalid_s_i; + output fabric_llpp1_wdata_s_o1; + output fabric_llpp1_wdata_s_o10; + output fabric_llpp1_wdata_s_o11; + output fabric_llpp1_wdata_s_o12; + output fabric_llpp1_wdata_s_o13; + output fabric_llpp1_wdata_s_o14; + output fabric_llpp1_wdata_s_o15; + output fabric_llpp1_wdata_s_o16; + output fabric_llpp1_wdata_s_o17; + output fabric_llpp1_wdata_s_o18; + output fabric_llpp1_wdata_s_o19; + output fabric_llpp1_wdata_s_o2; + output fabric_llpp1_wdata_s_o20; + output fabric_llpp1_wdata_s_o21; + output fabric_llpp1_wdata_s_o22; + output fabric_llpp1_wdata_s_o23; + output fabric_llpp1_wdata_s_o24; + output fabric_llpp1_wdata_s_o25; + output fabric_llpp1_wdata_s_o26; + output fabric_llpp1_wdata_s_o27; + output fabric_llpp1_wdata_s_o28; + output fabric_llpp1_wdata_s_o29; + output fabric_llpp1_wdata_s_o3; + output fabric_llpp1_wdata_s_o30; + output fabric_llpp1_wdata_s_o31; + output fabric_llpp1_wdata_s_o32; + output fabric_llpp1_wdata_s_o4; + output fabric_llpp1_wdata_s_o5; + output fabric_llpp1_wdata_s_o6; + output fabric_llpp1_wdata_s_o7; + output fabric_llpp1_wdata_s_o8; + output fabric_llpp1_wdata_s_o9; + output fabric_llpp1_wlast_s_o; + input fabric_llpp1_wready_s_i; + output fabric_llpp1_wstrb_s_o1; + output fabric_llpp1_wstrb_s_o2; + output fabric_llpp1_wstrb_s_o3; + output fabric_llpp1_wstrb_s_o4; + output fabric_llpp1_wvalid_s_o; + output fabric_llpp2_araddr_s_o1; + output fabric_llpp2_araddr_s_o10; + output fabric_llpp2_araddr_s_o11; + output fabric_llpp2_araddr_s_o12; + output fabric_llpp2_araddr_s_o13; + output fabric_llpp2_araddr_s_o14; + output fabric_llpp2_araddr_s_o15; + output fabric_llpp2_araddr_s_o16; + output fabric_llpp2_araddr_s_o17; + output fabric_llpp2_araddr_s_o18; + output fabric_llpp2_araddr_s_o19; + output fabric_llpp2_araddr_s_o2; + output fabric_llpp2_araddr_s_o20; + output fabric_llpp2_araddr_s_o21; + output fabric_llpp2_araddr_s_o22; + output fabric_llpp2_araddr_s_o23; + output fabric_llpp2_araddr_s_o24; + output fabric_llpp2_araddr_s_o25; + output fabric_llpp2_araddr_s_o26; + output fabric_llpp2_araddr_s_o27; + output fabric_llpp2_araddr_s_o28; + output fabric_llpp2_araddr_s_o29; + output fabric_llpp2_araddr_s_o3; + output fabric_llpp2_araddr_s_o30; + output fabric_llpp2_araddr_s_o31; + output fabric_llpp2_araddr_s_o32; + output fabric_llpp2_araddr_s_o4; + output fabric_llpp2_araddr_s_o5; + output fabric_llpp2_araddr_s_o6; + output fabric_llpp2_araddr_s_o7; + output fabric_llpp2_araddr_s_o8; + output fabric_llpp2_araddr_s_o9; + output fabric_llpp2_arburst_s_o1; + output fabric_llpp2_arburst_s_o2; + output fabric_llpp2_arcache_s_o1; + output fabric_llpp2_arcache_s_o2; + output fabric_llpp2_arcache_s_o3; + output fabric_llpp2_arcache_s_o4; + output fabric_llpp2_arid_s_o1; + output fabric_llpp2_arid_s_o10; + output fabric_llpp2_arid_s_o11; + output fabric_llpp2_arid_s_o12; + output fabric_llpp2_arid_s_o2; + output fabric_llpp2_arid_s_o3; + output fabric_llpp2_arid_s_o4; + output fabric_llpp2_arid_s_o5; + output fabric_llpp2_arid_s_o6; + output fabric_llpp2_arid_s_o7; + output fabric_llpp2_arid_s_o8; + output fabric_llpp2_arid_s_o9; + output fabric_llpp2_arlen_s_o1; + output fabric_llpp2_arlen_s_o2; + output fabric_llpp2_arlen_s_o3; + output fabric_llpp2_arlen_s_o4; + output fabric_llpp2_arlen_s_o5; + output fabric_llpp2_arlen_s_o6; + output fabric_llpp2_arlen_s_o7; + output fabric_llpp2_arlen_s_o8; + output fabric_llpp2_arlock_s_o; + output fabric_llpp2_arprot_s_o1; + output fabric_llpp2_arprot_s_o2; + output fabric_llpp2_arprot_s_o3; + output fabric_llpp2_arqos_s_o1; + output fabric_llpp2_arqos_s_o2; + output fabric_llpp2_arqos_s_o3; + output fabric_llpp2_arqos_s_o4; + input fabric_llpp2_arready_s_i; + output fabric_llpp2_arsize_s_o1; + output fabric_llpp2_arsize_s_o2; + output fabric_llpp2_arsize_s_o3; + output fabric_llpp2_arvalid_s_o; + output fabric_llpp2_awaddr_s_o1; + output fabric_llpp2_awaddr_s_o10; + output fabric_llpp2_awaddr_s_o11; + output fabric_llpp2_awaddr_s_o12; + output fabric_llpp2_awaddr_s_o13; + output fabric_llpp2_awaddr_s_o14; + output fabric_llpp2_awaddr_s_o15; + output fabric_llpp2_awaddr_s_o16; + output fabric_llpp2_awaddr_s_o17; + output fabric_llpp2_awaddr_s_o18; + output fabric_llpp2_awaddr_s_o19; + output fabric_llpp2_awaddr_s_o2; + output fabric_llpp2_awaddr_s_o20; + output fabric_llpp2_awaddr_s_o21; + output fabric_llpp2_awaddr_s_o22; + output fabric_llpp2_awaddr_s_o23; + output fabric_llpp2_awaddr_s_o24; + output fabric_llpp2_awaddr_s_o25; + output fabric_llpp2_awaddr_s_o26; + output fabric_llpp2_awaddr_s_o27; + output fabric_llpp2_awaddr_s_o28; + output fabric_llpp2_awaddr_s_o29; + output fabric_llpp2_awaddr_s_o3; + output fabric_llpp2_awaddr_s_o30; + output fabric_llpp2_awaddr_s_o31; + output fabric_llpp2_awaddr_s_o32; + output fabric_llpp2_awaddr_s_o4; + output fabric_llpp2_awaddr_s_o5; + output fabric_llpp2_awaddr_s_o6; + output fabric_llpp2_awaddr_s_o7; + output fabric_llpp2_awaddr_s_o8; + output fabric_llpp2_awaddr_s_o9; + output fabric_llpp2_awburst_s_o1; + output fabric_llpp2_awburst_s_o2; + output fabric_llpp2_awcache_s_o1; + output fabric_llpp2_awcache_s_o2; + output fabric_llpp2_awcache_s_o3; + output fabric_llpp2_awcache_s_o4; + output fabric_llpp2_awid_s_o1; + output fabric_llpp2_awid_s_o10; + output fabric_llpp2_awid_s_o11; + output fabric_llpp2_awid_s_o12; + output fabric_llpp2_awid_s_o2; + output fabric_llpp2_awid_s_o3; + output fabric_llpp2_awid_s_o4; + output fabric_llpp2_awid_s_o5; + output fabric_llpp2_awid_s_o6; + output fabric_llpp2_awid_s_o7; + output fabric_llpp2_awid_s_o8; + output fabric_llpp2_awid_s_o9; + output fabric_llpp2_awlen_s_o1; + output fabric_llpp2_awlen_s_o2; + output fabric_llpp2_awlen_s_o3; + output fabric_llpp2_awlen_s_o4; + output fabric_llpp2_awlen_s_o5; + output fabric_llpp2_awlen_s_o6; + output fabric_llpp2_awlen_s_o7; + output fabric_llpp2_awlen_s_o8; + output fabric_llpp2_awlock_s_o; + output fabric_llpp2_awprot_s_o1; + output fabric_llpp2_awprot_s_o2; + output fabric_llpp2_awprot_s_o3; + output fabric_llpp2_awqos_s_o1; + output fabric_llpp2_awqos_s_o2; + output fabric_llpp2_awqos_s_o3; + output fabric_llpp2_awqos_s_o4; + input fabric_llpp2_awready_s_i; + output fabric_llpp2_awsize_s_o1; + output fabric_llpp2_awsize_s_o2; + output fabric_llpp2_awsize_s_o3; + output fabric_llpp2_awvalid_s_o; + input fabric_llpp2_bid_s_i1; + input fabric_llpp2_bid_s_i10; + input fabric_llpp2_bid_s_i11; + input fabric_llpp2_bid_s_i12; + input fabric_llpp2_bid_s_i2; + input fabric_llpp2_bid_s_i3; + input fabric_llpp2_bid_s_i4; + input fabric_llpp2_bid_s_i5; + input fabric_llpp2_bid_s_i6; + input fabric_llpp2_bid_s_i7; + input fabric_llpp2_bid_s_i8; + input fabric_llpp2_bid_s_i9; + output fabric_llpp2_bready_s_o; + input fabric_llpp2_bresp_s_i1; + input fabric_llpp2_bresp_s_i2; + input fabric_llpp2_bvalid_s_i; + input fabric_llpp2_rdata_s_i1; + input fabric_llpp2_rdata_s_i10; + input fabric_llpp2_rdata_s_i11; + input fabric_llpp2_rdata_s_i12; + input fabric_llpp2_rdata_s_i13; + input fabric_llpp2_rdata_s_i14; + input fabric_llpp2_rdata_s_i15; + input fabric_llpp2_rdata_s_i16; + input fabric_llpp2_rdata_s_i17; + input fabric_llpp2_rdata_s_i18; + input fabric_llpp2_rdata_s_i19; + input fabric_llpp2_rdata_s_i2; + input fabric_llpp2_rdata_s_i20; + input fabric_llpp2_rdata_s_i21; + input fabric_llpp2_rdata_s_i22; + input fabric_llpp2_rdata_s_i23; + input fabric_llpp2_rdata_s_i24; + input fabric_llpp2_rdata_s_i25; + input fabric_llpp2_rdata_s_i26; + input fabric_llpp2_rdata_s_i27; + input fabric_llpp2_rdata_s_i28; + input fabric_llpp2_rdata_s_i29; + input fabric_llpp2_rdata_s_i3; + input fabric_llpp2_rdata_s_i30; + input fabric_llpp2_rdata_s_i31; + input fabric_llpp2_rdata_s_i32; + input fabric_llpp2_rdata_s_i4; + input fabric_llpp2_rdata_s_i5; + input fabric_llpp2_rdata_s_i6; + input fabric_llpp2_rdata_s_i7; + input fabric_llpp2_rdata_s_i8; + input fabric_llpp2_rdata_s_i9; + input fabric_llpp2_rid_s_i1; + input fabric_llpp2_rid_s_i10; + input fabric_llpp2_rid_s_i11; + input fabric_llpp2_rid_s_i12; + input fabric_llpp2_rid_s_i2; + input fabric_llpp2_rid_s_i3; + input fabric_llpp2_rid_s_i4; + input fabric_llpp2_rid_s_i5; + input fabric_llpp2_rid_s_i6; + input fabric_llpp2_rid_s_i7; + input fabric_llpp2_rid_s_i8; + input fabric_llpp2_rid_s_i9; + input fabric_llpp2_rlast_s_i; + output fabric_llpp2_rready_s_o; + input fabric_llpp2_rresp_s_i1; + input fabric_llpp2_rresp_s_i2; + input fabric_llpp2_rvalid_s_i; + output fabric_llpp2_wdata_s_o1; + output fabric_llpp2_wdata_s_o10; + output fabric_llpp2_wdata_s_o11; + output fabric_llpp2_wdata_s_o12; + output fabric_llpp2_wdata_s_o13; + output fabric_llpp2_wdata_s_o14; + output fabric_llpp2_wdata_s_o15; + output fabric_llpp2_wdata_s_o16; + output fabric_llpp2_wdata_s_o17; + output fabric_llpp2_wdata_s_o18; + output fabric_llpp2_wdata_s_o19; + output fabric_llpp2_wdata_s_o2; + output fabric_llpp2_wdata_s_o20; + output fabric_llpp2_wdata_s_o21; + output fabric_llpp2_wdata_s_o22; + output fabric_llpp2_wdata_s_o23; + output fabric_llpp2_wdata_s_o24; + output fabric_llpp2_wdata_s_o25; + output fabric_llpp2_wdata_s_o26; + output fabric_llpp2_wdata_s_o27; + output fabric_llpp2_wdata_s_o28; + output fabric_llpp2_wdata_s_o29; + output fabric_llpp2_wdata_s_o3; + output fabric_llpp2_wdata_s_o30; + output fabric_llpp2_wdata_s_o31; + output fabric_llpp2_wdata_s_o32; + output fabric_llpp2_wdata_s_o4; + output fabric_llpp2_wdata_s_o5; + output fabric_llpp2_wdata_s_o6; + output fabric_llpp2_wdata_s_o7; + output fabric_llpp2_wdata_s_o8; + output fabric_llpp2_wdata_s_o9; + output fabric_llpp2_wlast_s_o; + input fabric_llpp2_wready_s_i; + output fabric_llpp2_wstrb_s_o1; + output fabric_llpp2_wstrb_s_o2; + output fabric_llpp2_wstrb_s_o3; + output fabric_llpp2_wstrb_s_o4; + output fabric_llpp2_wvalid_s_o; + output fabric_llpp3_araddr_s_o1; + output fabric_llpp3_araddr_s_o10; + output fabric_llpp3_araddr_s_o11; + output fabric_llpp3_araddr_s_o12; + output fabric_llpp3_araddr_s_o13; + output fabric_llpp3_araddr_s_o14; + output fabric_llpp3_araddr_s_o15; + output fabric_llpp3_araddr_s_o16; + output fabric_llpp3_araddr_s_o17; + output fabric_llpp3_araddr_s_o18; + output fabric_llpp3_araddr_s_o19; + output fabric_llpp3_araddr_s_o2; + output fabric_llpp3_araddr_s_o20; + output fabric_llpp3_araddr_s_o21; + output fabric_llpp3_araddr_s_o22; + output fabric_llpp3_araddr_s_o23; + output fabric_llpp3_araddr_s_o24; + output fabric_llpp3_araddr_s_o25; + output fabric_llpp3_araddr_s_o26; + output fabric_llpp3_araddr_s_o27; + output fabric_llpp3_araddr_s_o28; + output fabric_llpp3_araddr_s_o29; + output fabric_llpp3_araddr_s_o3; + output fabric_llpp3_araddr_s_o30; + output fabric_llpp3_araddr_s_o31; + output fabric_llpp3_araddr_s_o32; + output fabric_llpp3_araddr_s_o4; + output fabric_llpp3_araddr_s_o5; + output fabric_llpp3_araddr_s_o6; + output fabric_llpp3_araddr_s_o7; + output fabric_llpp3_araddr_s_o8; + output fabric_llpp3_araddr_s_o9; + output fabric_llpp3_arburst_s_o1; + output fabric_llpp3_arburst_s_o2; + output fabric_llpp3_arcache_s_o1; + output fabric_llpp3_arcache_s_o2; + output fabric_llpp3_arcache_s_o3; + output fabric_llpp3_arcache_s_o4; + output fabric_llpp3_arid_s_o1; + output fabric_llpp3_arid_s_o10; + output fabric_llpp3_arid_s_o11; + output fabric_llpp3_arid_s_o12; + output fabric_llpp3_arid_s_o2; + output fabric_llpp3_arid_s_o3; + output fabric_llpp3_arid_s_o4; + output fabric_llpp3_arid_s_o5; + output fabric_llpp3_arid_s_o6; + output fabric_llpp3_arid_s_o7; + output fabric_llpp3_arid_s_o8; + output fabric_llpp3_arid_s_o9; + output fabric_llpp3_arlen_s_o1; + output fabric_llpp3_arlen_s_o2; + output fabric_llpp3_arlen_s_o3; + output fabric_llpp3_arlen_s_o4; + output fabric_llpp3_arlen_s_o5; + output fabric_llpp3_arlen_s_o6; + output fabric_llpp3_arlen_s_o7; + output fabric_llpp3_arlen_s_o8; + output fabric_llpp3_arlock_s_o; + output fabric_llpp3_arprot_s_o1; + output fabric_llpp3_arprot_s_o2; + output fabric_llpp3_arprot_s_o3; + output fabric_llpp3_arqos_s_o1; + output fabric_llpp3_arqos_s_o2; + output fabric_llpp3_arqos_s_o3; + output fabric_llpp3_arqos_s_o4; + input fabric_llpp3_arready_s_i; + output fabric_llpp3_arsize_s_o1; + output fabric_llpp3_arsize_s_o2; + output fabric_llpp3_arsize_s_o3; + output fabric_llpp3_arvalid_s_o; + output fabric_llpp3_awaddr_s_o1; + output fabric_llpp3_awaddr_s_o10; + output fabric_llpp3_awaddr_s_o11; + output fabric_llpp3_awaddr_s_o12; + output fabric_llpp3_awaddr_s_o13; + output fabric_llpp3_awaddr_s_o14; + output fabric_llpp3_awaddr_s_o15; + output fabric_llpp3_awaddr_s_o16; + output fabric_llpp3_awaddr_s_o17; + output fabric_llpp3_awaddr_s_o18; + output fabric_llpp3_awaddr_s_o19; + output fabric_llpp3_awaddr_s_o2; + output fabric_llpp3_awaddr_s_o20; + output fabric_llpp3_awaddr_s_o21; + output fabric_llpp3_awaddr_s_o22; + output fabric_llpp3_awaddr_s_o23; + output fabric_llpp3_awaddr_s_o24; + output fabric_llpp3_awaddr_s_o25; + output fabric_llpp3_awaddr_s_o26; + output fabric_llpp3_awaddr_s_o27; + output fabric_llpp3_awaddr_s_o28; + output fabric_llpp3_awaddr_s_o29; + output fabric_llpp3_awaddr_s_o3; + output fabric_llpp3_awaddr_s_o30; + output fabric_llpp3_awaddr_s_o31; + output fabric_llpp3_awaddr_s_o32; + output fabric_llpp3_awaddr_s_o4; + output fabric_llpp3_awaddr_s_o5; + output fabric_llpp3_awaddr_s_o6; + output fabric_llpp3_awaddr_s_o7; + output fabric_llpp3_awaddr_s_o8; + output fabric_llpp3_awaddr_s_o9; + output fabric_llpp3_awburst_s_o1; + output fabric_llpp3_awburst_s_o2; + output fabric_llpp3_awcache_s_o1; + output fabric_llpp3_awcache_s_o2; + output fabric_llpp3_awcache_s_o3; + output fabric_llpp3_awcache_s_o4; + output fabric_llpp3_awid_s_o1; + output fabric_llpp3_awid_s_o10; + output fabric_llpp3_awid_s_o11; + output fabric_llpp3_awid_s_o12; + output fabric_llpp3_awid_s_o2; + output fabric_llpp3_awid_s_o3; + output fabric_llpp3_awid_s_o4; + output fabric_llpp3_awid_s_o5; + output fabric_llpp3_awid_s_o6; + output fabric_llpp3_awid_s_o7; + output fabric_llpp3_awid_s_o8; + output fabric_llpp3_awid_s_o9; + output fabric_llpp3_awlen_s_o1; + output fabric_llpp3_awlen_s_o2; + output fabric_llpp3_awlen_s_o3; + output fabric_llpp3_awlen_s_o4; + output fabric_llpp3_awlen_s_o5; + output fabric_llpp3_awlen_s_o6; + output fabric_llpp3_awlen_s_o7; + output fabric_llpp3_awlen_s_o8; + output fabric_llpp3_awlock_s_o; + output fabric_llpp3_awprot_s_o1; + output fabric_llpp3_awprot_s_o2; + output fabric_llpp3_awprot_s_o3; + output fabric_llpp3_awqos_s_o1; + output fabric_llpp3_awqos_s_o2; + output fabric_llpp3_awqos_s_o3; + output fabric_llpp3_awqos_s_o4; + input fabric_llpp3_awready_s_i; + output fabric_llpp3_awsize_s_o1; + output fabric_llpp3_awsize_s_o2; + output fabric_llpp3_awsize_s_o3; + output fabric_llpp3_awvalid_s_o; + input fabric_llpp3_bid_s_i1; + input fabric_llpp3_bid_s_i10; + input fabric_llpp3_bid_s_i11; + input fabric_llpp3_bid_s_i12; + input fabric_llpp3_bid_s_i2; + input fabric_llpp3_bid_s_i3; + input fabric_llpp3_bid_s_i4; + input fabric_llpp3_bid_s_i5; + input fabric_llpp3_bid_s_i6; + input fabric_llpp3_bid_s_i7; + input fabric_llpp3_bid_s_i8; + input fabric_llpp3_bid_s_i9; + output fabric_llpp3_bready_s_o; + input fabric_llpp3_bresp_s_i1; + input fabric_llpp3_bresp_s_i2; + input fabric_llpp3_bvalid_s_i; + input fabric_llpp3_rdata_s_i1; + input fabric_llpp3_rdata_s_i10; + input fabric_llpp3_rdata_s_i11; + input fabric_llpp3_rdata_s_i12; + input fabric_llpp3_rdata_s_i13; + input fabric_llpp3_rdata_s_i14; + input fabric_llpp3_rdata_s_i15; + input fabric_llpp3_rdata_s_i16; + input fabric_llpp3_rdata_s_i17; + input fabric_llpp3_rdata_s_i18; + input fabric_llpp3_rdata_s_i19; + input fabric_llpp3_rdata_s_i2; + input fabric_llpp3_rdata_s_i20; + input fabric_llpp3_rdata_s_i21; + input fabric_llpp3_rdata_s_i22; + input fabric_llpp3_rdata_s_i23; + input fabric_llpp3_rdata_s_i24; + input fabric_llpp3_rdata_s_i25; + input fabric_llpp3_rdata_s_i26; + input fabric_llpp3_rdata_s_i27; + input fabric_llpp3_rdata_s_i28; + input fabric_llpp3_rdata_s_i29; + input fabric_llpp3_rdata_s_i3; + input fabric_llpp3_rdata_s_i30; + input fabric_llpp3_rdata_s_i31; + input fabric_llpp3_rdata_s_i32; + input fabric_llpp3_rdata_s_i4; + input fabric_llpp3_rdata_s_i5; + input fabric_llpp3_rdata_s_i6; + input fabric_llpp3_rdata_s_i7; + input fabric_llpp3_rdata_s_i8; + input fabric_llpp3_rdata_s_i9; + input fabric_llpp3_rid_s_i1; + input fabric_llpp3_rid_s_i10; + input fabric_llpp3_rid_s_i11; + input fabric_llpp3_rid_s_i12; + input fabric_llpp3_rid_s_i2; + input fabric_llpp3_rid_s_i3; + input fabric_llpp3_rid_s_i4; + input fabric_llpp3_rid_s_i5; + input fabric_llpp3_rid_s_i6; + input fabric_llpp3_rid_s_i7; + input fabric_llpp3_rid_s_i8; + input fabric_llpp3_rid_s_i9; + input fabric_llpp3_rlast_s_i; + output fabric_llpp3_rready_s_o; + input fabric_llpp3_rresp_s_i1; + input fabric_llpp3_rresp_s_i2; + input fabric_llpp3_rvalid_s_i; + output fabric_llpp3_wdata_s_o1; + output fabric_llpp3_wdata_s_o10; + output fabric_llpp3_wdata_s_o11; + output fabric_llpp3_wdata_s_o12; + output fabric_llpp3_wdata_s_o13; + output fabric_llpp3_wdata_s_o14; + output fabric_llpp3_wdata_s_o15; + output fabric_llpp3_wdata_s_o16; + output fabric_llpp3_wdata_s_o17; + output fabric_llpp3_wdata_s_o18; + output fabric_llpp3_wdata_s_o19; + output fabric_llpp3_wdata_s_o2; + output fabric_llpp3_wdata_s_o20; + output fabric_llpp3_wdata_s_o21; + output fabric_llpp3_wdata_s_o22; + output fabric_llpp3_wdata_s_o23; + output fabric_llpp3_wdata_s_o24; + output fabric_llpp3_wdata_s_o25; + output fabric_llpp3_wdata_s_o26; + output fabric_llpp3_wdata_s_o27; + output fabric_llpp3_wdata_s_o28; + output fabric_llpp3_wdata_s_o29; + output fabric_llpp3_wdata_s_o3; + output fabric_llpp3_wdata_s_o30; + output fabric_llpp3_wdata_s_o31; + output fabric_llpp3_wdata_s_o32; + output fabric_llpp3_wdata_s_o4; + output fabric_llpp3_wdata_s_o5; + output fabric_llpp3_wdata_s_o6; + output fabric_llpp3_wdata_s_o7; + output fabric_llpp3_wdata_s_o8; + output fabric_llpp3_wdata_s_o9; + output fabric_llpp3_wlast_s_o; + input fabric_llpp3_wready_s_i; + output fabric_llpp3_wstrb_s_o1; + output fabric_llpp3_wstrb_s_o2; + output fabric_llpp3_wstrb_s_o3; + output fabric_llpp3_wstrb_s_o4; + output fabric_llpp3_wvalid_s_o; + input fabric_lowskew_i1; + input fabric_lowskew_i10; + input fabric_lowskew_i2; + input fabric_lowskew_i3; + input fabric_lowskew_i4; + input fabric_lowskew_i5; + input fabric_lowskew_i6; + input fabric_lowskew_i7; + input fabric_lowskew_i8; + input fabric_lowskew_i9; + output fabric_lowskew_o1; + output fabric_lowskew_o2; + input fabric_qos_pclk_i; + input fabric_qos_ppaddr_i1; + input fabric_qos_ppaddr_i10; + input fabric_qos_ppaddr_i11; + input fabric_qos_ppaddr_i12; + input fabric_qos_ppaddr_i13; + input fabric_qos_ppaddr_i14; + input fabric_qos_ppaddr_i15; + input fabric_qos_ppaddr_i16; + input fabric_qos_ppaddr_i17; + input fabric_qos_ppaddr_i18; + input fabric_qos_ppaddr_i19; + input fabric_qos_ppaddr_i2; + input fabric_qos_ppaddr_i20; + input fabric_qos_ppaddr_i21; + input fabric_qos_ppaddr_i22; + input fabric_qos_ppaddr_i23; + input fabric_qos_ppaddr_i24; + input fabric_qos_ppaddr_i25; + input fabric_qos_ppaddr_i26; + input fabric_qos_ppaddr_i27; + input fabric_qos_ppaddr_i28; + input fabric_qos_ppaddr_i29; + input fabric_qos_ppaddr_i3; + input fabric_qos_ppaddr_i30; + input fabric_qos_ppaddr_i31; + input fabric_qos_ppaddr_i32; + input fabric_qos_ppaddr_i4; + input fabric_qos_ppaddr_i5; + input fabric_qos_ppaddr_i6; + input fabric_qos_ppaddr_i7; + input fabric_qos_ppaddr_i8; + input fabric_qos_ppaddr_i9; + input fabric_qos_ppenable_i; + output fabric_qos_pprdata_o1; + output fabric_qos_pprdata_o10; + output fabric_qos_pprdata_o11; + output fabric_qos_pprdata_o12; + output fabric_qos_pprdata_o13; + output fabric_qos_pprdata_o14; + output fabric_qos_pprdata_o15; + output fabric_qos_pprdata_o16; + output fabric_qos_pprdata_o17; + output fabric_qos_pprdata_o18; + output fabric_qos_pprdata_o19; + output fabric_qos_pprdata_o2; + output fabric_qos_pprdata_o20; + output fabric_qos_pprdata_o21; + output fabric_qos_pprdata_o22; + output fabric_qos_pprdata_o23; + output fabric_qos_pprdata_o24; + output fabric_qos_pprdata_o25; + output fabric_qos_pprdata_o26; + output fabric_qos_pprdata_o27; + output fabric_qos_pprdata_o28; + output fabric_qos_pprdata_o29; + output fabric_qos_pprdata_o3; + output fabric_qos_pprdata_o30; + output fabric_qos_pprdata_o31; + output fabric_qos_pprdata_o32; + output fabric_qos_pprdata_o4; + output fabric_qos_pprdata_o5; + output fabric_qos_pprdata_o6; + output fabric_qos_pprdata_o7; + output fabric_qos_pprdata_o8; + output fabric_qos_pprdata_o9; + output fabric_qos_ppready_o; + output fabric_qos_ppslverr_o; + input fabric_qos_ppwdata_i1; + input fabric_qos_ppwdata_i10; + input fabric_qos_ppwdata_i11; + input fabric_qos_ppwdata_i12; + input fabric_qos_ppwdata_i13; + input fabric_qos_ppwdata_i14; + input fabric_qos_ppwdata_i15; + input fabric_qos_ppwdata_i16; + input fabric_qos_ppwdata_i17; + input fabric_qos_ppwdata_i18; + input fabric_qos_ppwdata_i19; + input fabric_qos_ppwdata_i2; + input fabric_qos_ppwdata_i20; + input fabric_qos_ppwdata_i21; + input fabric_qos_ppwdata_i22; + input fabric_qos_ppwdata_i23; + input fabric_qos_ppwdata_i24; + input fabric_qos_ppwdata_i25; + input fabric_qos_ppwdata_i26; + input fabric_qos_ppwdata_i27; + input fabric_qos_ppwdata_i28; + input fabric_qos_ppwdata_i29; + input fabric_qos_ppwdata_i3; + input fabric_qos_ppwdata_i30; + input fabric_qos_ppwdata_i31; + input fabric_qos_ppwdata_i32; + input fabric_qos_ppwdata_i4; + input fabric_qos_ppwdata_i5; + input fabric_qos_ppwdata_i6; + input fabric_qos_ppwdata_i7; + input fabric_qos_ppwdata_i8; + input fabric_qos_ppwdata_i9; + input fabric_qos_ppwrite_i; + input fabric_qos_presetn_i; + input fabric_qos_psel_i; + output fabric_soc_mon_sensor_alarm_o; + input fabric_sysc_hold_on_debug_i; + output fabric_tnd_fpga_apb_master_paddr_o1; + output fabric_tnd_fpga_apb_master_paddr_o10; + output fabric_tnd_fpga_apb_master_paddr_o11; + output fabric_tnd_fpga_apb_master_paddr_o12; + output fabric_tnd_fpga_apb_master_paddr_o13; + output fabric_tnd_fpga_apb_master_paddr_o14; + output fabric_tnd_fpga_apb_master_paddr_o15; + output fabric_tnd_fpga_apb_master_paddr_o16; + output fabric_tnd_fpga_apb_master_paddr_o17; + output fabric_tnd_fpga_apb_master_paddr_o18; + output fabric_tnd_fpga_apb_master_paddr_o19; + output fabric_tnd_fpga_apb_master_paddr_o2; + output fabric_tnd_fpga_apb_master_paddr_o20; + output fabric_tnd_fpga_apb_master_paddr_o21; + output fabric_tnd_fpga_apb_master_paddr_o22; + output fabric_tnd_fpga_apb_master_paddr_o23; + output fabric_tnd_fpga_apb_master_paddr_o24; + output fabric_tnd_fpga_apb_master_paddr_o25; + output fabric_tnd_fpga_apb_master_paddr_o26; + output fabric_tnd_fpga_apb_master_paddr_o27; + output fabric_tnd_fpga_apb_master_paddr_o28; + output fabric_tnd_fpga_apb_master_paddr_o29; + output fabric_tnd_fpga_apb_master_paddr_o3; + output fabric_tnd_fpga_apb_master_paddr_o30; + output fabric_tnd_fpga_apb_master_paddr_o31; + output fabric_tnd_fpga_apb_master_paddr_o32; + output fabric_tnd_fpga_apb_master_paddr_o4; + output fabric_tnd_fpga_apb_master_paddr_o5; + output fabric_tnd_fpga_apb_master_paddr_o6; + output fabric_tnd_fpga_apb_master_paddr_o7; + output fabric_tnd_fpga_apb_master_paddr_o8; + output fabric_tnd_fpga_apb_master_paddr_o9; + output fabric_tnd_fpga_apb_master_penable_o; + input fabric_tnd_fpga_apb_master_prdata_i1; + input fabric_tnd_fpga_apb_master_prdata_i10; + input fabric_tnd_fpga_apb_master_prdata_i11; + input fabric_tnd_fpga_apb_master_prdata_i12; + input fabric_tnd_fpga_apb_master_prdata_i13; + input fabric_tnd_fpga_apb_master_prdata_i14; + input fabric_tnd_fpga_apb_master_prdata_i15; + input fabric_tnd_fpga_apb_master_prdata_i16; + input fabric_tnd_fpga_apb_master_prdata_i17; + input fabric_tnd_fpga_apb_master_prdata_i18; + input fabric_tnd_fpga_apb_master_prdata_i19; + input fabric_tnd_fpga_apb_master_prdata_i2; + input fabric_tnd_fpga_apb_master_prdata_i20; + input fabric_tnd_fpga_apb_master_prdata_i21; + input fabric_tnd_fpga_apb_master_prdata_i22; + input fabric_tnd_fpga_apb_master_prdata_i23; + input fabric_tnd_fpga_apb_master_prdata_i24; + input fabric_tnd_fpga_apb_master_prdata_i25; + input fabric_tnd_fpga_apb_master_prdata_i26; + input fabric_tnd_fpga_apb_master_prdata_i27; + input fabric_tnd_fpga_apb_master_prdata_i28; + input fabric_tnd_fpga_apb_master_prdata_i29; + input fabric_tnd_fpga_apb_master_prdata_i3; + input fabric_tnd_fpga_apb_master_prdata_i30; + input fabric_tnd_fpga_apb_master_prdata_i31; + input fabric_tnd_fpga_apb_master_prdata_i32; + input fabric_tnd_fpga_apb_master_prdata_i4; + input fabric_tnd_fpga_apb_master_prdata_i5; + input fabric_tnd_fpga_apb_master_prdata_i6; + input fabric_tnd_fpga_apb_master_prdata_i7; + input fabric_tnd_fpga_apb_master_prdata_i8; + input fabric_tnd_fpga_apb_master_prdata_i9; + input fabric_tnd_fpga_apb_master_pready_i; + output fabric_tnd_fpga_apb_master_psel_o; + input fabric_tnd_fpga_apb_master_pslverr_i; + output fabric_tnd_fpga_apb_master_pwdata_o1; + output fabric_tnd_fpga_apb_master_pwdata_o10; + output fabric_tnd_fpga_apb_master_pwdata_o11; + output fabric_tnd_fpga_apb_master_pwdata_o12; + output fabric_tnd_fpga_apb_master_pwdata_o13; + output fabric_tnd_fpga_apb_master_pwdata_o14; + output fabric_tnd_fpga_apb_master_pwdata_o15; + output fabric_tnd_fpga_apb_master_pwdata_o16; + output fabric_tnd_fpga_apb_master_pwdata_o17; + output fabric_tnd_fpga_apb_master_pwdata_o18; + output fabric_tnd_fpga_apb_master_pwdata_o19; + output fabric_tnd_fpga_apb_master_pwdata_o2; + output fabric_tnd_fpga_apb_master_pwdata_o20; + output fabric_tnd_fpga_apb_master_pwdata_o21; + output fabric_tnd_fpga_apb_master_pwdata_o22; + output fabric_tnd_fpga_apb_master_pwdata_o23; + output fabric_tnd_fpga_apb_master_pwdata_o24; + output fabric_tnd_fpga_apb_master_pwdata_o25; + output fabric_tnd_fpga_apb_master_pwdata_o26; + output fabric_tnd_fpga_apb_master_pwdata_o27; + output fabric_tnd_fpga_apb_master_pwdata_o28; + output fabric_tnd_fpga_apb_master_pwdata_o29; + output fabric_tnd_fpga_apb_master_pwdata_o3; + output fabric_tnd_fpga_apb_master_pwdata_o30; + output fabric_tnd_fpga_apb_master_pwdata_o31; + output fabric_tnd_fpga_apb_master_pwdata_o32; + output fabric_tnd_fpga_apb_master_pwdata_o4; + output fabric_tnd_fpga_apb_master_pwdata_o5; + output fabric_tnd_fpga_apb_master_pwdata_o6; + output fabric_tnd_fpga_apb_master_pwdata_o7; + output fabric_tnd_fpga_apb_master_pwdata_o8; + output fabric_tnd_fpga_apb_master_pwdata_o9; + output fabric_tnd_fpga_apb_master_pwrite_o; + input fabric_tnd_fpga_atb_master_afready_i; + output fabric_tnd_fpga_atb_master_afvalid_o; + input fabric_tnd_fpga_atb_master_atbytes_i1; + input fabric_tnd_fpga_atb_master_atbytes_i2; + input fabric_tnd_fpga_atb_master_atbytes_i3; + input fabric_tnd_fpga_atb_master_atbytes_i4; + input fabric_tnd_fpga_atb_master_atdata_i1; + input fabric_tnd_fpga_atb_master_atdata_i10; + input fabric_tnd_fpga_atb_master_atdata_i100; + input fabric_tnd_fpga_atb_master_atdata_i101; + input fabric_tnd_fpga_atb_master_atdata_i102; + input fabric_tnd_fpga_atb_master_atdata_i103; + input fabric_tnd_fpga_atb_master_atdata_i104; + input fabric_tnd_fpga_atb_master_atdata_i105; + input fabric_tnd_fpga_atb_master_atdata_i106; + input fabric_tnd_fpga_atb_master_atdata_i107; + input fabric_tnd_fpga_atb_master_atdata_i108; + input fabric_tnd_fpga_atb_master_atdata_i109; + input fabric_tnd_fpga_atb_master_atdata_i11; + input fabric_tnd_fpga_atb_master_atdata_i110; + input fabric_tnd_fpga_atb_master_atdata_i111; + input fabric_tnd_fpga_atb_master_atdata_i112; + input fabric_tnd_fpga_atb_master_atdata_i113; + input fabric_tnd_fpga_atb_master_atdata_i114; + input fabric_tnd_fpga_atb_master_atdata_i115; + input fabric_tnd_fpga_atb_master_atdata_i116; + input fabric_tnd_fpga_atb_master_atdata_i117; + input fabric_tnd_fpga_atb_master_atdata_i118; + input fabric_tnd_fpga_atb_master_atdata_i119; + input fabric_tnd_fpga_atb_master_atdata_i12; + input fabric_tnd_fpga_atb_master_atdata_i120; + input fabric_tnd_fpga_atb_master_atdata_i121; + input fabric_tnd_fpga_atb_master_atdata_i122; + input fabric_tnd_fpga_atb_master_atdata_i123; + input fabric_tnd_fpga_atb_master_atdata_i124; + input fabric_tnd_fpga_atb_master_atdata_i125; + input fabric_tnd_fpga_atb_master_atdata_i126; + input fabric_tnd_fpga_atb_master_atdata_i127; + input fabric_tnd_fpga_atb_master_atdata_i128; + input fabric_tnd_fpga_atb_master_atdata_i13; + input fabric_tnd_fpga_atb_master_atdata_i14; + input fabric_tnd_fpga_atb_master_atdata_i15; + input fabric_tnd_fpga_atb_master_atdata_i16; + input fabric_tnd_fpga_atb_master_atdata_i17; + input fabric_tnd_fpga_atb_master_atdata_i18; + input fabric_tnd_fpga_atb_master_atdata_i19; + input fabric_tnd_fpga_atb_master_atdata_i2; + input fabric_tnd_fpga_atb_master_atdata_i20; + input fabric_tnd_fpga_atb_master_atdata_i21; + input fabric_tnd_fpga_atb_master_atdata_i22; + input fabric_tnd_fpga_atb_master_atdata_i23; + input fabric_tnd_fpga_atb_master_atdata_i24; + input fabric_tnd_fpga_atb_master_atdata_i25; + input fabric_tnd_fpga_atb_master_atdata_i26; + input fabric_tnd_fpga_atb_master_atdata_i27; + input fabric_tnd_fpga_atb_master_atdata_i28; + input fabric_tnd_fpga_atb_master_atdata_i29; + input fabric_tnd_fpga_atb_master_atdata_i3; + input fabric_tnd_fpga_atb_master_atdata_i30; + input fabric_tnd_fpga_atb_master_atdata_i31; + input fabric_tnd_fpga_atb_master_atdata_i32; + input fabric_tnd_fpga_atb_master_atdata_i33; + input fabric_tnd_fpga_atb_master_atdata_i34; + input fabric_tnd_fpga_atb_master_atdata_i35; + input fabric_tnd_fpga_atb_master_atdata_i36; + input fabric_tnd_fpga_atb_master_atdata_i37; + input fabric_tnd_fpga_atb_master_atdata_i38; + input fabric_tnd_fpga_atb_master_atdata_i39; + input fabric_tnd_fpga_atb_master_atdata_i4; + input fabric_tnd_fpga_atb_master_atdata_i40; + input fabric_tnd_fpga_atb_master_atdata_i41; + input fabric_tnd_fpga_atb_master_atdata_i42; + input fabric_tnd_fpga_atb_master_atdata_i43; + input fabric_tnd_fpga_atb_master_atdata_i44; + input fabric_tnd_fpga_atb_master_atdata_i45; + input fabric_tnd_fpga_atb_master_atdata_i46; + input fabric_tnd_fpga_atb_master_atdata_i47; + input fabric_tnd_fpga_atb_master_atdata_i48; + input fabric_tnd_fpga_atb_master_atdata_i49; + input fabric_tnd_fpga_atb_master_atdata_i5; + input fabric_tnd_fpga_atb_master_atdata_i50; + input fabric_tnd_fpga_atb_master_atdata_i51; + input fabric_tnd_fpga_atb_master_atdata_i52; + input fabric_tnd_fpga_atb_master_atdata_i53; + input fabric_tnd_fpga_atb_master_atdata_i54; + input fabric_tnd_fpga_atb_master_atdata_i55; + input fabric_tnd_fpga_atb_master_atdata_i56; + input fabric_tnd_fpga_atb_master_atdata_i57; + input fabric_tnd_fpga_atb_master_atdata_i58; + input fabric_tnd_fpga_atb_master_atdata_i59; + input fabric_tnd_fpga_atb_master_atdata_i6; + input fabric_tnd_fpga_atb_master_atdata_i60; + input fabric_tnd_fpga_atb_master_atdata_i61; + input fabric_tnd_fpga_atb_master_atdata_i62; + input fabric_tnd_fpga_atb_master_atdata_i63; + input fabric_tnd_fpga_atb_master_atdata_i64; + input fabric_tnd_fpga_atb_master_atdata_i65; + input fabric_tnd_fpga_atb_master_atdata_i66; + input fabric_tnd_fpga_atb_master_atdata_i67; + input fabric_tnd_fpga_atb_master_atdata_i68; + input fabric_tnd_fpga_atb_master_atdata_i69; + input fabric_tnd_fpga_atb_master_atdata_i7; + input fabric_tnd_fpga_atb_master_atdata_i70; + input fabric_tnd_fpga_atb_master_atdata_i71; + input fabric_tnd_fpga_atb_master_atdata_i72; + input fabric_tnd_fpga_atb_master_atdata_i73; + input fabric_tnd_fpga_atb_master_atdata_i74; + input fabric_tnd_fpga_atb_master_atdata_i75; + input fabric_tnd_fpga_atb_master_atdata_i76; + input fabric_tnd_fpga_atb_master_atdata_i77; + input fabric_tnd_fpga_atb_master_atdata_i78; + input fabric_tnd_fpga_atb_master_atdata_i79; + input fabric_tnd_fpga_atb_master_atdata_i8; + input fabric_tnd_fpga_atb_master_atdata_i80; + input fabric_tnd_fpga_atb_master_atdata_i81; + input fabric_tnd_fpga_atb_master_atdata_i82; + input fabric_tnd_fpga_atb_master_atdata_i83; + input fabric_tnd_fpga_atb_master_atdata_i84; + input fabric_tnd_fpga_atb_master_atdata_i85; + input fabric_tnd_fpga_atb_master_atdata_i86; + input fabric_tnd_fpga_atb_master_atdata_i87; + input fabric_tnd_fpga_atb_master_atdata_i88; + input fabric_tnd_fpga_atb_master_atdata_i89; + input fabric_tnd_fpga_atb_master_atdata_i9; + input fabric_tnd_fpga_atb_master_atdata_i90; + input fabric_tnd_fpga_atb_master_atdata_i91; + input fabric_tnd_fpga_atb_master_atdata_i92; + input fabric_tnd_fpga_atb_master_atdata_i93; + input fabric_tnd_fpga_atb_master_atdata_i94; + input fabric_tnd_fpga_atb_master_atdata_i95; + input fabric_tnd_fpga_atb_master_atdata_i96; + input fabric_tnd_fpga_atb_master_atdata_i97; + input fabric_tnd_fpga_atb_master_atdata_i98; + input fabric_tnd_fpga_atb_master_atdata_i99; + input fabric_tnd_fpga_atb_master_atid_i1; + input fabric_tnd_fpga_atb_master_atid_i2; + input fabric_tnd_fpga_atb_master_atid_i3; + input fabric_tnd_fpga_atb_master_atid_i4; + input fabric_tnd_fpga_atb_master_atid_i5; + input fabric_tnd_fpga_atb_master_atid_i6; + input fabric_tnd_fpga_atb_master_atid_i7; + output fabric_tnd_fpga_atb_master_atready_o; + input fabric_tnd_fpga_atb_master_atvalid_i; + output fabric_tnd_fpga_atb_master_syncreq_o; + output fabric_tnd_hssl_apb_master_paddr_o1; + output fabric_tnd_hssl_apb_master_paddr_o10; + output fabric_tnd_hssl_apb_master_paddr_o11; + output fabric_tnd_hssl_apb_master_paddr_o12; + output fabric_tnd_hssl_apb_master_paddr_o13; + output fabric_tnd_hssl_apb_master_paddr_o14; + output fabric_tnd_hssl_apb_master_paddr_o15; + output fabric_tnd_hssl_apb_master_paddr_o16; + output fabric_tnd_hssl_apb_master_paddr_o17; + output fabric_tnd_hssl_apb_master_paddr_o18; + output fabric_tnd_hssl_apb_master_paddr_o19; + output fabric_tnd_hssl_apb_master_paddr_o2; + output fabric_tnd_hssl_apb_master_paddr_o20; + output fabric_tnd_hssl_apb_master_paddr_o21; + output fabric_tnd_hssl_apb_master_paddr_o22; + output fabric_tnd_hssl_apb_master_paddr_o23; + output fabric_tnd_hssl_apb_master_paddr_o24; + output fabric_tnd_hssl_apb_master_paddr_o25; + output fabric_tnd_hssl_apb_master_paddr_o26; + output fabric_tnd_hssl_apb_master_paddr_o27; + output fabric_tnd_hssl_apb_master_paddr_o28; + output fabric_tnd_hssl_apb_master_paddr_o29; + output fabric_tnd_hssl_apb_master_paddr_o3; + output fabric_tnd_hssl_apb_master_paddr_o30; + output fabric_tnd_hssl_apb_master_paddr_o31; + output fabric_tnd_hssl_apb_master_paddr_o32; + output fabric_tnd_hssl_apb_master_paddr_o4; + output fabric_tnd_hssl_apb_master_paddr_o5; + output fabric_tnd_hssl_apb_master_paddr_o6; + output fabric_tnd_hssl_apb_master_paddr_o7; + output fabric_tnd_hssl_apb_master_paddr_o8; + output fabric_tnd_hssl_apb_master_paddr_o9; + output fabric_tnd_hssl_apb_master_penable_o; + input fabric_tnd_hssl_apb_master_prdata_i1; + input fabric_tnd_hssl_apb_master_prdata_i10; + input fabric_tnd_hssl_apb_master_prdata_i11; + input fabric_tnd_hssl_apb_master_prdata_i12; + input fabric_tnd_hssl_apb_master_prdata_i13; + input fabric_tnd_hssl_apb_master_prdata_i14; + input fabric_tnd_hssl_apb_master_prdata_i15; + input fabric_tnd_hssl_apb_master_prdata_i16; + input fabric_tnd_hssl_apb_master_prdata_i17; + input fabric_tnd_hssl_apb_master_prdata_i18; + input fabric_tnd_hssl_apb_master_prdata_i19; + input fabric_tnd_hssl_apb_master_prdata_i2; + input fabric_tnd_hssl_apb_master_prdata_i20; + input fabric_tnd_hssl_apb_master_prdata_i21; + input fabric_tnd_hssl_apb_master_prdata_i22; + input fabric_tnd_hssl_apb_master_prdata_i23; + input fabric_tnd_hssl_apb_master_prdata_i24; + input fabric_tnd_hssl_apb_master_prdata_i25; + input fabric_tnd_hssl_apb_master_prdata_i26; + input fabric_tnd_hssl_apb_master_prdata_i27; + input fabric_tnd_hssl_apb_master_prdata_i28; + input fabric_tnd_hssl_apb_master_prdata_i29; + input fabric_tnd_hssl_apb_master_prdata_i3; + input fabric_tnd_hssl_apb_master_prdata_i30; + input fabric_tnd_hssl_apb_master_prdata_i31; + input fabric_tnd_hssl_apb_master_prdata_i32; + input fabric_tnd_hssl_apb_master_prdata_i4; + input fabric_tnd_hssl_apb_master_prdata_i5; + input fabric_tnd_hssl_apb_master_prdata_i6; + input fabric_tnd_hssl_apb_master_prdata_i7; + input fabric_tnd_hssl_apb_master_prdata_i8; + input fabric_tnd_hssl_apb_master_prdata_i9; + input fabric_tnd_hssl_apb_master_pready_i; + output fabric_tnd_hssl_apb_master_psel_o; + input fabric_tnd_hssl_apb_master_pslverr_i; + output fabric_tnd_hssl_apb_master_pwdata_o1; + output fabric_tnd_hssl_apb_master_pwdata_o10; + output fabric_tnd_hssl_apb_master_pwdata_o11; + output fabric_tnd_hssl_apb_master_pwdata_o12; + output fabric_tnd_hssl_apb_master_pwdata_o13; + output fabric_tnd_hssl_apb_master_pwdata_o14; + output fabric_tnd_hssl_apb_master_pwdata_o15; + output fabric_tnd_hssl_apb_master_pwdata_o16; + output fabric_tnd_hssl_apb_master_pwdata_o17; + output fabric_tnd_hssl_apb_master_pwdata_o18; + output fabric_tnd_hssl_apb_master_pwdata_o19; + output fabric_tnd_hssl_apb_master_pwdata_o2; + output fabric_tnd_hssl_apb_master_pwdata_o20; + output fabric_tnd_hssl_apb_master_pwdata_o21; + output fabric_tnd_hssl_apb_master_pwdata_o22; + output fabric_tnd_hssl_apb_master_pwdata_o23; + output fabric_tnd_hssl_apb_master_pwdata_o24; + output fabric_tnd_hssl_apb_master_pwdata_o25; + output fabric_tnd_hssl_apb_master_pwdata_o26; + output fabric_tnd_hssl_apb_master_pwdata_o27; + output fabric_tnd_hssl_apb_master_pwdata_o28; + output fabric_tnd_hssl_apb_master_pwdata_o29; + output fabric_tnd_hssl_apb_master_pwdata_o3; + output fabric_tnd_hssl_apb_master_pwdata_o30; + output fabric_tnd_hssl_apb_master_pwdata_o31; + output fabric_tnd_hssl_apb_master_pwdata_o32; + output fabric_tnd_hssl_apb_master_pwdata_o4; + output fabric_tnd_hssl_apb_master_pwdata_o5; + output fabric_tnd_hssl_apb_master_pwdata_o6; + output fabric_tnd_hssl_apb_master_pwdata_o7; + output fabric_tnd_hssl_apb_master_pwdata_o8; + output fabric_tnd_hssl_apb_master_pwdata_o9; + output fabric_tnd_hssl_apb_master_pwrite_o; + output fabric_tnd_hssl_atb_master_afready_o; + input fabric_tnd_hssl_atb_master_afvalid_i; + output fabric_tnd_hssl_atb_master_atbytes_o1; + output fabric_tnd_hssl_atb_master_atbytes_o2; + output fabric_tnd_hssl_atb_master_atbytes_o3; + output fabric_tnd_hssl_atb_master_atbytes_o4; + output fabric_tnd_hssl_atb_master_atdata_o1; + output fabric_tnd_hssl_atb_master_atdata_o10; + output fabric_tnd_hssl_atb_master_atdata_o100; + output fabric_tnd_hssl_atb_master_atdata_o101; + output fabric_tnd_hssl_atb_master_atdata_o102; + output fabric_tnd_hssl_atb_master_atdata_o103; + output fabric_tnd_hssl_atb_master_atdata_o104; + output fabric_tnd_hssl_atb_master_atdata_o105; + output fabric_tnd_hssl_atb_master_atdata_o106; + output fabric_tnd_hssl_atb_master_atdata_o107; + output fabric_tnd_hssl_atb_master_atdata_o108; + output fabric_tnd_hssl_atb_master_atdata_o109; + output fabric_tnd_hssl_atb_master_atdata_o11; + output fabric_tnd_hssl_atb_master_atdata_o110; + output fabric_tnd_hssl_atb_master_atdata_o111; + output fabric_tnd_hssl_atb_master_atdata_o112; + output fabric_tnd_hssl_atb_master_atdata_o113; + output fabric_tnd_hssl_atb_master_atdata_o114; + output fabric_tnd_hssl_atb_master_atdata_o115; + output fabric_tnd_hssl_atb_master_atdata_o116; + output fabric_tnd_hssl_atb_master_atdata_o117; + output fabric_tnd_hssl_atb_master_atdata_o118; + output fabric_tnd_hssl_atb_master_atdata_o119; + output fabric_tnd_hssl_atb_master_atdata_o12; + output fabric_tnd_hssl_atb_master_atdata_o120; + output fabric_tnd_hssl_atb_master_atdata_o121; + output fabric_tnd_hssl_atb_master_atdata_o122; + output fabric_tnd_hssl_atb_master_atdata_o123; + output fabric_tnd_hssl_atb_master_atdata_o124; + output fabric_tnd_hssl_atb_master_atdata_o125; + output fabric_tnd_hssl_atb_master_atdata_o126; + output fabric_tnd_hssl_atb_master_atdata_o127; + output fabric_tnd_hssl_atb_master_atdata_o128; + output fabric_tnd_hssl_atb_master_atdata_o13; + output fabric_tnd_hssl_atb_master_atdata_o14; + output fabric_tnd_hssl_atb_master_atdata_o15; + output fabric_tnd_hssl_atb_master_atdata_o16; + output fabric_tnd_hssl_atb_master_atdata_o17; + output fabric_tnd_hssl_atb_master_atdata_o18; + output fabric_tnd_hssl_atb_master_atdata_o19; + output fabric_tnd_hssl_atb_master_atdata_o2; + output fabric_tnd_hssl_atb_master_atdata_o20; + output fabric_tnd_hssl_atb_master_atdata_o21; + output fabric_tnd_hssl_atb_master_atdata_o22; + output fabric_tnd_hssl_atb_master_atdata_o23; + output fabric_tnd_hssl_atb_master_atdata_o24; + output fabric_tnd_hssl_atb_master_atdata_o25; + output fabric_tnd_hssl_atb_master_atdata_o26; + output fabric_tnd_hssl_atb_master_atdata_o27; + output fabric_tnd_hssl_atb_master_atdata_o28; + output fabric_tnd_hssl_atb_master_atdata_o29; + output fabric_tnd_hssl_atb_master_atdata_o3; + output fabric_tnd_hssl_atb_master_atdata_o30; + output fabric_tnd_hssl_atb_master_atdata_o31; + output fabric_tnd_hssl_atb_master_atdata_o32; + output fabric_tnd_hssl_atb_master_atdata_o33; + output fabric_tnd_hssl_atb_master_atdata_o34; + output fabric_tnd_hssl_atb_master_atdata_o35; + output fabric_tnd_hssl_atb_master_atdata_o36; + output fabric_tnd_hssl_atb_master_atdata_o37; + output fabric_tnd_hssl_atb_master_atdata_o38; + output fabric_tnd_hssl_atb_master_atdata_o39; + output fabric_tnd_hssl_atb_master_atdata_o4; + output fabric_tnd_hssl_atb_master_atdata_o40; + output fabric_tnd_hssl_atb_master_atdata_o41; + output fabric_tnd_hssl_atb_master_atdata_o42; + output fabric_tnd_hssl_atb_master_atdata_o43; + output fabric_tnd_hssl_atb_master_atdata_o44; + output fabric_tnd_hssl_atb_master_atdata_o45; + output fabric_tnd_hssl_atb_master_atdata_o46; + output fabric_tnd_hssl_atb_master_atdata_o47; + output fabric_tnd_hssl_atb_master_atdata_o48; + output fabric_tnd_hssl_atb_master_atdata_o49; + output fabric_tnd_hssl_atb_master_atdata_o5; + output fabric_tnd_hssl_atb_master_atdata_o50; + output fabric_tnd_hssl_atb_master_atdata_o51; + output fabric_tnd_hssl_atb_master_atdata_o52; + output fabric_tnd_hssl_atb_master_atdata_o53; + output fabric_tnd_hssl_atb_master_atdata_o54; + output fabric_tnd_hssl_atb_master_atdata_o55; + output fabric_tnd_hssl_atb_master_atdata_o56; + output fabric_tnd_hssl_atb_master_atdata_o57; + output fabric_tnd_hssl_atb_master_atdata_o58; + output fabric_tnd_hssl_atb_master_atdata_o59; + output fabric_tnd_hssl_atb_master_atdata_o6; + output fabric_tnd_hssl_atb_master_atdata_o60; + output fabric_tnd_hssl_atb_master_atdata_o61; + output fabric_tnd_hssl_atb_master_atdata_o62; + output fabric_tnd_hssl_atb_master_atdata_o63; + output fabric_tnd_hssl_atb_master_atdata_o64; + output fabric_tnd_hssl_atb_master_atdata_o65; + output fabric_tnd_hssl_atb_master_atdata_o66; + output fabric_tnd_hssl_atb_master_atdata_o67; + output fabric_tnd_hssl_atb_master_atdata_o68; + output fabric_tnd_hssl_atb_master_atdata_o69; + output fabric_tnd_hssl_atb_master_atdata_o7; + output fabric_tnd_hssl_atb_master_atdata_o70; + output fabric_tnd_hssl_atb_master_atdata_o71; + output fabric_tnd_hssl_atb_master_atdata_o72; + output fabric_tnd_hssl_atb_master_atdata_o73; + output fabric_tnd_hssl_atb_master_atdata_o74; + output fabric_tnd_hssl_atb_master_atdata_o75; + output fabric_tnd_hssl_atb_master_atdata_o76; + output fabric_tnd_hssl_atb_master_atdata_o77; + output fabric_tnd_hssl_atb_master_atdata_o78; + output fabric_tnd_hssl_atb_master_atdata_o79; + output fabric_tnd_hssl_atb_master_atdata_o8; + output fabric_tnd_hssl_atb_master_atdata_o80; + output fabric_tnd_hssl_atb_master_atdata_o81; + output fabric_tnd_hssl_atb_master_atdata_o82; + output fabric_tnd_hssl_atb_master_atdata_o83; + output fabric_tnd_hssl_atb_master_atdata_o84; + output fabric_tnd_hssl_atb_master_atdata_o85; + output fabric_tnd_hssl_atb_master_atdata_o86; + output fabric_tnd_hssl_atb_master_atdata_o87; + output fabric_tnd_hssl_atb_master_atdata_o88; + output fabric_tnd_hssl_atb_master_atdata_o89; + output fabric_tnd_hssl_atb_master_atdata_o9; + output fabric_tnd_hssl_atb_master_atdata_o90; + output fabric_tnd_hssl_atb_master_atdata_o91; + output fabric_tnd_hssl_atb_master_atdata_o92; + output fabric_tnd_hssl_atb_master_atdata_o93; + output fabric_tnd_hssl_atb_master_atdata_o94; + output fabric_tnd_hssl_atb_master_atdata_o95; + output fabric_tnd_hssl_atb_master_atdata_o96; + output fabric_tnd_hssl_atb_master_atdata_o97; + output fabric_tnd_hssl_atb_master_atdata_o98; + output fabric_tnd_hssl_atb_master_atdata_o99; + output fabric_tnd_hssl_atb_master_atid_o1; + output fabric_tnd_hssl_atb_master_atid_o2; + output fabric_tnd_hssl_atb_master_atid_o3; + output fabric_tnd_hssl_atb_master_atid_o4; + output fabric_tnd_hssl_atb_master_atid_o5; + output fabric_tnd_hssl_atb_master_atid_o6; + output fabric_tnd_hssl_atb_master_atid_o7; + input fabric_tnd_hssl_atb_master_atready_i; + output fabric_tnd_hssl_atb_master_atvalid_o; + input fabric_tnd_hssl_atb_master_syncreq_i; + output fabric_tnd_hssl_flushin_o; + output fabric_tnd_hssl_trigin_o; + output fabric_tnd_trace_clk_traceoutportintf_o; + output fabric_tnd_trace_ctl_traceoutportintf_o; + output fabric_tnd_trace_data_traceoutportintf_o1; + output fabric_tnd_trace_data_traceoutportintf_o10; + output fabric_tnd_trace_data_traceoutportintf_o11; + output fabric_tnd_trace_data_traceoutportintf_o12; + output fabric_tnd_trace_data_traceoutportintf_o13; + output fabric_tnd_trace_data_traceoutportintf_o14; + output fabric_tnd_trace_data_traceoutportintf_o15; + output fabric_tnd_trace_data_traceoutportintf_o16; + output fabric_tnd_trace_data_traceoutportintf_o17; + output fabric_tnd_trace_data_traceoutportintf_o18; + output fabric_tnd_trace_data_traceoutportintf_o19; + output fabric_tnd_trace_data_traceoutportintf_o2; + output fabric_tnd_trace_data_traceoutportintf_o20; + output fabric_tnd_trace_data_traceoutportintf_o21; + output fabric_tnd_trace_data_traceoutportintf_o22; + output fabric_tnd_trace_data_traceoutportintf_o23; + output fabric_tnd_trace_data_traceoutportintf_o24; + output fabric_tnd_trace_data_traceoutportintf_o25; + output fabric_tnd_trace_data_traceoutportintf_o26; + output fabric_tnd_trace_data_traceoutportintf_o27; + output fabric_tnd_trace_data_traceoutportintf_o28; + output fabric_tnd_trace_data_traceoutportintf_o29; + output fabric_tnd_trace_data_traceoutportintf_o3; + output fabric_tnd_trace_data_traceoutportintf_o30; + output fabric_tnd_trace_data_traceoutportintf_o31; + output fabric_tnd_trace_data_traceoutportintf_o32; + output fabric_tnd_trace_data_traceoutportintf_o4; + output fabric_tnd_trace_data_traceoutportintf_o5; + output fabric_tnd_trace_data_traceoutportintf_o6; + output fabric_tnd_trace_data_traceoutportintf_o7; + output fabric_tnd_trace_data_traceoutportintf_o8; + output fabric_tnd_trace_data_traceoutportintf_o9; + output fabric_tst_pll_lock_o1; + output fabric_tst_pll_lock_o2; + output fabric_tst_pll_lock_o3; + output fabric_tst_pll_lock_o4; + output fabric_tst_pll_lock_o5; + output fabric_tst_pll_lock_o6; + output fabric_tst_pll_lock_o7; + output fabric_tsvalue_tsgen_fpga_o1; + output fabric_tsvalue_tsgen_fpga_o10; + output fabric_tsvalue_tsgen_fpga_o11; + output fabric_tsvalue_tsgen_fpga_o12; + output fabric_tsvalue_tsgen_fpga_o13; + output fabric_tsvalue_tsgen_fpga_o14; + output fabric_tsvalue_tsgen_fpga_o15; + output fabric_tsvalue_tsgen_fpga_o16; + output fabric_tsvalue_tsgen_fpga_o17; + output fabric_tsvalue_tsgen_fpga_o18; + output fabric_tsvalue_tsgen_fpga_o19; + output fabric_tsvalue_tsgen_fpga_o2; + output fabric_tsvalue_tsgen_fpga_o20; + output fabric_tsvalue_tsgen_fpga_o21; + output fabric_tsvalue_tsgen_fpga_o22; + output fabric_tsvalue_tsgen_fpga_o23; + output fabric_tsvalue_tsgen_fpga_o24; + output fabric_tsvalue_tsgen_fpga_o25; + output fabric_tsvalue_tsgen_fpga_o26; + output fabric_tsvalue_tsgen_fpga_o27; + output fabric_tsvalue_tsgen_fpga_o28; + output fabric_tsvalue_tsgen_fpga_o29; + output fabric_tsvalue_tsgen_fpga_o3; + output fabric_tsvalue_tsgen_fpga_o30; + output fabric_tsvalue_tsgen_fpga_o31; + output fabric_tsvalue_tsgen_fpga_o32; + output fabric_tsvalue_tsgen_fpga_o33; + output fabric_tsvalue_tsgen_fpga_o34; + output fabric_tsvalue_tsgen_fpga_o35; + output fabric_tsvalue_tsgen_fpga_o36; + output fabric_tsvalue_tsgen_fpga_o37; + output fabric_tsvalue_tsgen_fpga_o38; + output fabric_tsvalue_tsgen_fpga_o39; + output fabric_tsvalue_tsgen_fpga_o4; + output fabric_tsvalue_tsgen_fpga_o40; + output fabric_tsvalue_tsgen_fpga_o41; + output fabric_tsvalue_tsgen_fpga_o42; + output fabric_tsvalue_tsgen_fpga_o43; + output fabric_tsvalue_tsgen_fpga_o44; + output fabric_tsvalue_tsgen_fpga_o45; + output fabric_tsvalue_tsgen_fpga_o46; + output fabric_tsvalue_tsgen_fpga_o47; + output fabric_tsvalue_tsgen_fpga_o48; + output fabric_tsvalue_tsgen_fpga_o49; + output fabric_tsvalue_tsgen_fpga_o5; + output fabric_tsvalue_tsgen_fpga_o50; + output fabric_tsvalue_tsgen_fpga_o51; + output fabric_tsvalue_tsgen_fpga_o52; + output fabric_tsvalue_tsgen_fpga_o53; + output fabric_tsvalue_tsgen_fpga_o54; + output fabric_tsvalue_tsgen_fpga_o55; + output fabric_tsvalue_tsgen_fpga_o56; + output fabric_tsvalue_tsgen_fpga_o57; + output fabric_tsvalue_tsgen_fpga_o58; + output fabric_tsvalue_tsgen_fpga_o59; + output fabric_tsvalue_tsgen_fpga_o6; + output fabric_tsvalue_tsgen_fpga_o60; + output fabric_tsvalue_tsgen_fpga_o61; + output fabric_tsvalue_tsgen_fpga_o62; + output fabric_tsvalue_tsgen_fpga_o63; + output fabric_tsvalue_tsgen_fpga_o64; + output fabric_tsvalue_tsgen_fpga_o7; + output fabric_tsvalue_tsgen_fpga_o8; + output fabric_tsvalue_tsgen_fpga_o9; + output fabric_watchdog0_signal_0_o; + output fabric_watchdog0_signal_1_o; + output fabric_watchdog1_signal_0_o; + output fabric_watchdog1_signal_1_o; + output fabric_watchdog2_signal_0_o; + output fabric_watchdog2_signal_1_o; + output fabric_watchdog3_signal_0_o; + output fabric_watchdog3_signal_1_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SOC_INTERFACE_V1_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o +, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i +, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o +, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o +, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i +, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o +, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o +, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o +, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i +, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o, fabric_fpga_arqos_axi_s1_o +, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o, fabric_fpga_arcache_axi_s2_o +, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i, fabric_fpga_rid_axi_s2_i +, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i, fabric_fpga_awlen_axi_m1_i +, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i, fabric_fpga_arprot_axi_m2_i +, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o, fabric_fpga_ddr0_araddr_i +, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i, fabric_llpp0_araddr_s_o +, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i, fabric_llpp0_rid_s_i +, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arqos_s1_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i +, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o +, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o +, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i +, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o); + input [2:0] fabric_enable_TMR_i; + input fabric_erom_fpga_cpu0_dbgen_i; + input fabric_erom_fpga_cpu0_hiden_i; + input fabric_erom_fpga_cpu0_hniden_i; + input fabric_erom_fpga_cpu0_niden_i; + input fabric_erom_fpga_cpu1_dbgen_i; + input fabric_erom_fpga_cpu1_hiden_i; + input fabric_erom_fpga_cpu1_hniden_i; + input fabric_erom_fpga_cpu1_niden_i; + input fabric_erom_fpga_cpu2_dbgen_i; + input fabric_erom_fpga_cpu2_hiden_i; + input fabric_erom_fpga_cpu2_hniden_i; + input fabric_erom_fpga_cpu2_niden_i; + input fabric_erom_fpga_cpu3_dbgen_i; + input fabric_erom_fpga_cpu3_hiden_i; + input fabric_erom_fpga_cpu3_hniden_i; + input fabric_erom_fpga_cpu3_niden_i; + input fabric_erom_fpga_cs_dbgen_i; + input fabric_erom_fpga_cs_deviceen_i; + input fabric_erom_fpga_cs_niden_i; + input fabric_erom_fpga_cs_rst_n_i; + input fabric_erom_fpga_debug_en_i; + input [39:0] fabric_fpga_araddr_axi_m1_i; + input [39:0] fabric_fpga_araddr_axi_m2_i; + output [39:0] fabric_fpga_araddr_axi_s1_o; + output [39:0] fabric_fpga_araddr_axi_s2_o; + input [1:0] fabric_fpga_arburst_axi_m1_i; + input [1:0] fabric_fpga_arburst_axi_m2_i; + output [1:0] fabric_fpga_arburst_axi_s1_o; + output [1:0] fabric_fpga_arburst_axi_s2_o; + input [3:0] fabric_fpga_arcache_axi_m1_i; + input [3:0] fabric_fpga_arcache_axi_m2_i; + output [3:0] fabric_fpga_arcache_axi_s1_o; + output [3:0] fabric_fpga_arcache_axi_s2_o; + input [4:0] fabric_fpga_arid_axi_m1_i; + input [4:0] fabric_fpga_arid_axi_m2_i; + output [11:0] fabric_fpga_arid_axi_s1_o; + output [11:0] fabric_fpga_arid_axi_s2_o; + input [7:0] fabric_fpga_arlen_axi_m1_i; + input [7:0] fabric_fpga_arlen_axi_m2_i; + output [7:0] fabric_fpga_arlen_axi_s1_o; + output [7:0] fabric_fpga_arlen_axi_s2_o; + input fabric_fpga_arlock_axi_m1_i; + input fabric_fpga_arlock_axi_m2_i; + output fabric_fpga_arlock_axi_s1_o; + output fabric_fpga_arlock_axi_s2_o; + input [2:0] fabric_fpga_arprot_axi_m1_i; + input [2:0] fabric_fpga_arprot_axi_m2_i; + output [2:0] fabric_fpga_arprot_axi_s1_o; + output [2:0] fabric_fpga_arprot_axi_s2_o; + input [3:0] fabric_fpga_arqos_axi_m1_i; + input [3:0] fabric_fpga_arqos_axi_m2_i; + output [3:0] fabric_fpga_arqos_axi_s1_o; + output [3:0] fabric_fpga_arqos_axi_s2_o; + output fabric_fpga_arready_axi_m1_o; + output fabric_fpga_arready_axi_m2_o; + input fabric_fpga_arready_axi_s1_i; + input fabric_fpga_arready_axi_s2_i; + output [3:0] fabric_fpga_arregion_axi_s1_o; + output [3:0] fabric_fpga_arregion_axi_s2_o; + input [2:0] fabric_fpga_arsize_axi_m1_i; + input [2:0] fabric_fpga_arsize_axi_m2_i; + output [2:0] fabric_fpga_arsize_axi_s1_o; + output [2:0] fabric_fpga_arsize_axi_s2_o; + input fabric_fpga_arvalid_axi_m1_i; + input fabric_fpga_arvalid_axi_m2_i; + output fabric_fpga_arvalid_axi_s1_o; + output fabric_fpga_arvalid_axi_s2_o; + input [39:0] fabric_fpga_awaddr_axi_m1_i; + input [39:0] fabric_fpga_awaddr_axi_m2_i; + output [39:0] fabric_fpga_awaddr_axi_s1_o; + output [39:0] fabric_fpga_awaddr_axi_s2_o; + input [1:0] fabric_fpga_awburst_axi_m1_i; + input [1:0] fabric_fpga_awburst_axi_m2_i; + output [1:0] fabric_fpga_awburst_axi_s1_o; + output [1:0] fabric_fpga_awburst_axi_s2_o; + input [3:0] fabric_fpga_awcache_axi_m1_i; + input [3:0] fabric_fpga_awcache_axi_m2_i; + output [3:0] fabric_fpga_awcache_axi_s1_o; + output [3:0] fabric_fpga_awcache_axi_s2_o; + input [4:0] fabric_fpga_awid_axi_m1_i; + input [4:0] fabric_fpga_awid_axi_m2_i; + output [11:0] fabric_fpga_awid_axi_s1_o; + output [11:0] fabric_fpga_awid_axi_s2_o; + input [7:0] fabric_fpga_awlen_axi_m1_i; + input [7:0] fabric_fpga_awlen_axi_m2_i; + output [7:0] fabric_fpga_awlen_axi_s1_o; + output [7:0] fabric_fpga_awlen_axi_s2_o; + input fabric_fpga_awlock_axi_m1_i; + input fabric_fpga_awlock_axi_m2_i; + output fabric_fpga_awlock_axi_s1_o; + output fabric_fpga_awlock_axi_s2_o; + input [2:0] fabric_fpga_awprot_axi_m1_i; + input [2:0] fabric_fpga_awprot_axi_m2_i; + output [2:0] fabric_fpga_awprot_axi_s1_o; + output [2:0] fabric_fpga_awprot_axi_s2_o; + input [3:0] fabric_fpga_awqos_axi_m1_i; + input [3:0] fabric_fpga_awqos_axi_m2_i; + output [3:0] fabric_fpga_awqos_axi_s1_o; + output [3:0] fabric_fpga_awqos_axi_s2_o; + output fabric_fpga_awready_axi_m1_o; + output fabric_fpga_awready_axi_m2_o; + input fabric_fpga_awready_axi_s1_i; + input fabric_fpga_awready_axi_s2_i; + output [3:0] fabric_fpga_awregion_axi_s1_o; + output [3:0] fabric_fpga_awregion_axi_s2_o; + input [2:0] fabric_fpga_awsize_axi_m1_i; + input [2:0] fabric_fpga_awsize_axi_m2_i; + output [2:0] fabric_fpga_awsize_axi_s1_o; + output [2:0] fabric_fpga_awsize_axi_s2_o; + input fabric_fpga_awvalid_axi_m1_i; + input fabric_fpga_awvalid_axi_m2_i; + output fabric_fpga_awvalid_axi_s1_o; + output fabric_fpga_awvalid_axi_s2_o; + output [4:0] fabric_fpga_bid_axi_m1_o; + output [4:0] fabric_fpga_bid_axi_m2_o; + input [11:0] fabric_fpga_bid_axi_s1_i; + input [11:0] fabric_fpga_bid_axi_s2_i; + input fabric_fpga_bready_axi_m1_i; + input fabric_fpga_bready_axi_m2_i; + output fabric_fpga_bready_axi_s1_o; + output fabric_fpga_bready_axi_s2_o; + output [1:0] fabric_fpga_bresp_axi_m1_o; + output [1:0] fabric_fpga_bresp_axi_m2_o; + input [1:0] fabric_fpga_bresp_axi_s1_i; + input [1:0] fabric_fpga_bresp_axi_s2_i; + output fabric_fpga_bvalid_axi_m1_o; + output fabric_fpga_bvalid_axi_m2_o; + input fabric_fpga_bvalid_axi_s1_i; + input fabric_fpga_bvalid_axi_s2_i; + input [39:0] fabric_fpga_ddr0_araddr_i; + input [1:0] fabric_fpga_ddr0_arburst_i; + input [3:0] fabric_fpga_ddr0_arcache_i; + input [4:0] fabric_fpga_ddr0_arid_i; + input [7:0] fabric_fpga_ddr0_arlen_i; + input fabric_fpga_ddr0_arlock_i; + input [2:0] fabric_fpga_ddr0_arprot_i; + input [3:0] fabric_fpga_ddr0_arqos_i; + output fabric_fpga_ddr0_arready_o; + input [2:0] fabric_fpga_ddr0_arsize_i; + input fabric_fpga_ddr0_arvalid_i; + input [39:0] fabric_fpga_ddr0_awaddr_i; + input [1:0] fabric_fpga_ddr0_awburst_i; + input [3:0] fabric_fpga_ddr0_awcache_i; + input [4:0] fabric_fpga_ddr0_awid_i; + input [7:0] fabric_fpga_ddr0_awlen_i; + input fabric_fpga_ddr0_awlock_i; + input [2:0] fabric_fpga_ddr0_awprot_i; + input [3:0] fabric_fpga_ddr0_awqos_i; + output fabric_fpga_ddr0_awready_o; + input [2:0] fabric_fpga_ddr0_awsize_i; + input fabric_fpga_ddr0_awvalid_i; + output [4:0] fabric_fpga_ddr0_bid_o; + input fabric_fpga_ddr0_bready_i; + output [1:0] fabric_fpga_ddr0_bresp_o; + output fabric_fpga_ddr0_bvalid_o; + output [127:0] fabric_fpga_ddr0_rdata_o; + output [4:0] fabric_fpga_ddr0_rid_o; + output fabric_fpga_ddr0_rlast_o; + input fabric_fpga_ddr0_rready_i; + output [1:0] fabric_fpga_ddr0_rresp_o; + output fabric_fpga_ddr0_rvalid_o; + input [127:0] fabric_fpga_ddr0_wdata_i; + input fabric_fpga_ddr0_wlast_i; + output fabric_fpga_ddr0_wready_o; + input [15:0] fabric_fpga_ddr0_wstrb_i; + input fabric_fpga_ddr0_wvalid_i; + output [5:0] fabric_fpga_dma_ack_m1_o; + output [5:0] fabric_fpga_dma_ack_m2_o; + output [5:0] fabric_fpga_dma_finish_m1_o; + output [5:0] fabric_fpga_dma_finish_m2_o; + input [5:0] fabric_fpga_dma_last_m1_i; + input [5:0] fabric_fpga_dma_last_m2_i; + input [5:0] fabric_fpga_dma_req_m1_i; + input [5:0] fabric_fpga_dma_req_m2_i; + input [5:0] fabric_fpga_dma_single_m1_i; + input [5:0] fabric_fpga_dma_single_m2_i; + input [59:0] fabric_fpga_events60_i; + input [119:0] fabric_fpga_interrupt_in_i; + input [9:0] fabric_fpga_nic_rstn_i; + output [31:0] fabric_fpga_paddr_apb_o; + output fabric_fpga_penable_apb_o; + input fabric_fpga_pmrstn_i; + input [31:0] fabric_fpga_prdata_apb_i; + input fabric_fpga_pready_apb_i; + output fabric_fpga_psel_apb_o; + input fabric_fpga_pslverr_apb_i; + output [31:0] fabric_fpga_pwdata_apb_o; + output fabric_fpga_pwrite_apb_o; + output [127:0] fabric_fpga_rdata_axi_m1_o; + output [127:0] fabric_fpga_rdata_axi_m2_o; + input [127:0] fabric_fpga_rdata_axi_s1_i; + input [127:0] fabric_fpga_rdata_axi_s2_i; + output [4:0] fabric_fpga_rid_axi_m1_o; + output [4:0] fabric_fpga_rid_axi_m2_o; + input [11:0] fabric_fpga_rid_axi_s1_i; + input [11:0] fabric_fpga_rid_axi_s2_i; + output fabric_fpga_rlast_axi_m1_o; + output fabric_fpga_rlast_axi_m2_o; + input fabric_fpga_rlast_axi_s1_i; + input fabric_fpga_rlast_axi_s2_i; + input fabric_fpga_rready_axi_m1_i; + input fabric_fpga_rready_axi_m2_i; + output fabric_fpga_rready_axi_s1_o; + output fabric_fpga_rready_axi_s2_o; + output [1:0] fabric_fpga_rresp_axi_m1_o; + output [1:0] fabric_fpga_rresp_axi_m2_o; + input [1:0] fabric_fpga_rresp_axi_s1_i; + input [1:0] fabric_fpga_rresp_axi_s2_i; + output fabric_fpga_rvalid_axi_m1_o; + output fabric_fpga_rvalid_axi_m2_o; + input fabric_fpga_rvalid_axi_s1_i; + input fabric_fpga_rvalid_axi_s2_i; + input fabric_fpga_sysrstn_i; + output [7:0] fabric_fpga_trigger_in_o; + input [7:0] fabric_fpga_trigger_out_i; + input [127:0] fabric_fpga_wdata_axi_m1_i; + input [127:0] fabric_fpga_wdata_axi_m2_i; + output [127:0] fabric_fpga_wdata_axi_s1_o; + output [127:0] fabric_fpga_wdata_axi_s2_o; + input fabric_fpga_wlast_axi_m1_i; + input fabric_fpga_wlast_axi_m2_i; + output fabric_fpga_wlast_axi_s1_o; + output fabric_fpga_wlast_axi_s2_o; + output fabric_fpga_wready_axi_m1_o; + output fabric_fpga_wready_axi_m2_o; + input fabric_fpga_wready_axi_s1_i; + input fabric_fpga_wready_axi_s2_i; + input [15:0] fabric_fpga_wstrb_axi_m1_i; + input [15:0] fabric_fpga_wstrb_axi_m2_i; + output [15:0] fabric_fpga_wstrb_axi_s1_o; + output [15:0] fabric_fpga_wstrb_axi_s2_o; + input fabric_fpga_wvalid_axi_m1_i; + input fabric_fpga_wvalid_axi_m2_i; + output fabric_fpga_wvalid_axi_s1_o; + output fabric_fpga_wvalid_axi_s2_o; + output [31:0] fabric_llpp0_araddr_s_o; + output [1:0] fabric_llpp0_arburst_s_o; + output [3:0] fabric_llpp0_arcache_s_o; + output [11:0] fabric_llpp0_arid_s_o; + output [7:0] fabric_llpp0_arlen_s_o; + output fabric_llpp0_arlock_s_o; + output [2:0] fabric_llpp0_arprot_s_o; + output [3:0] fabric_llpp0_arqos_s_o; + input fabric_llpp0_arready_s_i; + output [2:0] fabric_llpp0_arsize_s_o; + output fabric_llpp0_arvalid_s_o; + output [31:0] fabric_llpp0_awaddr_s_o; + output [1:0] fabric_llpp0_awburst_s_o; + output [3:0] fabric_llpp0_awcache_s_o; + output [11:0] fabric_llpp0_awid_s_o; + output [7:0] fabric_llpp0_awlen_s_o; + output fabric_llpp0_awlock_s_o; + output [2:0] fabric_llpp0_awprot_s_o; + output [3:0] fabric_llpp0_awqos_s_o; + input fabric_llpp0_awready_s_i; + output [2:0] fabric_llpp0_awsize_s_o; + output fabric_llpp0_awvalid_s_o; + input [11:0] fabric_llpp0_bid_s_i; + output fabric_llpp0_bready_s_o; + input [1:0] fabric_llpp0_bresp_s_i; + input fabric_llpp0_bvalid_s_i; + input [31:0] fabric_llpp0_rdata_s_i; + input [11:0] fabric_llpp0_rid_s_i; + input fabric_llpp0_rlast_s_i; + output fabric_llpp0_rready_s_o; + input [1:0] fabric_llpp0_rresp_s_i; + input fabric_llpp0_rvalid_s_i; + output [31:0] fabric_llpp0_wdata_s_o; + output fabric_llpp0_wlast_s_o; + input fabric_llpp0_wready_s_i; + output [3:0] fabric_llpp0_wstrb_s_o; + output fabric_llpp0_wvalid_s_o; + output [31:0] fabric_llpp1_araddr_s_o; + output [1:0] fabric_llpp1_arburst_s_o; + output [3:0] fabric_llpp1_arcache_s_o; + output [11:0] fabric_llpp1_arid_s_o; + output [7:0] fabric_llpp1_arlen_s_o; + output fabric_llpp1_arlock_s_o; + output [2:0] fabric_llpp1_arprot_s_o; + output [3:0] fabric_llpp1_arqos_s1_o; + input fabric_llpp1_arready_s_i; + output [2:0] fabric_llpp1_arsize_s_o; + output fabric_llpp1_arvalid_s_o; + output [31:0] fabric_llpp1_awaddr_s_o; + output [1:0] fabric_llpp1_awburst_s_o; + output [3:0] fabric_llpp1_awcache_s_o; + output [11:0] fabric_llpp1_awid_s_o; + output [7:0] fabric_llpp1_awlen_s_o; + output fabric_llpp1_awlock_s_o; + output [2:0] fabric_llpp1_awprot_s_o; + output [3:0] fabric_llpp1_awqos_s_o; + input fabric_llpp1_awready_s_i; + output [2:0] fabric_llpp1_awsize_s_o; + output fabric_llpp1_awvalid_s_o; + input [11:0] fabric_llpp1_bid_s_i; + output fabric_llpp1_bready_s_o; + input [1:0] fabric_llpp1_bresp_s_i; + input fabric_llpp1_bvalid_s_i; + input [31:0] fabric_llpp1_rdata_s_i; + input [11:0] fabric_llpp1_rid_s_i; + input fabric_llpp1_rlast_s_i; + output fabric_llpp1_rready_s_o; + input [1:0] fabric_llpp1_rresp_s_i; + input fabric_llpp1_rvalid_s_i; + output [31:0] fabric_llpp1_wdata_s_o; + output fabric_llpp1_wlast_s_o; + input fabric_llpp1_wready_s_i; + output [3:0] fabric_llpp1_wstrb_s_o; + output fabric_llpp1_wvalid_s_o; + output [31:0] fabric_llpp2_araddr_s_o; + output [1:0] fabric_llpp2_arburst_s_o; + output [3:0] fabric_llpp2_arcache_s_o; + output [11:0] fabric_llpp2_arid_s_o; + output [7:0] fabric_llpp2_arlen_s_o; + output fabric_llpp2_arlock_s_o; + output [2:0] fabric_llpp2_arprot_s_o; + output [3:0] fabric_llpp2_arqos_s_o; + input fabric_llpp2_arready_s_i; + output [2:0] fabric_llpp2_arsize_s_o; + output fabric_llpp2_arvalid_s_o; + output [31:0] fabric_llpp2_awaddr_s_o; + output [1:0] fabric_llpp2_awburst_s_o; + output [3:0] fabric_llpp2_awcache_s_o; + output [11:0] fabric_llpp2_awid_s_o; + output [7:0] fabric_llpp2_awlen_s_o; + output fabric_llpp2_awlock_s_o; + output [2:0] fabric_llpp2_awprot_s_o; + output [3:0] fabric_llpp2_awqos_s_o; + input fabric_llpp2_awready_s_i; + output [2:0] fabric_llpp2_awsize_s_o; + output fabric_llpp2_awvalid_s_o; + input [11:0] fabric_llpp2_bid_s_i; + output fabric_llpp2_bready_s_o; + input [1:0] fabric_llpp2_bresp_s_i; + input fabric_llpp2_bvalid_s_i; + input [31:0] fabric_llpp2_rdata_s_i; + input [11:0] fabric_llpp2_rid_s_i; + input fabric_llpp2_rlast_s_i; + output fabric_llpp2_rready_s_o; + input [1:0] fabric_llpp2_rresp_s_i; + input fabric_llpp2_rvalid_s_i; + output [31:0] fabric_llpp2_wdata_s_o; + output fabric_llpp2_wlast_s_o; + input fabric_llpp2_wready_s_i; + output [3:0] fabric_llpp2_wstrb_s_o; + output fabric_llpp2_wvalid_s_o; + output [31:0] fabric_llpp3_araddr_s_o; + output [1:0] fabric_llpp3_arburst_s_o; + output [3:0] fabric_llpp3_arcache_s_o; + output [11:0] fabric_llpp3_arid_s_o; + output [7:0] fabric_llpp3_arlen_s_o; + output fabric_llpp3_arlock_s_o; + output [2:0] fabric_llpp3_arprot_s_o; + output [3:0] fabric_llpp3_arqos_s_o; + input fabric_llpp3_arready_s_i; + output [2:0] fabric_llpp3_arsize_s_o; + output fabric_llpp3_arvalid_s_o; + output [31:0] fabric_llpp3_awaddr_s_o; + output [1:0] fabric_llpp3_awburst_s_o; + output [3:0] fabric_llpp3_awcache_s_o; + output [11:0] fabric_llpp3_awid_s_o; + output [7:0] fabric_llpp3_awlen_s_o; + output fabric_llpp3_awlock_s_o; + output [2:0] fabric_llpp3_awprot_s_o; + output [3:0] fabric_llpp3_awqos_s_o; + input fabric_llpp3_awready_s_i; + output [2:0] fabric_llpp3_awsize_s_o; + output fabric_llpp3_awvalid_s_o; + input [11:0] fabric_llpp3_bid_s_i; + output fabric_llpp3_bready_s_o; + input [1:0] fabric_llpp3_bresp_s_i; + input fabric_llpp3_bvalid_s_i; + input [31:0] fabric_llpp3_rdata_s_i; + input [11:0] fabric_llpp3_rid_s_i; + input fabric_llpp3_rlast_s_i; + output fabric_llpp3_rready_s_o; + input [1:0] fabric_llpp3_rresp_s_i; + input fabric_llpp3_rvalid_s_i; + output [31:0] fabric_llpp3_wdata_s_o; + output fabric_llpp3_wlast_s_o; + input fabric_llpp3_wready_s_i; + output [3:0] fabric_llpp3_wstrb_s_o; + output fabric_llpp3_wvalid_s_o; + input [9:0] fabric_lowskew_i; + output [1:0] fabric_lowskew_o; + input fabric_qos_pclk_i; + input [31:0] fabric_qos_ppaddr_i; + input fabric_qos_ppenable_i; + output [31:0] fabric_qos_pprdata_o; + output fabric_qos_ppready_o; + output fabric_qos_ppslverr_o; + input [31:0] fabric_qos_ppwdata_i; + input fabric_qos_ppwrite_i; + input fabric_qos_presetn_i; + input fabric_qos_psel_i; + output fabric_soc_mon_sensor_alarm_o; + input fabric_sysc_hold_on_debug_i; + output [31:0] fabric_tnd_fpga_apb_master_paddr_o; + output fabric_tnd_fpga_apb_master_penable_o; + input [31:0] fabric_tnd_fpga_apb_master_prdata_i; + input fabric_tnd_fpga_apb_master_pready_i; + output fabric_tnd_fpga_apb_master_psel_o; + input fabric_tnd_fpga_apb_master_pslverr_i; + output [31:0] fabric_tnd_fpga_apb_master_pwdata_o; + output fabric_tnd_fpga_apb_master_pwrite_o; + input fabric_tnd_fpga_atb_master_afready_i; + output fabric_tnd_fpga_atb_master_afvalid_o; + input [3:0] fabric_tnd_fpga_atb_master_atbytes_i; + input [127:0] fabric_tnd_fpga_atb_master_atdata_i; + input [6:0] fabric_tnd_fpga_atb_master_atid_i; + output fabric_tnd_fpga_atb_master_atready_o; + input fabric_tnd_fpga_atb_master_atvalid_i; + output fabric_tnd_fpga_atb_master_syncreq_o; + output [31:0] fabric_tnd_hssl_apb_master_paddr_o; + output fabric_tnd_hssl_apb_master_penable_o; + input [31:0] fabric_tnd_hssl_apb_master_prdata_i; + input fabric_tnd_hssl_apb_master_pready_i; + output fabric_tnd_hssl_apb_master_psel_o; + input fabric_tnd_hssl_apb_master_pslverr_i; + output [31:0] fabric_tnd_hssl_apb_master_pwdata_o; + output fabric_tnd_hssl_apb_master_pwrite_o; + output fabric_tnd_hssl_atb_master_afready_o; + input fabric_tnd_hssl_atb_master_afvalid_i; + output [3:0] fabric_tnd_hssl_atb_master_atbytes_o; + output [127:0] fabric_tnd_hssl_atb_master_atdata_o; + output [6:0] fabric_tnd_hssl_atb_master_atid_o; + input fabric_tnd_hssl_atb_master_atready_i; + output fabric_tnd_hssl_atb_master_atvalid_o; + input fabric_tnd_hssl_atb_master_syncreq_i; + output fabric_tnd_hssl_flushin_o; + output fabric_tnd_hssl_trigin_o; + output fabric_tnd_trace_clk_traceoutportintf_o; + output fabric_tnd_trace_ctl_traceoutportintf_o; + output [31:0] fabric_tnd_trace_data_traceoutportintf_o; + output [6:0] fabric_tst_pll_lock_o; + output [63:0] fabric_tsvalue_tsgen_fpga_o; + output fabric_watchdog0_signal_0_o; + output fabric_watchdog0_signal_1_o; + output fabric_watchdog1_signal_0_o; + output fabric_watchdog1_signal_1_o; + output fabric_watchdog2_signal_0_o; + output fabric_watchdog2_signal_1_o; + output fabric_watchdog3_signal_0_o; + output fabric_watchdog3_signal_1_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_SOC_INTERFACE_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o +, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i +, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o +, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o +, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i +, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o +, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o +, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o +, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i +, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o +, fabric_fpga_arqos_axi_s1_o, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o +, fabric_fpga_arcache_axi_s2_o, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i +, fabric_fpga_rid_axi_s2_i, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i +, fabric_fpga_awlen_axi_m1_i, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i +, fabric_fpga_arprot_axi_m2_i, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o +, fabric_fpga_ddr0_araddr_i, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i +, fabric_llpp0_araddr_s_o, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i +, fabric_llpp0_rid_s_i, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i +, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o +, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o +, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i +, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o, fabric_llpp1_arqos_s_o, fabric_spw_interrupts_toggle_o, fabric_spw_interrupts_o, fabric_fpga_dma_hs_rstn_i); + input [2:0] fabric_enable_TMR_i; + input fabric_erom_fpga_cpu0_dbgen_i; + input fabric_erom_fpga_cpu0_hiden_i; + input fabric_erom_fpga_cpu0_hniden_i; + input fabric_erom_fpga_cpu0_niden_i; + input fabric_erom_fpga_cpu1_dbgen_i; + input fabric_erom_fpga_cpu1_hiden_i; + input fabric_erom_fpga_cpu1_hniden_i; + input fabric_erom_fpga_cpu1_niden_i; + input fabric_erom_fpga_cpu2_dbgen_i; + input fabric_erom_fpga_cpu2_hiden_i; + input fabric_erom_fpga_cpu2_hniden_i; + input fabric_erom_fpga_cpu2_niden_i; + input fabric_erom_fpga_cpu3_dbgen_i; + input fabric_erom_fpga_cpu3_hiden_i; + input fabric_erom_fpga_cpu3_hniden_i; + input fabric_erom_fpga_cpu3_niden_i; + input fabric_erom_fpga_cs_dbgen_i; + input fabric_erom_fpga_cs_deviceen_i; + input fabric_erom_fpga_cs_niden_i; + input fabric_erom_fpga_cs_rst_n_i; + input fabric_erom_fpga_debug_en_i; + output fabric_flash_irq_o; + output fabric_flash_irq_toggle_o; + input [39:0] fabric_fpga_araddr_axi_m1_i; + input [39:0] fabric_fpga_araddr_axi_m2_i; + output [39:0] fabric_fpga_araddr_axi_s1_o; + output [39:0] fabric_fpga_araddr_axi_s2_o; + input [1:0] fabric_fpga_arburst_axi_m1_i; + input [1:0] fabric_fpga_arburst_axi_m2_i; + output [1:0] fabric_fpga_arburst_axi_s1_o; + output [1:0] fabric_fpga_arburst_axi_s2_o; + input [3:0] fabric_fpga_arcache_axi_m1_i; + input [3:0] fabric_fpga_arcache_axi_m2_i; + output [3:0] fabric_fpga_arcache_axi_s1_o; + output [3:0] fabric_fpga_arcache_axi_s2_o; + input [4:0] fabric_fpga_arid_axi_m1_i; + input [4:0] fabric_fpga_arid_axi_m2_i; + output [11:0] fabric_fpga_arid_axi_s1_o; + output [11:0] fabric_fpga_arid_axi_s2_o; + input [7:0] fabric_fpga_arlen_axi_m1_i; + input [7:0] fabric_fpga_arlen_axi_m2_i; + output [7:0] fabric_fpga_arlen_axi_s1_o; + output [7:0] fabric_fpga_arlen_axi_s2_o; + input fabric_fpga_arlock_axi_m1_i; + input fabric_fpga_arlock_axi_m2_i; + output fabric_fpga_arlock_axi_s1_o; + output fabric_fpga_arlock_axi_s2_o; + input [2:0] fabric_fpga_arprot_axi_m1_i; + input [2:0] fabric_fpga_arprot_axi_m2_i; + output [2:0] fabric_fpga_arprot_axi_s1_o; + output [2:0] fabric_fpga_arprot_axi_s2_o; + input [3:0] fabric_fpga_arqos_axi_m1_i; + input [3:0] fabric_fpga_arqos_axi_m2_i; + output [3:0] fabric_fpga_arqos_axi_s1_o; + output [3:0] fabric_fpga_arqos_axi_s2_o; + output fabric_fpga_arready_axi_m1_o; + output fabric_fpga_arready_axi_m2_o; + input fabric_fpga_arready_axi_s1_i; + input fabric_fpga_arready_axi_s2_i; + output [3:0] fabric_fpga_arregion_axi_s1_o; + output [3:0] fabric_fpga_arregion_axi_s2_o; + input [2:0] fabric_fpga_arsize_axi_m1_i; + input [2:0] fabric_fpga_arsize_axi_m2_i; + output [2:0] fabric_fpga_arsize_axi_s1_o; + output [2:0] fabric_fpga_arsize_axi_s2_o; + input fabric_fpga_arvalid_axi_m1_i; + input fabric_fpga_arvalid_axi_m2_i; + output fabric_fpga_arvalid_axi_s1_o; + output fabric_fpga_arvalid_axi_s2_o; + input [39:0] fabric_fpga_awaddr_axi_m1_i; + input [39:0] fabric_fpga_awaddr_axi_m2_i; + output [39:0] fabric_fpga_awaddr_axi_s1_o; + output [39:0] fabric_fpga_awaddr_axi_s2_o; + input [1:0] fabric_fpga_awburst_axi_m1_i; + input [1:0] fabric_fpga_awburst_axi_m2_i; + output [1:0] fabric_fpga_awburst_axi_s1_o; + output [1:0] fabric_fpga_awburst_axi_s2_o; + input [3:0] fabric_fpga_awcache_axi_m1_i; + input [3:0] fabric_fpga_awcache_axi_m2_i; + output [3:0] fabric_fpga_awcache_axi_s1_o; + output [3:0] fabric_fpga_awcache_axi_s2_o; + input [4:0] fabric_fpga_awid_axi_m1_i; + input [4:0] fabric_fpga_awid_axi_m2_i; + output [11:0] fabric_fpga_awid_axi_s1_o; + output [11:0] fabric_fpga_awid_axi_s2_o; + input [7:0] fabric_fpga_awlen_axi_m1_i; + input [7:0] fabric_fpga_awlen_axi_m2_i; + output [7:0] fabric_fpga_awlen_axi_s1_o; + output [7:0] fabric_fpga_awlen_axi_s2_o; + input fabric_fpga_awlock_axi_m1_i; + input fabric_fpga_awlock_axi_m2_i; + output fabric_fpga_awlock_axi_s1_o; + output fabric_fpga_awlock_axi_s2_o; + input [2:0] fabric_fpga_awprot_axi_m1_i; + input [2:0] fabric_fpga_awprot_axi_m2_i; + output [2:0] fabric_fpga_awprot_axi_s1_o; + output [2:0] fabric_fpga_awprot_axi_s2_o; + input [3:0] fabric_fpga_awqos_axi_m1_i; + input [3:0] fabric_fpga_awqos_axi_m2_i; + output [3:0] fabric_fpga_awqos_axi_s1_o; + output [3:0] fabric_fpga_awqos_axi_s2_o; + output fabric_fpga_awready_axi_m1_o; + output fabric_fpga_awready_axi_m2_o; + input fabric_fpga_awready_axi_s1_i; + input fabric_fpga_awready_axi_s2_i; + output [3:0] fabric_fpga_awregion_axi_s1_o; + output [3:0] fabric_fpga_awregion_axi_s2_o; + input [2:0] fabric_fpga_awsize_axi_m1_i; + input [2:0] fabric_fpga_awsize_axi_m2_i; + output [2:0] fabric_fpga_awsize_axi_s1_o; + output [2:0] fabric_fpga_awsize_axi_s2_o; + input fabric_fpga_awvalid_axi_m1_i; + input fabric_fpga_awvalid_axi_m2_i; + output fabric_fpga_awvalid_axi_s1_o; + output fabric_fpga_awvalid_axi_s2_o; + output [4:0] fabric_fpga_bid_axi_m1_o; + output [4:0] fabric_fpga_bid_axi_m2_o; + input [11:0] fabric_fpga_bid_axi_s1_i; + input [11:0] fabric_fpga_bid_axi_s2_i; + input fabric_fpga_bready_axi_m1_i; + input fabric_fpga_bready_axi_m2_i; + output fabric_fpga_bready_axi_s1_o; + output fabric_fpga_bready_axi_s2_o; + output [1:0] fabric_fpga_bresp_axi_m1_o; + output [1:0] fabric_fpga_bresp_axi_m2_o; + input [1:0] fabric_fpga_bresp_axi_s1_i; + input [1:0] fabric_fpga_bresp_axi_s2_i; + output fabric_fpga_bvalid_axi_m1_o; + output fabric_fpga_bvalid_axi_m2_o; + input fabric_fpga_bvalid_axi_s1_i; + input fabric_fpga_bvalid_axi_s2_i; + input [39:0] fabric_fpga_ddr0_araddr_i; + input [1:0] fabric_fpga_ddr0_arburst_i; + input [3:0] fabric_fpga_ddr0_arcache_i; + input [4:0] fabric_fpga_ddr0_arid_i; + input [7:0] fabric_fpga_ddr0_arlen_i; + input fabric_fpga_ddr0_arlock_i; + input [2:0] fabric_fpga_ddr0_arprot_i; + input [3:0] fabric_fpga_ddr0_arqos_i; + output fabric_fpga_ddr0_arready_o; + input [2:0] fabric_fpga_ddr0_arsize_i; + input fabric_fpga_ddr0_arvalid_i; + input [39:0] fabric_fpga_ddr0_awaddr_i; + input [1:0] fabric_fpga_ddr0_awburst_i; + input [3:0] fabric_fpga_ddr0_awcache_i; + input [4:0] fabric_fpga_ddr0_awid_i; + input [7:0] fabric_fpga_ddr0_awlen_i; + input fabric_fpga_ddr0_awlock_i; + input [2:0] fabric_fpga_ddr0_awprot_i; + input [3:0] fabric_fpga_ddr0_awqos_i; + output fabric_fpga_ddr0_awready_o; + input [2:0] fabric_fpga_ddr0_awsize_i; + input fabric_fpga_ddr0_awvalid_i; + output [4:0] fabric_fpga_ddr0_bid_o; + input fabric_fpga_ddr0_bready_i; + output [1:0] fabric_fpga_ddr0_bresp_o; + output fabric_fpga_ddr0_bvalid_o; + output [127:0] fabric_fpga_ddr0_rdata_o; + output [4:0] fabric_fpga_ddr0_rid_o; + output fabric_fpga_ddr0_rlast_o; + input fabric_fpga_ddr0_rready_i; + output [1:0] fabric_fpga_ddr0_rresp_o; + output fabric_fpga_ddr0_rvalid_o; + input [127:0] fabric_fpga_ddr0_wdata_i; + input fabric_fpga_ddr0_wlast_i; + output fabric_fpga_ddr0_wready_o; + input [15:0] fabric_fpga_ddr0_wstrb_i; + input fabric_fpga_ddr0_wvalid_i; + output [5:0] fabric_fpga_dma_ack_m1_o; + output [5:0] fabric_fpga_dma_ack_m2_o; + output [5:0] fabric_fpga_dma_finish_m1_o; + output [5:0] fabric_fpga_dma_finish_m2_o; + input [5:0] fabric_fpga_dma_hs_rstn_i; + input [5:0] fabric_fpga_dma_last_m1_i; + input [5:0] fabric_fpga_dma_last_m2_i; + input [5:0] fabric_fpga_dma_req_m1_i; + input [5:0] fabric_fpga_dma_req_m2_i; + input [5:0] fabric_fpga_dma_single_m1_i; + input [5:0] fabric_fpga_dma_single_m2_i; + input [59:0] fabric_fpga_events60_i; + input [119:0] fabric_fpga_interrupt_in_i; + input [9:0] fabric_fpga_nic_rstn_i; + output [31:0] fabric_fpga_paddr_apb_o; + output fabric_fpga_penable_apb_o; + input fabric_fpga_pmrstn_i; + input [31:0] fabric_fpga_prdata_apb_i; + input fabric_fpga_pready_apb_i; + output fabric_fpga_psel_apb_o; + input fabric_fpga_pslverr_apb_i; + output [31:0] fabric_fpga_pwdata_apb_o; + output fabric_fpga_pwrite_apb_o; + output [127:0] fabric_fpga_rdata_axi_m1_o; + output [127:0] fabric_fpga_rdata_axi_m2_o; + input [127:0] fabric_fpga_rdata_axi_s1_i; + input [127:0] fabric_fpga_rdata_axi_s2_i; + output [4:0] fabric_fpga_rid_axi_m1_o; + output [4:0] fabric_fpga_rid_axi_m2_o; + input [11:0] fabric_fpga_rid_axi_s1_i; + input [11:0] fabric_fpga_rid_axi_s2_i; + output fabric_fpga_rlast_axi_m1_o; + output fabric_fpga_rlast_axi_m2_o; + input fabric_fpga_rlast_axi_s1_i; + input fabric_fpga_rlast_axi_s2_i; + input fabric_fpga_rready_axi_m1_i; + input fabric_fpga_rready_axi_m2_i; + output fabric_fpga_rready_axi_s1_o; + output fabric_fpga_rready_axi_s2_o; + output [1:0] fabric_fpga_rresp_axi_m1_o; + output [1:0] fabric_fpga_rresp_axi_m2_o; + input [1:0] fabric_fpga_rresp_axi_s1_i; + input [1:0] fabric_fpga_rresp_axi_s2_i; + output fabric_fpga_rvalid_axi_m1_o; + output fabric_fpga_rvalid_axi_m2_o; + input fabric_fpga_rvalid_axi_s1_i; + input fabric_fpga_rvalid_axi_s2_i; + input fabric_fpga_sysrstn_i; + output [7:0] fabric_fpga_trigger_in_o; + input [7:0] fabric_fpga_trigger_out_i; + input [127:0] fabric_fpga_wdata_axi_m1_i; + input [127:0] fabric_fpga_wdata_axi_m2_i; + output [127:0] fabric_fpga_wdata_axi_s1_o; + output [127:0] fabric_fpga_wdata_axi_s2_o; + input fabric_fpga_wlast_axi_m1_i; + input fabric_fpga_wlast_axi_m2_i; + output fabric_fpga_wlast_axi_s1_o; + output fabric_fpga_wlast_axi_s2_o; + output fabric_fpga_wready_axi_m1_o; + output fabric_fpga_wready_axi_m2_o; + input fabric_fpga_wready_axi_s1_i; + input fabric_fpga_wready_axi_s2_i; + input [15:0] fabric_fpga_wstrb_axi_m1_i; + input [15:0] fabric_fpga_wstrb_axi_m2_i; + output [15:0] fabric_fpga_wstrb_axi_s1_o; + output [15:0] fabric_fpga_wstrb_axi_s2_o; + input fabric_fpga_wvalid_axi_m1_i; + input fabric_fpga_wvalid_axi_m2_i; + output fabric_fpga_wvalid_axi_s1_o; + output fabric_fpga_wvalid_axi_s2_o; + output [31:0] fabric_llpp0_araddr_s_o; + output [1:0] fabric_llpp0_arburst_s_o; + output [3:0] fabric_llpp0_arcache_s_o; + output [11:0] fabric_llpp0_arid_s_o; + output [7:0] fabric_llpp0_arlen_s_o; + output fabric_llpp0_arlock_s_o; + output [2:0] fabric_llpp0_arprot_s_o; + output [3:0] fabric_llpp0_arqos_s_o; + input fabric_llpp0_arready_s_i; + output [2:0] fabric_llpp0_arsize_s_o; + output fabric_llpp0_arvalid_s_o; + output [31:0] fabric_llpp0_awaddr_s_o; + output [1:0] fabric_llpp0_awburst_s_o; + output [3:0] fabric_llpp0_awcache_s_o; + output [11:0] fabric_llpp0_awid_s_o; + output [7:0] fabric_llpp0_awlen_s_o; + output fabric_llpp0_awlock_s_o; + output [2:0] fabric_llpp0_awprot_s_o; + output [3:0] fabric_llpp0_awqos_s_o; + input fabric_llpp0_awready_s_i; + output [2:0] fabric_llpp0_awsize_s_o; + output fabric_llpp0_awvalid_s_o; + input [11:0] fabric_llpp0_bid_s_i; + output fabric_llpp0_bready_s_o; + input [1:0] fabric_llpp0_bresp_s_i; + input fabric_llpp0_bvalid_s_i; + input [31:0] fabric_llpp0_rdata_s_i; + input [11:0] fabric_llpp0_rid_s_i; + input fabric_llpp0_rlast_s_i; + output fabric_llpp0_rready_s_o; + input [1:0] fabric_llpp0_rresp_s_i; + input fabric_llpp0_rvalid_s_i; + output [31:0] fabric_llpp0_wdata_s_o; + output fabric_llpp0_wlast_s_o; + input fabric_llpp0_wready_s_i; + output [3:0] fabric_llpp0_wstrb_s_o; + output fabric_llpp0_wvalid_s_o; + output [31:0] fabric_llpp1_araddr_s_o; + output [1:0] fabric_llpp1_arburst_s_o; + output [3:0] fabric_llpp1_arcache_s_o; + output [11:0] fabric_llpp1_arid_s_o; + output [7:0] fabric_llpp1_arlen_s_o; + output fabric_llpp1_arlock_s_o; + output [2:0] fabric_llpp1_arprot_s_o; + output [3:0] fabric_llpp1_arqos_s_o; + input fabric_llpp1_arready_s_i; + output [2:0] fabric_llpp1_arsize_s_o; + output fabric_llpp1_arvalid_s_o; + output [31:0] fabric_llpp1_awaddr_s_o; + output [1:0] fabric_llpp1_awburst_s_o; + output [3:0] fabric_llpp1_awcache_s_o; + output [11:0] fabric_llpp1_awid_s_o; + output [7:0] fabric_llpp1_awlen_s_o; + output fabric_llpp1_awlock_s_o; + output [2:0] fabric_llpp1_awprot_s_o; + output [3:0] fabric_llpp1_awqos_s_o; + input fabric_llpp1_awready_s_i; + output [2:0] fabric_llpp1_awsize_s_o; + output fabric_llpp1_awvalid_s_o; + input [11:0] fabric_llpp1_bid_s_i; + output fabric_llpp1_bready_s_o; + input [1:0] fabric_llpp1_bresp_s_i; + input fabric_llpp1_bvalid_s_i; + input [31:0] fabric_llpp1_rdata_s_i; + input [11:0] fabric_llpp1_rid_s_i; + input fabric_llpp1_rlast_s_i; + output fabric_llpp1_rready_s_o; + input [1:0] fabric_llpp1_rresp_s_i; + input fabric_llpp1_rvalid_s_i; + output [31:0] fabric_llpp1_wdata_s_o; + output fabric_llpp1_wlast_s_o; + input fabric_llpp1_wready_s_i; + output [3:0] fabric_llpp1_wstrb_s_o; + output fabric_llpp1_wvalid_s_o; + output [31:0] fabric_llpp2_araddr_s_o; + output [1:0] fabric_llpp2_arburst_s_o; + output [3:0] fabric_llpp2_arcache_s_o; + output [11:0] fabric_llpp2_arid_s_o; + output [7:0] fabric_llpp2_arlen_s_o; + output fabric_llpp2_arlock_s_o; + output [2:0] fabric_llpp2_arprot_s_o; + output [3:0] fabric_llpp2_arqos_s_o; + input fabric_llpp2_arready_s_i; + output [2:0] fabric_llpp2_arsize_s_o; + output fabric_llpp2_arvalid_s_o; + output [31:0] fabric_llpp2_awaddr_s_o; + output [1:0] fabric_llpp2_awburst_s_o; + output [3:0] fabric_llpp2_awcache_s_o; + output [11:0] fabric_llpp2_awid_s_o; + output [7:0] fabric_llpp2_awlen_s_o; + output fabric_llpp2_awlock_s_o; + output [2:0] fabric_llpp2_awprot_s_o; + output [3:0] fabric_llpp2_awqos_s_o; + input fabric_llpp2_awready_s_i; + output [2:0] fabric_llpp2_awsize_s_o; + output fabric_llpp2_awvalid_s_o; + input [11:0] fabric_llpp2_bid_s_i; + output fabric_llpp2_bready_s_o; + input [1:0] fabric_llpp2_bresp_s_i; + input fabric_llpp2_bvalid_s_i; + input [31:0] fabric_llpp2_rdata_s_i; + input [11:0] fabric_llpp2_rid_s_i; + input fabric_llpp2_rlast_s_i; + output fabric_llpp2_rready_s_o; + input [1:0] fabric_llpp2_rresp_s_i; + input fabric_llpp2_rvalid_s_i; + output [31:0] fabric_llpp2_wdata_s_o; + output fabric_llpp2_wlast_s_o; + input fabric_llpp2_wready_s_i; + output [3:0] fabric_llpp2_wstrb_s_o; + output fabric_llpp2_wvalid_s_o; + output [31:0] fabric_llpp3_araddr_s_o; + output [1:0] fabric_llpp3_arburst_s_o; + output [3:0] fabric_llpp3_arcache_s_o; + output [11:0] fabric_llpp3_arid_s_o; + output [7:0] fabric_llpp3_arlen_s_o; + output fabric_llpp3_arlock_s_o; + output [2:0] fabric_llpp3_arprot_s_o; + output [3:0] fabric_llpp3_arqos_s_o; + input fabric_llpp3_arready_s_i; + output [2:0] fabric_llpp3_arsize_s_o; + output fabric_llpp3_arvalid_s_o; + output [31:0] fabric_llpp3_awaddr_s_o; + output [1:0] fabric_llpp3_awburst_s_o; + output [3:0] fabric_llpp3_awcache_s_o; + output [11:0] fabric_llpp3_awid_s_o; + output [7:0] fabric_llpp3_awlen_s_o; + output fabric_llpp3_awlock_s_o; + output [2:0] fabric_llpp3_awprot_s_o; + output [3:0] fabric_llpp3_awqos_s_o; + input fabric_llpp3_awready_s_i; + output [2:0] fabric_llpp3_awsize_s_o; + output fabric_llpp3_awvalid_s_o; + input [11:0] fabric_llpp3_bid_s_i; + output fabric_llpp3_bready_s_o; + input [1:0] fabric_llpp3_bresp_s_i; + input fabric_llpp3_bvalid_s_i; + input [31:0] fabric_llpp3_rdata_s_i; + input [11:0] fabric_llpp3_rid_s_i; + input fabric_llpp3_rlast_s_i; + output fabric_llpp3_rready_s_o; + input [1:0] fabric_llpp3_rresp_s_i; + input fabric_llpp3_rvalid_s_i; + output [31:0] fabric_llpp3_wdata_s_o; + output fabric_llpp3_wlast_s_o; + input fabric_llpp3_wready_s_i; + output [3:0] fabric_llpp3_wstrb_s_o; + output fabric_llpp3_wvalid_s_o; + input [18:2] fabric_lowskew_i; + output [1:0] fabric_lowskew_o; + input [31:0] fabric_qos_ppaddr_i; + input fabric_qos_ppenable_i; + output [31:0] fabric_qos_pprdata_o; + output fabric_qos_ppready_o; + output fabric_qos_ppslverr_o; + input [31:0] fabric_qos_ppwdata_i; + input fabric_qos_ppwrite_i; + input fabric_qos_presetn_i; + input fabric_qos_psel_i; + output fabric_soc_mon_sensor_alarm_o; + output [2:0] fabric_spw_interrupts_o; + output [2:0] fabric_spw_interrupts_toggle_o; + input fabric_sysc_hold_on_debug_i; + output [31:0] fabric_tnd_fpga_apb_master_paddr_o; + output fabric_tnd_fpga_apb_master_penable_o; + input [31:0] fabric_tnd_fpga_apb_master_prdata_i; + input fabric_tnd_fpga_apb_master_pready_i; + output fabric_tnd_fpga_apb_master_psel_o; + input fabric_tnd_fpga_apb_master_pslverr_i; + output [31:0] fabric_tnd_fpga_apb_master_pwdata_o; + output fabric_tnd_fpga_apb_master_pwrite_o; + input fabric_tnd_fpga_atb_master_afready_i; + output fabric_tnd_fpga_atb_master_afvalid_o; + input [3:0] fabric_tnd_fpga_atb_master_atbytes_i; + input [127:0] fabric_tnd_fpga_atb_master_atdata_i; + input [6:0] fabric_tnd_fpga_atb_master_atid_i; + output fabric_tnd_fpga_atb_master_atready_o; + input fabric_tnd_fpga_atb_master_atvalid_i; + output fabric_tnd_fpga_atb_master_syncreq_o; + output [31:0] fabric_tnd_hssl_apb_master_paddr_o; + output fabric_tnd_hssl_apb_master_penable_o; + input [31:0] fabric_tnd_hssl_apb_master_prdata_i; + input fabric_tnd_hssl_apb_master_pready_i; + output fabric_tnd_hssl_apb_master_psel_o; + input fabric_tnd_hssl_apb_master_pslverr_i; + output [31:0] fabric_tnd_hssl_apb_master_pwdata_o; + output fabric_tnd_hssl_apb_master_pwrite_o; + output fabric_tnd_hssl_atb_master_afready_o; + input fabric_tnd_hssl_atb_master_afvalid_i; + output [3:0] fabric_tnd_hssl_atb_master_atbytes_o; + output [127:0] fabric_tnd_hssl_atb_master_atdata_o; + output [6:0] fabric_tnd_hssl_atb_master_atid_o; + input fabric_tnd_hssl_atb_master_atready_i; + output fabric_tnd_hssl_atb_master_atvalid_o; + input fabric_tnd_hssl_atb_master_syncreq_i; + output fabric_tnd_hssl_flushin_o; + output fabric_tnd_hssl_trigin_o; + output fabric_tnd_trace_clk_traceoutportintf_o; + output fabric_tnd_trace_ctl_traceoutportintf_o; + output [31:0] fabric_tnd_trace_data_traceoutportintf_o; + output [6:0] fabric_tst_pll_lock_o; + output [63:0] fabric_tsvalue_tsgen_fpga_o; + output fabric_watchdog0_signal_0_o; + output fabric_watchdog0_signal_1_o; + output fabric_watchdog1_signal_0_o; + output fabric_watchdog1_signal_1_o; + output fabric_watchdog2_signal_0_o; + output fabric_watchdog2_signal_1_o; + output fabric_watchdog3_signal_0_o; + output fabric_watchdog3_signal_1_o; + parameter ahb_config = 0; + parameter bsm_config = 0; +endmodule + +(* blackbox *) +module NX_WFG(SI, ZI, RDY, SO, ZO); + input RDY; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter location = ""; + parameter mode = 1'b0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 1; + parameter wfg_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_WFG_L(R, SI, ZI, RDY, SO, ZO); + input R; + input RDY; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter location = ""; + parameter mode = 1'b0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 1; + parameter wfg_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_WFG_U(R, SI, ZI, SO, ZO); + input R; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter div_phase = 1'b0; + parameter div_ratio = 0; + parameter location = ""; + parameter mode = 0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 0; + parameter reset_on_cal_lock_n = 1'b0; + parameter reset_on_pll_lock_n = 1'b0; + parameter reset_on_pll_locka_n = 1'b0; + parameter wfg_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO +, AO, BO, AI, DI, DO); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CDRSTI; + output CDRSTO; + input [5:0] CI; + input CK1; + input CK2; + output [5:0] CO; + input CSRSTI; + output CSRSTO; + input DDRSTI; + output DDRSTO; + input [5:0] DI; + output [5:0] DO; + input DSRSTI; + output DSRSTO; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + parameter use_cdest_arst = 1'b0; + parameter use_csrc_arst = 1'b0; + parameter use_ddest_arst = 1'b0; + parameter use_dsrc_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO); + input [35:0] I; + output [35:0] O; + input [5:0] RAI; + output [5:0] RAO; + input RCK; + output REQ; + input RRSTI; + input [5:0] WAI; + output [5:0] WAO; + input WCK; + input WE; + input WEA; + output WEQ; + input WRSTI; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO); + input [17:0] I; + output [17:0] O; + input [6:0] RAI; + output [6:0] RAO; + input RCK; + output [1:0] REQ; + input RRSTI; + input [6:0] WAI; + output [6:0] WAO; + input WCK; + input WE; + input WEA; + output [1:0] WEQ; + input WRSTI; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); + output [17:0] AO; + input [4:0] ARA; + output [17:0] BO; + input [4:0] BRA; + input [17:0] I; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); + input [35:0] I; + output [35:0] O; + input [4:0] RA; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); + input [17:0] I; + output [17:0] O; + input [5:0] RA; + input [5:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; +endmodule + +(* blackbox *) +module SMACC24x18_1DSP(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [55:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +(* blackbox *) +module SMACC24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +(* blackbox *) +module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + input we; + parameter STAGE_1 = "false"; + parameter STAGE_2 = "false"; + parameter STAGE_3 = "false"; + parameter STAGE_4 = "false"; +endmodule + +(* blackbox *) +module SMUL24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [54:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +(* blackbox *) +module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [97:0] Z; + input clk; + input rst; + input we; + parameter STAGE_1 = "false"; + parameter STAGE_2 = "false"; + parameter STAGE_3 = "false"; +endmodule + +(* blackbox *) +module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [91:0] Z; + input clk; + input rst; + input we; +endmodule + +(* blackbox *) +module SMUL47x35_4DSP(clk, rst, A, B, Z); + input [46:0] A; + input [34:0] B; + output [80:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMADD24_2DSP(clk, rst, A, B, C, Z); + input [23:0] A; + input [31:0] B; + input [55:0] C; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [15:0] B; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [59:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL24x36_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [35:0] B; + output [59:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [83:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +(* blackbox *) +module UMUL48x36_4DSP(clk, rst, A, B, Z); + input [47:0] A; + input [35:0] B; + output [83:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index eda65b66b..b37bed164 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -160,7 +160,7 @@ struct SynthNanoXplorePass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -specify +/nanoxplore/cells_sim.v"); + run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } From b0c4add642f23f899f5aac69c5970d9e34e1a921 Mon Sep 17 00:00:00 2001 From: Lofty Date: Fri, 1 Mar 2024 13:41:25 +0100 Subject: [PATCH 012/342] Added lutram --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/cells_bb.v | 50 ++++++++++++------------ techlibs/nanoxplore/cells_map.v | 12 ++++++ techlibs/nanoxplore/cells_sim.v | 51 +++++++++++++++++++++++++ techlibs/nanoxplore/drams.txt | 27 +++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 41 ++++++++++++++++++-- tests/arch/nanoxplore/lutram.ys | 8 ++++ 7 files changed, 161 insertions(+), 29 deletions(-) create mode 100644 techlibs/nanoxplore/drams.txt create mode 100644 tests/arch/nanoxplore/lutram.ys diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 0f7bcdbed..d7331f5de 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -6,3 +6,4 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 7ebad4ae8..6aa981529 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -32930,31 +32930,31 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); parameter wck_edge = 1'b0; endmodule -(* blackbox *) -module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); - input [35:0] I; - output [35:0] O; - input [4:0] RA; - input [4:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); - input [17:0] I; - output [17:0] O; - input [5:0] RA; - input [5:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule +//(* blackbox *) +//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); +// input [35:0] I; +// output [35:0] O; +// input [4:0] RA; +// input [4:0] WA; +// input WCK; +// input WE; +// input WEA; +// parameter mem_ctxt = ""; +// parameter wck_edge = 1'b0; +//endmodule +// +//(* blackbox *) +//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); +// input [17:0] I; +// output [17:0] O; +// input [5:0] RA; +// input [5:0] WA; +// input WCK; +// input WE; +// input WEA; +// parameter mem_ctxt = ""; +// parameter wck_edge = 1'b0; +//endmodule (* blackbox *) module SMACC24x18_1DSP(clk, rst, A, B, Z); diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index efa2a2af5..9728922f3 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -66,3 +66,15 @@ endmodule module \$_SDFF_NP1_ (input D, C, R, output Q); NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule + +module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule + +module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 1f04b216e..2a4b5b00f 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -9,6 +9,7 @@ assign O = I1 ? s3[1] : s3[0]; endmodule +(* abc9_box, lib_whitebox *) module NX_DFF(input I, CK, L, R, output reg O); parameter dff_ctxt = 1'bx; @@ -34,8 +35,58 @@ always @(posedge clock, posedge async_reset) endmodule +(* abc9_box, lib_whitebox *) module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); parameter add_carry = 0; assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI; + +endmodule + +(* abc9_box, lib_whitebox *) +module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O); + +parameter wck_edge = 1'b0; +parameter mem_ctxt = 1152'b0; + +reg [17:0] mem [63:0]; + +integer i; +initial begin + for (i = 0; i < 64; i = i + 1) + mem[i] = mem_ctxt[18*i +: 18]; +end + +wire clock = WCK ^ wck_edge; + +always @(posedge clock) + if (WE && WEA) + mem[WA] <= I; + +assign O = mem[RA]; + +endmodule + +(* abc9_box, lib_whitebox *) +module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O); + +parameter wck_edge = 1'b0; +parameter mem_ctxt = 1152'b0; + +reg [35:0] mem [31:0]; + +integer i; +initial begin + for (i = 0; i < 32; i = i + 1) + mem[i] = mem_ctxt[36*i +: 36]; +end + +wire clock = WCK ^ wck_edge; + +always @(posedge clock) + if (WE && WEA) + mem[WA] <= I; + +assign O = mem[RA]; + endmodule diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/drams.txt new file mode 100644 index 000000000..370b62b16 --- /dev/null +++ b/techlibs/nanoxplore/drams.txt @@ -0,0 +1,27 @@ +ram distributed $__NX_XRFB_64x18_ { + abits 6; + width 18; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port ar "R" { + } +} + +ram distributed $__NX_XRFB_32x36_ { + abits 5; + width 36; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port ar "R" { + } +} \ No newline at end of file diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index b37bed164..97c4a21a4 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -73,6 +73,18 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); + log(" -nolutram\n"); + log(" do not use LUT RAM cells in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not map multipliers to NX_DSP cells\n"); + log("\n"); + log(" -noiopad\n"); + log(" do not instantiate IO buffers\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -80,7 +92,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy; + bool flatten, abc9, nocy, nolutram, nobram, nodsp, noiopad; void clear_flags() override { @@ -90,6 +102,10 @@ struct SynthNanoXplorePass : public ScriptPass flatten = true; abc9 = false; nocy = false; + nolutram = false; + nobram = false; + nodsp = false; + noiopad = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -136,12 +152,28 @@ struct SynthNanoXplorePass : public ScriptPass nocy = true; continue; } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; + continue; + } break; } extra_args(args, argidx, design); if (family.empty()) { - log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); + //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; } @@ -190,8 +222,9 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); } - if (check_label("map_ram")) - { + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { + run("memory_libmap -lib +/nanoxplore/drams.txt"); + run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_"); } if (check_label("map_ffram")) diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys new file mode 100644 index 000000000..97035b64c --- /dev/null +++ b/tests/arch/nanoxplore/lutram.ys @@ -0,0 +1,8 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +synth_nanoxplore -noiopad +cd lutram_1w1r +select -assert-count 1 t:NX_XRFB_64x18 +select -assert-count 8 t:NX_DFF +select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D + From 65d2ebac9d941b854649aa0c118de629999fb236 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 13:51:56 +0100 Subject: [PATCH 013/342] fix test --- tests/arch/nanoxplore/lutram.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 97035b64c..669cb0007 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -1,6 +1,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -synth_nanoxplore -noiopad +synth_nanoxplore cd lutram_1w1r select -assert-count 1 t:NX_XRFB_64x18 select -assert-count 8 t:NX_DFF From 4c1f84a686ff86fc370690840643ee0470075990 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 13:52:11 +0100 Subject: [PATCH 014/342] add io mapping --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/io_map.v | 8 ++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 18 ++++++++++++------ 3 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 techlibs/nanoxplore/io_map.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index d7331f5de..030cabd64 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -7,3 +7,4 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) diff --git a/techlibs/nanoxplore/io_map.v b/techlibs/nanoxplore/io_map.v new file mode 100644 index 000000000..42fac4619 --- /dev/null +++ b/techlibs/nanoxplore/io_map.v @@ -0,0 +1,8 @@ +module \$__BEYOND_IBUF (input PAD, output O); + NX_IOB_I _TECHMAP_REPLACE_ (.IO(PAD), .O(O), .C(1'b0)); +endmodule + +module \$__BEYOND_OBUF (output PAD, input I); + NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1)); +endmodule + diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 97c4a21a4..d5e77daaa 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -82,8 +82,8 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nodsp\n"); log(" do not map multipliers to NX_DSP cells\n"); log("\n"); - log(" -noiopad\n"); - log(" do not instantiate IO buffers\n"); + log(" -iopad\n"); + log(" insert IO buffers\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -92,7 +92,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, nolutram, nobram, nodsp, noiopad; + bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad; void clear_flags() override { @@ -105,7 +105,7 @@ struct SynthNanoXplorePass : public ScriptPass nolutram = false; nobram = false; nodsp = false; - noiopad = false; + iopad = false; } void execute(std::vector args, RTLIL::Design *design) override @@ -164,8 +164,8 @@ struct SynthNanoXplorePass : public ScriptPass nodsp = true; continue; } - if (args[argidx] == "-noiopad") { - noiopad = true; + if (args[argidx] == "-iopad") { + iopad = true; continue; } break; @@ -240,6 +240,12 @@ struct SynthNanoXplorePass : public ScriptPass run("techmap"); else run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v"); + if (help_mode || iopad) { + run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')"); + run("techmap -map +/nanoxplore/io_map.v"); + run("attrmvcp -attr src -attr LOC t:NX_IOB_O n:*"); + run("attrmvcp -attr src -attr LOC -driven t:NX_IOB_I n:*"); + } run("opt -fast"); } From 74289b733968f4f4b41fd6ed31b02114f3a492dc Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 15:25:24 +0100 Subject: [PATCH 015/342] remove init from sdff --- techlibs/nanoxplore/cells_map.v | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 9728922f3..54f2414c8 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -52,18 +52,22 @@ module aldff(input D, C, L, AD, output Q); endmodule module \$_SDFF_PP0_ (input D, C, R, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule module \$_SDFF_PP1_ (input D, C, R, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule module \$_SDFF_NP0_ (input D, C, R, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule module \$_SDFF_NP1_ (input D, C, R, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule From 989eef29b2c317c5a9724a848b8f3b64ffb166b7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2024 16:19:00 +0100 Subject: [PATCH 016/342] produce less cells --- techlibs/nanoxplore/cells_sim.v | 1 + techlibs/nanoxplore/synth_nanoxplore.cc | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 2a4b5b00f..35b1574ba 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -1,3 +1,4 @@ +(* abc9_lut=1 *) module NX_LUT(input I1, I2, I3, I4, output O); parameter lut_table = 16'h0000; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index d5e77daaa..c4c625cb5 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -229,9 +229,10 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffram")) { - run("opt -fast -mux_undef -undriven -fine"); + //run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); - run("opt -undriven -fine -mux_undef"); + run("opt -full"); + //run("opt -undriven -fine -mux_undef"); } if (check_label("map_gates")) From 9700971a8ad95031caa6a23e17b9d861db73c1c2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 6 Mar 2024 14:45:49 +0100 Subject: [PATCH 017/342] just copy LOC --- techlibs/nanoxplore/synth_nanoxplore.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index c4c625cb5..75168adcc 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -244,8 +244,8 @@ struct SynthNanoXplorePass : public ScriptPass if (help_mode || iopad) { run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')"); run("techmap -map +/nanoxplore/io_map.v"); - run("attrmvcp -attr src -attr LOC t:NX_IOB_O n:*"); - run("attrmvcp -attr src -attr LOC -driven t:NX_IOB_I n:*"); + run("attrmvcp -attr LOC t:NX_IOB_O n:*"); + run("attrmvcp -attr LOC -driven t:NX_IOB_I n:*"); } run("opt -fast"); } From cfce7dd2f8b877213731a8abc3ee250c1d66515f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Mar 2024 10:42:14 +0100 Subject: [PATCH 018/342] remove soc --- techlibs/nanoxplore/cells_bb.v | 23061 ------------------------------- 1 file changed, 23061 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 6aa981529..01fc0e3f3 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -8222,1385 +8222,6 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D parameter tx_usrclk_use_pcs_clk_2 = 1'b0; endmodule -(* blackbox *) -module NX_R5_L(A_CKEM_I, A_CKEP_I, A_CKES_I, AR_A_I32, AR_A_I31, AR_A_I30, AR_A_I29, AR_A_I28, AR_A_I27, AR_A_I26, AR_A_I25, AR_A_I24, AR_A_I23, AR_A_I22, AR_A_I21, AR_A_I20, AR_A_I19, AR_A_I18, AR_A_I17, AR_A_I16, AR_A_I15 -, AR_A_I14, AR_A_I13, AR_A_I12, AR_A_I11, AR_A_I10, AR_A_I9, AR_A_I8, AR_A_I7, AR_A_I6, AR_A_I5, AR_A_I4, AR_A_I3, AR_A_I2, AR_A_I1, AR_BU_I2, AR_BU_I1, AR_CH_I4, AR_CH_I3, AR_CH_I2, AR_CH_I1, AR_IDS_I8 -, AR_IDS_I7, AR_IDS_I6, AR_IDS_I5, AR_IDS_I4, AR_IDS_I3, AR_IDS_I2, AR_IDS_I1, AR_LE_I4, AR_LE_I3, AR_LE_I2, AR_LE_I1, AR_LK_I2, AR_LK_I1, AR_PR_I3, AR_PR_I2, AR_PR_I1, AR_RYM_I, AR_RYP_I, AR_SZ_I3, AR_SZ_I2, AR_SZ_I1 -, AR_VD_I, AT_RS_I, AW_A_I32, AW_A_I31, AW_A_I30, AW_A_I29, AW_A_I28, AW_A_I27, AW_A_I26, AW_A_I25, AW_A_I24, AW_A_I23, AW_A_I22, AW_A_I21, AW_A_I20, AW_A_I19, AW_A_I18, AW_A_I17, AW_A_I16, AW_A_I15, AW_A_I14 -, AW_A_I13, AW_A_I12, AW_A_I11, AW_A_I10, AW_A_I9, AW_A_I8, AW_A_I7, AW_A_I6, AW_A_I5, AW_A_I4, AW_A_I3, AW_A_I2, AW_A_I1, AW_BU_I2, AW_BU_I1, AW_CH_I4, AW_CH_I3, AW_CH_I2, AW_CH_I1, AW_IDS_I8, AW_IDS_I7 -, AW_IDS_I6, AW_IDS_I5, AW_IDS_I4, AW_IDS_I3, AW_IDS_I2, AW_IDS_I1, AW_LE_I4, AW_LE_I3, AW_LE_I2, AW_LE_I1, AW_LK_I2, AW_LK_I1, AW_PR_I3, AW_PR_I2, AW_PR_I1, AW_RYM_I, AW_RYP_I, AW_SZ_I3, AW_SZ_I2, AW_SZ_I1, AW_VD_I -, B_IDM_I4, B_IDM_I3, B_IDM_I2, B_IDM_I1, B_IDP_I4, B_IDP_I3, B_IDP_I2, B_IDP_I1, B_RDY_I, B_RSPM_I2, B_RSPM_I1, B_RSPP_I2, B_RSPP_I1, B_VDM_I, B_VDP_I, CDB_PW_I, CDB_RS_I, CFG_EE_I, CFG_IE_I, CFG_NM_I, CK_I -, CS_PW_I, DB_E_I, DB_NCK_I, DB_RA_I20, DB_RA_I19, DB_RA_I18, DB_RA_I17, DB_RA_I16, DB_RA_I15, DB_RA_I14, DB_RA_I13, DB_RA_I12, DB_RA_I11, DB_RA_I10, DB_RA_I9, DB_RA_I8, DB_RA_I7, DB_RA_I6, DB_RA_I5, DB_RA_I4, DB_RA_I3 -, DB_RA_I2, DB_RA_I1, DB_RAV_I, DB_SA_I20, DB_SA_I19, DB_SA_I18, DB_SA_I17, DB_SA_I16, DB_SA_I15, DB_SA_I14, DB_SA_I13, DB_SA_I12, DB_SA_I11, DB_SA_I10, DB_SA_I9, DB_SA_I8, DB_SA_I7, DB_SA_I6, DB_SA_I5, DB_SA_I4, DB_SA_I3 -, DB_SA_I2, DB_SA_I1, DB_SAV_I, DEV_E_I, DFTS_I8, DFTS_I7, DFTS_I6, DFTS_I5, DFTS_I4, DFTS_I3, DFTS_I2, DFTS_I1, E_DB_I, ERR_R_I, EVENT_I, GID_I4, GID_I3, GID_I2, GID_I1, INIT_P_I, INIT_R_I -, LOC_R_I, NCPUH_I, NET_RS_I, N_FIQ_I, N_IDE_I, N_IRQ_I, N_PRS_I, N_RS_I, N_SPRS_I, N_TRS_I, P_A_I29, P_A_I28, P_A_I27, P_A_I26, P_A_I25, P_A_I24, P_A_I23, P_A_I22, P_A_I21, P_A_I20, P_A_I19 -, P_A_I18, P_A_I17, P_A_I16, P_A_I15, P_A_I14, P_A_I13, P_A_I12, P_A_I11, P_A_I10, P_A_I9, P_A_I8, P_A_I7, P_A_I6, P_A_I5, P_A_I4, P_A_I3, P_A_I2, P_A_I1, P_ECC_I, PLVL_I, P_CK_E_I -, P_CK_I, P_E_I, PPV_BS_I20, PPV_BS_I19, PPV_BS_I18, PPV_BS_I17, PPV_BS_I16, PPV_BS_I15, PPV_BS_I14, PPV_BS_I13, PPV_BS_I12, PPV_BS_I11, PPV_BS_I10, PPV_BS_I9, PPV_BS_I8, PPV_BS_I7, PPV_BS_I6, PPV_BS_I5, PPV_BS_I4, PPV_BS_I3, PPV_BS_I2 -, PPV_BS_I1, PPV_SZ_I5, PPV_SZ_I4, PPV_SZ_I3, PPV_SZ_I2, PPV_SZ_I1, PPX_BS_I20, PPX_BS_I19, PPX_BS_I18, PPX_BS_I17, PPX_BS_I16, PPX_BS_I15, PPX_BS_I14, PPX_BS_I13, PPX_BS_I12, PPX_BS_I11, PPX_BS_I10, PPX_BS_I9, PPX_BS_I8, PPX_BS_I7, PPX_BS_I6 -, PPX_BS_I5, PPX_BS_I4, PPX_BS_I3, PPX_BS_I2, PPX_BS_I1, PPX_SZ_I5, PPX_SZ_I4, PPX_SZ_I3, PPX_SZ_I2, PPX_SZ_I1, P_RS_I, P_SEL_I, PW_D_I32, PW_D_I31, PW_D_I30, PW_D_I29, PW_D_I28, PW_D_I27, PW_D_I26, PW_D_I25, PW_D_I24 -, PW_D_I23, PW_D_I22, PW_D_I21, PW_D_I20, PW_D_I19, PW_D_I18, PW_D_I17, PW_D_I16, PW_D_I15, PW_D_I14, PW_D_I13, PW_D_I12, PW_D_I11, PW_D_I10, PW_D_I9, PW_D_I8, PW_D_I7, PW_D_I6, PW_D_I5, PW_D_I4, PW_D_I3 -, PW_D_I2, PW_D_I1, PW_I, RAMCTL_I8, RAMCTL_I7, RAMCTL_I6, RAMCTL_I5, RAMCTL_I4, RAMCTL_I3, RAMCTL_I2, RAMCTL_I1, R_DM_I64, R_DM_I63, R_DM_I62, R_DM_I61, R_DM_I60, R_DM_I59, R_DM_I58, R_DM_I57, R_DM_I56, R_DM_I55 -, R_DM_I54, R_DM_I53, R_DM_I52, R_DM_I51, R_DM_I50, R_DM_I49, R_DM_I48, R_DM_I47, R_DM_I46, R_DM_I45, R_DM_I44, R_DM_I43, R_DM_I42, R_DM_I41, R_DM_I40, R_DM_I39, R_DM_I38, R_DM_I37, R_DM_I36, R_DM_I35, R_DM_I34 -, R_DM_I33, R_DM_I32, R_DM_I31, R_DM_I30, R_DM_I29, R_DM_I28, R_DM_I27, R_DM_I26, R_DM_I25, R_DM_I24, R_DM_I23, R_DM_I22, R_DM_I21, R_DM_I20, R_DM_I19, R_DM_I18, R_DM_I17, R_DM_I16, R_DM_I15, R_DM_I14, R_DM_I13 -, R_DM_I12, R_DM_I11, R_DM_I10, R_DM_I9, R_DM_I8, R_DM_I7, R_DM_I6, R_DM_I5, R_DM_I4, R_DM_I3, R_DM_I2, R_DM_I1, R_DP_I32, R_DP_I31, R_DP_I30, R_DP_I29, R_DP_I28, R_DP_I27, R_DP_I26, R_DP_I25, R_DP_I24 -, R_DP_I23, R_DP_I22, R_DP_I21, R_DP_I20, R_DP_I19, R_DP_I18, R_DP_I17, R_DP_I16, R_DP_I15, R_DP_I14, R_DP_I13, R_DP_I12, R_DP_I11, R_DP_I10, R_DP_I9, R_DP_I8, R_DP_I7, R_DP_I6, R_DP_I5, R_DP_I4, R_DP_I3 -, R_DP_I2, R_DP_I1, R_IDM_I4, R_IDM_I3, R_IDM_I2, R_IDM_I1, R_IDP_I4, R_IDP_I3, R_IDP_I2, R_IDP_I1, R_LSTM_I, R_LSTP_I, R_RDY_I, R_RSPM_I2, R_RSPM_I1, R_RSPP_I2, R_RSPP_I1, RS_BYP_I, R_VDM_I, R_VDP_I, SE_I -, SW_CK_I, SW_DI_I, T_DI_I, TE_INI_I, VINI_I, W_D_I64, W_D_I63, W_D_I62, W_D_I61, W_D_I60, W_D_I59, W_D_I58, W_D_I57, W_D_I56, W_D_I55, W_D_I54, W_D_I53, W_D_I52, W_D_I51, W_D_I50, W_D_I49 -, W_D_I48, W_D_I47, W_D_I46, W_D_I45, W_D_I44, W_D_I43, W_D_I42, W_D_I41, W_D_I40, W_D_I39, W_D_I38, W_D_I37, W_D_I36, W_D_I35, W_D_I34, W_D_I33, W_D_I32, W_D_I31, W_D_I30, W_D_I29, W_D_I28 -, W_D_I27, W_D_I26, W_D_I25, W_D_I24, W_D_I23, W_D_I22, W_D_I21, W_D_I20, W_D_I19, W_D_I18, W_D_I17, W_D_I16, W_D_I15, W_D_I14, W_D_I13, W_D_I12, W_D_I11, W_D_I10, W_D_I9, W_D_I8, W_D_I7 -, W_D_I6, W_D_I5, W_D_I4, W_D_I3, W_D_I2, W_D_I1, W_IDS_I8, W_IDS_I7, W_IDS_I6, W_IDS_I5, W_IDS_I4, W_IDS_I3, W_IDS_I2, W_IDS_I1, W_LST_I, W_RYM_I, W_RYP_I, W_SBS_I8, W_SBS_I7, W_SBS_I6, W_SBS_I5 -, W_SBS_I4, W_SBS_I3, W_SBS_I2, W_SBS_I1, W_VD_I, AR_AM_O32, AR_AM_O31, AR_AM_O30, AR_AM_O29, AR_AM_O28, AR_AM_O27, AR_AM_O26, AR_AM_O25, AR_AM_O24, AR_AM_O23, AR_AM_O22, AR_AM_O21, AR_AM_O20, AR_AM_O19, AR_AM_O18, AR_AM_O17 -, AR_AM_O16, AR_AM_O15, AR_AM_O14, AR_AM_O13, AR_AM_O12, AR_AM_O11, AR_AM_O10, AR_AM_O9, AR_AM_O8, AR_AM_O7, AR_AM_O6, AR_AM_O5, AR_AM_O4, AR_AM_O3, AR_AM_O2, AR_AM_O1, AR_AP_O32, AR_AP_O31, AR_AP_O30, AR_AP_O29, AR_AP_O28 -, AR_AP_O27, AR_AP_O26, AR_AP_O25, AR_AP_O24, AR_AP_O23, AR_AP_O22, AR_AP_O21, AR_AP_O20, AR_AP_O19, AR_AP_O18, AR_AP_O17, AR_AP_O16, AR_AP_O15, AR_AP_O14, AR_AP_O13, AR_AP_O12, AR_AP_O11, AR_AP_O10, AR_AP_O9, AR_AP_O8, AR_AP_O7 -, AR_AP_O6, AR_AP_O5, AR_AP_O4, AR_AP_O3, AR_AP_O2, AR_AP_O1, AR_BUM_O2, AR_BUM_O1, AR_BUP_O2, AR_BUP_O1, AR_CHM_O4, AR_CHM_O3, AR_CHM_O2, AR_CHM_O1, AR_CHP_O4, AR_CHP_O3, AR_CHP_O2, AR_CHP_O1, AR_IDM_O4, AR_IDM_O3, AR_IDM_O2 -, AR_IDM_O1, AR_IDP_O4, AR_IDP_O3, AR_IDP_O2, AR_IDP_O1, AR_INM_O4, AR_INM_O3, AR_INM_O2, AR_INM_O1, AR_LEM_O4, AR_LEM_O3, AR_LEM_O2, AR_LEM_O1, AR_LEP_O4, AR_LEP_O3, AR_LEP_O2, AR_LEP_O1, AR_LKM_O2, AR_LKM_O1, AR_LKP_O2, AR_LKP_O1 -, AR_PRM_O3, AR_PRM_O2, AR_PRM_O1, AR_PRP_O3, AR_PRP_O2, AR_PRP_O1, AR_RDY_O, AR_SHM_O, AR_SZM_O3, AR_SZM_O2, AR_SZM_O1, AR_SZP_O3, AR_SZP_O2, AR_SZP_O1, AR_VDM_O, AR_VDP_O, AW_AM_O32, AW_AM_O31, AW_AM_O30, AW_AM_O29, AW_AM_O28 -, AW_AM_O27, AW_AM_O26, AW_AM_O25, AW_AM_O24, AW_AM_O23, AW_AM_O22, AW_AM_O21, AW_AM_O20, AW_AM_O19, AW_AM_O18, AW_AM_O17, AW_AM_O16, AW_AM_O15, AW_AM_O14, AW_AM_O13, AW_AM_O12, AW_AM_O11, AW_AM_O10, AW_AM_O9, AW_AM_O8, AW_AM_O7 -, AW_AM_O6, AW_AM_O5, AW_AM_O4, AW_AM_O3, AW_AM_O2, AW_AM_O1, AW_AP_O32, AW_AP_O31, AW_AP_O30, AW_AP_O29, AW_AP_O28, AW_AP_O27, AW_AP_O26, AW_AP_O25, AW_AP_O24, AW_AP_O23, AW_AP_O22, AW_AP_O21, AW_AP_O20, AW_AP_O19, AW_AP_O18 -, AW_AP_O17, AW_AP_O16, AW_AP_O15, AW_AP_O14, AW_AP_O13, AW_AP_O12, AW_AP_O11, AW_AP_O10, AW_AP_O9, AW_AP_O8, AW_AP_O7, AW_AP_O6, AW_AP_O5, AW_AP_O4, AW_AP_O3, AW_AP_O2, AW_AP_O1, AW_BUM_O2, AW_BUM_O1, AW_BUP_O2, AW_BUP_O1 -, AW_CHM_O4, AW_CHM_O3, AW_CHM_O2, AW_CHM_O1, AW_CHP_O4, AW_CHP_O3, AW_CHP_O2, AW_CHP_O1, AW_IDM_O4, AW_IDM_O3, AW_IDM_O2, AW_IDM_O1, AW_IDP_O4, AW_IDP_O3, AW_IDP_O2, AW_IDP_O1, AW_INM_O4, AW_INM_O3, AW_INM_O2, AW_INM_O1, AW_LEM_O4 -, AW_LEM_O3, AW_LEM_O2, AW_LEM_O1, AW_LEP_O4, AW_LEP_O3, AW_LEP_O2, AW_LEP_O1, AW_LKM_O2, AW_LKM_O1, AW_LKP_O2, AW_LKP_O1, AW_PRM_O3, AW_PRM_O2, AW_PRM_O1, AW_PRP_O3, AW_PRP_O2, AW_PRP_O1, AW_RDY_O, AW_SHM_O, AW_SZM_O3, AW_SZM_O2 -, AW_SZM_O1, AW_SZP_O3, AW_SZP_O2, AW_SZP_O1, AW_VDM_O, AW_VDP_O, B_IDS_O8, B_IDS_O7, B_IDS_O6, B_IDS_O5, B_IDS_O4, B_IDS_O3, B_IDS_O2, B_IDS_O1, B_RDYM_O, B_RDYP_O, B_RSP_O2, B_RSP_O1, B_VD_O, CDB_PW_O, CDB_RS_O -, COM_RX_O, COM_TX_O, CS_PW_O, DB_ACK_O, DB_NPD_O, DB_RS_O, DFTS_O8, DFTS_O7, DFTS_O6, DFTS_O5, DFTS_O4, DFTS_O3, DFTS_O2, DFTS_O1, ET_ASC_O8, ET_ASC_O7, ET_ASC_O6, ET_ASC_O5, ET_ASC_O4, ET_ASC_O3, ET_ASC_O2 -, ET_ASC_O1, ET_E_O, ET_EXT_O2, ET_EXT_O1, EVENT_O, FP_DZC_O, FP_IDC_O, FP_IOC_O, FP_IXC_O, FP_OFC_O, FP_UFC_O, JTAG_O, N_CKST_O, N_PMU_O, N_TDO_O, N_VFIQ_O, N_VIRQ_O, N_VRST_O, N_EPST_O, N_IPST_O, P_RD_O32 -, P_RD_O31, P_RD_O30, P_RD_O29, P_RD_O28, P_RD_O27, P_RD_O26, P_RD_O25, P_RD_O24, P_RD_O23, P_RD_O22, P_RD_O21, P_RD_O20, P_RD_O19, P_RD_O18, P_RD_O17, P_RD_O16, P_RD_O15, P_RD_O14, P_RD_O13, P_RD_O12, P_RD_O11 -, P_RD_O10, P_RD_O9, P_RD_O8, P_RD_O7, P_RD_O6, P_RD_O5, P_RD_O4, P_RD_O3, P_RD_O2, P_RD_O1, P_RDY_O, P_VER_O, RD_O64, RD_O63, RD_O62, RD_O61, RD_O60, RD_O59, RD_O58, RD_O57, RD_O56 -, RD_O55, RD_O54, RD_O53, RD_O52, RD_O51, RD_O50, RD_O49, RD_O48, RD_O47, RD_O46, RD_O45, RD_O44, RD_O43, RD_O42, RD_O41, RD_O40, RD_O39, RD_O38, RD_O37, RD_O36, RD_O35 -, RD_O34, RD_O33, RD_O32, RD_O31, RD_O30, RD_O29, RD_O28, RD_O27, RD_O26, RD_O25, RD_O24, RD_O23, RD_O22, RD_O21, RD_O20, RD_O19, RD_O18, RD_O17, RD_O16, RD_O15, RD_O14 -, RD_O13, RD_O12, RD_O11, RD_O10, RD_O9, RD_O8, RD_O7, RD_O6, RD_O5, RD_O4, RD_O3, RD_O2, RD_O1, R_IDS_O8, R_IDS_O7, R_IDS_O6, R_IDS_O5, R_IDS_O4, R_IDS_O3, R_IDS_O2, R_IDS_O1 -, R_LST_O, R_RDYM_O, R_RDYP_O, R_RSP_O2, R_RSP_O1, R_VD_O, SWDO_O, SWDO_E_O, TDO_O, T_CK_O, T_CTL_O, T_DATA_O32, T_DATA_O31, T_DATA_O30, T_DATA_O29, T_DATA_O28, T_DATA_O27, T_DATA_O26, T_DATA_O25, T_DATA_O24, T_DATA_O23 -, T_DATA_O22, T_DATA_O21, T_DATA_O20, T_DATA_O19, T_DATA_O18, T_DATA_O17, T_DATA_O16, T_DATA_O15, T_DATA_O14, T_DATA_O13, T_DATA_O12, T_DATA_O11, T_DATA_O10, T_DATA_O9, T_DATA_O8, T_DATA_O7, T_DATA_O6, T_DATA_O5, T_DATA_O4, T_DATA_O3, T_DATA_O2 -, T_DATA_O1, W_DM_O64, W_DM_O63, W_DM_O62, W_DM_O61, W_DM_O60, W_DM_O59, W_DM_O58, W_DM_O57, W_DM_O56, W_DM_O55, W_DM_O54, W_DM_O53, W_DM_O52, W_DM_O51, W_DM_O50, W_DM_O49, W_DM_O48, W_DM_O47, W_DM_O46, W_DM_O45 -, W_DM_O44, W_DM_O43, W_DM_O42, W_DM_O41, W_DM_O40, W_DM_O39, W_DM_O38, W_DM_O37, W_DM_O36, W_DM_O35, W_DM_O34, W_DM_O33, W_DM_O32, W_DM_O31, W_DM_O30, W_DM_O29, W_DM_O28, W_DM_O27, W_DM_O26, W_DM_O25, W_DM_O24 -, W_DM_O23, W_DM_O22, W_DM_O21, W_DM_O20, W_DM_O19, W_DM_O18, W_DM_O17, W_DM_O16, W_DM_O15, W_DM_O14, W_DM_O13, W_DM_O12, W_DM_O11, W_DM_O10, W_DM_O9, W_DM_O8, W_DM_O7, W_DM_O6, W_DM_O5, W_DM_O4, W_DM_O3 -, W_DM_O2, W_DM_O1, W_DP_O32, W_DP_O31, W_DP_O30, W_DP_O29, W_DP_O28, W_DP_O27, W_DP_O26, W_DP_O25, W_DP_O24, W_DP_O23, W_DP_O22, W_DP_O21, W_DP_O20, W_DP_O19, W_DP_O18, W_DP_O17, W_DP_O16, W_DP_O15, W_DP_O14 -, W_DP_O13, W_DP_O12, W_DP_O11, W_DP_O10, W_DP_O9, W_DP_O8, W_DP_O7, W_DP_O6, W_DP_O5, W_DP_O4, W_DP_O3, W_DP_O2, W_DP_O1, W_IDM_O4, W_IDM_O3, W_IDM_O2, W_IDM_O1, W_IDP_O4, W_IDP_O3, W_IDP_O2, W_IDP_O1 -, W_LSTM_O, W_LSTP_O, W_RDY_O, W_SBM_O8, W_SBM_O7, W_SBM_O6, W_SBM_O5, W_SBM_O4, W_SBM_O3, W_SBM_O2, W_SBM_O1, W_SBP_O4, W_SBP_O3, W_SBP_O2, W_SBP_O1, W_VDM_O, W_VDP_O); - output AR_AM_O1; - output AR_AM_O10; - output AR_AM_O11; - output AR_AM_O12; - output AR_AM_O13; - output AR_AM_O14; - output AR_AM_O15; - output AR_AM_O16; - output AR_AM_O17; - output AR_AM_O18; - output AR_AM_O19; - output AR_AM_O2; - output AR_AM_O20; - output AR_AM_O21; - output AR_AM_O22; - output AR_AM_O23; - output AR_AM_O24; - output AR_AM_O25; - output AR_AM_O26; - output AR_AM_O27; - output AR_AM_O28; - output AR_AM_O29; - output AR_AM_O3; - output AR_AM_O30; - output AR_AM_O31; - output AR_AM_O32; - output AR_AM_O4; - output AR_AM_O5; - output AR_AM_O6; - output AR_AM_O7; - output AR_AM_O8; - output AR_AM_O9; - output AR_AP_O1; - output AR_AP_O10; - output AR_AP_O11; - output AR_AP_O12; - output AR_AP_O13; - output AR_AP_O14; - output AR_AP_O15; - output AR_AP_O16; - output AR_AP_O17; - output AR_AP_O18; - output AR_AP_O19; - output AR_AP_O2; - output AR_AP_O20; - output AR_AP_O21; - output AR_AP_O22; - output AR_AP_O23; - output AR_AP_O24; - output AR_AP_O25; - output AR_AP_O26; - output AR_AP_O27; - output AR_AP_O28; - output AR_AP_O29; - output AR_AP_O3; - output AR_AP_O30; - output AR_AP_O31; - output AR_AP_O32; - output AR_AP_O4; - output AR_AP_O5; - output AR_AP_O6; - output AR_AP_O7; - output AR_AP_O8; - output AR_AP_O9; - input AR_A_I1; - input AR_A_I10; - input AR_A_I11; - input AR_A_I12; - input AR_A_I13; - input AR_A_I14; - input AR_A_I15; - input AR_A_I16; - input AR_A_I17; - input AR_A_I18; - input AR_A_I19; - input AR_A_I2; - input AR_A_I20; - input AR_A_I21; - input AR_A_I22; - input AR_A_I23; - input AR_A_I24; - input AR_A_I25; - input AR_A_I26; - input AR_A_I27; - input AR_A_I28; - input AR_A_I29; - input AR_A_I3; - input AR_A_I30; - input AR_A_I31; - input AR_A_I32; - input AR_A_I4; - input AR_A_I5; - input AR_A_I6; - input AR_A_I7; - input AR_A_I8; - input AR_A_I9; - output AR_BUM_O1; - output AR_BUM_O2; - output AR_BUP_O1; - output AR_BUP_O2; - input AR_BU_I1; - input AR_BU_I2; - output AR_CHM_O1; - output AR_CHM_O2; - output AR_CHM_O3; - output AR_CHM_O4; - output AR_CHP_O1; - output AR_CHP_O2; - output AR_CHP_O3; - output AR_CHP_O4; - input AR_CH_I1; - input AR_CH_I2; - input AR_CH_I3; - input AR_CH_I4; - output AR_IDM_O1; - output AR_IDM_O2; - output AR_IDM_O3; - output AR_IDM_O4; - output AR_IDP_O1; - output AR_IDP_O2; - output AR_IDP_O3; - output AR_IDP_O4; - input AR_IDS_I1; - input AR_IDS_I2; - input AR_IDS_I3; - input AR_IDS_I4; - input AR_IDS_I5; - input AR_IDS_I6; - input AR_IDS_I7; - input AR_IDS_I8; - output AR_INM_O1; - output AR_INM_O2; - output AR_INM_O3; - output AR_INM_O4; - output AR_LEM_O1; - output AR_LEM_O2; - output AR_LEM_O3; - output AR_LEM_O4; - output AR_LEP_O1; - output AR_LEP_O2; - output AR_LEP_O3; - output AR_LEP_O4; - input AR_LE_I1; - input AR_LE_I2; - input AR_LE_I3; - input AR_LE_I4; - output AR_LKM_O1; - output AR_LKM_O2; - output AR_LKP_O1; - output AR_LKP_O2; - input AR_LK_I1; - input AR_LK_I2; - output AR_PRM_O1; - output AR_PRM_O2; - output AR_PRM_O3; - output AR_PRP_O1; - output AR_PRP_O2; - output AR_PRP_O3; - input AR_PR_I1; - input AR_PR_I2; - input AR_PR_I3; - output AR_RDY_O; - input AR_RYM_I; - input AR_RYP_I; - output AR_SHM_O; - output AR_SZM_O1; - output AR_SZM_O2; - output AR_SZM_O3; - output AR_SZP_O1; - output AR_SZP_O2; - output AR_SZP_O3; - input AR_SZ_I1; - input AR_SZ_I2; - input AR_SZ_I3; - output AR_VDM_O; - output AR_VDP_O; - input AR_VD_I; - input AT_RS_I; - output AW_AM_O1; - output AW_AM_O10; - output AW_AM_O11; - output AW_AM_O12; - output AW_AM_O13; - output AW_AM_O14; - output AW_AM_O15; - output AW_AM_O16; - output AW_AM_O17; - output AW_AM_O18; - output AW_AM_O19; - output AW_AM_O2; - output AW_AM_O20; - output AW_AM_O21; - output AW_AM_O22; - output AW_AM_O23; - output AW_AM_O24; - output AW_AM_O25; - output AW_AM_O26; - output AW_AM_O27; - output AW_AM_O28; - output AW_AM_O29; - output AW_AM_O3; - output AW_AM_O30; - output AW_AM_O31; - output AW_AM_O32; - output AW_AM_O4; - output AW_AM_O5; - output AW_AM_O6; - output AW_AM_O7; - output AW_AM_O8; - output AW_AM_O9; - output AW_AP_O1; - output AW_AP_O10; - output AW_AP_O11; - output AW_AP_O12; - output AW_AP_O13; - output AW_AP_O14; - output AW_AP_O15; - output AW_AP_O16; - output AW_AP_O17; - output AW_AP_O18; - output AW_AP_O19; - output AW_AP_O2; - output AW_AP_O20; - output AW_AP_O21; - output AW_AP_O22; - output AW_AP_O23; - output AW_AP_O24; - output AW_AP_O25; - output AW_AP_O26; - output AW_AP_O27; - output AW_AP_O28; - output AW_AP_O29; - output AW_AP_O3; - output AW_AP_O30; - output AW_AP_O31; - output AW_AP_O32; - output AW_AP_O4; - output AW_AP_O5; - output AW_AP_O6; - output AW_AP_O7; - output AW_AP_O8; - output AW_AP_O9; - input AW_A_I1; - input AW_A_I10; - input AW_A_I11; - input AW_A_I12; - input AW_A_I13; - input AW_A_I14; - input AW_A_I15; - input AW_A_I16; - input AW_A_I17; - input AW_A_I18; - input AW_A_I19; - input AW_A_I2; - input AW_A_I20; - input AW_A_I21; - input AW_A_I22; - input AW_A_I23; - input AW_A_I24; - input AW_A_I25; - input AW_A_I26; - input AW_A_I27; - input AW_A_I28; - input AW_A_I29; - input AW_A_I3; - input AW_A_I30; - input AW_A_I31; - input AW_A_I32; - input AW_A_I4; - input AW_A_I5; - input AW_A_I6; - input AW_A_I7; - input AW_A_I8; - input AW_A_I9; - output AW_BUM_O1; - output AW_BUM_O2; - output AW_BUP_O1; - output AW_BUP_O2; - input AW_BU_I1; - input AW_BU_I2; - output AW_CHM_O1; - output AW_CHM_O2; - output AW_CHM_O3; - output AW_CHM_O4; - output AW_CHP_O1; - output AW_CHP_O2; - output AW_CHP_O3; - output AW_CHP_O4; - input AW_CH_I1; - input AW_CH_I2; - input AW_CH_I3; - input AW_CH_I4; - output AW_IDM_O1; - output AW_IDM_O2; - output AW_IDM_O3; - output AW_IDM_O4; - output AW_IDP_O1; - output AW_IDP_O2; - output AW_IDP_O3; - output AW_IDP_O4; - input AW_IDS_I1; - input AW_IDS_I2; - input AW_IDS_I3; - input AW_IDS_I4; - input AW_IDS_I5; - input AW_IDS_I6; - input AW_IDS_I7; - input AW_IDS_I8; - output AW_INM_O1; - output AW_INM_O2; - output AW_INM_O3; - output AW_INM_O4; - output AW_LEM_O1; - output AW_LEM_O2; - output AW_LEM_O3; - output AW_LEM_O4; - output AW_LEP_O1; - output AW_LEP_O2; - output AW_LEP_O3; - output AW_LEP_O4; - input AW_LE_I1; - input AW_LE_I2; - input AW_LE_I3; - input AW_LE_I4; - output AW_LKM_O1; - output AW_LKM_O2; - output AW_LKP_O1; - output AW_LKP_O2; - input AW_LK_I1; - input AW_LK_I2; - output AW_PRM_O1; - output AW_PRM_O2; - output AW_PRM_O3; - output AW_PRP_O1; - output AW_PRP_O2; - output AW_PRP_O3; - input AW_PR_I1; - input AW_PR_I2; - input AW_PR_I3; - output AW_RDY_O; - input AW_RYM_I; - input AW_RYP_I; - output AW_SHM_O; - output AW_SZM_O1; - output AW_SZM_O2; - output AW_SZM_O3; - output AW_SZP_O1; - output AW_SZP_O2; - output AW_SZP_O3; - input AW_SZ_I1; - input AW_SZ_I2; - input AW_SZ_I3; - output AW_VDM_O; - output AW_VDP_O; - input AW_VD_I; - input A_CKEM_I; - input A_CKEP_I; - input A_CKES_I; - input B_IDM_I1; - input B_IDM_I2; - input B_IDM_I3; - input B_IDM_I4; - input B_IDP_I1; - input B_IDP_I2; - input B_IDP_I3; - input B_IDP_I4; - output B_IDS_O1; - output B_IDS_O2; - output B_IDS_O3; - output B_IDS_O4; - output B_IDS_O5; - output B_IDS_O6; - output B_IDS_O7; - output B_IDS_O8; - output B_RDYM_O; - output B_RDYP_O; - input B_RDY_I; - input B_RSPM_I1; - input B_RSPM_I2; - input B_RSPP_I1; - input B_RSPP_I2; - output B_RSP_O1; - output B_RSP_O2; - input B_VDM_I; - input B_VDP_I; - output B_VD_O; - input CDB_PW_I; - output CDB_PW_O; - input CDB_RS_I; - output CDB_RS_O; - input CFG_EE_I; - input CFG_IE_I; - input CFG_NM_I; - input CK_I; - output COM_RX_O; - output COM_TX_O; - input CS_PW_I; - output CS_PW_O; - output DB_ACK_O; - input DB_E_I; - input DB_NCK_I; - output DB_NPD_O; - input DB_RAV_I; - input DB_RA_I1; - input DB_RA_I10; - input DB_RA_I11; - input DB_RA_I12; - input DB_RA_I13; - input DB_RA_I14; - input DB_RA_I15; - input DB_RA_I16; - input DB_RA_I17; - input DB_RA_I18; - input DB_RA_I19; - input DB_RA_I2; - input DB_RA_I20; - input DB_RA_I3; - input DB_RA_I4; - input DB_RA_I5; - input DB_RA_I6; - input DB_RA_I7; - input DB_RA_I8; - input DB_RA_I9; - output DB_RS_O; - input DB_SAV_I; - input DB_SA_I1; - input DB_SA_I10; - input DB_SA_I11; - input DB_SA_I12; - input DB_SA_I13; - input DB_SA_I14; - input DB_SA_I15; - input DB_SA_I16; - input DB_SA_I17; - input DB_SA_I18; - input DB_SA_I19; - input DB_SA_I2; - input DB_SA_I20; - input DB_SA_I3; - input DB_SA_I4; - input DB_SA_I5; - input DB_SA_I6; - input DB_SA_I7; - input DB_SA_I8; - input DB_SA_I9; - input DEV_E_I; - input DFTS_I1; - input DFTS_I2; - input DFTS_I3; - input DFTS_I4; - input DFTS_I5; - input DFTS_I6; - input DFTS_I7; - input DFTS_I8; - output DFTS_O1; - output DFTS_O2; - output DFTS_O3; - output DFTS_O4; - output DFTS_O5; - output DFTS_O6; - output DFTS_O7; - output DFTS_O8; - input ERR_R_I; - output ET_ASC_O1; - output ET_ASC_O2; - output ET_ASC_O3; - output ET_ASC_O4; - output ET_ASC_O5; - output ET_ASC_O6; - output ET_ASC_O7; - output ET_ASC_O8; - output ET_EXT_O1; - output ET_EXT_O2; - output ET_E_O; - input EVENT_I; - output EVENT_O; - input E_DB_I; - output FP_DZC_O; - output FP_IDC_O; - output FP_IOC_O; - output FP_IXC_O; - output FP_OFC_O; - output FP_UFC_O; - input GID_I1; - input GID_I2; - input GID_I3; - input GID_I4; - input INIT_P_I; - input INIT_R_I; - output JTAG_O; - input LOC_R_I; - input NCPUH_I; - input NET_RS_I; - output N_CKST_O; - output N_EPST_O; - input N_FIQ_I; - input N_IDE_I; - output N_IPST_O; - input N_IRQ_I; - output N_PMU_O; - input N_PRS_I; - input N_RS_I; - input N_SPRS_I; - output N_TDO_O; - input N_TRS_I; - output N_VFIQ_O; - output N_VIRQ_O; - output N_VRST_O; - input PLVL_I; - input PPV_BS_I1; - input PPV_BS_I10; - input PPV_BS_I11; - input PPV_BS_I12; - input PPV_BS_I13; - input PPV_BS_I14; - input PPV_BS_I15; - input PPV_BS_I16; - input PPV_BS_I17; - input PPV_BS_I18; - input PPV_BS_I19; - input PPV_BS_I2; - input PPV_BS_I20; - input PPV_BS_I3; - input PPV_BS_I4; - input PPV_BS_I5; - input PPV_BS_I6; - input PPV_BS_I7; - input PPV_BS_I8; - input PPV_BS_I9; - input PPV_SZ_I1; - input PPV_SZ_I2; - input PPV_SZ_I3; - input PPV_SZ_I4; - input PPV_SZ_I5; - input PPX_BS_I1; - input PPX_BS_I10; - input PPX_BS_I11; - input PPX_BS_I12; - input PPX_BS_I13; - input PPX_BS_I14; - input PPX_BS_I15; - input PPX_BS_I16; - input PPX_BS_I17; - input PPX_BS_I18; - input PPX_BS_I19; - input PPX_BS_I2; - input PPX_BS_I20; - input PPX_BS_I3; - input PPX_BS_I4; - input PPX_BS_I5; - input PPX_BS_I6; - input PPX_BS_I7; - input PPX_BS_I8; - input PPX_BS_I9; - input PPX_SZ_I1; - input PPX_SZ_I2; - input PPX_SZ_I3; - input PPX_SZ_I4; - input PPX_SZ_I5; - input PW_D_I1; - input PW_D_I10; - input PW_D_I11; - input PW_D_I12; - input PW_D_I13; - input PW_D_I14; - input PW_D_I15; - input PW_D_I16; - input PW_D_I17; - input PW_D_I18; - input PW_D_I19; - input PW_D_I2; - input PW_D_I20; - input PW_D_I21; - input PW_D_I22; - input PW_D_I23; - input PW_D_I24; - input PW_D_I25; - input PW_D_I26; - input PW_D_I27; - input PW_D_I28; - input PW_D_I29; - input PW_D_I3; - input PW_D_I30; - input PW_D_I31; - input PW_D_I32; - input PW_D_I4; - input PW_D_I5; - input PW_D_I6; - input PW_D_I7; - input PW_D_I8; - input PW_D_I9; - input PW_I; - input P_A_I1; - input P_A_I10; - input P_A_I11; - input P_A_I12; - input P_A_I13; - input P_A_I14; - input P_A_I15; - input P_A_I16; - input P_A_I17; - input P_A_I18; - input P_A_I19; - input P_A_I2; - input P_A_I20; - input P_A_I21; - input P_A_I22; - input P_A_I23; - input P_A_I24; - input P_A_I25; - input P_A_I26; - input P_A_I27; - input P_A_I28; - input P_A_I29; - input P_A_I3; - input P_A_I4; - input P_A_I5; - input P_A_I6; - input P_A_I7; - input P_A_I8; - input P_A_I9; - input P_CK_E_I; - input P_CK_I; - input P_ECC_I; - input P_E_I; - output P_RDY_O; - output P_RD_O1; - output P_RD_O10; - output P_RD_O11; - output P_RD_O12; - output P_RD_O13; - output P_RD_O14; - output P_RD_O15; - output P_RD_O16; - output P_RD_O17; - output P_RD_O18; - output P_RD_O19; - output P_RD_O2; - output P_RD_O20; - output P_RD_O21; - output P_RD_O22; - output P_RD_O23; - output P_RD_O24; - output P_RD_O25; - output P_RD_O26; - output P_RD_O27; - output P_RD_O28; - output P_RD_O29; - output P_RD_O3; - output P_RD_O30; - output P_RD_O31; - output P_RD_O32; - output P_RD_O4; - output P_RD_O5; - output P_RD_O6; - output P_RD_O7; - output P_RD_O8; - output P_RD_O9; - input P_RS_I; - input P_SEL_I; - output P_VER_O; - input RAMCTL_I1; - input RAMCTL_I2; - input RAMCTL_I3; - input RAMCTL_I4; - input RAMCTL_I5; - input RAMCTL_I6; - input RAMCTL_I7; - input RAMCTL_I8; - output RD_O1; - output RD_O10; - output RD_O11; - output RD_O12; - output RD_O13; - output RD_O14; - output RD_O15; - output RD_O16; - output RD_O17; - output RD_O18; - output RD_O19; - output RD_O2; - output RD_O20; - output RD_O21; - output RD_O22; - output RD_O23; - output RD_O24; - output RD_O25; - output RD_O26; - output RD_O27; - output RD_O28; - output RD_O29; - output RD_O3; - output RD_O30; - output RD_O31; - output RD_O32; - output RD_O33; - output RD_O34; - output RD_O35; - output RD_O36; - output RD_O37; - output RD_O38; - output RD_O39; - output RD_O4; - output RD_O40; - output RD_O41; - output RD_O42; - output RD_O43; - output RD_O44; - output RD_O45; - output RD_O46; - output RD_O47; - output RD_O48; - output RD_O49; - output RD_O5; - output RD_O50; - output RD_O51; - output RD_O52; - output RD_O53; - output RD_O54; - output RD_O55; - output RD_O56; - output RD_O57; - output RD_O58; - output RD_O59; - output RD_O6; - output RD_O60; - output RD_O61; - output RD_O62; - output RD_O63; - output RD_O64; - output RD_O7; - output RD_O8; - output RD_O9; - input RS_BYP_I; - input R_DM_I1; - input R_DM_I10; - input R_DM_I11; - input R_DM_I12; - input R_DM_I13; - input R_DM_I14; - input R_DM_I15; - input R_DM_I16; - input R_DM_I17; - input R_DM_I18; - input R_DM_I19; - input R_DM_I2; - input R_DM_I20; - input R_DM_I21; - input R_DM_I22; - input R_DM_I23; - input R_DM_I24; - input R_DM_I25; - input R_DM_I26; - input R_DM_I27; - input R_DM_I28; - input R_DM_I29; - input R_DM_I3; - input R_DM_I30; - input R_DM_I31; - input R_DM_I32; - input R_DM_I33; - input R_DM_I34; - input R_DM_I35; - input R_DM_I36; - input R_DM_I37; - input R_DM_I38; - input R_DM_I39; - input R_DM_I4; - input R_DM_I40; - input R_DM_I41; - input R_DM_I42; - input R_DM_I43; - input R_DM_I44; - input R_DM_I45; - input R_DM_I46; - input R_DM_I47; - input R_DM_I48; - input R_DM_I49; - input R_DM_I5; - input R_DM_I50; - input R_DM_I51; - input R_DM_I52; - input R_DM_I53; - input R_DM_I54; - input R_DM_I55; - input R_DM_I56; - input R_DM_I57; - input R_DM_I58; - input R_DM_I59; - input R_DM_I6; - input R_DM_I60; - input R_DM_I61; - input R_DM_I62; - input R_DM_I63; - input R_DM_I64; - input R_DM_I7; - input R_DM_I8; - input R_DM_I9; - input R_DP_I1; - input R_DP_I10; - input R_DP_I11; - input R_DP_I12; - input R_DP_I13; - input R_DP_I14; - input R_DP_I15; - input R_DP_I16; - input R_DP_I17; - input R_DP_I18; - input R_DP_I19; - input R_DP_I2; - input R_DP_I20; - input R_DP_I21; - input R_DP_I22; - input R_DP_I23; - input R_DP_I24; - input R_DP_I25; - input R_DP_I26; - input R_DP_I27; - input R_DP_I28; - input R_DP_I29; - input R_DP_I3; - input R_DP_I30; - input R_DP_I31; - input R_DP_I32; - input R_DP_I4; - input R_DP_I5; - input R_DP_I6; - input R_DP_I7; - input R_DP_I8; - input R_DP_I9; - input R_IDM_I1; - input R_IDM_I2; - input R_IDM_I3; - input R_IDM_I4; - input R_IDP_I1; - input R_IDP_I2; - input R_IDP_I3; - input R_IDP_I4; - output R_IDS_O1; - output R_IDS_O2; - output R_IDS_O3; - output R_IDS_O4; - output R_IDS_O5; - output R_IDS_O6; - output R_IDS_O7; - output R_IDS_O8; - input R_LSTM_I; - input R_LSTP_I; - output R_LST_O; - output R_RDYM_O; - output R_RDYP_O; - input R_RDY_I; - input R_RSPM_I1; - input R_RSPM_I2; - input R_RSPP_I1; - input R_RSPP_I2; - output R_RSP_O1; - output R_RSP_O2; - input R_VDM_I; - input R_VDP_I; - output R_VD_O; - input SE_I; - output SWDO_E_O; - output SWDO_O; - input SW_CK_I; - input SW_DI_I; - output TDO_O; - input TE_INI_I; - output T_CK_O; - output T_CTL_O; - output T_DATA_O1; - output T_DATA_O10; - output T_DATA_O11; - output T_DATA_O12; - output T_DATA_O13; - output T_DATA_O14; - output T_DATA_O15; - output T_DATA_O16; - output T_DATA_O17; - output T_DATA_O18; - output T_DATA_O19; - output T_DATA_O2; - output T_DATA_O20; - output T_DATA_O21; - output T_DATA_O22; - output T_DATA_O23; - output T_DATA_O24; - output T_DATA_O25; - output T_DATA_O26; - output T_DATA_O27; - output T_DATA_O28; - output T_DATA_O29; - output T_DATA_O3; - output T_DATA_O30; - output T_DATA_O31; - output T_DATA_O32; - output T_DATA_O4; - output T_DATA_O5; - output T_DATA_O6; - output T_DATA_O7; - output T_DATA_O8; - output T_DATA_O9; - input T_DI_I; - input VINI_I; - output W_DM_O1; - output W_DM_O10; - output W_DM_O11; - output W_DM_O12; - output W_DM_O13; - output W_DM_O14; - output W_DM_O15; - output W_DM_O16; - output W_DM_O17; - output W_DM_O18; - output W_DM_O19; - output W_DM_O2; - output W_DM_O20; - output W_DM_O21; - output W_DM_O22; - output W_DM_O23; - output W_DM_O24; - output W_DM_O25; - output W_DM_O26; - output W_DM_O27; - output W_DM_O28; - output W_DM_O29; - output W_DM_O3; - output W_DM_O30; - output W_DM_O31; - output W_DM_O32; - output W_DM_O33; - output W_DM_O34; - output W_DM_O35; - output W_DM_O36; - output W_DM_O37; - output W_DM_O38; - output W_DM_O39; - output W_DM_O4; - output W_DM_O40; - output W_DM_O41; - output W_DM_O42; - output W_DM_O43; - output W_DM_O44; - output W_DM_O45; - output W_DM_O46; - output W_DM_O47; - output W_DM_O48; - output W_DM_O49; - output W_DM_O5; - output W_DM_O50; - output W_DM_O51; - output W_DM_O52; - output W_DM_O53; - output W_DM_O54; - output W_DM_O55; - output W_DM_O56; - output W_DM_O57; - output W_DM_O58; - output W_DM_O59; - output W_DM_O6; - output W_DM_O60; - output W_DM_O61; - output W_DM_O62; - output W_DM_O63; - output W_DM_O64; - output W_DM_O7; - output W_DM_O8; - output W_DM_O9; - output W_DP_O1; - output W_DP_O10; - output W_DP_O11; - output W_DP_O12; - output W_DP_O13; - output W_DP_O14; - output W_DP_O15; - output W_DP_O16; - output W_DP_O17; - output W_DP_O18; - output W_DP_O19; - output W_DP_O2; - output W_DP_O20; - output W_DP_O21; - output W_DP_O22; - output W_DP_O23; - output W_DP_O24; - output W_DP_O25; - output W_DP_O26; - output W_DP_O27; - output W_DP_O28; - output W_DP_O29; - output W_DP_O3; - output W_DP_O30; - output W_DP_O31; - output W_DP_O32; - output W_DP_O4; - output W_DP_O5; - output W_DP_O6; - output W_DP_O7; - output W_DP_O8; - output W_DP_O9; - input W_D_I1; - input W_D_I10; - input W_D_I11; - input W_D_I12; - input W_D_I13; - input W_D_I14; - input W_D_I15; - input W_D_I16; - input W_D_I17; - input W_D_I18; - input W_D_I19; - input W_D_I2; - input W_D_I20; - input W_D_I21; - input W_D_I22; - input W_D_I23; - input W_D_I24; - input W_D_I25; - input W_D_I26; - input W_D_I27; - input W_D_I28; - input W_D_I29; - input W_D_I3; - input W_D_I30; - input W_D_I31; - input W_D_I32; - input W_D_I33; - input W_D_I34; - input W_D_I35; - input W_D_I36; - input W_D_I37; - input W_D_I38; - input W_D_I39; - input W_D_I4; - input W_D_I40; - input W_D_I41; - input W_D_I42; - input W_D_I43; - input W_D_I44; - input W_D_I45; - input W_D_I46; - input W_D_I47; - input W_D_I48; - input W_D_I49; - input W_D_I5; - input W_D_I50; - input W_D_I51; - input W_D_I52; - input W_D_I53; - input W_D_I54; - input W_D_I55; - input W_D_I56; - input W_D_I57; - input W_D_I58; - input W_D_I59; - input W_D_I6; - input W_D_I60; - input W_D_I61; - input W_D_I62; - input W_D_I63; - input W_D_I64; - input W_D_I7; - input W_D_I8; - input W_D_I9; - output W_IDM_O1; - output W_IDM_O2; - output W_IDM_O3; - output W_IDM_O4; - output W_IDP_O1; - output W_IDP_O2; - output W_IDP_O3; - output W_IDP_O4; - input W_IDS_I1; - input W_IDS_I2; - input W_IDS_I3; - input W_IDS_I4; - input W_IDS_I5; - input W_IDS_I6; - input W_IDS_I7; - input W_IDS_I8; - output W_LSTM_O; - output W_LSTP_O; - input W_LST_I; - output W_RDY_O; - input W_RYM_I; - input W_RYP_I; - output W_SBM_O1; - output W_SBM_O2; - output W_SBM_O3; - output W_SBM_O4; - output W_SBM_O5; - output W_SBM_O6; - output W_SBM_O7; - output W_SBM_O8; - output W_SBP_O1; - output W_SBP_O2; - output W_SBP_O3; - output W_SBP_O4; - input W_SBS_I1; - input W_SBS_I2; - input W_SBS_I3; - input W_SBS_I4; - input W_SBS_I5; - input W_SBS_I6; - input W_SBS_I7; - input W_SBS_I8; - output W_VDM_O; - output W_VDP_O; - input W_VD_I; -endmodule - -(* blackbox *) -module NX_R5_L_WRAP(CLKIN, nRESET0, nSYSPORESET, nCPUHALT0, DBGNOCLKSTOP, nCLKSTOPPED0, nWFEPIPESTOPPED0, nWFIPIPESTOPPED0, EVENTI0, EVENTO0, VINITHI0, CFGEE, CFGIE, INITRAMA0, LOCZRAMA0, TEINIT, CFGNMFI0, PARECCENRAM0, PARITYLEVEL, ERRENRAM0, INITPPX0 -, nFIQ0, nIRQ0, nPMUIRQ0, ACLKENM0, AWREADYM0, AWSHAREM0, AWVALIDM0, WLASTM0, WREADYM0, WVALIDM0, BREADYM0, BVALIDM0, ARREADYM0, ARSHAREM0, ARVALIDM0, RLASTM0, RREADYM0, RVALIDM0, ACLKENS0, AWREADYS0, AWVALIDS0 -, WLASTS0, WREADYS0, WVALIDS0, BREADYS0, BVALIDS0, ARREADYS0, ARVALIDS0, RLASTS0, RREADYS0, RVALIDS0, ACLKENP0, AWVALIDP0, AWREADYP0, WLASTP0, WVALIDP0, WREADYP0, BVALIDP0, BREADYP0, ARVALIDP0, ARREADYP0, RLASTP0 -, RVALIDP0, RREADYP0, DBGEN0, NIDEN0, EDBGRQ0, DBGACK0, DBGRSTREQ0, COMMRX0, COMMTX0, DBGNOPWRDWN, DBGROMADDRV, DBGSELFADDRV0, nETMPORESET, ETMEN0, nVALIRQ0, nVALFIQ0, nVALRESET0, FPIXC0, FPOFC0, FPUFC0, FPIOC0 -, FPDZC0, FPIDC0, ATRESETn, TRACECLK, TRACECTL, PCLKSYS, PCLKENSYS, PRESETSYSn, PENABLESYS, PREADYSYS, PSELSYS, PSLVERRSYS, PWRITESYS, CDBGPWRUPACK, CDBGPWRUPREQ, CDBGRSTACK, CDBGRSTREQ, CSYSPWRUPACK, CSYSPWRUPREQ, DEVICEEN, JTAGNSW -, nPOTRST, nTDOEN, nTRST, SWCLKTCK, SWDITMS, SWDO, SWDOEN, TDI, TDO, PPXBASE0, PPXSIZE0, PPVBASE0, PPVSIZE0, AWADDRM0, AWBURSTM0, AWCACHEM0, AWIDM0, AWLENM0, AWLOCKM0, AWPROTM0, AWSIZEM0 -, AWINNERM0, WDATAM0, WIDM0, WSTRBM0, BIDM0, BRESPM0, ARADDRM0, ARBURSTM0, ARCACHEM0, ARIDM0, ARLENM0, ARLOCKM0, ARPROTM0, ARSIZEM0, ARINNERM0, RDATAM0, RIDM0, RRESPM0, AWADDRS0, AWBURSTS0, AWCACHES0 -, AWIDS0, AWLENS0, AWLOCKS0, AWPROTS0, AWSIZES0, WDATAS0, WIDS0, WSTRBS0, BIDS0, BRESPS0, ARADDRS0, ARBURSTS0, ARCACHES0, ARIDS0, ARLENS0, ARLOCKS0, ARPROTS0, ARSIZES0, RDATAS0, RIDS0, RRESPS0 -, AWIDP0, AWADDRP0, AWLENP0, AWSIZEP0, AWBURSTP0, AWLOCKP0, AWCACHEP0, AWPROTP0, WIDP0, WDATAP0, WSTRBP0, BIDP0, BRESPP0, ARIDP0, ARADDRP0, ARLENP0, ARSIZEP0, ARBURSTP0, ARLOCKP0, ARCACHEP0, ARPROTP0 -, RIDP0, RDATAP0, RRESPP0, DBGROMADDR, DBGSELFADDR0, ETMASICCTL0, ETMEXTOUT0, TRACEDATA, PADDRSYS, PRDATASYS, PWDATASYS, GROUPID); - input ACLKENM0; - input ACLKENP0; - input ACLKENS0; - output [31:0] ARADDRM0; - output [31:0] ARADDRP0; - input [31:0] ARADDRS0; - output [1:0] ARBURSTM0; - output [1:0] ARBURSTP0; - input [1:0] ARBURSTS0; - output [3:0] ARCACHEM0; - output [3:0] ARCACHEP0; - input [3:0] ARCACHES0; - output [3:0] ARIDM0; - output [3:0] ARIDP0; - input [7:0] ARIDS0; - output [3:0] ARINNERM0; - output [3:0] ARLENM0; - output [3:0] ARLENP0; - input [3:0] ARLENS0; - output [1:0] ARLOCKM0; - output [1:0] ARLOCKP0; - input [1:0] ARLOCKS0; - output [2:0] ARPROTM0; - output [2:0] ARPROTP0; - input [2:0] ARPROTS0; - input ARREADYM0; - input ARREADYP0; - output ARREADYS0; - output ARSHAREM0; - output [2:0] ARSIZEM0; - output [2:0] ARSIZEP0; - input [2:0] ARSIZES0; - output ARVALIDM0; - output ARVALIDP0; - input ARVALIDS0; - input ATRESETn; - output [31:0] AWADDRM0; - output [31:0] AWADDRP0; - input [31:0] AWADDRS0; - output [1:0] AWBURSTM0; - output [1:0] AWBURSTP0; - input [1:0] AWBURSTS0; - output [3:0] AWCACHEM0; - output [3:0] AWCACHEP0; - input [3:0] AWCACHES0; - output [3:0] AWIDM0; - output [3:0] AWIDP0; - input [7:0] AWIDS0; - output [3:0] AWINNERM0; - output [3:0] AWLENM0; - output [3:0] AWLENP0; - input [3:0] AWLENS0; - output [1:0] AWLOCKM0; - output [1:0] AWLOCKP0; - input [1:0] AWLOCKS0; - output [2:0] AWPROTM0; - output [2:0] AWPROTP0; - input [2:0] AWPROTS0; - input AWREADYM0; - input AWREADYP0; - output AWREADYS0; - output AWSHAREM0; - output [2:0] AWSIZEM0; - output [2:0] AWSIZEP0; - input [2:0] AWSIZES0; - output AWVALIDM0; - output AWVALIDP0; - input AWVALIDS0; - input [3:0] BIDM0; - input [3:0] BIDP0; - output [7:0] BIDS0; - output BREADYM0; - output BREADYP0; - input BREADYS0; - input [1:0] BRESPM0; - input [1:0] BRESPP0; - output [1:0] BRESPS0; - input BVALIDM0; - input BVALIDP0; - output BVALIDS0; - input CDBGPWRUPACK; - output CDBGPWRUPREQ; - input CDBGRSTACK; - output CDBGRSTREQ; - input CFGEE; - input CFGIE; - input CFGNMFI0; - input CLKIN; - output COMMRX0; - output COMMTX0; - input CSYSPWRUPACK; - output CSYSPWRUPREQ; - output DBGACK0; - input DBGEN0; - input DBGNOCLKSTOP; - output DBGNOPWRDWN; - input [19:0] DBGROMADDR; - input DBGROMADDRV; - output DBGRSTREQ0; - input [19:0] DBGSELFADDR0; - input DBGSELFADDRV0; - input DEVICEEN; - input EDBGRQ0; - input ERRENRAM0; - output [7:0] ETMASICCTL0; - output ETMEN0; - output [1:0] ETMEXTOUT0; - input EVENTI0; - output EVENTO0; - output FPDZC0; - output FPIDC0; - output FPIOC0; - output FPIXC0; - output FPOFC0; - output FPUFC0; - input [3:0] GROUPID; - input INITPPX0; - input INITRAMA0; - output JTAGNSW; - input LOCZRAMA0; - input NIDEN0; - input [28:0] PADDRSYS; - input PARECCENRAM0; - input PARITYLEVEL; - input PCLKENSYS; - input PCLKSYS; - input PENABLESYS; - input [19:0] PPVBASE0; - input [4:0] PPVSIZE0; - input [19:0] PPXBASE0; - input [4:0] PPXSIZE0; - output [31:0] PRDATASYS; - output PREADYSYS; - input PRESETSYSn; - input PSELSYS; - output PSLVERRSYS; - input [31:0] PWDATASYS; - input PWRITESYS; - input [63:0] RDATAM0; - input [31:0] RDATAP0; - output [63:0] RDATAS0; - input [3:0] RIDM0; - input [3:0] RIDP0; - output [7:0] RIDS0; - input RLASTM0; - input RLASTP0; - output RLASTS0; - output RREADYM0; - output RREADYP0; - input RREADYS0; - input [1:0] RRESPM0; - input [1:0] RRESPP0; - output [1:0] RRESPS0; - input RVALIDM0; - input RVALIDP0; - output RVALIDS0; - input SWCLKTCK; - input SWDITMS; - output SWDO; - output SWDOEN; - input TDI; - output TDO; - input TEINIT; - output TRACECLK; - output TRACECTL; - output [31:0] TRACEDATA; - input VINITHI0; - output [63:0] WDATAM0; - output [31:0] WDATAP0; - input [63:0] WDATAS0; - output [3:0] WIDM0; - output [3:0] WIDP0; - input [7:0] WIDS0; - output WLASTM0; - output WLASTP0; - input WLASTS0; - input WREADYM0; - input WREADYP0; - output WREADYS0; - output [7:0] WSTRBM0; - output [3:0] WSTRBP0; - input [7:0] WSTRBS0; - output WVALIDM0; - output WVALIDP0; - input WVALIDS0; - output nCLKSTOPPED0; - input nCPUHALT0; - input nETMPORESET; - input nFIQ0; - input nIRQ0; - output nPMUIRQ0; - input nPOTRST; - input nRESET0; - input nSYSPORESET; - output nTDOEN; - input nTRST; - output nVALFIQ0; - output nVALIRQ0; - output nVALRESET0; - output nWFEPIPESTOPPED0; - output nWFIPIPESTOPPED0; -endmodule - (* blackbox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 @@ -11085,21688 +9706,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD parameter weakTermination = ""; endmodule -(* blackbox *) -module NX_SERVICE_IF_U(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7 -, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20 -, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2 -, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4 -, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10 -, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31 -, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7 -, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7 -, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13 -, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34 -, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20 -, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6 -, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27 -, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12 -, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1 -, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22 -, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2 -, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7 -, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o -, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15 -, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36 -, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11 -, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32 -, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53 -, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74 -, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95 -, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116 -, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9 -, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30 -, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51 -, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72 -, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93 -, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114 -, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1, fabric_thsens_fm_mode_w_i2 -, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22, fabric_thsens_fm_mode_w_i23 -, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10, fabric_thsens_fm_config_w_i11 -, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3, fabric_thsens_fm_data_o4 -, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8, fabric_thsens_fm_mode_r_o9 -, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29, fabric_thsens_fm_mode_r_o30 -, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18, fabric_thsens_fm_config_r_o19 -, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5 -, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26 -, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8 -, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2 -, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8 -, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2 -, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23 -, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44 -, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17 -, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38 -, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2 -, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2 -, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5 -, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8 -, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2 -, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17 -, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6 -, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2 -, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17 -, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7 -, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28 -, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i -, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1 -, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22 -, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12 -, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o -); - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_clk_bsm_o; - input fabric_clk_otp_mux_i; - output fabric_clk_otp_o; - output fabric_clk_user0_o; - output fabric_clk_user1_o; - input fabric_enable_TMR_i1; - input fabric_enable_TMR_i2; - input fabric_enable_TMR_i3; - output fabric_flag_ready_TMR_o1; - output fabric_flag_ready_TMR_o2; - output fabric_flag_ready_TMR_o3; - output fabric_flag_trigger0_o; - output fabric_flag_trigger1_o; - input fabric_io_in_i1; - input fabric_io_in_i10; - input fabric_io_in_i11; - input fabric_io_in_i12; - input fabric_io_in_i13; - input fabric_io_in_i14; - input fabric_io_in_i15; - input fabric_io_in_i16; - input fabric_io_in_i17; - input fabric_io_in_i18; - input fabric_io_in_i19; - input fabric_io_in_i2; - input fabric_io_in_i20; - input fabric_io_in_i21; - input fabric_io_in_i22; - input fabric_io_in_i23; - input fabric_io_in_i24; - input fabric_io_in_i25; - input fabric_io_in_i26; - input fabric_io_in_i27; - input fabric_io_in_i28; - input fabric_io_in_i29; - input fabric_io_in_i3; - input fabric_io_in_i30; - input fabric_io_in_i31; - input fabric_io_in_i32; - input fabric_io_in_i33; - input fabric_io_in_i34; - input fabric_io_in_i35; - input fabric_io_in_i4; - input fabric_io_in_i5; - input fabric_io_in_i6; - input fabric_io_in_i7; - input fabric_io_in_i8; - input fabric_io_in_i9; - input fabric_io_oe_i1; - input fabric_io_oe_i10; - input fabric_io_oe_i11; - input fabric_io_oe_i12; - input fabric_io_oe_i13; - input fabric_io_oe_i14; - input fabric_io_oe_i15; - input fabric_io_oe_i16; - input fabric_io_oe_i17; - input fabric_io_oe_i18; - input fabric_io_oe_i19; - input fabric_io_oe_i2; - input fabric_io_oe_i20; - input fabric_io_oe_i21; - input fabric_io_oe_i22; - input fabric_io_oe_i23; - input fabric_io_oe_i24; - input fabric_io_oe_i25; - input fabric_io_oe_i26; - input fabric_io_oe_i27; - input fabric_io_oe_i28; - input fabric_io_oe_i29; - input fabric_io_oe_i3; - input fabric_io_oe_i30; - input fabric_io_oe_i31; - input fabric_io_oe_i32; - input fabric_io_oe_i33; - input fabric_io_oe_i34; - input fabric_io_oe_i35; - input fabric_io_oe_i4; - input fabric_io_oe_i5; - input fabric_io_oe_i6; - input fabric_io_oe_i7; - input fabric_io_oe_i8; - input fabric_io_oe_i9; - output fabric_io_out_o1; - output fabric_io_out_o10; - output fabric_io_out_o11; - output fabric_io_out_o12; - output fabric_io_out_o13; - output fabric_io_out_o14; - output fabric_io_out_o15; - output fabric_io_out_o16; - output fabric_io_out_o17; - output fabric_io_out_o18; - output fabric_io_out_o19; - output fabric_io_out_o2; - output fabric_io_out_o20; - output fabric_io_out_o21; - output fabric_io_out_o22; - output fabric_io_out_o23; - output fabric_io_out_o24; - output fabric_io_out_o25; - output fabric_io_out_o26; - output fabric_io_out_o27; - output fabric_io_out_o28; - output fabric_io_out_o29; - output fabric_io_out_o3; - output fabric_io_out_o30; - output fabric_io_out_o31; - output fabric_io_out_o32; - output fabric_io_out_o33; - output fabric_io_out_o34; - output fabric_io_out_o35; - output fabric_io_out_o4; - output fabric_io_out_o5; - output fabric_io_out_o6; - output fabric_io_out_o7; - output fabric_io_out_o8; - output fabric_io_out_o9; - output fabric_jtag_tck_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i1; - input fabric_lowskew_i10; - input fabric_lowskew_i11; - input fabric_lowskew_i12; - input fabric_lowskew_i13; - input fabric_lowskew_i14; - input fabric_lowskew_i15; - input fabric_lowskew_i16; - input fabric_lowskew_i17; - input fabric_lowskew_i18; - input fabric_lowskew_i19; - input fabric_lowskew_i2; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - input fabric_lowskew_i24; - input fabric_lowskew_i25; - input fabric_lowskew_i26; - input fabric_lowskew_i27; - input fabric_lowskew_i28; - input fabric_lowskew_i29; - input fabric_lowskew_i3; - input fabric_lowskew_i30; - input fabric_lowskew_i31; - input fabric_lowskew_i32; - input fabric_lowskew_i33; - input fabric_lowskew_i34; - input fabric_lowskew_i35; - input fabric_lowskew_i36; - input fabric_lowskew_i37; - input fabric_lowskew_i38; - input fabric_lowskew_i39; - input fabric_lowskew_i4; - input fabric_lowskew_i40; - input fabric_lowskew_i5; - input fabric_lowskew_i6; - input fabric_lowskew_i7; - input fabric_lowskew_i8; - input fabric_lowskew_i9; - output fabric_lowskew_o1; - output fabric_lowskew_o2; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - output fabric_otp_user_ack_o; - input fabric_otp_user_add_i1; - input fabric_otp_user_add_i2; - input fabric_otp_user_add_i3; - input fabric_otp_user_add_i4; - input fabric_otp_user_add_i5; - input fabric_otp_user_add_i6; - input fabric_otp_user_add_i7; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output fabric_otp_user_bist1fail_o1; - output fabric_otp_user_bist1fail_o2; - output fabric_otp_user_bist1fail_o3; - output fabric_otp_user_bist1fail_o4; - output fabric_otp_user_bist1fail_o5; - output fabric_otp_user_bist1fail_o6; - output fabric_otp_user_bist1fail_o7; - output fabric_otp_user_bist1fail_o8; - output fabric_otp_user_bist2fail_o1; - output fabric_otp_user_bist2fail_o2; - output fabric_otp_user_bist2fail_o3; - output fabric_otp_user_bist2fail_o4; - output fabric_otp_user_bist2fail_o5; - output fabric_otp_user_bist2fail_o6; - output fabric_otp_user_bist2fail_o7; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clk_i; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input fabric_otp_user_din_i1; - input fabric_otp_user_din_i10; - input fabric_otp_user_din_i11; - input fabric_otp_user_din_i12; - input fabric_otp_user_din_i13; - input fabric_otp_user_din_i14; - input fabric_otp_user_din_i15; - input fabric_otp_user_din_i16; - input fabric_otp_user_din_i17; - input fabric_otp_user_din_i18; - input fabric_otp_user_din_i19; - input fabric_otp_user_din_i2; - input fabric_otp_user_din_i20; - input fabric_otp_user_din_i21; - input fabric_otp_user_din_i22; - input fabric_otp_user_din_i23; - input fabric_otp_user_din_i24; - input fabric_otp_user_din_i25; - input fabric_otp_user_din_i26; - input fabric_otp_user_din_i27; - input fabric_otp_user_din_i28; - input fabric_otp_user_din_i29; - input fabric_otp_user_din_i3; - input fabric_otp_user_din_i30; - input fabric_otp_user_din_i31; - input fabric_otp_user_din_i32; - input fabric_otp_user_din_i33; - input fabric_otp_user_din_i34; - input fabric_otp_user_din_i35; - input fabric_otp_user_din_i36; - input fabric_otp_user_din_i37; - input fabric_otp_user_din_i38; - input fabric_otp_user_din_i39; - input fabric_otp_user_din_i4; - input fabric_otp_user_din_i5; - input fabric_otp_user_din_i6; - input fabric_otp_user_din_i7; - input fabric_otp_user_din_i8; - input fabric_otp_user_din_i9; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output fabric_otp_user_dout_o1; - output fabric_otp_user_dout_o10; - output fabric_otp_user_dout_o11; - output fabric_otp_user_dout_o12; - output fabric_otp_user_dout_o13; - output fabric_otp_user_dout_o14; - output fabric_otp_user_dout_o15; - output fabric_otp_user_dout_o16; - output fabric_otp_user_dout_o17; - output fabric_otp_user_dout_o18; - output fabric_otp_user_dout_o19; - output fabric_otp_user_dout_o2; - output fabric_otp_user_dout_o20; - output fabric_otp_user_dout_o21; - output fabric_otp_user_dout_o22; - output fabric_otp_user_dout_o23; - output fabric_otp_user_dout_o24; - output fabric_otp_user_dout_o25; - output fabric_otp_user_dout_o26; - output fabric_otp_user_dout_o27; - output fabric_otp_user_dout_o28; - output fabric_otp_user_dout_o29; - output fabric_otp_user_dout_o3; - output fabric_otp_user_dout_o30; - output fabric_otp_user_dout_o31; - output fabric_otp_user_dout_o32; - output fabric_otp_user_dout_o33; - output fabric_otp_user_dout_o34; - output fabric_otp_user_dout_o35; - output fabric_otp_user_dout_o36; - output fabric_otp_user_dout_o37; - output fabric_otp_user_dout_o38; - output fabric_otp_user_dout_o39; - output fabric_otp_user_dout_o4; - output fabric_otp_user_dout_o40; - output fabric_otp_user_dout_o41; - output fabric_otp_user_dout_o5; - output fabric_otp_user_dout_o6; - output fabric_otp_user_dout_o7; - output fabric_otp_user_dout_o8; - output fabric_otp_user_dout_o9; - input fabric_otp_user_eccbypass_i; - output fabric_otp_user_flagstate_o1; - output fabric_otp_user_flagstate_o2; - output fabric_otp_user_flagstate_o3; - output fabric_otp_user_flagstate_o4; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input fabric_otp_user_prgwidth_i1; - input fabric_otp_user_prgwidth_i2; - input fabric_otp_user_prgwidth_i3; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output fabric_otp_user_startword_o1; - output fabric_otp_user_startword_o10; - output fabric_otp_user_startword_o11; - output fabric_otp_user_startword_o12; - output fabric_otp_user_startword_o13; - output fabric_otp_user_startword_o14; - output fabric_otp_user_startword_o15; - output fabric_otp_user_startword_o16; - output fabric_otp_user_startword_o2; - output fabric_otp_user_startword_o3; - output fabric_otp_user_startword_o4; - output fabric_otp_user_startword_o5; - output fabric_otp_user_startword_o6; - output fabric_otp_user_startword_o7; - output fabric_otp_user_startword_o8; - output fabric_otp_user_startword_o9; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input fabric_otp_user_tst_scanin_i1; - input fabric_otp_user_tst_scanin_i2; - input fabric_otp_user_tst_scanin_i3; - input fabric_otp_user_tst_scanin_i4; - input fabric_otp_user_tst_scanin_i5; - output fabric_otp_user_tst_scanout_o1; - output fabric_otp_user_tst_scanout_o2; - output fabric_otp_user_tst_scanout_o3; - output fabric_otp_user_tst_scanout_o4; - output fabric_otp_user_tst_scanout_o5; - output fabric_otp_user_wlromout_o1; - output fabric_otp_user_wlromout_o10; - output fabric_otp_user_wlromout_o2; - output fabric_otp_user_wlromout_o3; - output fabric_otp_user_wlromout_o4; - output fabric_otp_user_wlromout_o5; - output fabric_otp_user_wlromout_o6; - output fabric_otp_user_wlromout_o7; - output fabric_otp_user_wlromout_o8; - output fabric_otp_user_wlromout_o9; - input fabric_otp_user_wordlock_i; - input fabric_parusr_clk_i; - input fabric_parusr_cs_i; - input fabric_parusr_data_i1; - input fabric_parusr_data_i10; - input fabric_parusr_data_i11; - input fabric_parusr_data_i12; - input fabric_parusr_data_i13; - input fabric_parusr_data_i14; - input fabric_parusr_data_i15; - input fabric_parusr_data_i16; - input fabric_parusr_data_i2; - input fabric_parusr_data_i3; - input fabric_parusr_data_i4; - input fabric_parusr_data_i5; - input fabric_parusr_data_i6; - input fabric_parusr_data_i7; - input fabric_parusr_data_i8; - input fabric_parusr_data_i9; - output fabric_parusr_data_o1; - output fabric_parusr_data_o10; - output fabric_parusr_data_o11; - output fabric_parusr_data_o12; - output fabric_parusr_data_o13; - output fabric_parusr_data_o14; - output fabric_parusr_data_o15; - output fabric_parusr_data_o16; - output fabric_parusr_data_o2; - output fabric_parusr_data_o3; - output fabric_parusr_data_o4; - output fabric_parusr_data_o5; - output fabric_parusr_data_o6; - output fabric_parusr_data_o7; - output fabric_parusr_data_o8; - output fabric_parusr_data_o9; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input fabric_parusr_type_i1; - input fabric_parusr_type_i2; - input fabric_spare_i1; - input fabric_spare_i10; - input fabric_spare_i100; - input fabric_spare_i101; - input fabric_spare_i102; - input fabric_spare_i103; - input fabric_spare_i104; - input fabric_spare_i105; - input fabric_spare_i106; - input fabric_spare_i107; - input fabric_spare_i108; - input fabric_spare_i109; - input fabric_spare_i11; - input fabric_spare_i110; - input fabric_spare_i111; - input fabric_spare_i112; - input fabric_spare_i113; - input fabric_spare_i114; - input fabric_spare_i115; - input fabric_spare_i116; - input fabric_spare_i117; - input fabric_spare_i118; - input fabric_spare_i119; - input fabric_spare_i12; - input fabric_spare_i120; - input fabric_spare_i121; - input fabric_spare_i122; - input fabric_spare_i123; - input fabric_spare_i124; - input fabric_spare_i125; - input fabric_spare_i126; - input fabric_spare_i127; - input fabric_spare_i128; - input fabric_spare_i13; - input fabric_spare_i14; - input fabric_spare_i15; - input fabric_spare_i16; - input fabric_spare_i17; - input fabric_spare_i18; - input fabric_spare_i19; - input fabric_spare_i2; - input fabric_spare_i20; - input fabric_spare_i21; - input fabric_spare_i22; - input fabric_spare_i23; - input fabric_spare_i24; - input fabric_spare_i25; - input fabric_spare_i26; - input fabric_spare_i27; - input fabric_spare_i28; - input fabric_spare_i29; - input fabric_spare_i3; - input fabric_spare_i30; - input fabric_spare_i31; - input fabric_spare_i32; - input fabric_spare_i33; - input fabric_spare_i34; - input fabric_spare_i35; - input fabric_spare_i36; - input fabric_spare_i37; - input fabric_spare_i38; - input fabric_spare_i39; - input fabric_spare_i4; - input fabric_spare_i40; - input fabric_spare_i41; - input fabric_spare_i42; - input fabric_spare_i43; - input fabric_spare_i44; - input fabric_spare_i45; - input fabric_spare_i46; - input fabric_spare_i47; - input fabric_spare_i48; - input fabric_spare_i49; - input fabric_spare_i5; - input fabric_spare_i50; - input fabric_spare_i51; - input fabric_spare_i52; - input fabric_spare_i53; - input fabric_spare_i54; - input fabric_spare_i55; - input fabric_spare_i56; - input fabric_spare_i57; - input fabric_spare_i58; - input fabric_spare_i59; - input fabric_spare_i6; - input fabric_spare_i60; - input fabric_spare_i61; - input fabric_spare_i62; - input fabric_spare_i63; - input fabric_spare_i64; - input fabric_spare_i65; - input fabric_spare_i66; - input fabric_spare_i67; - input fabric_spare_i68; - input fabric_spare_i69; - input fabric_spare_i7; - input fabric_spare_i70; - input fabric_spare_i71; - input fabric_spare_i72; - input fabric_spare_i73; - input fabric_spare_i74; - input fabric_spare_i75; - input fabric_spare_i76; - input fabric_spare_i77; - input fabric_spare_i78; - input fabric_spare_i79; - input fabric_spare_i8; - input fabric_spare_i80; - input fabric_spare_i81; - input fabric_spare_i82; - input fabric_spare_i83; - input fabric_spare_i84; - input fabric_spare_i85; - input fabric_spare_i86; - input fabric_spare_i87; - input fabric_spare_i88; - input fabric_spare_i89; - input fabric_spare_i9; - input fabric_spare_i90; - input fabric_spare_i91; - input fabric_spare_i92; - input fabric_spare_i93; - input fabric_spare_i94; - input fabric_spare_i95; - input fabric_spare_i96; - input fabric_spare_i97; - input fabric_spare_i98; - input fabric_spare_i99; - output fabric_spare_o1; - output fabric_spare_o10; - output fabric_spare_o100; - output fabric_spare_o101; - output fabric_spare_o102; - output fabric_spare_o103; - output fabric_spare_o104; - output fabric_spare_o105; - output fabric_spare_o106; - output fabric_spare_o107; - output fabric_spare_o108; - output fabric_spare_o109; - output fabric_spare_o11; - output fabric_spare_o110; - output fabric_spare_o111; - output fabric_spare_o112; - output fabric_spare_o113; - output fabric_spare_o114; - output fabric_spare_o115; - output fabric_spare_o116; - output fabric_spare_o117; - output fabric_spare_o118; - output fabric_spare_o119; - output fabric_spare_o12; - output fabric_spare_o120; - output fabric_spare_o121; - output fabric_spare_o122; - output fabric_spare_o123; - output fabric_spare_o124; - output fabric_spare_o125; - output fabric_spare_o126; - output fabric_spare_o127; - output fabric_spare_o128; - output fabric_spare_o13; - output fabric_spare_o14; - output fabric_spare_o15; - output fabric_spare_o16; - output fabric_spare_o17; - output fabric_spare_o18; - output fabric_spare_o19; - output fabric_spare_o2; - output fabric_spare_o20; - output fabric_spare_o21; - output fabric_spare_o22; - output fabric_spare_o23; - output fabric_spare_o24; - output fabric_spare_o25; - output fabric_spare_o26; - output fabric_spare_o27; - output fabric_spare_o28; - output fabric_spare_o29; - output fabric_spare_o3; - output fabric_spare_o30; - output fabric_spare_o31; - output fabric_spare_o32; - output fabric_spare_o33; - output fabric_spare_o34; - output fabric_spare_o35; - output fabric_spare_o36; - output fabric_spare_o37; - output fabric_spare_o38; - output fabric_spare_o39; - output fabric_spare_o4; - output fabric_spare_o40; - output fabric_spare_o41; - output fabric_spare_o42; - output fabric_spare_o43; - output fabric_spare_o44; - output fabric_spare_o45; - output fabric_spare_o46; - output fabric_spare_o47; - output fabric_spare_o48; - output fabric_spare_o49; - output fabric_spare_o5; - output fabric_spare_o50; - output fabric_spare_o51; - output fabric_spare_o52; - output fabric_spare_o53; - output fabric_spare_o54; - output fabric_spare_o55; - output fabric_spare_o56; - output fabric_spare_o57; - output fabric_spare_o58; - output fabric_spare_o59; - output fabric_spare_o6; - output fabric_spare_o60; - output fabric_spare_o61; - output fabric_spare_o62; - output fabric_spare_o63; - output fabric_spare_o64; - output fabric_spare_o65; - output fabric_spare_o66; - output fabric_spare_o67; - output fabric_spare_o68; - output fabric_spare_o69; - output fabric_spare_o7; - output fabric_spare_o70; - output fabric_spare_o71; - output fabric_spare_o72; - output fabric_spare_o73; - output fabric_spare_o74; - output fabric_spare_o75; - output fabric_spare_o76; - output fabric_spare_o77; - output fabric_spare_o78; - output fabric_spare_o79; - output fabric_spare_o8; - output fabric_spare_o80; - output fabric_spare_o81; - output fabric_spare_o82; - output fabric_spare_o83; - output fabric_spare_o84; - output fabric_spare_o85; - output fabric_spare_o86; - output fabric_spare_o87; - output fabric_spare_o88; - output fabric_spare_o89; - output fabric_spare_o9; - output fabric_spare_o90; - output fabric_spare_o91; - output fabric_spare_o92; - output fabric_spare_o93; - output fabric_spare_o94; - output fabric_spare_o95; - output fabric_spare_o96; - output fabric_spare_o97; - output fabric_spare_o98; - output fabric_spare_o99; - input fabric_spi_arst_tmr_n_i1; - input fabric_spi_arst_tmr_n_i2; - input fabric_spi_arst_tmr_n_i3; - input fabric_spi_arst_tmr_n_i4; - input fabric_spi_arst_tmr_n_i5; - input fabric_spi_arst_tmr_n_i6; - input fabric_spi_arst_tmr_n_i7; - input fabric_spi_arst_tmr_n_i8; - input fabric_spi_arst_tmr_n_i9; - output fabric_spi_bsm_release_o1; - output fabric_spi_bsm_release_o2; - output fabric_spi_bsm_release_o3; - output fabric_spi_busy_o1; - output fabric_spi_busy_o2; - output fabric_spi_busy_o3; - input fabric_spi_clk_i0; - input fabric_spi_clk_i1; - input fabric_spi_clk_i2; - input fabric_spi_cmd_bytes_i1; - input fabric_spi_cmd_bytes_i2; - input fabric_spi_cmd_bytes_i3; - input fabric_spi_cmd_bytes_i4; - input fabric_spi_cmd_bytes_i5; - input fabric_spi_cmd_bytes_i6; - output fabric_spi_cmd_full_o1; - output fabric_spi_cmd_full_o2; - output fabric_spi_cmd_full_o3; - input fabric_spi_cmd_mode_i1; - input fabric_spi_cmd_mode_i2; - input fabric_spi_cmd_mode_i3; - input fabric_spi_cmd_mode_i4; - input fabric_spi_cmd_mode_i5; - input fabric_spi_cmd_mode_i6; - input fabric_spi_cmd_push_i1; - input fabric_spi_cmd_push_i2; - input fabric_spi_cmd_push_i3; - input fabric_spi_cmd_type_i1; - input fabric_spi_cmd_type_i2; - input fabric_spi_cmd_type_i3; - input fabric_spi_cmd_type_i4; - input fabric_spi_cmd_type_i5; - input fabric_spi_cmd_type_i6; - input fabric_spi_cpha_i1; - input fabric_spi_cpha_i2; - input fabric_spi_cpha_i3; - input fabric_spi_cpol_i1; - input fabric_spi_cpol_i2; - input fabric_spi_cpol_i3; - input fabric_spi_cs_holdtime_i1; - input fabric_spi_cs_holdtime_i10; - input fabric_spi_cs_holdtime_i11; - input fabric_spi_cs_holdtime_i12; - input fabric_spi_cs_holdtime_i2; - input fabric_spi_cs_holdtime_i3; - input fabric_spi_cs_holdtime_i4; - input fabric_spi_cs_holdtime_i5; - input fabric_spi_cs_holdtime_i6; - input fabric_spi_cs_holdtime_i7; - input fabric_spi_cs_holdtime_i8; - input fabric_spi_cs_holdtime_i9; - input fabric_spi_cs_offtime_i1; - input fabric_spi_cs_offtime_i10; - input fabric_spi_cs_offtime_i11; - input fabric_spi_cs_offtime_i12; - input fabric_spi_cs_offtime_i2; - input fabric_spi_cs_offtime_i3; - input fabric_spi_cs_offtime_i4; - input fabric_spi_cs_offtime_i5; - input fabric_spi_cs_offtime_i6; - input fabric_spi_cs_offtime_i7; - input fabric_spi_cs_offtime_i8; - input fabric_spi_cs_offtime_i9; - input fabric_spi_cs_setuptime_i1; - input fabric_spi_cs_setuptime_i10; - input fabric_spi_cs_setuptime_i11; - input fabric_spi_cs_setuptime_i12; - input fabric_spi_cs_setuptime_i2; - input fabric_spi_cs_setuptime_i3; - input fabric_spi_cs_setuptime_i4; - input fabric_spi_cs_setuptime_i5; - input fabric_spi_cs_setuptime_i6; - input fabric_spi_cs_setuptime_i7; - input fabric_spi_cs_setuptime_i8; - input fabric_spi_cs_setuptime_i9; - input fabric_spi_data_in_unlimited_i1; - input fabric_spi_data_in_unlimited_i2; - input fabric_spi_data_in_unlimited_i3; - input fabric_spi_enable_i1; - input fabric_spi_enable_i2; - input fabric_spi_enable_i3; - output fabric_spi_error_endianness_o1; - output fabric_spi_error_endianness_o2; - output fabric_spi_error_endianness_o3; - output fabric_spi_error_loopback_o1; - output fabric_spi_error_loopback_o2; - output fabric_spi_error_loopback_o3; - output fabric_spi_error_mode_o1; - output fabric_spi_error_mode_o2; - output fabric_spi_error_mode_o3; - output fabric_spi_error_sel_o1; - output fabric_spi_error_sel_o2; - output fabric_spi_error_sel_o3; - input fabric_spi_fifo_arst_tmr_n_i1; - input fabric_spi_fifo_arst_tmr_n_i2; - input fabric_spi_fifo_arst_tmr_n_i3; - input fabric_spi_fifo_arst_tmr_n_i4; - input fabric_spi_fifo_arst_tmr_n_i5; - input fabric_spi_fifo_arst_tmr_n_i6; - input fabric_spi_fifo_arst_tmr_n_i7; - input fabric_spi_fifo_arst_tmr_n_i8; - input fabric_spi_fifo_arst_tmr_n_i9; - output fabric_spi_init_done_o1; - output fabric_spi_init_done_o2; - output fabric_spi_init_done_o3; - input fabric_spi_legacy_enable_i1; - input fabric_spi_legacy_enable_i2; - input fabric_spi_legacy_enable_i3; - input fabric_spi_legacy_master_i1; - input fabric_spi_legacy_master_i2; - input fabric_spi_legacy_master_i3; - input fabric_spi_loopback_i1; - input fabric_spi_loopback_i2; - input fabric_spi_loopback_i3; - input fabric_spi_lsb_first_i1; - input fabric_spi_lsb_first_i2; - input fabric_spi_lsb_first_i3; - output fabric_spi_miso_data_inv_o1; - output fabric_spi_miso_data_inv_o2; - output fabric_spi_miso_data_inv_o3; - output fabric_spi_miso_data_o1; - output fabric_spi_miso_data_o10; - output fabric_spi_miso_data_o11; - output fabric_spi_miso_data_o12; - output fabric_spi_miso_data_o13; - output fabric_spi_miso_data_o14; - output fabric_spi_miso_data_o15; - output fabric_spi_miso_data_o16; - output fabric_spi_miso_data_o17; - output fabric_spi_miso_data_o18; - output fabric_spi_miso_data_o19; - output fabric_spi_miso_data_o2; - output fabric_spi_miso_data_o20; - output fabric_spi_miso_data_o21; - output fabric_spi_miso_data_o22; - output fabric_spi_miso_data_o23; - output fabric_spi_miso_data_o24; - output fabric_spi_miso_data_o3; - output fabric_spi_miso_data_o4; - output fabric_spi_miso_data_o5; - output fabric_spi_miso_data_o6; - output fabric_spi_miso_data_o7; - output fabric_spi_miso_data_o8; - output fabric_spi_miso_data_o9; - output fabric_spi_miso_empty_o1; - output fabric_spi_miso_empty_o2; - output fabric_spi_miso_empty_o3; - input fabric_spi_miso_pop_i1; - input fabric_spi_miso_pop_i2; - input fabric_spi_miso_pop_i3; - input fabric_spi_mosi_data_i1; - input fabric_spi_mosi_data_i10; - input fabric_spi_mosi_data_i11; - input fabric_spi_mosi_data_i12; - input fabric_spi_mosi_data_i13; - input fabric_spi_mosi_data_i14; - input fabric_spi_mosi_data_i15; - input fabric_spi_mosi_data_i16; - input fabric_spi_mosi_data_i17; - input fabric_spi_mosi_data_i18; - input fabric_spi_mosi_data_i19; - input fabric_spi_mosi_data_i2; - input fabric_spi_mosi_data_i20; - input fabric_spi_mosi_data_i21; - input fabric_spi_mosi_data_i22; - input fabric_spi_mosi_data_i23; - input fabric_spi_mosi_data_i24; - input fabric_spi_mosi_data_i3; - input fabric_spi_mosi_data_i4; - input fabric_spi_mosi_data_i5; - input fabric_spi_mosi_data_i6; - input fabric_spi_mosi_data_i7; - input fabric_spi_mosi_data_i8; - input fabric_spi_mosi_data_i9; - input fabric_spi_mosi_data_inv_i1; - input fabric_spi_mosi_data_inv_i2; - input fabric_spi_mosi_data_inv_i3; - output fabric_spi_mosi_full_o1; - output fabric_spi_mosi_full_o2; - output fabric_spi_mosi_full_o3; - input fabric_spi_mosi_push_i1; - input fabric_spi_mosi_push_i2; - input fabric_spi_mosi_push_i3; - input fabric_spi_needed_i1; - input fabric_spi_needed_i2; - input fabric_spi_needed_i3; - input fabric_spi_powerdown_cycle_i1; - input fabric_spi_powerdown_cycle_i10; - input fabric_spi_powerdown_cycle_i11; - input fabric_spi_powerdown_cycle_i12; - input fabric_spi_powerdown_cycle_i13; - input fabric_spi_powerdown_cycle_i14; - input fabric_spi_powerdown_cycle_i15; - input fabric_spi_powerdown_cycle_i16; - input fabric_spi_powerdown_cycle_i17; - input fabric_spi_powerdown_cycle_i18; - input fabric_spi_powerdown_cycle_i19; - input fabric_spi_powerdown_cycle_i2; - input fabric_spi_powerdown_cycle_i20; - input fabric_spi_powerdown_cycle_i21; - input fabric_spi_powerdown_cycle_i22; - input fabric_spi_powerdown_cycle_i23; - input fabric_spi_powerdown_cycle_i24; - input fabric_spi_powerdown_cycle_i25; - input fabric_spi_powerdown_cycle_i26; - input fabric_spi_powerdown_cycle_i27; - input fabric_spi_powerdown_cycle_i28; - input fabric_spi_powerdown_cycle_i29; - input fabric_spi_powerdown_cycle_i3; - input fabric_spi_powerdown_cycle_i30; - input fabric_spi_powerdown_cycle_i31; - input fabric_spi_powerdown_cycle_i32; - input fabric_spi_powerdown_cycle_i33; - input fabric_spi_powerdown_cycle_i34; - input fabric_spi_powerdown_cycle_i35; - input fabric_spi_powerdown_cycle_i36; - input fabric_spi_powerdown_cycle_i37; - input fabric_spi_powerdown_cycle_i38; - input fabric_spi_powerdown_cycle_i39; - input fabric_spi_powerdown_cycle_i4; - input fabric_spi_powerdown_cycle_i40; - input fabric_spi_powerdown_cycle_i41; - input fabric_spi_powerdown_cycle_i42; - input fabric_spi_powerdown_cycle_i43; - input fabric_spi_powerdown_cycle_i44; - input fabric_spi_powerdown_cycle_i45; - input fabric_spi_powerdown_cycle_i46; - input fabric_spi_powerdown_cycle_i47; - input fabric_spi_powerdown_cycle_i48; - input fabric_spi_powerdown_cycle_i5; - input fabric_spi_powerdown_cycle_i6; - input fabric_spi_powerdown_cycle_i7; - input fabric_spi_powerdown_cycle_i8; - input fabric_spi_powerdown_cycle_i9; - input fabric_spi_powerup_cycle_i1; - input fabric_spi_powerup_cycle_i10; - input fabric_spi_powerup_cycle_i11; - input fabric_spi_powerup_cycle_i12; - input fabric_spi_powerup_cycle_i13; - input fabric_spi_powerup_cycle_i14; - input fabric_spi_powerup_cycle_i15; - input fabric_spi_powerup_cycle_i16; - input fabric_spi_powerup_cycle_i17; - input fabric_spi_powerup_cycle_i18; - input fabric_spi_powerup_cycle_i19; - input fabric_spi_powerup_cycle_i2; - input fabric_spi_powerup_cycle_i20; - input fabric_spi_powerup_cycle_i21; - input fabric_spi_powerup_cycle_i22; - input fabric_spi_powerup_cycle_i23; - input fabric_spi_powerup_cycle_i24; - input fabric_spi_powerup_cycle_i25; - input fabric_spi_powerup_cycle_i26; - input fabric_spi_powerup_cycle_i27; - input fabric_spi_powerup_cycle_i28; - input fabric_spi_powerup_cycle_i29; - input fabric_spi_powerup_cycle_i3; - input fabric_spi_powerup_cycle_i30; - input fabric_spi_powerup_cycle_i31; - input fabric_spi_powerup_cycle_i32; - input fabric_spi_powerup_cycle_i33; - input fabric_spi_powerup_cycle_i34; - input fabric_spi_powerup_cycle_i35; - input fabric_spi_powerup_cycle_i36; - input fabric_spi_powerup_cycle_i37; - input fabric_spi_powerup_cycle_i38; - input fabric_spi_powerup_cycle_i39; - input fabric_spi_powerup_cycle_i4; - input fabric_spi_powerup_cycle_i40; - input fabric_spi_powerup_cycle_i41; - input fabric_spi_powerup_cycle_i42; - input fabric_spi_powerup_cycle_i43; - input fabric_spi_powerup_cycle_i44; - input fabric_spi_powerup_cycle_i45; - input fabric_spi_powerup_cycle_i46; - input fabric_spi_powerup_cycle_i47; - input fabric_spi_powerup_cycle_i48; - input fabric_spi_powerup_cycle_i5; - input fabric_spi_powerup_cycle_i6; - input fabric_spi_powerup_cycle_i7; - input fabric_spi_powerup_cycle_i8; - input fabric_spi_powerup_cycle_i9; - input fabric_spi_rst_n_i1; - input fabric_spi_rst_n_i2; - input fabric_spi_rst_n_i3; - input fabric_spi_sck_i0; - input fabric_spi_sck_i1; - input fabric_spi_sck_i2; - input fabric_spi_vcc_enable_i1; - input fabric_spi_vcc_enable_i2; - input fabric_spi_vcc_enable_i3; - output fabric_spi_vcc_used_o1; - output fabric_spi_vcc_used_o2; - output fabric_spi_vcc_used_o3; - input fabric_spw0_apb_slv_paddr_i1; - input fabric_spw0_apb_slv_paddr_i2; - input fabric_spw0_apb_slv_paddr_i3; - input fabric_spw0_apb_slv_paddr_i4; - input fabric_spw0_apb_slv_paddr_i5; - input fabric_spw0_apb_slv_penable_i; - output fabric_spw0_apb_slv_prdata_o1; - output fabric_spw0_apb_slv_prdata_o10; - output fabric_spw0_apb_slv_prdata_o11; - output fabric_spw0_apb_slv_prdata_o12; - output fabric_spw0_apb_slv_prdata_o13; - output fabric_spw0_apb_slv_prdata_o14; - output fabric_spw0_apb_slv_prdata_o15; - output fabric_spw0_apb_slv_prdata_o16; - output fabric_spw0_apb_slv_prdata_o17; - output fabric_spw0_apb_slv_prdata_o18; - output fabric_spw0_apb_slv_prdata_o19; - output fabric_spw0_apb_slv_prdata_o2; - output fabric_spw0_apb_slv_prdata_o20; - output fabric_spw0_apb_slv_prdata_o21; - output fabric_spw0_apb_slv_prdata_o22; - output fabric_spw0_apb_slv_prdata_o23; - output fabric_spw0_apb_slv_prdata_o24; - output fabric_spw0_apb_slv_prdata_o25; - output fabric_spw0_apb_slv_prdata_o26; - output fabric_spw0_apb_slv_prdata_o27; - output fabric_spw0_apb_slv_prdata_o28; - output fabric_spw0_apb_slv_prdata_o29; - output fabric_spw0_apb_slv_prdata_o3; - output fabric_spw0_apb_slv_prdata_o30; - output fabric_spw0_apb_slv_prdata_o31; - output fabric_spw0_apb_slv_prdata_o4; - output fabric_spw0_apb_slv_prdata_o5; - output fabric_spw0_apb_slv_prdata_o6; - output fabric_spw0_apb_slv_prdata_o7; - output fabric_spw0_apb_slv_prdata_o8; - output fabric_spw0_apb_slv_prdata_o9; - output fabric_spw0_apb_slv_pready_o; - input fabric_spw0_apb_slv_psel_i; - output fabric_spw0_apb_slv_pslverr_o; - input fabric_spw0_apb_slv_pwdata_i1; - input fabric_spw0_apb_slv_pwdata_i10; - input fabric_spw0_apb_slv_pwdata_i11; - input fabric_spw0_apb_slv_pwdata_i12; - input fabric_spw0_apb_slv_pwdata_i13; - input fabric_spw0_apb_slv_pwdata_i14; - input fabric_spw0_apb_slv_pwdata_i15; - input fabric_spw0_apb_slv_pwdata_i16; - input fabric_spw0_apb_slv_pwdata_i17; - input fabric_spw0_apb_slv_pwdata_i18; - input fabric_spw0_apb_slv_pwdata_i19; - input fabric_spw0_apb_slv_pwdata_i2; - input fabric_spw0_apb_slv_pwdata_i20; - input fabric_spw0_apb_slv_pwdata_i21; - input fabric_spw0_apb_slv_pwdata_i22; - input fabric_spw0_apb_slv_pwdata_i23; - input fabric_spw0_apb_slv_pwdata_i24; - input fabric_spw0_apb_slv_pwdata_i25; - input fabric_spw0_apb_slv_pwdata_i26; - input fabric_spw0_apb_slv_pwdata_i27; - input fabric_spw0_apb_slv_pwdata_i28; - input fabric_spw0_apb_slv_pwdata_i29; - input fabric_spw0_apb_slv_pwdata_i3; - input fabric_spw0_apb_slv_pwdata_i30; - input fabric_spw0_apb_slv_pwdata_i31; - input fabric_spw0_apb_slv_pwdata_i4; - input fabric_spw0_apb_slv_pwdata_i5; - input fabric_spw0_apb_slv_pwdata_i6; - input fabric_spw0_apb_slv_pwdata_i7; - input fabric_spw0_apb_slv_pwdata_i8; - input fabric_spw0_apb_slv_pwdata_i9; - input fabric_spw0_apb_slv_pwrite_i; - input fabric_spw0_clk_i; - input fabric_spw0_clk_tx_i; - input fabric_spw0_rst_n_i; - output fabric_spw0_rx_fifo_data_o1; - output fabric_spw0_rx_fifo_data_o2; - output fabric_spw0_rx_fifo_data_o3; - output fabric_spw0_rx_fifo_data_o4; - output fabric_spw0_rx_fifo_data_o5; - output fabric_spw0_rx_fifo_data_o6; - output fabric_spw0_rx_fifo_data_o7; - output fabric_spw0_rx_fifo_data_o8; - output fabric_spw0_rx_fifo_data_o9; - output fabric_spw0_rx_fifo_empty_o; - input fabric_spw0_rx_fifo_read_i; - input fabric_spw0_tick_ctm_i; - output fabric_spw0_tick_ctm_o; - input fabric_spw0_tx_fifo_data_i1; - input fabric_spw0_tx_fifo_data_i2; - input fabric_spw0_tx_fifo_data_i3; - input fabric_spw0_tx_fifo_data_i4; - input fabric_spw0_tx_fifo_data_i5; - input fabric_spw0_tx_fifo_data_i6; - input fabric_spw0_tx_fifo_data_i7; - input fabric_spw0_tx_fifo_data_i8; - input fabric_spw0_tx_fifo_data_i9; - output fabric_spw0_tx_fifo_full_o; - input fabric_spw0_tx_fifo_write_i; - output fabric_spw0_user_shared_o; - input fabric_spw1_apb_slv_paddr_i1; - input fabric_spw1_apb_slv_paddr_i2; - input fabric_spw1_apb_slv_paddr_i3; - input fabric_spw1_apb_slv_paddr_i4; - input fabric_spw1_apb_slv_paddr_i5; - input fabric_spw1_apb_slv_penable_i; - output fabric_spw1_apb_slv_prdata_o1; - output fabric_spw1_apb_slv_prdata_o10; - output fabric_spw1_apb_slv_prdata_o11; - output fabric_spw1_apb_slv_prdata_o12; - output fabric_spw1_apb_slv_prdata_o13; - output fabric_spw1_apb_slv_prdata_o14; - output fabric_spw1_apb_slv_prdata_o15; - output fabric_spw1_apb_slv_prdata_o16; - output fabric_spw1_apb_slv_prdata_o17; - output fabric_spw1_apb_slv_prdata_o18; - output fabric_spw1_apb_slv_prdata_o19; - output fabric_spw1_apb_slv_prdata_o2; - output fabric_spw1_apb_slv_prdata_o20; - output fabric_spw1_apb_slv_prdata_o21; - output fabric_spw1_apb_slv_prdata_o22; - output fabric_spw1_apb_slv_prdata_o23; - output fabric_spw1_apb_slv_prdata_o24; - output fabric_spw1_apb_slv_prdata_o25; - output fabric_spw1_apb_slv_prdata_o26; - output fabric_spw1_apb_slv_prdata_o27; - output fabric_spw1_apb_slv_prdata_o28; - output fabric_spw1_apb_slv_prdata_o29; - output fabric_spw1_apb_slv_prdata_o3; - output fabric_spw1_apb_slv_prdata_o30; - output fabric_spw1_apb_slv_prdata_o31; - output fabric_spw1_apb_slv_prdata_o4; - output fabric_spw1_apb_slv_prdata_o5; - output fabric_spw1_apb_slv_prdata_o6; - output fabric_spw1_apb_slv_prdata_o7; - output fabric_spw1_apb_slv_prdata_o8; - output fabric_spw1_apb_slv_prdata_o9; - output fabric_spw1_apb_slv_pready_o; - input fabric_spw1_apb_slv_psel_i; - output fabric_spw1_apb_slv_pslverr_o; - input fabric_spw1_apb_slv_pwdata_i1; - input fabric_spw1_apb_slv_pwdata_i10; - input fabric_spw1_apb_slv_pwdata_i11; - input fabric_spw1_apb_slv_pwdata_i12; - input fabric_spw1_apb_slv_pwdata_i13; - input fabric_spw1_apb_slv_pwdata_i14; - input fabric_spw1_apb_slv_pwdata_i15; - input fabric_spw1_apb_slv_pwdata_i16; - input fabric_spw1_apb_slv_pwdata_i17; - input fabric_spw1_apb_slv_pwdata_i18; - input fabric_spw1_apb_slv_pwdata_i19; - input fabric_spw1_apb_slv_pwdata_i2; - input fabric_spw1_apb_slv_pwdata_i20; - input fabric_spw1_apb_slv_pwdata_i21; - input fabric_spw1_apb_slv_pwdata_i22; - input fabric_spw1_apb_slv_pwdata_i23; - input fabric_spw1_apb_slv_pwdata_i24; - input fabric_spw1_apb_slv_pwdata_i25; - input fabric_spw1_apb_slv_pwdata_i26; - input fabric_spw1_apb_slv_pwdata_i27; - input fabric_spw1_apb_slv_pwdata_i28; - input fabric_spw1_apb_slv_pwdata_i29; - input fabric_spw1_apb_slv_pwdata_i3; - input fabric_spw1_apb_slv_pwdata_i30; - input fabric_spw1_apb_slv_pwdata_i31; - input fabric_spw1_apb_slv_pwdata_i4; - input fabric_spw1_apb_slv_pwdata_i5; - input fabric_spw1_apb_slv_pwdata_i6; - input fabric_spw1_apb_slv_pwdata_i7; - input fabric_spw1_apb_slv_pwdata_i8; - input fabric_spw1_apb_slv_pwdata_i9; - input fabric_spw1_apb_slv_pwrite_i; - input fabric_spw1_clk_i; - input fabric_spw1_clk_tx_i; - input fabric_spw1_rst_n_i; - output fabric_spw1_rx_fifo_data_o1; - output fabric_spw1_rx_fifo_data_o2; - output fabric_spw1_rx_fifo_data_o3; - output fabric_spw1_rx_fifo_data_o4; - output fabric_spw1_rx_fifo_data_o5; - output fabric_spw1_rx_fifo_data_o6; - output fabric_spw1_rx_fifo_data_o7; - output fabric_spw1_rx_fifo_data_o8; - output fabric_spw1_rx_fifo_data_o9; - output fabric_spw1_rx_fifo_empty_o; - input fabric_spw1_rx_fifo_read_i; - input fabric_spw1_tick_ctm_i; - output fabric_spw1_tick_ctm_o; - input fabric_spw1_tx_fifo_data_i1; - input fabric_spw1_tx_fifo_data_i2; - input fabric_spw1_tx_fifo_data_i3; - input fabric_spw1_tx_fifo_data_i4; - input fabric_spw1_tx_fifo_data_i5; - input fabric_spw1_tx_fifo_data_i6; - input fabric_spw1_tx_fifo_data_i7; - input fabric_spw1_tx_fifo_data_i8; - input fabric_spw1_tx_fifo_data_i9; - output fabric_spw1_tx_fifo_full_o; - input fabric_spw1_tx_fifo_write_i; - output fabric_spw1_user_shared_o; - output fabric_status_cold_start_o; - input fabric_thsens_arst_tmr_n_i1; - input fabric_thsens_arst_tmr_n_i2; - input fabric_thsens_arst_tmr_n_i3; - input fabric_thsens_clk_div_ratio_i1; - input fabric_thsens_clk_div_ratio_i2; - input fabric_thsens_clk_div_ratio_i3; - input fabric_thsens_clk_div_ratio_i4; - input fabric_thsens_clk_div_ratio_i5; - input fabric_thsens_clk_div_ratio_i6; - input fabric_thsens_clk_div_ratio_i7; - input fabric_thsens_clk_div_ratio_i8; - input fabric_thsens_clk_i; - output fabric_thsens_fm_config_r_o1; - output fabric_thsens_fm_config_r_o10; - output fabric_thsens_fm_config_r_o11; - output fabric_thsens_fm_config_r_o12; - output fabric_thsens_fm_config_r_o13; - output fabric_thsens_fm_config_r_o14; - output fabric_thsens_fm_config_r_o15; - output fabric_thsens_fm_config_r_o16; - output fabric_thsens_fm_config_r_o17; - output fabric_thsens_fm_config_r_o18; - output fabric_thsens_fm_config_r_o19; - output fabric_thsens_fm_config_r_o2; - output fabric_thsens_fm_config_r_o20; - output fabric_thsens_fm_config_r_o21; - output fabric_thsens_fm_config_r_o22; - output fabric_thsens_fm_config_r_o23; - output fabric_thsens_fm_config_r_o24; - output fabric_thsens_fm_config_r_o25; - output fabric_thsens_fm_config_r_o26; - output fabric_thsens_fm_config_r_o27; - output fabric_thsens_fm_config_r_o3; - output fabric_thsens_fm_config_r_o4; - output fabric_thsens_fm_config_r_o5; - output fabric_thsens_fm_config_r_o6; - output fabric_thsens_fm_config_r_o7; - output fabric_thsens_fm_config_r_o8; - output fabric_thsens_fm_config_r_o9; - input fabric_thsens_fm_config_w_i1; - input fabric_thsens_fm_config_w_i10; - input fabric_thsens_fm_config_w_i11; - input fabric_thsens_fm_config_w_i12; - input fabric_thsens_fm_config_w_i13; - input fabric_thsens_fm_config_w_i14; - input fabric_thsens_fm_config_w_i15; - input fabric_thsens_fm_config_w_i16; - input fabric_thsens_fm_config_w_i17; - input fabric_thsens_fm_config_w_i18; - input fabric_thsens_fm_config_w_i19; - input fabric_thsens_fm_config_w_i2; - input fabric_thsens_fm_config_w_i20; - input fabric_thsens_fm_config_w_i21; - input fabric_thsens_fm_config_w_i22; - input fabric_thsens_fm_config_w_i23; - input fabric_thsens_fm_config_w_i24; - input fabric_thsens_fm_config_w_i25; - input fabric_thsens_fm_config_w_i26; - input fabric_thsens_fm_config_w_i27; - input fabric_thsens_fm_config_w_i3; - input fabric_thsens_fm_config_w_i4; - input fabric_thsens_fm_config_w_i5; - input fabric_thsens_fm_config_w_i6; - input fabric_thsens_fm_config_w_i7; - input fabric_thsens_fm_config_w_i8; - input fabric_thsens_fm_config_w_i9; - input fabric_thsens_fm_config_wen_i; - output fabric_thsens_fm_data_o1; - output fabric_thsens_fm_data_o10; - output fabric_thsens_fm_data_o11; - output fabric_thsens_fm_data_o12; - output fabric_thsens_fm_data_o13; - output fabric_thsens_fm_data_o14; - output fabric_thsens_fm_data_o2; - output fabric_thsens_fm_data_o3; - output fabric_thsens_fm_data_o4; - output fabric_thsens_fm_data_o5; - output fabric_thsens_fm_data_o6; - output fabric_thsens_fm_data_o7; - output fabric_thsens_fm_data_o8; - output fabric_thsens_fm_data_o9; - input fabric_thsens_fm_enable_i; - output fabric_thsens_fm_mode_r_o1; - output fabric_thsens_fm_mode_r_o10; - output fabric_thsens_fm_mode_r_o11; - output fabric_thsens_fm_mode_r_o12; - output fabric_thsens_fm_mode_r_o13; - output fabric_thsens_fm_mode_r_o14; - output fabric_thsens_fm_mode_r_o15; - output fabric_thsens_fm_mode_r_o16; - output fabric_thsens_fm_mode_r_o17; - output fabric_thsens_fm_mode_r_o18; - output fabric_thsens_fm_mode_r_o19; - output fabric_thsens_fm_mode_r_o2; - output fabric_thsens_fm_mode_r_o20; - output fabric_thsens_fm_mode_r_o21; - output fabric_thsens_fm_mode_r_o22; - output fabric_thsens_fm_mode_r_o23; - output fabric_thsens_fm_mode_r_o24; - output fabric_thsens_fm_mode_r_o25; - output fabric_thsens_fm_mode_r_o26; - output fabric_thsens_fm_mode_r_o27; - output fabric_thsens_fm_mode_r_o28; - output fabric_thsens_fm_mode_r_o29; - output fabric_thsens_fm_mode_r_o3; - output fabric_thsens_fm_mode_r_o30; - output fabric_thsens_fm_mode_r_o31; - output fabric_thsens_fm_mode_r_o32; - output fabric_thsens_fm_mode_r_o4; - output fabric_thsens_fm_mode_r_o5; - output fabric_thsens_fm_mode_r_o6; - output fabric_thsens_fm_mode_r_o7; - output fabric_thsens_fm_mode_r_o8; - output fabric_thsens_fm_mode_r_o9; - input fabric_thsens_fm_mode_w_i1; - input fabric_thsens_fm_mode_w_i10; - input fabric_thsens_fm_mode_w_i11; - input fabric_thsens_fm_mode_w_i12; - input fabric_thsens_fm_mode_w_i13; - input fabric_thsens_fm_mode_w_i14; - input fabric_thsens_fm_mode_w_i15; - input fabric_thsens_fm_mode_w_i16; - input fabric_thsens_fm_mode_w_i17; - input fabric_thsens_fm_mode_w_i18; - input fabric_thsens_fm_mode_w_i19; - input fabric_thsens_fm_mode_w_i2; - input fabric_thsens_fm_mode_w_i20; - input fabric_thsens_fm_mode_w_i21; - input fabric_thsens_fm_mode_w_i22; - input fabric_thsens_fm_mode_w_i23; - input fabric_thsens_fm_mode_w_i24; - input fabric_thsens_fm_mode_w_i25; - input fabric_thsens_fm_mode_w_i26; - input fabric_thsens_fm_mode_w_i27; - input fabric_thsens_fm_mode_w_i28; - input fabric_thsens_fm_mode_w_i29; - input fabric_thsens_fm_mode_w_i3; - input fabric_thsens_fm_mode_w_i30; - input fabric_thsens_fm_mode_w_i31; - input fabric_thsens_fm_mode_w_i32; - input fabric_thsens_fm_mode_w_i4; - input fabric_thsens_fm_mode_w_i5; - input fabric_thsens_fm_mode_w_i6; - input fabric_thsens_fm_mode_w_i7; - input fabric_thsens_fm_mode_w_i8; - input fabric_thsens_fm_mode_w_i9; - input fabric_thsens_fm_mode_wen_i; - output fabric_thsens_fm_overflow_o; - output fabric_thsens_fm_valid_o; - output fabric_thsens_otp_config_o1; - output fabric_thsens_otp_config_o10; - output fabric_thsens_otp_config_o11; - output fabric_thsens_otp_config_o12; - output fabric_thsens_otp_config_o13; - output fabric_thsens_otp_config_o14; - output fabric_thsens_otp_config_o15; - output fabric_thsens_otp_config_o16; - output fabric_thsens_otp_config_o17; - output fabric_thsens_otp_config_o18; - output fabric_thsens_otp_config_o19; - output fabric_thsens_otp_config_o2; - output fabric_thsens_otp_config_o20; - output fabric_thsens_otp_config_o21; - output fabric_thsens_otp_config_o22; - output fabric_thsens_otp_config_o23; - output fabric_thsens_otp_config_o24; - output fabric_thsens_otp_config_o25; - output fabric_thsens_otp_config_o26; - output fabric_thsens_otp_config_o27; - output fabric_thsens_otp_config_o3; - output fabric_thsens_otp_config_o4; - output fabric_thsens_otp_config_o5; - output fabric_thsens_otp_config_o6; - output fabric_thsens_otp_config_o7; - output fabric_thsens_otp_config_o8; - output fabric_thsens_otp_config_o9; - input fabric_user_clk_i; - input fabric_user_data_i1; - input fabric_user_data_i10; - input fabric_user_data_i11; - input fabric_user_data_i12; - input fabric_user_data_i13; - input fabric_user_data_i14; - input fabric_user_data_i15; - input fabric_user_data_i16; - input fabric_user_data_i17; - input fabric_user_data_i18; - input fabric_user_data_i19; - input fabric_user_data_i2; - input fabric_user_data_i20; - input fabric_user_data_i21; - input fabric_user_data_i22; - input fabric_user_data_i23; - input fabric_user_data_i24; - input fabric_user_data_i25; - input fabric_user_data_i26; - input fabric_user_data_i27; - input fabric_user_data_i28; - input fabric_user_data_i29; - input fabric_user_data_i3; - input fabric_user_data_i30; - input fabric_user_data_i31; - input fabric_user_data_i32; - input fabric_user_data_i4; - input fabric_user_data_i5; - input fabric_user_data_i6; - input fabric_user_data_i7; - input fabric_user_data_i8; - input fabric_user_data_i9; - output fabric_user_data_o1; - output fabric_user_data_o10; - output fabric_user_data_o11; - output fabric_user_data_o12; - output fabric_user_data_o13; - output fabric_user_data_o14; - output fabric_user_data_o15; - output fabric_user_data_o16; - output fabric_user_data_o17; - output fabric_user_data_o18; - output fabric_user_data_o19; - output fabric_user_data_o2; - output fabric_user_data_o20; - output fabric_user_data_o21; - output fabric_user_data_o22; - output fabric_user_data_o23; - output fabric_user_data_o24; - output fabric_user_data_o25; - output fabric_user_data_o26; - output fabric_user_data_o27; - output fabric_user_data_o28; - output fabric_user_data_o29; - output fabric_user_data_o3; - output fabric_user_data_o30; - output fabric_user_data_o31; - output fabric_user_data_o32; - output fabric_user_data_o4; - output fabric_user_data_o5; - output fabric_user_data_o6; - output fabric_user_data_o7; - output fabric_user_data_o8; - output fabric_user_data_o9; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_IF_U_FULL(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_data_from_bist_i1, fabric_mrepair_data_from_bist_i2, fabric_mrepair_data_from_bist_i3, fabric_mrepair_data_from_bist_i4, fabric_mrepair_data_from_bist_i5, fabric_mrepair_data_from_bist_i6, fabric_mrepair_data_from_bist_i7, fabric_mrepair_data_from_bist_i8, fabric_mrepair_data_from_bist_i9, fabric_mrepair_data_from_bist_i10, fabric_mrepair_data_from_bist_i11, fabric_mrepair_data_from_bist_i12, fabric_mrepair_data_from_bist_i13, fabric_mrepair_data_from_bist_i14 -, fabric_mrepair_data_from_bist_i15, fabric_mrepair_data_from_bist_i16, fabric_mrepair_data_from_bist_i17, fabric_mrepair_data_from_bist_i18, fabric_mrepair_data_from_bist_i19, fabric_mrepair_data_from_bist_i20, fabric_mrepair_data_from_bist_i21, fabric_mrepair_data_from_bist_i22, fabric_mrepair_data_from_bist_i23, fabric_mrepair_data_from_bist_i24, fabric_mrepair_data_from_bist_i25, fabric_mrepair_data_from_bist_i26, fabric_mrepair_data_to_bist_o1, fabric_mrepair_data_to_bist_o2, fabric_mrepair_data_to_bist_o3, fabric_mrepair_data_to_bist_o4, fabric_mrepair_data_to_bist_o5, fabric_mrepair_data_to_bist_o6, fabric_mrepair_data_to_bist_o7, fabric_mrepair_data_to_bist_o8, fabric_mrepair_data_to_bist_o9 -, fabric_mrepair_data_to_bist_o10, fabric_mrepair_data_to_bist_o11, fabric_mrepair_data_to_bist_o12, fabric_mrepair_data_to_bist_o13, fabric_mrepair_data_to_bist_o14, fabric_mrepair_data_to_bist_o15, fabric_mrepair_data_to_bist_o16, fabric_mrepair_data_to_bist_o17, fabric_mrepair_data_to_bist_o18, fabric_mrepair_data_to_bist_o19, fabric_mrepair_data_to_bist_o20, fabric_mrepair_data_to_bist_o21, fabric_mrepair_data_to_bist_o22, fabric_mrepair_data_to_bist_o23, fabric_mrepair_data_to_bist_o24, fabric_mrepair_data_to_bist_o25, fabric_mrepair_data_to_bist_o26, fabric_mrepair_shift_en_to_bist_o1, fabric_mrepair_shift_en_to_bist_o2, fabric_mrepair_shift_en_to_bist_o3, fabric_mrepair_shift_en_to_bist_o4 -, fabric_mrepair_shift_en_to_bist_o5, fabric_mrepair_shift_en_to_bist_o6, fabric_mrepair_shift_en_to_bist_o7, fabric_mrepair_shift_en_to_bist_o8, fabric_mrepair_shift_en_to_bist_o9, fabric_mrepair_shift_en_to_bist_o10, fabric_mrepair_shift_en_to_bist_o11, fabric_mrepair_shift_en_to_bist_o12, fabric_mrepair_shift_en_to_bist_o13, fabric_mrepair_shift_en_to_bist_o14, fabric_mrepair_shift_en_to_bist_o15, fabric_mrepair_shift_en_to_bist_o16, fabric_mrepair_shift_en_to_bist_o17, fabric_mrepair_shift_en_to_bist_o18, fabric_mrepair_shift_en_to_bist_o19, fabric_mrepair_shift_en_to_bist_o20, fabric_mrepair_shift_en_to_bist_o21, fabric_mrepair_shift_en_to_bist_o22, fabric_mrepair_shift_en_to_bist_o23, fabric_mrepair_shift_en_to_bist_o24, fabric_mrepair_shift_en_to_bist_o25 -, fabric_mrepair_shift_en_to_bist_o26, fabric_mrepair_sif_load_en_to_bist_o1, fabric_mrepair_sif_load_en_to_bist_o2, fabric_mrepair_sif_load_en_to_bist_o3, fabric_mrepair_sif_load_en_to_bist_o4, fabric_mrepair_sif_load_en_to_bist_o5, fabric_mrepair_sif_load_en_to_bist_o6, fabric_mrepair_sif_load_en_to_bist_o7, fabric_mrepair_sif_load_en_to_bist_o8, fabric_mrepair_sif_load_en_to_bist_o9, fabric_mrepair_sif_load_en_to_bist_o10, fabric_mrepair_sif_load_en_to_bist_o11, fabric_mrepair_sif_load_en_to_bist_o12, fabric_mrepair_sif_load_en_to_bist_o13, fabric_mrepair_sif_load_en_to_bist_o14, fabric_mrepair_sif_load_en_to_bist_o15, fabric_mrepair_sif_load_en_to_bist_o16, fabric_mrepair_sif_load_en_to_bist_o17, fabric_mrepair_sif_load_en_to_bist_o18, fabric_mrepair_sif_load_en_to_bist_o19, fabric_mrepair_sif_load_en_to_bist_o20 -, fabric_mrepair_sif_load_en_to_bist_o21, fabric_mrepair_sif_load_en_to_bist_o22, fabric_mrepair_sif_load_en_to_bist_o23, fabric_mrepair_sif_load_en_to_bist_o24, fabric_mrepair_sif_load_en_to_bist_o25, fabric_mrepair_sif_load_en_to_bist_o26, fabric_mrepair_sif_update_en_to_bist_o1, fabric_mrepair_sif_update_en_to_bist_o2, fabric_mrepair_sif_update_en_to_bist_o3, fabric_mrepair_sif_update_en_to_bist_o4, fabric_mrepair_sif_update_en_to_bist_o5, fabric_mrepair_sif_update_en_to_bist_o6, fabric_mrepair_sif_update_en_to_bist_o7, fabric_mrepair_sif_update_en_to_bist_o8, fabric_mrepair_sif_update_en_to_bist_o9, fabric_mrepair_sif_update_en_to_bist_o10, fabric_mrepair_sif_update_en_to_bist_o11, fabric_mrepair_sif_update_en_to_bist_o12, fabric_mrepair_sif_update_en_to_bist_o13, fabric_mrepair_sif_update_en_to_bist_o14, fabric_mrepair_sif_update_en_to_bist_o15 -, fabric_mrepair_sif_update_en_to_bist_o16, fabric_mrepair_sif_update_en_to_bist_o17, fabric_mrepair_sif_update_en_to_bist_o18, fabric_mrepair_sif_update_en_to_bist_o19, fabric_mrepair_sif_update_en_to_bist_o20, fabric_mrepair_sif_update_en_to_bist_o21, fabric_mrepair_sif_update_en_to_bist_o22, fabric_mrepair_sif_update_en_to_bist_o23, fabric_mrepair_sif_update_en_to_bist_o24, fabric_mrepair_sif_update_en_to_bist_o25, fabric_mrepair_sif_update_en_to_bist_o26, fabric_mrepair_sif_reg_en_to_bist_o1, fabric_mrepair_sif_reg_en_to_bist_o2, fabric_mrepair_sif_reg_en_to_bist_o3, fabric_mrepair_sif_reg_en_to_bist_o4, fabric_mrepair_sif_reg_en_to_bist_o5, fabric_mrepair_sif_reg_en_to_bist_o6, fabric_mrepair_sif_reg_en_to_bist_o7, fabric_mrepair_sif_reg_en_to_bist_o8, fabric_mrepair_sif_reg_en_to_bist_o9, fabric_mrepair_sif_reg_en_to_bist_o10 -, fabric_mrepair_sif_reg_en_to_bist_o11, fabric_mrepair_sif_reg_en_to_bist_o12, fabric_mrepair_sif_reg_en_to_bist_o13, fabric_mrepair_sif_reg_en_to_bist_o14, fabric_mrepair_sif_reg_en_to_bist_o15, fabric_mrepair_sif_reg_en_to_bist_o16, fabric_mrepair_sif_reg_en_to_bist_o17, fabric_mrepair_sif_reg_en_to_bist_o18, fabric_mrepair_sif_reg_en_to_bist_o19, fabric_mrepair_sif_reg_en_to_bist_o20, fabric_mrepair_sif_reg_en_to_bist_o21, fabric_mrepair_sif_reg_en_to_bist_o22, fabric_mrepair_sif_reg_en_to_bist_o23, fabric_mrepair_sif_reg_en_to_bist_o24, fabric_mrepair_sif_reg_en_to_bist_o25, fabric_mrepair_sif_reg_en_to_bist_o26, fabric_mrepair_system_data_to_mem_bist_i1, fabric_mrepair_system_data_to_mem_bist_i2, fabric_mrepair_system_data_to_mem_bist_i3, fabric_mrepair_system_data_to_mem_bist_i4, fabric_mrepair_system_data_to_mem_bist_i5 -, fabric_mrepair_system_data_to_mem_bist_i6, fabric_mrepair_system_data_to_mem_bist_i7, fabric_mrepair_system_data_to_mem_bist_i8, fabric_mrepair_system_data_to_mem_bist_i9, fabric_mrepair_system_data_to_mem_bist_i10, fabric_mrepair_system_data_to_mem_bist_i11, fabric_mrepair_system_data_to_mem_bist_i12, fabric_mrepair_system_data_to_mem_bist_i13, fabric_mrepair_system_data_to_mem_bist_i14, fabric_mrepair_system_data_to_mem_bist_i15, fabric_mrepair_system_data_to_mem_bist_i16, fabric_mrepair_system_data_to_mem_bist_i17, fabric_mrepair_system_data_to_mem_bist_i18, fabric_mrepair_system_data_to_mem_bist_i19, fabric_mrepair_system_data_to_mem_bist_i20, fabric_mrepair_system_data_to_mem_bist_i21, fabric_mrepair_system_data_to_mem_bist_i22, fabric_mrepair_system_data_to_mem_bist_i23, fabric_mrepair_system_data_to_mem_bist_i24, fabric_mrepair_system_data_to_mem_bist_i25, fabric_mrepair_system_data_to_mem_bist_i26 -, fabric_mrepair_shift_en_i1, fabric_mrepair_shift_en_i2, fabric_mrepair_shift_en_i3, fabric_mrepair_shift_en_i4, fabric_mrepair_shift_en_i5, fabric_mrepair_shift_en_i6, fabric_mrepair_shift_en_i7, fabric_mrepair_shift_en_i8, fabric_mrepair_shift_en_i9, fabric_mrepair_shift_en_i10, fabric_mrepair_shift_en_i11, fabric_mrepair_shift_en_i12, fabric_mrepair_shift_en_i13, fabric_mrepair_shift_en_i14, fabric_mrepair_shift_en_i15, fabric_mrepair_shift_en_i16, fabric_mrepair_shift_en_i17, fabric_mrepair_shift_en_i18, fabric_mrepair_shift_en_i19, fabric_mrepair_shift_en_i20, fabric_mrepair_shift_en_i21 -, fabric_mrepair_shift_en_i22, fabric_mrepair_shift_en_i23, fabric_mrepair_shift_en_i24, fabric_mrepair_shift_en_i25, fabric_mrepair_shift_en_i26, fabric_mrepair_sif_load_en_i1, fabric_mrepair_sif_load_en_i2, fabric_mrepair_sif_load_en_i3, fabric_mrepair_sif_load_en_i4, fabric_mrepair_sif_load_en_i5, fabric_mrepair_sif_load_en_i6, fabric_mrepair_sif_load_en_i7, fabric_mrepair_sif_load_en_i8, fabric_mrepair_sif_load_en_i9, fabric_mrepair_sif_load_en_i10, fabric_mrepair_sif_load_en_i11, fabric_mrepair_sif_load_en_i12, fabric_mrepair_sif_load_en_i13, fabric_mrepair_sif_load_en_i14, fabric_mrepair_sif_load_en_i15, fabric_mrepair_sif_load_en_i16 -, fabric_mrepair_sif_load_en_i17, fabric_mrepair_sif_load_en_i18, fabric_mrepair_sif_load_en_i19, fabric_mrepair_sif_load_en_i20, fabric_mrepair_sif_load_en_i21, fabric_mrepair_sif_load_en_i22, fabric_mrepair_sif_load_en_i23, fabric_mrepair_sif_load_en_i24, fabric_mrepair_sif_load_en_i25, fabric_mrepair_sif_load_en_i26, fabric_mrepair_sif_update_en_i1, fabric_mrepair_sif_update_en_i2, fabric_mrepair_sif_update_en_i3, fabric_mrepair_sif_update_en_i4, fabric_mrepair_sif_update_en_i5, fabric_mrepair_sif_update_en_i6, fabric_mrepair_sif_update_en_i7, fabric_mrepair_sif_update_en_i8, fabric_mrepair_sif_update_en_i9, fabric_mrepair_sif_update_en_i10, fabric_mrepair_sif_update_en_i11 -, fabric_mrepair_sif_update_en_i12, fabric_mrepair_sif_update_en_i13, fabric_mrepair_sif_update_en_i14, fabric_mrepair_sif_update_en_i15, fabric_mrepair_sif_update_en_i16, fabric_mrepair_sif_update_en_i17, fabric_mrepair_sif_update_en_i18, fabric_mrepair_sif_update_en_i19, fabric_mrepair_sif_update_en_i20, fabric_mrepair_sif_update_en_i21, fabric_mrepair_sif_update_en_i22, fabric_mrepair_sif_update_en_i23, fabric_mrepair_sif_update_en_i24, fabric_mrepair_sif_update_en_i25, fabric_mrepair_sif_update_en_i26, fabric_mrepair_sif_reg_en_i1, fabric_mrepair_sif_reg_en_i2, fabric_mrepair_sif_reg_en_i3, fabric_mrepair_sif_reg_en_i4, fabric_mrepair_sif_reg_en_i5, fabric_mrepair_sif_reg_en_i6 -, fabric_mrepair_sif_reg_en_i7, fabric_mrepair_sif_reg_en_i8, fabric_mrepair_sif_reg_en_i9, fabric_mrepair_sif_reg_en_i10, fabric_mrepair_sif_reg_en_i11, fabric_mrepair_sif_reg_en_i12, fabric_mrepair_sif_reg_en_i13, fabric_mrepair_sif_reg_en_i14, fabric_mrepair_sif_reg_en_i15, fabric_mrepair_sif_reg_en_i16, fabric_mrepair_sif_reg_en_i17, fabric_mrepair_sif_reg_en_i18, fabric_mrepair_sif_reg_en_i19, fabric_mrepair_sif_reg_en_i20, fabric_mrepair_sif_reg_en_i21, fabric_mrepair_sif_reg_en_i22, fabric_mrepair_sif_reg_en_i23, fabric_mrepair_sif_reg_en_i24, fabric_mrepair_sif_reg_en_i25, fabric_mrepair_sif_reg_en_i26, fabric_mrepair_system_data_from_mem_bist_o1 -, fabric_mrepair_system_data_from_mem_bist_o2, fabric_mrepair_system_data_from_mem_bist_o3, fabric_mrepair_system_data_from_mem_bist_o4, fabric_mrepair_system_data_from_mem_bist_o5, fabric_mrepair_system_data_from_mem_bist_o6, fabric_mrepair_system_data_from_mem_bist_o7, fabric_mrepair_system_data_from_mem_bist_o8, fabric_mrepair_system_data_from_mem_bist_o9, fabric_mrepair_system_data_from_mem_bist_o10, fabric_mrepair_system_data_from_mem_bist_o11, fabric_mrepair_system_data_from_mem_bist_o12, fabric_mrepair_system_data_from_mem_bist_o13, fabric_mrepair_system_data_from_mem_bist_o14, fabric_mrepair_system_data_from_mem_bist_o15, fabric_mrepair_system_data_from_mem_bist_o16, fabric_mrepair_system_data_from_mem_bist_o17, fabric_mrepair_system_data_from_mem_bist_o18, fabric_mrepair_system_data_from_mem_bist_o19, fabric_mrepair_system_data_from_mem_bist_o20, fabric_mrepair_system_data_from_mem_bist_o21, fabric_mrepair_system_data_from_mem_bist_o22 -, fabric_mrepair_system_data_from_mem_bist_o23, fabric_mrepair_system_data_from_mem_bist_o24, fabric_mrepair_system_data_from_mem_bist_o25, fabric_mrepair_system_data_from_mem_bist_o26, fabric_mrepair_bist_mode_o, fabric_mrepair_mem_type_sel_o1, fabric_mrepair_mem_type_sel_o2, fabric_mrepair_mem_type_sel_o3, fabric_mrepair_mem_type_sel_o4, fabric_mrepair_mem_type_sel_o5, fabric_mrepair_mode_sel_o1, fabric_mrepair_mode_sel_o2, fabric_mrepair_mode_sel_o3, fabric_mrepair_mode_sel_o4, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o -, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_mrepair_pd_active_i1, fabric_mrepair_pd_active_i2, fabric_mrepair_pd_active_i3, fabric_mrepair_pd_active_i4, fabric_mrepair_pd_active_i5, fabric_mrepair_pd_active_i6, fabric_mrepair_pd_active_i7, fabric_mrepair_pd_active_i8, fabric_mrepair_pd_active_i9, fabric_mrepair_pd_active_i10, fabric_mrepair_pd_active_i11, fabric_mrepair_pd_active_i12 -, fabric_mrepair_pd_active_i13, fabric_mrepair_pd_active_i14, fabric_mrepair_pd_active_i15, fabric_mrepair_pd_active_i16, fabric_mrepair_pd_active_i17, fabric_mrepair_pd_active_i18, fabric_mrepair_pd_active_i19, fabric_mrepair_pd_active_i20, fabric_mrepair_pd_active_i21, fabric_mrepair_pd_active_i22, fabric_mrepair_pd_active_i23, fabric_mrepair_pd_active_i24, fabric_mrepair_pd_active_i25, fabric_mrepair_pd_active_i26, fabric_mrepair_chip_status_o1, fabric_mrepair_chip_status_o2, fabric_mrepair_chip_status_o3, fabric_mrepair_chip_status_o4, fabric_mrepair_chip_status_o5, fabric_mrepair_chip_status_o6, fabric_mrepair_chip_status_o7 -, fabric_mrepair_chip_status_o8, fabric_mrepair_chip_status_o9, fabric_mrepair_chip_status_o10, fabric_mrepair_chip_status_o11, fabric_mrepair_chip_status_o12, fabric_mrepair_chip_status_o13, fabric_mrepair_chip_status_o14, fabric_mrepair_chip_status_o15, fabric_mrepair_chip_status_o16, fabric_mrepair_chip_status_o17, fabric_mrepair_chip_status_o18, fabric_mrepair_chip_status_o19, fabric_mrepair_chip_status_o20, fabric_mrepair_chip_status_o21, fabric_mrepair_chip_status_o22, fabric_mrepair_chip_status_o23, fabric_mrepair_chip_status_o24, fabric_mrepair_chip_status_o25, fabric_mrepair_chip_status_o26, fabric_mrepair_chip_status_o27, fabric_mrepair_chip_status_o28 -, fabric_mrepair_chip_status_o29, fabric_mrepair_chip_status_o30, fabric_mrepair_chip_status_o31, fabric_mrepair_chip_status_o32, fabric_mrepair_chip_status_o33, fabric_mrepair_chip_status_o34, fabric_mrepair_chip_status_o35, fabric_mrepair_chip_status_o36, fabric_mrepair_chip_status_o37, fabric_mrepair_chip_status_o38, fabric_mrepair_chip_status_o39, fabric_mrepair_chip_status_o40, fabric_mrepair_chip_status_o41, fabric_mrepair_chip_status_o42, fabric_mrepair_chip_status_o43, fabric_mrepair_chip_status_o44, fabric_mrepair_chip_status_o45, fabric_mrepair_chip_status_o46, fabric_mrepair_chip_status_o47, fabric_mrepair_chip_status_o48, fabric_mrepair_chip_status_o49 -, fabric_mrepair_chip_status_o50, fabric_mrepair_chip_status_o51, fabric_mrepair_chip_status_o52, fabric_mrepair_chip_status_o53, fabric_mrepair_chip_status_o54, fabric_mrepair_chip_status_o55, fabric_mrepair_chip_status_o56, fabric_mrepair_chip_status_o57, fabric_mrepair_chip_status_o58, fabric_mrepair_chip_status_o59, fabric_mrepair_chip_status_o60, fabric_mrepair_chip_status_o61, fabric_mrepair_chip_status_o62, fabric_mrepair_chip_status_o63, fabric_mrepair_chip_status_o64, fabric_mrepair_chip_status_o65, fabric_mrepair_chip_status_o66, fabric_mrepair_chip_status_o67, fabric_mrepair_chip_status_o68, fabric_mrepair_chip_status_o69, fabric_mrepair_chip_status_o70 -, fabric_mrepair_chip_status_o71, fabric_mrepair_chip_status_o72, fabric_mrepair_chip_status_o73, fabric_mrepair_chip_status_o74, fabric_mrepair_chip_status_o75, fabric_mrepair_chip_status_o76, fabric_mrepair_chip_status_o77, fabric_mrepair_chip_status_o78, fabric_mrepair_global_chip_status_o1, fabric_mrepair_global_chip_status_o2, fabric_mrepair_global_chip_status_o3, fabric_mrepair_pd_ready_o1, fabric_mrepair_pd_ready_o2, fabric_mrepair_pd_ready_o3, fabric_mrepair_pd_ready_o4, fabric_mrepair_pd_ready_o5, fabric_mrepair_pd_ready_o6, fabric_mrepair_pd_ready_o7, fabric_mrepair_pd_ready_o8, fabric_mrepair_pd_ready_o9, fabric_mrepair_pd_ready_o10 -, fabric_mrepair_pd_ready_o11, fabric_mrepair_pd_ready_o12, fabric_mrepair_pd_ready_o13, fabric_mrepair_pd_ready_o14, fabric_mrepair_pd_ready_o15, fabric_mrepair_pd_ready_o16, fabric_mrepair_pd_ready_o17, fabric_mrepair_pd_ready_o18, fabric_mrepair_pd_ready_o19, fabric_mrepair_pd_ready_o20, fabric_mrepair_pd_ready_o21, fabric_mrepair_pd_ready_o22, fabric_mrepair_pd_ready_o23, fabric_mrepair_pd_ready_o24, fabric_mrepair_pd_ready_o25, fabric_mrepair_pd_ready_o26, fabric_mrepair_system_dataready_o, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i -, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14 -, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35 -, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2 -, fabric_mrepair_fuse_prgwidth_i3, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18 -, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39 -, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o -, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8 -, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o -, fabric_mrepair_fuse_status_o1, fabric_mrepair_fuse_status_o2, fabric_mrepair_fuse_status_o3, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3 -, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16 -, fabric_otp_user_din_i17, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37 -, fabric_otp_user_din_i38, fabric_otp_user_din_i39, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o -, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6 -, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27 -, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3 -, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3 -, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9 -, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_io_in_i26, fabric_io_in_i27, fabric_io_in_i28, fabric_io_in_i29, fabric_io_in_i30 -, fabric_io_in_i31, fabric_io_in_i32, fabric_io_in_i33, fabric_io_in_i34, fabric_io_in_i35, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16 -, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_io_oe_i26, fabric_io_oe_i27, fabric_io_oe_i28, fabric_io_oe_i29, fabric_io_oe_i30, fabric_io_oe_i31, fabric_io_oe_i32, fabric_io_oe_i33, fabric_io_oe_i34, fabric_io_oe_i35, fabric_io_out_o1, fabric_io_out_o2 -, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23 -, fabric_io_out_o24, fabric_io_out_o25, fabric_io_out_o26, fabric_io_out_o27, fabric_io_out_o28, fabric_io_out_o29, fabric_io_out_o30, fabric_io_out_o31, fabric_io_out_o32, fabric_io_out_o33, fabric_io_out_o34, fabric_io_out_o35, fabric_user_clk_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8 -, fabric_user_data_i9, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29 -, fabric_user_data_i30, fabric_user_data_i31, fabric_user_data_i32, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18 -, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i -, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3 -, fabric_parusr_data_o4, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i -, fabric_jtag_tdo_usr2_i, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20 -, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9 -, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30 -, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17 -, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3 -, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24 -, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_apb_ready_o, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12 -, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_otp_cfg_fabric_apb_en_i -, fabric_otp_cfg_loader_read_en_i, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2 -, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_debug_lifecycle_o1 -, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_debug_frame_use_encryption_o, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2 -, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_debug_key_correct_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_debug_otp_reload_err_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4 -, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25 -, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_enable_TMR_i1, fabric_enable_TMR_i2 -, fabric_enable_TMR_i3, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_lowskew_i20 -, fabric_lowskew_i21, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i24, fabric_lowskew_i25, fabric_lowskew_i26, fabric_lowskew_i27, fabric_lowskew_i28, fabric_lowskew_i29, fabric_lowskew_i30, fabric_lowskew_i31, fabric_lowskew_i32, fabric_lowskew_i33, fabric_lowskew_i34, fabric_lowskew_i35, fabric_lowskew_i36, fabric_lowskew_i37, fabric_lowskew_i38, fabric_lowskew_i39, fabric_lowskew_i40, fabric_lowskew_o1 -, fabric_lowskew_o2, fabric_lowskew_o3, fabric_lowskew_o4, fabric_lowskew_o5, fabric_lowskew_o6, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_spare_i4, fabric_spare_i5, fabric_spare_i6, fabric_spare_i7, fabric_spare_i8, fabric_spare_i9, fabric_spare_i10, fabric_spare_i11, fabric_spare_i12, fabric_spare_i13, fabric_spare_i14, fabric_spare_i15, fabric_spare_i16 -, fabric_spare_i17, fabric_spare_i18, fabric_spare_i19, fabric_spare_i20, fabric_spare_i21, fabric_spare_i22, fabric_spare_i23, fabric_spare_i24, fabric_spare_i25, fabric_spare_i26, fabric_spare_i27, fabric_spare_i28, fabric_spare_i29, fabric_spare_i30, fabric_spare_i31, fabric_spare_i32, fabric_spare_i33, fabric_spare_i34, fabric_spare_i35, fabric_spare_i36, fabric_spare_i37 -, fabric_spare_i38, fabric_spare_i39, fabric_spare_i40, fabric_spare_i41, fabric_spare_i42, fabric_spare_i43, fabric_spare_i44, fabric_spare_i45, fabric_spare_i46, fabric_spare_i47, fabric_spare_i48, fabric_spare_i49, fabric_spare_i50, fabric_spare_i51, fabric_spare_i52, fabric_spare_i53, fabric_spare_i54, fabric_spare_i55, fabric_spare_i56, fabric_spare_i57, fabric_spare_i58 -, fabric_spare_i59, fabric_spare_i60, fabric_spare_i61, fabric_spare_i62, fabric_spare_i63, fabric_spare_i64, fabric_spare_i65, fabric_spare_i66, fabric_spare_i67, fabric_spare_i68, fabric_spare_i69, fabric_spare_i70, fabric_spare_i71, fabric_spare_i72, fabric_spare_i73, fabric_spare_i74, fabric_spare_i75, fabric_spare_i76, fabric_spare_i77, fabric_spare_i78, fabric_spare_i79 -, fabric_spare_i80, fabric_spare_i81, fabric_spare_i82, fabric_spare_i83, fabric_spare_i84, fabric_spare_i85, fabric_spare_i86, fabric_spare_i87, fabric_spare_i88, fabric_spare_i89, fabric_spare_i90, fabric_spare_i91, fabric_spare_i92, fabric_spare_i93, fabric_spare_i94, fabric_spare_i95, fabric_spare_i96, fabric_spare_i97, fabric_spare_i98, fabric_spare_i99, fabric_spare_i100 -, fabric_spare_i101, fabric_spare_i102, fabric_spare_i103, fabric_spare_i104, fabric_spare_i105, fabric_spare_i106, fabric_spare_i107, fabric_spare_i108, fabric_spare_i109, fabric_spare_i110, fabric_spare_i111, fabric_spare_i112, fabric_spare_i113, fabric_spare_i114, fabric_spare_i115, fabric_spare_i116, fabric_spare_i117, fabric_spare_i118, fabric_spare_i119, fabric_spare_i120, fabric_spare_i121 -, fabric_spare_i122, fabric_spare_i123, fabric_spare_i124, fabric_spare_i125, fabric_spare_i126, fabric_spare_i127, fabric_spare_i128, fabric_spare_o1, fabric_spare_o2, fabric_spare_o3, fabric_spare_o4, fabric_spare_o5, fabric_spare_o6, fabric_spare_o7, fabric_spare_o8, fabric_spare_o9, fabric_spare_o10, fabric_spare_o11, fabric_spare_o12, fabric_spare_o13, fabric_spare_o14 -, fabric_spare_o15, fabric_spare_o16, fabric_spare_o17, fabric_spare_o18, fabric_spare_o19, fabric_spare_o20, fabric_spare_o21, fabric_spare_o22, fabric_spare_o23, fabric_spare_o24, fabric_spare_o25, fabric_spare_o26, fabric_spare_o27, fabric_spare_o28, fabric_spare_o29, fabric_spare_o30, fabric_spare_o31, fabric_spare_o32, fabric_spare_o33, fabric_spare_o34, fabric_spare_o35 -, fabric_spare_o36, fabric_spare_o37, fabric_spare_o38, fabric_spare_o39, fabric_spare_o40, fabric_spare_o41, fabric_spare_o42, fabric_spare_o43, fabric_spare_o44, fabric_spare_o45, fabric_spare_o46, fabric_spare_o47, fabric_spare_o48, fabric_spare_o49, fabric_spare_o50, fabric_spare_o51, fabric_spare_o52, fabric_spare_o53, fabric_spare_o54, fabric_spare_o55, fabric_spare_o56 -, fabric_spare_o57, fabric_spare_o58, fabric_spare_o59, fabric_spare_o60, fabric_spare_o61, fabric_spare_o62, fabric_spare_o63, fabric_spare_o64, fabric_spare_o65, fabric_spare_o66, fabric_spare_o67, fabric_spare_o68, fabric_spare_o69, fabric_spare_o70, fabric_spare_o71, fabric_spare_o72, fabric_spare_o73, fabric_spare_o74, fabric_spare_o75, fabric_spare_o76, fabric_spare_o77 -, fabric_spare_o78, fabric_spare_o79, fabric_spare_o80, fabric_spare_o81, fabric_spare_o82, fabric_spare_o83, fabric_spare_o84, fabric_spare_o85, fabric_spare_o86, fabric_spare_o87, fabric_spare_o88, fabric_spare_o89, fabric_spare_o90, fabric_spare_o91, fabric_spare_o92, fabric_spare_o93, fabric_spare_o94, fabric_spare_o95, fabric_spare_o96, fabric_spare_o97, fabric_spare_o98 -, fabric_spare_o99, fabric_spare_o100, fabric_spare_o101, fabric_spare_o102, fabric_spare_o103, fabric_spare_o104, fabric_spare_o105, fabric_spare_o106, fabric_spare_o107, fabric_spare_o108, fabric_spare_o109, fabric_spare_o110, fabric_spare_o111, fabric_spare_o112, fabric_spare_o113, fabric_spare_o114, fabric_spare_o115, fabric_spare_o116, fabric_spare_o117, fabric_spare_o118, fabric_spare_o119 -, fabric_spare_o120, fabric_spare_o121, fabric_spare_o122, fabric_spare_o123, fabric_spare_o124, fabric_spare_o125, fabric_spare_o126, fabric_spare_o127, fabric_spare_o128, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_din_i1, fabric_dac0_din_i2, fabric_dac0_din_i3, fabric_dac0_din_i4, fabric_dac0_din_i5, fabric_dac0_din_i6, fabric_dac0_din_i7, fabric_dac0_din_i8, fabric_dac0_din_i9, fabric_dac0_din_i10 -, fabric_dac0_din_i11, fabric_dac0_din_i12, fabric_dac0_din_i13, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_in_sel_i1, fabric_dac0_comp_in_sel_i2, fabric_dac0_comp_in_sel_i3, fabric_dac0_comp_in_sel_i4, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_res_i1, fabric_cfg_dac0_reg_res_i2, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i -, fabric_dac1_clk_en_i, fabric_dac1_din_i1, fabric_dac1_din_i2, fabric_dac1_din_i3, fabric_dac1_din_i4, fabric_dac1_din_i5, fabric_dac1_din_i6, fabric_dac1_din_i7, fabric_dac1_din_i8, fabric_dac1_din_i9, fabric_dac1_din_i10, fabric_dac1_din_i11, fabric_dac1_din_i12, fabric_dac1_din_i13, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i -, fabric_dac1_comp_in_sel_i1, fabric_dac1_comp_in_sel_i2, fabric_dac1_comp_in_sel_i3, fabric_dac1_comp_in_sel_i4, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_res_i1, fabric_cfg_dac1_reg_res_i2, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_din_i1, fabric_dac2_din_i2, fabric_dac2_din_i3, fabric_dac2_din_i4, fabric_dac2_din_i5, fabric_dac2_din_i6, fabric_dac2_din_i7, fabric_dac2_din_i8, fabric_dac2_din_i9 -, fabric_dac2_din_i10, fabric_dac2_din_i11, fabric_dac2_din_i12, fabric_dac2_din_i13, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_in_sel_i1, fabric_dac2_comp_in_sel_i2, fabric_dac2_comp_in_sel_i3, fabric_dac2_comp_in_sel_i4, fabric_dac2_comp_in_sel_i5, fabric_dac2_comp_in_sel_i6, fabric_dac2_comp_in_sel_i7, fabric_dac2_comp_in_sel_i8, fabric_dac2_comp_in_sel_i9, fabric_dac2_comp_in_sel_i10 -, fabric_dac2_comp_in_sel_i11, fabric_dac2_comp_in_sel_i12, fabric_dac2_comp_in_sel_i13, fabric_dac2_comp_out_o, fabric_cfg_dac2_reg_res_i1, fabric_cfg_dac2_reg_res_i2, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_din_i1, fabric_dac3_din_i2, fabric_dac3_din_i3, fabric_dac3_din_i4, fabric_dac3_din_i5, fabric_dac3_din_i6, fabric_dac3_din_i7, fabric_dac3_din_i8, fabric_dac3_din_i9, fabric_dac3_din_i10 -, fabric_dac3_din_i11, fabric_dac3_din_i12, fabric_dac3_din_i13, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_in_sel_i1, fabric_dac3_comp_in_sel_i2, fabric_dac3_comp_in_sel_i3, fabric_dac3_comp_in_sel_i4, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_res_i1, fabric_cfg_dac3_reg_res_i2, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i -, fabric_adc0_arst_b_tmr_i1, fabric_adc0_arst_b_tmr_i2, fabric_adc0_arst_b_tmr_i3, fabric_adc0_pwr_down_b_tmr_i1, fabric_adc0_pwr_down_b_tmr_i2, fabric_adc0_pwr_down_b_tmr_i3, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_spare_i1, fabric_adc0_spare_i2, fabric_adc0_spare_i3, fabric_adc0_spare_i4, fabric_adc0_spare_i5, fabric_adc0_spare_i6, fabric_adc0_spare_i7, fabric_adc0_spare_i8, fabric_adc0_spare_i9 -, fabric_adc0_spare_i10, fabric_adc0_spare_i11, fabric_adc0_spare_i12, fabric_adc0_spare_i13, fabric_adc0_spare_i14, fabric_adc0_spare_i15, fabric_adc0_spare_i16, fabric_adc0_dft_test_mode_i1, fabric_adc0_dft_test_mode_i2, fabric_adc0_dft_scan_en_i, fabric_adc0_dft_si_i1, fabric_adc0_dft_si_i2, fabric_adc0_dft_si_i3, fabric_adc0_dft_si_i4, fabric_adc0_dft_si_i5, fabric_adc0_dft_si_i6, fabric_adc0_dft_si_i7, fabric_adc0_dft_si_i8, fabric_adc0_dft_si_i9, fabric_adc0_dft_si_i10, fabric_adc0_dft_si_i11 -, fabric_adc0_dft_si_i12, fabric_adc0_usr_cke_i, fabric_adc0_usr_arst_b_tmr_i1, fabric_adc0_usr_arst_b_tmr_i2, fabric_adc0_usr_arst_b_tmr_i3, fabric_adc0_usr_channel_i1, fabric_adc0_usr_channel_i2, fabric_adc0_usr_channel_i3, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_adc0_usr_sample_o1, fabric_adc0_usr_sample_o2, fabric_adc0_usr_sample_o3, fabric_adc0_usr_sample_o4, fabric_adc0_usr_sample_o5, fabric_adc0_usr_sample_o6, fabric_adc0_usr_sample_o7, fabric_adc0_usr_sample_o8, fabric_adc0_usr_sample_o9, fabric_adc0_usr_sample_o10, fabric_adc0_usr_sample_o11 -, fabric_adc0_usr_sample_o12, fabric_adc0_usr_sample_lsb_i1, fabric_adc0_usr_sample_lsb_i2, fabric_adc0_usr_sample_lsb_i3, fabric_adc0_usr_sample_lsb_i4, fabric_adc0_dbg_addr_i1, fabric_adc0_dbg_addr_i2, fabric_adc0_dbg_addr_i3, fabric_adc0_dbg_addr_i4, fabric_adc0_dbg_data_o1, fabric_adc0_dbg_data_o2, fabric_adc0_dbg_data_o3, fabric_adc0_dbg_data_o4, fabric_adc0_dbg_data_o5, fabric_adc0_dbg_data_o6, fabric_adc0_dbg_data_o7, fabric_adc0_dbg_data_o8, fabric_adc0_dbg_data_o9, fabric_adc0_dbg_data_o10, fabric_adc0_dbg_data_o11, fabric_adc0_dbg_data_o12 -, fabric_adc0_dbg_data_o13, fabric_adc0_dbg_data_o14, fabric_adc0_dbg_data_o15, fabric_adc0_dbg_data_o16, fabric_adc0_dbg_data_o17, fabric_adc0_dbg_data_o18, fabric_adc0_dbg_data_o19, fabric_adc0_dbg_data_o20, fabric_adc0_dbg_data_o21, fabric_adc0_dbg_data_o22, fabric_adc0_dbg_data_o23, fabric_adc0_dbg_data_o24, fabric_adc0_dbg_data_o25, fabric_adc0_dbg_data_o26, fabric_adc0_dbg_data_o27, fabric_adc0_dbg_data_o28, fabric_adc0_dbg_data_o29, fabric_adc0_dbg_data_o30, fabric_adc0_dbg_data_o31, fabric_adc0_dbg_data_o32, fabric_cfg_adc0_clk_cal_div_ratio_i1 -, fabric_cfg_adc0_clk_cal_div_ratio_i2, fabric_cfg_adc0_clk_cal_div_ratio_i3, fabric_cfg_adc0_clk_cal_div_ratio_i4, fabric_cfg_adc0_clk_cal_div_ratio_i5, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_arst_b_tmr_i1, fabric_adc1_arst_b_tmr_i2, fabric_adc1_arst_b_tmr_i3, fabric_adc1_pwr_down_b_tmr_i1, fabric_adc1_pwr_down_b_tmr_i2, fabric_adc1_pwr_down_b_tmr_i3, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_spare_i1, fabric_adc1_spare_i2 -, fabric_adc1_spare_i3, fabric_adc1_spare_i4, fabric_adc1_spare_i5, fabric_adc1_spare_i6, fabric_adc1_spare_i7, fabric_adc1_spare_i8, fabric_adc1_spare_i9, fabric_adc1_spare_i10, fabric_adc1_spare_i11, fabric_adc1_spare_i12, fabric_adc1_spare_i13, fabric_adc1_spare_i14, fabric_adc1_spare_i15, fabric_adc1_spare_i16, fabric_adc1_dft_test_mode_i1, fabric_adc1_dft_test_mode_i2, fabric_adc1_dft_scan_en_i, fabric_adc1_dft_si_i1, fabric_adc1_dft_si_i2, fabric_adc1_dft_si_i3, fabric_adc1_dft_si_i4 -, fabric_adc1_dft_si_i5, fabric_adc1_dft_si_i6, fabric_adc1_dft_si_i7, fabric_adc1_dft_si_i8, fabric_adc1_dft_si_i9, fabric_adc1_dft_si_i10, fabric_adc1_dft_si_i11, fabric_adc1_dft_si_i12, fabric_adc1_usr_cke_i, fabric_adc1_usr_arst_b_tmr_i1, fabric_adc1_usr_arst_b_tmr_i2, fabric_adc1_usr_arst_b_tmr_i3, fabric_adc1_usr_channel_i1, fabric_adc1_usr_channel_i2, fabric_adc1_usr_channel_i3, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_adc1_usr_sample_o1, fabric_adc1_usr_sample_o2, fabric_adc1_usr_sample_o3, fabric_adc1_usr_sample_o4 -, fabric_adc1_usr_sample_o5, fabric_adc1_usr_sample_o6, fabric_adc1_usr_sample_o7, fabric_adc1_usr_sample_o8, fabric_adc1_usr_sample_o9, fabric_adc1_usr_sample_o10, fabric_adc1_usr_sample_o11, fabric_adc1_usr_sample_o12, fabric_adc1_usr_sample_lsb_i1, fabric_adc1_usr_sample_lsb_i2, fabric_adc1_usr_sample_lsb_i3, fabric_adc1_usr_sample_lsb_i4, fabric_adc1_dbg_addr_i1, fabric_adc1_dbg_addr_i2, fabric_adc1_dbg_addr_i3, fabric_adc1_dbg_addr_i4, fabric_adc1_dbg_data_o1, fabric_adc1_dbg_data_o2, fabric_adc1_dbg_data_o3, fabric_adc1_dbg_data_o4, fabric_adc1_dbg_data_o5 -, fabric_adc1_dbg_data_o6, fabric_adc1_dbg_data_o7, fabric_adc1_dbg_data_o8, fabric_adc1_dbg_data_o9, fabric_adc1_dbg_data_o10, fabric_adc1_dbg_data_o11, fabric_adc1_dbg_data_o12, fabric_adc1_dbg_data_o13, fabric_adc1_dbg_data_o14, fabric_adc1_dbg_data_o15, fabric_adc1_dbg_data_o16, fabric_adc1_dbg_data_o17, fabric_adc1_dbg_data_o18, fabric_adc1_dbg_data_o19, fabric_adc1_dbg_data_o20, fabric_adc1_dbg_data_o21, fabric_adc1_dbg_data_o22, fabric_adc1_dbg_data_o23, fabric_adc1_dbg_data_o24, fabric_adc1_dbg_data_o25, fabric_adc1_dbg_data_o26 -, fabric_adc1_dbg_data_o27, fabric_adc1_dbg_data_o28, fabric_adc1_dbg_data_o29, fabric_adc1_dbg_data_o30, fabric_adc1_dbg_data_o31, fabric_adc1_dbg_data_o32, fabric_cfg_adc1_clk_cal_div_ratio_i1, fabric_cfg_adc1_clk_cal_div_ratio_i2, fabric_cfg_adc1_clk_cal_div_ratio_i3, fabric_cfg_adc1_clk_cal_div_ratio_i4, fabric_cfg_adc1_clk_cal_div_ratio_i5, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i, fabric_adc2_clk_i, fabric_adc2_arst_b_tmr_i1, fabric_adc2_arst_b_tmr_i2, fabric_adc2_arst_b_tmr_i3, fabric_adc2_pwr_down_b_tmr_i1, fabric_adc2_pwr_down_b_tmr_i2, fabric_adc2_pwr_down_b_tmr_i3, fabric_adc2_cal_start_i -, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_spare_i1, fabric_adc2_spare_i2, fabric_adc2_spare_i3, fabric_adc2_spare_i4, fabric_adc2_spare_i5, fabric_adc2_spare_i6, fabric_adc2_spare_i7, fabric_adc2_spare_i8, fabric_adc2_spare_i9, fabric_adc2_spare_i10, fabric_adc2_spare_i11, fabric_adc2_spare_i12, fabric_adc2_spare_i13, fabric_adc2_spare_i14, fabric_adc2_spare_i15, fabric_adc2_spare_i16 -, fabric_adc2_dft_test_mode_i1, fabric_adc2_dft_test_mode_i2, fabric_adc2_dft_scan_en_i, fabric_adc2_dft_si_i1, fabric_adc2_dft_si_i2, fabric_adc2_dft_si_i3, fabric_adc2_dft_si_i4, fabric_adc2_dft_si_i5, fabric_adc2_dft_si_i6, fabric_adc2_dft_si_i7, fabric_adc2_dft_si_i8, fabric_adc2_dft_si_i9, fabric_adc2_dft_si_i10, fabric_adc2_dft_si_i11, fabric_adc2_dft_si_i12, fabric_adc2_usr_cke_i, fabric_adc2_usr_arst_b_tmr_i1, fabric_adc2_usr_arst_b_tmr_i2, fabric_adc2_usr_arst_b_tmr_i3, fabric_adc2_usr_channel_i1, fabric_adc2_usr_channel_i2 -, fabric_adc2_usr_channel_i3, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_adc2_usr_sample_o1, fabric_adc2_usr_sample_o2, fabric_adc2_usr_sample_o3, fabric_adc2_usr_sample_o4, fabric_adc2_usr_sample_o5, fabric_adc2_usr_sample_o6, fabric_adc2_usr_sample_o7, fabric_adc2_usr_sample_o8, fabric_adc2_usr_sample_o9, fabric_adc2_usr_sample_o10, fabric_adc2_usr_sample_o11, fabric_adc2_usr_sample_o12, fabric_adc2_usr_sample_lsb_i1, fabric_adc2_usr_sample_lsb_i2, fabric_adc2_usr_sample_lsb_i3, fabric_adc2_usr_sample_lsb_i4, fabric_adc2_dbg_addr_i1, fabric_adc2_dbg_addr_i2 -, fabric_adc2_dbg_addr_i3, fabric_adc2_dbg_addr_i4, fabric_adc2_dbg_data_o1, fabric_adc2_dbg_data_o2, fabric_adc2_dbg_data_o3, fabric_adc2_dbg_data_o4, fabric_adc2_dbg_data_o5, fabric_adc2_dbg_data_o6, fabric_adc2_dbg_data_o7, fabric_adc2_dbg_data_o8, fabric_adc2_dbg_data_o9, fabric_adc2_dbg_data_o10, fabric_adc2_dbg_data_o11, fabric_adc2_dbg_data_o12, fabric_adc2_dbg_data_o13, fabric_adc2_dbg_data_o14, fabric_adc2_dbg_data_o15, fabric_adc2_dbg_data_o16, fabric_adc2_dbg_data_o17, fabric_adc2_dbg_data_o18, fabric_adc2_dbg_data_o19 -, fabric_adc2_dbg_data_o20, fabric_adc2_dbg_data_o21, fabric_adc2_dbg_data_o22, fabric_adc2_dbg_data_o23, fabric_adc2_dbg_data_o24, fabric_adc2_dbg_data_o25, fabric_adc2_dbg_data_o26, fabric_adc2_dbg_data_o27, fabric_adc2_dbg_data_o28, fabric_adc2_dbg_data_o29, fabric_adc2_dbg_data_o30, fabric_adc2_dbg_data_o31, fabric_adc2_dbg_data_o32, fabric_cfg_adc2_clk_cal_div_ratio_i1, fabric_cfg_adc2_clk_cal_div_ratio_i2, fabric_cfg_adc2_clk_cal_div_ratio_i3, fabric_cfg_adc2_clk_cal_div_ratio_i4, fabric_cfg_adc2_clk_cal_div_ratio_i5, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i -, fabric_adc3_arst_b_tmr_i1, fabric_adc3_arst_b_tmr_i2, fabric_adc3_arst_b_tmr_i3, fabric_adc3_pwr_down_b_tmr_i1, fabric_adc3_pwr_down_b_tmr_i2, fabric_adc3_pwr_down_b_tmr_i3, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_spare_i1, fabric_adc3_spare_i2, fabric_adc3_spare_i3, fabric_adc3_spare_i4, fabric_adc3_spare_i5, fabric_adc3_spare_i6, fabric_adc3_spare_i7, fabric_adc3_spare_i8, fabric_adc3_spare_i9 -, fabric_adc3_spare_i10, fabric_adc3_spare_i11, fabric_adc3_spare_i12, fabric_adc3_spare_i13, fabric_adc3_spare_i14, fabric_adc3_spare_i15, fabric_adc3_spare_i16, fabric_adc3_dft_test_mode_i1, fabric_adc3_dft_test_mode_i2, fabric_adc3_dft_scan_en_i, fabric_adc3_dft_si_i1, fabric_adc3_dft_si_i2, fabric_adc3_dft_si_i3, fabric_adc3_dft_si_i4, fabric_adc3_dft_si_i5, fabric_adc3_dft_si_i6, fabric_adc3_dft_si_i7, fabric_adc3_dft_si_i8, fabric_adc3_dft_si_i9, fabric_adc3_dft_si_i10, fabric_adc3_dft_si_i11 -, fabric_adc3_dft_si_i12, fabric_adc3_usr_cke_i, fabric_adc3_usr_arst_b_tmr_i1, fabric_adc3_usr_arst_b_tmr_i2, fabric_adc3_usr_arst_b_tmr_i3, fabric_adc3_usr_channel_i1, fabric_adc3_usr_channel_i2, fabric_adc3_usr_channel_i3, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_adc3_usr_sample_o1, fabric_adc3_usr_sample_o2, fabric_adc3_usr_sample_o3, fabric_adc3_usr_sample_o4, fabric_adc3_usr_sample_o5, fabric_adc3_usr_sample_o6, fabric_adc3_usr_sample_o7, fabric_adc3_usr_sample_o8, fabric_adc3_usr_sample_o9, fabric_adc3_usr_sample_o10, fabric_adc3_usr_sample_o11 -, fabric_adc3_usr_sample_o12, fabric_adc3_usr_sample_lsb_i1, fabric_adc3_usr_sample_lsb_i2, fabric_adc3_usr_sample_lsb_i3, fabric_adc3_usr_sample_lsb_i4, fabric_adc3_dbg_addr_i1, fabric_adc3_dbg_addr_i2, fabric_adc3_dbg_addr_i3, fabric_adc3_dbg_addr_i4, fabric_adc3_dbg_data_o1, fabric_adc3_dbg_data_o2, fabric_adc3_dbg_data_o3, fabric_adc3_dbg_data_o4, fabric_adc3_dbg_data_o5, fabric_adc3_dbg_data_o6, fabric_adc3_dbg_data_o7, fabric_adc3_dbg_data_o8, fabric_adc3_dbg_data_o9, fabric_adc3_dbg_data_o10, fabric_adc3_dbg_data_o11, fabric_adc3_dbg_data_o12 -, fabric_adc3_dbg_data_o13, fabric_adc3_dbg_data_o14, fabric_adc3_dbg_data_o15, fabric_adc3_dbg_data_o16, fabric_adc3_dbg_data_o17, fabric_adc3_dbg_data_o18, fabric_adc3_dbg_data_o19, fabric_adc3_dbg_data_o20, fabric_adc3_dbg_data_o21, fabric_adc3_dbg_data_o22, fabric_adc3_dbg_data_o23, fabric_adc3_dbg_data_o24, fabric_adc3_dbg_data_o25, fabric_adc3_dbg_data_o26, fabric_adc3_dbg_data_o27, fabric_adc3_dbg_data_o28, fabric_adc3_dbg_data_o29, fabric_adc3_dbg_data_o30, fabric_adc3_dbg_data_o31, fabric_adc3_dbg_data_o32, fabric_cfg_adc3_clk_cal_div_ratio_i1 -, fabric_cfg_adc3_clk_cal_div_ratio_i2, fabric_cfg_adc3_clk_cal_div_ratio_i3, fabric_cfg_adc3_clk_cal_div_ratio_i4, fabric_cfg_adc3_clk_cal_div_ratio_i5, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_clock_fabric_i1, fabric_direct0_clock_fabric_i2, fabric_direct0_clock_fabric_i3, fabric_direct0_clock_fabric_i4, fabric_direct0_oe_i1, fabric_direct0_oe_i2, fabric_direct0_oe_i3, fabric_direct0_oe_i4, fabric_direct0_oe_i5, fabric_direct0_oe_i6, fabric_direct0_oe_i7, fabric_direct0_oe_i8, fabric_direct0_oe_i9, fabric_direct0_oe_i10, fabric_direct0_oe_i11 -, fabric_direct0_oe_i12, fabric_direct0_oe_i13, fabric_direct0_oe_i14, fabric_direct0_oe_i15, fabric_direct0_oe_i16, fabric_direct0_oe_i17, fabric_direct0_oe_i18, fabric_direct0_oe_i19, fabric_direct0_oe_i20, fabric_direct0_oe_i21, fabric_direct0_oe_i22, fabric_direct0_oe_i23, fabric_direct0_oe_i24, fabric_direct0_oe_ena_i1, fabric_direct0_oe_ena_i2, fabric_direct0_oe_ena_i3, fabric_direct0_oe_ena_i4, fabric_direct0_oe_ena_i5, fabric_direct0_oe_ena_i6, fabric_direct0_oe_ena_i7, fabric_direct0_oe_ena_i8 -, fabric_direct0_oe_ena_i9, fabric_direct0_oe_ena_i10, fabric_direct0_oe_ena_i11, fabric_direct0_oe_ena_i12, fabric_direct0_oe_ena_i13, fabric_direct0_oe_ena_i14, fabric_direct0_oe_ena_i15, fabric_direct0_oe_ena_i16, fabric_direct0_oe_ena_i17, fabric_direct0_oe_ena_i18, fabric_direct0_oe_ena_i19, fabric_direct0_oe_ena_i20, fabric_direct0_oe_ena_i21, fabric_direct0_oe_ena_i22, fabric_direct0_oe_ena_i23, fabric_direct0_oe_ena_i24, fabric_direct0_oe_rs_i1, fabric_direct0_oe_rs_i2, fabric_direct0_oe_rs_i3, fabric_direct0_oe_rs_i4, fabric_direct0_oe_rs_i5 -, fabric_direct0_oe_rs_i6, fabric_direct0_oe_rs_i7, fabric_direct0_oe_rs_i8, fabric_direct0_oe_rs_i9, fabric_direct0_oe_rs_i10, fabric_direct0_oe_rs_i11, fabric_direct0_oe_rs_i12, fabric_direct0_oe_rs_i13, fabric_direct0_oe_rs_i14, fabric_direct0_oe_rs_i15, fabric_direct0_oe_rs_i16, fabric_direct0_oe_rs_i17, fabric_direct0_oe_rs_i18, fabric_direct0_oe_rs_i19, fabric_direct0_oe_rs_i20, fabric_direct0_oe_rs_i21, fabric_direct0_oe_rs_i22, fabric_direct0_oe_rs_i23, fabric_direct0_oe_rs_i24, fabric_direct0_do_i1, fabric_direct0_do_i2 -, fabric_direct0_do_i3, fabric_direct0_do_i4, fabric_direct0_do_i5, fabric_direct0_do_i6, fabric_direct0_do_i7, fabric_direct0_do_i8, fabric_direct0_do_i9, fabric_direct0_do_i10, fabric_direct0_do_i11, fabric_direct0_do_i12, fabric_direct0_do_i13, fabric_direct0_do_i14, fabric_direct0_do_i15, fabric_direct0_do_i16, fabric_direct0_do_i17, fabric_direct0_do_i18, fabric_direct0_do_i19, fabric_direct0_do_i20, fabric_direct0_do_i21, fabric_direct0_do_i22, fabric_direct0_do_i23 -, fabric_direct0_do_i24, fabric_direct0_do_ena_i1, fabric_direct0_do_ena_i2, fabric_direct0_do_ena_i3, fabric_direct0_do_ena_i4, fabric_direct0_do_ena_i5, fabric_direct0_do_ena_i6, fabric_direct0_do_ena_i7, fabric_direct0_do_ena_i8, fabric_direct0_do_ena_i9, fabric_direct0_do_ena_i10, fabric_direct0_do_ena_i11, fabric_direct0_do_ena_i12, fabric_direct0_do_ena_i13, fabric_direct0_do_ena_i14, fabric_direct0_do_ena_i15, fabric_direct0_do_ena_i16, fabric_direct0_do_ena_i17, fabric_direct0_do_ena_i18, fabric_direct0_do_ena_i19, fabric_direct0_do_ena_i20 -, fabric_direct0_do_ena_i21, fabric_direct0_do_ena_i22, fabric_direct0_do_ena_i23, fabric_direct0_do_ena_i24, fabric_direct0_do_rs_i1, fabric_direct0_do_rs_i2, fabric_direct0_do_rs_i3, fabric_direct0_do_rs_i4, fabric_direct0_do_rs_i5, fabric_direct0_do_rs_i6, fabric_direct0_do_rs_i7, fabric_direct0_do_rs_i8, fabric_direct0_do_rs_i9, fabric_direct0_do_rs_i10, fabric_direct0_do_rs_i11, fabric_direct0_do_rs_i12, fabric_direct0_do_rs_i13, fabric_direct0_do_rs_i14, fabric_direct0_do_rs_i15, fabric_direct0_do_rs_i16, fabric_direct0_do_rs_i17 -, fabric_direct0_do_rs_i18, fabric_direct0_do_rs_i19, fabric_direct0_do_rs_i20, fabric_direct0_do_rs_i21, fabric_direct0_do_rs_i22, fabric_direct0_do_rs_i23, fabric_direct0_do_rs_i24, fabric_direct0_di_o1, fabric_direct0_di_o2, fabric_direct0_di_o3, fabric_direct0_di_o4, fabric_direct0_di_o5, fabric_direct0_di_o6, fabric_direct0_di_o7, fabric_direct0_di_o8, fabric_direct0_di_o9, fabric_direct0_di_o10, fabric_direct0_di_o11, fabric_direct0_di_o12, fabric_direct0_di_o13, fabric_direct0_di_o14 -, fabric_direct0_di_o15, fabric_direct0_di_o16, fabric_direct0_di_o17, fabric_direct0_di_o18, fabric_direct0_di_o19, fabric_direct0_di_o20, fabric_direct0_di_o21, fabric_direct0_di_o22, fabric_direct0_di_o23, fabric_direct0_di_o24, fabric_direct0_di_ena_i1, fabric_direct0_di_ena_i2, fabric_direct0_di_ena_i3, fabric_direct0_di_ena_i4, fabric_direct0_di_ena_i5, fabric_direct0_di_ena_i6, fabric_direct0_di_ena_i7, fabric_direct0_di_ena_i8, fabric_direct0_di_ena_i9, fabric_direct0_di_ena_i10, fabric_direct0_di_ena_i11 -, fabric_direct0_di_ena_i12, fabric_direct0_di_ena_i13, fabric_direct0_di_ena_i14, fabric_direct0_di_ena_i15, fabric_direct0_di_ena_i16, fabric_direct0_di_ena_i17, fabric_direct0_di_ena_i18, fabric_direct0_di_ena_i19, fabric_direct0_di_ena_i20, fabric_direct0_di_ena_i21, fabric_direct0_di_ena_i22, fabric_direct0_di_ena_i23, fabric_direct0_di_ena_i24, fabric_direct0_di_rs_i1, fabric_direct0_di_rs_i2, fabric_direct0_di_rs_i3, fabric_direct0_di_rs_i4, fabric_direct0_di_rs_i5, fabric_direct0_di_rs_i6, fabric_direct0_di_rs_i7, fabric_direct0_di_rs_i8 -, fabric_direct0_di_rs_i9, fabric_direct0_di_rs_i10, fabric_direct0_di_rs_i11, fabric_direct0_di_rs_i12, fabric_direct0_di_rs_i13, fabric_direct0_di_rs_i14, fabric_direct0_di_rs_i15, fabric_direct0_di_rs_i16, fabric_direct0_di_rs_i17, fabric_direct0_di_rs_i18, fabric_direct0_di_rs_i19, fabric_direct0_di_rs_i20, fabric_direct0_di_rs_i21, fabric_direct0_di_rs_i22, fabric_direct0_di_rs_i23, fabric_direct0_di_rs_i24, fabric_direct0_cfg_bank_i1, fabric_direct0_cfg_bank_i2, fabric_direct0_cfg_bank_i3, fabric_direct0_cfg_bank_i4, fabric_direct0_cfg_pad_i1 -, fabric_direct0_cfg_pad_i2, fabric_direct0_cfg_pad_i3, fabric_direct0_cfg_pad_i4, fabric_direct0_cfg_pad_i5, fabric_direct0_cfg_pad_i6, fabric_direct0_cfg_pad_i7, fabric_direct0_cfg_pad_i8, fabric_direct0_cfg_pad_i9, fabric_direct0_cfg_pad_i10, fabric_direct0_cfg_pad_i11, fabric_direct0_cfg_pad_i12, fabric_direct0_cfg_pad_i13, fabric_direct0_cfg_pad_i14, fabric_direct0_cfg_pad_i15, fabric_direct0_cfg_pad_i16, fabric_direct0_cfg_pad_i17, fabric_direct0_cfg_pad_i18, fabric_direct0_cfg_pad_i19, fabric_direct0_cfg_pad_i20, fabric_direct0_cfg_pad_i21, fabric_direct0_cfg_pad_i22 -, fabric_direct0_cfg_pad_i23, fabric_direct0_cfg_pad_i24, fabric_direct0_cfg_pad_i25, fabric_direct0_cfg_pad_i26, fabric_direct0_cfg_pad_i27, fabric_direct0_cfg_pad_i28, fabric_direct0_cfg_pad_i29, fabric_direct0_cfg_pad_i30, fabric_direct0_cfg_pad_i31, fabric_direct0_cfg_pad_i32, fabric_direct0_cfg_pad_i33, fabric_direct0_cfg_pad_i34, fabric_direct0_cfg_pad_i35, fabric_direct0_cfg_pad_i36, fabric_direct0_cfg_pad_i37, fabric_direct0_cfg_pad_i38, fabric_direct0_cfg_pad_i39, fabric_direct0_cfg_pad_i40, fabric_direct0_cfg_pad_i41, fabric_direct0_cfg_pad_i42, fabric_direct0_cfg_pad_i43 -, fabric_direct0_cfg_pad_i44, fabric_direct0_cfg_pad_i45, fabric_direct0_cfg_pad_i46, fabric_direct0_cfg_pad_i47, fabric_direct0_cfg_pad_i48, fabric_direct0_cfg_pad_i49, fabric_direct0_cfg_pad_i50, fabric_direct0_cfg_pad_i51, fabric_direct0_cfg_pad_i52, fabric_direct0_cfg_pad_i53, fabric_direct0_cfg_pad_i54, fabric_direct0_cfg_pad_i55, fabric_direct0_cfg_pad_i56, fabric_direct0_cfg_pad_i57, fabric_direct0_cfg_pad_i58, fabric_direct0_cfg_pad_i59, fabric_direct0_cfg_pad_i60, fabric_direct0_cfg_pad_i61, fabric_direct0_cfg_pad_i62, fabric_direct0_cfg_pad_i63, fabric_direct0_cfg_pad_i64 -, fabric_direct0_cfg_pad_i65, fabric_direct0_cfg_pad_i66, fabric_direct0_cfg_pad_i67, fabric_direct0_cfg_pad_i68, fabric_direct0_cfg_pad_i69, fabric_direct0_cfg_pad_i70, fabric_direct0_cfg_pad_i71, fabric_direct0_cfg_pad_i72, fabric_direct0_cfg_pad_i73, fabric_direct0_cfg_pad_i74, fabric_direct0_cfg_pad_i75, fabric_direct0_cfg_pad_i76, fabric_direct0_cfg_pad_i77, fabric_direct0_cfg_pad_i78, fabric_direct0_cfg_pad_i79, fabric_direct0_cfg_pad_i80, fabric_direct0_cfg_pad_i81, fabric_direct0_cfg_pad_i82, fabric_direct0_cfg_pad_i83, fabric_direct0_cfg_pad_i84, fabric_direct0_cfg_pad_i85 -, fabric_direct0_cfg_pad_i86, fabric_direct0_cfg_pad_i87, fabric_direct0_cfg_pad_i88, fabric_direct0_cfg_pad_i89, fabric_direct0_cfg_pad_i90, fabric_direct0_cfg_pad_i91, fabric_direct0_cfg_pad_i92, fabric_direct0_cfg_pad_i93, fabric_direct0_cfg_pad_i94, fabric_direct0_cfg_pad_i95, fabric_direct0_cfg_pad_i96, fabric_direct0_cfg_pad_i97, fabric_direct0_cfg_pad_i98, fabric_direct0_cfg_pad_i99, fabric_direct0_cfg_pad_i100, fabric_direct0_cfg_pad_i101, fabric_direct0_cfg_pad_i102, fabric_direct0_cfg_pad_i103, fabric_direct0_cfg_pad_i104, fabric_direct0_cfg_pad_i105, fabric_direct0_cfg_pad_i106 -, fabric_direct0_cfg_pad_i107, fabric_direct0_cfg_pad_i108, fabric_direct0_cfg_pad_i109, fabric_direct0_cfg_pad_i110, fabric_direct0_cfg_pad_i111, fabric_direct0_cfg_pad_i112, fabric_direct0_cfg_pad_i113, fabric_direct0_cfg_pad_i114, fabric_direct0_cfg_pad_i115, fabric_direct0_cfg_pad_i116, fabric_direct0_cfg_pad_i117, fabric_direct0_cfg_pad_i118, fabric_direct0_cfg_pad_i119, fabric_direct0_cfg_pad_i120, fabric_direct0_cfg_pad_i121, fabric_direct0_cfg_pad_i122, fabric_direct0_cfg_pad_i123, fabric_direct0_cfg_pad_i124, fabric_direct0_cfg_pad_i125, fabric_direct0_cfg_pad_i126, fabric_direct0_cfg_pad_i127 -, fabric_direct0_cfg_pad_i128, fabric_direct0_cfg_pad_i129, fabric_direct0_cfg_pad_i130, fabric_direct0_cfg_pad_i131, fabric_direct0_cfg_pad_i132, fabric_direct0_cfg_pad_i133, fabric_direct0_cfg_pad_i134, fabric_direct0_cfg_pad_i135, fabric_direct0_cfg_pad_i136, fabric_direct0_cfg_pad_i137, fabric_direct0_cfg_pad_i138, fabric_direct0_cfg_pad_i139, fabric_direct0_cfg_pad_i140, fabric_direct0_cfg_pad_i141, fabric_direct0_cfg_pad_i142, fabric_direct0_cfg_pad_i143, fabric_direct0_cfg_pad_i144, fabric_direct0_cfg_pad_i145, fabric_direct0_cfg_pad_i146, fabric_direct0_cfg_pad_i147, fabric_direct0_cfg_pad_i148 -, fabric_direct0_cfg_pad_i149, fabric_direct0_cfg_pad_i150, fabric_direct0_cfg_pad_i151, fabric_direct0_cfg_pad_i152, fabric_direct0_cfg_pad_i153, fabric_direct0_cfg_pad_i154, fabric_direct0_cfg_pad_i155, fabric_direct0_cfg_pad_i156, fabric_direct0_cfg_pad_i157, fabric_direct0_cfg_pad_i158, fabric_direct0_cfg_pad_i159, fabric_direct0_cfg_pad_i160, fabric_direct0_cfg_pad_i161, fabric_direct0_cfg_pad_i162, fabric_direct0_cfg_pad_i163, fabric_direct0_cfg_pad_i164, fabric_direct0_cfg_pad_i165, fabric_direct0_cfg_pad_i166, fabric_direct0_cfg_pad_i167, fabric_direct0_cfg_pad_i168, fabric_direct0_cfg_pad_i169 -, fabric_direct0_cfg_pad_i170, fabric_direct0_cfg_pad_i171, fabric_direct0_cfg_pad_i172, fabric_direct0_cfg_pad_i173, fabric_direct0_cfg_pad_i174, fabric_direct0_cfg_pad_i175, fabric_direct0_cfg_pad_i176, fabric_direct0_cfg_pad_i177, fabric_direct0_cfg_pad_i178, fabric_direct0_cfg_pad_i179, fabric_direct0_cfg_pad_i180, fabric_direct0_cfg_pad_i181, fabric_direct0_cfg_pad_i182, fabric_direct0_cfg_pad_i183, fabric_direct0_cfg_pad_i184, fabric_direct0_cfg_pad_i185, fabric_direct0_cfg_pad_i186, fabric_direct0_cfg_pad_i187, fabric_direct0_cfg_pad_i188, fabric_direct0_cfg_pad_i189, fabric_direct0_cfg_pad_i190 -, fabric_direct0_cfg_pad_i191, fabric_direct0_cfg_pad_i192, fabric_direct0_cfg_pad_i193, fabric_direct0_cfg_pad_i194, fabric_direct0_cfg_pad_i195, fabric_direct0_cfg_pad_i196, fabric_direct0_cfg_pad_i197, fabric_direct0_cfg_pad_i198, fabric_direct0_cfg_pad_i199, fabric_direct0_cfg_pad_i200, fabric_direct0_cfg_pad_i201, fabric_direct0_cfg_pad_i202, fabric_direct0_cfg_pad_i203, fabric_direct0_cfg_pad_i204, fabric_direct0_cfg_pad_i205, fabric_direct0_cfg_pad_i206, fabric_direct0_cfg_pad_i207, fabric_direct0_cfg_pad_i208, fabric_direct0_cfg_pad_i209, fabric_direct0_cfg_pad_i210, fabric_direct0_cfg_pad_i211 -, fabric_direct0_cfg_pad_i212, fabric_direct0_cfg_pad_i213, fabric_direct0_cfg_pad_i214, fabric_direct0_cfg_pad_i215, fabric_direct0_cfg_pad_i216, fabric_direct0_cfg_pad_i217, fabric_direct0_cfg_pad_i218, fabric_direct0_cfg_pad_i219, fabric_direct0_cfg_pad_i220, fabric_direct0_cfg_pad_i221, fabric_direct0_cfg_pad_i222, fabric_direct0_cfg_pad_i223, fabric_direct0_cfg_pad_i224, fabric_direct0_cfg_pad_i225, fabric_direct0_cfg_pad_i226, fabric_direct0_cfg_pad_i227, fabric_direct0_cfg_pad_i228, fabric_direct0_cfg_pad_i229, fabric_direct0_cfg_pad_i230, fabric_direct0_cfg_pad_i231, fabric_direct0_cfg_pad_i232 -, fabric_direct0_cfg_pad_i233, fabric_direct0_cfg_pad_i234, fabric_direct0_cfg_pad_i235, fabric_direct0_cfg_pad_i236, fabric_direct0_cfg_pad_i237, fabric_direct0_cfg_pad_i238, fabric_direct0_cfg_pad_i239, fabric_direct0_cfg_pad_i240, fabric_direct0_cfg_pad_i241, fabric_direct0_cfg_pad_i242, fabric_direct0_cfg_pad_i243, fabric_direct0_cfg_pad_i244, fabric_direct0_cfg_pad_i245, fabric_direct0_cfg_pad_i246, fabric_direct0_cfg_pad_i247, fabric_direct0_cfg_pad_i248, fabric_direct0_cfg_pad_i249, fabric_direct0_cfg_pad_i250, fabric_direct0_cfg_pad_i251, fabric_direct0_cfg_pad_i252, fabric_direct0_cfg_pad_i253 -, fabric_direct0_cfg_pad_i254, fabric_direct0_cfg_pad_i255, fabric_direct0_cfg_pad_i256, fabric_direct0_cfg_pad_i257, fabric_direct0_cfg_pad_i258, fabric_direct0_cfg_pad_i259, fabric_direct0_cfg_pad_i260, fabric_direct0_cfg_pad_i261, fabric_direct0_cfg_pad_i262, fabric_direct0_cfg_pad_i263, fabric_direct0_cfg_pad_i264, fabric_direct0_cfg_pad_i265, fabric_direct0_cfg_pad_i266, fabric_direct0_cfg_pad_i267, fabric_direct0_cfg_pad_i268, fabric_direct0_cfg_pad_i269, fabric_direct0_cfg_pad_i270, fabric_direct0_cfg_pad_i271, fabric_direct0_cfg_pad_i272, fabric_direct0_cfg_pad_i273, fabric_direct0_cfg_pad_i274 -, fabric_direct0_cfg_pad_i275, fabric_direct0_cfg_pad_i276, fabric_direct0_cfg_pad_i277, fabric_direct0_cfg_pad_i278, fabric_direct0_cfg_pad_i279, fabric_direct0_cfg_pad_i280, fabric_direct0_cfg_pad_i281, fabric_direct0_cfg_pad_i282, fabric_direct0_cfg_pad_i283, fabric_direct0_cfg_pad_i284, fabric_direct0_cfg_pad_i285, fabric_direct0_cfg_pad_i286, fabric_direct0_cfg_pad_i287, fabric_direct0_cfg_pad_i288, fabric_direct0_cfg_pad_i289, fabric_direct0_cfg_pad_i290, fabric_direct0_cfg_pad_i291, fabric_direct0_cfg_pad_i292, fabric_direct0_cfg_pad_i293, fabric_direct0_cfg_pad_i294, fabric_direct0_cfg_pad_i295 -, fabric_direct0_cfg_pad_i296, fabric_direct0_cfg_pad_i297, fabric_direct0_cfg_pad_i298, fabric_direct0_cfg_pad_i299, fabric_direct0_cfg_pad_i300, fabric_direct0_cfg_pad_i301, fabric_direct0_cfg_pad_i302, fabric_direct0_cfg_pad_i303, fabric_direct0_cfg_pad_i304, fabric_direct0_cfg_pad_i305, fabric_direct0_cfg_pad_i306, fabric_direct0_cfg_pad_i307, fabric_direct0_cfg_pad_i308, fabric_direct0_cfg_pad_i309, fabric_direct0_cfg_pad_i310, fabric_direct0_cfg_pad_i311, fabric_direct0_cfg_pad_i312, fabric_direct0_cfg_pad_i313, fabric_direct0_cfg_pad_i314, fabric_direct0_cfg_pad_i315, fabric_direct0_cfg_pad_i316 -, fabric_direct0_cfg_pad_i317, fabric_direct0_cfg_pad_i318, fabric_direct0_cfg_pad_i319, fabric_direct0_cfg_pad_i320, fabric_direct0_cfg_pad_i321, fabric_direct0_cfg_pad_i322, fabric_direct0_cfg_pad_i323, fabric_direct0_cfg_pad_i324, fabric_direct0_cfg_pad_i325, fabric_direct0_cfg_pad_i326, fabric_direct0_cfg_pad_i327, fabric_direct0_cfg_pad_i328, fabric_direct0_cfg_pad_i329, fabric_direct0_cfg_pad_i330, fabric_direct0_cfg_pad_i331, fabric_direct0_cfg_pad_i332, fabric_direct0_cfg_pad_i333, fabric_direct0_cfg_pad_i334, fabric_direct0_cfg_pad_i335, fabric_direct0_cfg_pad_i336, fabric_direct0_cfg_pad_i337 -, fabric_direct0_cfg_pad_i338, fabric_direct0_cfg_pad_i339, fabric_direct0_cfg_pad_i340, fabric_direct0_cfg_pad_i341, fabric_direct0_cfg_pad_i342, fabric_direct0_cfg_pad_i343, fabric_direct0_cfg_pad_i344, fabric_direct0_cfg_pad_i345, fabric_direct0_cfg_pad_i346, fabric_direct0_cfg_pad_i347, fabric_direct0_cfg_pad_i348, fabric_direct0_cfg_pad_i349, fabric_direct0_cfg_pad_i350, fabric_direct0_cfg_pad_i351, fabric_direct0_cfg_pad_i352, fabric_direct0_cfg_pad_i353, fabric_direct0_cfg_pad_i354, fabric_direct0_cfg_pad_i355, fabric_direct0_cfg_pad_i356, fabric_direct0_cfg_pad_i357, fabric_direct0_cfg_pad_i358 -, fabric_direct0_cfg_pad_i359, fabric_direct0_cfg_pad_i360, fabric_direct0_cfg_pad_i361, fabric_direct0_cfg_pad_i362, fabric_direct0_cfg_pad_i363, fabric_direct0_cfg_pad_i364, fabric_direct0_cfg_pad_i365, fabric_direct0_cfg_pad_i366, fabric_direct0_cfg_pad_i367, fabric_direct0_cfg_pad_i368, fabric_direct0_cfg_pad_i369, fabric_direct0_cfg_pad_i370, fabric_direct0_cfg_pad_i371, fabric_direct0_cfg_pad_i372, fabric_direct0_cfg_pad_i373, fabric_direct0_cfg_pad_i374, fabric_direct0_cfg_pad_i375, fabric_direct0_cfg_pad_i376, fabric_direct0_cfg_pad_i377, fabric_direct0_cfg_pad_i378, fabric_direct0_cfg_pad_i379 -, fabric_direct0_cfg_pad_i380, fabric_direct0_cfg_pad_i381, fabric_direct0_cfg_pad_i382, fabric_direct0_cfg_pad_i383, fabric_direct0_cfg_pad_i384, fabric_direct0_cfg_pad_i385, fabric_direct0_cfg_pad_i386, fabric_direct0_cfg_pad_i387, fabric_direct0_cfg_pad_i388, fabric_direct0_cfg_pad_i389, fabric_direct0_cfg_pad_i390, fabric_direct0_cfg_pad_i391, fabric_direct0_cfg_pad_i392, fabric_direct0_cfg_pad_i393, fabric_direct0_cfg_pad_i394, fabric_direct0_cfg_pad_i395, fabric_direct0_cfg_pad_i396, fabric_direct0_cfg_pad_i397, fabric_direct0_cfg_pad_i398, fabric_direct0_cfg_pad_i399, fabric_direct0_cfg_pad_i400 -, fabric_direct0_cfg_pad_i401, fabric_direct0_cfg_pad_i402, fabric_direct0_cfg_pad_i403, fabric_direct0_cfg_pad_i404, fabric_direct0_cfg_pad_i405, fabric_direct0_cfg_pad_i406, fabric_direct0_cfg_pad_i407, fabric_direct0_cfg_pad_i408, fabric_direct0_cfg_pad_i409, fabric_direct0_cfg_pad_i410, fabric_direct0_cfg_pad_i411, fabric_direct0_cfg_pad_i412, fabric_direct0_cfg_pad_i413, fabric_direct0_cfg_pad_i414, fabric_direct0_cfg_pad_i415, fabric_direct0_cfg_pad_i416, fabric_direct0_cfg_pad_i417, fabric_direct0_cfg_pad_i418, fabric_direct0_cfg_pad_i419, fabric_direct0_cfg_pad_i420, fabric_direct0_cfg_pad_i421 -, fabric_direct0_cfg_pad_i422, fabric_direct0_cfg_pad_i423, fabric_direct0_cfg_pad_i424, fabric_direct0_cfg_pad_i425, fabric_direct0_cfg_pad_i426, fabric_direct0_cfg_pad_i427, fabric_direct0_cfg_pad_i428, fabric_direct0_cfg_pad_i429, fabric_direct0_cfg_pad_i430, fabric_direct0_cfg_pad_i431, fabric_direct0_cfg_pad_i432, fabric_direct0_cfg_pad_i433, fabric_direct0_cfg_pad_i434, fabric_direct0_cfg_pad_i435, fabric_direct0_cfg_pad_i436, fabric_direct0_cfg_pad_i437, fabric_direct0_cfg_pad_i438, fabric_direct0_cfg_pad_i439, fabric_direct0_cfg_pad_i440, fabric_direct0_cfg_pad_i441, fabric_direct0_cfg_pad_i442 -, fabric_direct0_cfg_pad_i443, fabric_direct0_cfg_pad_i444, fabric_direct0_cfg_pad_i445, fabric_direct0_cfg_pad_i446, fabric_direct0_cfg_pad_i447, fabric_direct0_cfg_pad_i448, fabric_direct0_cfg_pad_i449, fabric_direct0_cfg_pad_i450, fabric_direct0_cfg_pad_i451, fabric_direct0_cfg_pad_i452, fabric_direct0_cfg_pad_i453, fabric_direct0_cfg_pad_i454, fabric_direct0_cfg_pad_i455, fabric_direct0_cfg_pad_i456, fabric_direct0_cfg_pad_i457, fabric_direct0_cfg_pad_i458, fabric_direct0_cfg_pad_i459, fabric_direct0_cfg_pad_i460, fabric_direct0_cfg_pad_i461, fabric_direct0_cfg_pad_i462, fabric_direct0_cfg_pad_i463 -, fabric_direct0_cfg_pad_i464, fabric_direct0_cfg_pad_i465, fabric_direct0_cfg_pad_i466, fabric_direct0_cfg_pad_i467, fabric_direct0_cfg_pad_i468, fabric_direct0_cfg_pad_i469, fabric_direct0_cfg_pad_i470, fabric_direct0_cfg_pad_i471, fabric_direct0_cfg_pad_i472, fabric_direct0_cfg_pad_i473, fabric_direct0_cfg_pad_i474, fabric_direct0_cfg_pad_i475, fabric_direct0_cfg_pad_i476, fabric_direct0_cfg_pad_i477, fabric_direct0_cfg_pad_i478, fabric_direct0_cfg_pad_i479, fabric_direct0_cfg_pad_i480, fabric_direct0_cfg_pad_i481, fabric_direct0_cfg_pad_i482, fabric_direct0_cfg_pad_i483, fabric_direct0_cfg_pad_i484 -, fabric_direct0_cfg_pad_i485, fabric_direct0_cfg_pad_i486, fabric_direct0_cfg_pad_i487, fabric_direct0_cfg_pad_i488, fabric_direct0_cfg_pad_i489, fabric_direct0_cfg_pad_i490, fabric_direct0_cfg_pad_i491, fabric_direct0_cfg_pad_i492, fabric_direct0_cfg_pad_i493, fabric_direct0_cfg_pad_i494, fabric_direct0_cfg_pad_i495, fabric_direct0_cfg_pad_i496, fabric_direct0_cfg_pad_i497, fabric_direct0_cfg_pad_i498, fabric_direct0_cfg_pad_i499, fabric_direct0_cfg_pad_i500, fabric_direct0_cfg_pad_i501, fabric_direct0_cfg_pad_i502, fabric_direct0_cfg_pad_i503, fabric_direct0_cfg_pad_i504, fabric_direct0_cfg_pad_i505 -, fabric_direct0_cfg_pad_i506, fabric_direct0_cfg_pad_i507, fabric_direct0_cfg_pad_i508, fabric_direct0_cfg_pad_i509, fabric_direct0_cfg_pad_i510, fabric_direct0_cfg_pad_i511, fabric_direct0_cfg_pad_i512, fabric_direct0_cfg_pad_i513, fabric_direct0_cfg_pad_i514, fabric_direct0_cfg_pad_i515, fabric_direct0_cfg_pad_i516, fabric_direct0_cfg_pad_i517, fabric_direct0_cfg_pad_i518, fabric_direct0_cfg_pad_i519, fabric_direct0_cfg_pad_i520, fabric_direct0_cfg_pad_i521, fabric_direct0_cfg_pad_i522, fabric_direct0_cfg_pad_i523, fabric_direct0_cfg_pad_i524, fabric_direct0_cfg_pad_i525, fabric_direct0_cfg_pad_i526 -, fabric_direct0_cfg_pad_i527, fabric_direct0_cfg_pad_i528, fabric_direct0_cfg_pad_i529, fabric_direct0_cfg_pad_i530, fabric_direct0_cfg_pad_i531, fabric_direct0_cfg_pad_i532, fabric_direct0_cfg_pad_i533, fabric_direct0_cfg_pad_i534, fabric_direct0_cfg_pad_i535, fabric_direct0_cfg_pad_i536, fabric_direct0_cfg_pad_i537, fabric_direct0_cfg_pad_i538, fabric_direct0_cfg_pad_i539, fabric_direct0_cfg_pad_i540, fabric_direct0_cfg_pad_i541, fabric_direct0_cfg_pad_i542, fabric_direct0_cfg_pad_i543, fabric_direct0_cfg_pad_i544, fabric_direct0_cfg_pad_i545, fabric_direct0_cfg_pad_i546, fabric_direct0_cfg_pad_i547 -, fabric_direct0_cfg_pad_i548, fabric_direct0_cfg_pad_i549, fabric_direct0_cfg_pad_i550, fabric_direct0_cfg_pad_i551, fabric_direct0_cfg_pad_i552, fabric_direct0_cfg_pad_i553, fabric_direct0_cfg_pad_i554, fabric_direct0_cfg_pad_i555, fabric_direct0_cfg_pad_i556, fabric_direct0_cfg_pad_i557, fabric_direct0_cfg_pad_i558, fabric_direct0_cfg_pad_i559, fabric_direct0_cfg_pad_i560, fabric_direct0_cfg_pad_i561, fabric_direct0_cfg_pad_i562, fabric_direct0_cfg_pad_i563, fabric_direct0_cfg_pad_i564, fabric_direct0_cfg_pad_i565, fabric_direct0_cfg_pad_i566, fabric_direct0_cfg_pad_i567, fabric_direct0_cfg_pad_i568 -, fabric_direct0_cfg_pad_i569, fabric_direct0_cfg_pad_i570, fabric_direct0_cfg_pad_i571, fabric_direct0_cfg_pad_i572, fabric_direct0_cfg_pad_i573, fabric_direct0_cfg_pad_i574, fabric_direct0_cfg_pad_i575, fabric_direct0_cfg_pad_i576, fabric_direct0_cfg_pad_i577, fabric_direct0_cfg_pad_i578, fabric_direct0_cfg_pad_i579, fabric_direct0_cfg_pad_i580, fabric_direct0_cfg_pad_i581, fabric_direct0_cfg_pad_i582, fabric_direct0_cfg_pad_i583, fabric_direct0_cfg_pad_i584, fabric_direct0_cfg_pad_i585, fabric_direct0_cfg_pad_i586, fabric_direct0_cfg_pad_i587, fabric_direct0_cfg_pad_i588, fabric_direct0_cfg_pad_i589 -, fabric_direct0_cfg_pad_i590, fabric_direct0_cfg_pad_i591, fabric_direct0_cfg_pad_i592, fabric_direct0_cfg_pad_i593, fabric_direct0_cfg_pad_i594, fabric_direct0_cfg_pad_i595, fabric_direct0_cfg_pad_i596, fabric_direct0_cfg_pad_i597, fabric_direct0_cfg_pad_i598, fabric_direct0_cfg_pad_i599, fabric_direct0_cfg_pad_i600, fabric_direct0_cfg_pad_i601, fabric_direct0_cfg_pad_i602, fabric_direct0_cfg_pad_i603, fabric_direct0_cfg_pad_i604, fabric_direct0_cfg_pad_i605, fabric_direct0_cfg_pad_i606, fabric_direct0_cfg_pad_i607, fabric_direct0_cfg_pad_i608, fabric_direct0_cfg_pad_i609, fabric_direct0_cfg_pad_i610 -, fabric_direct0_cfg_pad_i611, fabric_direct0_cfg_pad_i612, fabric_direct0_cfg_pad_i613, fabric_direct0_cfg_pad_i614, fabric_direct0_cfg_pad_i615, fabric_direct0_cfg_pad_i616, fabric_direct0_cfg_pad_i617, fabric_direct0_cfg_pad_i618, fabric_direct0_cfg_pad_i619, fabric_direct0_cfg_pad_i620, fabric_direct0_cfg_pad_i621, fabric_direct0_cfg_pad_i622, fabric_direct0_cfg_pad_i623, fabric_direct0_cfg_pad_i624, fabric_direct0_cfg_pad_i625, fabric_direct0_cfg_pad_i626, fabric_direct0_cfg_pad_i627, fabric_direct0_cfg_pad_i628, fabric_direct0_cfg_pad_i629, fabric_direct0_cfg_pad_i630, fabric_direct0_cfg_pad_i631 -, fabric_direct0_cfg_pad_i632, fabric_direct0_cfg_pad_i633, fabric_direct0_cfg_pad_i634, fabric_direct0_cfg_pad_i635, fabric_direct0_cfg_pad_i636, fabric_direct0_cfg_pad_i637, fabric_direct0_cfg_pad_i638, fabric_direct0_cfg_pad_i639, fabric_direct0_cfg_pad_i640, fabric_direct0_cfg_pad_i641, fabric_direct0_cfg_pad_i642, fabric_direct0_cfg_pad_i643, fabric_direct0_cfg_pad_i644, fabric_direct0_cfg_pad_i645, fabric_direct0_cfg_pad_i646, fabric_direct0_cfg_pad_i647, fabric_direct0_cfg_pad_i648, fabric_direct0_cfg_pad_i649, fabric_direct0_cfg_pad_i650, fabric_direct0_cfg_pad_i651, fabric_direct0_cfg_pad_i652 -, fabric_direct0_cfg_pad_i653, fabric_direct0_cfg_pad_i654, fabric_direct0_cfg_pad_i655, fabric_direct0_cfg_pad_i656, fabric_direct0_cfg_pad_i657, fabric_direct0_cfg_pad_i658, fabric_direct0_cfg_pad_i659, fabric_direct0_cfg_pad_i660, fabric_direct0_cfg_pad_i661, fabric_direct0_cfg_pad_i662, fabric_direct0_cfg_pad_i663, fabric_direct0_cfg_pad_i664, fabric_direct0_cfg_pad_i665, fabric_direct0_cfg_pad_i666, fabric_direct0_cfg_pad_i667, fabric_direct0_cfg_pad_i668, fabric_direct0_cfg_pad_i669, fabric_direct0_cfg_pad_i670, fabric_direct0_cfg_pad_i671, fabric_direct0_cfg_pad_i672, fabric_direct0_cfg_pad_i673 -, fabric_direct0_cfg_pad_i674, fabric_direct0_cfg_pad_i675, fabric_direct0_cfg_pad_i676, fabric_direct0_cfg_pad_i677, fabric_direct0_cfg_pad_i678, fabric_direct0_cfg_pad_i679, fabric_direct0_cfg_pad_i680, fabric_direct0_cfg_pad_i681, fabric_direct0_cfg_pad_i682, fabric_direct0_cfg_pad_i683, fabric_direct0_cfg_pad_i684, fabric_direct0_cfg_pad_i685, fabric_direct0_cfg_pad_i686, fabric_direct0_cfg_pad_i687, fabric_direct0_cfg_pad_i688, fabric_direct0_cfg_pad_i689, fabric_direct0_cfg_pad_i690, fabric_direct0_cfg_pad_i691, fabric_direct0_cfg_pad_i692, fabric_direct0_cfg_pad_i693, fabric_direct0_cfg_pad_i694 -, fabric_direct0_cfg_pad_i695, fabric_direct0_cfg_pad_i696, fabric_direct0_cfg_pad_i697, fabric_direct0_cfg_pad_i698, fabric_direct0_cfg_pad_i699, fabric_direct0_cfg_pad_i700, fabric_direct0_cfg_pad_i701, fabric_direct0_cfg_pad_i702, fabric_direct0_cfg_pad_i703, fabric_direct0_cfg_pad_i704, fabric_direct0_cfg_pad_i705, fabric_direct0_cfg_pad_i706, fabric_direct0_cfg_pad_i707, fabric_direct0_cfg_pad_i708, fabric_direct0_cfg_pad_i709, fabric_direct0_cfg_pad_i710, fabric_direct0_cfg_pad_i711, fabric_direct0_cfg_pad_i712, fabric_direct0_cfg_pad_i713, fabric_direct0_cfg_pad_i714, fabric_direct0_cfg_pad_i715 -, fabric_direct0_cfg_pad_i716, fabric_direct0_cfg_pad_i717, fabric_direct0_cfg_pad_i718, fabric_direct0_cfg_pad_i719, fabric_direct0_cfg_pad_i720, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_clock_fabric_i1, fabric_direct2_clock_fabric_i2, fabric_direct2_clock_fabric_i3, fabric_direct2_clock_fabric_i4, fabric_direct2_oe_i1, fabric_direct2_oe_i2, fabric_direct2_oe_i3, fabric_direct2_oe_i4, fabric_direct2_oe_i5, fabric_direct2_oe_i6, fabric_direct2_oe_i7, fabric_direct2_oe_i8, fabric_direct2_oe_i9 -, fabric_direct2_oe_i10, fabric_direct2_oe_i11, fabric_direct2_oe_i12, fabric_direct2_oe_i13, fabric_direct2_oe_i14, fabric_direct2_oe_i15, fabric_direct2_oe_i16, fabric_direct2_oe_i17, fabric_direct2_oe_i18, fabric_direct2_oe_i19, fabric_direct2_oe_i20, fabric_direct2_oe_i21, fabric_direct2_oe_i22, fabric_direct2_oe_i23, fabric_direct2_oe_i24, fabric_direct2_oe_ena_i1, fabric_direct2_oe_ena_i2, fabric_direct2_oe_ena_i3, fabric_direct2_oe_ena_i4, fabric_direct2_oe_ena_i5, fabric_direct2_oe_ena_i6 -, fabric_direct2_oe_ena_i7, fabric_direct2_oe_ena_i8, fabric_direct2_oe_ena_i9, fabric_direct2_oe_ena_i10, fabric_direct2_oe_ena_i11, fabric_direct2_oe_ena_i12, fabric_direct2_oe_ena_i13, fabric_direct2_oe_ena_i14, fabric_direct2_oe_ena_i15, fabric_direct2_oe_ena_i16, fabric_direct2_oe_ena_i17, fabric_direct2_oe_ena_i18, fabric_direct2_oe_ena_i19, fabric_direct2_oe_ena_i20, fabric_direct2_oe_ena_i21, fabric_direct2_oe_ena_i22, fabric_direct2_oe_ena_i23, fabric_direct2_oe_ena_i24, fabric_direct2_oe_rs_i1, fabric_direct2_oe_rs_i2, fabric_direct2_oe_rs_i3 -, fabric_direct2_oe_rs_i4, fabric_direct2_oe_rs_i5, fabric_direct2_oe_rs_i6, fabric_direct2_oe_rs_i7, fabric_direct2_oe_rs_i8, fabric_direct2_oe_rs_i9, fabric_direct2_oe_rs_i10, fabric_direct2_oe_rs_i11, fabric_direct2_oe_rs_i12, fabric_direct2_oe_rs_i13, fabric_direct2_oe_rs_i14, fabric_direct2_oe_rs_i15, fabric_direct2_oe_rs_i16, fabric_direct2_oe_rs_i17, fabric_direct2_oe_rs_i18, fabric_direct2_oe_rs_i19, fabric_direct2_oe_rs_i20, fabric_direct2_oe_rs_i21, fabric_direct2_oe_rs_i22, fabric_direct2_oe_rs_i23, fabric_direct2_oe_rs_i24 -, fabric_direct2_do_i1, fabric_direct2_do_i2, fabric_direct2_do_i3, fabric_direct2_do_i4, fabric_direct2_do_i5, fabric_direct2_do_i6, fabric_direct2_do_i7, fabric_direct2_do_i8, fabric_direct2_do_i9, fabric_direct2_do_i10, fabric_direct2_do_i11, fabric_direct2_do_i12, fabric_direct2_do_i13, fabric_direct2_do_i14, fabric_direct2_do_i15, fabric_direct2_do_i16, fabric_direct2_do_i17, fabric_direct2_do_i18, fabric_direct2_do_i19, fabric_direct2_do_i20, fabric_direct2_do_i21 -, fabric_direct2_do_i22, fabric_direct2_do_i23, fabric_direct2_do_i24, fabric_direct2_do_ena_i1, fabric_direct2_do_ena_i2, fabric_direct2_do_ena_i3, fabric_direct2_do_ena_i4, fabric_direct2_do_ena_i5, fabric_direct2_do_ena_i6, fabric_direct2_do_ena_i7, fabric_direct2_do_ena_i8, fabric_direct2_do_ena_i9, fabric_direct2_do_ena_i10, fabric_direct2_do_ena_i11, fabric_direct2_do_ena_i12, fabric_direct2_do_ena_i13, fabric_direct2_do_ena_i14, fabric_direct2_do_ena_i15, fabric_direct2_do_ena_i16, fabric_direct2_do_ena_i17, fabric_direct2_do_ena_i18 -, fabric_direct2_do_ena_i19, fabric_direct2_do_ena_i20, fabric_direct2_do_ena_i21, fabric_direct2_do_ena_i22, fabric_direct2_do_ena_i23, fabric_direct2_do_ena_i24, fabric_direct2_do_rs_i1, fabric_direct2_do_rs_i2, fabric_direct2_do_rs_i3, fabric_direct2_do_rs_i4, fabric_direct2_do_rs_i5, fabric_direct2_do_rs_i6, fabric_direct2_do_rs_i7, fabric_direct2_do_rs_i8, fabric_direct2_do_rs_i9, fabric_direct2_do_rs_i10, fabric_direct2_do_rs_i11, fabric_direct2_do_rs_i12, fabric_direct2_do_rs_i13, fabric_direct2_do_rs_i14, fabric_direct2_do_rs_i15 -, fabric_direct2_do_rs_i16, fabric_direct2_do_rs_i17, fabric_direct2_do_rs_i18, fabric_direct2_do_rs_i19, fabric_direct2_do_rs_i20, fabric_direct2_do_rs_i21, fabric_direct2_do_rs_i22, fabric_direct2_do_rs_i23, fabric_direct2_do_rs_i24, fabric_direct2_di_o1, fabric_direct2_di_o2, fabric_direct2_di_o3, fabric_direct2_di_o4, fabric_direct2_di_o5, fabric_direct2_di_o6, fabric_direct2_di_o7, fabric_direct2_di_o8, fabric_direct2_di_o9, fabric_direct2_di_o10, fabric_direct2_di_o11, fabric_direct2_di_o12 -, fabric_direct2_di_o13, fabric_direct2_di_o14, fabric_direct2_di_o15, fabric_direct2_di_o16, fabric_direct2_di_o17, fabric_direct2_di_o18, fabric_direct2_di_o19, fabric_direct2_di_o20, fabric_direct2_di_o21, fabric_direct2_di_o22, fabric_direct2_di_o23, fabric_direct2_di_o24, fabric_direct2_di_ena_i1, fabric_direct2_di_ena_i2, fabric_direct2_di_ena_i3, fabric_direct2_di_ena_i4, fabric_direct2_di_ena_i5, fabric_direct2_di_ena_i6, fabric_direct2_di_ena_i7, fabric_direct2_di_ena_i8, fabric_direct2_di_ena_i9 -, fabric_direct2_di_ena_i10, fabric_direct2_di_ena_i11, fabric_direct2_di_ena_i12, fabric_direct2_di_ena_i13, fabric_direct2_di_ena_i14, fabric_direct2_di_ena_i15, fabric_direct2_di_ena_i16, fabric_direct2_di_ena_i17, fabric_direct2_di_ena_i18, fabric_direct2_di_ena_i19, fabric_direct2_di_ena_i20, fabric_direct2_di_ena_i21, fabric_direct2_di_ena_i22, fabric_direct2_di_ena_i23, fabric_direct2_di_ena_i24, fabric_direct2_di_rs_i1, fabric_direct2_di_rs_i2, fabric_direct2_di_rs_i3, fabric_direct2_di_rs_i4, fabric_direct2_di_rs_i5, fabric_direct2_di_rs_i6 -, fabric_direct2_di_rs_i7, fabric_direct2_di_rs_i8, fabric_direct2_di_rs_i9, fabric_direct2_di_rs_i10, fabric_direct2_di_rs_i11, fabric_direct2_di_rs_i12, fabric_direct2_di_rs_i13, fabric_direct2_di_rs_i14, fabric_direct2_di_rs_i15, fabric_direct2_di_rs_i16, fabric_direct2_di_rs_i17, fabric_direct2_di_rs_i18, fabric_direct2_di_rs_i19, fabric_direct2_di_rs_i20, fabric_direct2_di_rs_i21, fabric_direct2_di_rs_i22, fabric_direct2_di_rs_i23, fabric_direct2_di_rs_i24, fabric_direct2_cfg_bank_i1, fabric_direct2_cfg_bank_i2, fabric_direct2_cfg_bank_i3 -, fabric_direct2_cfg_bank_i4, fabric_direct2_cfg_pad_i1, fabric_direct2_cfg_pad_i2, fabric_direct2_cfg_pad_i3, fabric_direct2_cfg_pad_i4, fabric_direct2_cfg_pad_i5, fabric_direct2_cfg_pad_i6, fabric_direct2_cfg_pad_i7, fabric_direct2_cfg_pad_i8, fabric_direct2_cfg_pad_i9, fabric_direct2_cfg_pad_i10, fabric_direct2_cfg_pad_i11, fabric_direct2_cfg_pad_i12, fabric_direct2_cfg_pad_i13, fabric_direct2_cfg_pad_i14, fabric_direct2_cfg_pad_i15, fabric_direct2_cfg_pad_i16, fabric_direct2_cfg_pad_i17, fabric_direct2_cfg_pad_i18, fabric_direct2_cfg_pad_i19, fabric_direct2_cfg_pad_i20 -, fabric_direct2_cfg_pad_i21, fabric_direct2_cfg_pad_i22, fabric_direct2_cfg_pad_i23, fabric_direct2_cfg_pad_i24, fabric_direct2_cfg_pad_i25, fabric_direct2_cfg_pad_i26, fabric_direct2_cfg_pad_i27, fabric_direct2_cfg_pad_i28, fabric_direct2_cfg_pad_i29, fabric_direct2_cfg_pad_i30, fabric_direct2_cfg_pad_i31, fabric_direct2_cfg_pad_i32, fabric_direct2_cfg_pad_i33, fabric_direct2_cfg_pad_i34, fabric_direct2_cfg_pad_i35, fabric_direct2_cfg_pad_i36, fabric_direct2_cfg_pad_i37, fabric_direct2_cfg_pad_i38, fabric_direct2_cfg_pad_i39, fabric_direct2_cfg_pad_i40, fabric_direct2_cfg_pad_i41 -, fabric_direct2_cfg_pad_i42, fabric_direct2_cfg_pad_i43, fabric_direct2_cfg_pad_i44, fabric_direct2_cfg_pad_i45, fabric_direct2_cfg_pad_i46, fabric_direct2_cfg_pad_i47, fabric_direct2_cfg_pad_i48, fabric_direct2_cfg_pad_i49, fabric_direct2_cfg_pad_i50, fabric_direct2_cfg_pad_i51, fabric_direct2_cfg_pad_i52, fabric_direct2_cfg_pad_i53, fabric_direct2_cfg_pad_i54, fabric_direct2_cfg_pad_i55, fabric_direct2_cfg_pad_i56, fabric_direct2_cfg_pad_i57, fabric_direct2_cfg_pad_i58, fabric_direct2_cfg_pad_i59, fabric_direct2_cfg_pad_i60, fabric_direct2_cfg_pad_i61, fabric_direct2_cfg_pad_i62 -, fabric_direct2_cfg_pad_i63, fabric_direct2_cfg_pad_i64, fabric_direct2_cfg_pad_i65, fabric_direct2_cfg_pad_i66, fabric_direct2_cfg_pad_i67, fabric_direct2_cfg_pad_i68, fabric_direct2_cfg_pad_i69, fabric_direct2_cfg_pad_i70, fabric_direct2_cfg_pad_i71, fabric_direct2_cfg_pad_i72, fabric_direct2_cfg_pad_i73, fabric_direct2_cfg_pad_i74, fabric_direct2_cfg_pad_i75, fabric_direct2_cfg_pad_i76, fabric_direct2_cfg_pad_i77, fabric_direct2_cfg_pad_i78, fabric_direct2_cfg_pad_i79, fabric_direct2_cfg_pad_i80, fabric_direct2_cfg_pad_i81, fabric_direct2_cfg_pad_i82, fabric_direct2_cfg_pad_i83 -, fabric_direct2_cfg_pad_i84, fabric_direct2_cfg_pad_i85, fabric_direct2_cfg_pad_i86, fabric_direct2_cfg_pad_i87, fabric_direct2_cfg_pad_i88, fabric_direct2_cfg_pad_i89, fabric_direct2_cfg_pad_i90, fabric_direct2_cfg_pad_i91, fabric_direct2_cfg_pad_i92, fabric_direct2_cfg_pad_i93, fabric_direct2_cfg_pad_i94, fabric_direct2_cfg_pad_i95, fabric_direct2_cfg_pad_i96, fabric_direct2_cfg_pad_i97, fabric_direct2_cfg_pad_i98, fabric_direct2_cfg_pad_i99, fabric_direct2_cfg_pad_i100, fabric_direct2_cfg_pad_i101, fabric_direct2_cfg_pad_i102, fabric_direct2_cfg_pad_i103, fabric_direct2_cfg_pad_i104 -, fabric_direct2_cfg_pad_i105, fabric_direct2_cfg_pad_i106, fabric_direct2_cfg_pad_i107, fabric_direct2_cfg_pad_i108, fabric_direct2_cfg_pad_i109, fabric_direct2_cfg_pad_i110, fabric_direct2_cfg_pad_i111, fabric_direct2_cfg_pad_i112, fabric_direct2_cfg_pad_i113, fabric_direct2_cfg_pad_i114, fabric_direct2_cfg_pad_i115, fabric_direct2_cfg_pad_i116, fabric_direct2_cfg_pad_i117, fabric_direct2_cfg_pad_i118, fabric_direct2_cfg_pad_i119, fabric_direct2_cfg_pad_i120, fabric_direct2_cfg_pad_i121, fabric_direct2_cfg_pad_i122, fabric_direct2_cfg_pad_i123, fabric_direct2_cfg_pad_i124, fabric_direct2_cfg_pad_i125 -, fabric_direct2_cfg_pad_i126, fabric_direct2_cfg_pad_i127, fabric_direct2_cfg_pad_i128, fabric_direct2_cfg_pad_i129, fabric_direct2_cfg_pad_i130, fabric_direct2_cfg_pad_i131, fabric_direct2_cfg_pad_i132, fabric_direct2_cfg_pad_i133, fabric_direct2_cfg_pad_i134, fabric_direct2_cfg_pad_i135, fabric_direct2_cfg_pad_i136, fabric_direct2_cfg_pad_i137, fabric_direct2_cfg_pad_i138, fabric_direct2_cfg_pad_i139, fabric_direct2_cfg_pad_i140, fabric_direct2_cfg_pad_i141, fabric_direct2_cfg_pad_i142, fabric_direct2_cfg_pad_i143, fabric_direct2_cfg_pad_i144, fabric_direct2_cfg_pad_i145, fabric_direct2_cfg_pad_i146 -, fabric_direct2_cfg_pad_i147, fabric_direct2_cfg_pad_i148, fabric_direct2_cfg_pad_i149, fabric_direct2_cfg_pad_i150, fabric_direct2_cfg_pad_i151, fabric_direct2_cfg_pad_i152, fabric_direct2_cfg_pad_i153, fabric_direct2_cfg_pad_i154, fabric_direct2_cfg_pad_i155, fabric_direct2_cfg_pad_i156, fabric_direct2_cfg_pad_i157, fabric_direct2_cfg_pad_i158, fabric_direct2_cfg_pad_i159, fabric_direct2_cfg_pad_i160, fabric_direct2_cfg_pad_i161, fabric_direct2_cfg_pad_i162, fabric_direct2_cfg_pad_i163, fabric_direct2_cfg_pad_i164, fabric_direct2_cfg_pad_i165, fabric_direct2_cfg_pad_i166, fabric_direct2_cfg_pad_i167 -, fabric_direct2_cfg_pad_i168, fabric_direct2_cfg_pad_i169, fabric_direct2_cfg_pad_i170, fabric_direct2_cfg_pad_i171, fabric_direct2_cfg_pad_i172, fabric_direct2_cfg_pad_i173, fabric_direct2_cfg_pad_i174, fabric_direct2_cfg_pad_i175, fabric_direct2_cfg_pad_i176, fabric_direct2_cfg_pad_i177, fabric_direct2_cfg_pad_i178, fabric_direct2_cfg_pad_i179, fabric_direct2_cfg_pad_i180, fabric_direct2_cfg_pad_i181, fabric_direct2_cfg_pad_i182, fabric_direct2_cfg_pad_i183, fabric_direct2_cfg_pad_i184, fabric_direct2_cfg_pad_i185, fabric_direct2_cfg_pad_i186, fabric_direct2_cfg_pad_i187, fabric_direct2_cfg_pad_i188 -, fabric_direct2_cfg_pad_i189, fabric_direct2_cfg_pad_i190, fabric_direct2_cfg_pad_i191, fabric_direct2_cfg_pad_i192, fabric_direct2_cfg_pad_i193, fabric_direct2_cfg_pad_i194, fabric_direct2_cfg_pad_i195, fabric_direct2_cfg_pad_i196, fabric_direct2_cfg_pad_i197, fabric_direct2_cfg_pad_i198, fabric_direct2_cfg_pad_i199, fabric_direct2_cfg_pad_i200, fabric_direct2_cfg_pad_i201, fabric_direct2_cfg_pad_i202, fabric_direct2_cfg_pad_i203, fabric_direct2_cfg_pad_i204, fabric_direct2_cfg_pad_i205, fabric_direct2_cfg_pad_i206, fabric_direct2_cfg_pad_i207, fabric_direct2_cfg_pad_i208, fabric_direct2_cfg_pad_i209 -, fabric_direct2_cfg_pad_i210, fabric_direct2_cfg_pad_i211, fabric_direct2_cfg_pad_i212, fabric_direct2_cfg_pad_i213, fabric_direct2_cfg_pad_i214, fabric_direct2_cfg_pad_i215, fabric_direct2_cfg_pad_i216, fabric_direct2_cfg_pad_i217, fabric_direct2_cfg_pad_i218, fabric_direct2_cfg_pad_i219, fabric_direct2_cfg_pad_i220, fabric_direct2_cfg_pad_i221, fabric_direct2_cfg_pad_i222, fabric_direct2_cfg_pad_i223, fabric_direct2_cfg_pad_i224, fabric_direct2_cfg_pad_i225, fabric_direct2_cfg_pad_i226, fabric_direct2_cfg_pad_i227, fabric_direct2_cfg_pad_i228, fabric_direct2_cfg_pad_i229, fabric_direct2_cfg_pad_i230 -, fabric_direct2_cfg_pad_i231, fabric_direct2_cfg_pad_i232, fabric_direct2_cfg_pad_i233, fabric_direct2_cfg_pad_i234, fabric_direct2_cfg_pad_i235, fabric_direct2_cfg_pad_i236, fabric_direct2_cfg_pad_i237, fabric_direct2_cfg_pad_i238, fabric_direct2_cfg_pad_i239, fabric_direct2_cfg_pad_i240, fabric_direct2_cfg_pad_i241, fabric_direct2_cfg_pad_i242, fabric_direct2_cfg_pad_i243, fabric_direct2_cfg_pad_i244, fabric_direct2_cfg_pad_i245, fabric_direct2_cfg_pad_i246, fabric_direct2_cfg_pad_i247, fabric_direct2_cfg_pad_i248, fabric_direct2_cfg_pad_i249, fabric_direct2_cfg_pad_i250, fabric_direct2_cfg_pad_i251 -, fabric_direct2_cfg_pad_i252, fabric_direct2_cfg_pad_i253, fabric_direct2_cfg_pad_i254, fabric_direct2_cfg_pad_i255, fabric_direct2_cfg_pad_i256, fabric_direct2_cfg_pad_i257, fabric_direct2_cfg_pad_i258, fabric_direct2_cfg_pad_i259, fabric_direct2_cfg_pad_i260, fabric_direct2_cfg_pad_i261, fabric_direct2_cfg_pad_i262, fabric_direct2_cfg_pad_i263, fabric_direct2_cfg_pad_i264, fabric_direct2_cfg_pad_i265, fabric_direct2_cfg_pad_i266, fabric_direct2_cfg_pad_i267, fabric_direct2_cfg_pad_i268, fabric_direct2_cfg_pad_i269, fabric_direct2_cfg_pad_i270, fabric_direct2_cfg_pad_i271, fabric_direct2_cfg_pad_i272 -, fabric_direct2_cfg_pad_i273, fabric_direct2_cfg_pad_i274, fabric_direct2_cfg_pad_i275, fabric_direct2_cfg_pad_i276, fabric_direct2_cfg_pad_i277, fabric_direct2_cfg_pad_i278, fabric_direct2_cfg_pad_i279, fabric_direct2_cfg_pad_i280, fabric_direct2_cfg_pad_i281, fabric_direct2_cfg_pad_i282, fabric_direct2_cfg_pad_i283, fabric_direct2_cfg_pad_i284, fabric_direct2_cfg_pad_i285, fabric_direct2_cfg_pad_i286, fabric_direct2_cfg_pad_i287, fabric_direct2_cfg_pad_i288, fabric_direct2_cfg_pad_i289, fabric_direct2_cfg_pad_i290, fabric_direct2_cfg_pad_i291, fabric_direct2_cfg_pad_i292, fabric_direct2_cfg_pad_i293 -, fabric_direct2_cfg_pad_i294, fabric_direct2_cfg_pad_i295, fabric_direct2_cfg_pad_i296, fabric_direct2_cfg_pad_i297, fabric_direct2_cfg_pad_i298, fabric_direct2_cfg_pad_i299, fabric_direct2_cfg_pad_i300, fabric_direct2_cfg_pad_i301, fabric_direct2_cfg_pad_i302, fabric_direct2_cfg_pad_i303, fabric_direct2_cfg_pad_i304, fabric_direct2_cfg_pad_i305, fabric_direct2_cfg_pad_i306, fabric_direct2_cfg_pad_i307, fabric_direct2_cfg_pad_i308, fabric_direct2_cfg_pad_i309, fabric_direct2_cfg_pad_i310, fabric_direct2_cfg_pad_i311, fabric_direct2_cfg_pad_i312, fabric_direct2_cfg_pad_i313, fabric_direct2_cfg_pad_i314 -, fabric_direct2_cfg_pad_i315, fabric_direct2_cfg_pad_i316, fabric_direct2_cfg_pad_i317, fabric_direct2_cfg_pad_i318, fabric_direct2_cfg_pad_i319, fabric_direct2_cfg_pad_i320, fabric_direct2_cfg_pad_i321, fabric_direct2_cfg_pad_i322, fabric_direct2_cfg_pad_i323, fabric_direct2_cfg_pad_i324, fabric_direct2_cfg_pad_i325, fabric_direct2_cfg_pad_i326, fabric_direct2_cfg_pad_i327, fabric_direct2_cfg_pad_i328, fabric_direct2_cfg_pad_i329, fabric_direct2_cfg_pad_i330, fabric_direct2_cfg_pad_i331, fabric_direct2_cfg_pad_i332, fabric_direct2_cfg_pad_i333, fabric_direct2_cfg_pad_i334, fabric_direct2_cfg_pad_i335 -, fabric_direct2_cfg_pad_i336, fabric_direct2_cfg_pad_i337, fabric_direct2_cfg_pad_i338, fabric_direct2_cfg_pad_i339, fabric_direct2_cfg_pad_i340, fabric_direct2_cfg_pad_i341, fabric_direct2_cfg_pad_i342, fabric_direct2_cfg_pad_i343, fabric_direct2_cfg_pad_i344, fabric_direct2_cfg_pad_i345, fabric_direct2_cfg_pad_i346, fabric_direct2_cfg_pad_i347, fabric_direct2_cfg_pad_i348, fabric_direct2_cfg_pad_i349, fabric_direct2_cfg_pad_i350, fabric_direct2_cfg_pad_i351, fabric_direct2_cfg_pad_i352, fabric_direct2_cfg_pad_i353, fabric_direct2_cfg_pad_i354, fabric_direct2_cfg_pad_i355, fabric_direct2_cfg_pad_i356 -, fabric_direct2_cfg_pad_i357, fabric_direct2_cfg_pad_i358, fabric_direct2_cfg_pad_i359, fabric_direct2_cfg_pad_i360, fabric_direct2_cfg_pad_i361, fabric_direct2_cfg_pad_i362, fabric_direct2_cfg_pad_i363, fabric_direct2_cfg_pad_i364, fabric_direct2_cfg_pad_i365, fabric_direct2_cfg_pad_i366, fabric_direct2_cfg_pad_i367, fabric_direct2_cfg_pad_i368, fabric_direct2_cfg_pad_i369, fabric_direct2_cfg_pad_i370, fabric_direct2_cfg_pad_i371, fabric_direct2_cfg_pad_i372, fabric_direct2_cfg_pad_i373, fabric_direct2_cfg_pad_i374, fabric_direct2_cfg_pad_i375, fabric_direct2_cfg_pad_i376, fabric_direct2_cfg_pad_i377 -, fabric_direct2_cfg_pad_i378, fabric_direct2_cfg_pad_i379, fabric_direct2_cfg_pad_i380, fabric_direct2_cfg_pad_i381, fabric_direct2_cfg_pad_i382, fabric_direct2_cfg_pad_i383, fabric_direct2_cfg_pad_i384, fabric_direct2_cfg_pad_i385, fabric_direct2_cfg_pad_i386, fabric_direct2_cfg_pad_i387, fabric_direct2_cfg_pad_i388, fabric_direct2_cfg_pad_i389, fabric_direct2_cfg_pad_i390, fabric_direct2_cfg_pad_i391, fabric_direct2_cfg_pad_i392, fabric_direct2_cfg_pad_i393, fabric_direct2_cfg_pad_i394, fabric_direct2_cfg_pad_i395, fabric_direct2_cfg_pad_i396, fabric_direct2_cfg_pad_i397, fabric_direct2_cfg_pad_i398 -, fabric_direct2_cfg_pad_i399, fabric_direct2_cfg_pad_i400, fabric_direct2_cfg_pad_i401, fabric_direct2_cfg_pad_i402, fabric_direct2_cfg_pad_i403, fabric_direct2_cfg_pad_i404, fabric_direct2_cfg_pad_i405, fabric_direct2_cfg_pad_i406, fabric_direct2_cfg_pad_i407, fabric_direct2_cfg_pad_i408, fabric_direct2_cfg_pad_i409, fabric_direct2_cfg_pad_i410, fabric_direct2_cfg_pad_i411, fabric_direct2_cfg_pad_i412, fabric_direct2_cfg_pad_i413, fabric_direct2_cfg_pad_i414, fabric_direct2_cfg_pad_i415, fabric_direct2_cfg_pad_i416, fabric_direct2_cfg_pad_i417, fabric_direct2_cfg_pad_i418, fabric_direct2_cfg_pad_i419 -, fabric_direct2_cfg_pad_i420, fabric_direct2_cfg_pad_i421, fabric_direct2_cfg_pad_i422, fabric_direct2_cfg_pad_i423, fabric_direct2_cfg_pad_i424, fabric_direct2_cfg_pad_i425, fabric_direct2_cfg_pad_i426, fabric_direct2_cfg_pad_i427, fabric_direct2_cfg_pad_i428, fabric_direct2_cfg_pad_i429, fabric_direct2_cfg_pad_i430, fabric_direct2_cfg_pad_i431, fabric_direct2_cfg_pad_i432, fabric_direct2_cfg_pad_i433, fabric_direct2_cfg_pad_i434, fabric_direct2_cfg_pad_i435, fabric_direct2_cfg_pad_i436, fabric_direct2_cfg_pad_i437, fabric_direct2_cfg_pad_i438, fabric_direct2_cfg_pad_i439, fabric_direct2_cfg_pad_i440 -, fabric_direct2_cfg_pad_i441, fabric_direct2_cfg_pad_i442, fabric_direct2_cfg_pad_i443, fabric_direct2_cfg_pad_i444, fabric_direct2_cfg_pad_i445, fabric_direct2_cfg_pad_i446, fabric_direct2_cfg_pad_i447, fabric_direct2_cfg_pad_i448, fabric_direct2_cfg_pad_i449, fabric_direct2_cfg_pad_i450, fabric_direct2_cfg_pad_i451, fabric_direct2_cfg_pad_i452, fabric_direct2_cfg_pad_i453, fabric_direct2_cfg_pad_i454, fabric_direct2_cfg_pad_i455, fabric_direct2_cfg_pad_i456, fabric_direct2_cfg_pad_i457, fabric_direct2_cfg_pad_i458, fabric_direct2_cfg_pad_i459, fabric_direct2_cfg_pad_i460, fabric_direct2_cfg_pad_i461 -, fabric_direct2_cfg_pad_i462, fabric_direct2_cfg_pad_i463, fabric_direct2_cfg_pad_i464, fabric_direct2_cfg_pad_i465, fabric_direct2_cfg_pad_i466, fabric_direct2_cfg_pad_i467, fabric_direct2_cfg_pad_i468, fabric_direct2_cfg_pad_i469, fabric_direct2_cfg_pad_i470, fabric_direct2_cfg_pad_i471, fabric_direct2_cfg_pad_i472, fabric_direct2_cfg_pad_i473, fabric_direct2_cfg_pad_i474, fabric_direct2_cfg_pad_i475, fabric_direct2_cfg_pad_i476, fabric_direct2_cfg_pad_i477, fabric_direct2_cfg_pad_i478, fabric_direct2_cfg_pad_i479, fabric_direct2_cfg_pad_i480, fabric_direct2_cfg_pad_i481, fabric_direct2_cfg_pad_i482 -, fabric_direct2_cfg_pad_i483, fabric_direct2_cfg_pad_i484, fabric_direct2_cfg_pad_i485, fabric_direct2_cfg_pad_i486, fabric_direct2_cfg_pad_i487, fabric_direct2_cfg_pad_i488, fabric_direct2_cfg_pad_i489, fabric_direct2_cfg_pad_i490, fabric_direct2_cfg_pad_i491, fabric_direct2_cfg_pad_i492, fabric_direct2_cfg_pad_i493, fabric_direct2_cfg_pad_i494, fabric_direct2_cfg_pad_i495, fabric_direct2_cfg_pad_i496, fabric_direct2_cfg_pad_i497, fabric_direct2_cfg_pad_i498, fabric_direct2_cfg_pad_i499, fabric_direct2_cfg_pad_i500, fabric_direct2_cfg_pad_i501, fabric_direct2_cfg_pad_i502, fabric_direct2_cfg_pad_i503 -, fabric_direct2_cfg_pad_i504, fabric_direct2_cfg_pad_i505, fabric_direct2_cfg_pad_i506, fabric_direct2_cfg_pad_i507, fabric_direct2_cfg_pad_i508, fabric_direct2_cfg_pad_i509, fabric_direct2_cfg_pad_i510, fabric_direct2_cfg_pad_i511, fabric_direct2_cfg_pad_i512, fabric_direct2_cfg_pad_i513, fabric_direct2_cfg_pad_i514, fabric_direct2_cfg_pad_i515, fabric_direct2_cfg_pad_i516, fabric_direct2_cfg_pad_i517, fabric_direct2_cfg_pad_i518, fabric_direct2_cfg_pad_i519, fabric_direct2_cfg_pad_i520, fabric_direct2_cfg_pad_i521, fabric_direct2_cfg_pad_i522, fabric_direct2_cfg_pad_i523, fabric_direct2_cfg_pad_i524 -, fabric_direct2_cfg_pad_i525, fabric_direct2_cfg_pad_i526, fabric_direct2_cfg_pad_i527, fabric_direct2_cfg_pad_i528, fabric_direct2_cfg_pad_i529, fabric_direct2_cfg_pad_i530, fabric_direct2_cfg_pad_i531, fabric_direct2_cfg_pad_i532, fabric_direct2_cfg_pad_i533, fabric_direct2_cfg_pad_i534, fabric_direct2_cfg_pad_i535, fabric_direct2_cfg_pad_i536, fabric_direct2_cfg_pad_i537, fabric_direct2_cfg_pad_i538, fabric_direct2_cfg_pad_i539, fabric_direct2_cfg_pad_i540, fabric_direct2_cfg_pad_i541, fabric_direct2_cfg_pad_i542, fabric_direct2_cfg_pad_i543, fabric_direct2_cfg_pad_i544, fabric_direct2_cfg_pad_i545 -, fabric_direct2_cfg_pad_i546, fabric_direct2_cfg_pad_i547, fabric_direct2_cfg_pad_i548, fabric_direct2_cfg_pad_i549, fabric_direct2_cfg_pad_i550, fabric_direct2_cfg_pad_i551, fabric_direct2_cfg_pad_i552, fabric_direct2_cfg_pad_i553, fabric_direct2_cfg_pad_i554, fabric_direct2_cfg_pad_i555, fabric_direct2_cfg_pad_i556, fabric_direct2_cfg_pad_i557, fabric_direct2_cfg_pad_i558, fabric_direct2_cfg_pad_i559, fabric_direct2_cfg_pad_i560, fabric_direct2_cfg_pad_i561, fabric_direct2_cfg_pad_i562, fabric_direct2_cfg_pad_i563, fabric_direct2_cfg_pad_i564, fabric_direct2_cfg_pad_i565, fabric_direct2_cfg_pad_i566 -, fabric_direct2_cfg_pad_i567, fabric_direct2_cfg_pad_i568, fabric_direct2_cfg_pad_i569, fabric_direct2_cfg_pad_i570, fabric_direct2_cfg_pad_i571, fabric_direct2_cfg_pad_i572, fabric_direct2_cfg_pad_i573, fabric_direct2_cfg_pad_i574, fabric_direct2_cfg_pad_i575, fabric_direct2_cfg_pad_i576, fabric_direct2_cfg_pad_i577, fabric_direct2_cfg_pad_i578, fabric_direct2_cfg_pad_i579, fabric_direct2_cfg_pad_i580, fabric_direct2_cfg_pad_i581, fabric_direct2_cfg_pad_i582, fabric_direct2_cfg_pad_i583, fabric_direct2_cfg_pad_i584, fabric_direct2_cfg_pad_i585, fabric_direct2_cfg_pad_i586, fabric_direct2_cfg_pad_i587 -, fabric_direct2_cfg_pad_i588, fabric_direct2_cfg_pad_i589, fabric_direct2_cfg_pad_i590, fabric_direct2_cfg_pad_i591, fabric_direct2_cfg_pad_i592, fabric_direct2_cfg_pad_i593, fabric_direct2_cfg_pad_i594, fabric_direct2_cfg_pad_i595, fabric_direct2_cfg_pad_i596, fabric_direct2_cfg_pad_i597, fabric_direct2_cfg_pad_i598, fabric_direct2_cfg_pad_i599, fabric_direct2_cfg_pad_i600, fabric_direct2_cfg_pad_i601, fabric_direct2_cfg_pad_i602, fabric_direct2_cfg_pad_i603, fabric_direct2_cfg_pad_i604, fabric_direct2_cfg_pad_i605, fabric_direct2_cfg_pad_i606, fabric_direct2_cfg_pad_i607, fabric_direct2_cfg_pad_i608 -, fabric_direct2_cfg_pad_i609, fabric_direct2_cfg_pad_i610, fabric_direct2_cfg_pad_i611, fabric_direct2_cfg_pad_i612, fabric_direct2_cfg_pad_i613, fabric_direct2_cfg_pad_i614, fabric_direct2_cfg_pad_i615, fabric_direct2_cfg_pad_i616, fabric_direct2_cfg_pad_i617, fabric_direct2_cfg_pad_i618, fabric_direct2_cfg_pad_i619, fabric_direct2_cfg_pad_i620, fabric_direct2_cfg_pad_i621, fabric_direct2_cfg_pad_i622, fabric_direct2_cfg_pad_i623, fabric_direct2_cfg_pad_i624, fabric_direct2_cfg_pad_i625, fabric_direct2_cfg_pad_i626, fabric_direct2_cfg_pad_i627, fabric_direct2_cfg_pad_i628, fabric_direct2_cfg_pad_i629 -, fabric_direct2_cfg_pad_i630, fabric_direct2_cfg_pad_i631, fabric_direct2_cfg_pad_i632, fabric_direct2_cfg_pad_i633, fabric_direct2_cfg_pad_i634, fabric_direct2_cfg_pad_i635, fabric_direct2_cfg_pad_i636, fabric_direct2_cfg_pad_i637, fabric_direct2_cfg_pad_i638, fabric_direct2_cfg_pad_i639, fabric_direct2_cfg_pad_i640, fabric_direct2_cfg_pad_i641, fabric_direct2_cfg_pad_i642, fabric_direct2_cfg_pad_i643, fabric_direct2_cfg_pad_i644, fabric_direct2_cfg_pad_i645, fabric_direct2_cfg_pad_i646, fabric_direct2_cfg_pad_i647, fabric_direct2_cfg_pad_i648, fabric_direct2_cfg_pad_i649, fabric_direct2_cfg_pad_i650 -, fabric_direct2_cfg_pad_i651, fabric_direct2_cfg_pad_i652, fabric_direct2_cfg_pad_i653, fabric_direct2_cfg_pad_i654, fabric_direct2_cfg_pad_i655, fabric_direct2_cfg_pad_i656, fabric_direct2_cfg_pad_i657, fabric_direct2_cfg_pad_i658, fabric_direct2_cfg_pad_i659, fabric_direct2_cfg_pad_i660, fabric_direct2_cfg_pad_i661, fabric_direct2_cfg_pad_i662, fabric_direct2_cfg_pad_i663, fabric_direct2_cfg_pad_i664, fabric_direct2_cfg_pad_i665, fabric_direct2_cfg_pad_i666, fabric_direct2_cfg_pad_i667, fabric_direct2_cfg_pad_i668, fabric_direct2_cfg_pad_i669, fabric_direct2_cfg_pad_i670, fabric_direct2_cfg_pad_i671 -, fabric_direct2_cfg_pad_i672, fabric_direct2_cfg_pad_i673, fabric_direct2_cfg_pad_i674, fabric_direct2_cfg_pad_i675, fabric_direct2_cfg_pad_i676, fabric_direct2_cfg_pad_i677, fabric_direct2_cfg_pad_i678, fabric_direct2_cfg_pad_i679, fabric_direct2_cfg_pad_i680, fabric_direct2_cfg_pad_i681, fabric_direct2_cfg_pad_i682, fabric_direct2_cfg_pad_i683, fabric_direct2_cfg_pad_i684, fabric_direct2_cfg_pad_i685, fabric_direct2_cfg_pad_i686, fabric_direct2_cfg_pad_i687, fabric_direct2_cfg_pad_i688, fabric_direct2_cfg_pad_i689, fabric_direct2_cfg_pad_i690, fabric_direct2_cfg_pad_i691, fabric_direct2_cfg_pad_i692 -, fabric_direct2_cfg_pad_i693, fabric_direct2_cfg_pad_i694, fabric_direct2_cfg_pad_i695, fabric_direct2_cfg_pad_i696, fabric_direct2_cfg_pad_i697, fabric_direct2_cfg_pad_i698, fabric_direct2_cfg_pad_i699, fabric_direct2_cfg_pad_i700, fabric_direct2_cfg_pad_i701, fabric_direct2_cfg_pad_i702, fabric_direct2_cfg_pad_i703, fabric_direct2_cfg_pad_i704, fabric_direct2_cfg_pad_i705, fabric_direct2_cfg_pad_i706, fabric_direct2_cfg_pad_i707, fabric_direct2_cfg_pad_i708, fabric_direct2_cfg_pad_i709, fabric_direct2_cfg_pad_i710, fabric_direct2_cfg_pad_i711, fabric_direct2_cfg_pad_i712, fabric_direct2_cfg_pad_i713 -, fabric_direct2_cfg_pad_i714, fabric_direct2_cfg_pad_i715, fabric_direct2_cfg_pad_i716, fabric_direct2_cfg_pad_i717, fabric_direct2_cfg_pad_i718, fabric_direct2_cfg_pad_i719, fabric_direct2_cfg_pad_i720, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_clock_fabric_i1, fabric_direct1_clock_fabric_i2, fabric_direct1_clock_fabric_i3, fabric_direct1_clock_fabric_i4, fabric_direct1_oe_i1, fabric_direct1_oe_i2, fabric_direct1_oe_i3, fabric_direct1_oe_i4, fabric_direct1_oe_i5, fabric_direct1_oe_i6, fabric_direct1_oe_i7 -, fabric_direct1_oe_i8, fabric_direct1_oe_i9, fabric_direct1_oe_i10, fabric_direct1_oe_i11, fabric_direct1_oe_i12, fabric_direct1_oe_i13, fabric_direct1_oe_i14, fabric_direct1_oe_i15, fabric_direct1_oe_i16, fabric_direct1_oe_ena_i1, fabric_direct1_oe_ena_i2, fabric_direct1_oe_ena_i3, fabric_direct1_oe_ena_i4, fabric_direct1_oe_ena_i5, fabric_direct1_oe_ena_i6, fabric_direct1_oe_ena_i7, fabric_direct1_oe_ena_i8, fabric_direct1_oe_ena_i9, fabric_direct1_oe_ena_i10, fabric_direct1_oe_ena_i11, fabric_direct1_oe_ena_i12 -, fabric_direct1_oe_ena_i13, fabric_direct1_oe_ena_i14, fabric_direct1_oe_ena_i15, fabric_direct1_oe_ena_i16, fabric_direct1_oe_rs_i1, fabric_direct1_oe_rs_i2, fabric_direct1_oe_rs_i3, fabric_direct1_oe_rs_i4, fabric_direct1_oe_rs_i5, fabric_direct1_oe_rs_i6, fabric_direct1_oe_rs_i7, fabric_direct1_oe_rs_i8, fabric_direct1_oe_rs_i9, fabric_direct1_oe_rs_i10, fabric_direct1_oe_rs_i11, fabric_direct1_oe_rs_i12, fabric_direct1_oe_rs_i13, fabric_direct1_oe_rs_i14, fabric_direct1_oe_rs_i15, fabric_direct1_oe_rs_i16, fabric_direct1_do_i1 -, fabric_direct1_do_i2, fabric_direct1_do_i3, fabric_direct1_do_i4, fabric_direct1_do_i5, fabric_direct1_do_i6, fabric_direct1_do_i7, fabric_direct1_do_i8, fabric_direct1_do_i9, fabric_direct1_do_i10, fabric_direct1_do_i11, fabric_direct1_do_i12, fabric_direct1_do_i13, fabric_direct1_do_i14, fabric_direct1_do_i15, fabric_direct1_do_i16, fabric_direct1_do_ena_i1, fabric_direct1_do_ena_i2, fabric_direct1_do_ena_i3, fabric_direct1_do_ena_i4, fabric_direct1_do_ena_i5, fabric_direct1_do_ena_i6 -, fabric_direct1_do_ena_i7, fabric_direct1_do_ena_i8, fabric_direct1_do_ena_i9, fabric_direct1_do_ena_i10, fabric_direct1_do_ena_i11, fabric_direct1_do_ena_i12, fabric_direct1_do_ena_i13, fabric_direct1_do_ena_i14, fabric_direct1_do_ena_i15, fabric_direct1_do_ena_i16, fabric_direct1_do_rs_i1, fabric_direct1_do_rs_i2, fabric_direct1_do_rs_i3, fabric_direct1_do_rs_i4, fabric_direct1_do_rs_i5, fabric_direct1_do_rs_i6, fabric_direct1_do_rs_i7, fabric_direct1_do_rs_i8, fabric_direct1_do_rs_i9, fabric_direct1_do_rs_i10, fabric_direct1_do_rs_i11 -, fabric_direct1_do_rs_i12, fabric_direct1_do_rs_i13, fabric_direct1_do_rs_i14, fabric_direct1_do_rs_i15, fabric_direct1_do_rs_i16, fabric_direct1_di_o1, fabric_direct1_di_o2, fabric_direct1_di_o3, fabric_direct1_di_o4, fabric_direct1_di_o5, fabric_direct1_di_o6, fabric_direct1_di_o7, fabric_direct1_di_o8, fabric_direct1_di_o9, fabric_direct1_di_o10, fabric_direct1_di_o11, fabric_direct1_di_o12, fabric_direct1_di_o13, fabric_direct1_di_o14, fabric_direct1_di_o15, fabric_direct1_di_o16 -, fabric_direct1_di_ena_i1, fabric_direct1_di_ena_i2, fabric_direct1_di_ena_i3, fabric_direct1_di_ena_i4, fabric_direct1_di_ena_i5, fabric_direct1_di_ena_i6, fabric_direct1_di_ena_i7, fabric_direct1_di_ena_i8, fabric_direct1_di_ena_i9, fabric_direct1_di_ena_i10, fabric_direct1_di_ena_i11, fabric_direct1_di_ena_i12, fabric_direct1_di_ena_i13, fabric_direct1_di_ena_i14, fabric_direct1_di_ena_i15, fabric_direct1_di_ena_i16, fabric_direct1_di_rs_i1, fabric_direct1_di_rs_i2, fabric_direct1_di_rs_i3, fabric_direct1_di_rs_i4, fabric_direct1_di_rs_i5 -, fabric_direct1_di_rs_i6, fabric_direct1_di_rs_i7, fabric_direct1_di_rs_i8, fabric_direct1_di_rs_i9, fabric_direct1_di_rs_i10, fabric_direct1_di_rs_i11, fabric_direct1_di_rs_i12, fabric_direct1_di_rs_i13, fabric_direct1_di_rs_i14, fabric_direct1_di_rs_i15, fabric_direct1_di_rs_i16, fabric_direct1_cfg_bank_i1, fabric_direct1_cfg_bank_i2, fabric_direct1_cfg_bank_i3, fabric_direct1_cfg_bank_i4, fabric_direct1_cfg_pad_i1, fabric_direct1_cfg_pad_i2, fabric_direct1_cfg_pad_i3, fabric_direct1_cfg_pad_i4, fabric_direct1_cfg_pad_i5, fabric_direct1_cfg_pad_i6 -, fabric_direct1_cfg_pad_i7, fabric_direct1_cfg_pad_i8, fabric_direct1_cfg_pad_i9, fabric_direct1_cfg_pad_i10, fabric_direct1_cfg_pad_i11, fabric_direct1_cfg_pad_i12, fabric_direct1_cfg_pad_i13, fabric_direct1_cfg_pad_i14, fabric_direct1_cfg_pad_i15, fabric_direct1_cfg_pad_i16, fabric_direct1_cfg_pad_i17, fabric_direct1_cfg_pad_i18, fabric_direct1_cfg_pad_i19, fabric_direct1_cfg_pad_i20, fabric_direct1_cfg_pad_i21, fabric_direct1_cfg_pad_i22, fabric_direct1_cfg_pad_i23, fabric_direct1_cfg_pad_i24, fabric_direct1_cfg_pad_i25, fabric_direct1_cfg_pad_i26, fabric_direct1_cfg_pad_i27 -, fabric_direct1_cfg_pad_i28, fabric_direct1_cfg_pad_i29, fabric_direct1_cfg_pad_i30, fabric_direct1_cfg_pad_i31, fabric_direct1_cfg_pad_i32, fabric_direct1_cfg_pad_i33, fabric_direct1_cfg_pad_i34, fabric_direct1_cfg_pad_i35, fabric_direct1_cfg_pad_i36, fabric_direct1_cfg_pad_i37, fabric_direct1_cfg_pad_i38, fabric_direct1_cfg_pad_i39, fabric_direct1_cfg_pad_i40, fabric_direct1_cfg_pad_i41, fabric_direct1_cfg_pad_i42, fabric_direct1_cfg_pad_i43, fabric_direct1_cfg_pad_i44, fabric_direct1_cfg_pad_i45, fabric_direct1_cfg_pad_i46, fabric_direct1_cfg_pad_i47, fabric_direct1_cfg_pad_i48 -, fabric_direct1_cfg_pad_i49, fabric_direct1_cfg_pad_i50, fabric_direct1_cfg_pad_i51, fabric_direct1_cfg_pad_i52, fabric_direct1_cfg_pad_i53, fabric_direct1_cfg_pad_i54, fabric_direct1_cfg_pad_i55, fabric_direct1_cfg_pad_i56, fabric_direct1_cfg_pad_i57, fabric_direct1_cfg_pad_i58, fabric_direct1_cfg_pad_i59, fabric_direct1_cfg_pad_i60, fabric_direct1_cfg_pad_i61, fabric_direct1_cfg_pad_i62, fabric_direct1_cfg_pad_i63, fabric_direct1_cfg_pad_i64, fabric_direct1_cfg_pad_i65, fabric_direct1_cfg_pad_i66, fabric_direct1_cfg_pad_i67, fabric_direct1_cfg_pad_i68, fabric_direct1_cfg_pad_i69 -, fabric_direct1_cfg_pad_i70, fabric_direct1_cfg_pad_i71, fabric_direct1_cfg_pad_i72, fabric_direct1_cfg_pad_i73, fabric_direct1_cfg_pad_i74, fabric_direct1_cfg_pad_i75, fabric_direct1_cfg_pad_i76, fabric_direct1_cfg_pad_i77, fabric_direct1_cfg_pad_i78, fabric_direct1_cfg_pad_i79, fabric_direct1_cfg_pad_i80, fabric_direct1_cfg_pad_i81, fabric_direct1_cfg_pad_i82, fabric_direct1_cfg_pad_i83, fabric_direct1_cfg_pad_i84, fabric_direct1_cfg_pad_i85, fabric_direct1_cfg_pad_i86, fabric_direct1_cfg_pad_i87, fabric_direct1_cfg_pad_i88, fabric_direct1_cfg_pad_i89, fabric_direct1_cfg_pad_i90 -, fabric_direct1_cfg_pad_i91, fabric_direct1_cfg_pad_i92, fabric_direct1_cfg_pad_i93, fabric_direct1_cfg_pad_i94, fabric_direct1_cfg_pad_i95, fabric_direct1_cfg_pad_i96, fabric_direct1_cfg_pad_i97, fabric_direct1_cfg_pad_i98, fabric_direct1_cfg_pad_i99, fabric_direct1_cfg_pad_i100, fabric_direct1_cfg_pad_i101, fabric_direct1_cfg_pad_i102, fabric_direct1_cfg_pad_i103, fabric_direct1_cfg_pad_i104, fabric_direct1_cfg_pad_i105, fabric_direct1_cfg_pad_i106, fabric_direct1_cfg_pad_i107, fabric_direct1_cfg_pad_i108, fabric_direct1_cfg_pad_i109, fabric_direct1_cfg_pad_i110, fabric_direct1_cfg_pad_i111 -, fabric_direct1_cfg_pad_i112, fabric_direct1_cfg_pad_i113, fabric_direct1_cfg_pad_i114, fabric_direct1_cfg_pad_i115, fabric_direct1_cfg_pad_i116, fabric_direct1_cfg_pad_i117, fabric_direct1_cfg_pad_i118, fabric_direct1_cfg_pad_i119, fabric_direct1_cfg_pad_i120, fabric_direct1_cfg_pad_i121, fabric_direct1_cfg_pad_i122, fabric_direct1_cfg_pad_i123, fabric_direct1_cfg_pad_i124, fabric_direct1_cfg_pad_i125, fabric_direct1_cfg_pad_i126, fabric_direct1_cfg_pad_i127, fabric_direct1_cfg_pad_i128, fabric_direct1_cfg_pad_i129, fabric_direct1_cfg_pad_i130, fabric_direct1_cfg_pad_i131, fabric_direct1_cfg_pad_i132 -, fabric_direct1_cfg_pad_i133, fabric_direct1_cfg_pad_i134, fabric_direct1_cfg_pad_i135, fabric_direct1_cfg_pad_i136, fabric_direct1_cfg_pad_i137, fabric_direct1_cfg_pad_i138, fabric_direct1_cfg_pad_i139, fabric_direct1_cfg_pad_i140, fabric_direct1_cfg_pad_i141, fabric_direct1_cfg_pad_i142, fabric_direct1_cfg_pad_i143, fabric_direct1_cfg_pad_i144, fabric_direct1_cfg_pad_i145, fabric_direct1_cfg_pad_i146, fabric_direct1_cfg_pad_i147, fabric_direct1_cfg_pad_i148, fabric_direct1_cfg_pad_i149, fabric_direct1_cfg_pad_i150, fabric_direct1_cfg_pad_i151, fabric_direct1_cfg_pad_i152, fabric_direct1_cfg_pad_i153 -, fabric_direct1_cfg_pad_i154, fabric_direct1_cfg_pad_i155, fabric_direct1_cfg_pad_i156, fabric_direct1_cfg_pad_i157, fabric_direct1_cfg_pad_i158, fabric_direct1_cfg_pad_i159, fabric_direct1_cfg_pad_i160, fabric_direct1_cfg_pad_i161, fabric_direct1_cfg_pad_i162, fabric_direct1_cfg_pad_i163, fabric_direct1_cfg_pad_i164, fabric_direct1_cfg_pad_i165, fabric_direct1_cfg_pad_i166, fabric_direct1_cfg_pad_i167, fabric_direct1_cfg_pad_i168, fabric_direct1_cfg_pad_i169, fabric_direct1_cfg_pad_i170, fabric_direct1_cfg_pad_i171, fabric_direct1_cfg_pad_i172, fabric_direct1_cfg_pad_i173, fabric_direct1_cfg_pad_i174 -, fabric_direct1_cfg_pad_i175, fabric_direct1_cfg_pad_i176, fabric_direct1_cfg_pad_i177, fabric_direct1_cfg_pad_i178, fabric_direct1_cfg_pad_i179, fabric_direct1_cfg_pad_i180, fabric_direct1_cfg_pad_i181, fabric_direct1_cfg_pad_i182, fabric_direct1_cfg_pad_i183, fabric_direct1_cfg_pad_i184, fabric_direct1_cfg_pad_i185, fabric_direct1_cfg_pad_i186, fabric_direct1_cfg_pad_i187, fabric_direct1_cfg_pad_i188, fabric_direct1_cfg_pad_i189, fabric_direct1_cfg_pad_i190, fabric_direct1_cfg_pad_i191, fabric_direct1_cfg_pad_i192, fabric_direct1_cfg_pad_i193, fabric_direct1_cfg_pad_i194, fabric_direct1_cfg_pad_i195 -, fabric_direct1_cfg_pad_i196, fabric_direct1_cfg_pad_i197, fabric_direct1_cfg_pad_i198, fabric_direct1_cfg_pad_i199, fabric_direct1_cfg_pad_i200, fabric_direct1_cfg_pad_i201, fabric_direct1_cfg_pad_i202, fabric_direct1_cfg_pad_i203, fabric_direct1_cfg_pad_i204, fabric_direct1_cfg_pad_i205, fabric_direct1_cfg_pad_i206, fabric_direct1_cfg_pad_i207, fabric_direct1_cfg_pad_i208, fabric_direct1_cfg_pad_i209, fabric_direct1_cfg_pad_i210, fabric_direct1_cfg_pad_i211, fabric_direct1_cfg_pad_i212, fabric_direct1_cfg_pad_i213, fabric_direct1_cfg_pad_i214, fabric_direct1_cfg_pad_i215, fabric_direct1_cfg_pad_i216 -, fabric_direct1_cfg_pad_i217, fabric_direct1_cfg_pad_i218, fabric_direct1_cfg_pad_i219, fabric_direct1_cfg_pad_i220, fabric_direct1_cfg_pad_i221, fabric_direct1_cfg_pad_i222, fabric_direct1_cfg_pad_i223, fabric_direct1_cfg_pad_i224, fabric_direct1_cfg_pad_i225, fabric_direct1_cfg_pad_i226, fabric_direct1_cfg_pad_i227, fabric_direct1_cfg_pad_i228, fabric_direct1_cfg_pad_i229, fabric_direct1_cfg_pad_i230, fabric_direct1_cfg_pad_i231, fabric_direct1_cfg_pad_i232, fabric_direct1_cfg_pad_i233, fabric_direct1_cfg_pad_i234, fabric_direct1_cfg_pad_i235, fabric_direct1_cfg_pad_i236, fabric_direct1_cfg_pad_i237 -, fabric_direct1_cfg_pad_i238, fabric_direct1_cfg_pad_i239, fabric_direct1_cfg_pad_i240, fabric_direct1_cfg_pad_i241, fabric_direct1_cfg_pad_i242, fabric_direct1_cfg_pad_i243, fabric_direct1_cfg_pad_i244, fabric_direct1_cfg_pad_i245, fabric_direct1_cfg_pad_i246, fabric_direct1_cfg_pad_i247, fabric_direct1_cfg_pad_i248, fabric_direct1_cfg_pad_i249, fabric_direct1_cfg_pad_i250, fabric_direct1_cfg_pad_i251, fabric_direct1_cfg_pad_i252, fabric_direct1_cfg_pad_i253, fabric_direct1_cfg_pad_i254, fabric_direct1_cfg_pad_i255, fabric_direct1_cfg_pad_i256, fabric_direct1_cfg_pad_i257, fabric_direct1_cfg_pad_i258 -, fabric_direct1_cfg_pad_i259, fabric_direct1_cfg_pad_i260, fabric_direct1_cfg_pad_i261, fabric_direct1_cfg_pad_i262, fabric_direct1_cfg_pad_i263, fabric_direct1_cfg_pad_i264, fabric_direct1_cfg_pad_i265, fabric_direct1_cfg_pad_i266, fabric_direct1_cfg_pad_i267, fabric_direct1_cfg_pad_i268, fabric_direct1_cfg_pad_i269, fabric_direct1_cfg_pad_i270, fabric_direct1_cfg_pad_i271, fabric_direct1_cfg_pad_i272, fabric_direct1_cfg_pad_i273, fabric_direct1_cfg_pad_i274, fabric_direct1_cfg_pad_i275, fabric_direct1_cfg_pad_i276, fabric_direct1_cfg_pad_i277, fabric_direct1_cfg_pad_i278, fabric_direct1_cfg_pad_i279 -, fabric_direct1_cfg_pad_i280, fabric_direct1_cfg_pad_i281, fabric_direct1_cfg_pad_i282, fabric_direct1_cfg_pad_i283, fabric_direct1_cfg_pad_i284, fabric_direct1_cfg_pad_i285, fabric_direct1_cfg_pad_i286, fabric_direct1_cfg_pad_i287, fabric_direct1_cfg_pad_i288, fabric_direct1_cfg_pad_i289, fabric_direct1_cfg_pad_i290, fabric_direct1_cfg_pad_i291, fabric_direct1_cfg_pad_i292, fabric_direct1_cfg_pad_i293, fabric_direct1_cfg_pad_i294, fabric_direct1_cfg_pad_i295, fabric_direct1_cfg_pad_i296, fabric_direct1_cfg_pad_i297, fabric_direct1_cfg_pad_i298, fabric_direct1_cfg_pad_i299, fabric_direct1_cfg_pad_i300 -, fabric_direct1_cfg_pad_i301, fabric_direct1_cfg_pad_i302, fabric_direct1_cfg_pad_i303, fabric_direct1_cfg_pad_i304, fabric_direct1_cfg_pad_i305, fabric_direct1_cfg_pad_i306, fabric_direct1_cfg_pad_i307, fabric_direct1_cfg_pad_i308, fabric_direct1_cfg_pad_i309, fabric_direct1_cfg_pad_i310, fabric_direct1_cfg_pad_i311, fabric_direct1_cfg_pad_i312, fabric_direct1_cfg_pad_i313, fabric_direct1_cfg_pad_i314, fabric_direct1_cfg_pad_i315, fabric_direct1_cfg_pad_i316, fabric_direct1_cfg_pad_i317, fabric_direct1_cfg_pad_i318, fabric_direct1_cfg_pad_i319, fabric_direct1_cfg_pad_i320, fabric_direct1_cfg_pad_i321 -, fabric_direct1_cfg_pad_i322, fabric_direct1_cfg_pad_i323, fabric_direct1_cfg_pad_i324, fabric_direct1_cfg_pad_i325, fabric_direct1_cfg_pad_i326, fabric_direct1_cfg_pad_i327, fabric_direct1_cfg_pad_i328, fabric_direct1_cfg_pad_i329, fabric_direct1_cfg_pad_i330, fabric_direct1_cfg_pad_i331, fabric_direct1_cfg_pad_i332, fabric_direct1_cfg_pad_i333, fabric_direct1_cfg_pad_i334, fabric_direct1_cfg_pad_i335, fabric_direct1_cfg_pad_i336, fabric_direct1_cfg_pad_i337, fabric_direct1_cfg_pad_i338, fabric_direct1_cfg_pad_i339, fabric_direct1_cfg_pad_i340, fabric_direct1_cfg_pad_i341, fabric_direct1_cfg_pad_i342 -, fabric_direct1_cfg_pad_i343, fabric_direct1_cfg_pad_i344, fabric_direct1_cfg_pad_i345, fabric_direct1_cfg_pad_i346, fabric_direct1_cfg_pad_i347, fabric_direct1_cfg_pad_i348, fabric_direct1_cfg_pad_i349, fabric_direct1_cfg_pad_i350, fabric_direct1_cfg_pad_i351, fabric_direct1_cfg_pad_i352, fabric_direct1_cfg_pad_i353, fabric_direct1_cfg_pad_i354, fabric_direct1_cfg_pad_i355, fabric_direct1_cfg_pad_i356, fabric_direct1_cfg_pad_i357, fabric_direct1_cfg_pad_i358, fabric_direct1_cfg_pad_i359, fabric_direct1_cfg_pad_i360, fabric_direct1_cfg_pad_i361, fabric_direct1_cfg_pad_i362, fabric_direct1_cfg_pad_i363 -, fabric_direct1_cfg_pad_i364, fabric_direct1_cfg_pad_i365, fabric_direct1_cfg_pad_i366, fabric_direct1_cfg_pad_i367, fabric_direct1_cfg_pad_i368, fabric_direct1_cfg_pad_i369, fabric_direct1_cfg_pad_i370, fabric_direct1_cfg_pad_i371, fabric_direct1_cfg_pad_i372, fabric_direct1_cfg_pad_i373, fabric_direct1_cfg_pad_i374, fabric_direct1_cfg_pad_i375, fabric_direct1_cfg_pad_i376, fabric_direct1_cfg_pad_i377, fabric_direct1_cfg_pad_i378, fabric_direct1_cfg_pad_i379, fabric_direct1_cfg_pad_i380, fabric_direct1_cfg_pad_i381, fabric_direct1_cfg_pad_i382, fabric_direct1_cfg_pad_i383, fabric_direct1_cfg_pad_i384 -, fabric_direct1_cfg_pad_i385, fabric_direct1_cfg_pad_i386, fabric_direct1_cfg_pad_i387, fabric_direct1_cfg_pad_i388, fabric_direct1_cfg_pad_i389, fabric_direct1_cfg_pad_i390, fabric_direct1_cfg_pad_i391, fabric_direct1_cfg_pad_i392, fabric_direct1_cfg_pad_i393, fabric_direct1_cfg_pad_i394, fabric_direct1_cfg_pad_i395, fabric_direct1_cfg_pad_i396, fabric_direct1_cfg_pad_i397, fabric_direct1_cfg_pad_i398, fabric_direct1_cfg_pad_i399, fabric_direct1_cfg_pad_i400, fabric_direct1_cfg_pad_i401, fabric_direct1_cfg_pad_i402, fabric_direct1_cfg_pad_i403, fabric_direct1_cfg_pad_i404, fabric_direct1_cfg_pad_i405 -, fabric_direct1_cfg_pad_i406, fabric_direct1_cfg_pad_i407, fabric_direct1_cfg_pad_i408, fabric_direct1_cfg_pad_i409, fabric_direct1_cfg_pad_i410, fabric_direct1_cfg_pad_i411, fabric_direct1_cfg_pad_i412, fabric_direct1_cfg_pad_i413, fabric_direct1_cfg_pad_i414, fabric_direct1_cfg_pad_i415, fabric_direct1_cfg_pad_i416, fabric_direct1_cfg_pad_i417, fabric_direct1_cfg_pad_i418, fabric_direct1_cfg_pad_i419, fabric_direct1_cfg_pad_i420, fabric_direct1_cfg_pad_i421, fabric_direct1_cfg_pad_i422, fabric_direct1_cfg_pad_i423, fabric_direct1_cfg_pad_i424, fabric_direct1_cfg_pad_i425, fabric_direct1_cfg_pad_i426 -, fabric_direct1_cfg_pad_i427, fabric_direct1_cfg_pad_i428, fabric_direct1_cfg_pad_i429, fabric_direct1_cfg_pad_i430, fabric_direct1_cfg_pad_i431, fabric_direct1_cfg_pad_i432, fabric_direct1_cfg_pad_i433, fabric_direct1_cfg_pad_i434, fabric_direct1_cfg_pad_i435, fabric_direct1_cfg_pad_i436, fabric_direct1_cfg_pad_i437, fabric_direct1_cfg_pad_i438, fabric_direct1_cfg_pad_i439, fabric_direct1_cfg_pad_i440, fabric_direct1_cfg_pad_i441, fabric_direct1_cfg_pad_i442, fabric_direct1_cfg_pad_i443, fabric_direct1_cfg_pad_i444, fabric_direct1_cfg_pad_i445, fabric_direct1_cfg_pad_i446, fabric_direct1_cfg_pad_i447 -, fabric_direct1_cfg_pad_i448, fabric_direct1_cfg_pad_i449, fabric_direct1_cfg_pad_i450, fabric_direct1_cfg_pad_i451, fabric_direct1_cfg_pad_i452, fabric_direct1_cfg_pad_i453, fabric_direct1_cfg_pad_i454, fabric_direct1_cfg_pad_i455, fabric_direct1_cfg_pad_i456, fabric_direct1_cfg_pad_i457, fabric_direct1_cfg_pad_i458, fabric_direct1_cfg_pad_i459, fabric_direct1_cfg_pad_i460, fabric_direct1_cfg_pad_i461, fabric_direct1_cfg_pad_i462, fabric_direct1_cfg_pad_i463, fabric_direct1_cfg_pad_i464, fabric_direct1_cfg_pad_i465, fabric_direct1_cfg_pad_i466, fabric_direct1_cfg_pad_i467, fabric_direct1_cfg_pad_i468 -, fabric_direct1_cfg_pad_i469, fabric_direct1_cfg_pad_i470, fabric_direct1_cfg_pad_i471, fabric_direct1_cfg_pad_i472, fabric_direct1_cfg_pad_i473, fabric_direct1_cfg_pad_i474, fabric_direct1_cfg_pad_i475, fabric_direct1_cfg_pad_i476, fabric_direct1_cfg_pad_i477, fabric_direct1_cfg_pad_i478, fabric_direct1_cfg_pad_i479, fabric_direct1_cfg_pad_i480, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_arst_tmr_n_i1, fabric_thsens_arst_tmr_n_i2, fabric_thsens_arst_tmr_n_i3, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_w_i1 -, fabric_thsens_fm_mode_w_i2, fabric_thsens_fm_mode_w_i3, fabric_thsens_fm_mode_w_i4, fabric_thsens_fm_mode_w_i5, fabric_thsens_fm_mode_w_i6, fabric_thsens_fm_mode_w_i7, fabric_thsens_fm_mode_w_i8, fabric_thsens_fm_mode_w_i9, fabric_thsens_fm_mode_w_i10, fabric_thsens_fm_mode_w_i11, fabric_thsens_fm_mode_w_i12, fabric_thsens_fm_mode_w_i13, fabric_thsens_fm_mode_w_i14, fabric_thsens_fm_mode_w_i15, fabric_thsens_fm_mode_w_i16, fabric_thsens_fm_mode_w_i17, fabric_thsens_fm_mode_w_i18, fabric_thsens_fm_mode_w_i19, fabric_thsens_fm_mode_w_i20, fabric_thsens_fm_mode_w_i21, fabric_thsens_fm_mode_w_i22 -, fabric_thsens_fm_mode_w_i23, fabric_thsens_fm_mode_w_i24, fabric_thsens_fm_mode_w_i25, fabric_thsens_fm_mode_w_i26, fabric_thsens_fm_mode_w_i27, fabric_thsens_fm_mode_w_i28, fabric_thsens_fm_mode_w_i29, fabric_thsens_fm_mode_w_i30, fabric_thsens_fm_mode_w_i31, fabric_thsens_fm_mode_w_i32, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_w_i1, fabric_thsens_fm_config_w_i2, fabric_thsens_fm_config_w_i3, fabric_thsens_fm_config_w_i4, fabric_thsens_fm_config_w_i5, fabric_thsens_fm_config_w_i6, fabric_thsens_fm_config_w_i7, fabric_thsens_fm_config_w_i8, fabric_thsens_fm_config_w_i9, fabric_thsens_fm_config_w_i10 -, fabric_thsens_fm_config_w_i11, fabric_thsens_fm_config_w_i12, fabric_thsens_fm_config_w_i13, fabric_thsens_fm_config_w_i14, fabric_thsens_fm_config_w_i15, fabric_thsens_fm_config_w_i16, fabric_thsens_fm_config_w_i17, fabric_thsens_fm_config_w_i18, fabric_thsens_fm_config_w_i19, fabric_thsens_fm_config_w_i20, fabric_thsens_fm_config_w_i21, fabric_thsens_fm_config_w_i22, fabric_thsens_fm_config_w_i23, fabric_thsens_fm_config_w_i24, fabric_thsens_fm_config_w_i25, fabric_thsens_fm_config_w_i26, fabric_thsens_fm_config_w_i27, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_data_o1, fabric_thsens_fm_data_o2, fabric_thsens_fm_data_o3 -, fabric_thsens_fm_data_o4, fabric_thsens_fm_data_o5, fabric_thsens_fm_data_o6, fabric_thsens_fm_data_o7, fabric_thsens_fm_data_o8, fabric_thsens_fm_data_o9, fabric_thsens_fm_data_o10, fabric_thsens_fm_data_o11, fabric_thsens_fm_data_o12, fabric_thsens_fm_data_o13, fabric_thsens_fm_data_o14, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_fm_mode_r_o1, fabric_thsens_fm_mode_r_o2, fabric_thsens_fm_mode_r_o3, fabric_thsens_fm_mode_r_o4, fabric_thsens_fm_mode_r_o5, fabric_thsens_fm_mode_r_o6, fabric_thsens_fm_mode_r_o7, fabric_thsens_fm_mode_r_o8 -, fabric_thsens_fm_mode_r_o9, fabric_thsens_fm_mode_r_o10, fabric_thsens_fm_mode_r_o11, fabric_thsens_fm_mode_r_o12, fabric_thsens_fm_mode_r_o13, fabric_thsens_fm_mode_r_o14, fabric_thsens_fm_mode_r_o15, fabric_thsens_fm_mode_r_o16, fabric_thsens_fm_mode_r_o17, fabric_thsens_fm_mode_r_o18, fabric_thsens_fm_mode_r_o19, fabric_thsens_fm_mode_r_o20, fabric_thsens_fm_mode_r_o21, fabric_thsens_fm_mode_r_o22, fabric_thsens_fm_mode_r_o23, fabric_thsens_fm_mode_r_o24, fabric_thsens_fm_mode_r_o25, fabric_thsens_fm_mode_r_o26, fabric_thsens_fm_mode_r_o27, fabric_thsens_fm_mode_r_o28, fabric_thsens_fm_mode_r_o29 -, fabric_thsens_fm_mode_r_o30, fabric_thsens_fm_mode_r_o31, fabric_thsens_fm_mode_r_o32, fabric_thsens_fm_config_r_o1, fabric_thsens_fm_config_r_o2, fabric_thsens_fm_config_r_o3, fabric_thsens_fm_config_r_o4, fabric_thsens_fm_config_r_o5, fabric_thsens_fm_config_r_o6, fabric_thsens_fm_config_r_o7, fabric_thsens_fm_config_r_o8, fabric_thsens_fm_config_r_o9, fabric_thsens_fm_config_r_o10, fabric_thsens_fm_config_r_o11, fabric_thsens_fm_config_r_o12, fabric_thsens_fm_config_r_o13, fabric_thsens_fm_config_r_o14, fabric_thsens_fm_config_r_o15, fabric_thsens_fm_config_r_o16, fabric_thsens_fm_config_r_o17, fabric_thsens_fm_config_r_o18 -, fabric_thsens_fm_config_r_o19, fabric_thsens_fm_config_r_o20, fabric_thsens_fm_config_r_o21, fabric_thsens_fm_config_r_o22, fabric_thsens_fm_config_r_o23, fabric_thsens_fm_config_r_o24, fabric_thsens_fm_config_r_o25, fabric_thsens_fm_config_r_o26, fabric_thsens_fm_config_r_o27, fabric_thsens_clk_div_ratio_i1, fabric_thsens_clk_div_ratio_i2, fabric_thsens_clk_div_ratio_i3, fabric_thsens_clk_div_ratio_i4, fabric_thsens_clk_div_ratio_i5, fabric_thsens_clk_div_ratio_i6, fabric_thsens_clk_div_ratio_i7, fabric_thsens_clk_div_ratio_i8, fabric_thsens_tst_scanenable_i, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o -, fabric_thsens_tst_scanout2_o, fabric_thsens_otp_config_o1, fabric_thsens_otp_config_o2, fabric_thsens_otp_config_o3, fabric_thsens_otp_config_o4, fabric_thsens_otp_config_o5, fabric_thsens_otp_config_o6, fabric_thsens_otp_config_o7, fabric_thsens_otp_config_o8, fabric_thsens_otp_config_o9, fabric_thsens_otp_config_o10, fabric_thsens_otp_config_o11, fabric_thsens_otp_config_o12, fabric_thsens_otp_config_o13, fabric_thsens_otp_config_o14, fabric_thsens_otp_config_o15, fabric_thsens_otp_config_o16, fabric_thsens_otp_config_o17, fabric_thsens_otp_config_o18, fabric_thsens_otp_config_o19, fabric_thsens_otp_config_o20 -, fabric_thsens_otp_config_o21, fabric_thsens_otp_config_o22, fabric_thsens_otp_config_o23, fabric_thsens_otp_config_o24, fabric_thsens_otp_config_o25, fabric_thsens_otp_config_o26, fabric_thsens_otp_config_o27, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spi_needed_i1, fabric_spi_needed_i2, fabric_spi_needed_i3, fabric_spi_bsm_release_o1, fabric_spi_bsm_release_o2, fabric_spi_bsm_release_o3, fabric_spi_arst_tmr_n_i1, fabric_spi_arst_tmr_n_i2 -, fabric_spi_arst_tmr_n_i3, fabric_spi_arst_tmr_n_i4, fabric_spi_arst_tmr_n_i5, fabric_spi_arst_tmr_n_i6, fabric_spi_arst_tmr_n_i7, fabric_spi_arst_tmr_n_i8, fabric_spi_arst_tmr_n_i9, fabric_spi_fifo_arst_tmr_n_i1, fabric_spi_fifo_arst_tmr_n_i2, fabric_spi_fifo_arst_tmr_n_i3, fabric_spi_fifo_arst_tmr_n_i4, fabric_spi_fifo_arst_tmr_n_i5, fabric_spi_fifo_arst_tmr_n_i6, fabric_spi_fifo_arst_tmr_n_i7, fabric_spi_fifo_arst_tmr_n_i8, fabric_spi_fifo_arst_tmr_n_i9, fabric_spi_cpol_i1, fabric_spi_cpol_i2, fabric_spi_cpol_i3, fabric_spi_cpha_i1, fabric_spi_cpha_i2 -, fabric_spi_cpha_i3, fabric_spi_loopback_i1, fabric_spi_loopback_i2, fabric_spi_loopback_i3, fabric_spi_lsb_first_i1, fabric_spi_lsb_first_i2, fabric_spi_lsb_first_i3, fabric_spi_cs_setuptime_i1, fabric_spi_cs_setuptime_i2, fabric_spi_cs_setuptime_i3, fabric_spi_cs_setuptime_i4, fabric_spi_cs_setuptime_i5, fabric_spi_cs_setuptime_i6, fabric_spi_cs_setuptime_i7, fabric_spi_cs_setuptime_i8, fabric_spi_cs_setuptime_i9, fabric_spi_cs_setuptime_i10, fabric_spi_cs_setuptime_i11, fabric_spi_cs_setuptime_i12, fabric_spi_cs_holdtime_i1, fabric_spi_cs_holdtime_i2 -, fabric_spi_cs_holdtime_i3, fabric_spi_cs_holdtime_i4, fabric_spi_cs_holdtime_i5, fabric_spi_cs_holdtime_i6, fabric_spi_cs_holdtime_i7, fabric_spi_cs_holdtime_i8, fabric_spi_cs_holdtime_i9, fabric_spi_cs_holdtime_i10, fabric_spi_cs_holdtime_i11, fabric_spi_cs_holdtime_i12, fabric_spi_cs_offtime_i1, fabric_spi_cs_offtime_i2, fabric_spi_cs_offtime_i3, fabric_spi_cs_offtime_i4, fabric_spi_cs_offtime_i5, fabric_spi_cs_offtime_i6, fabric_spi_cs_offtime_i7, fabric_spi_cs_offtime_i8, fabric_spi_cs_offtime_i9, fabric_spi_cs_offtime_i10, fabric_spi_cs_offtime_i11 -, fabric_spi_cs_offtime_i12, fabric_spi_vcc_enable_i1, fabric_spi_vcc_enable_i2, fabric_spi_vcc_enable_i3, fabric_spi_powerdown_cycle_i1, fabric_spi_powerdown_cycle_i2, fabric_spi_powerdown_cycle_i3, fabric_spi_powerdown_cycle_i4, fabric_spi_powerdown_cycle_i5, fabric_spi_powerdown_cycle_i6, fabric_spi_powerdown_cycle_i7, fabric_spi_powerdown_cycle_i8, fabric_spi_powerdown_cycle_i9, fabric_spi_powerdown_cycle_i10, fabric_spi_powerdown_cycle_i11, fabric_spi_powerdown_cycle_i12, fabric_spi_powerdown_cycle_i13, fabric_spi_powerdown_cycle_i14, fabric_spi_powerdown_cycle_i15, fabric_spi_powerdown_cycle_i16, fabric_spi_powerdown_cycle_i17 -, fabric_spi_powerdown_cycle_i18, fabric_spi_powerdown_cycle_i19, fabric_spi_powerdown_cycle_i20, fabric_spi_powerdown_cycle_i21, fabric_spi_powerdown_cycle_i22, fabric_spi_powerdown_cycle_i23, fabric_spi_powerdown_cycle_i24, fabric_spi_powerdown_cycle_i25, fabric_spi_powerdown_cycle_i26, fabric_spi_powerdown_cycle_i27, fabric_spi_powerdown_cycle_i28, fabric_spi_powerdown_cycle_i29, fabric_spi_powerdown_cycle_i30, fabric_spi_powerdown_cycle_i31, fabric_spi_powerdown_cycle_i32, fabric_spi_powerdown_cycle_i33, fabric_spi_powerdown_cycle_i34, fabric_spi_powerdown_cycle_i35, fabric_spi_powerdown_cycle_i36, fabric_spi_powerdown_cycle_i37, fabric_spi_powerdown_cycle_i38 -, fabric_spi_powerdown_cycle_i39, fabric_spi_powerdown_cycle_i40, fabric_spi_powerdown_cycle_i41, fabric_spi_powerdown_cycle_i42, fabric_spi_powerdown_cycle_i43, fabric_spi_powerdown_cycle_i44, fabric_spi_powerdown_cycle_i45, fabric_spi_powerdown_cycle_i46, fabric_spi_powerdown_cycle_i47, fabric_spi_powerdown_cycle_i48, fabric_spi_powerup_cycle_i1, fabric_spi_powerup_cycle_i2, fabric_spi_powerup_cycle_i3, fabric_spi_powerup_cycle_i4, fabric_spi_powerup_cycle_i5, fabric_spi_powerup_cycle_i6, fabric_spi_powerup_cycle_i7, fabric_spi_powerup_cycle_i8, fabric_spi_powerup_cycle_i9, fabric_spi_powerup_cycle_i10, fabric_spi_powerup_cycle_i11 -, fabric_spi_powerup_cycle_i12, fabric_spi_powerup_cycle_i13, fabric_spi_powerup_cycle_i14, fabric_spi_powerup_cycle_i15, fabric_spi_powerup_cycle_i16, fabric_spi_powerup_cycle_i17, fabric_spi_powerup_cycle_i18, fabric_spi_powerup_cycle_i19, fabric_spi_powerup_cycle_i20, fabric_spi_powerup_cycle_i21, fabric_spi_powerup_cycle_i22, fabric_spi_powerup_cycle_i23, fabric_spi_powerup_cycle_i24, fabric_spi_powerup_cycle_i25, fabric_spi_powerup_cycle_i26, fabric_spi_powerup_cycle_i27, fabric_spi_powerup_cycle_i28, fabric_spi_powerup_cycle_i29, fabric_spi_powerup_cycle_i30, fabric_spi_powerup_cycle_i31, fabric_spi_powerup_cycle_i32 -, fabric_spi_powerup_cycle_i33, fabric_spi_powerup_cycle_i34, fabric_spi_powerup_cycle_i35, fabric_spi_powerup_cycle_i36, fabric_spi_powerup_cycle_i37, fabric_spi_powerup_cycle_i38, fabric_spi_powerup_cycle_i39, fabric_spi_powerup_cycle_i40, fabric_spi_powerup_cycle_i41, fabric_spi_powerup_cycle_i42, fabric_spi_powerup_cycle_i43, fabric_spi_powerup_cycle_i44, fabric_spi_powerup_cycle_i45, fabric_spi_powerup_cycle_i46, fabric_spi_powerup_cycle_i47, fabric_spi_powerup_cycle_i48, fabric_spi_legacy_enable_i1, fabric_spi_legacy_enable_i2, fabric_spi_legacy_enable_i3, fabric_spi_legacy_master_i1, fabric_spi_legacy_master_i2 -, fabric_spi_legacy_master_i3, fabric_spi_data_in_unlimited_i1, fabric_spi_data_in_unlimited_i2, fabric_spi_data_in_unlimited_i3, fabric_spi_enable_i1, fabric_spi_enable_i2, fabric_spi_enable_i3, fabric_spi_rst_n_i1, fabric_spi_rst_n_i2, fabric_spi_rst_n_i3, fabric_spi_init_done_o1, fabric_spi_init_done_o2, fabric_spi_init_done_o3, fabric_spi_busy_o1, fabric_spi_busy_o2, fabric_spi_busy_o3, fabric_spi_vcc_used_o1, fabric_spi_vcc_used_o2, fabric_spi_vcc_used_o3, fabric_spi_error_sel_o1, fabric_spi_error_sel_o2 -, fabric_spi_error_sel_o3, fabric_spi_error_loopback_o1, fabric_spi_error_loopback_o2, fabric_spi_error_loopback_o3, fabric_spi_error_mode_o1, fabric_spi_error_mode_o2, fabric_spi_error_mode_o3, fabric_spi_error_endianness_o1, fabric_spi_error_endianness_o2, fabric_spi_error_endianness_o3, fabric_spi_cmd_push_i1, fabric_spi_cmd_push_i2, fabric_spi_cmd_push_i3, fabric_spi_cmd_full_o1, fabric_spi_cmd_full_o2, fabric_spi_cmd_full_o3, fabric_spi_cmd_type_i1, fabric_spi_cmd_type_i2, fabric_spi_cmd_type_i3, fabric_spi_cmd_type_i4, fabric_spi_cmd_type_i5 -, fabric_spi_cmd_type_i6, fabric_spi_cmd_mode_i1, fabric_spi_cmd_mode_i2, fabric_spi_cmd_mode_i3, fabric_spi_cmd_mode_i4, fabric_spi_cmd_mode_i5, fabric_spi_cmd_mode_i6, fabric_spi_cmd_bytes_i1, fabric_spi_cmd_bytes_i2, fabric_spi_cmd_bytes_i3, fabric_spi_cmd_bytes_i4, fabric_spi_cmd_bytes_i5, fabric_spi_cmd_bytes_i6, fabric_spi_mosi_push_i1, fabric_spi_mosi_push_i2, fabric_spi_mosi_push_i3, fabric_spi_mosi_full_o1, fabric_spi_mosi_full_o2, fabric_spi_mosi_full_o3, fabric_spi_mosi_data_i1, fabric_spi_mosi_data_i2 -, fabric_spi_mosi_data_i3, fabric_spi_mosi_data_i4, fabric_spi_mosi_data_i5, fabric_spi_mosi_data_i6, fabric_spi_mosi_data_i7, fabric_spi_mosi_data_i8, fabric_spi_mosi_data_i9, fabric_spi_mosi_data_i10, fabric_spi_mosi_data_i11, fabric_spi_mosi_data_i12, fabric_spi_mosi_data_i13, fabric_spi_mosi_data_i14, fabric_spi_mosi_data_i15, fabric_spi_mosi_data_i16, fabric_spi_mosi_data_i17, fabric_spi_mosi_data_i18, fabric_spi_mosi_data_i19, fabric_spi_mosi_data_i20, fabric_spi_mosi_data_i21, fabric_spi_mosi_data_i22, fabric_spi_mosi_data_i23 -, fabric_spi_mosi_data_i24, fabric_spi_mosi_data_inv_i1, fabric_spi_mosi_data_inv_i2, fabric_spi_mosi_data_inv_i3, fabric_spi_miso_pop_i1, fabric_spi_miso_pop_i2, fabric_spi_miso_pop_i3, fabric_spi_miso_empty_o1, fabric_spi_miso_empty_o2, fabric_spi_miso_empty_o3, fabric_spi_miso_data_o1, fabric_spi_miso_data_o2, fabric_spi_miso_data_o3, fabric_spi_miso_data_o4, fabric_spi_miso_data_o5, fabric_spi_miso_data_o6, fabric_spi_miso_data_o7, fabric_spi_miso_data_o8, fabric_spi_miso_data_o9, fabric_spi_miso_data_o10, fabric_spi_miso_data_o11 -, fabric_spi_miso_data_o12, fabric_spi_miso_data_o13, fabric_spi_miso_data_o14, fabric_spi_miso_data_o15, fabric_spi_miso_data_o16, fabric_spi_miso_data_o17, fabric_spi_miso_data_o18, fabric_spi_miso_data_o19, fabric_spi_miso_data_o20, fabric_spi_miso_data_o21, fabric_spi_miso_data_o22, fabric_spi_miso_data_o23, fabric_spi_miso_data_o24, fabric_spi_miso_data_inv_o1, fabric_spi_miso_data_inv_o2, fabric_spi_miso_data_inv_o3, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i -, fabric_spw0_tx_fifo_data_i1, fabric_spw0_tx_fifo_data_i2, fabric_spw0_tx_fifo_data_i3, fabric_spw0_tx_fifo_data_i4, fabric_spw0_tx_fifo_data_i5, fabric_spw0_tx_fifo_data_i6, fabric_spw0_tx_fifo_data_i7, fabric_spw0_tx_fifo_data_i8, fabric_spw0_tx_fifo_data_i9, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_rx_fifo_data_o1, fabric_spw0_rx_fifo_data_o2, fabric_spw0_rx_fifo_data_o3, fabric_spw0_rx_fifo_data_o4, fabric_spw0_rx_fifo_data_o5, fabric_spw0_rx_fifo_data_o6, fabric_spw0_rx_fifo_data_o7, fabric_spw0_rx_fifo_data_o8, fabric_spw0_rx_fifo_data_o9 -, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_paddr_i1, fabric_spw0_apb_slv_paddr_i2, fabric_spw0_apb_slv_paddr_i3, fabric_spw0_apb_slv_paddr_i4, fabric_spw0_apb_slv_paddr_i5, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pwdata_i1, fabric_spw0_apb_slv_pwdata_i2, fabric_spw0_apb_slv_pwdata_i3, fabric_spw0_apb_slv_pwdata_i4, fabric_spw0_apb_slv_pwdata_i5, fabric_spw0_apb_slv_pwdata_i6, fabric_spw0_apb_slv_pwdata_i7, fabric_spw0_apb_slv_pwdata_i8, fabric_spw0_apb_slv_pwdata_i9, fabric_spw0_apb_slv_pwdata_i10, fabric_spw0_apb_slv_pwdata_i11 -, fabric_spw0_apb_slv_pwdata_i12, fabric_spw0_apb_slv_pwdata_i13, fabric_spw0_apb_slv_pwdata_i14, fabric_spw0_apb_slv_pwdata_i15, fabric_spw0_apb_slv_pwdata_i16, fabric_spw0_apb_slv_pwdata_i17, fabric_spw0_apb_slv_pwdata_i18, fabric_spw0_apb_slv_pwdata_i19, fabric_spw0_apb_slv_pwdata_i20, fabric_spw0_apb_slv_pwdata_i21, fabric_spw0_apb_slv_pwdata_i22, fabric_spw0_apb_slv_pwdata_i23, fabric_spw0_apb_slv_pwdata_i24, fabric_spw0_apb_slv_pwdata_i25, fabric_spw0_apb_slv_pwdata_i26, fabric_spw0_apb_slv_pwdata_i27, fabric_spw0_apb_slv_pwdata_i28, fabric_spw0_apb_slv_pwdata_i29, fabric_spw0_apb_slv_pwdata_i30, fabric_spw0_apb_slv_pwdata_i31, fabric_spw0_apb_slv_prdata_o1 -, fabric_spw0_apb_slv_prdata_o2, fabric_spw0_apb_slv_prdata_o3, fabric_spw0_apb_slv_prdata_o4, fabric_spw0_apb_slv_prdata_o5, fabric_spw0_apb_slv_prdata_o6, fabric_spw0_apb_slv_prdata_o7, fabric_spw0_apb_slv_prdata_o8, fabric_spw0_apb_slv_prdata_o9, fabric_spw0_apb_slv_prdata_o10, fabric_spw0_apb_slv_prdata_o11, fabric_spw0_apb_slv_prdata_o12, fabric_spw0_apb_slv_prdata_o13, fabric_spw0_apb_slv_prdata_o14, fabric_spw0_apb_slv_prdata_o15, fabric_spw0_apb_slv_prdata_o16, fabric_spw0_apb_slv_prdata_o17, fabric_spw0_apb_slv_prdata_o18, fabric_spw0_apb_slv_prdata_o19, fabric_spw0_apb_slv_prdata_o20, fabric_spw0_apb_slv_prdata_o21, fabric_spw0_apb_slv_prdata_o22 -, fabric_spw0_apb_slv_prdata_o23, fabric_spw0_apb_slv_prdata_o24, fabric_spw0_apb_slv_prdata_o25, fabric_spw0_apb_slv_prdata_o26, fabric_spw0_apb_slv_prdata_o27, fabric_spw0_apb_slv_prdata_o28, fabric_spw0_apb_slv_prdata_o29, fabric_spw0_apb_slv_prdata_o30, fabric_spw0_apb_slv_prdata_o31, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_data_i1, fabric_spw1_tx_fifo_data_i2, fabric_spw1_tx_fifo_data_i3, fabric_spw1_tx_fifo_data_i4, fabric_spw1_tx_fifo_data_i5 -, fabric_spw1_tx_fifo_data_i6, fabric_spw1_tx_fifo_data_i7, fabric_spw1_tx_fifo_data_i8, fabric_spw1_tx_fifo_data_i9, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_rx_fifo_data_o1, fabric_spw1_rx_fifo_data_o2, fabric_spw1_rx_fifo_data_o3, fabric_spw1_rx_fifo_data_o4, fabric_spw1_rx_fifo_data_o5, fabric_spw1_rx_fifo_data_o6, fabric_spw1_rx_fifo_data_o7, fabric_spw1_rx_fifo_data_o8, fabric_spw1_rx_fifo_data_o9, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_paddr_i1 -, fabric_spw1_apb_slv_paddr_i2, fabric_spw1_apb_slv_paddr_i3, fabric_spw1_apb_slv_paddr_i4, fabric_spw1_apb_slv_paddr_i5, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pwdata_i1, fabric_spw1_apb_slv_pwdata_i2, fabric_spw1_apb_slv_pwdata_i3, fabric_spw1_apb_slv_pwdata_i4, fabric_spw1_apb_slv_pwdata_i5, fabric_spw1_apb_slv_pwdata_i6, fabric_spw1_apb_slv_pwdata_i7, fabric_spw1_apb_slv_pwdata_i8, fabric_spw1_apb_slv_pwdata_i9, fabric_spw1_apb_slv_pwdata_i10, fabric_spw1_apb_slv_pwdata_i11, fabric_spw1_apb_slv_pwdata_i12, fabric_spw1_apb_slv_pwdata_i13, fabric_spw1_apb_slv_pwdata_i14, fabric_spw1_apb_slv_pwdata_i15, fabric_spw1_apb_slv_pwdata_i16 -, fabric_spw1_apb_slv_pwdata_i17, fabric_spw1_apb_slv_pwdata_i18, fabric_spw1_apb_slv_pwdata_i19, fabric_spw1_apb_slv_pwdata_i20, fabric_spw1_apb_slv_pwdata_i21, fabric_spw1_apb_slv_pwdata_i22, fabric_spw1_apb_slv_pwdata_i23, fabric_spw1_apb_slv_pwdata_i24, fabric_spw1_apb_slv_pwdata_i25, fabric_spw1_apb_slv_pwdata_i26, fabric_spw1_apb_slv_pwdata_i27, fabric_spw1_apb_slv_pwdata_i28, fabric_spw1_apb_slv_pwdata_i29, fabric_spw1_apb_slv_pwdata_i30, fabric_spw1_apb_slv_pwdata_i31, fabric_spw1_apb_slv_prdata_o1, fabric_spw1_apb_slv_prdata_o2, fabric_spw1_apb_slv_prdata_o3, fabric_spw1_apb_slv_prdata_o4, fabric_spw1_apb_slv_prdata_o5, fabric_spw1_apb_slv_prdata_o6 -, fabric_spw1_apb_slv_prdata_o7, fabric_spw1_apb_slv_prdata_o8, fabric_spw1_apb_slv_prdata_o9, fabric_spw1_apb_slv_prdata_o10, fabric_spw1_apb_slv_prdata_o11, fabric_spw1_apb_slv_prdata_o12, fabric_spw1_apb_slv_prdata_o13, fabric_spw1_apb_slv_prdata_o14, fabric_spw1_apb_slv_prdata_o15, fabric_spw1_apb_slv_prdata_o16, fabric_spw1_apb_slv_prdata_o17, fabric_spw1_apb_slv_prdata_o18, fabric_spw1_apb_slv_prdata_o19, fabric_spw1_apb_slv_prdata_o20, fabric_spw1_apb_slv_prdata_o21, fabric_spw1_apb_slv_prdata_o22, fabric_spw1_apb_slv_prdata_o23, fabric_spw1_apb_slv_prdata_o24, fabric_spw1_apb_slv_prdata_o25, fabric_spw1_apb_slv_prdata_o26, fabric_spw1_apb_slv_prdata_o27 -, fabric_spw1_apb_slv_prdata_o28, fabric_spw1_apb_slv_prdata_o29, fabric_spw1_apb_slv_prdata_o30, fabric_spw1_apb_slv_prdata_o31, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o); - input fabric_adc0_arst_b_tmr_i1; - input fabric_adc0_arst_b_tmr_i2; - input fabric_adc0_arst_b_tmr_i3; - output fabric_adc0_cal_done_o; - output fabric_adc0_cal_n_overflow_o; - output fabric_adc0_cal_n_underflow_o; - output fabric_adc0_cal_p_overflow_o; - output fabric_adc0_cal_p_underflow_o; - input fabric_adc0_cal_start_i; - input fabric_adc0_clk_i; - input fabric_adc0_dbg_addr_i1; - input fabric_adc0_dbg_addr_i2; - input fabric_adc0_dbg_addr_i3; - input fabric_adc0_dbg_addr_i4; - output fabric_adc0_dbg_data_o1; - output fabric_adc0_dbg_data_o10; - output fabric_adc0_dbg_data_o11; - output fabric_adc0_dbg_data_o12; - output fabric_adc0_dbg_data_o13; - output fabric_adc0_dbg_data_o14; - output fabric_adc0_dbg_data_o15; - output fabric_adc0_dbg_data_o16; - output fabric_adc0_dbg_data_o17; - output fabric_adc0_dbg_data_o18; - output fabric_adc0_dbg_data_o19; - output fabric_adc0_dbg_data_o2; - output fabric_adc0_dbg_data_o20; - output fabric_adc0_dbg_data_o21; - output fabric_adc0_dbg_data_o22; - output fabric_adc0_dbg_data_o23; - output fabric_adc0_dbg_data_o24; - output fabric_adc0_dbg_data_o25; - output fabric_adc0_dbg_data_o26; - output fabric_adc0_dbg_data_o27; - output fabric_adc0_dbg_data_o28; - output fabric_adc0_dbg_data_o29; - output fabric_adc0_dbg_data_o3; - output fabric_adc0_dbg_data_o30; - output fabric_adc0_dbg_data_o31; - output fabric_adc0_dbg_data_o32; - output fabric_adc0_dbg_data_o4; - output fabric_adc0_dbg_data_o5; - output fabric_adc0_dbg_data_o6; - output fabric_adc0_dbg_data_o7; - output fabric_adc0_dbg_data_o8; - output fabric_adc0_dbg_data_o9; - input fabric_adc0_dft_scan_en_i; - input fabric_adc0_dft_si_i1; - input fabric_adc0_dft_si_i10; - input fabric_adc0_dft_si_i11; - input fabric_adc0_dft_si_i12; - input fabric_adc0_dft_si_i2; - input fabric_adc0_dft_si_i3; - input fabric_adc0_dft_si_i4; - input fabric_adc0_dft_si_i5; - input fabric_adc0_dft_si_i6; - input fabric_adc0_dft_si_i7; - input fabric_adc0_dft_si_i8; - input fabric_adc0_dft_si_i9; - input fabric_adc0_dft_test_mode_i1; - input fabric_adc0_dft_test_mode_i2; - input fabric_adc0_pwr_down_b_tmr_i1; - input fabric_adc0_pwr_down_b_tmr_i2; - input fabric_adc0_pwr_down_b_tmr_i3; - input fabric_adc0_spare_i1; - input fabric_adc0_spare_i10; - input fabric_adc0_spare_i11; - input fabric_adc0_spare_i12; - input fabric_adc0_spare_i13; - input fabric_adc0_spare_i14; - input fabric_adc0_spare_i15; - input fabric_adc0_spare_i16; - input fabric_adc0_spare_i2; - input fabric_adc0_spare_i3; - input fabric_adc0_spare_i4; - input fabric_adc0_spare_i5; - input fabric_adc0_spare_i6; - input fabric_adc0_spare_i7; - input fabric_adc0_spare_i8; - input fabric_adc0_spare_i9; - input fabric_adc0_usr_arst_b_tmr_i1; - input fabric_adc0_usr_arst_b_tmr_i2; - input fabric_adc0_usr_arst_b_tmr_i3; - input fabric_adc0_usr_channel_i1; - input fabric_adc0_usr_channel_i2; - input fabric_adc0_usr_channel_i3; - input fabric_adc0_usr_cke_i; - output fabric_adc0_usr_conv_done_o; - input fabric_adc0_usr_conv_start_i; - input fabric_adc0_usr_sample_lsb_i1; - input fabric_adc0_usr_sample_lsb_i2; - input fabric_adc0_usr_sample_lsb_i3; - input fabric_adc0_usr_sample_lsb_i4; - output fabric_adc0_usr_sample_o1; - output fabric_adc0_usr_sample_o10; - output fabric_adc0_usr_sample_o11; - output fabric_adc0_usr_sample_o12; - output fabric_adc0_usr_sample_o2; - output fabric_adc0_usr_sample_o3; - output fabric_adc0_usr_sample_o4; - output fabric_adc0_usr_sample_o5; - output fabric_adc0_usr_sample_o6; - output fabric_adc0_usr_sample_o7; - output fabric_adc0_usr_sample_o8; - output fabric_adc0_usr_sample_o9; - input fabric_adc1_arst_b_tmr_i1; - input fabric_adc1_arst_b_tmr_i2; - input fabric_adc1_arst_b_tmr_i3; - output fabric_adc1_cal_done_o; - output fabric_adc1_cal_n_overflow_o; - output fabric_adc1_cal_n_underflow_o; - output fabric_adc1_cal_p_overflow_o; - output fabric_adc1_cal_p_underflow_o; - input fabric_adc1_cal_start_i; - input fabric_adc1_clk_i; - input fabric_adc1_dbg_addr_i1; - input fabric_adc1_dbg_addr_i2; - input fabric_adc1_dbg_addr_i3; - input fabric_adc1_dbg_addr_i4; - output fabric_adc1_dbg_data_o1; - output fabric_adc1_dbg_data_o10; - output fabric_adc1_dbg_data_o11; - output fabric_adc1_dbg_data_o12; - output fabric_adc1_dbg_data_o13; - output fabric_adc1_dbg_data_o14; - output fabric_adc1_dbg_data_o15; - output fabric_adc1_dbg_data_o16; - output fabric_adc1_dbg_data_o17; - output fabric_adc1_dbg_data_o18; - output fabric_adc1_dbg_data_o19; - output fabric_adc1_dbg_data_o2; - output fabric_adc1_dbg_data_o20; - output fabric_adc1_dbg_data_o21; - output fabric_adc1_dbg_data_o22; - output fabric_adc1_dbg_data_o23; - output fabric_adc1_dbg_data_o24; - output fabric_adc1_dbg_data_o25; - output fabric_adc1_dbg_data_o26; - output fabric_adc1_dbg_data_o27; - output fabric_adc1_dbg_data_o28; - output fabric_adc1_dbg_data_o29; - output fabric_adc1_dbg_data_o3; - output fabric_adc1_dbg_data_o30; - output fabric_adc1_dbg_data_o31; - output fabric_adc1_dbg_data_o32; - output fabric_adc1_dbg_data_o4; - output fabric_adc1_dbg_data_o5; - output fabric_adc1_dbg_data_o6; - output fabric_adc1_dbg_data_o7; - output fabric_adc1_dbg_data_o8; - output fabric_adc1_dbg_data_o9; - input fabric_adc1_dft_scan_en_i; - input fabric_adc1_dft_si_i1; - input fabric_adc1_dft_si_i10; - input fabric_adc1_dft_si_i11; - input fabric_adc1_dft_si_i12; - input fabric_adc1_dft_si_i2; - input fabric_adc1_dft_si_i3; - input fabric_adc1_dft_si_i4; - input fabric_adc1_dft_si_i5; - input fabric_adc1_dft_si_i6; - input fabric_adc1_dft_si_i7; - input fabric_adc1_dft_si_i8; - input fabric_adc1_dft_si_i9; - input fabric_adc1_dft_test_mode_i1; - input fabric_adc1_dft_test_mode_i2; - input fabric_adc1_pwr_down_b_tmr_i1; - input fabric_adc1_pwr_down_b_tmr_i2; - input fabric_adc1_pwr_down_b_tmr_i3; - input fabric_adc1_spare_i1; - input fabric_adc1_spare_i10; - input fabric_adc1_spare_i11; - input fabric_adc1_spare_i12; - input fabric_adc1_spare_i13; - input fabric_adc1_spare_i14; - input fabric_adc1_spare_i15; - input fabric_adc1_spare_i16; - input fabric_adc1_spare_i2; - input fabric_adc1_spare_i3; - input fabric_adc1_spare_i4; - input fabric_adc1_spare_i5; - input fabric_adc1_spare_i6; - input fabric_adc1_spare_i7; - input fabric_adc1_spare_i8; - input fabric_adc1_spare_i9; - input fabric_adc1_usr_arst_b_tmr_i1; - input fabric_adc1_usr_arst_b_tmr_i2; - input fabric_adc1_usr_arst_b_tmr_i3; - input fabric_adc1_usr_channel_i1; - input fabric_adc1_usr_channel_i2; - input fabric_adc1_usr_channel_i3; - input fabric_adc1_usr_cke_i; - output fabric_adc1_usr_conv_done_o; - input fabric_adc1_usr_conv_start_i; - input fabric_adc1_usr_sample_lsb_i1; - input fabric_adc1_usr_sample_lsb_i2; - input fabric_adc1_usr_sample_lsb_i3; - input fabric_adc1_usr_sample_lsb_i4; - output fabric_adc1_usr_sample_o1; - output fabric_adc1_usr_sample_o10; - output fabric_adc1_usr_sample_o11; - output fabric_adc1_usr_sample_o12; - output fabric_adc1_usr_sample_o2; - output fabric_adc1_usr_sample_o3; - output fabric_adc1_usr_sample_o4; - output fabric_adc1_usr_sample_o5; - output fabric_adc1_usr_sample_o6; - output fabric_adc1_usr_sample_o7; - output fabric_adc1_usr_sample_o8; - output fabric_adc1_usr_sample_o9; - input fabric_adc2_arst_b_tmr_i1; - input fabric_adc2_arst_b_tmr_i2; - input fabric_adc2_arst_b_tmr_i3; - output fabric_adc2_cal_done_o; - output fabric_adc2_cal_n_overflow_o; - output fabric_adc2_cal_n_underflow_o; - output fabric_adc2_cal_p_overflow_o; - output fabric_adc2_cal_p_underflow_o; - input fabric_adc2_cal_start_i; - input fabric_adc2_clk_i; - input fabric_adc2_dbg_addr_i1; - input fabric_adc2_dbg_addr_i2; - input fabric_adc2_dbg_addr_i3; - input fabric_adc2_dbg_addr_i4; - output fabric_adc2_dbg_data_o1; - output fabric_adc2_dbg_data_o10; - output fabric_adc2_dbg_data_o11; - output fabric_adc2_dbg_data_o12; - output fabric_adc2_dbg_data_o13; - output fabric_adc2_dbg_data_o14; - output fabric_adc2_dbg_data_o15; - output fabric_adc2_dbg_data_o16; - output fabric_adc2_dbg_data_o17; - output fabric_adc2_dbg_data_o18; - output fabric_adc2_dbg_data_o19; - output fabric_adc2_dbg_data_o2; - output fabric_adc2_dbg_data_o20; - output fabric_adc2_dbg_data_o21; - output fabric_adc2_dbg_data_o22; - output fabric_adc2_dbg_data_o23; - output fabric_adc2_dbg_data_o24; - output fabric_adc2_dbg_data_o25; - output fabric_adc2_dbg_data_o26; - output fabric_adc2_dbg_data_o27; - output fabric_adc2_dbg_data_o28; - output fabric_adc2_dbg_data_o29; - output fabric_adc2_dbg_data_o3; - output fabric_adc2_dbg_data_o30; - output fabric_adc2_dbg_data_o31; - output fabric_adc2_dbg_data_o32; - output fabric_adc2_dbg_data_o4; - output fabric_adc2_dbg_data_o5; - output fabric_adc2_dbg_data_o6; - output fabric_adc2_dbg_data_o7; - output fabric_adc2_dbg_data_o8; - output fabric_adc2_dbg_data_o9; - input fabric_adc2_dft_scan_en_i; - input fabric_adc2_dft_si_i1; - input fabric_adc2_dft_si_i10; - input fabric_adc2_dft_si_i11; - input fabric_adc2_dft_si_i12; - input fabric_adc2_dft_si_i2; - input fabric_adc2_dft_si_i3; - input fabric_adc2_dft_si_i4; - input fabric_adc2_dft_si_i5; - input fabric_adc2_dft_si_i6; - input fabric_adc2_dft_si_i7; - input fabric_adc2_dft_si_i8; - input fabric_adc2_dft_si_i9; - input fabric_adc2_dft_test_mode_i1; - input fabric_adc2_dft_test_mode_i2; - input fabric_adc2_pwr_down_b_tmr_i1; - input fabric_adc2_pwr_down_b_tmr_i2; - input fabric_adc2_pwr_down_b_tmr_i3; - input fabric_adc2_spare_i1; - input fabric_adc2_spare_i10; - input fabric_adc2_spare_i11; - input fabric_adc2_spare_i12; - input fabric_adc2_spare_i13; - input fabric_adc2_spare_i14; - input fabric_adc2_spare_i15; - input fabric_adc2_spare_i16; - input fabric_adc2_spare_i2; - input fabric_adc2_spare_i3; - input fabric_adc2_spare_i4; - input fabric_adc2_spare_i5; - input fabric_adc2_spare_i6; - input fabric_adc2_spare_i7; - input fabric_adc2_spare_i8; - input fabric_adc2_spare_i9; - input fabric_adc2_usr_arst_b_tmr_i1; - input fabric_adc2_usr_arst_b_tmr_i2; - input fabric_adc2_usr_arst_b_tmr_i3; - input fabric_adc2_usr_channel_i1; - input fabric_adc2_usr_channel_i2; - input fabric_adc2_usr_channel_i3; - input fabric_adc2_usr_cke_i; - output fabric_adc2_usr_conv_done_o; - input fabric_adc2_usr_conv_start_i; - input fabric_adc2_usr_sample_lsb_i1; - input fabric_adc2_usr_sample_lsb_i2; - input fabric_adc2_usr_sample_lsb_i3; - input fabric_adc2_usr_sample_lsb_i4; - output fabric_adc2_usr_sample_o1; - output fabric_adc2_usr_sample_o10; - output fabric_adc2_usr_sample_o11; - output fabric_adc2_usr_sample_o12; - output fabric_adc2_usr_sample_o2; - output fabric_adc2_usr_sample_o3; - output fabric_adc2_usr_sample_o4; - output fabric_adc2_usr_sample_o5; - output fabric_adc2_usr_sample_o6; - output fabric_adc2_usr_sample_o7; - output fabric_adc2_usr_sample_o8; - output fabric_adc2_usr_sample_o9; - input fabric_adc3_arst_b_tmr_i1; - input fabric_adc3_arst_b_tmr_i2; - input fabric_adc3_arst_b_tmr_i3; - output fabric_adc3_cal_done_o; - output fabric_adc3_cal_n_overflow_o; - output fabric_adc3_cal_n_underflow_o; - output fabric_adc3_cal_p_overflow_o; - output fabric_adc3_cal_p_underflow_o; - input fabric_adc3_cal_start_i; - input fabric_adc3_clk_i; - input fabric_adc3_dbg_addr_i1; - input fabric_adc3_dbg_addr_i2; - input fabric_adc3_dbg_addr_i3; - input fabric_adc3_dbg_addr_i4; - output fabric_adc3_dbg_data_o1; - output fabric_adc3_dbg_data_o10; - output fabric_adc3_dbg_data_o11; - output fabric_adc3_dbg_data_o12; - output fabric_adc3_dbg_data_o13; - output fabric_adc3_dbg_data_o14; - output fabric_adc3_dbg_data_o15; - output fabric_adc3_dbg_data_o16; - output fabric_adc3_dbg_data_o17; - output fabric_adc3_dbg_data_o18; - output fabric_adc3_dbg_data_o19; - output fabric_adc3_dbg_data_o2; - output fabric_adc3_dbg_data_o20; - output fabric_adc3_dbg_data_o21; - output fabric_adc3_dbg_data_o22; - output fabric_adc3_dbg_data_o23; - output fabric_adc3_dbg_data_o24; - output fabric_adc3_dbg_data_o25; - output fabric_adc3_dbg_data_o26; - output fabric_adc3_dbg_data_o27; - output fabric_adc3_dbg_data_o28; - output fabric_adc3_dbg_data_o29; - output fabric_adc3_dbg_data_o3; - output fabric_adc3_dbg_data_o30; - output fabric_adc3_dbg_data_o31; - output fabric_adc3_dbg_data_o32; - output fabric_adc3_dbg_data_o4; - output fabric_adc3_dbg_data_o5; - output fabric_adc3_dbg_data_o6; - output fabric_adc3_dbg_data_o7; - output fabric_adc3_dbg_data_o8; - output fabric_adc3_dbg_data_o9; - input fabric_adc3_dft_scan_en_i; - input fabric_adc3_dft_si_i1; - input fabric_adc3_dft_si_i10; - input fabric_adc3_dft_si_i11; - input fabric_adc3_dft_si_i12; - input fabric_adc3_dft_si_i2; - input fabric_adc3_dft_si_i3; - input fabric_adc3_dft_si_i4; - input fabric_adc3_dft_si_i5; - input fabric_adc3_dft_si_i6; - input fabric_adc3_dft_si_i7; - input fabric_adc3_dft_si_i8; - input fabric_adc3_dft_si_i9; - input fabric_adc3_dft_test_mode_i1; - input fabric_adc3_dft_test_mode_i2; - input fabric_adc3_pwr_down_b_tmr_i1; - input fabric_adc3_pwr_down_b_tmr_i2; - input fabric_adc3_pwr_down_b_tmr_i3; - input fabric_adc3_spare_i1; - input fabric_adc3_spare_i10; - input fabric_adc3_spare_i11; - input fabric_adc3_spare_i12; - input fabric_adc3_spare_i13; - input fabric_adc3_spare_i14; - input fabric_adc3_spare_i15; - input fabric_adc3_spare_i16; - input fabric_adc3_spare_i2; - input fabric_adc3_spare_i3; - input fabric_adc3_spare_i4; - input fabric_adc3_spare_i5; - input fabric_adc3_spare_i6; - input fabric_adc3_spare_i7; - input fabric_adc3_spare_i8; - input fabric_adc3_spare_i9; - input fabric_adc3_usr_arst_b_tmr_i1; - input fabric_adc3_usr_arst_b_tmr_i2; - input fabric_adc3_usr_arst_b_tmr_i3; - input fabric_adc3_usr_channel_i1; - input fabric_adc3_usr_channel_i2; - input fabric_adc3_usr_channel_i3; - input fabric_adc3_usr_cke_i; - output fabric_adc3_usr_conv_done_o; - input fabric_adc3_usr_conv_start_i; - input fabric_adc3_usr_sample_lsb_i1; - input fabric_adc3_usr_sample_lsb_i2; - input fabric_adc3_usr_sample_lsb_i3; - input fabric_adc3_usr_sample_lsb_i4; - output fabric_adc3_usr_sample_o1; - output fabric_adc3_usr_sample_o10; - output fabric_adc3_usr_sample_o11; - output fabric_adc3_usr_sample_o12; - output fabric_adc3_usr_sample_o2; - output fabric_adc3_usr_sample_o3; - output fabric_adc3_usr_sample_o4; - output fabric_adc3_usr_sample_o5; - output fabric_adc3_usr_sample_o6; - output fabric_adc3_usr_sample_o7; - output fabric_adc3_usr_sample_o8; - output fabric_adc3_usr_sample_o9; - input fabric_cfg_adc0_clk_cal_div_ratio_i1; - input fabric_cfg_adc0_clk_cal_div_ratio_i2; - input fabric_cfg_adc0_clk_cal_div_ratio_i3; - input fabric_cfg_adc0_clk_cal_div_ratio_i4; - input fabric_cfg_adc0_clk_cal_div_ratio_i5; - input fabric_cfg_adc0_conv_done_delayed_i; - input fabric_cfg_adc0_use_cdc_i; - input fabric_cfg_adc1_clk_cal_div_ratio_i1; - input fabric_cfg_adc1_clk_cal_div_ratio_i2; - input fabric_cfg_adc1_clk_cal_div_ratio_i3; - input fabric_cfg_adc1_clk_cal_div_ratio_i4; - input fabric_cfg_adc1_clk_cal_div_ratio_i5; - input fabric_cfg_adc1_conv_done_delayed_i; - input fabric_cfg_adc1_use_cdc_i; - input fabric_cfg_adc2_clk_cal_div_ratio_i1; - input fabric_cfg_adc2_clk_cal_div_ratio_i2; - input fabric_cfg_adc2_clk_cal_div_ratio_i3; - input fabric_cfg_adc2_clk_cal_div_ratio_i4; - input fabric_cfg_adc2_clk_cal_div_ratio_i5; - input fabric_cfg_adc2_conv_done_delayed_i; - input fabric_cfg_adc2_use_cdc_i; - input fabric_cfg_adc3_clk_cal_div_ratio_i1; - input fabric_cfg_adc3_clk_cal_div_ratio_i2; - input fabric_cfg_adc3_clk_cal_div_ratio_i3; - input fabric_cfg_adc3_clk_cal_div_ratio_i4; - input fabric_cfg_adc3_clk_cal_div_ratio_i5; - input fabric_cfg_adc3_conv_done_delayed_i; - input fabric_cfg_adc3_use_cdc_i; - input fabric_cfg_dac0_reg_cm_select_i; - input fabric_cfg_dac0_reg_res_i1; - input fabric_cfg_dac0_reg_res_i2; - input fabric_cfg_dac0_reg_vref_select_i; - input fabric_cfg_dac0_sync_i; - input fabric_cfg_dac1_reg_cm_select_i; - input fabric_cfg_dac1_reg_res_i1; - input fabric_cfg_dac1_reg_res_i2; - input fabric_cfg_dac1_reg_vref_select_i; - input fabric_cfg_dac1_sync_i; - input fabric_cfg_dac2_reg_cm_select_i; - input fabric_cfg_dac2_reg_res_i1; - input fabric_cfg_dac2_reg_res_i2; - input fabric_cfg_dac2_reg_vref_select_i; - input fabric_cfg_dac2_sync_i; - input fabric_cfg_dac3_reg_cm_select_i; - input fabric_cfg_dac3_reg_res_i1; - input fabric_cfg_dac3_reg_res_i2; - input fabric_cfg_dac3_reg_vref_select_i; - input fabric_cfg_dac3_sync_i; - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_clk_bsm_o; - output fabric_clk_otp_mrepair_o; - input fabric_clk_otp_mux_i; - output fabric_clk_otp_o; - output fabric_clk_user0_o; - output fabric_clk_user1_o; - input fabric_dac0_clk_en_i; - input fabric_dac0_clk_i; - input fabric_dac0_comp_en_i; - input fabric_dac0_comp_hyst_en_i; - input fabric_dac0_comp_in_sel_i1; - input fabric_dac0_comp_in_sel_i2; - input fabric_dac0_comp_in_sel_i3; - input fabric_dac0_comp_in_sel_i4; - output fabric_dac0_comp_out_o; - input fabric_dac0_comp_ref_sel_i; - input fabric_dac0_din_i1; - input fabric_dac0_din_i10; - input fabric_dac0_din_i11; - input fabric_dac0_din_i12; - input fabric_dac0_din_i13; - input fabric_dac0_din_i2; - input fabric_dac0_din_i3; - input fabric_dac0_din_i4; - input fabric_dac0_din_i5; - input fabric_dac0_din_i6; - input fabric_dac0_din_i7; - input fabric_dac0_din_i8; - input fabric_dac0_din_i9; - input fabric_dac0_filt_en_i; - input fabric_dac0_op_en_i; - input fabric_dac0_reg_pwr_down_n_i; - input fabric_dac0_rstn_i; - input fabric_dac1_clk_en_i; - input fabric_dac1_clk_i; - input fabric_dac1_comp_en_i; - input fabric_dac1_comp_hyst_en_i; - input fabric_dac1_comp_in_sel_i1; - input fabric_dac1_comp_in_sel_i2; - input fabric_dac1_comp_in_sel_i3; - input fabric_dac1_comp_in_sel_i4; - output fabric_dac1_comp_out_o; - input fabric_dac1_comp_ref_sel_i; - input fabric_dac1_din_i1; - input fabric_dac1_din_i10; - input fabric_dac1_din_i11; - input fabric_dac1_din_i12; - input fabric_dac1_din_i13; - input fabric_dac1_din_i2; - input fabric_dac1_din_i3; - input fabric_dac1_din_i4; - input fabric_dac1_din_i5; - input fabric_dac1_din_i6; - input fabric_dac1_din_i7; - input fabric_dac1_din_i8; - input fabric_dac1_din_i9; - input fabric_dac1_filt_en_i; - input fabric_dac1_op_en_i; - input fabric_dac1_reg_pwr_down_n_i; - input fabric_dac1_rstn_i; - input fabric_dac2_clk_en_i; - input fabric_dac2_clk_i; - input fabric_dac2_comp_en_i; - input fabric_dac2_comp_hyst_en_i; - input fabric_dac2_comp_in_sel_i1; - input fabric_dac2_comp_in_sel_i10; - input fabric_dac2_comp_in_sel_i11; - input fabric_dac2_comp_in_sel_i12; - input fabric_dac2_comp_in_sel_i13; - input fabric_dac2_comp_in_sel_i2; - input fabric_dac2_comp_in_sel_i3; - input fabric_dac2_comp_in_sel_i4; - input fabric_dac2_comp_in_sel_i5; - input fabric_dac2_comp_in_sel_i6; - input fabric_dac2_comp_in_sel_i7; - input fabric_dac2_comp_in_sel_i8; - input fabric_dac2_comp_in_sel_i9; - output fabric_dac2_comp_out_o; - input fabric_dac2_comp_ref_sel_i; - input fabric_dac2_din_i1; - input fabric_dac2_din_i10; - input fabric_dac2_din_i11; - input fabric_dac2_din_i12; - input fabric_dac2_din_i13; - input fabric_dac2_din_i2; - input fabric_dac2_din_i3; - input fabric_dac2_din_i4; - input fabric_dac2_din_i5; - input fabric_dac2_din_i6; - input fabric_dac2_din_i7; - input fabric_dac2_din_i8; - input fabric_dac2_din_i9; - input fabric_dac2_filt_en_i; - input fabric_dac2_op_en_i; - input fabric_dac2_reg_pwr_down_n_i; - input fabric_dac2_rstn_i; - input fabric_dac3_clk_en_i; - input fabric_dac3_clk_i; - input fabric_dac3_comp_en_i; - input fabric_dac3_comp_hyst_en_i; - input fabric_dac3_comp_in_sel_i1; - input fabric_dac3_comp_in_sel_i2; - input fabric_dac3_comp_in_sel_i3; - input fabric_dac3_comp_in_sel_i4; - output fabric_dac3_comp_out_o; - input fabric_dac3_comp_ref_sel_i; - input fabric_dac3_din_i1; - input fabric_dac3_din_i10; - input fabric_dac3_din_i11; - input fabric_dac3_din_i12; - input fabric_dac3_din_i13; - input fabric_dac3_din_i2; - input fabric_dac3_din_i3; - input fabric_dac3_din_i4; - input fabric_dac3_din_i5; - input fabric_dac3_din_i6; - input fabric_dac3_din_i7; - input fabric_dac3_din_i8; - input fabric_dac3_din_i9; - input fabric_dac3_filt_en_i; - input fabric_dac3_op_en_i; - input fabric_dac3_reg_pwr_down_n_i; - input fabric_dac3_rstn_i; - output fabric_debug_access_reg_data_ready_o; - output fabric_debug_bsec_core_status_o1; - output fabric_debug_bsec_core_status_o10; - output fabric_debug_bsec_core_status_o11; - output fabric_debug_bsec_core_status_o12; - output fabric_debug_bsec_core_status_o13; - output fabric_debug_bsec_core_status_o14; - output fabric_debug_bsec_core_status_o15; - output fabric_debug_bsec_core_status_o16; - output fabric_debug_bsec_core_status_o17; - output fabric_debug_bsec_core_status_o18; - output fabric_debug_bsec_core_status_o19; - output fabric_debug_bsec_core_status_o2; - output fabric_debug_bsec_core_status_o20; - output fabric_debug_bsec_core_status_o21; - output fabric_debug_bsec_core_status_o22; - output fabric_debug_bsec_core_status_o23; - output fabric_debug_bsec_core_status_o24; - output fabric_debug_bsec_core_status_o25; - output fabric_debug_bsec_core_status_o26; - output fabric_debug_bsec_core_status_o27; - output fabric_debug_bsec_core_status_o28; - output fabric_debug_bsec_core_status_o29; - output fabric_debug_bsec_core_status_o3; - output fabric_debug_bsec_core_status_o30; - output fabric_debug_bsec_core_status_o31; - output fabric_debug_bsec_core_status_o32; - output fabric_debug_bsec_core_status_o4; - output fabric_debug_bsec_core_status_o5; - output fabric_debug_bsec_core_status_o6; - output fabric_debug_bsec_core_status_o7; - output fabric_debug_bsec_core_status_o8; - output fabric_debug_bsec_core_status_o9; - output fabric_debug_cpt_retry_o1; - output fabric_debug_cpt_retry_o2; - output fabric_debug_cpt_retry_o3; - output fabric_debug_cpt_retry_o4; - output fabric_debug_direct_permission_read_o1; - output fabric_debug_direct_permission_read_o2; - output fabric_debug_direct_permission_read_o3; - output fabric_debug_direct_permission_read_o4; - output fabric_debug_direct_permission_write_o1; - output fabric_debug_direct_permission_write_o2; - output fabric_debug_direct_permission_write_o3; - output fabric_debug_direct_permission_write_o4; - output fabric_debug_error_o; - output fabric_debug_frame_permission_frame_o1; - output fabric_debug_frame_permission_frame_o2; - output fabric_debug_frame_permission_frame_o3; - output fabric_debug_frame_permission_frame_o4; - output fabric_debug_frame_use_encryption_o; - output fabric_debug_fsm_state_o1; - output fabric_debug_fsm_state_o2; - output fabric_debug_fsm_state_o3; - output fabric_debug_key_correct_o; - output fabric_debug_lifecycle_o1; - output fabric_debug_lifecycle_o2; - output fabric_debug_lifecycle_o3; - output fabric_debug_lifecycle_o4; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output fabric_debug_otpapb_state_o1; - output fabric_debug_otpapb_state_o2; - output fabric_debug_otpapb_state_o3; - output fabric_debug_otpboot_curr_addr_o1; - output fabric_debug_otpboot_curr_addr_o2; - output fabric_debug_otpboot_curr_addr_o3; - output fabric_debug_otpboot_curr_addr_o4; - output fabric_debug_otpboot_curr_addr_o5; - output fabric_debug_otpboot_curr_addr_o6; - output fabric_debug_otpboot_curr_addr_o7; - output fabric_debug_otpboot_curr_addr_o8; - output fabric_debug_otpboot_state_o1; - output fabric_debug_otpboot_state_o2; - output fabric_debug_otpboot_state_o3; - output fabric_debug_otpmgmt_state_o1; - output fabric_debug_otpmgmt_state_o2; - output fabric_debug_otpmgmt_state_o3; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - input fabric_direct0_cfg_bank_i1; - input fabric_direct0_cfg_bank_i2; - input fabric_direct0_cfg_bank_i3; - input fabric_direct0_cfg_bank_i4; - input fabric_direct0_cfg_pad_i1; - input fabric_direct0_cfg_pad_i10; - input fabric_direct0_cfg_pad_i100; - input fabric_direct0_cfg_pad_i101; - input fabric_direct0_cfg_pad_i102; - input fabric_direct0_cfg_pad_i103; - input fabric_direct0_cfg_pad_i104; - input fabric_direct0_cfg_pad_i105; - input fabric_direct0_cfg_pad_i106; - input fabric_direct0_cfg_pad_i107; - input fabric_direct0_cfg_pad_i108; - input fabric_direct0_cfg_pad_i109; - input fabric_direct0_cfg_pad_i11; - input fabric_direct0_cfg_pad_i110; - input fabric_direct0_cfg_pad_i111; - input fabric_direct0_cfg_pad_i112; - input fabric_direct0_cfg_pad_i113; - input fabric_direct0_cfg_pad_i114; - input fabric_direct0_cfg_pad_i115; - input fabric_direct0_cfg_pad_i116; - input fabric_direct0_cfg_pad_i117; - input fabric_direct0_cfg_pad_i118; - input fabric_direct0_cfg_pad_i119; - input fabric_direct0_cfg_pad_i12; - input fabric_direct0_cfg_pad_i120; - input fabric_direct0_cfg_pad_i121; - input fabric_direct0_cfg_pad_i122; - input fabric_direct0_cfg_pad_i123; - input fabric_direct0_cfg_pad_i124; - input fabric_direct0_cfg_pad_i125; - input fabric_direct0_cfg_pad_i126; - input fabric_direct0_cfg_pad_i127; - input fabric_direct0_cfg_pad_i128; - input fabric_direct0_cfg_pad_i129; - input fabric_direct0_cfg_pad_i13; - input fabric_direct0_cfg_pad_i130; - input fabric_direct0_cfg_pad_i131; - input fabric_direct0_cfg_pad_i132; - input fabric_direct0_cfg_pad_i133; - input fabric_direct0_cfg_pad_i134; - input fabric_direct0_cfg_pad_i135; - input fabric_direct0_cfg_pad_i136; - input fabric_direct0_cfg_pad_i137; - input fabric_direct0_cfg_pad_i138; - input fabric_direct0_cfg_pad_i139; - input fabric_direct0_cfg_pad_i14; - input fabric_direct0_cfg_pad_i140; - input fabric_direct0_cfg_pad_i141; - input fabric_direct0_cfg_pad_i142; - input fabric_direct0_cfg_pad_i143; - input fabric_direct0_cfg_pad_i144; - input fabric_direct0_cfg_pad_i145; - input fabric_direct0_cfg_pad_i146; - input fabric_direct0_cfg_pad_i147; - input fabric_direct0_cfg_pad_i148; - input fabric_direct0_cfg_pad_i149; - input fabric_direct0_cfg_pad_i15; - input fabric_direct0_cfg_pad_i150; - input fabric_direct0_cfg_pad_i151; - input fabric_direct0_cfg_pad_i152; - input fabric_direct0_cfg_pad_i153; - input fabric_direct0_cfg_pad_i154; - input fabric_direct0_cfg_pad_i155; - input fabric_direct0_cfg_pad_i156; - input fabric_direct0_cfg_pad_i157; - input fabric_direct0_cfg_pad_i158; - input fabric_direct0_cfg_pad_i159; - input fabric_direct0_cfg_pad_i16; - input fabric_direct0_cfg_pad_i160; - input fabric_direct0_cfg_pad_i161; - input fabric_direct0_cfg_pad_i162; - input fabric_direct0_cfg_pad_i163; - input fabric_direct0_cfg_pad_i164; - input fabric_direct0_cfg_pad_i165; - input fabric_direct0_cfg_pad_i166; - input fabric_direct0_cfg_pad_i167; - input fabric_direct0_cfg_pad_i168; - input fabric_direct0_cfg_pad_i169; - input fabric_direct0_cfg_pad_i17; - input fabric_direct0_cfg_pad_i170; - input fabric_direct0_cfg_pad_i171; - input fabric_direct0_cfg_pad_i172; - input fabric_direct0_cfg_pad_i173; - input fabric_direct0_cfg_pad_i174; - input fabric_direct0_cfg_pad_i175; - input fabric_direct0_cfg_pad_i176; - input fabric_direct0_cfg_pad_i177; - input fabric_direct0_cfg_pad_i178; - input fabric_direct0_cfg_pad_i179; - input fabric_direct0_cfg_pad_i18; - input fabric_direct0_cfg_pad_i180; - input fabric_direct0_cfg_pad_i181; - input fabric_direct0_cfg_pad_i182; - input fabric_direct0_cfg_pad_i183; - input fabric_direct0_cfg_pad_i184; - input fabric_direct0_cfg_pad_i185; - input fabric_direct0_cfg_pad_i186; - input fabric_direct0_cfg_pad_i187; - input fabric_direct0_cfg_pad_i188; - input fabric_direct0_cfg_pad_i189; - input fabric_direct0_cfg_pad_i19; - input fabric_direct0_cfg_pad_i190; - input fabric_direct0_cfg_pad_i191; - input fabric_direct0_cfg_pad_i192; - input fabric_direct0_cfg_pad_i193; - input fabric_direct0_cfg_pad_i194; - input fabric_direct0_cfg_pad_i195; - input fabric_direct0_cfg_pad_i196; - input fabric_direct0_cfg_pad_i197; - input fabric_direct0_cfg_pad_i198; - input fabric_direct0_cfg_pad_i199; - input fabric_direct0_cfg_pad_i2; - input fabric_direct0_cfg_pad_i20; - input fabric_direct0_cfg_pad_i200; - input fabric_direct0_cfg_pad_i201; - input fabric_direct0_cfg_pad_i202; - input fabric_direct0_cfg_pad_i203; - input fabric_direct0_cfg_pad_i204; - input fabric_direct0_cfg_pad_i205; - input fabric_direct0_cfg_pad_i206; - input fabric_direct0_cfg_pad_i207; - input fabric_direct0_cfg_pad_i208; - input fabric_direct0_cfg_pad_i209; - input fabric_direct0_cfg_pad_i21; - input fabric_direct0_cfg_pad_i210; - input fabric_direct0_cfg_pad_i211; - input fabric_direct0_cfg_pad_i212; - input fabric_direct0_cfg_pad_i213; - input fabric_direct0_cfg_pad_i214; - input fabric_direct0_cfg_pad_i215; - input fabric_direct0_cfg_pad_i216; - input fabric_direct0_cfg_pad_i217; - input fabric_direct0_cfg_pad_i218; - input fabric_direct0_cfg_pad_i219; - input fabric_direct0_cfg_pad_i22; - input fabric_direct0_cfg_pad_i220; - input fabric_direct0_cfg_pad_i221; - input fabric_direct0_cfg_pad_i222; - input fabric_direct0_cfg_pad_i223; - input fabric_direct0_cfg_pad_i224; - input fabric_direct0_cfg_pad_i225; - input fabric_direct0_cfg_pad_i226; - input fabric_direct0_cfg_pad_i227; - input fabric_direct0_cfg_pad_i228; - input fabric_direct0_cfg_pad_i229; - input fabric_direct0_cfg_pad_i23; - input fabric_direct0_cfg_pad_i230; - input fabric_direct0_cfg_pad_i231; - input fabric_direct0_cfg_pad_i232; - input fabric_direct0_cfg_pad_i233; - input fabric_direct0_cfg_pad_i234; - input fabric_direct0_cfg_pad_i235; - input fabric_direct0_cfg_pad_i236; - input fabric_direct0_cfg_pad_i237; - input fabric_direct0_cfg_pad_i238; - input fabric_direct0_cfg_pad_i239; - input fabric_direct0_cfg_pad_i24; - input fabric_direct0_cfg_pad_i240; - input fabric_direct0_cfg_pad_i241; - input fabric_direct0_cfg_pad_i242; - input fabric_direct0_cfg_pad_i243; - input fabric_direct0_cfg_pad_i244; - input fabric_direct0_cfg_pad_i245; - input fabric_direct0_cfg_pad_i246; - input fabric_direct0_cfg_pad_i247; - input fabric_direct0_cfg_pad_i248; - input fabric_direct0_cfg_pad_i249; - input fabric_direct0_cfg_pad_i25; - input fabric_direct0_cfg_pad_i250; - input fabric_direct0_cfg_pad_i251; - input fabric_direct0_cfg_pad_i252; - input fabric_direct0_cfg_pad_i253; - input fabric_direct0_cfg_pad_i254; - input fabric_direct0_cfg_pad_i255; - input fabric_direct0_cfg_pad_i256; - input fabric_direct0_cfg_pad_i257; - input fabric_direct0_cfg_pad_i258; - input fabric_direct0_cfg_pad_i259; - input fabric_direct0_cfg_pad_i26; - input fabric_direct0_cfg_pad_i260; - input fabric_direct0_cfg_pad_i261; - input fabric_direct0_cfg_pad_i262; - input fabric_direct0_cfg_pad_i263; - input fabric_direct0_cfg_pad_i264; - input fabric_direct0_cfg_pad_i265; - input fabric_direct0_cfg_pad_i266; - input fabric_direct0_cfg_pad_i267; - input fabric_direct0_cfg_pad_i268; - input fabric_direct0_cfg_pad_i269; - input fabric_direct0_cfg_pad_i27; - input fabric_direct0_cfg_pad_i270; - input fabric_direct0_cfg_pad_i271; - input fabric_direct0_cfg_pad_i272; - input fabric_direct0_cfg_pad_i273; - input fabric_direct0_cfg_pad_i274; - input fabric_direct0_cfg_pad_i275; - input fabric_direct0_cfg_pad_i276; - input fabric_direct0_cfg_pad_i277; - input fabric_direct0_cfg_pad_i278; - input fabric_direct0_cfg_pad_i279; - input fabric_direct0_cfg_pad_i28; - input fabric_direct0_cfg_pad_i280; - input fabric_direct0_cfg_pad_i281; - input fabric_direct0_cfg_pad_i282; - input fabric_direct0_cfg_pad_i283; - input fabric_direct0_cfg_pad_i284; - input fabric_direct0_cfg_pad_i285; - input fabric_direct0_cfg_pad_i286; - input fabric_direct0_cfg_pad_i287; - input fabric_direct0_cfg_pad_i288; - input fabric_direct0_cfg_pad_i289; - input fabric_direct0_cfg_pad_i29; - input fabric_direct0_cfg_pad_i290; - input fabric_direct0_cfg_pad_i291; - input fabric_direct0_cfg_pad_i292; - input fabric_direct0_cfg_pad_i293; - input fabric_direct0_cfg_pad_i294; - input fabric_direct0_cfg_pad_i295; - input fabric_direct0_cfg_pad_i296; - input fabric_direct0_cfg_pad_i297; - input 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fabric_direct0_cfg_pad_i710; - input fabric_direct0_cfg_pad_i711; - input fabric_direct0_cfg_pad_i712; - input fabric_direct0_cfg_pad_i713; - input fabric_direct0_cfg_pad_i714; - input fabric_direct0_cfg_pad_i715; - input fabric_direct0_cfg_pad_i716; - input fabric_direct0_cfg_pad_i717; - input fabric_direct0_cfg_pad_i718; - input fabric_direct0_cfg_pad_i719; - input fabric_direct0_cfg_pad_i72; - input fabric_direct0_cfg_pad_i720; - input fabric_direct0_cfg_pad_i73; - input fabric_direct0_cfg_pad_i74; - input fabric_direct0_cfg_pad_i75; - input fabric_direct0_cfg_pad_i76; - input fabric_direct0_cfg_pad_i77; - input fabric_direct0_cfg_pad_i78; - input fabric_direct0_cfg_pad_i79; - input fabric_direct0_cfg_pad_i8; - input fabric_direct0_cfg_pad_i80; - input fabric_direct0_cfg_pad_i81; - input fabric_direct0_cfg_pad_i82; - input fabric_direct0_cfg_pad_i83; - input fabric_direct0_cfg_pad_i84; - input fabric_direct0_cfg_pad_i85; - input fabric_direct0_cfg_pad_i86; - input fabric_direct0_cfg_pad_i87; - input fabric_direct0_cfg_pad_i88; - input fabric_direct0_cfg_pad_i89; - input fabric_direct0_cfg_pad_i9; - input fabric_direct0_cfg_pad_i90; - input fabric_direct0_cfg_pad_i91; - input fabric_direct0_cfg_pad_i92; - input fabric_direct0_cfg_pad_i93; - input fabric_direct0_cfg_pad_i94; - input fabric_direct0_cfg_pad_i95; - input fabric_direct0_cfg_pad_i96; - input fabric_direct0_cfg_pad_i97; - input fabric_direct0_cfg_pad_i98; - input fabric_direct0_cfg_pad_i99; - input fabric_direct0_clock_fabric_i1; - input fabric_direct0_clock_fabric_i2; - input fabric_direct0_clock_fabric_i3; - input fabric_direct0_clock_fabric_i4; - input fabric_direct0_di_ena_i1; - input fabric_direct0_di_ena_i10; - input fabric_direct0_di_ena_i11; - input fabric_direct0_di_ena_i12; - input fabric_direct0_di_ena_i13; - input fabric_direct0_di_ena_i14; - input fabric_direct0_di_ena_i15; - input fabric_direct0_di_ena_i16; - input fabric_direct0_di_ena_i17; - input fabric_direct0_di_ena_i18; - input fabric_direct0_di_ena_i19; - input fabric_direct0_di_ena_i2; - input fabric_direct0_di_ena_i20; - input fabric_direct0_di_ena_i21; - input fabric_direct0_di_ena_i22; - input fabric_direct0_di_ena_i23; - input fabric_direct0_di_ena_i24; - input fabric_direct0_di_ena_i3; - input fabric_direct0_di_ena_i4; - input fabric_direct0_di_ena_i5; - input fabric_direct0_di_ena_i6; - input fabric_direct0_di_ena_i7; - input fabric_direct0_di_ena_i8; - input fabric_direct0_di_ena_i9; - output fabric_direct0_di_o1; - output fabric_direct0_di_o10; - output fabric_direct0_di_o11; - output fabric_direct0_di_o12; - output fabric_direct0_di_o13; - output fabric_direct0_di_o14; - output fabric_direct0_di_o15; - output fabric_direct0_di_o16; - output fabric_direct0_di_o17; - output fabric_direct0_di_o18; - output fabric_direct0_di_o19; - output fabric_direct0_di_o2; - output fabric_direct0_di_o20; - output fabric_direct0_di_o21; - output fabric_direct0_di_o22; - output fabric_direct0_di_o23; - output fabric_direct0_di_o24; - output fabric_direct0_di_o3; - output fabric_direct0_di_o4; - output fabric_direct0_di_o5; - output fabric_direct0_di_o6; - output fabric_direct0_di_o7; - output fabric_direct0_di_o8; - output fabric_direct0_di_o9; - input fabric_direct0_di_rs_i1; - input fabric_direct0_di_rs_i10; - input fabric_direct0_di_rs_i11; - input fabric_direct0_di_rs_i12; - input fabric_direct0_di_rs_i13; - input fabric_direct0_di_rs_i14; - input fabric_direct0_di_rs_i15; - input fabric_direct0_di_rs_i16; - input fabric_direct0_di_rs_i17; - input fabric_direct0_di_rs_i18; - input fabric_direct0_di_rs_i19; - input fabric_direct0_di_rs_i2; - input fabric_direct0_di_rs_i20; - input fabric_direct0_di_rs_i21; - input fabric_direct0_di_rs_i22; - input fabric_direct0_di_rs_i23; - input fabric_direct0_di_rs_i24; - input fabric_direct0_di_rs_i3; - input fabric_direct0_di_rs_i4; - input fabric_direct0_di_rs_i5; - input fabric_direct0_di_rs_i6; - input fabric_direct0_di_rs_i7; - input fabric_direct0_di_rs_i8; - input fabric_direct0_di_rs_i9; - input fabric_direct0_do_ena_i1; - input fabric_direct0_do_ena_i10; - input fabric_direct0_do_ena_i11; - input fabric_direct0_do_ena_i12; - input fabric_direct0_do_ena_i13; - input fabric_direct0_do_ena_i14; - input fabric_direct0_do_ena_i15; - input fabric_direct0_do_ena_i16; - input fabric_direct0_do_ena_i17; - input fabric_direct0_do_ena_i18; - input fabric_direct0_do_ena_i19; - input fabric_direct0_do_ena_i2; - input fabric_direct0_do_ena_i20; - input fabric_direct0_do_ena_i21; - input fabric_direct0_do_ena_i22; - input fabric_direct0_do_ena_i23; - input fabric_direct0_do_ena_i24; - input fabric_direct0_do_ena_i3; - input fabric_direct0_do_ena_i4; - input fabric_direct0_do_ena_i5; - input fabric_direct0_do_ena_i6; - input fabric_direct0_do_ena_i7; - input fabric_direct0_do_ena_i8; - input fabric_direct0_do_ena_i9; - input fabric_direct0_do_i1; - input fabric_direct0_do_i10; - input fabric_direct0_do_i11; - input fabric_direct0_do_i12; - input fabric_direct0_do_i13; - input fabric_direct0_do_i14; - input fabric_direct0_do_i15; - input fabric_direct0_do_i16; - input fabric_direct0_do_i17; - input fabric_direct0_do_i18; - input fabric_direct0_do_i19; - input fabric_direct0_do_i2; - input fabric_direct0_do_i20; - input fabric_direct0_do_i21; - input fabric_direct0_do_i22; - input fabric_direct0_do_i23; - input fabric_direct0_do_i24; - input fabric_direct0_do_i3; - input fabric_direct0_do_i4; - input fabric_direct0_do_i5; - input fabric_direct0_do_i6; - input fabric_direct0_do_i7; - input fabric_direct0_do_i8; - input fabric_direct0_do_i9; - input fabric_direct0_do_rs_i1; - input fabric_direct0_do_rs_i10; - input fabric_direct0_do_rs_i11; - input fabric_direct0_do_rs_i12; - input fabric_direct0_do_rs_i13; - input fabric_direct0_do_rs_i14; - input fabric_direct0_do_rs_i15; - input fabric_direct0_do_rs_i16; - input fabric_direct0_do_rs_i17; - input fabric_direct0_do_rs_i18; - input fabric_direct0_do_rs_i19; - input fabric_direct0_do_rs_i2; - input fabric_direct0_do_rs_i20; - input fabric_direct0_do_rs_i21; - input fabric_direct0_do_rs_i22; - input fabric_direct0_do_rs_i23; - input fabric_direct0_do_rs_i24; - input fabric_direct0_do_rs_i3; - input fabric_direct0_do_rs_i4; - input fabric_direct0_do_rs_i5; - input fabric_direct0_do_rs_i6; - input fabric_direct0_do_rs_i7; - input fabric_direct0_do_rs_i8; - input fabric_direct0_do_rs_i9; - input fabric_direct0_loopback_en_i; - input fabric_direct0_loopback_mux_i; - input fabric_direct0_oe_ena_i1; - input fabric_direct0_oe_ena_i10; - input fabric_direct0_oe_ena_i11; - input fabric_direct0_oe_ena_i12; - input fabric_direct0_oe_ena_i13; - input fabric_direct0_oe_ena_i14; - input fabric_direct0_oe_ena_i15; - input fabric_direct0_oe_ena_i16; - input fabric_direct0_oe_ena_i17; - input fabric_direct0_oe_ena_i18; - input fabric_direct0_oe_ena_i19; - input fabric_direct0_oe_ena_i2; - input fabric_direct0_oe_ena_i20; - input fabric_direct0_oe_ena_i21; - input fabric_direct0_oe_ena_i22; - input fabric_direct0_oe_ena_i23; - input fabric_direct0_oe_ena_i24; - input fabric_direct0_oe_ena_i3; - input fabric_direct0_oe_ena_i4; - input fabric_direct0_oe_ena_i5; - input fabric_direct0_oe_ena_i6; - input fabric_direct0_oe_ena_i7; - input fabric_direct0_oe_ena_i8; - input fabric_direct0_oe_ena_i9; - input fabric_direct0_oe_i1; - input fabric_direct0_oe_i10; - input fabric_direct0_oe_i11; - input fabric_direct0_oe_i12; - input fabric_direct0_oe_i13; - input fabric_direct0_oe_i14; - input fabric_direct0_oe_i15; - input fabric_direct0_oe_i16; - input fabric_direct0_oe_i17; - input fabric_direct0_oe_i18; - input fabric_direct0_oe_i19; - input fabric_direct0_oe_i2; - input fabric_direct0_oe_i20; - input fabric_direct0_oe_i21; - input fabric_direct0_oe_i22; - input fabric_direct0_oe_i23; - input fabric_direct0_oe_i24; - input fabric_direct0_oe_i3; - input fabric_direct0_oe_i4; - input fabric_direct0_oe_i5; - input fabric_direct0_oe_i6; - input fabric_direct0_oe_i7; - input fabric_direct0_oe_i8; - input fabric_direct0_oe_i9; - input fabric_direct0_oe_rs_i1; - input fabric_direct0_oe_rs_i10; - input fabric_direct0_oe_rs_i11; - input fabric_direct0_oe_rs_i12; - input fabric_direct0_oe_rs_i13; - input fabric_direct0_oe_rs_i14; - input fabric_direct0_oe_rs_i15; - input fabric_direct0_oe_rs_i16; - input fabric_direct0_oe_rs_i17; - input fabric_direct0_oe_rs_i18; - input fabric_direct0_oe_rs_i19; - input fabric_direct0_oe_rs_i2; - input fabric_direct0_oe_rs_i20; - input fabric_direct0_oe_rs_i21; - input fabric_direct0_oe_rs_i22; - input fabric_direct0_oe_rs_i23; - input fabric_direct0_oe_rs_i24; - input fabric_direct0_oe_rs_i3; - input fabric_direct0_oe_rs_i4; - input fabric_direct0_oe_rs_i5; - input fabric_direct0_oe_rs_i6; - input fabric_direct0_oe_rs_i7; - input fabric_direct0_oe_rs_i8; - input fabric_direct0_oe_rs_i9; - input fabric_direct0_scan_en_i; - input fabric_direct1_cfg_bank_i1; - input fabric_direct1_cfg_bank_i2; - input fabric_direct1_cfg_bank_i3; - input fabric_direct1_cfg_bank_i4; - input fabric_direct1_cfg_pad_i1; - input fabric_direct1_cfg_pad_i10; - input fabric_direct1_cfg_pad_i100; - input fabric_direct1_cfg_pad_i101; - input fabric_direct1_cfg_pad_i102; - input fabric_direct1_cfg_pad_i103; - input fabric_direct1_cfg_pad_i104; - input fabric_direct1_cfg_pad_i105; - input fabric_direct1_cfg_pad_i106; - input fabric_direct1_cfg_pad_i107; - input fabric_direct1_cfg_pad_i108; - input fabric_direct1_cfg_pad_i109; - input fabric_direct1_cfg_pad_i11; - input fabric_direct1_cfg_pad_i110; - input fabric_direct1_cfg_pad_i111; - input fabric_direct1_cfg_pad_i112; - input fabric_direct1_cfg_pad_i113; - input fabric_direct1_cfg_pad_i114; - input fabric_direct1_cfg_pad_i115; - input fabric_direct1_cfg_pad_i116; - input fabric_direct1_cfg_pad_i117; - input fabric_direct1_cfg_pad_i118; - input fabric_direct1_cfg_pad_i119; - input fabric_direct1_cfg_pad_i12; - input fabric_direct1_cfg_pad_i120; - input fabric_direct1_cfg_pad_i121; - input fabric_direct1_cfg_pad_i122; - input fabric_direct1_cfg_pad_i123; - input fabric_direct1_cfg_pad_i124; - input fabric_direct1_cfg_pad_i125; - input fabric_direct1_cfg_pad_i126; - input fabric_direct1_cfg_pad_i127; - input fabric_direct1_cfg_pad_i128; - input fabric_direct1_cfg_pad_i129; - input fabric_direct1_cfg_pad_i13; - input fabric_direct1_cfg_pad_i130; - input fabric_direct1_cfg_pad_i131; - input fabric_direct1_cfg_pad_i132; - input fabric_direct1_cfg_pad_i133; - input fabric_direct1_cfg_pad_i134; - input fabric_direct1_cfg_pad_i135; - input fabric_direct1_cfg_pad_i136; - input fabric_direct1_cfg_pad_i137; - input fabric_direct1_cfg_pad_i138; - input fabric_direct1_cfg_pad_i139; - input fabric_direct1_cfg_pad_i14; - input fabric_direct1_cfg_pad_i140; - input fabric_direct1_cfg_pad_i141; - input fabric_direct1_cfg_pad_i142; - input fabric_direct1_cfg_pad_i143; - input fabric_direct1_cfg_pad_i144; - input fabric_direct1_cfg_pad_i145; - input fabric_direct1_cfg_pad_i146; - input fabric_direct1_cfg_pad_i147; - input fabric_direct1_cfg_pad_i148; - input fabric_direct1_cfg_pad_i149; - input fabric_direct1_cfg_pad_i15; - input fabric_direct1_cfg_pad_i150; - input fabric_direct1_cfg_pad_i151; - input fabric_direct1_cfg_pad_i152; - input fabric_direct1_cfg_pad_i153; - input fabric_direct1_cfg_pad_i154; - input fabric_direct1_cfg_pad_i155; - input fabric_direct1_cfg_pad_i156; - input fabric_direct1_cfg_pad_i157; - input fabric_direct1_cfg_pad_i158; - input fabric_direct1_cfg_pad_i159; - input fabric_direct1_cfg_pad_i16; - input fabric_direct1_cfg_pad_i160; - input fabric_direct1_cfg_pad_i161; - input fabric_direct1_cfg_pad_i162; - input fabric_direct1_cfg_pad_i163; - input fabric_direct1_cfg_pad_i164; - input fabric_direct1_cfg_pad_i165; - input fabric_direct1_cfg_pad_i166; - input fabric_direct1_cfg_pad_i167; - input fabric_direct1_cfg_pad_i168; - input fabric_direct1_cfg_pad_i169; - input fabric_direct1_cfg_pad_i17; - input fabric_direct1_cfg_pad_i170; - input fabric_direct1_cfg_pad_i171; - input fabric_direct1_cfg_pad_i172; - input fabric_direct1_cfg_pad_i173; - input fabric_direct1_cfg_pad_i174; - input fabric_direct1_cfg_pad_i175; - input fabric_direct1_cfg_pad_i176; - input fabric_direct1_cfg_pad_i177; - input fabric_direct1_cfg_pad_i178; - input fabric_direct1_cfg_pad_i179; - input fabric_direct1_cfg_pad_i18; - input fabric_direct1_cfg_pad_i180; - input fabric_direct1_cfg_pad_i181; - input fabric_direct1_cfg_pad_i182; - input fabric_direct1_cfg_pad_i183; - input fabric_direct1_cfg_pad_i184; - input fabric_direct1_cfg_pad_i185; - input fabric_direct1_cfg_pad_i186; - input fabric_direct1_cfg_pad_i187; - input fabric_direct1_cfg_pad_i188; - input fabric_direct1_cfg_pad_i189; - input fabric_direct1_cfg_pad_i19; - input fabric_direct1_cfg_pad_i190; - input fabric_direct1_cfg_pad_i191; - input fabric_direct1_cfg_pad_i192; - input fabric_direct1_cfg_pad_i193; - input fabric_direct1_cfg_pad_i194; - input fabric_direct1_cfg_pad_i195; - input fabric_direct1_cfg_pad_i196; - input fabric_direct1_cfg_pad_i197; - input fabric_direct1_cfg_pad_i198; - input fabric_direct1_cfg_pad_i199; - input fabric_direct1_cfg_pad_i2; - input fabric_direct1_cfg_pad_i20; - input fabric_direct1_cfg_pad_i200; - input fabric_direct1_cfg_pad_i201; - input fabric_direct1_cfg_pad_i202; - input fabric_direct1_cfg_pad_i203; - input fabric_direct1_cfg_pad_i204; - input fabric_direct1_cfg_pad_i205; - input fabric_direct1_cfg_pad_i206; - input fabric_direct1_cfg_pad_i207; - input fabric_direct1_cfg_pad_i208; - input fabric_direct1_cfg_pad_i209; - input fabric_direct1_cfg_pad_i21; - input fabric_direct1_cfg_pad_i210; - input fabric_direct1_cfg_pad_i211; - input fabric_direct1_cfg_pad_i212; - input fabric_direct1_cfg_pad_i213; - input fabric_direct1_cfg_pad_i214; - input fabric_direct1_cfg_pad_i215; - input fabric_direct1_cfg_pad_i216; - input fabric_direct1_cfg_pad_i217; - input fabric_direct1_cfg_pad_i218; - input fabric_direct1_cfg_pad_i219; - input fabric_direct1_cfg_pad_i22; - input fabric_direct1_cfg_pad_i220; - input fabric_direct1_cfg_pad_i221; - input fabric_direct1_cfg_pad_i222; - input fabric_direct1_cfg_pad_i223; - input fabric_direct1_cfg_pad_i224; - input fabric_direct1_cfg_pad_i225; - input fabric_direct1_cfg_pad_i226; - input fabric_direct1_cfg_pad_i227; - input fabric_direct1_cfg_pad_i228; - input fabric_direct1_cfg_pad_i229; - input fabric_direct1_cfg_pad_i23; - input fabric_direct1_cfg_pad_i230; - input fabric_direct1_cfg_pad_i231; - input fabric_direct1_cfg_pad_i232; - input fabric_direct1_cfg_pad_i233; - input fabric_direct1_cfg_pad_i234; - input fabric_direct1_cfg_pad_i235; - input fabric_direct1_cfg_pad_i236; - input fabric_direct1_cfg_pad_i237; - input fabric_direct1_cfg_pad_i238; - input fabric_direct1_cfg_pad_i239; - input fabric_direct1_cfg_pad_i24; - input fabric_direct1_cfg_pad_i240; - input fabric_direct1_cfg_pad_i241; - input fabric_direct1_cfg_pad_i242; - input fabric_direct1_cfg_pad_i243; - input fabric_direct1_cfg_pad_i244; - input fabric_direct1_cfg_pad_i245; - input fabric_direct1_cfg_pad_i246; - input fabric_direct1_cfg_pad_i247; - input fabric_direct1_cfg_pad_i248; - input fabric_direct1_cfg_pad_i249; - input fabric_direct1_cfg_pad_i25; - input fabric_direct1_cfg_pad_i250; - input fabric_direct1_cfg_pad_i251; - input fabric_direct1_cfg_pad_i252; - input fabric_direct1_cfg_pad_i253; - input fabric_direct1_cfg_pad_i254; - input fabric_direct1_cfg_pad_i255; - input fabric_direct1_cfg_pad_i256; - input fabric_direct1_cfg_pad_i257; - input fabric_direct1_cfg_pad_i258; - input fabric_direct1_cfg_pad_i259; - input fabric_direct1_cfg_pad_i26; - input fabric_direct1_cfg_pad_i260; - input fabric_direct1_cfg_pad_i261; - input fabric_direct1_cfg_pad_i262; - input fabric_direct1_cfg_pad_i263; - input fabric_direct1_cfg_pad_i264; - input fabric_direct1_cfg_pad_i265; - input fabric_direct1_cfg_pad_i266; - input fabric_direct1_cfg_pad_i267; - input fabric_direct1_cfg_pad_i268; - input fabric_direct1_cfg_pad_i269; - input fabric_direct1_cfg_pad_i27; - input fabric_direct1_cfg_pad_i270; - input fabric_direct1_cfg_pad_i271; - input fabric_direct1_cfg_pad_i272; - input fabric_direct1_cfg_pad_i273; - input fabric_direct1_cfg_pad_i274; - input fabric_direct1_cfg_pad_i275; - input fabric_direct1_cfg_pad_i276; - input fabric_direct1_cfg_pad_i277; - input fabric_direct1_cfg_pad_i278; - input fabric_direct1_cfg_pad_i279; - input fabric_direct1_cfg_pad_i28; - input fabric_direct1_cfg_pad_i280; - input fabric_direct1_cfg_pad_i281; - input fabric_direct1_cfg_pad_i282; - input fabric_direct1_cfg_pad_i283; - input fabric_direct1_cfg_pad_i284; - input fabric_direct1_cfg_pad_i285; - input fabric_direct1_cfg_pad_i286; - input fabric_direct1_cfg_pad_i287; - input fabric_direct1_cfg_pad_i288; - input fabric_direct1_cfg_pad_i289; - input fabric_direct1_cfg_pad_i29; - input fabric_direct1_cfg_pad_i290; - input fabric_direct1_cfg_pad_i291; - input fabric_direct1_cfg_pad_i292; - input fabric_direct1_cfg_pad_i293; - input fabric_direct1_cfg_pad_i294; - input fabric_direct1_cfg_pad_i295; - input fabric_direct1_cfg_pad_i296; - input fabric_direct1_cfg_pad_i297; - input fabric_direct1_cfg_pad_i298; - input fabric_direct1_cfg_pad_i299; - input fabric_direct1_cfg_pad_i3; - input fabric_direct1_cfg_pad_i30; - input fabric_direct1_cfg_pad_i300; - input fabric_direct1_cfg_pad_i301; - input fabric_direct1_cfg_pad_i302; - input fabric_direct1_cfg_pad_i303; - input fabric_direct1_cfg_pad_i304; - input fabric_direct1_cfg_pad_i305; - input fabric_direct1_cfg_pad_i306; - input fabric_direct1_cfg_pad_i307; - input fabric_direct1_cfg_pad_i308; - input fabric_direct1_cfg_pad_i309; - input fabric_direct1_cfg_pad_i31; - input fabric_direct1_cfg_pad_i310; - input fabric_direct1_cfg_pad_i311; - input fabric_direct1_cfg_pad_i312; - input fabric_direct1_cfg_pad_i313; - input fabric_direct1_cfg_pad_i314; - input fabric_direct1_cfg_pad_i315; - input fabric_direct1_cfg_pad_i316; - input fabric_direct1_cfg_pad_i317; - input fabric_direct1_cfg_pad_i318; - input fabric_direct1_cfg_pad_i319; - input fabric_direct1_cfg_pad_i32; - input fabric_direct1_cfg_pad_i320; - input fabric_direct1_cfg_pad_i321; - input fabric_direct1_cfg_pad_i322; - input fabric_direct1_cfg_pad_i323; - input fabric_direct1_cfg_pad_i324; - input fabric_direct1_cfg_pad_i325; - input fabric_direct1_cfg_pad_i326; - input fabric_direct1_cfg_pad_i327; - input fabric_direct1_cfg_pad_i328; - input fabric_direct1_cfg_pad_i329; - input fabric_direct1_cfg_pad_i33; - input fabric_direct1_cfg_pad_i330; - input fabric_direct1_cfg_pad_i331; - input fabric_direct1_cfg_pad_i332; - input fabric_direct1_cfg_pad_i333; - input fabric_direct1_cfg_pad_i334; - input fabric_direct1_cfg_pad_i335; - input fabric_direct1_cfg_pad_i336; - input fabric_direct1_cfg_pad_i337; - input fabric_direct1_cfg_pad_i338; - input fabric_direct1_cfg_pad_i339; - input fabric_direct1_cfg_pad_i34; - input fabric_direct1_cfg_pad_i340; - input fabric_direct1_cfg_pad_i341; - input fabric_direct1_cfg_pad_i342; - input fabric_direct1_cfg_pad_i343; - input fabric_direct1_cfg_pad_i344; - input fabric_direct1_cfg_pad_i345; - input fabric_direct1_cfg_pad_i346; - input fabric_direct1_cfg_pad_i347; - input fabric_direct1_cfg_pad_i348; - input fabric_direct1_cfg_pad_i349; - input fabric_direct1_cfg_pad_i35; - input fabric_direct1_cfg_pad_i350; - input fabric_direct1_cfg_pad_i351; - input fabric_direct1_cfg_pad_i352; - input fabric_direct1_cfg_pad_i353; - input fabric_direct1_cfg_pad_i354; - input fabric_direct1_cfg_pad_i355; - input fabric_direct1_cfg_pad_i356; - input fabric_direct1_cfg_pad_i357; - input fabric_direct1_cfg_pad_i358; - input fabric_direct1_cfg_pad_i359; - input fabric_direct1_cfg_pad_i36; - input fabric_direct1_cfg_pad_i360; - input fabric_direct1_cfg_pad_i361; - input fabric_direct1_cfg_pad_i362; - input fabric_direct1_cfg_pad_i363; - input fabric_direct1_cfg_pad_i364; - input fabric_direct1_cfg_pad_i365; - input fabric_direct1_cfg_pad_i366; - input fabric_direct1_cfg_pad_i367; - input fabric_direct1_cfg_pad_i368; - input fabric_direct1_cfg_pad_i369; - input fabric_direct1_cfg_pad_i37; - input fabric_direct1_cfg_pad_i370; - input fabric_direct1_cfg_pad_i371; - input fabric_direct1_cfg_pad_i372; - input fabric_direct1_cfg_pad_i373; - input fabric_direct1_cfg_pad_i374; - input fabric_direct1_cfg_pad_i375; - input fabric_direct1_cfg_pad_i376; - input fabric_direct1_cfg_pad_i377; - input fabric_direct1_cfg_pad_i378; - input fabric_direct1_cfg_pad_i379; - input fabric_direct1_cfg_pad_i38; - input fabric_direct1_cfg_pad_i380; - input fabric_direct1_cfg_pad_i381; - input fabric_direct1_cfg_pad_i382; - input fabric_direct1_cfg_pad_i383; - input fabric_direct1_cfg_pad_i384; - input fabric_direct1_cfg_pad_i385; - input fabric_direct1_cfg_pad_i386; - input fabric_direct1_cfg_pad_i387; - input fabric_direct1_cfg_pad_i388; - input fabric_direct1_cfg_pad_i389; - input fabric_direct1_cfg_pad_i39; - input fabric_direct1_cfg_pad_i390; - input fabric_direct1_cfg_pad_i391; - input fabric_direct1_cfg_pad_i392; - input fabric_direct1_cfg_pad_i393; - input fabric_direct1_cfg_pad_i394; - input fabric_direct1_cfg_pad_i395; - input fabric_direct1_cfg_pad_i396; - input fabric_direct1_cfg_pad_i397; - input fabric_direct1_cfg_pad_i398; - input fabric_direct1_cfg_pad_i399; - input fabric_direct1_cfg_pad_i4; - input fabric_direct1_cfg_pad_i40; - input fabric_direct1_cfg_pad_i400; - input fabric_direct1_cfg_pad_i401; - input fabric_direct1_cfg_pad_i402; - input fabric_direct1_cfg_pad_i403; - input fabric_direct1_cfg_pad_i404; - input fabric_direct1_cfg_pad_i405; - input fabric_direct1_cfg_pad_i406; - input fabric_direct1_cfg_pad_i407; - input fabric_direct1_cfg_pad_i408; - input fabric_direct1_cfg_pad_i409; - input fabric_direct1_cfg_pad_i41; - input fabric_direct1_cfg_pad_i410; - input fabric_direct1_cfg_pad_i411; - input fabric_direct1_cfg_pad_i412; - input fabric_direct1_cfg_pad_i413; - input fabric_direct1_cfg_pad_i414; - input fabric_direct1_cfg_pad_i415; - input fabric_direct1_cfg_pad_i416; - input fabric_direct1_cfg_pad_i417; - input fabric_direct1_cfg_pad_i418; - input fabric_direct1_cfg_pad_i419; - input fabric_direct1_cfg_pad_i42; - input fabric_direct1_cfg_pad_i420; - input fabric_direct1_cfg_pad_i421; - input fabric_direct1_cfg_pad_i422; - input fabric_direct1_cfg_pad_i423; - input fabric_direct1_cfg_pad_i424; - input fabric_direct1_cfg_pad_i425; - input fabric_direct1_cfg_pad_i426; - input fabric_direct1_cfg_pad_i427; - input fabric_direct1_cfg_pad_i428; - input fabric_direct1_cfg_pad_i429; - input fabric_direct1_cfg_pad_i43; - input fabric_direct1_cfg_pad_i430; - input fabric_direct1_cfg_pad_i431; - input fabric_direct1_cfg_pad_i432; - input fabric_direct1_cfg_pad_i433; - input fabric_direct1_cfg_pad_i434; - input fabric_direct1_cfg_pad_i435; - input fabric_direct1_cfg_pad_i436; - input fabric_direct1_cfg_pad_i437; - input fabric_direct1_cfg_pad_i438; - input fabric_direct1_cfg_pad_i439; - input fabric_direct1_cfg_pad_i44; - input fabric_direct1_cfg_pad_i440; - input fabric_direct1_cfg_pad_i441; - input fabric_direct1_cfg_pad_i442; - input fabric_direct1_cfg_pad_i443; - input fabric_direct1_cfg_pad_i444; - input fabric_direct1_cfg_pad_i445; - input fabric_direct1_cfg_pad_i446; - input fabric_direct1_cfg_pad_i447; - input fabric_direct1_cfg_pad_i448; - input fabric_direct1_cfg_pad_i449; - input fabric_direct1_cfg_pad_i45; - input fabric_direct1_cfg_pad_i450; - input fabric_direct1_cfg_pad_i451; - input fabric_direct1_cfg_pad_i452; - input fabric_direct1_cfg_pad_i453; - input fabric_direct1_cfg_pad_i454; - input fabric_direct1_cfg_pad_i455; - input fabric_direct1_cfg_pad_i456; - input fabric_direct1_cfg_pad_i457; - input fabric_direct1_cfg_pad_i458; - input fabric_direct1_cfg_pad_i459; - input fabric_direct1_cfg_pad_i46; - input fabric_direct1_cfg_pad_i460; - input fabric_direct1_cfg_pad_i461; - input fabric_direct1_cfg_pad_i462; - input fabric_direct1_cfg_pad_i463; - input fabric_direct1_cfg_pad_i464; - input fabric_direct1_cfg_pad_i465; - input fabric_direct1_cfg_pad_i466; - input fabric_direct1_cfg_pad_i467; - input fabric_direct1_cfg_pad_i468; - input fabric_direct1_cfg_pad_i469; - input fabric_direct1_cfg_pad_i47; - input fabric_direct1_cfg_pad_i470; - input fabric_direct1_cfg_pad_i471; - input fabric_direct1_cfg_pad_i472; - input fabric_direct1_cfg_pad_i473; - input fabric_direct1_cfg_pad_i474; - input fabric_direct1_cfg_pad_i475; - input fabric_direct1_cfg_pad_i476; - input fabric_direct1_cfg_pad_i477; - input fabric_direct1_cfg_pad_i478; - input fabric_direct1_cfg_pad_i479; - input fabric_direct1_cfg_pad_i48; - input fabric_direct1_cfg_pad_i480; - input fabric_direct1_cfg_pad_i49; - input fabric_direct1_cfg_pad_i5; - input fabric_direct1_cfg_pad_i50; - input fabric_direct1_cfg_pad_i51; - input fabric_direct1_cfg_pad_i52; - input fabric_direct1_cfg_pad_i53; - input fabric_direct1_cfg_pad_i54; - input fabric_direct1_cfg_pad_i55; - input fabric_direct1_cfg_pad_i56; - input fabric_direct1_cfg_pad_i57; - input fabric_direct1_cfg_pad_i58; - input fabric_direct1_cfg_pad_i59; - input fabric_direct1_cfg_pad_i6; - input fabric_direct1_cfg_pad_i60; - input fabric_direct1_cfg_pad_i61; - input fabric_direct1_cfg_pad_i62; - input fabric_direct1_cfg_pad_i63; - input fabric_direct1_cfg_pad_i64; - input fabric_direct1_cfg_pad_i65; - input fabric_direct1_cfg_pad_i66; - input fabric_direct1_cfg_pad_i67; - input fabric_direct1_cfg_pad_i68; - input fabric_direct1_cfg_pad_i69; - input fabric_direct1_cfg_pad_i7; - input fabric_direct1_cfg_pad_i70; - input fabric_direct1_cfg_pad_i71; - input fabric_direct1_cfg_pad_i72; - input fabric_direct1_cfg_pad_i73; - input fabric_direct1_cfg_pad_i74; - input fabric_direct1_cfg_pad_i75; - input fabric_direct1_cfg_pad_i76; - input fabric_direct1_cfg_pad_i77; - input fabric_direct1_cfg_pad_i78; - input fabric_direct1_cfg_pad_i79; - input fabric_direct1_cfg_pad_i8; - input fabric_direct1_cfg_pad_i80; - input fabric_direct1_cfg_pad_i81; - input fabric_direct1_cfg_pad_i82; - input fabric_direct1_cfg_pad_i83; - input fabric_direct1_cfg_pad_i84; - input fabric_direct1_cfg_pad_i85; - input fabric_direct1_cfg_pad_i86; - input fabric_direct1_cfg_pad_i87; - input fabric_direct1_cfg_pad_i88; - input fabric_direct1_cfg_pad_i89; - input fabric_direct1_cfg_pad_i9; - input fabric_direct1_cfg_pad_i90; - input fabric_direct1_cfg_pad_i91; - input fabric_direct1_cfg_pad_i92; - input fabric_direct1_cfg_pad_i93; - input fabric_direct1_cfg_pad_i94; - input fabric_direct1_cfg_pad_i95; - input fabric_direct1_cfg_pad_i96; - input fabric_direct1_cfg_pad_i97; - input fabric_direct1_cfg_pad_i98; - input fabric_direct1_cfg_pad_i99; - input fabric_direct1_clock_fabric_i1; - input fabric_direct1_clock_fabric_i2; - input fabric_direct1_clock_fabric_i3; - input fabric_direct1_clock_fabric_i4; - input fabric_direct1_di_ena_i1; - input fabric_direct1_di_ena_i10; - input fabric_direct1_di_ena_i11; - input fabric_direct1_di_ena_i12; - input fabric_direct1_di_ena_i13; - input fabric_direct1_di_ena_i14; - input fabric_direct1_di_ena_i15; - input fabric_direct1_di_ena_i16; - input fabric_direct1_di_ena_i2; - input fabric_direct1_di_ena_i3; - input fabric_direct1_di_ena_i4; - input fabric_direct1_di_ena_i5; - input fabric_direct1_di_ena_i6; - input fabric_direct1_di_ena_i7; - input fabric_direct1_di_ena_i8; - input fabric_direct1_di_ena_i9; - output fabric_direct1_di_o1; - output fabric_direct1_di_o10; - output fabric_direct1_di_o11; - output fabric_direct1_di_o12; - output fabric_direct1_di_o13; - output fabric_direct1_di_o14; - output fabric_direct1_di_o15; - output fabric_direct1_di_o16; - output fabric_direct1_di_o2; - output fabric_direct1_di_o3; - output fabric_direct1_di_o4; - output fabric_direct1_di_o5; - output fabric_direct1_di_o6; - output fabric_direct1_di_o7; - output fabric_direct1_di_o8; - output fabric_direct1_di_o9; - input fabric_direct1_di_rs_i1; - input fabric_direct1_di_rs_i10; - input fabric_direct1_di_rs_i11; - input fabric_direct1_di_rs_i12; - input fabric_direct1_di_rs_i13; - input fabric_direct1_di_rs_i14; - input fabric_direct1_di_rs_i15; - input fabric_direct1_di_rs_i16; - input fabric_direct1_di_rs_i2; - input fabric_direct1_di_rs_i3; - input fabric_direct1_di_rs_i4; - input fabric_direct1_di_rs_i5; - input fabric_direct1_di_rs_i6; - input fabric_direct1_di_rs_i7; - input fabric_direct1_di_rs_i8; - input fabric_direct1_di_rs_i9; - input fabric_direct1_do_ena_i1; - input fabric_direct1_do_ena_i10; - input fabric_direct1_do_ena_i11; - input fabric_direct1_do_ena_i12; - input fabric_direct1_do_ena_i13; - input fabric_direct1_do_ena_i14; - input fabric_direct1_do_ena_i15; - input fabric_direct1_do_ena_i16; - input fabric_direct1_do_ena_i2; - input fabric_direct1_do_ena_i3; - input fabric_direct1_do_ena_i4; - input fabric_direct1_do_ena_i5; - input fabric_direct1_do_ena_i6; - input fabric_direct1_do_ena_i7; - input fabric_direct1_do_ena_i8; - input fabric_direct1_do_ena_i9; - input fabric_direct1_do_i1; - input fabric_direct1_do_i10; - input fabric_direct1_do_i11; - input fabric_direct1_do_i12; - input fabric_direct1_do_i13; - input fabric_direct1_do_i14; - input fabric_direct1_do_i15; - input fabric_direct1_do_i16; - input fabric_direct1_do_i2; - input fabric_direct1_do_i3; - input fabric_direct1_do_i4; - input fabric_direct1_do_i5; - input fabric_direct1_do_i6; - input fabric_direct1_do_i7; - input fabric_direct1_do_i8; - input fabric_direct1_do_i9; - input fabric_direct1_do_rs_i1; - input fabric_direct1_do_rs_i10; - input fabric_direct1_do_rs_i11; - input fabric_direct1_do_rs_i12; - input fabric_direct1_do_rs_i13; - input fabric_direct1_do_rs_i14; - input fabric_direct1_do_rs_i15; - input fabric_direct1_do_rs_i16; - input fabric_direct1_do_rs_i2; - input fabric_direct1_do_rs_i3; - input fabric_direct1_do_rs_i4; - input fabric_direct1_do_rs_i5; - input fabric_direct1_do_rs_i6; - input fabric_direct1_do_rs_i7; - input fabric_direct1_do_rs_i8; - input fabric_direct1_do_rs_i9; - input fabric_direct1_loopback_en_i; - input fabric_direct1_loopback_mux_i; - input fabric_direct1_oe_ena_i1; - input fabric_direct1_oe_ena_i10; - input fabric_direct1_oe_ena_i11; - input fabric_direct1_oe_ena_i12; - input fabric_direct1_oe_ena_i13; - input fabric_direct1_oe_ena_i14; - input fabric_direct1_oe_ena_i15; - input fabric_direct1_oe_ena_i16; - input fabric_direct1_oe_ena_i2; - input fabric_direct1_oe_ena_i3; - input fabric_direct1_oe_ena_i4; - input fabric_direct1_oe_ena_i5; - input fabric_direct1_oe_ena_i6; - input fabric_direct1_oe_ena_i7; - input fabric_direct1_oe_ena_i8; - input fabric_direct1_oe_ena_i9; - input fabric_direct1_oe_i1; - input fabric_direct1_oe_i10; - input fabric_direct1_oe_i11; - input fabric_direct1_oe_i12; - input fabric_direct1_oe_i13; - input fabric_direct1_oe_i14; - input fabric_direct1_oe_i15; - input fabric_direct1_oe_i16; - input fabric_direct1_oe_i2; - input fabric_direct1_oe_i3; - input fabric_direct1_oe_i4; - input fabric_direct1_oe_i5; - input fabric_direct1_oe_i6; - input fabric_direct1_oe_i7; - input fabric_direct1_oe_i8; - input fabric_direct1_oe_i9; - input fabric_direct1_oe_rs_i1; - input fabric_direct1_oe_rs_i10; - input fabric_direct1_oe_rs_i11; - input fabric_direct1_oe_rs_i12; - input fabric_direct1_oe_rs_i13; - input fabric_direct1_oe_rs_i14; - input fabric_direct1_oe_rs_i15; - input fabric_direct1_oe_rs_i16; - input fabric_direct1_oe_rs_i2; - input fabric_direct1_oe_rs_i3; - input fabric_direct1_oe_rs_i4; - input fabric_direct1_oe_rs_i5; - input fabric_direct1_oe_rs_i6; - input fabric_direct1_oe_rs_i7; - input fabric_direct1_oe_rs_i8; - input fabric_direct1_oe_rs_i9; - input fabric_direct1_scan_en_i; - input fabric_direct2_cfg_bank_i1; - input fabric_direct2_cfg_bank_i2; - input fabric_direct2_cfg_bank_i3; - input fabric_direct2_cfg_bank_i4; - input fabric_direct2_cfg_pad_i1; - input fabric_direct2_cfg_pad_i10; - input fabric_direct2_cfg_pad_i100; - input fabric_direct2_cfg_pad_i101; - input fabric_direct2_cfg_pad_i102; - input fabric_direct2_cfg_pad_i103; - input fabric_direct2_cfg_pad_i104; - input fabric_direct2_cfg_pad_i105; - input fabric_direct2_cfg_pad_i106; - input fabric_direct2_cfg_pad_i107; - input fabric_direct2_cfg_pad_i108; - input fabric_direct2_cfg_pad_i109; - input fabric_direct2_cfg_pad_i11; - input fabric_direct2_cfg_pad_i110; - input fabric_direct2_cfg_pad_i111; - input fabric_direct2_cfg_pad_i112; - input fabric_direct2_cfg_pad_i113; - input fabric_direct2_cfg_pad_i114; - input fabric_direct2_cfg_pad_i115; - input fabric_direct2_cfg_pad_i116; - input fabric_direct2_cfg_pad_i117; - input fabric_direct2_cfg_pad_i118; - input fabric_direct2_cfg_pad_i119; - input fabric_direct2_cfg_pad_i12; - input fabric_direct2_cfg_pad_i120; - input fabric_direct2_cfg_pad_i121; - input fabric_direct2_cfg_pad_i122; - input fabric_direct2_cfg_pad_i123; - input fabric_direct2_cfg_pad_i124; - input fabric_direct2_cfg_pad_i125; - input fabric_direct2_cfg_pad_i126; - input fabric_direct2_cfg_pad_i127; - input fabric_direct2_cfg_pad_i128; - input fabric_direct2_cfg_pad_i129; - input fabric_direct2_cfg_pad_i13; - input fabric_direct2_cfg_pad_i130; - input fabric_direct2_cfg_pad_i131; - input fabric_direct2_cfg_pad_i132; - input fabric_direct2_cfg_pad_i133; - input fabric_direct2_cfg_pad_i134; - input fabric_direct2_cfg_pad_i135; - input fabric_direct2_cfg_pad_i136; - input fabric_direct2_cfg_pad_i137; - input fabric_direct2_cfg_pad_i138; - input fabric_direct2_cfg_pad_i139; - input fabric_direct2_cfg_pad_i14; - input fabric_direct2_cfg_pad_i140; - input fabric_direct2_cfg_pad_i141; - input fabric_direct2_cfg_pad_i142; - input fabric_direct2_cfg_pad_i143; - input fabric_direct2_cfg_pad_i144; - input fabric_direct2_cfg_pad_i145; - input fabric_direct2_cfg_pad_i146; - input fabric_direct2_cfg_pad_i147; - input fabric_direct2_cfg_pad_i148; - input fabric_direct2_cfg_pad_i149; - input fabric_direct2_cfg_pad_i15; - input fabric_direct2_cfg_pad_i150; - input fabric_direct2_cfg_pad_i151; - input fabric_direct2_cfg_pad_i152; - input fabric_direct2_cfg_pad_i153; - input fabric_direct2_cfg_pad_i154; - input fabric_direct2_cfg_pad_i155; - input fabric_direct2_cfg_pad_i156; - input fabric_direct2_cfg_pad_i157; - input fabric_direct2_cfg_pad_i158; - input fabric_direct2_cfg_pad_i159; - input fabric_direct2_cfg_pad_i16; - input fabric_direct2_cfg_pad_i160; - input fabric_direct2_cfg_pad_i161; - input fabric_direct2_cfg_pad_i162; - input fabric_direct2_cfg_pad_i163; - input fabric_direct2_cfg_pad_i164; - input fabric_direct2_cfg_pad_i165; - input fabric_direct2_cfg_pad_i166; - input fabric_direct2_cfg_pad_i167; - input fabric_direct2_cfg_pad_i168; - input fabric_direct2_cfg_pad_i169; - input fabric_direct2_cfg_pad_i17; - input fabric_direct2_cfg_pad_i170; - input fabric_direct2_cfg_pad_i171; - input fabric_direct2_cfg_pad_i172; - input fabric_direct2_cfg_pad_i173; - input fabric_direct2_cfg_pad_i174; - input fabric_direct2_cfg_pad_i175; - input fabric_direct2_cfg_pad_i176; - input fabric_direct2_cfg_pad_i177; - input fabric_direct2_cfg_pad_i178; - input fabric_direct2_cfg_pad_i179; - input fabric_direct2_cfg_pad_i18; - input fabric_direct2_cfg_pad_i180; - input fabric_direct2_cfg_pad_i181; - input fabric_direct2_cfg_pad_i182; - input fabric_direct2_cfg_pad_i183; - input fabric_direct2_cfg_pad_i184; - input fabric_direct2_cfg_pad_i185; - input fabric_direct2_cfg_pad_i186; - input fabric_direct2_cfg_pad_i187; - input fabric_direct2_cfg_pad_i188; - input fabric_direct2_cfg_pad_i189; - input fabric_direct2_cfg_pad_i19; - input fabric_direct2_cfg_pad_i190; - input fabric_direct2_cfg_pad_i191; - input fabric_direct2_cfg_pad_i192; - input fabric_direct2_cfg_pad_i193; - input fabric_direct2_cfg_pad_i194; - input fabric_direct2_cfg_pad_i195; - input fabric_direct2_cfg_pad_i196; - input fabric_direct2_cfg_pad_i197; - input fabric_direct2_cfg_pad_i198; - input fabric_direct2_cfg_pad_i199; - input fabric_direct2_cfg_pad_i2; - input fabric_direct2_cfg_pad_i20; - input fabric_direct2_cfg_pad_i200; - input fabric_direct2_cfg_pad_i201; - input fabric_direct2_cfg_pad_i202; - input fabric_direct2_cfg_pad_i203; - input fabric_direct2_cfg_pad_i204; - input fabric_direct2_cfg_pad_i205; - input fabric_direct2_cfg_pad_i206; - input fabric_direct2_cfg_pad_i207; - input fabric_direct2_cfg_pad_i208; - input fabric_direct2_cfg_pad_i209; - input fabric_direct2_cfg_pad_i21; - input fabric_direct2_cfg_pad_i210; - input fabric_direct2_cfg_pad_i211; - input fabric_direct2_cfg_pad_i212; - input fabric_direct2_cfg_pad_i213; - input fabric_direct2_cfg_pad_i214; - input fabric_direct2_cfg_pad_i215; - input fabric_direct2_cfg_pad_i216; - input fabric_direct2_cfg_pad_i217; - input fabric_direct2_cfg_pad_i218; - input fabric_direct2_cfg_pad_i219; - input fabric_direct2_cfg_pad_i22; - input fabric_direct2_cfg_pad_i220; - input fabric_direct2_cfg_pad_i221; - input fabric_direct2_cfg_pad_i222; - input fabric_direct2_cfg_pad_i223; - input fabric_direct2_cfg_pad_i224; - input fabric_direct2_cfg_pad_i225; - input fabric_direct2_cfg_pad_i226; - input fabric_direct2_cfg_pad_i227; - input fabric_direct2_cfg_pad_i228; - input fabric_direct2_cfg_pad_i229; - input fabric_direct2_cfg_pad_i23; - input fabric_direct2_cfg_pad_i230; - input fabric_direct2_cfg_pad_i231; - input fabric_direct2_cfg_pad_i232; - input fabric_direct2_cfg_pad_i233; - input fabric_direct2_cfg_pad_i234; - input fabric_direct2_cfg_pad_i235; - input fabric_direct2_cfg_pad_i236; - input fabric_direct2_cfg_pad_i237; - input fabric_direct2_cfg_pad_i238; - input fabric_direct2_cfg_pad_i239; - input fabric_direct2_cfg_pad_i24; - input fabric_direct2_cfg_pad_i240; - input fabric_direct2_cfg_pad_i241; - input fabric_direct2_cfg_pad_i242; - input fabric_direct2_cfg_pad_i243; - input fabric_direct2_cfg_pad_i244; - input fabric_direct2_cfg_pad_i245; - input fabric_direct2_cfg_pad_i246; - input fabric_direct2_cfg_pad_i247; - input fabric_direct2_cfg_pad_i248; - input fabric_direct2_cfg_pad_i249; - input fabric_direct2_cfg_pad_i25; - input fabric_direct2_cfg_pad_i250; - input fabric_direct2_cfg_pad_i251; - input fabric_direct2_cfg_pad_i252; - input fabric_direct2_cfg_pad_i253; - input fabric_direct2_cfg_pad_i254; - input fabric_direct2_cfg_pad_i255; - input fabric_direct2_cfg_pad_i256; - input fabric_direct2_cfg_pad_i257; - input fabric_direct2_cfg_pad_i258; - input fabric_direct2_cfg_pad_i259; - input fabric_direct2_cfg_pad_i26; - input fabric_direct2_cfg_pad_i260; - input fabric_direct2_cfg_pad_i261; - input fabric_direct2_cfg_pad_i262; - input fabric_direct2_cfg_pad_i263; - input fabric_direct2_cfg_pad_i264; - input fabric_direct2_cfg_pad_i265; - input fabric_direct2_cfg_pad_i266; - input fabric_direct2_cfg_pad_i267; - input fabric_direct2_cfg_pad_i268; - input fabric_direct2_cfg_pad_i269; - input fabric_direct2_cfg_pad_i27; - input fabric_direct2_cfg_pad_i270; - input fabric_direct2_cfg_pad_i271; - input fabric_direct2_cfg_pad_i272; - input fabric_direct2_cfg_pad_i273; - input fabric_direct2_cfg_pad_i274; - input fabric_direct2_cfg_pad_i275; - input fabric_direct2_cfg_pad_i276; - input fabric_direct2_cfg_pad_i277; - input fabric_direct2_cfg_pad_i278; - input fabric_direct2_cfg_pad_i279; - input fabric_direct2_cfg_pad_i28; - input fabric_direct2_cfg_pad_i280; - input fabric_direct2_cfg_pad_i281; - input fabric_direct2_cfg_pad_i282; - input fabric_direct2_cfg_pad_i283; - input fabric_direct2_cfg_pad_i284; - input fabric_direct2_cfg_pad_i285; - input fabric_direct2_cfg_pad_i286; - input fabric_direct2_cfg_pad_i287; - input fabric_direct2_cfg_pad_i288; - input fabric_direct2_cfg_pad_i289; - input fabric_direct2_cfg_pad_i29; - input fabric_direct2_cfg_pad_i290; - input fabric_direct2_cfg_pad_i291; - input fabric_direct2_cfg_pad_i292; - input fabric_direct2_cfg_pad_i293; - input fabric_direct2_cfg_pad_i294; - input fabric_direct2_cfg_pad_i295; - input fabric_direct2_cfg_pad_i296; - input fabric_direct2_cfg_pad_i297; - input fabric_direct2_cfg_pad_i298; - input fabric_direct2_cfg_pad_i299; - input fabric_direct2_cfg_pad_i3; - input fabric_direct2_cfg_pad_i30; - input fabric_direct2_cfg_pad_i300; - input fabric_direct2_cfg_pad_i301; - input fabric_direct2_cfg_pad_i302; - input fabric_direct2_cfg_pad_i303; - input fabric_direct2_cfg_pad_i304; - input fabric_direct2_cfg_pad_i305; - input fabric_direct2_cfg_pad_i306; - input fabric_direct2_cfg_pad_i307; - input fabric_direct2_cfg_pad_i308; - input fabric_direct2_cfg_pad_i309; - input fabric_direct2_cfg_pad_i31; - input fabric_direct2_cfg_pad_i310; - input fabric_direct2_cfg_pad_i311; - input fabric_direct2_cfg_pad_i312; - input fabric_direct2_cfg_pad_i313; - input fabric_direct2_cfg_pad_i314; - input fabric_direct2_cfg_pad_i315; - input fabric_direct2_cfg_pad_i316; - input fabric_direct2_cfg_pad_i317; - input fabric_direct2_cfg_pad_i318; - input fabric_direct2_cfg_pad_i319; - input fabric_direct2_cfg_pad_i32; - input fabric_direct2_cfg_pad_i320; - input fabric_direct2_cfg_pad_i321; - input fabric_direct2_cfg_pad_i322; - input fabric_direct2_cfg_pad_i323; - input fabric_direct2_cfg_pad_i324; - input fabric_direct2_cfg_pad_i325; - input fabric_direct2_cfg_pad_i326; - input fabric_direct2_cfg_pad_i327; - input fabric_direct2_cfg_pad_i328; - input fabric_direct2_cfg_pad_i329; - input fabric_direct2_cfg_pad_i33; - input fabric_direct2_cfg_pad_i330; - input fabric_direct2_cfg_pad_i331; - input fabric_direct2_cfg_pad_i332; - input fabric_direct2_cfg_pad_i333; - input fabric_direct2_cfg_pad_i334; - input fabric_direct2_cfg_pad_i335; - input fabric_direct2_cfg_pad_i336; - input fabric_direct2_cfg_pad_i337; - input fabric_direct2_cfg_pad_i338; - input fabric_direct2_cfg_pad_i339; - input fabric_direct2_cfg_pad_i34; - input fabric_direct2_cfg_pad_i340; - input fabric_direct2_cfg_pad_i341; - input fabric_direct2_cfg_pad_i342; - input fabric_direct2_cfg_pad_i343; - input fabric_direct2_cfg_pad_i344; - input fabric_direct2_cfg_pad_i345; - input fabric_direct2_cfg_pad_i346; - input fabric_direct2_cfg_pad_i347; - input fabric_direct2_cfg_pad_i348; - input fabric_direct2_cfg_pad_i349; - input fabric_direct2_cfg_pad_i35; - input fabric_direct2_cfg_pad_i350; - input fabric_direct2_cfg_pad_i351; - input fabric_direct2_cfg_pad_i352; - input fabric_direct2_cfg_pad_i353; - input fabric_direct2_cfg_pad_i354; - input fabric_direct2_cfg_pad_i355; - input fabric_direct2_cfg_pad_i356; - input fabric_direct2_cfg_pad_i357; - input fabric_direct2_cfg_pad_i358; - input fabric_direct2_cfg_pad_i359; - input fabric_direct2_cfg_pad_i36; - input fabric_direct2_cfg_pad_i360; - input fabric_direct2_cfg_pad_i361; - input fabric_direct2_cfg_pad_i362; - input fabric_direct2_cfg_pad_i363; - input fabric_direct2_cfg_pad_i364; - input fabric_direct2_cfg_pad_i365; - input fabric_direct2_cfg_pad_i366; - input fabric_direct2_cfg_pad_i367; - input fabric_direct2_cfg_pad_i368; - input fabric_direct2_cfg_pad_i369; - input fabric_direct2_cfg_pad_i37; - input fabric_direct2_cfg_pad_i370; - input fabric_direct2_cfg_pad_i371; - input fabric_direct2_cfg_pad_i372; - input fabric_direct2_cfg_pad_i373; - input fabric_direct2_cfg_pad_i374; - input fabric_direct2_cfg_pad_i375; - input fabric_direct2_cfg_pad_i376; - input fabric_direct2_cfg_pad_i377; - input fabric_direct2_cfg_pad_i378; - input fabric_direct2_cfg_pad_i379; - input fabric_direct2_cfg_pad_i38; - input fabric_direct2_cfg_pad_i380; - input fabric_direct2_cfg_pad_i381; - input fabric_direct2_cfg_pad_i382; - input fabric_direct2_cfg_pad_i383; - input fabric_direct2_cfg_pad_i384; - input fabric_direct2_cfg_pad_i385; - input fabric_direct2_cfg_pad_i386; - input fabric_direct2_cfg_pad_i387; - input fabric_direct2_cfg_pad_i388; - input fabric_direct2_cfg_pad_i389; - input fabric_direct2_cfg_pad_i39; - input fabric_direct2_cfg_pad_i390; - input fabric_direct2_cfg_pad_i391; - input fabric_direct2_cfg_pad_i392; - input fabric_direct2_cfg_pad_i393; - input fabric_direct2_cfg_pad_i394; - input fabric_direct2_cfg_pad_i395; - input fabric_direct2_cfg_pad_i396; - input fabric_direct2_cfg_pad_i397; - input fabric_direct2_cfg_pad_i398; - input fabric_direct2_cfg_pad_i399; - input fabric_direct2_cfg_pad_i4; - input fabric_direct2_cfg_pad_i40; - input fabric_direct2_cfg_pad_i400; - input fabric_direct2_cfg_pad_i401; - input fabric_direct2_cfg_pad_i402; - input fabric_direct2_cfg_pad_i403; - input fabric_direct2_cfg_pad_i404; - input fabric_direct2_cfg_pad_i405; - input fabric_direct2_cfg_pad_i406; - input fabric_direct2_cfg_pad_i407; - input fabric_direct2_cfg_pad_i408; - input fabric_direct2_cfg_pad_i409; - input fabric_direct2_cfg_pad_i41; - input fabric_direct2_cfg_pad_i410; - input fabric_direct2_cfg_pad_i411; - input fabric_direct2_cfg_pad_i412; - input fabric_direct2_cfg_pad_i413; - input fabric_direct2_cfg_pad_i414; - input fabric_direct2_cfg_pad_i415; - input fabric_direct2_cfg_pad_i416; - input fabric_direct2_cfg_pad_i417; - input fabric_direct2_cfg_pad_i418; - input fabric_direct2_cfg_pad_i419; - input fabric_direct2_cfg_pad_i42; - input fabric_direct2_cfg_pad_i420; - input fabric_direct2_cfg_pad_i421; - input fabric_direct2_cfg_pad_i422; - input fabric_direct2_cfg_pad_i423; - input fabric_direct2_cfg_pad_i424; - input fabric_direct2_cfg_pad_i425; - input fabric_direct2_cfg_pad_i426; - input fabric_direct2_cfg_pad_i427; - input fabric_direct2_cfg_pad_i428; - input fabric_direct2_cfg_pad_i429; - input fabric_direct2_cfg_pad_i43; - input fabric_direct2_cfg_pad_i430; - input fabric_direct2_cfg_pad_i431; - input fabric_direct2_cfg_pad_i432; - input fabric_direct2_cfg_pad_i433; - input fabric_direct2_cfg_pad_i434; - input fabric_direct2_cfg_pad_i435; - input fabric_direct2_cfg_pad_i436; - input fabric_direct2_cfg_pad_i437; - input fabric_direct2_cfg_pad_i438; - input fabric_direct2_cfg_pad_i439; - input fabric_direct2_cfg_pad_i44; - input fabric_direct2_cfg_pad_i440; - input fabric_direct2_cfg_pad_i441; - input fabric_direct2_cfg_pad_i442; - input fabric_direct2_cfg_pad_i443; - input fabric_direct2_cfg_pad_i444; - input fabric_direct2_cfg_pad_i445; - input fabric_direct2_cfg_pad_i446; - input fabric_direct2_cfg_pad_i447; - input fabric_direct2_cfg_pad_i448; - input fabric_direct2_cfg_pad_i449; - input fabric_direct2_cfg_pad_i45; - input fabric_direct2_cfg_pad_i450; - input fabric_direct2_cfg_pad_i451; - input fabric_direct2_cfg_pad_i452; - input fabric_direct2_cfg_pad_i453; - input fabric_direct2_cfg_pad_i454; - input fabric_direct2_cfg_pad_i455; - input fabric_direct2_cfg_pad_i456; - input fabric_direct2_cfg_pad_i457; - input fabric_direct2_cfg_pad_i458; - input fabric_direct2_cfg_pad_i459; - input fabric_direct2_cfg_pad_i46; - input fabric_direct2_cfg_pad_i460; - input fabric_direct2_cfg_pad_i461; - input fabric_direct2_cfg_pad_i462; - input fabric_direct2_cfg_pad_i463; - input fabric_direct2_cfg_pad_i464; - input fabric_direct2_cfg_pad_i465; - input fabric_direct2_cfg_pad_i466; - input fabric_direct2_cfg_pad_i467; - input fabric_direct2_cfg_pad_i468; - input fabric_direct2_cfg_pad_i469; - input fabric_direct2_cfg_pad_i47; - input fabric_direct2_cfg_pad_i470; - input fabric_direct2_cfg_pad_i471; - input fabric_direct2_cfg_pad_i472; - input fabric_direct2_cfg_pad_i473; - input fabric_direct2_cfg_pad_i474; - input fabric_direct2_cfg_pad_i475; - input fabric_direct2_cfg_pad_i476; - input fabric_direct2_cfg_pad_i477; - input fabric_direct2_cfg_pad_i478; - input fabric_direct2_cfg_pad_i479; - input fabric_direct2_cfg_pad_i48; - input fabric_direct2_cfg_pad_i480; - input fabric_direct2_cfg_pad_i481; - input fabric_direct2_cfg_pad_i482; - input fabric_direct2_cfg_pad_i483; - input fabric_direct2_cfg_pad_i484; - input fabric_direct2_cfg_pad_i485; - input fabric_direct2_cfg_pad_i486; - input fabric_direct2_cfg_pad_i487; - input fabric_direct2_cfg_pad_i488; - input fabric_direct2_cfg_pad_i489; - input fabric_direct2_cfg_pad_i49; - input fabric_direct2_cfg_pad_i490; - input fabric_direct2_cfg_pad_i491; - input fabric_direct2_cfg_pad_i492; - input fabric_direct2_cfg_pad_i493; - input fabric_direct2_cfg_pad_i494; - input fabric_direct2_cfg_pad_i495; - input fabric_direct2_cfg_pad_i496; - input fabric_direct2_cfg_pad_i497; - input fabric_direct2_cfg_pad_i498; - input fabric_direct2_cfg_pad_i499; - input fabric_direct2_cfg_pad_i5; - input fabric_direct2_cfg_pad_i50; - input fabric_direct2_cfg_pad_i500; - input fabric_direct2_cfg_pad_i501; - input fabric_direct2_cfg_pad_i502; - input fabric_direct2_cfg_pad_i503; - input fabric_direct2_cfg_pad_i504; - input fabric_direct2_cfg_pad_i505; - input fabric_direct2_cfg_pad_i506; - input fabric_direct2_cfg_pad_i507; - input fabric_direct2_cfg_pad_i508; - input fabric_direct2_cfg_pad_i509; - input fabric_direct2_cfg_pad_i51; - input fabric_direct2_cfg_pad_i510; - input fabric_direct2_cfg_pad_i511; - input fabric_direct2_cfg_pad_i512; - input fabric_direct2_cfg_pad_i513; - input fabric_direct2_cfg_pad_i514; - input fabric_direct2_cfg_pad_i515; - input fabric_direct2_cfg_pad_i516; - input fabric_direct2_cfg_pad_i517; - input fabric_direct2_cfg_pad_i518; - input fabric_direct2_cfg_pad_i519; - input fabric_direct2_cfg_pad_i52; - input fabric_direct2_cfg_pad_i520; - input fabric_direct2_cfg_pad_i521; - input fabric_direct2_cfg_pad_i522; - input fabric_direct2_cfg_pad_i523; - input fabric_direct2_cfg_pad_i524; - input fabric_direct2_cfg_pad_i525; - input fabric_direct2_cfg_pad_i526; - input fabric_direct2_cfg_pad_i527; - input fabric_direct2_cfg_pad_i528; - input fabric_direct2_cfg_pad_i529; - input fabric_direct2_cfg_pad_i53; - input fabric_direct2_cfg_pad_i530; - input fabric_direct2_cfg_pad_i531; - input fabric_direct2_cfg_pad_i532; - input fabric_direct2_cfg_pad_i533; - input fabric_direct2_cfg_pad_i534; - input fabric_direct2_cfg_pad_i535; - input fabric_direct2_cfg_pad_i536; - input fabric_direct2_cfg_pad_i537; - input fabric_direct2_cfg_pad_i538; - input fabric_direct2_cfg_pad_i539; - input fabric_direct2_cfg_pad_i54; - input fabric_direct2_cfg_pad_i540; - input fabric_direct2_cfg_pad_i541; - input fabric_direct2_cfg_pad_i542; - input fabric_direct2_cfg_pad_i543; - input fabric_direct2_cfg_pad_i544; - input fabric_direct2_cfg_pad_i545; - input fabric_direct2_cfg_pad_i546; - input fabric_direct2_cfg_pad_i547; - input fabric_direct2_cfg_pad_i548; - input fabric_direct2_cfg_pad_i549; - input fabric_direct2_cfg_pad_i55; - input fabric_direct2_cfg_pad_i550; - input fabric_direct2_cfg_pad_i551; - input fabric_direct2_cfg_pad_i552; - input fabric_direct2_cfg_pad_i553; - input fabric_direct2_cfg_pad_i554; - input fabric_direct2_cfg_pad_i555; - input fabric_direct2_cfg_pad_i556; - input fabric_direct2_cfg_pad_i557; - input fabric_direct2_cfg_pad_i558; - input fabric_direct2_cfg_pad_i559; - input fabric_direct2_cfg_pad_i56; - input fabric_direct2_cfg_pad_i560; - input fabric_direct2_cfg_pad_i561; - input fabric_direct2_cfg_pad_i562; - input fabric_direct2_cfg_pad_i563; - input fabric_direct2_cfg_pad_i564; - input fabric_direct2_cfg_pad_i565; - input fabric_direct2_cfg_pad_i566; - input fabric_direct2_cfg_pad_i567; - input fabric_direct2_cfg_pad_i568; - input fabric_direct2_cfg_pad_i569; - input fabric_direct2_cfg_pad_i57; - input fabric_direct2_cfg_pad_i570; - input fabric_direct2_cfg_pad_i571; - input fabric_direct2_cfg_pad_i572; - input fabric_direct2_cfg_pad_i573; - input fabric_direct2_cfg_pad_i574; - input fabric_direct2_cfg_pad_i575; - input fabric_direct2_cfg_pad_i576; - input fabric_direct2_cfg_pad_i577; - input fabric_direct2_cfg_pad_i578; - input fabric_direct2_cfg_pad_i579; - input fabric_direct2_cfg_pad_i58; - input fabric_direct2_cfg_pad_i580; - input fabric_direct2_cfg_pad_i581; - input fabric_direct2_cfg_pad_i582; - input fabric_direct2_cfg_pad_i583; - input fabric_direct2_cfg_pad_i584; - input fabric_direct2_cfg_pad_i585; - input fabric_direct2_cfg_pad_i586; - input fabric_direct2_cfg_pad_i587; - input fabric_direct2_cfg_pad_i588; - input fabric_direct2_cfg_pad_i589; - input fabric_direct2_cfg_pad_i59; - input fabric_direct2_cfg_pad_i590; - input fabric_direct2_cfg_pad_i591; - input fabric_direct2_cfg_pad_i592; - input fabric_direct2_cfg_pad_i593; - input fabric_direct2_cfg_pad_i594; - input fabric_direct2_cfg_pad_i595; - input fabric_direct2_cfg_pad_i596; - input fabric_direct2_cfg_pad_i597; - input fabric_direct2_cfg_pad_i598; - input fabric_direct2_cfg_pad_i599; - input fabric_direct2_cfg_pad_i6; - input fabric_direct2_cfg_pad_i60; - input fabric_direct2_cfg_pad_i600; - input fabric_direct2_cfg_pad_i601; - input fabric_direct2_cfg_pad_i602; - input fabric_direct2_cfg_pad_i603; - input fabric_direct2_cfg_pad_i604; - input fabric_direct2_cfg_pad_i605; - input fabric_direct2_cfg_pad_i606; - input fabric_direct2_cfg_pad_i607; - input fabric_direct2_cfg_pad_i608; - input fabric_direct2_cfg_pad_i609; - input fabric_direct2_cfg_pad_i61; - input fabric_direct2_cfg_pad_i610; - input fabric_direct2_cfg_pad_i611; - input fabric_direct2_cfg_pad_i612; - input fabric_direct2_cfg_pad_i613; - input fabric_direct2_cfg_pad_i614; - input fabric_direct2_cfg_pad_i615; - input fabric_direct2_cfg_pad_i616; - input fabric_direct2_cfg_pad_i617; - input fabric_direct2_cfg_pad_i618; - input fabric_direct2_cfg_pad_i619; - input fabric_direct2_cfg_pad_i62; - input fabric_direct2_cfg_pad_i620; - input fabric_direct2_cfg_pad_i621; - input fabric_direct2_cfg_pad_i622; - input fabric_direct2_cfg_pad_i623; - input fabric_direct2_cfg_pad_i624; - input fabric_direct2_cfg_pad_i625; - input fabric_direct2_cfg_pad_i626; - input fabric_direct2_cfg_pad_i627; - input fabric_direct2_cfg_pad_i628; - input fabric_direct2_cfg_pad_i629; - input fabric_direct2_cfg_pad_i63; - input fabric_direct2_cfg_pad_i630; - input fabric_direct2_cfg_pad_i631; - input fabric_direct2_cfg_pad_i632; - input fabric_direct2_cfg_pad_i633; - input fabric_direct2_cfg_pad_i634; - input fabric_direct2_cfg_pad_i635; - input fabric_direct2_cfg_pad_i636; - input fabric_direct2_cfg_pad_i637; - input fabric_direct2_cfg_pad_i638; - input fabric_direct2_cfg_pad_i639; - input fabric_direct2_cfg_pad_i64; - input fabric_direct2_cfg_pad_i640; - input fabric_direct2_cfg_pad_i641; - input fabric_direct2_cfg_pad_i642; - input fabric_direct2_cfg_pad_i643; - input fabric_direct2_cfg_pad_i644; - input fabric_direct2_cfg_pad_i645; - input fabric_direct2_cfg_pad_i646; - input fabric_direct2_cfg_pad_i647; - input fabric_direct2_cfg_pad_i648; - input fabric_direct2_cfg_pad_i649; - input fabric_direct2_cfg_pad_i65; - input fabric_direct2_cfg_pad_i650; - input fabric_direct2_cfg_pad_i651; - input fabric_direct2_cfg_pad_i652; - input fabric_direct2_cfg_pad_i653; - input fabric_direct2_cfg_pad_i654; - input fabric_direct2_cfg_pad_i655; - input fabric_direct2_cfg_pad_i656; - input fabric_direct2_cfg_pad_i657; - input fabric_direct2_cfg_pad_i658; - input fabric_direct2_cfg_pad_i659; - input fabric_direct2_cfg_pad_i66; - input fabric_direct2_cfg_pad_i660; - input fabric_direct2_cfg_pad_i661; - input fabric_direct2_cfg_pad_i662; - input fabric_direct2_cfg_pad_i663; - input fabric_direct2_cfg_pad_i664; - input fabric_direct2_cfg_pad_i665; - input fabric_direct2_cfg_pad_i666; - input fabric_direct2_cfg_pad_i667; - input fabric_direct2_cfg_pad_i668; - input fabric_direct2_cfg_pad_i669; - input fabric_direct2_cfg_pad_i67; - input fabric_direct2_cfg_pad_i670; - input fabric_direct2_cfg_pad_i671; - input fabric_direct2_cfg_pad_i672; - input fabric_direct2_cfg_pad_i673; - input fabric_direct2_cfg_pad_i674; - input fabric_direct2_cfg_pad_i675; - input fabric_direct2_cfg_pad_i676; - input fabric_direct2_cfg_pad_i677; - input fabric_direct2_cfg_pad_i678; - input fabric_direct2_cfg_pad_i679; - input fabric_direct2_cfg_pad_i68; - input fabric_direct2_cfg_pad_i680; - input fabric_direct2_cfg_pad_i681; - input fabric_direct2_cfg_pad_i682; - input fabric_direct2_cfg_pad_i683; - input fabric_direct2_cfg_pad_i684; - input fabric_direct2_cfg_pad_i685; - input fabric_direct2_cfg_pad_i686; - input fabric_direct2_cfg_pad_i687; - input fabric_direct2_cfg_pad_i688; - input fabric_direct2_cfg_pad_i689; - input fabric_direct2_cfg_pad_i69; - input fabric_direct2_cfg_pad_i690; - input fabric_direct2_cfg_pad_i691; - input fabric_direct2_cfg_pad_i692; - input fabric_direct2_cfg_pad_i693; - input fabric_direct2_cfg_pad_i694; - input fabric_direct2_cfg_pad_i695; - input fabric_direct2_cfg_pad_i696; - input fabric_direct2_cfg_pad_i697; - input fabric_direct2_cfg_pad_i698; - input fabric_direct2_cfg_pad_i699; - input fabric_direct2_cfg_pad_i7; - input fabric_direct2_cfg_pad_i70; - input fabric_direct2_cfg_pad_i700; - input fabric_direct2_cfg_pad_i701; - input fabric_direct2_cfg_pad_i702; - input fabric_direct2_cfg_pad_i703; - input fabric_direct2_cfg_pad_i704; - input fabric_direct2_cfg_pad_i705; - input fabric_direct2_cfg_pad_i706; - input fabric_direct2_cfg_pad_i707; - input fabric_direct2_cfg_pad_i708; - input fabric_direct2_cfg_pad_i709; - input fabric_direct2_cfg_pad_i71; - input fabric_direct2_cfg_pad_i710; - input fabric_direct2_cfg_pad_i711; - input fabric_direct2_cfg_pad_i712; - input fabric_direct2_cfg_pad_i713; - input fabric_direct2_cfg_pad_i714; - input fabric_direct2_cfg_pad_i715; - input fabric_direct2_cfg_pad_i716; - input fabric_direct2_cfg_pad_i717; - input fabric_direct2_cfg_pad_i718; - input fabric_direct2_cfg_pad_i719; - input fabric_direct2_cfg_pad_i72; - input fabric_direct2_cfg_pad_i720; - input fabric_direct2_cfg_pad_i73; - input fabric_direct2_cfg_pad_i74; - input fabric_direct2_cfg_pad_i75; - input fabric_direct2_cfg_pad_i76; - input fabric_direct2_cfg_pad_i77; - input fabric_direct2_cfg_pad_i78; - input fabric_direct2_cfg_pad_i79; - input fabric_direct2_cfg_pad_i8; - input fabric_direct2_cfg_pad_i80; - input fabric_direct2_cfg_pad_i81; - input fabric_direct2_cfg_pad_i82; - input fabric_direct2_cfg_pad_i83; - input fabric_direct2_cfg_pad_i84; - input fabric_direct2_cfg_pad_i85; - input fabric_direct2_cfg_pad_i86; - input fabric_direct2_cfg_pad_i87; - input fabric_direct2_cfg_pad_i88; - input fabric_direct2_cfg_pad_i89; - input fabric_direct2_cfg_pad_i9; - input fabric_direct2_cfg_pad_i90; - input fabric_direct2_cfg_pad_i91; - input fabric_direct2_cfg_pad_i92; - input fabric_direct2_cfg_pad_i93; - input fabric_direct2_cfg_pad_i94; - input fabric_direct2_cfg_pad_i95; - input fabric_direct2_cfg_pad_i96; - input fabric_direct2_cfg_pad_i97; - input fabric_direct2_cfg_pad_i98; - input fabric_direct2_cfg_pad_i99; - input fabric_direct2_clock_fabric_i1; - input fabric_direct2_clock_fabric_i2; - input fabric_direct2_clock_fabric_i3; - input fabric_direct2_clock_fabric_i4; - input fabric_direct2_di_ena_i1; - input fabric_direct2_di_ena_i10; - input fabric_direct2_di_ena_i11; - input fabric_direct2_di_ena_i12; - input fabric_direct2_di_ena_i13; - input fabric_direct2_di_ena_i14; - input fabric_direct2_di_ena_i15; - input fabric_direct2_di_ena_i16; - input fabric_direct2_di_ena_i17; - input fabric_direct2_di_ena_i18; - input fabric_direct2_di_ena_i19; - input fabric_direct2_di_ena_i2; - input fabric_direct2_di_ena_i20; - input fabric_direct2_di_ena_i21; - input fabric_direct2_di_ena_i22; - input fabric_direct2_di_ena_i23; - input fabric_direct2_di_ena_i24; - input fabric_direct2_di_ena_i3; - input fabric_direct2_di_ena_i4; - input fabric_direct2_di_ena_i5; - input fabric_direct2_di_ena_i6; - input fabric_direct2_di_ena_i7; - input fabric_direct2_di_ena_i8; - input fabric_direct2_di_ena_i9; - output fabric_direct2_di_o1; - output fabric_direct2_di_o10; - output fabric_direct2_di_o11; - output fabric_direct2_di_o12; - output fabric_direct2_di_o13; - output fabric_direct2_di_o14; - output fabric_direct2_di_o15; - output fabric_direct2_di_o16; - output fabric_direct2_di_o17; - output fabric_direct2_di_o18; - output fabric_direct2_di_o19; - output fabric_direct2_di_o2; - output fabric_direct2_di_o20; - output fabric_direct2_di_o21; - output fabric_direct2_di_o22; - output fabric_direct2_di_o23; - output fabric_direct2_di_o24; - output fabric_direct2_di_o3; - output fabric_direct2_di_o4; - output fabric_direct2_di_o5; - output fabric_direct2_di_o6; - output fabric_direct2_di_o7; - output fabric_direct2_di_o8; - output fabric_direct2_di_o9; - input fabric_direct2_di_rs_i1; - input fabric_direct2_di_rs_i10; - input fabric_direct2_di_rs_i11; - input fabric_direct2_di_rs_i12; - input fabric_direct2_di_rs_i13; - input fabric_direct2_di_rs_i14; - input fabric_direct2_di_rs_i15; - input fabric_direct2_di_rs_i16; - input fabric_direct2_di_rs_i17; - input fabric_direct2_di_rs_i18; - input fabric_direct2_di_rs_i19; - input fabric_direct2_di_rs_i2; - input fabric_direct2_di_rs_i20; - input fabric_direct2_di_rs_i21; - input fabric_direct2_di_rs_i22; - input fabric_direct2_di_rs_i23; - input fabric_direct2_di_rs_i24; - input fabric_direct2_di_rs_i3; - input fabric_direct2_di_rs_i4; - input fabric_direct2_di_rs_i5; - input fabric_direct2_di_rs_i6; - input fabric_direct2_di_rs_i7; - input fabric_direct2_di_rs_i8; - input fabric_direct2_di_rs_i9; - input fabric_direct2_do_ena_i1; - input fabric_direct2_do_ena_i10; - input fabric_direct2_do_ena_i11; - input fabric_direct2_do_ena_i12; - input fabric_direct2_do_ena_i13; - input fabric_direct2_do_ena_i14; - input fabric_direct2_do_ena_i15; - input fabric_direct2_do_ena_i16; - input fabric_direct2_do_ena_i17; - input fabric_direct2_do_ena_i18; - input fabric_direct2_do_ena_i19; - input fabric_direct2_do_ena_i2; - input fabric_direct2_do_ena_i20; - input fabric_direct2_do_ena_i21; - input fabric_direct2_do_ena_i22; - input fabric_direct2_do_ena_i23; - input fabric_direct2_do_ena_i24; - input fabric_direct2_do_ena_i3; - input fabric_direct2_do_ena_i4; - input fabric_direct2_do_ena_i5; - input fabric_direct2_do_ena_i6; - input fabric_direct2_do_ena_i7; - input fabric_direct2_do_ena_i8; - input fabric_direct2_do_ena_i9; - input fabric_direct2_do_i1; - input fabric_direct2_do_i10; - input fabric_direct2_do_i11; - input fabric_direct2_do_i12; - input fabric_direct2_do_i13; - input fabric_direct2_do_i14; - input fabric_direct2_do_i15; - input fabric_direct2_do_i16; - input fabric_direct2_do_i17; - input fabric_direct2_do_i18; - input fabric_direct2_do_i19; - input fabric_direct2_do_i2; - input fabric_direct2_do_i20; - input fabric_direct2_do_i21; - input fabric_direct2_do_i22; - input fabric_direct2_do_i23; - input fabric_direct2_do_i24; - input fabric_direct2_do_i3; - input fabric_direct2_do_i4; - input fabric_direct2_do_i5; - input fabric_direct2_do_i6; - input fabric_direct2_do_i7; - input fabric_direct2_do_i8; - input fabric_direct2_do_i9; - input fabric_direct2_do_rs_i1; - input fabric_direct2_do_rs_i10; - input fabric_direct2_do_rs_i11; - input fabric_direct2_do_rs_i12; - input fabric_direct2_do_rs_i13; - input fabric_direct2_do_rs_i14; - input fabric_direct2_do_rs_i15; - input fabric_direct2_do_rs_i16; - input fabric_direct2_do_rs_i17; - input fabric_direct2_do_rs_i18; - input fabric_direct2_do_rs_i19; - input fabric_direct2_do_rs_i2; - input fabric_direct2_do_rs_i20; - input fabric_direct2_do_rs_i21; - input fabric_direct2_do_rs_i22; - input fabric_direct2_do_rs_i23; - input fabric_direct2_do_rs_i24; - input fabric_direct2_do_rs_i3; - input fabric_direct2_do_rs_i4; - input fabric_direct2_do_rs_i5; - input fabric_direct2_do_rs_i6; - input fabric_direct2_do_rs_i7; - input fabric_direct2_do_rs_i8; - input fabric_direct2_do_rs_i9; - input fabric_direct2_loopback_en_i; - input fabric_direct2_loopback_mux_i; - input fabric_direct2_oe_ena_i1; - input fabric_direct2_oe_ena_i10; - input fabric_direct2_oe_ena_i11; - input fabric_direct2_oe_ena_i12; - input fabric_direct2_oe_ena_i13; - input fabric_direct2_oe_ena_i14; - input fabric_direct2_oe_ena_i15; - input fabric_direct2_oe_ena_i16; - input fabric_direct2_oe_ena_i17; - input fabric_direct2_oe_ena_i18; - input fabric_direct2_oe_ena_i19; - input fabric_direct2_oe_ena_i2; - input fabric_direct2_oe_ena_i20; - input fabric_direct2_oe_ena_i21; - input fabric_direct2_oe_ena_i22; - input fabric_direct2_oe_ena_i23; - input fabric_direct2_oe_ena_i24; - input fabric_direct2_oe_ena_i3; - input fabric_direct2_oe_ena_i4; - input fabric_direct2_oe_ena_i5; - input fabric_direct2_oe_ena_i6; - input fabric_direct2_oe_ena_i7; - input fabric_direct2_oe_ena_i8; - input fabric_direct2_oe_ena_i9; - input fabric_direct2_oe_i1; - input fabric_direct2_oe_i10; - input fabric_direct2_oe_i11; - input fabric_direct2_oe_i12; - input fabric_direct2_oe_i13; - input fabric_direct2_oe_i14; - input fabric_direct2_oe_i15; - input fabric_direct2_oe_i16; - input fabric_direct2_oe_i17; - input fabric_direct2_oe_i18; - input fabric_direct2_oe_i19; - input fabric_direct2_oe_i2; - input fabric_direct2_oe_i20; - input fabric_direct2_oe_i21; - input fabric_direct2_oe_i22; - input fabric_direct2_oe_i23; - input fabric_direct2_oe_i24; - input fabric_direct2_oe_i3; - input fabric_direct2_oe_i4; - input fabric_direct2_oe_i5; - input fabric_direct2_oe_i6; - input fabric_direct2_oe_i7; - input fabric_direct2_oe_i8; - input fabric_direct2_oe_i9; - input fabric_direct2_oe_rs_i1; - input fabric_direct2_oe_rs_i10; - input fabric_direct2_oe_rs_i11; - input fabric_direct2_oe_rs_i12; - input fabric_direct2_oe_rs_i13; - input fabric_direct2_oe_rs_i14; - input fabric_direct2_oe_rs_i15; - input fabric_direct2_oe_rs_i16; - input fabric_direct2_oe_rs_i17; - input fabric_direct2_oe_rs_i18; - input fabric_direct2_oe_rs_i19; - input fabric_direct2_oe_rs_i2; - input fabric_direct2_oe_rs_i20; - input fabric_direct2_oe_rs_i21; - input fabric_direct2_oe_rs_i22; - input fabric_direct2_oe_rs_i23; - input fabric_direct2_oe_rs_i24; - input fabric_direct2_oe_rs_i3; - input fabric_direct2_oe_rs_i4; - input fabric_direct2_oe_rs_i5; - input fabric_direct2_oe_rs_i6; - input fabric_direct2_oe_rs_i7; - input fabric_direct2_oe_rs_i8; - input fabric_direct2_oe_rs_i9; - input fabric_direct2_scan_en_i; - input fabric_direct_data_i1; - input fabric_direct_data_i10; - input fabric_direct_data_i11; - input fabric_direct_data_i12; - input fabric_direct_data_i13; - input fabric_direct_data_i14; - input fabric_direct_data_i15; - input fabric_direct_data_i16; - input fabric_direct_data_i17; - input fabric_direct_data_i18; - input fabric_direct_data_i19; - input fabric_direct_data_i2; - input fabric_direct_data_i20; - input fabric_direct_data_i21; - input fabric_direct_data_i22; - input fabric_direct_data_i23; - input fabric_direct_data_i24; - input fabric_direct_data_i25; - input fabric_direct_data_i26; - input fabric_direct_data_i27; - input fabric_direct_data_i28; - input fabric_direct_data_i29; - input fabric_direct_data_i3; - input fabric_direct_data_i30; - input fabric_direct_data_i31; - input fabric_direct_data_i32; - input fabric_direct_data_i4; - input fabric_direct_data_i5; - input fabric_direct_data_i6; - input fabric_direct_data_i7; - input fabric_direct_data_i8; - input fabric_direct_data_i9; - output fabric_direct_data_o1; - output fabric_direct_data_o10; - output fabric_direct_data_o11; - output fabric_direct_data_o12; - output fabric_direct_data_o13; - output fabric_direct_data_o14; - output fabric_direct_data_o15; - output fabric_direct_data_o16; - output fabric_direct_data_o17; - output fabric_direct_data_o18; - output fabric_direct_data_o19; - output fabric_direct_data_o2; - output fabric_direct_data_o20; - output fabric_direct_data_o21; - output fabric_direct_data_o22; - output fabric_direct_data_o23; - output fabric_direct_data_o24; - output fabric_direct_data_o25; - output fabric_direct_data_o26; - output fabric_direct_data_o27; - output fabric_direct_data_o28; - output fabric_direct_data_o29; - output fabric_direct_data_o3; - output fabric_direct_data_o30; - output fabric_direct_data_o31; - output fabric_direct_data_o32; - output fabric_direct_data_o4; - output fabric_direct_data_o5; - output fabric_direct_data_o6; - output fabric_direct_data_o7; - output fabric_direct_data_o8; - output fabric_direct_data_o9; - input fabric_enable_TMR_i1; - input fabric_enable_TMR_i2; - input fabric_enable_TMR_i3; - output fabric_flag_ready_TMR_o1; - output fabric_flag_ready_TMR_o2; - output fabric_flag_ready_TMR_o3; - output fabric_flag_trigger0_o; - output fabric_flag_trigger1_o; - input fabric_io_in_i1; - input fabric_io_in_i10; - input fabric_io_in_i11; - input fabric_io_in_i12; - input fabric_io_in_i13; - input fabric_io_in_i14; - input fabric_io_in_i15; - input fabric_io_in_i16; - input fabric_io_in_i17; - input fabric_io_in_i18; - input fabric_io_in_i19; - input fabric_io_in_i2; - input fabric_io_in_i20; - input fabric_io_in_i21; - input fabric_io_in_i22; - input fabric_io_in_i23; - input fabric_io_in_i24; - input fabric_io_in_i25; - input fabric_io_in_i26; - input fabric_io_in_i27; - input fabric_io_in_i28; - input fabric_io_in_i29; - input fabric_io_in_i3; - input fabric_io_in_i30; - input fabric_io_in_i31; - input fabric_io_in_i32; - input fabric_io_in_i33; - input fabric_io_in_i34; - input fabric_io_in_i35; - input fabric_io_in_i4; - input fabric_io_in_i5; - input fabric_io_in_i6; - input fabric_io_in_i7; - input fabric_io_in_i8; - input fabric_io_in_i9; - input fabric_io_oe_i1; - input fabric_io_oe_i10; - input fabric_io_oe_i11; - input fabric_io_oe_i12; - input fabric_io_oe_i13; - input fabric_io_oe_i14; - input fabric_io_oe_i15; - input fabric_io_oe_i16; - input fabric_io_oe_i17; - input fabric_io_oe_i18; - input fabric_io_oe_i19; - input fabric_io_oe_i2; - input fabric_io_oe_i20; - input fabric_io_oe_i21; - input fabric_io_oe_i22; - input fabric_io_oe_i23; - input fabric_io_oe_i24; - input fabric_io_oe_i25; - input fabric_io_oe_i26; - input fabric_io_oe_i27; - input fabric_io_oe_i28; - input fabric_io_oe_i29; - input fabric_io_oe_i3; - input fabric_io_oe_i30; - input fabric_io_oe_i31; - input fabric_io_oe_i32; - input fabric_io_oe_i33; - input fabric_io_oe_i34; - input fabric_io_oe_i35; - input fabric_io_oe_i4; - input fabric_io_oe_i5; - input fabric_io_oe_i6; - input fabric_io_oe_i7; - input fabric_io_oe_i8; - input fabric_io_oe_i9; - output fabric_io_out_o1; - output fabric_io_out_o10; - output fabric_io_out_o11; - output fabric_io_out_o12; - output fabric_io_out_o13; - output fabric_io_out_o14; - output fabric_io_out_o15; - output fabric_io_out_o16; - output fabric_io_out_o17; - output fabric_io_out_o18; - output fabric_io_out_o19; - output fabric_io_out_o2; - output fabric_io_out_o20; - output fabric_io_out_o21; - output fabric_io_out_o22; - output fabric_io_out_o23; - output fabric_io_out_o24; - output fabric_io_out_o25; - output fabric_io_out_o26; - output fabric_io_out_o27; - output fabric_io_out_o28; - output fabric_io_out_o29; - output fabric_io_out_o3; - output fabric_io_out_o30; - output fabric_io_out_o31; - output fabric_io_out_o32; - output fabric_io_out_o33; - output fabric_io_out_o34; - output fabric_io_out_o35; - output fabric_io_out_o4; - output fabric_io_out_o5; - output fabric_io_out_o6; - output fabric_io_out_o7; - output fabric_io_out_o8; - output fabric_io_out_o9; - output fabric_jtag_tck_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i1; - input fabric_lowskew_i10; - input fabric_lowskew_i11; - input fabric_lowskew_i12; - input fabric_lowskew_i13; - input fabric_lowskew_i14; - input fabric_lowskew_i15; - input fabric_lowskew_i16; - input fabric_lowskew_i17; - input fabric_lowskew_i18; - input fabric_lowskew_i19; - input fabric_lowskew_i2; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - input fabric_lowskew_i24; - input fabric_lowskew_i25; - input fabric_lowskew_i26; - input fabric_lowskew_i27; - input fabric_lowskew_i28; - input fabric_lowskew_i29; - input fabric_lowskew_i3; - input fabric_lowskew_i30; - input fabric_lowskew_i31; - input fabric_lowskew_i32; - input fabric_lowskew_i33; - input fabric_lowskew_i34; - input fabric_lowskew_i35; - input fabric_lowskew_i36; - input fabric_lowskew_i37; - input fabric_lowskew_i38; - input fabric_lowskew_i39; - input fabric_lowskew_i4; - input fabric_lowskew_i40; - input fabric_lowskew_i5; - input fabric_lowskew_i6; - input fabric_lowskew_i7; - input fabric_lowskew_i8; - input fabric_lowskew_i9; - output fabric_lowskew_o1; - output fabric_lowskew_o2; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - input fabric_mrepair_bend_i; - output fabric_mrepair_bist_mode_o; - output fabric_mrepair_bypass_o; - output fabric_mrepair_chip_status_o1; - output fabric_mrepair_chip_status_o10; - output fabric_mrepair_chip_status_o11; - output fabric_mrepair_chip_status_o12; - output fabric_mrepair_chip_status_o13; - output fabric_mrepair_chip_status_o14; - output fabric_mrepair_chip_status_o15; - output fabric_mrepair_chip_status_o16; - output fabric_mrepair_chip_status_o17; - output fabric_mrepair_chip_status_o18; - output fabric_mrepair_chip_status_o19; - output fabric_mrepair_chip_status_o2; - output fabric_mrepair_chip_status_o20; - output fabric_mrepair_chip_status_o21; - output fabric_mrepair_chip_status_o22; - output fabric_mrepair_chip_status_o23; - output fabric_mrepair_chip_status_o24; - output fabric_mrepair_chip_status_o25; - output fabric_mrepair_chip_status_o26; - output fabric_mrepair_chip_status_o27; - output fabric_mrepair_chip_status_o28; - output fabric_mrepair_chip_status_o29; - output fabric_mrepair_chip_status_o3; - output fabric_mrepair_chip_status_o30; - output fabric_mrepair_chip_status_o31; - output fabric_mrepair_chip_status_o32; - output fabric_mrepair_chip_status_o33; - output fabric_mrepair_chip_status_o34; - output fabric_mrepair_chip_status_o35; - output fabric_mrepair_chip_status_o36; - output fabric_mrepair_chip_status_o37; - output fabric_mrepair_chip_status_o38; - output fabric_mrepair_chip_status_o39; - output fabric_mrepair_chip_status_o4; - output fabric_mrepair_chip_status_o40; - output fabric_mrepair_chip_status_o41; - output fabric_mrepair_chip_status_o42; - output fabric_mrepair_chip_status_o43; - output fabric_mrepair_chip_status_o44; - output fabric_mrepair_chip_status_o45; - output fabric_mrepair_chip_status_o46; - output fabric_mrepair_chip_status_o47; - output fabric_mrepair_chip_status_o48; - output fabric_mrepair_chip_status_o49; - output fabric_mrepair_chip_status_o5; - output fabric_mrepair_chip_status_o50; - output fabric_mrepair_chip_status_o51; - output fabric_mrepair_chip_status_o52; - output fabric_mrepair_chip_status_o53; - output fabric_mrepair_chip_status_o54; - output fabric_mrepair_chip_status_o55; - output fabric_mrepair_chip_status_o56; - output fabric_mrepair_chip_status_o57; - output fabric_mrepair_chip_status_o58; - output fabric_mrepair_chip_status_o59; - output fabric_mrepair_chip_status_o6; - output fabric_mrepair_chip_status_o60; - output fabric_mrepair_chip_status_o61; - output fabric_mrepair_chip_status_o62; - output fabric_mrepair_chip_status_o63; - output fabric_mrepair_chip_status_o64; - output fabric_mrepair_chip_status_o65; - output fabric_mrepair_chip_status_o66; - output fabric_mrepair_chip_status_o67; - output fabric_mrepair_chip_status_o68; - output fabric_mrepair_chip_status_o69; - output fabric_mrepair_chip_status_o7; - output fabric_mrepair_chip_status_o70; - output fabric_mrepair_chip_status_o71; - output fabric_mrepair_chip_status_o72; - output fabric_mrepair_chip_status_o73; - output fabric_mrepair_chip_status_o74; - output fabric_mrepair_chip_status_o75; - output fabric_mrepair_chip_status_o76; - output fabric_mrepair_chip_status_o77; - output fabric_mrepair_chip_status_o78; - output fabric_mrepair_chip_status_o8; - output fabric_mrepair_chip_status_o9; - input fabric_mrepair_cke_force_i; - input fabric_mrepair_cke_i; - input fabric_mrepair_clk_i; - input fabric_mrepair_data_from_bist_i1; - input fabric_mrepair_data_from_bist_i10; - input fabric_mrepair_data_from_bist_i11; - input fabric_mrepair_data_from_bist_i12; - input fabric_mrepair_data_from_bist_i13; - input fabric_mrepair_data_from_bist_i14; - input fabric_mrepair_data_from_bist_i15; - input fabric_mrepair_data_from_bist_i16; - input fabric_mrepair_data_from_bist_i17; - input fabric_mrepair_data_from_bist_i18; - input fabric_mrepair_data_from_bist_i19; - input fabric_mrepair_data_from_bist_i2; - input fabric_mrepair_data_from_bist_i20; - input fabric_mrepair_data_from_bist_i21; - input fabric_mrepair_data_from_bist_i22; - input fabric_mrepair_data_from_bist_i23; - input fabric_mrepair_data_from_bist_i24; - input fabric_mrepair_data_from_bist_i25; - input fabric_mrepair_data_from_bist_i26; - input fabric_mrepair_data_from_bist_i3; - input fabric_mrepair_data_from_bist_i4; - input fabric_mrepair_data_from_bist_i5; - input fabric_mrepair_data_from_bist_i6; - input fabric_mrepair_data_from_bist_i7; - input fabric_mrepair_data_from_bist_i8; - input fabric_mrepair_data_from_bist_i9; - input fabric_mrepair_data_from_system_i; - input fabric_mrepair_data_shift_en_i; - output fabric_mrepair_data_to_bist_o1; - output fabric_mrepair_data_to_bist_o10; - output fabric_mrepair_data_to_bist_o11; - output fabric_mrepair_data_to_bist_o12; - output fabric_mrepair_data_to_bist_o13; - output fabric_mrepair_data_to_bist_o14; - output fabric_mrepair_data_to_bist_o15; - output fabric_mrepair_data_to_bist_o16; - output fabric_mrepair_data_to_bist_o17; - output fabric_mrepair_data_to_bist_o18; - output fabric_mrepair_data_to_bist_o19; - output fabric_mrepair_data_to_bist_o2; - output fabric_mrepair_data_to_bist_o20; - output fabric_mrepair_data_to_bist_o21; - output fabric_mrepair_data_to_bist_o22; - output fabric_mrepair_data_to_bist_o23; - output fabric_mrepair_data_to_bist_o24; - output fabric_mrepair_data_to_bist_o25; - output fabric_mrepair_data_to_bist_o26; - output fabric_mrepair_data_to_bist_o3; - output fabric_mrepair_data_to_bist_o4; - output fabric_mrepair_data_to_bist_o5; - output fabric_mrepair_data_to_bist_o6; - output fabric_mrepair_data_to_bist_o7; - output fabric_mrepair_data_to_bist_o8; - output fabric_mrepair_data_to_bist_o9; - output fabric_mrepair_data_to_system_o; - output fabric_mrepair_decoder_init_ready_o; - input fabric_mrepair_end_encoding_i; - output fabric_mrepair_fuse_ack_o; - input fabric_mrepair_fuse_add_i1; - input fabric_mrepair_fuse_add_i2; - input fabric_mrepair_fuse_add_i3; - input fabric_mrepair_fuse_add_i4; - input fabric_mrepair_fuse_add_i5; - input fabric_mrepair_fuse_add_i6; - input fabric_mrepair_fuse_add_i7; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output fabric_mrepair_fuse_bist1fail_o1; - output fabric_mrepair_fuse_bist1fail_o2; - output fabric_mrepair_fuse_bist1fail_o3; - output fabric_mrepair_fuse_bist1fail_o4; - output fabric_mrepair_fuse_bist1fail_o5; - output fabric_mrepair_fuse_bist1fail_o6; - output fabric_mrepair_fuse_bist1fail_o7; - output fabric_mrepair_fuse_bist1fail_o8; - output fabric_mrepair_fuse_bist2fail_o1; - output fabric_mrepair_fuse_bist2fail_o2; - output fabric_mrepair_fuse_bist2fail_o3; - output fabric_mrepair_fuse_bist2fail_o4; - output fabric_mrepair_fuse_bist2fail_o5; - output fabric_mrepair_fuse_bist2fail_o6; - output fabric_mrepair_fuse_bist2fail_o7; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - output fabric_mrepair_fuse_ded_o; - input fabric_mrepair_fuse_din_i1; - input fabric_mrepair_fuse_din_i10; - input fabric_mrepair_fuse_din_i11; - input fabric_mrepair_fuse_din_i12; - input fabric_mrepair_fuse_din_i13; - input fabric_mrepair_fuse_din_i14; - input fabric_mrepair_fuse_din_i15; - input fabric_mrepair_fuse_din_i16; - input fabric_mrepair_fuse_din_i17; - input fabric_mrepair_fuse_din_i18; - input fabric_mrepair_fuse_din_i19; - input fabric_mrepair_fuse_din_i2; - input fabric_mrepair_fuse_din_i20; - input fabric_mrepair_fuse_din_i21; - input fabric_mrepair_fuse_din_i22; - input fabric_mrepair_fuse_din_i23; - input fabric_mrepair_fuse_din_i24; - input fabric_mrepair_fuse_din_i25; - input fabric_mrepair_fuse_din_i26; - input fabric_mrepair_fuse_din_i27; - input fabric_mrepair_fuse_din_i28; - input fabric_mrepair_fuse_din_i29; - input fabric_mrepair_fuse_din_i3; - input fabric_mrepair_fuse_din_i30; - input fabric_mrepair_fuse_din_i31; - input fabric_mrepair_fuse_din_i32; - input fabric_mrepair_fuse_din_i33; - input fabric_mrepair_fuse_din_i34; - input fabric_mrepair_fuse_din_i35; - input fabric_mrepair_fuse_din_i36; - input fabric_mrepair_fuse_din_i37; - input fabric_mrepair_fuse_din_i38; - input fabric_mrepair_fuse_din_i39; - input fabric_mrepair_fuse_din_i4; - input fabric_mrepair_fuse_din_i5; - input fabric_mrepair_fuse_din_i6; - input fabric_mrepair_fuse_din_i7; - input fabric_mrepair_fuse_din_i8; - input fabric_mrepair_fuse_din_i9; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output fabric_mrepair_fuse_dout_o1; - output fabric_mrepair_fuse_dout_o10; - output fabric_mrepair_fuse_dout_o11; - output fabric_mrepair_fuse_dout_o12; - output fabric_mrepair_fuse_dout_o13; - output fabric_mrepair_fuse_dout_o14; - output fabric_mrepair_fuse_dout_o15; - output fabric_mrepair_fuse_dout_o16; - output fabric_mrepair_fuse_dout_o17; - output fabric_mrepair_fuse_dout_o18; - output fabric_mrepair_fuse_dout_o19; - output fabric_mrepair_fuse_dout_o2; - output fabric_mrepair_fuse_dout_o20; - output fabric_mrepair_fuse_dout_o21; - output fabric_mrepair_fuse_dout_o22; - output fabric_mrepair_fuse_dout_o23; - output fabric_mrepair_fuse_dout_o24; - output fabric_mrepair_fuse_dout_o25; - output fabric_mrepair_fuse_dout_o26; - output fabric_mrepair_fuse_dout_o27; - output fabric_mrepair_fuse_dout_o28; - output fabric_mrepair_fuse_dout_o29; - output fabric_mrepair_fuse_dout_o3; - output fabric_mrepair_fuse_dout_o30; - output fabric_mrepair_fuse_dout_o31; - output fabric_mrepair_fuse_dout_o32; - output fabric_mrepair_fuse_dout_o33; - output fabric_mrepair_fuse_dout_o34; - output fabric_mrepair_fuse_dout_o35; - output fabric_mrepair_fuse_dout_o36; - output fabric_mrepair_fuse_dout_o37; - output fabric_mrepair_fuse_dout_o38; - output fabric_mrepair_fuse_dout_o39; - output fabric_mrepair_fuse_dout_o4; - output fabric_mrepair_fuse_dout_o40; - output fabric_mrepair_fuse_dout_o41; - output fabric_mrepair_fuse_dout_o5; - output fabric_mrepair_fuse_dout_o6; - output fabric_mrepair_fuse_dout_o7; - output fabric_mrepair_fuse_dout_o8; - output fabric_mrepair_fuse_dout_o9; - input fabric_mrepair_fuse_eccbypass_i; - output fabric_mrepair_fuse_flagstate_o1; - output fabric_mrepair_fuse_flagstate_o2; - output fabric_mrepair_fuse_flagstate_o3; - output fabric_mrepair_fuse_flagstate_o4; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input fabric_mrepair_fuse_prgwidth_i1; - input fabric_mrepair_fuse_prgwidth_i2; - input fabric_mrepair_fuse_prgwidth_i3; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output fabric_mrepair_fuse_startword_o1; - output fabric_mrepair_fuse_startword_o10; - output fabric_mrepair_fuse_startword_o11; - output fabric_mrepair_fuse_startword_o12; - output fabric_mrepair_fuse_startword_o13; - output fabric_mrepair_fuse_startword_o14; - output fabric_mrepair_fuse_startword_o15; - output fabric_mrepair_fuse_startword_o16; - output fabric_mrepair_fuse_startword_o2; - output fabric_mrepair_fuse_startword_o3; - output fabric_mrepair_fuse_startword_o4; - output fabric_mrepair_fuse_startword_o5; - output fabric_mrepair_fuse_startword_o6; - output fabric_mrepair_fuse_startword_o7; - output fabric_mrepair_fuse_startword_o8; - output fabric_mrepair_fuse_startword_o9; - output fabric_mrepair_fuse_status_o1; - output fabric_mrepair_fuse_status_o2; - output fabric_mrepair_fuse_status_o3; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input fabric_mrepair_fuse_tst_scanin_i1; - input fabric_mrepair_fuse_tst_scanin_i2; - input fabric_mrepair_fuse_tst_scanin_i3; - input fabric_mrepair_fuse_tst_scanin_i4; - input fabric_mrepair_fuse_tst_scanin_i5; - input fabric_mrepair_fuse_tstscanenable_i; - output fabric_mrepair_fuse_tstscanout_o1; - output fabric_mrepair_fuse_tstscanout_o2; - output fabric_mrepair_fuse_tstscanout_o3; - output fabric_mrepair_fuse_tstscanout_o4; - output fabric_mrepair_fuse_tstscanout_o5; - output fabric_mrepair_fuse_wlromout_o1; - output fabric_mrepair_fuse_wlromout_o10; - output fabric_mrepair_fuse_wlromout_o2; - output fabric_mrepair_fuse_wlromout_o3; - output fabric_mrepair_fuse_wlromout_o4; - output fabric_mrepair_fuse_wlromout_o5; - output fabric_mrepair_fuse_wlromout_o6; - output fabric_mrepair_fuse_wlromout_o7; - output fabric_mrepair_fuse_wlromout_o8; - output fabric_mrepair_fuse_wlromout_o9; - input fabric_mrepair_fuse_wordlock_i; - input fabric_mrepair_global_bbad_i; - output fabric_mrepair_global_chip_status_o1; - output fabric_mrepair_global_chip_status_o2; - output fabric_mrepair_global_chip_status_o3; - input fabric_mrepair_global_repairable_i; - input fabric_mrepair_initn_i; - output fabric_mrepair_mem_atpg_mode_o; - output fabric_mrepair_mem_type_sel_o1; - output fabric_mrepair_mem_type_sel_o2; - output fabric_mrepair_mem_type_sel_o3; - output fabric_mrepair_mem_type_sel_o4; - output fabric_mrepair_mem_type_sel_o5; - output fabric_mrepair_memsafe_o; - input fabric_mrepair_mode_i1; - input fabric_mrepair_mode_i2; - input fabric_mrepair_mode_i3; - input fabric_mrepair_mode_i4; - output fabric_mrepair_mode_sel_o1; - output fabric_mrepair_mode_sel_o2; - output fabric_mrepair_mode_sel_o3; - output fabric_mrepair_mode_sel_o4; - input fabric_mrepair_pd_active_i1; - input fabric_mrepair_pd_active_i10; - input fabric_mrepair_pd_active_i11; - input fabric_mrepair_pd_active_i12; - input fabric_mrepair_pd_active_i13; - input fabric_mrepair_pd_active_i14; - input fabric_mrepair_pd_active_i15; - input fabric_mrepair_pd_active_i16; - input fabric_mrepair_pd_active_i17; - input fabric_mrepair_pd_active_i18; - input fabric_mrepair_pd_active_i19; - input fabric_mrepair_pd_active_i2; - input fabric_mrepair_pd_active_i20; - input fabric_mrepair_pd_active_i21; - input fabric_mrepair_pd_active_i22; - input fabric_mrepair_pd_active_i23; - input fabric_mrepair_pd_active_i24; - input fabric_mrepair_pd_active_i25; - input fabric_mrepair_pd_active_i26; - input fabric_mrepair_pd_active_i3; - input fabric_mrepair_pd_active_i4; - input fabric_mrepair_pd_active_i5; - input fabric_mrepair_pd_active_i6; - input fabric_mrepair_pd_active_i7; - input fabric_mrepair_pd_active_i8; - input fabric_mrepair_pd_active_i9; - output fabric_mrepair_pd_ready_o1; - output fabric_mrepair_pd_ready_o10; - output fabric_mrepair_pd_ready_o11; - output fabric_mrepair_pd_ready_o12; - output fabric_mrepair_pd_ready_o13; - output fabric_mrepair_pd_ready_o14; - output fabric_mrepair_pd_ready_o15; - output fabric_mrepair_pd_ready_o16; - output fabric_mrepair_pd_ready_o17; - output fabric_mrepair_pd_ready_o18; - output fabric_mrepair_pd_ready_o19; - output fabric_mrepair_pd_ready_o2; - output fabric_mrepair_pd_ready_o20; - output fabric_mrepair_pd_ready_o21; - output fabric_mrepair_pd_ready_o22; - output fabric_mrepair_pd_ready_o23; - output fabric_mrepair_pd_ready_o24; - output fabric_mrepair_pd_ready_o25; - output fabric_mrepair_pd_ready_o26; - output fabric_mrepair_pd_ready_o3; - output fabric_mrepair_pd_ready_o4; - output fabric_mrepair_pd_ready_o5; - output fabric_mrepair_pd_ready_o6; - output fabric_mrepair_pd_ready_o7; - output fabric_mrepair_pd_ready_o8; - output fabric_mrepair_pd_ready_o9; - input fabric_mrepair_por_i; - input fabric_mrepair_rst_n_i; - input fabric_mrepair_shift_en_i1; - input fabric_mrepair_shift_en_i10; - input fabric_mrepair_shift_en_i11; - input fabric_mrepair_shift_en_i12; - input fabric_mrepair_shift_en_i13; - input fabric_mrepair_shift_en_i14; - input fabric_mrepair_shift_en_i15; - input fabric_mrepair_shift_en_i16; - input fabric_mrepair_shift_en_i17; - input fabric_mrepair_shift_en_i18; - input fabric_mrepair_shift_en_i19; - input fabric_mrepair_shift_en_i2; - input fabric_mrepair_shift_en_i20; - input fabric_mrepair_shift_en_i21; - input fabric_mrepair_shift_en_i22; - input fabric_mrepair_shift_en_i23; - input fabric_mrepair_shift_en_i24; - input fabric_mrepair_shift_en_i25; - input fabric_mrepair_shift_en_i26; - input fabric_mrepair_shift_en_i3; - input fabric_mrepair_shift_en_i4; - input fabric_mrepair_shift_en_i5; - input fabric_mrepair_shift_en_i6; - input fabric_mrepair_shift_en_i7; - input fabric_mrepair_shift_en_i8; - input fabric_mrepair_shift_en_i9; - output fabric_mrepair_shift_en_to_bist_o1; - output fabric_mrepair_shift_en_to_bist_o10; - output fabric_mrepair_shift_en_to_bist_o11; - output fabric_mrepair_shift_en_to_bist_o12; - output fabric_mrepair_shift_en_to_bist_o13; - output fabric_mrepair_shift_en_to_bist_o14; - output fabric_mrepair_shift_en_to_bist_o15; - output fabric_mrepair_shift_en_to_bist_o16; - output fabric_mrepair_shift_en_to_bist_o17; - output fabric_mrepair_shift_en_to_bist_o18; - output fabric_mrepair_shift_en_to_bist_o19; - output fabric_mrepair_shift_en_to_bist_o2; - output fabric_mrepair_shift_en_to_bist_o20; - output fabric_mrepair_shift_en_to_bist_o21; - output fabric_mrepair_shift_en_to_bist_o22; - output fabric_mrepair_shift_en_to_bist_o23; - output fabric_mrepair_shift_en_to_bist_o24; - output fabric_mrepair_shift_en_to_bist_o25; - output fabric_mrepair_shift_en_to_bist_o26; - output fabric_mrepair_shift_en_to_bist_o3; - output fabric_mrepair_shift_en_to_bist_o4; - output fabric_mrepair_shift_en_to_bist_o5; - output fabric_mrepair_shift_en_to_bist_o6; - output fabric_mrepair_shift_en_to_bist_o7; - output fabric_mrepair_shift_en_to_bist_o8; - output fabric_mrepair_shift_en_to_bist_o9; - input fabric_mrepair_sif_load_en_i1; - input fabric_mrepair_sif_load_en_i10; - input fabric_mrepair_sif_load_en_i11; - input fabric_mrepair_sif_load_en_i12; - input fabric_mrepair_sif_load_en_i13; - input fabric_mrepair_sif_load_en_i14; - input fabric_mrepair_sif_load_en_i15; - input fabric_mrepair_sif_load_en_i16; - input fabric_mrepair_sif_load_en_i17; - input fabric_mrepair_sif_load_en_i18; - input fabric_mrepair_sif_load_en_i19; - input fabric_mrepair_sif_load_en_i2; - input fabric_mrepair_sif_load_en_i20; - input fabric_mrepair_sif_load_en_i21; - input fabric_mrepair_sif_load_en_i22; - input fabric_mrepair_sif_load_en_i23; - input fabric_mrepair_sif_load_en_i24; - input fabric_mrepair_sif_load_en_i25; - input fabric_mrepair_sif_load_en_i26; - input fabric_mrepair_sif_load_en_i3; - input fabric_mrepair_sif_load_en_i4; - input fabric_mrepair_sif_load_en_i5; - input fabric_mrepair_sif_load_en_i6; - input fabric_mrepair_sif_load_en_i7; - input fabric_mrepair_sif_load_en_i8; - input fabric_mrepair_sif_load_en_i9; - output fabric_mrepair_sif_load_en_to_bist_o1; - output fabric_mrepair_sif_load_en_to_bist_o10; - output fabric_mrepair_sif_load_en_to_bist_o11; - output fabric_mrepair_sif_load_en_to_bist_o12; - output fabric_mrepair_sif_load_en_to_bist_o13; - output fabric_mrepair_sif_load_en_to_bist_o14; - output fabric_mrepair_sif_load_en_to_bist_o15; - output fabric_mrepair_sif_load_en_to_bist_o16; - output fabric_mrepair_sif_load_en_to_bist_o17; - output fabric_mrepair_sif_load_en_to_bist_o18; - output fabric_mrepair_sif_load_en_to_bist_o19; - output fabric_mrepair_sif_load_en_to_bist_o2; - output fabric_mrepair_sif_load_en_to_bist_o20; - output fabric_mrepair_sif_load_en_to_bist_o21; - output fabric_mrepair_sif_load_en_to_bist_o22; - output fabric_mrepair_sif_load_en_to_bist_o23; - output fabric_mrepair_sif_load_en_to_bist_o24; - output fabric_mrepair_sif_load_en_to_bist_o25; - output fabric_mrepair_sif_load_en_to_bist_o26; - output fabric_mrepair_sif_load_en_to_bist_o3; - output fabric_mrepair_sif_load_en_to_bist_o4; - output fabric_mrepair_sif_load_en_to_bist_o5; - output fabric_mrepair_sif_load_en_to_bist_o6; - output fabric_mrepair_sif_load_en_to_bist_o7; - output fabric_mrepair_sif_load_en_to_bist_o8; - output fabric_mrepair_sif_load_en_to_bist_o9; - input fabric_mrepair_sif_reg_en_i1; - input fabric_mrepair_sif_reg_en_i10; - input fabric_mrepair_sif_reg_en_i11; - input fabric_mrepair_sif_reg_en_i12; - input fabric_mrepair_sif_reg_en_i13; - input fabric_mrepair_sif_reg_en_i14; - input fabric_mrepair_sif_reg_en_i15; - input fabric_mrepair_sif_reg_en_i16; - input fabric_mrepair_sif_reg_en_i17; - input fabric_mrepair_sif_reg_en_i18; - input fabric_mrepair_sif_reg_en_i19; - input fabric_mrepair_sif_reg_en_i2; - input fabric_mrepair_sif_reg_en_i20; - input fabric_mrepair_sif_reg_en_i21; - input fabric_mrepair_sif_reg_en_i22; - input fabric_mrepair_sif_reg_en_i23; - input fabric_mrepair_sif_reg_en_i24; - input fabric_mrepair_sif_reg_en_i25; - input fabric_mrepair_sif_reg_en_i26; - input fabric_mrepair_sif_reg_en_i3; - input fabric_mrepair_sif_reg_en_i4; - input fabric_mrepair_sif_reg_en_i5; - input fabric_mrepair_sif_reg_en_i6; - input fabric_mrepair_sif_reg_en_i7; - input fabric_mrepair_sif_reg_en_i8; - input fabric_mrepair_sif_reg_en_i9; - output fabric_mrepair_sif_reg_en_to_bist_o1; - output fabric_mrepair_sif_reg_en_to_bist_o10; - output fabric_mrepair_sif_reg_en_to_bist_o11; - output fabric_mrepair_sif_reg_en_to_bist_o12; - output fabric_mrepair_sif_reg_en_to_bist_o13; - output fabric_mrepair_sif_reg_en_to_bist_o14; - output fabric_mrepair_sif_reg_en_to_bist_o15; - output fabric_mrepair_sif_reg_en_to_bist_o16; - output fabric_mrepair_sif_reg_en_to_bist_o17; - output fabric_mrepair_sif_reg_en_to_bist_o18; - output fabric_mrepair_sif_reg_en_to_bist_o19; - output fabric_mrepair_sif_reg_en_to_bist_o2; - output fabric_mrepair_sif_reg_en_to_bist_o20; - output fabric_mrepair_sif_reg_en_to_bist_o21; - output fabric_mrepair_sif_reg_en_to_bist_o22; - output fabric_mrepair_sif_reg_en_to_bist_o23; - output fabric_mrepair_sif_reg_en_to_bist_o24; - output fabric_mrepair_sif_reg_en_to_bist_o25; - output fabric_mrepair_sif_reg_en_to_bist_o26; - output fabric_mrepair_sif_reg_en_to_bist_o3; - output fabric_mrepair_sif_reg_en_to_bist_o4; - output fabric_mrepair_sif_reg_en_to_bist_o5; - output fabric_mrepair_sif_reg_en_to_bist_o6; - output fabric_mrepair_sif_reg_en_to_bist_o7; - output fabric_mrepair_sif_reg_en_to_bist_o8; - output fabric_mrepair_sif_reg_en_to_bist_o9; - input fabric_mrepair_sif_update_en_i1; - input fabric_mrepair_sif_update_en_i10; - input fabric_mrepair_sif_update_en_i11; - input fabric_mrepair_sif_update_en_i12; - input fabric_mrepair_sif_update_en_i13; - input fabric_mrepair_sif_update_en_i14; - input fabric_mrepair_sif_update_en_i15; - input fabric_mrepair_sif_update_en_i16; - input fabric_mrepair_sif_update_en_i17; - input fabric_mrepair_sif_update_en_i18; - input fabric_mrepair_sif_update_en_i19; - input fabric_mrepair_sif_update_en_i2; - input fabric_mrepair_sif_update_en_i20; - input fabric_mrepair_sif_update_en_i21; - input fabric_mrepair_sif_update_en_i22; - input fabric_mrepair_sif_update_en_i23; - input fabric_mrepair_sif_update_en_i24; - input fabric_mrepair_sif_update_en_i25; - input fabric_mrepair_sif_update_en_i26; - input fabric_mrepair_sif_update_en_i3; - input fabric_mrepair_sif_update_en_i4; - input fabric_mrepair_sif_update_en_i5; - input fabric_mrepair_sif_update_en_i6; - input fabric_mrepair_sif_update_en_i7; - input fabric_mrepair_sif_update_en_i8; - input fabric_mrepair_sif_update_en_i9; - output fabric_mrepair_sif_update_en_to_bist_o1; - output fabric_mrepair_sif_update_en_to_bist_o10; - output fabric_mrepair_sif_update_en_to_bist_o11; - output fabric_mrepair_sif_update_en_to_bist_o12; - output fabric_mrepair_sif_update_en_to_bist_o13; - output fabric_mrepair_sif_update_en_to_bist_o14; - output fabric_mrepair_sif_update_en_to_bist_o15; - output fabric_mrepair_sif_update_en_to_bist_o16; - output fabric_mrepair_sif_update_en_to_bist_o17; - output fabric_mrepair_sif_update_en_to_bist_o18; - output fabric_mrepair_sif_update_en_to_bist_o19; - output fabric_mrepair_sif_update_en_to_bist_o2; - output fabric_mrepair_sif_update_en_to_bist_o20; - output fabric_mrepair_sif_update_en_to_bist_o21; - output fabric_mrepair_sif_update_en_to_bist_o22; - output fabric_mrepair_sif_update_en_to_bist_o23; - output fabric_mrepair_sif_update_en_to_bist_o24; - output fabric_mrepair_sif_update_en_to_bist_o25; - output fabric_mrepair_sif_update_en_to_bist_o26; - output fabric_mrepair_sif_update_en_to_bist_o3; - output fabric_mrepair_sif_update_en_to_bist_o4; - output fabric_mrepair_sif_update_en_to_bist_o5; - output fabric_mrepair_sif_update_en_to_bist_o6; - output fabric_mrepair_sif_update_en_to_bist_o7; - output fabric_mrepair_sif_update_en_to_bist_o8; - output fabric_mrepair_sif_update_en_to_bist_o9; - output fabric_mrepair_system_data_from_mem_bist_o1; - output fabric_mrepair_system_data_from_mem_bist_o10; - output fabric_mrepair_system_data_from_mem_bist_o11; - output fabric_mrepair_system_data_from_mem_bist_o12; - output fabric_mrepair_system_data_from_mem_bist_o13; - output fabric_mrepair_system_data_from_mem_bist_o14; - output fabric_mrepair_system_data_from_mem_bist_o15; - output fabric_mrepair_system_data_from_mem_bist_o16; - output fabric_mrepair_system_data_from_mem_bist_o17; - output fabric_mrepair_system_data_from_mem_bist_o18; - output fabric_mrepair_system_data_from_mem_bist_o19; - output fabric_mrepair_system_data_from_mem_bist_o2; - output fabric_mrepair_system_data_from_mem_bist_o20; - output fabric_mrepair_system_data_from_mem_bist_o21; - output fabric_mrepair_system_data_from_mem_bist_o22; - output fabric_mrepair_system_data_from_mem_bist_o23; - output fabric_mrepair_system_data_from_mem_bist_o24; - output fabric_mrepair_system_data_from_mem_bist_o25; - output fabric_mrepair_system_data_from_mem_bist_o26; - output fabric_mrepair_system_data_from_mem_bist_o3; - output fabric_mrepair_system_data_from_mem_bist_o4; - output fabric_mrepair_system_data_from_mem_bist_o5; - output fabric_mrepair_system_data_from_mem_bist_o6; - output fabric_mrepair_system_data_from_mem_bist_o7; - output fabric_mrepair_system_data_from_mem_bist_o8; - output fabric_mrepair_system_data_from_mem_bist_o9; - input fabric_mrepair_system_data_to_mem_bist_i1; - input fabric_mrepair_system_data_to_mem_bist_i10; - input fabric_mrepair_system_data_to_mem_bist_i11; - input fabric_mrepair_system_data_to_mem_bist_i12; - input fabric_mrepair_system_data_to_mem_bist_i13; - input fabric_mrepair_system_data_to_mem_bist_i14; - input fabric_mrepair_system_data_to_mem_bist_i15; - input fabric_mrepair_system_data_to_mem_bist_i16; - input fabric_mrepair_system_data_to_mem_bist_i17; - input fabric_mrepair_system_data_to_mem_bist_i18; - input fabric_mrepair_system_data_to_mem_bist_i19; - input fabric_mrepair_system_data_to_mem_bist_i2; - input fabric_mrepair_system_data_to_mem_bist_i20; - input fabric_mrepair_system_data_to_mem_bist_i21; - input fabric_mrepair_system_data_to_mem_bist_i22; - input fabric_mrepair_system_data_to_mem_bist_i23; - input fabric_mrepair_system_data_to_mem_bist_i24; - input fabric_mrepair_system_data_to_mem_bist_i25; - input fabric_mrepair_system_data_to_mem_bist_i26; - input fabric_mrepair_system_data_to_mem_bist_i3; - input fabric_mrepair_system_data_to_mem_bist_i4; - input fabric_mrepair_system_data_to_mem_bist_i5; - input fabric_mrepair_system_data_to_mem_bist_i6; - input fabric_mrepair_system_data_to_mem_bist_i7; - input fabric_mrepair_system_data_to_mem_bist_i8; - input fabric_mrepair_system_data_to_mem_bist_i9; - output fabric_mrepair_system_dataready_o; - output fabric_mrepair_test_se_o; - input fabric_mrepair_tst_atpg_mrepair_i; - output fabric_mrepair_tst_gatedclock_o; - input fabric_otp_apb_addr_i1; - input fabric_otp_apb_addr_i10; - input fabric_otp_apb_addr_i11; - input fabric_otp_apb_addr_i12; - input fabric_otp_apb_addr_i13; - input fabric_otp_apb_addr_i14; - input fabric_otp_apb_addr_i15; - input fabric_otp_apb_addr_i16; - input fabric_otp_apb_addr_i17; - input fabric_otp_apb_addr_i18; - input fabric_otp_apb_addr_i19; - input fabric_otp_apb_addr_i2; - input fabric_otp_apb_addr_i20; - input fabric_otp_apb_addr_i21; - input fabric_otp_apb_addr_i22; - input fabric_otp_apb_addr_i23; - input fabric_otp_apb_addr_i24; - input fabric_otp_apb_addr_i25; - input fabric_otp_apb_addr_i26; - input fabric_otp_apb_addr_i27; - input fabric_otp_apb_addr_i28; - input fabric_otp_apb_addr_i29; - input fabric_otp_apb_addr_i3; - input fabric_otp_apb_addr_i30; - input fabric_otp_apb_addr_i31; - input fabric_otp_apb_addr_i32; - input fabric_otp_apb_addr_i4; - input fabric_otp_apb_addr_i5; - input fabric_otp_apb_addr_i6; - input fabric_otp_apb_addr_i7; - input fabric_otp_apb_addr_i8; - input fabric_otp_apb_addr_i9; - input fabric_otp_apb_enable_i; - output fabric_otp_apb_rdata_o1; - output fabric_otp_apb_rdata_o10; - output fabric_otp_apb_rdata_o11; - output fabric_otp_apb_rdata_o12; - output fabric_otp_apb_rdata_o13; - output fabric_otp_apb_rdata_o14; - output fabric_otp_apb_rdata_o15; - output fabric_otp_apb_rdata_o16; - output fabric_otp_apb_rdata_o17; - output fabric_otp_apb_rdata_o18; - output fabric_otp_apb_rdata_o19; - output fabric_otp_apb_rdata_o2; - output fabric_otp_apb_rdata_o20; - output fabric_otp_apb_rdata_o21; - output fabric_otp_apb_rdata_o22; - output fabric_otp_apb_rdata_o23; - output fabric_otp_apb_rdata_o24; - output fabric_otp_apb_rdata_o25; - output fabric_otp_apb_rdata_o26; - output fabric_otp_apb_rdata_o27; - output fabric_otp_apb_rdata_o28; - output fabric_otp_apb_rdata_o29; - output fabric_otp_apb_rdata_o3; - output fabric_otp_apb_rdata_o30; - output fabric_otp_apb_rdata_o31; - output fabric_otp_apb_rdata_o32; - output fabric_otp_apb_rdata_o4; - output fabric_otp_apb_rdata_o5; - output fabric_otp_apb_rdata_o6; - output fabric_otp_apb_rdata_o7; - output fabric_otp_apb_rdata_o8; - output fabric_otp_apb_rdata_o9; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input fabric_otp_apb_wdata_i1; - input fabric_otp_apb_wdata_i10; - input fabric_otp_apb_wdata_i11; - input fabric_otp_apb_wdata_i12; - input fabric_otp_apb_wdata_i13; - input fabric_otp_apb_wdata_i14; - input fabric_otp_apb_wdata_i15; - input fabric_otp_apb_wdata_i16; - input fabric_otp_apb_wdata_i17; - input fabric_otp_apb_wdata_i18; - input fabric_otp_apb_wdata_i19; - input fabric_otp_apb_wdata_i2; - input fabric_otp_apb_wdata_i20; - input fabric_otp_apb_wdata_i21; - input fabric_otp_apb_wdata_i22; - input fabric_otp_apb_wdata_i23; - input fabric_otp_apb_wdata_i24; - input fabric_otp_apb_wdata_i25; - input fabric_otp_apb_wdata_i26; - input fabric_otp_apb_wdata_i27; - input fabric_otp_apb_wdata_i28; - input fabric_otp_apb_wdata_i29; - input fabric_otp_apb_wdata_i3; - input fabric_otp_apb_wdata_i30; - input fabric_otp_apb_wdata_i31; - input fabric_otp_apb_wdata_i32; - input fabric_otp_apb_wdata_i4; - input fabric_otp_apb_wdata_i5; - input fabric_otp_apb_wdata_i6; - input fabric_otp_apb_wdata_i7; - input fabric_otp_apb_wdata_i8; - input fabric_otp_apb_wdata_i9; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_clk_i; - input fabric_otp_rst_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output fabric_otp_security_bist_fail1_o1; - output fabric_otp_security_bist_fail1_o2; - output fabric_otp_security_bist_fail1_o3; - output fabric_otp_security_bist_fail1_o4; - output fabric_otp_security_bist_fail1_o5; - output fabric_otp_security_bist_fail1_o6; - output fabric_otp_security_bist_fail1_o7; - output fabric_otp_security_bist_fail2_o1; - output fabric_otp_security_bist_fail2_o2; - output fabric_otp_security_bist_fail2_o3; - output fabric_otp_security_bist_fail2_o4; - output fabric_otp_security_bist_fail2_o5; - output fabric_otp_security_bist_fail2_o6; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input fabric_otp_security_scanin_i1; - input fabric_otp_security_scanin_i2; - input fabric_otp_security_scanin_i3; - input fabric_otp_security_scanin_i4; - output fabric_otp_security_scanout_o1; - output fabric_otp_security_scanout_o2; - output fabric_otp_security_scanout_o3; - output fabric_otp_security_scanout_o4; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input fabric_otp_user_add_i1; - input fabric_otp_user_add_i2; - input fabric_otp_user_add_i3; - input fabric_otp_user_add_i4; - input fabric_otp_user_add_i5; - input fabric_otp_user_add_i6; - input fabric_otp_user_add_i7; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output fabric_otp_user_bist1fail_o1; - output fabric_otp_user_bist1fail_o2; - output fabric_otp_user_bist1fail_o3; - output fabric_otp_user_bist1fail_o4; - output fabric_otp_user_bist1fail_o5; - output fabric_otp_user_bist1fail_o6; - output fabric_otp_user_bist1fail_o7; - output fabric_otp_user_bist1fail_o8; - output fabric_otp_user_bist2fail_o1; - output fabric_otp_user_bist2fail_o2; - output fabric_otp_user_bist2fail_o3; - output fabric_otp_user_bist2fail_o4; - output fabric_otp_user_bist2fail_o5; - output fabric_otp_user_bist2fail_o6; - output fabric_otp_user_bist2fail_o7; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clk_i; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input fabric_otp_user_din_i1; - input fabric_otp_user_din_i10; - input fabric_otp_user_din_i11; - input fabric_otp_user_din_i12; - input fabric_otp_user_din_i13; - input fabric_otp_user_din_i14; - input fabric_otp_user_din_i15; - input fabric_otp_user_din_i16; - input fabric_otp_user_din_i17; - input fabric_otp_user_din_i18; - input fabric_otp_user_din_i19; - input fabric_otp_user_din_i2; - input fabric_otp_user_din_i20; - input fabric_otp_user_din_i21; - input fabric_otp_user_din_i22; - input fabric_otp_user_din_i23; - input fabric_otp_user_din_i24; - input fabric_otp_user_din_i25; - input fabric_otp_user_din_i26; - input fabric_otp_user_din_i27; - input fabric_otp_user_din_i28; - input fabric_otp_user_din_i29; - input fabric_otp_user_din_i3; - input fabric_otp_user_din_i30; - input fabric_otp_user_din_i31; - input fabric_otp_user_din_i32; - input fabric_otp_user_din_i33; - input fabric_otp_user_din_i34; - input fabric_otp_user_din_i35; - input fabric_otp_user_din_i36; - input fabric_otp_user_din_i37; - input fabric_otp_user_din_i38; - input fabric_otp_user_din_i39; - input fabric_otp_user_din_i4; - input fabric_otp_user_din_i5; - input fabric_otp_user_din_i6; - input fabric_otp_user_din_i7; - input fabric_otp_user_din_i8; - input fabric_otp_user_din_i9; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output fabric_otp_user_dout_o1; - output fabric_otp_user_dout_o10; - output fabric_otp_user_dout_o11; - output fabric_otp_user_dout_o12; - output fabric_otp_user_dout_o13; - output fabric_otp_user_dout_o14; - output fabric_otp_user_dout_o15; - output fabric_otp_user_dout_o16; - output fabric_otp_user_dout_o17; - output fabric_otp_user_dout_o18; - output fabric_otp_user_dout_o19; - output fabric_otp_user_dout_o2; - output fabric_otp_user_dout_o20; - output fabric_otp_user_dout_o21; - output fabric_otp_user_dout_o22; - output fabric_otp_user_dout_o23; - output fabric_otp_user_dout_o24; - output fabric_otp_user_dout_o25; - output fabric_otp_user_dout_o26; - output fabric_otp_user_dout_o27; - output fabric_otp_user_dout_o28; - output fabric_otp_user_dout_o29; - output fabric_otp_user_dout_o3; - output fabric_otp_user_dout_o30; - output fabric_otp_user_dout_o31; - output fabric_otp_user_dout_o32; - output fabric_otp_user_dout_o33; - output fabric_otp_user_dout_o34; - output fabric_otp_user_dout_o35; - output fabric_otp_user_dout_o36; - output fabric_otp_user_dout_o37; - output fabric_otp_user_dout_o38; - output fabric_otp_user_dout_o39; - output fabric_otp_user_dout_o4; - output fabric_otp_user_dout_o40; - output fabric_otp_user_dout_o41; - output fabric_otp_user_dout_o5; - output fabric_otp_user_dout_o6; - output fabric_otp_user_dout_o7; - output fabric_otp_user_dout_o8; - output fabric_otp_user_dout_o9; - input fabric_otp_user_eccbypass_i; - output fabric_otp_user_flagstate_o1; - output fabric_otp_user_flagstate_o2; - output fabric_otp_user_flagstate_o3; - output fabric_otp_user_flagstate_o4; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input fabric_otp_user_prgwidth_i1; - input fabric_otp_user_prgwidth_i2; - input fabric_otp_user_prgwidth_i3; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output fabric_otp_user_startword_o1; - output fabric_otp_user_startword_o10; - output fabric_otp_user_startword_o11; - output fabric_otp_user_startword_o12; - output fabric_otp_user_startword_o13; - output fabric_otp_user_startword_o14; - output fabric_otp_user_startword_o15; - output fabric_otp_user_startword_o16; - output fabric_otp_user_startword_o2; - output fabric_otp_user_startword_o3; - output fabric_otp_user_startword_o4; - output fabric_otp_user_startword_o5; - output fabric_otp_user_startword_o6; - output fabric_otp_user_startword_o7; - output fabric_otp_user_startword_o8; - output fabric_otp_user_startword_o9; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input fabric_otp_user_tst_scanin_i1; - input fabric_otp_user_tst_scanin_i2; - input fabric_otp_user_tst_scanin_i3; - input fabric_otp_user_tst_scanin_i4; - input fabric_otp_user_tst_scanin_i5; - output fabric_otp_user_tst_scanout_o1; - output fabric_otp_user_tst_scanout_o2; - output fabric_otp_user_tst_scanout_o3; - output fabric_otp_user_tst_scanout_o4; - output fabric_otp_user_tst_scanout_o5; - output fabric_otp_user_wlromout_o1; - output fabric_otp_user_wlromout_o10; - output fabric_otp_user_wlromout_o2; - output fabric_otp_user_wlromout_o3; - output fabric_otp_user_wlromout_o4; - output fabric_otp_user_wlromout_o5; - output fabric_otp_user_wlromout_o6; - output fabric_otp_user_wlromout_o7; - output fabric_otp_user_wlromout_o8; - output fabric_otp_user_wlromout_o9; - input fabric_otp_user_wordlock_i; - input fabric_parusr_clk_i; - input fabric_parusr_cs_i; - input fabric_parusr_data_i1; - input fabric_parusr_data_i10; - input fabric_parusr_data_i11; - input fabric_parusr_data_i12; - input fabric_parusr_data_i13; - input fabric_parusr_data_i14; - input fabric_parusr_data_i15; - input fabric_parusr_data_i16; - input fabric_parusr_data_i2; - input fabric_parusr_data_i3; - input fabric_parusr_data_i4; - input fabric_parusr_data_i5; - input fabric_parusr_data_i6; - input fabric_parusr_data_i7; - input fabric_parusr_data_i8; - input fabric_parusr_data_i9; - output fabric_parusr_data_o1; - output fabric_parusr_data_o10; - output fabric_parusr_data_o11; - output fabric_parusr_data_o12; - output fabric_parusr_data_o13; - output fabric_parusr_data_o14; - output fabric_parusr_data_o15; - output fabric_parusr_data_o16; - output fabric_parusr_data_o2; - output fabric_parusr_data_o3; - output fabric_parusr_data_o4; - output fabric_parusr_data_o5; - output fabric_parusr_data_o6; - output fabric_parusr_data_o7; - output fabric_parusr_data_o8; - output fabric_parusr_data_o9; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input fabric_parusr_type_i1; - input fabric_parusr_type_i2; - input fabric_spare_i1; - input fabric_spare_i10; - input fabric_spare_i100; - input fabric_spare_i101; - input fabric_spare_i102; - input fabric_spare_i103; - input fabric_spare_i104; - input fabric_spare_i105; - input fabric_spare_i106; - input fabric_spare_i107; - input fabric_spare_i108; - input fabric_spare_i109; - input fabric_spare_i11; - input fabric_spare_i110; - input fabric_spare_i111; - input fabric_spare_i112; - input fabric_spare_i113; - input fabric_spare_i114; - input fabric_spare_i115; - input fabric_spare_i116; - input fabric_spare_i117; - input fabric_spare_i118; - input fabric_spare_i119; - input fabric_spare_i12; - input fabric_spare_i120; - input fabric_spare_i121; - input fabric_spare_i122; - input fabric_spare_i123; - input fabric_spare_i124; - input fabric_spare_i125; - input fabric_spare_i126; - input fabric_spare_i127; - input fabric_spare_i128; - input fabric_spare_i13; - input fabric_spare_i14; - input fabric_spare_i15; - input fabric_spare_i16; - input fabric_spare_i17; - input fabric_spare_i18; - input fabric_spare_i19; - input fabric_spare_i2; - input fabric_spare_i20; - input fabric_spare_i21; - input fabric_spare_i22; - input fabric_spare_i23; - input fabric_spare_i24; - input fabric_spare_i25; - input fabric_spare_i26; - input fabric_spare_i27; - input fabric_spare_i28; - input fabric_spare_i29; - input fabric_spare_i3; - input fabric_spare_i30; - input fabric_spare_i31; - input fabric_spare_i32; - input fabric_spare_i33; - input fabric_spare_i34; - input fabric_spare_i35; - input fabric_spare_i36; - input fabric_spare_i37; - input fabric_spare_i38; - input fabric_spare_i39; - input fabric_spare_i4; - input fabric_spare_i40; - input fabric_spare_i41; - input fabric_spare_i42; - input fabric_spare_i43; - input fabric_spare_i44; - input fabric_spare_i45; - input fabric_spare_i46; - input fabric_spare_i47; - input fabric_spare_i48; - input fabric_spare_i49; - input fabric_spare_i5; - input fabric_spare_i50; - input fabric_spare_i51; - input fabric_spare_i52; - input fabric_spare_i53; - input fabric_spare_i54; - input fabric_spare_i55; - input fabric_spare_i56; - input fabric_spare_i57; - input fabric_spare_i58; - input fabric_spare_i59; - input fabric_spare_i6; - input fabric_spare_i60; - input fabric_spare_i61; - input fabric_spare_i62; - input fabric_spare_i63; - input fabric_spare_i64; - input fabric_spare_i65; - input fabric_spare_i66; - input fabric_spare_i67; - input fabric_spare_i68; - input fabric_spare_i69; - input fabric_spare_i7; - input fabric_spare_i70; - input fabric_spare_i71; - input fabric_spare_i72; - input fabric_spare_i73; - input fabric_spare_i74; - input fabric_spare_i75; - input fabric_spare_i76; - input fabric_spare_i77; - input fabric_spare_i78; - input fabric_spare_i79; - input fabric_spare_i8; - input fabric_spare_i80; - input fabric_spare_i81; - input fabric_spare_i82; - input fabric_spare_i83; - input fabric_spare_i84; - input fabric_spare_i85; - input fabric_spare_i86; - input fabric_spare_i87; - input fabric_spare_i88; - input fabric_spare_i89; - input fabric_spare_i9; - input fabric_spare_i90; - input fabric_spare_i91; - input fabric_spare_i92; - input fabric_spare_i93; - input fabric_spare_i94; - input fabric_spare_i95; - input fabric_spare_i96; - input fabric_spare_i97; - input fabric_spare_i98; - input fabric_spare_i99; - output fabric_spare_o1; - output fabric_spare_o10; - output fabric_spare_o100; - output fabric_spare_o101; - output fabric_spare_o102; - output fabric_spare_o103; - output fabric_spare_o104; - output fabric_spare_o105; - output fabric_spare_o106; - output fabric_spare_o107; - output fabric_spare_o108; - output fabric_spare_o109; - output fabric_spare_o11; - output fabric_spare_o110; - output fabric_spare_o111; - output fabric_spare_o112; - output fabric_spare_o113; - output fabric_spare_o114; - output fabric_spare_o115; - output fabric_spare_o116; - output fabric_spare_o117; - output fabric_spare_o118; - output fabric_spare_o119; - output fabric_spare_o12; - output fabric_spare_o120; - output fabric_spare_o121; - output fabric_spare_o122; - output fabric_spare_o123; - output fabric_spare_o124; - output fabric_spare_o125; - output fabric_spare_o126; - output fabric_spare_o127; - output fabric_spare_o128; - output fabric_spare_o13; - output fabric_spare_o14; - output fabric_spare_o15; - output fabric_spare_o16; - output fabric_spare_o17; - output fabric_spare_o18; - output fabric_spare_o19; - output fabric_spare_o2; - output fabric_spare_o20; - output fabric_spare_o21; - output fabric_spare_o22; - output fabric_spare_o23; - output fabric_spare_o24; - output fabric_spare_o25; - output fabric_spare_o26; - output fabric_spare_o27; - output fabric_spare_o28; - output fabric_spare_o29; - output fabric_spare_o3; - output fabric_spare_o30; - output fabric_spare_o31; - output fabric_spare_o32; - output fabric_spare_o33; - output fabric_spare_o34; - output fabric_spare_o35; - output fabric_spare_o36; - output fabric_spare_o37; - output fabric_spare_o38; - output fabric_spare_o39; - output fabric_spare_o4; - output fabric_spare_o40; - output fabric_spare_o41; - output fabric_spare_o42; - output fabric_spare_o43; - output fabric_spare_o44; - output fabric_spare_o45; - output fabric_spare_o46; - output fabric_spare_o47; - output fabric_spare_o48; - output fabric_spare_o49; - output fabric_spare_o5; - output fabric_spare_o50; - output fabric_spare_o51; - output fabric_spare_o52; - output fabric_spare_o53; - output fabric_spare_o54; - output fabric_spare_o55; - output fabric_spare_o56; - output fabric_spare_o57; - output fabric_spare_o58; - output fabric_spare_o59; - output fabric_spare_o6; - output fabric_spare_o60; - output fabric_spare_o61; - output fabric_spare_o62; - output fabric_spare_o63; - output fabric_spare_o64; - output fabric_spare_o65; - output fabric_spare_o66; - output fabric_spare_o67; - output fabric_spare_o68; - output fabric_spare_o69; - output fabric_spare_o7; - output fabric_spare_o70; - output fabric_spare_o71; - output fabric_spare_o72; - output fabric_spare_o73; - output fabric_spare_o74; - output fabric_spare_o75; - output fabric_spare_o76; - output fabric_spare_o77; - output fabric_spare_o78; - output fabric_spare_o79; - output fabric_spare_o8; - output fabric_spare_o80; - output fabric_spare_o81; - output fabric_spare_o82; - output fabric_spare_o83; - output fabric_spare_o84; - output fabric_spare_o85; - output fabric_spare_o86; - output fabric_spare_o87; - output fabric_spare_o88; - output fabric_spare_o89; - output fabric_spare_o9; - output fabric_spare_o90; - output fabric_spare_o91; - output fabric_spare_o92; - output fabric_spare_o93; - output fabric_spare_o94; - output fabric_spare_o95; - output fabric_spare_o96; - output fabric_spare_o97; - output fabric_spare_o98; - output fabric_spare_o99; - input fabric_spi_arst_tmr_n_i1; - input fabric_spi_arst_tmr_n_i2; - input fabric_spi_arst_tmr_n_i3; - input fabric_spi_arst_tmr_n_i4; - input fabric_spi_arst_tmr_n_i5; - input fabric_spi_arst_tmr_n_i6; - input fabric_spi_arst_tmr_n_i7; - input fabric_spi_arst_tmr_n_i8; - input fabric_spi_arst_tmr_n_i9; - output fabric_spi_bsm_release_o1; - output fabric_spi_bsm_release_o2; - output fabric_spi_bsm_release_o3; - output fabric_spi_busy_o1; - output fabric_spi_busy_o2; - output fabric_spi_busy_o3; - input fabric_spi_clk_i0; - input fabric_spi_clk_i1; - input fabric_spi_clk_i2; - input fabric_spi_cmd_bytes_i1; - input fabric_spi_cmd_bytes_i2; - input fabric_spi_cmd_bytes_i3; - input fabric_spi_cmd_bytes_i4; - input fabric_spi_cmd_bytes_i5; - input fabric_spi_cmd_bytes_i6; - output fabric_spi_cmd_full_o1; - output fabric_spi_cmd_full_o2; - output fabric_spi_cmd_full_o3; - input fabric_spi_cmd_mode_i1; - input fabric_spi_cmd_mode_i2; - input fabric_spi_cmd_mode_i3; - input fabric_spi_cmd_mode_i4; - input fabric_spi_cmd_mode_i5; - input fabric_spi_cmd_mode_i6; - input fabric_spi_cmd_push_i1; - input fabric_spi_cmd_push_i2; - input fabric_spi_cmd_push_i3; - input fabric_spi_cmd_type_i1; - input fabric_spi_cmd_type_i2; - input fabric_spi_cmd_type_i3; - input fabric_spi_cmd_type_i4; - input fabric_spi_cmd_type_i5; - input fabric_spi_cmd_type_i6; - input fabric_spi_cpha_i1; - input fabric_spi_cpha_i2; - input fabric_spi_cpha_i3; - input fabric_spi_cpol_i1; - input fabric_spi_cpol_i2; - input fabric_spi_cpol_i3; - input fabric_spi_cs_holdtime_i1; - input fabric_spi_cs_holdtime_i10; - input fabric_spi_cs_holdtime_i11; - input fabric_spi_cs_holdtime_i12; - input fabric_spi_cs_holdtime_i2; - input fabric_spi_cs_holdtime_i3; - input fabric_spi_cs_holdtime_i4; - input fabric_spi_cs_holdtime_i5; - input fabric_spi_cs_holdtime_i6; - input fabric_spi_cs_holdtime_i7; - input fabric_spi_cs_holdtime_i8; - input fabric_spi_cs_holdtime_i9; - input fabric_spi_cs_offtime_i1; - input fabric_spi_cs_offtime_i10; - input fabric_spi_cs_offtime_i11; - input fabric_spi_cs_offtime_i12; - input fabric_spi_cs_offtime_i2; - input fabric_spi_cs_offtime_i3; - input fabric_spi_cs_offtime_i4; - input fabric_spi_cs_offtime_i5; - input fabric_spi_cs_offtime_i6; - input fabric_spi_cs_offtime_i7; - input fabric_spi_cs_offtime_i8; - input fabric_spi_cs_offtime_i9; - input fabric_spi_cs_setuptime_i1; - input fabric_spi_cs_setuptime_i10; - input fabric_spi_cs_setuptime_i11; - input fabric_spi_cs_setuptime_i12; - input fabric_spi_cs_setuptime_i2; - input fabric_spi_cs_setuptime_i3; - input fabric_spi_cs_setuptime_i4; - input fabric_spi_cs_setuptime_i5; - input fabric_spi_cs_setuptime_i6; - input fabric_spi_cs_setuptime_i7; - input fabric_spi_cs_setuptime_i8; - input fabric_spi_cs_setuptime_i9; - input fabric_spi_data_in_unlimited_i1; - input fabric_spi_data_in_unlimited_i2; - input fabric_spi_data_in_unlimited_i3; - input fabric_spi_enable_i1; - input fabric_spi_enable_i2; - input fabric_spi_enable_i3; - output fabric_spi_error_endianness_o1; - output fabric_spi_error_endianness_o2; - output fabric_spi_error_endianness_o3; - output fabric_spi_error_loopback_o1; - output fabric_spi_error_loopback_o2; - output fabric_spi_error_loopback_o3; - output fabric_spi_error_mode_o1; - output fabric_spi_error_mode_o2; - output fabric_spi_error_mode_o3; - output fabric_spi_error_sel_o1; - output fabric_spi_error_sel_o2; - output fabric_spi_error_sel_o3; - input fabric_spi_fifo_arst_tmr_n_i1; - input fabric_spi_fifo_arst_tmr_n_i2; - input fabric_spi_fifo_arst_tmr_n_i3; - input fabric_spi_fifo_arst_tmr_n_i4; - input fabric_spi_fifo_arst_tmr_n_i5; - input fabric_spi_fifo_arst_tmr_n_i6; - input fabric_spi_fifo_arst_tmr_n_i7; - input fabric_spi_fifo_arst_tmr_n_i8; - input fabric_spi_fifo_arst_tmr_n_i9; - output fabric_spi_init_done_o1; - output fabric_spi_init_done_o2; - output fabric_spi_init_done_o3; - input fabric_spi_legacy_enable_i1; - input fabric_spi_legacy_enable_i2; - input fabric_spi_legacy_enable_i3; - input fabric_spi_legacy_master_i1; - input fabric_spi_legacy_master_i2; - input fabric_spi_legacy_master_i3; - input fabric_spi_loopback_i1; - input fabric_spi_loopback_i2; - input fabric_spi_loopback_i3; - input fabric_spi_lsb_first_i1; - input fabric_spi_lsb_first_i2; - input fabric_spi_lsb_first_i3; - output fabric_spi_miso_data_inv_o1; - output fabric_spi_miso_data_inv_o2; - output fabric_spi_miso_data_inv_o3; - output fabric_spi_miso_data_o1; - output fabric_spi_miso_data_o10; - output fabric_spi_miso_data_o11; - output fabric_spi_miso_data_o12; - output fabric_spi_miso_data_o13; - output fabric_spi_miso_data_o14; - output fabric_spi_miso_data_o15; - output fabric_spi_miso_data_o16; - output fabric_spi_miso_data_o17; - output fabric_spi_miso_data_o18; - output fabric_spi_miso_data_o19; - output fabric_spi_miso_data_o2; - output fabric_spi_miso_data_o20; - output fabric_spi_miso_data_o21; - output fabric_spi_miso_data_o22; - output fabric_spi_miso_data_o23; - output fabric_spi_miso_data_o24; - output fabric_spi_miso_data_o3; - output fabric_spi_miso_data_o4; - output fabric_spi_miso_data_o5; - output fabric_spi_miso_data_o6; - output fabric_spi_miso_data_o7; - output fabric_spi_miso_data_o8; - output fabric_spi_miso_data_o9; - output fabric_spi_miso_empty_o1; - output fabric_spi_miso_empty_o2; - output fabric_spi_miso_empty_o3; - input fabric_spi_miso_pop_i1; - input fabric_spi_miso_pop_i2; - input fabric_spi_miso_pop_i3; - input fabric_spi_mosi_data_i1; - input fabric_spi_mosi_data_i10; - input fabric_spi_mosi_data_i11; - input fabric_spi_mosi_data_i12; - input fabric_spi_mosi_data_i13; - input fabric_spi_mosi_data_i14; - input fabric_spi_mosi_data_i15; - input fabric_spi_mosi_data_i16; - input fabric_spi_mosi_data_i17; - input fabric_spi_mosi_data_i18; - input fabric_spi_mosi_data_i19; - input fabric_spi_mosi_data_i2; - input fabric_spi_mosi_data_i20; - input fabric_spi_mosi_data_i21; - input fabric_spi_mosi_data_i22; - input fabric_spi_mosi_data_i23; - input fabric_spi_mosi_data_i24; - input fabric_spi_mosi_data_i3; - input fabric_spi_mosi_data_i4; - input fabric_spi_mosi_data_i5; - input fabric_spi_mosi_data_i6; - input fabric_spi_mosi_data_i7; - input fabric_spi_mosi_data_i8; - input fabric_spi_mosi_data_i9; - input fabric_spi_mosi_data_inv_i1; - input fabric_spi_mosi_data_inv_i2; - input fabric_spi_mosi_data_inv_i3; - output fabric_spi_mosi_full_o1; - output fabric_spi_mosi_full_o2; - output fabric_spi_mosi_full_o3; - input fabric_spi_mosi_push_i1; - input fabric_spi_mosi_push_i2; - input fabric_spi_mosi_push_i3; - input fabric_spi_needed_i1; - input fabric_spi_needed_i2; - input fabric_spi_needed_i3; - input fabric_spi_powerdown_cycle_i1; - input fabric_spi_powerdown_cycle_i10; - input fabric_spi_powerdown_cycle_i11; - input fabric_spi_powerdown_cycle_i12; - input fabric_spi_powerdown_cycle_i13; - input fabric_spi_powerdown_cycle_i14; - input fabric_spi_powerdown_cycle_i15; - input fabric_spi_powerdown_cycle_i16; - input fabric_spi_powerdown_cycle_i17; - input fabric_spi_powerdown_cycle_i18; - input fabric_spi_powerdown_cycle_i19; - input fabric_spi_powerdown_cycle_i2; - input fabric_spi_powerdown_cycle_i20; - input fabric_spi_powerdown_cycle_i21; - input fabric_spi_powerdown_cycle_i22; - input fabric_spi_powerdown_cycle_i23; - input fabric_spi_powerdown_cycle_i24; - input fabric_spi_powerdown_cycle_i25; - input fabric_spi_powerdown_cycle_i26; - input fabric_spi_powerdown_cycle_i27; - input fabric_spi_powerdown_cycle_i28; - input fabric_spi_powerdown_cycle_i29; - input fabric_spi_powerdown_cycle_i3; - input fabric_spi_powerdown_cycle_i30; - input fabric_spi_powerdown_cycle_i31; - input fabric_spi_powerdown_cycle_i32; - input fabric_spi_powerdown_cycle_i33; - input fabric_spi_powerdown_cycle_i34; - input fabric_spi_powerdown_cycle_i35; - input fabric_spi_powerdown_cycle_i36; - input fabric_spi_powerdown_cycle_i37; - input fabric_spi_powerdown_cycle_i38; - input fabric_spi_powerdown_cycle_i39; - input fabric_spi_powerdown_cycle_i4; - input fabric_spi_powerdown_cycle_i40; - input fabric_spi_powerdown_cycle_i41; - input fabric_spi_powerdown_cycle_i42; - input fabric_spi_powerdown_cycle_i43; - input fabric_spi_powerdown_cycle_i44; - input fabric_spi_powerdown_cycle_i45; - input fabric_spi_powerdown_cycle_i46; - input fabric_spi_powerdown_cycle_i47; - input fabric_spi_powerdown_cycle_i48; - input fabric_spi_powerdown_cycle_i5; - input fabric_spi_powerdown_cycle_i6; - input fabric_spi_powerdown_cycle_i7; - input fabric_spi_powerdown_cycle_i8; - input fabric_spi_powerdown_cycle_i9; - input fabric_spi_powerup_cycle_i1; - input fabric_spi_powerup_cycle_i10; - input fabric_spi_powerup_cycle_i11; - input fabric_spi_powerup_cycle_i12; - input fabric_spi_powerup_cycle_i13; - input fabric_spi_powerup_cycle_i14; - input fabric_spi_powerup_cycle_i15; - input fabric_spi_powerup_cycle_i16; - input fabric_spi_powerup_cycle_i17; - input fabric_spi_powerup_cycle_i18; - input fabric_spi_powerup_cycle_i19; - input fabric_spi_powerup_cycle_i2; - input fabric_spi_powerup_cycle_i20; - input fabric_spi_powerup_cycle_i21; - input fabric_spi_powerup_cycle_i22; - input fabric_spi_powerup_cycle_i23; - input fabric_spi_powerup_cycle_i24; - input fabric_spi_powerup_cycle_i25; - input fabric_spi_powerup_cycle_i26; - input fabric_spi_powerup_cycle_i27; - input fabric_spi_powerup_cycle_i28; - input fabric_spi_powerup_cycle_i29; - input fabric_spi_powerup_cycle_i3; - input fabric_spi_powerup_cycle_i30; - input fabric_spi_powerup_cycle_i31; - input fabric_spi_powerup_cycle_i32; - input fabric_spi_powerup_cycle_i33; - input fabric_spi_powerup_cycle_i34; - input fabric_spi_powerup_cycle_i35; - input fabric_spi_powerup_cycle_i36; - input fabric_spi_powerup_cycle_i37; - input fabric_spi_powerup_cycle_i38; - input fabric_spi_powerup_cycle_i39; - input fabric_spi_powerup_cycle_i4; - input fabric_spi_powerup_cycle_i40; - input fabric_spi_powerup_cycle_i41; - input fabric_spi_powerup_cycle_i42; - input fabric_spi_powerup_cycle_i43; - input fabric_spi_powerup_cycle_i44; - input fabric_spi_powerup_cycle_i45; - input fabric_spi_powerup_cycle_i46; - input fabric_spi_powerup_cycle_i47; - input fabric_spi_powerup_cycle_i48; - input fabric_spi_powerup_cycle_i5; - input fabric_spi_powerup_cycle_i6; - input fabric_spi_powerup_cycle_i7; - input fabric_spi_powerup_cycle_i8; - input fabric_spi_powerup_cycle_i9; - input fabric_spi_rst_n_i1; - input fabric_spi_rst_n_i2; - input fabric_spi_rst_n_i3; - input fabric_spi_sck_i0; - input fabric_spi_sck_i1; - input fabric_spi_sck_i2; - input fabric_spi_vcc_enable_i1; - input fabric_spi_vcc_enable_i2; - input fabric_spi_vcc_enable_i3; - output fabric_spi_vcc_used_o1; - output fabric_spi_vcc_used_o2; - output fabric_spi_vcc_used_o3; - input fabric_spw0_apb_slv_paddr_i1; - input fabric_spw0_apb_slv_paddr_i2; - input fabric_spw0_apb_slv_paddr_i3; - input fabric_spw0_apb_slv_paddr_i4; - input fabric_spw0_apb_slv_paddr_i5; - input fabric_spw0_apb_slv_penable_i; - output fabric_spw0_apb_slv_prdata_o1; - output fabric_spw0_apb_slv_prdata_o10; - output fabric_spw0_apb_slv_prdata_o11; - output fabric_spw0_apb_slv_prdata_o12; - output fabric_spw0_apb_slv_prdata_o13; - output fabric_spw0_apb_slv_prdata_o14; - output fabric_spw0_apb_slv_prdata_o15; - output fabric_spw0_apb_slv_prdata_o16; - output fabric_spw0_apb_slv_prdata_o17; - output fabric_spw0_apb_slv_prdata_o18; - output fabric_spw0_apb_slv_prdata_o19; - output fabric_spw0_apb_slv_prdata_o2; - output fabric_spw0_apb_slv_prdata_o20; - output fabric_spw0_apb_slv_prdata_o21; - output fabric_spw0_apb_slv_prdata_o22; - output fabric_spw0_apb_slv_prdata_o23; - output fabric_spw0_apb_slv_prdata_o24; - output fabric_spw0_apb_slv_prdata_o25; - output fabric_spw0_apb_slv_prdata_o26; - output fabric_spw0_apb_slv_prdata_o27; - output fabric_spw0_apb_slv_prdata_o28; - output fabric_spw0_apb_slv_prdata_o29; - output fabric_spw0_apb_slv_prdata_o3; - output fabric_spw0_apb_slv_prdata_o30; - output fabric_spw0_apb_slv_prdata_o31; - output fabric_spw0_apb_slv_prdata_o4; - output fabric_spw0_apb_slv_prdata_o5; - output fabric_spw0_apb_slv_prdata_o6; - output fabric_spw0_apb_slv_prdata_o7; - output fabric_spw0_apb_slv_prdata_o8; - output fabric_spw0_apb_slv_prdata_o9; - output fabric_spw0_apb_slv_pready_o; - input fabric_spw0_apb_slv_psel_i; - output fabric_spw0_apb_slv_pslverr_o; - input fabric_spw0_apb_slv_pwdata_i1; - input fabric_spw0_apb_slv_pwdata_i10; - input fabric_spw0_apb_slv_pwdata_i11; - input fabric_spw0_apb_slv_pwdata_i12; - input fabric_spw0_apb_slv_pwdata_i13; - input fabric_spw0_apb_slv_pwdata_i14; - input fabric_spw0_apb_slv_pwdata_i15; - input fabric_spw0_apb_slv_pwdata_i16; - input fabric_spw0_apb_slv_pwdata_i17; - input fabric_spw0_apb_slv_pwdata_i18; - input fabric_spw0_apb_slv_pwdata_i19; - input fabric_spw0_apb_slv_pwdata_i2; - input fabric_spw0_apb_slv_pwdata_i20; - input fabric_spw0_apb_slv_pwdata_i21; - input fabric_spw0_apb_slv_pwdata_i22; - input fabric_spw0_apb_slv_pwdata_i23; - input fabric_spw0_apb_slv_pwdata_i24; - input fabric_spw0_apb_slv_pwdata_i25; - input fabric_spw0_apb_slv_pwdata_i26; - input fabric_spw0_apb_slv_pwdata_i27; - input fabric_spw0_apb_slv_pwdata_i28; - input fabric_spw0_apb_slv_pwdata_i29; - input fabric_spw0_apb_slv_pwdata_i3; - input fabric_spw0_apb_slv_pwdata_i30; - input fabric_spw0_apb_slv_pwdata_i31; - input fabric_spw0_apb_slv_pwdata_i4; - input fabric_spw0_apb_slv_pwdata_i5; - input fabric_spw0_apb_slv_pwdata_i6; - input fabric_spw0_apb_slv_pwdata_i7; - input fabric_spw0_apb_slv_pwdata_i8; - input fabric_spw0_apb_slv_pwdata_i9; - input fabric_spw0_apb_slv_pwrite_i; - input fabric_spw0_clk_i; - input fabric_spw0_clk_tx_i; - input fabric_spw0_rst_n_i; - output fabric_spw0_rx_fifo_data_o1; - output fabric_spw0_rx_fifo_data_o2; - output fabric_spw0_rx_fifo_data_o3; - output fabric_spw0_rx_fifo_data_o4; - output fabric_spw0_rx_fifo_data_o5; - output fabric_spw0_rx_fifo_data_o6; - output fabric_spw0_rx_fifo_data_o7; - output fabric_spw0_rx_fifo_data_o8; - output fabric_spw0_rx_fifo_data_o9; - output fabric_spw0_rx_fifo_empty_o; - input fabric_spw0_rx_fifo_read_i; - input fabric_spw0_tick_ctm_i; - output fabric_spw0_tick_ctm_o; - input fabric_spw0_tx_fifo_data_i1; - input fabric_spw0_tx_fifo_data_i2; - input fabric_spw0_tx_fifo_data_i3; - input fabric_spw0_tx_fifo_data_i4; - input fabric_spw0_tx_fifo_data_i5; - input fabric_spw0_tx_fifo_data_i6; - input fabric_spw0_tx_fifo_data_i7; - input fabric_spw0_tx_fifo_data_i8; - input fabric_spw0_tx_fifo_data_i9; - output fabric_spw0_tx_fifo_full_o; - input fabric_spw0_tx_fifo_write_i; - output fabric_spw0_user_shared_o; - input fabric_spw1_apb_slv_paddr_i1; - input fabric_spw1_apb_slv_paddr_i2; - input fabric_spw1_apb_slv_paddr_i3; - input fabric_spw1_apb_slv_paddr_i4; - input fabric_spw1_apb_slv_paddr_i5; - input fabric_spw1_apb_slv_penable_i; - output fabric_spw1_apb_slv_prdata_o1; - output fabric_spw1_apb_slv_prdata_o10; - output fabric_spw1_apb_slv_prdata_o11; - output fabric_spw1_apb_slv_prdata_o12; - output fabric_spw1_apb_slv_prdata_o13; - output fabric_spw1_apb_slv_prdata_o14; - output fabric_spw1_apb_slv_prdata_o15; - output fabric_spw1_apb_slv_prdata_o16; - output fabric_spw1_apb_slv_prdata_o17; - output fabric_spw1_apb_slv_prdata_o18; - output fabric_spw1_apb_slv_prdata_o19; - output fabric_spw1_apb_slv_prdata_o2; - output fabric_spw1_apb_slv_prdata_o20; - output fabric_spw1_apb_slv_prdata_o21; - output fabric_spw1_apb_slv_prdata_o22; - output fabric_spw1_apb_slv_prdata_o23; - output fabric_spw1_apb_slv_prdata_o24; - output fabric_spw1_apb_slv_prdata_o25; - output fabric_spw1_apb_slv_prdata_o26; - output fabric_spw1_apb_slv_prdata_o27; - output fabric_spw1_apb_slv_prdata_o28; - output fabric_spw1_apb_slv_prdata_o29; - output fabric_spw1_apb_slv_prdata_o3; - output fabric_spw1_apb_slv_prdata_o30; - output fabric_spw1_apb_slv_prdata_o31; - output fabric_spw1_apb_slv_prdata_o4; - output fabric_spw1_apb_slv_prdata_o5; - output fabric_spw1_apb_slv_prdata_o6; - output fabric_spw1_apb_slv_prdata_o7; - output fabric_spw1_apb_slv_prdata_o8; - output fabric_spw1_apb_slv_prdata_o9; - output fabric_spw1_apb_slv_pready_o; - input fabric_spw1_apb_slv_psel_i; - output fabric_spw1_apb_slv_pslverr_o; - input fabric_spw1_apb_slv_pwdata_i1; - input fabric_spw1_apb_slv_pwdata_i10; - input fabric_spw1_apb_slv_pwdata_i11; - input fabric_spw1_apb_slv_pwdata_i12; - input fabric_spw1_apb_slv_pwdata_i13; - input fabric_spw1_apb_slv_pwdata_i14; - input fabric_spw1_apb_slv_pwdata_i15; - input fabric_spw1_apb_slv_pwdata_i16; - input fabric_spw1_apb_slv_pwdata_i17; - input fabric_spw1_apb_slv_pwdata_i18; - input fabric_spw1_apb_slv_pwdata_i19; - input fabric_spw1_apb_slv_pwdata_i2; - input fabric_spw1_apb_slv_pwdata_i20; - input fabric_spw1_apb_slv_pwdata_i21; - input fabric_spw1_apb_slv_pwdata_i22; - input fabric_spw1_apb_slv_pwdata_i23; - input fabric_spw1_apb_slv_pwdata_i24; - input fabric_spw1_apb_slv_pwdata_i25; - input fabric_spw1_apb_slv_pwdata_i26; - input fabric_spw1_apb_slv_pwdata_i27; - input fabric_spw1_apb_slv_pwdata_i28; - input fabric_spw1_apb_slv_pwdata_i29; - input fabric_spw1_apb_slv_pwdata_i3; - input fabric_spw1_apb_slv_pwdata_i30; - input fabric_spw1_apb_slv_pwdata_i31; - input fabric_spw1_apb_slv_pwdata_i4; - input fabric_spw1_apb_slv_pwdata_i5; - input fabric_spw1_apb_slv_pwdata_i6; - input fabric_spw1_apb_slv_pwdata_i7; - input fabric_spw1_apb_slv_pwdata_i8; - input fabric_spw1_apb_slv_pwdata_i9; - input fabric_spw1_apb_slv_pwrite_i; - input fabric_spw1_clk_i; - input fabric_spw1_clk_tx_i; - input fabric_spw1_rst_n_i; - output fabric_spw1_rx_fifo_data_o1; - output fabric_spw1_rx_fifo_data_o2; - output fabric_spw1_rx_fifo_data_o3; - output fabric_spw1_rx_fifo_data_o4; - output fabric_spw1_rx_fifo_data_o5; - output fabric_spw1_rx_fifo_data_o6; - output fabric_spw1_rx_fifo_data_o7; - output fabric_spw1_rx_fifo_data_o8; - output fabric_spw1_rx_fifo_data_o9; - output fabric_spw1_rx_fifo_empty_o; - input fabric_spw1_rx_fifo_read_i; - input fabric_spw1_tick_ctm_i; - output fabric_spw1_tick_ctm_o; - input fabric_spw1_tx_fifo_data_i1; - input fabric_spw1_tx_fifo_data_i2; - input fabric_spw1_tx_fifo_data_i3; - input fabric_spw1_tx_fifo_data_i4; - input fabric_spw1_tx_fifo_data_i5; - input fabric_spw1_tx_fifo_data_i6; - input fabric_spw1_tx_fifo_data_i7; - input fabric_spw1_tx_fifo_data_i8; - input fabric_spw1_tx_fifo_data_i9; - output fabric_spw1_tx_fifo_full_o; - input fabric_spw1_tx_fifo_write_i; - output fabric_spw1_user_shared_o; - output fabric_status_cold_start_o; - input fabric_thsens_arst_tmr_n_i1; - input fabric_thsens_arst_tmr_n_i2; - input fabric_thsens_arst_tmr_n_i3; - input fabric_thsens_clk_div_ratio_i1; - input fabric_thsens_clk_div_ratio_i2; - input fabric_thsens_clk_div_ratio_i3; - input fabric_thsens_clk_div_ratio_i4; - input fabric_thsens_clk_div_ratio_i5; - input fabric_thsens_clk_div_ratio_i6; - input fabric_thsens_clk_div_ratio_i7; - input fabric_thsens_clk_div_ratio_i8; - input fabric_thsens_clk_i; - output fabric_thsens_fm_config_r_o1; - output fabric_thsens_fm_config_r_o10; - output fabric_thsens_fm_config_r_o11; - output fabric_thsens_fm_config_r_o12; - output fabric_thsens_fm_config_r_o13; - output fabric_thsens_fm_config_r_o14; - output fabric_thsens_fm_config_r_o15; - output fabric_thsens_fm_config_r_o16; - output fabric_thsens_fm_config_r_o17; - output fabric_thsens_fm_config_r_o18; - output fabric_thsens_fm_config_r_o19; - output fabric_thsens_fm_config_r_o2; - output fabric_thsens_fm_config_r_o20; - output fabric_thsens_fm_config_r_o21; - output fabric_thsens_fm_config_r_o22; - output fabric_thsens_fm_config_r_o23; - output fabric_thsens_fm_config_r_o24; - output fabric_thsens_fm_config_r_o25; - output fabric_thsens_fm_config_r_o26; - output fabric_thsens_fm_config_r_o27; - output fabric_thsens_fm_config_r_o3; - output fabric_thsens_fm_config_r_o4; - output fabric_thsens_fm_config_r_o5; - output fabric_thsens_fm_config_r_o6; - output fabric_thsens_fm_config_r_o7; - output fabric_thsens_fm_config_r_o8; - output fabric_thsens_fm_config_r_o9; - input fabric_thsens_fm_config_w_i1; - input fabric_thsens_fm_config_w_i10; - input fabric_thsens_fm_config_w_i11; - input fabric_thsens_fm_config_w_i12; - input fabric_thsens_fm_config_w_i13; - input fabric_thsens_fm_config_w_i14; - input fabric_thsens_fm_config_w_i15; - input fabric_thsens_fm_config_w_i16; - input fabric_thsens_fm_config_w_i17; - input fabric_thsens_fm_config_w_i18; - input fabric_thsens_fm_config_w_i19; - input fabric_thsens_fm_config_w_i2; - input fabric_thsens_fm_config_w_i20; - input fabric_thsens_fm_config_w_i21; - input fabric_thsens_fm_config_w_i22; - input fabric_thsens_fm_config_w_i23; - input fabric_thsens_fm_config_w_i24; - input fabric_thsens_fm_config_w_i25; - input fabric_thsens_fm_config_w_i26; - input fabric_thsens_fm_config_w_i27; - input fabric_thsens_fm_config_w_i3; - input fabric_thsens_fm_config_w_i4; - input fabric_thsens_fm_config_w_i5; - input fabric_thsens_fm_config_w_i6; - input fabric_thsens_fm_config_w_i7; - input fabric_thsens_fm_config_w_i8; - input fabric_thsens_fm_config_w_i9; - input fabric_thsens_fm_config_wen_i; - output fabric_thsens_fm_data_o1; - output fabric_thsens_fm_data_o10; - output fabric_thsens_fm_data_o11; - output fabric_thsens_fm_data_o12; - output fabric_thsens_fm_data_o13; - output fabric_thsens_fm_data_o14; - output fabric_thsens_fm_data_o2; - output fabric_thsens_fm_data_o3; - output fabric_thsens_fm_data_o4; - output fabric_thsens_fm_data_o5; - output fabric_thsens_fm_data_o6; - output fabric_thsens_fm_data_o7; - output fabric_thsens_fm_data_o8; - output fabric_thsens_fm_data_o9; - input fabric_thsens_fm_enable_i; - output fabric_thsens_fm_mode_r_o1; - output fabric_thsens_fm_mode_r_o10; - output fabric_thsens_fm_mode_r_o11; - output fabric_thsens_fm_mode_r_o12; - output fabric_thsens_fm_mode_r_o13; - output fabric_thsens_fm_mode_r_o14; - output fabric_thsens_fm_mode_r_o15; - output fabric_thsens_fm_mode_r_o16; - output fabric_thsens_fm_mode_r_o17; - output fabric_thsens_fm_mode_r_o18; - output fabric_thsens_fm_mode_r_o19; - output fabric_thsens_fm_mode_r_o2; - output fabric_thsens_fm_mode_r_o20; - output fabric_thsens_fm_mode_r_o21; - output fabric_thsens_fm_mode_r_o22; - output fabric_thsens_fm_mode_r_o23; - output fabric_thsens_fm_mode_r_o24; - output fabric_thsens_fm_mode_r_o25; - output fabric_thsens_fm_mode_r_o26; - output fabric_thsens_fm_mode_r_o27; - output fabric_thsens_fm_mode_r_o28; - output fabric_thsens_fm_mode_r_o29; - output fabric_thsens_fm_mode_r_o3; - output fabric_thsens_fm_mode_r_o30; - output fabric_thsens_fm_mode_r_o31; - output fabric_thsens_fm_mode_r_o32; - output fabric_thsens_fm_mode_r_o4; - output fabric_thsens_fm_mode_r_o5; - output fabric_thsens_fm_mode_r_o6; - output fabric_thsens_fm_mode_r_o7; - output fabric_thsens_fm_mode_r_o8; - output fabric_thsens_fm_mode_r_o9; - input fabric_thsens_fm_mode_w_i1; - input fabric_thsens_fm_mode_w_i10; - input fabric_thsens_fm_mode_w_i11; - input fabric_thsens_fm_mode_w_i12; - input fabric_thsens_fm_mode_w_i13; - input fabric_thsens_fm_mode_w_i14; - input fabric_thsens_fm_mode_w_i15; - input fabric_thsens_fm_mode_w_i16; - input fabric_thsens_fm_mode_w_i17; - input fabric_thsens_fm_mode_w_i18; - input fabric_thsens_fm_mode_w_i19; - input fabric_thsens_fm_mode_w_i2; - input fabric_thsens_fm_mode_w_i20; - input fabric_thsens_fm_mode_w_i21; - input fabric_thsens_fm_mode_w_i22; - input fabric_thsens_fm_mode_w_i23; - input fabric_thsens_fm_mode_w_i24; - input fabric_thsens_fm_mode_w_i25; - input fabric_thsens_fm_mode_w_i26; - input fabric_thsens_fm_mode_w_i27; - input fabric_thsens_fm_mode_w_i28; - input fabric_thsens_fm_mode_w_i29; - input fabric_thsens_fm_mode_w_i3; - input fabric_thsens_fm_mode_w_i30; - input fabric_thsens_fm_mode_w_i31; - input fabric_thsens_fm_mode_w_i32; - input fabric_thsens_fm_mode_w_i4; - input fabric_thsens_fm_mode_w_i5; - input fabric_thsens_fm_mode_w_i6; - input fabric_thsens_fm_mode_w_i7; - input fabric_thsens_fm_mode_w_i8; - input fabric_thsens_fm_mode_w_i9; - input fabric_thsens_fm_mode_wen_i; - output fabric_thsens_fm_overflow_o; - output fabric_thsens_fm_valid_o; - output fabric_thsens_otp_config_o1; - output fabric_thsens_otp_config_o10; - output fabric_thsens_otp_config_o11; - output fabric_thsens_otp_config_o12; - output fabric_thsens_otp_config_o13; - output fabric_thsens_otp_config_o14; - output fabric_thsens_otp_config_o15; - output fabric_thsens_otp_config_o16; - output fabric_thsens_otp_config_o17; - output fabric_thsens_otp_config_o18; - output fabric_thsens_otp_config_o19; - output fabric_thsens_otp_config_o2; - output fabric_thsens_otp_config_o20; - output fabric_thsens_otp_config_o21; - output fabric_thsens_otp_config_o22; - output fabric_thsens_otp_config_o23; - output fabric_thsens_otp_config_o24; - output fabric_thsens_otp_config_o25; - output fabric_thsens_otp_config_o26; - output fabric_thsens_otp_config_o27; - output fabric_thsens_otp_config_o3; - output fabric_thsens_otp_config_o4; - output fabric_thsens_otp_config_o5; - output fabric_thsens_otp_config_o6; - output fabric_thsens_otp_config_o7; - output fabric_thsens_otp_config_o8; - output fabric_thsens_otp_config_o9; - input fabric_thsens_tst_scanenable_i; - input fabric_thsens_tst_scanin1_i; - input fabric_thsens_tst_scanin2_i; - output fabric_thsens_tst_scanout1_o; - output fabric_thsens_tst_scanout2_o; - input fabric_user_clk_i; - input fabric_user_data_i1; - input fabric_user_data_i10; - input fabric_user_data_i11; - input fabric_user_data_i12; - input fabric_user_data_i13; - input fabric_user_data_i14; - input fabric_user_data_i15; - input fabric_user_data_i16; - input fabric_user_data_i17; - input fabric_user_data_i18; - input fabric_user_data_i19; - input fabric_user_data_i2; - input fabric_user_data_i20; - input fabric_user_data_i21; - input fabric_user_data_i22; - input fabric_user_data_i23; - input fabric_user_data_i24; - input fabric_user_data_i25; - input fabric_user_data_i26; - input fabric_user_data_i27; - input fabric_user_data_i28; - input fabric_user_data_i29; - input fabric_user_data_i3; - input fabric_user_data_i30; - input fabric_user_data_i31; - input fabric_user_data_i32; - input fabric_user_data_i4; - input fabric_user_data_i5; - input fabric_user_data_i6; - input fabric_user_data_i7; - input fabric_user_data_i8; - input fabric_user_data_i9; - output fabric_user_data_o1; - output fabric_user_data_o10; - output fabric_user_data_o11; - output fabric_user_data_o12; - output fabric_user_data_o13; - output fabric_user_data_o14; - output fabric_user_data_o15; - output fabric_user_data_o16; - output fabric_user_data_o17; - output fabric_user_data_o18; - output fabric_user_data_o19; - output fabric_user_data_o2; - output fabric_user_data_o20; - output fabric_user_data_o21; - output fabric_user_data_o22; - output fabric_user_data_o23; - output fabric_user_data_o24; - output fabric_user_data_o25; - output fabric_user_data_o26; - output fabric_user_data_o27; - output fabric_user_data_o28; - output fabric_user_data_o29; - output fabric_user_data_o3; - output fabric_user_data_o30; - output fabric_user_data_o31; - output fabric_user_data_o32; - output fabric_user_data_o4; - output fabric_user_data_o5; - output fabric_user_data_o6; - output fabric_user_data_o7; - output fabric_user_data_o8; - output fabric_user_data_o9; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_IF_U_FULL_WRAP(fabric_mrepair_clk_i, fabric_clk_otp_mrepair_o, fabric_mrepair_cke_i, fabric_mrepair_por_i, fabric_mrepair_cke_force_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_bist_mode_o, fabric_mrepair_bend_i, fabric_mrepair_global_bbad_i, fabric_mrepair_global_repairable_i, fabric_mrepair_bypass_o, fabric_mrepair_memsafe_o, fabric_mrepair_mem_atpg_mode_o, fabric_mrepair_tst_gatedclock_o, fabric_mrepair_test_se_o, fabric_mrepair_data_to_system_o, fabric_mrepair_tst_atpg_mrepair_i, fabric_mrepair_data_from_system_i, fabric_mrepair_end_encoding_i, fabric_mrepair_system_dataready_o -, fabric_mrepair_decoder_init_ready_o, fabric_mrepair_fuse_pdn_i, fabric_mrepair_fuse_bistmode_i, fabric_mrepair_fuse_tm_i, fabric_mrepair_fuse_read_i, fabric_mrepair_fuse_prog_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_rbact2_i, fabric_mrepair_fuse_tstscanenable_i, fabric_mrepair_fuse_eccbypass_i, fabric_mrepair_fuse_wordlock_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_redbypass_i, fabric_mrepair_fuse_disturbchecked_i, fabric_mrepair_data_shift_en_i, fabric_mrepair_fuse_pwok_o, fabric_mrepair_fuse_ack_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_ded_o, fabric_mrepair_fuse_progfail_o, fabric_mrepair_fuse_locked_o -, fabric_mrepair_fuse_disturbed_o, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_bbad_o, fabric_mrepair_fuse_calibrated_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i -, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o -, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_otp_clk_i, fabric_otp_rst_i, fabric_otp_apb_write_i, fabric_otp_apb_sel_i, fabric_otp_apb_enable_i, fabric_otp_apb_ready_o, fabric_otp_cfg_fabric_apb_en_i, fabric_otp_cfg_loader_read_en_i -, fabric_otp_cfg_loader_write_en_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_security_ack_o, fabric_otp_security_rbact1_i, fabric_otp_security_rbact2_i, fabric_otp_security_bistmode_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_bist_end1_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_bad_o, fabric_otp_security_testmode_i, fabric_otp_security_scanenable_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_debug_rst_soft_o, fabric_debug_error_o, fabric_debug_otp_manager_read_otp_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o -, fabric_debug_key_correct_o, fabric_debug_otp_reload_err_o, fabric_debug_access_reg_data_ready_o, fabric_debug_security_error_read_o, fabric_debug_security_boot_done_o, fabric_debug_lock_reg_o, fabric_dac0_clk_i, fabric_dac0_clk_en_i, fabric_dac0_reg_pwr_down_n_i, fabric_dac0_rstn_i, fabric_dac0_op_en_i, fabric_dac0_filt_en_i, fabric_dac0_comp_en_i, fabric_dac0_comp_ref_sel_i, fabric_dac0_comp_hyst_en_i, fabric_dac0_comp_out_o, fabric_cfg_dac0_reg_vref_select_i, fabric_cfg_dac0_reg_cm_select_i, fabric_cfg_dac0_sync_i, fabric_dac1_clk_i, fabric_dac1_clk_en_i -, fabric_dac1_reg_pwr_down_n_i, fabric_dac1_rstn_i, fabric_dac1_op_en_i, fabric_dac1_filt_en_i, fabric_dac1_comp_en_i, fabric_dac1_comp_ref_sel_i, fabric_dac1_comp_hyst_en_i, fabric_dac1_comp_out_o, fabric_cfg_dac1_reg_vref_select_i, fabric_cfg_dac1_reg_cm_select_i, fabric_cfg_dac1_sync_i, fabric_dac2_clk_i, fabric_dac2_clk_en_i, fabric_dac2_reg_pwr_down_n_i, fabric_dac2_rstn_i, fabric_dac2_op_en_i, fabric_dac2_filt_en_i, fabric_dac2_comp_en_i, fabric_dac2_comp_ref_sel_i, fabric_dac2_comp_hyst_en_i, fabric_dac2_comp_out_o -, fabric_cfg_dac2_reg_vref_select_i, fabric_cfg_dac2_reg_cm_select_i, fabric_cfg_dac2_sync_i, fabric_dac3_clk_i, fabric_dac3_clk_en_i, fabric_dac3_reg_pwr_down_n_i, fabric_dac3_rstn_i, fabric_dac3_op_en_i, fabric_dac3_filt_en_i, fabric_dac3_comp_en_i, fabric_dac3_comp_ref_sel_i, fabric_dac3_comp_hyst_en_i, fabric_dac3_comp_out_o, fabric_cfg_dac3_reg_vref_select_i, fabric_cfg_dac3_reg_cm_select_i, fabric_cfg_dac3_sync_i, fabric_adc0_clk_i, fabric_adc0_cal_start_i, fabric_adc0_cal_done_o, fabric_adc0_cal_p_overflow_o, fabric_adc0_cal_p_underflow_o -, fabric_adc0_cal_n_overflow_o, fabric_adc0_cal_n_underflow_o, fabric_adc0_dft_scan_en_i, fabric_adc0_usr_cke_i, fabric_adc0_usr_conv_start_i, fabric_adc0_usr_conv_done_o, fabric_cfg_adc0_conv_done_delayed_i, fabric_cfg_adc0_use_cdc_i, fabric_adc1_clk_i, fabric_adc1_cal_start_i, fabric_adc1_cal_done_o, fabric_adc1_cal_p_overflow_o, fabric_adc1_cal_p_underflow_o, fabric_adc1_cal_n_overflow_o, fabric_adc1_cal_n_underflow_o, fabric_adc1_dft_scan_en_i, fabric_adc1_usr_cke_i, fabric_adc1_usr_conv_start_i, fabric_adc1_usr_conv_done_o, fabric_cfg_adc1_conv_done_delayed_i, fabric_cfg_adc1_use_cdc_i -, fabric_adc2_clk_i, fabric_adc2_cal_start_i, fabric_adc2_cal_done_o, fabric_adc2_cal_p_overflow_o, fabric_adc2_cal_p_underflow_o, fabric_adc2_cal_n_overflow_o, fabric_adc2_cal_n_underflow_o, fabric_adc2_dft_scan_en_i, fabric_adc2_usr_cke_i, fabric_adc2_usr_conv_start_i, fabric_adc2_usr_conv_done_o, fabric_cfg_adc2_conv_done_delayed_i, fabric_cfg_adc2_use_cdc_i, fabric_adc3_clk_i, fabric_adc3_cal_start_i, fabric_adc3_cal_done_o, fabric_adc3_cal_p_overflow_o, fabric_adc3_cal_p_underflow_o, fabric_adc3_cal_n_overflow_o, fabric_adc3_cal_n_underflow_o, fabric_adc3_dft_scan_en_i -, fabric_adc3_usr_cke_i, fabric_adc3_usr_conv_start_i, fabric_adc3_usr_conv_done_o, fabric_cfg_adc3_conv_done_delayed_i, fabric_cfg_adc3_use_cdc_i, fabric_direct0_scan_en_i, fabric_direct0_loopback_en_i, fabric_direct0_loopback_mux_i, fabric_direct2_scan_en_i, fabric_direct2_loopback_en_i, fabric_direct2_loopback_mux_i, fabric_direct1_scan_en_i, fabric_direct1_loopback_en_i, fabric_direct1_loopback_mux_i, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_thsens_tst_scanenable_i -, fabric_thsens_tst_scanin1_i, fabric_thsens_tst_scanin2_i, fabric_thsens_tst_scanout1_o, fabric_thsens_tst_scanout2_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i -, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_mrepair_data_to_bist_o, fabric_mrepair_shift_en_to_bist_o -, fabric_mrepair_sif_load_en_to_bist_o, fabric_mrepair_sif_update_en_to_bist_o, fabric_mrepair_sif_reg_en_to_bist_o, fabric_mrepair_system_data_to_mem_bist_i, fabric_mrepair_shift_en_i, fabric_mrepair_sif_load_en_i, fabric_mrepair_sif_update_en_i, fabric_mrepair_sif_reg_en_i, fabric_mrepair_system_data_from_mem_bist_o, fabric_mrepair_mem_type_sel_o, fabric_mrepair_mode_sel_o, fabric_mrepair_mode_i, fabric_mrepair_pd_active_i, fabric_mrepair_chip_status_o, fabric_mrepair_global_chip_status_o, fabric_mrepair_pd_ready_o, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o -, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_mrepair_fuse_status_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o -, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o -, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_dac0_din_i, fabric_dac0_comp_in_sel_i, fabric_cfg_dac0_reg_res_i, fabric_dac1_din_i, fabric_dac1_comp_in_sel_i, fabric_cfg_dac1_reg_res_i, fabric_dac2_din_i, fabric_dac2_comp_in_sel_i, fabric_cfg_dac2_reg_res_i, fabric_dac3_din_i, fabric_dac3_comp_in_sel_i -, fabric_cfg_dac3_reg_res_i, fabric_adc0_arst_b_tmr_i, fabric_adc0_pwr_down_b_tmr_i, fabric_adc0_spare_i, fabric_adc0_dft_test_mode_i, fabric_adc0_dft_si_i, fabric_adc0_usr_arst_b_tmr_i, fabric_adc0_usr_channel_i, fabric_adc0_usr_sample_o, fabric_adc0_usr_sample_lsb_i, fabric_adc0_dbg_addr_i, fabric_adc0_dbg_data_o, fabric_cfg_adc0_clk_cal_div_ratio_i, fabric_adc1_arst_b_tmr_i, fabric_adc1_pwr_down_b_tmr_i, fabric_adc1_spare_i, fabric_adc1_dft_test_mode_i, fabric_adc1_dft_si_i, fabric_adc1_usr_arst_b_tmr_i, fabric_adc1_usr_channel_i, fabric_adc1_usr_sample_o -, fabric_adc1_usr_sample_lsb_i, fabric_adc1_dbg_addr_i, fabric_adc1_dbg_data_o, fabric_cfg_adc1_clk_cal_div_ratio_i, fabric_adc2_arst_b_tmr_i, fabric_adc2_pwr_down_b_tmr_i, fabric_adc2_spare_i, fabric_adc2_dft_test_mode_i, fabric_adc2_dft_si_i, fabric_adc2_usr_arst_b_tmr_i, fabric_adc2_usr_channel_i, fabric_adc2_usr_sample_o, fabric_adc2_usr_sample_lsb_i, fabric_adc2_dbg_addr_i, fabric_adc2_dbg_data_o, fabric_cfg_adc2_clk_cal_div_ratio_i, fabric_adc3_arst_b_tmr_i, fabric_adc3_pwr_down_b_tmr_i, fabric_adc3_spare_i, fabric_adc3_dft_test_mode_i, fabric_adc3_dft_si_i -, fabric_adc3_usr_arst_b_tmr_i, fabric_adc3_usr_channel_i, fabric_adc3_usr_sample_o, fabric_adc3_usr_sample_lsb_i, fabric_adc3_dbg_addr_i, fabric_adc3_dbg_data_o, fabric_cfg_adc3_clk_cal_div_ratio_i, fabric_direct0_clock_fabric_i, fabric_direct0_oe_i, fabric_direct0_oe_ena_i, fabric_direct0_oe_rs_i, fabric_direct0_do_i, fabric_direct0_do_ena_i, fabric_direct0_do_rs_i, fabric_direct0_di_o, fabric_direct0_di_ena_i, fabric_direct0_di_rs_i, fabric_direct0_cfg_bank_i, fabric_direct0_cfg_pad_i, fabric_direct2_clock_fabric_i, fabric_direct2_oe_i -, fabric_direct2_oe_ena_i, fabric_direct2_oe_rs_i, fabric_direct2_do_i, fabric_direct2_do_ena_i, fabric_direct2_do_rs_i, fabric_direct2_di_o, fabric_direct2_di_ena_i, fabric_direct2_di_rs_i, fabric_direct2_cfg_bank_i, fabric_direct2_cfg_pad_i, fabric_direct1_clock_fabric_i, fabric_direct1_oe_i, fabric_direct1_oe_ena_i, fabric_direct1_oe_rs_i, fabric_direct1_do_i, fabric_direct1_do_ena_i, fabric_direct1_do_rs_i, fabric_direct1_di_o, fabric_direct1_di_ena_i, fabric_direct1_di_rs_i, fabric_direct1_cfg_bank_i -, fabric_direct1_cfg_pad_i, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i -, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o -, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o, fabric_mrepair_data_from_bist_i); - input [2:0] fabric_adc0_arst_b_tmr_i; - output fabric_adc0_cal_done_o; - output fabric_adc0_cal_n_overflow_o; - output fabric_adc0_cal_n_underflow_o; - output fabric_adc0_cal_p_overflow_o; - output fabric_adc0_cal_p_underflow_o; - input fabric_adc0_cal_start_i; - input fabric_adc0_clk_i; - input [3:0] fabric_adc0_dbg_addr_i; - output [31:0] fabric_adc0_dbg_data_o; - input fabric_adc0_dft_scan_en_i; - input [11:0] fabric_adc0_dft_si_i; - input [1:0] fabric_adc0_dft_test_mode_i; - input [2:0] fabric_adc0_pwr_down_b_tmr_i; - input [15:0] fabric_adc0_spare_i; - input [2:0] fabric_adc0_usr_arst_b_tmr_i; - input [2:0] fabric_adc0_usr_channel_i; - input fabric_adc0_usr_cke_i; - output fabric_adc0_usr_conv_done_o; - input fabric_adc0_usr_conv_start_i; - input [3:0] fabric_adc0_usr_sample_lsb_i; - output [11:0] fabric_adc0_usr_sample_o; - input [2:0] fabric_adc1_arst_b_tmr_i; - output fabric_adc1_cal_done_o; - output fabric_adc1_cal_n_overflow_o; - output fabric_adc1_cal_n_underflow_o; - output fabric_adc1_cal_p_overflow_o; - output fabric_adc1_cal_p_underflow_o; - input fabric_adc1_cal_start_i; - input fabric_adc1_clk_i; - input [3:0] fabric_adc1_dbg_addr_i; - output [31:0] fabric_adc1_dbg_data_o; - input fabric_adc1_dft_scan_en_i; - input [11:0] fabric_adc1_dft_si_i; - input [1:0] fabric_adc1_dft_test_mode_i; - input [2:0] fabric_adc1_pwr_down_b_tmr_i; - input [15:0] fabric_adc1_spare_i; - input [2:0] fabric_adc1_usr_arst_b_tmr_i; - input [2:0] fabric_adc1_usr_channel_i; - input fabric_adc1_usr_cke_i; - output fabric_adc1_usr_conv_done_o; - input fabric_adc1_usr_conv_start_i; - input [3:0] fabric_adc1_usr_sample_lsb_i; - output [11:0] fabric_adc1_usr_sample_o; - input [2:0] fabric_adc2_arst_b_tmr_i; - output fabric_adc2_cal_done_o; - output fabric_adc2_cal_n_overflow_o; - output fabric_adc2_cal_n_underflow_o; - output fabric_adc2_cal_p_overflow_o; - output fabric_adc2_cal_p_underflow_o; - input fabric_adc2_cal_start_i; - input fabric_adc2_clk_i; - input [3:0] fabric_adc2_dbg_addr_i; - output [31:0] fabric_adc2_dbg_data_o; - input fabric_adc2_dft_scan_en_i; - input [11:0] fabric_adc2_dft_si_i; - input [1:0] fabric_adc2_dft_test_mode_i; - input [2:0] fabric_adc2_pwr_down_b_tmr_i; - input [15:0] fabric_adc2_spare_i; - input [2:0] fabric_adc2_usr_arst_b_tmr_i; - input [2:0] fabric_adc2_usr_channel_i; - input fabric_adc2_usr_cke_i; - output fabric_adc2_usr_conv_done_o; - input fabric_adc2_usr_conv_start_i; - input [3:0] fabric_adc2_usr_sample_lsb_i; - output [11:0] fabric_adc2_usr_sample_o; - input [2:0] fabric_adc3_arst_b_tmr_i; - output fabric_adc3_cal_done_o; - output fabric_adc3_cal_n_overflow_o; - output fabric_adc3_cal_n_underflow_o; - output fabric_adc3_cal_p_overflow_o; - output fabric_adc3_cal_p_underflow_o; - input fabric_adc3_cal_start_i; - input fabric_adc3_clk_i; - input [3:0] fabric_adc3_dbg_addr_i; - output [31:0] fabric_adc3_dbg_data_o; - input fabric_adc3_dft_scan_en_i; - input [11:0] fabric_adc3_dft_si_i; - input [1:0] fabric_adc3_dft_test_mode_i; - input [2:0] fabric_adc3_pwr_down_b_tmr_i; - input [15:0] fabric_adc3_spare_i; - input [2:0] fabric_adc3_usr_arst_b_tmr_i; - input [2:0] fabric_adc3_usr_channel_i; - input fabric_adc3_usr_cke_i; - output fabric_adc3_usr_conv_done_o; - input fabric_adc3_usr_conv_start_i; - input [3:0] fabric_adc3_usr_sample_lsb_i; - output [11:0] fabric_adc3_usr_sample_o; - input [4:0] fabric_cfg_adc0_clk_cal_div_ratio_i; - input fabric_cfg_adc0_conv_done_delayed_i; - input fabric_cfg_adc0_use_cdc_i; - input [4:0] fabric_cfg_adc1_clk_cal_div_ratio_i; - input fabric_cfg_adc1_conv_done_delayed_i; - input fabric_cfg_adc1_use_cdc_i; - input [4:0] fabric_cfg_adc2_clk_cal_div_ratio_i; - input fabric_cfg_adc2_conv_done_delayed_i; - input fabric_cfg_adc2_use_cdc_i; - input [4:0] fabric_cfg_adc3_clk_cal_div_ratio_i; - input fabric_cfg_adc3_conv_done_delayed_i; - input fabric_cfg_adc3_use_cdc_i; - input fabric_cfg_dac0_reg_cm_select_i; - input [1:0] fabric_cfg_dac0_reg_res_i; - input fabric_cfg_dac0_reg_vref_select_i; - input fabric_cfg_dac0_sync_i; - input fabric_cfg_dac1_reg_cm_select_i; - input [1:0] fabric_cfg_dac1_reg_res_i; - input fabric_cfg_dac1_reg_vref_select_i; - input fabric_cfg_dac1_sync_i; - input fabric_cfg_dac2_reg_cm_select_i; - input [1:0] fabric_cfg_dac2_reg_res_i; - input fabric_cfg_dac2_reg_vref_select_i; - input fabric_cfg_dac2_sync_i; - input fabric_cfg_dac3_reg_cm_select_i; - input [1:0] fabric_cfg_dac3_reg_res_i; - input fabric_cfg_dac3_reg_vref_select_i; - input fabric_cfg_dac3_sync_i; - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_clk_bsm_o; - output fabric_clk_otp_mrepair_o; - input fabric_clk_otp_mux_i; - output fabric_clk_otp_o; - output fabric_clk_user0_o; - output fabric_clk_user1_o; - input fabric_dac0_clk_en_i; - input fabric_dac0_clk_i; - input fabric_dac0_comp_en_i; - input fabric_dac0_comp_hyst_en_i; - input [3:0] fabric_dac0_comp_in_sel_i; - output fabric_dac0_comp_out_o; - input fabric_dac0_comp_ref_sel_i; - input [12:0] fabric_dac0_din_i; - input fabric_dac0_filt_en_i; - input fabric_dac0_op_en_i; - input fabric_dac0_reg_pwr_down_n_i; - input fabric_dac0_rstn_i; - input fabric_dac1_clk_en_i; - input fabric_dac1_clk_i; - input fabric_dac1_comp_en_i; - input fabric_dac1_comp_hyst_en_i; - input [3:0] fabric_dac1_comp_in_sel_i; - output fabric_dac1_comp_out_o; - input fabric_dac1_comp_ref_sel_i; - input [12:0] fabric_dac1_din_i; - input fabric_dac1_filt_en_i; - input fabric_dac1_op_en_i; - input fabric_dac1_reg_pwr_down_n_i; - input fabric_dac1_rstn_i; - input fabric_dac2_clk_en_i; - input fabric_dac2_clk_i; - input fabric_dac2_comp_en_i; - input fabric_dac2_comp_hyst_en_i; - input [12:0] fabric_dac2_comp_in_sel_i; - output fabric_dac2_comp_out_o; - input fabric_dac2_comp_ref_sel_i; - input [12:0] fabric_dac2_din_i; - input fabric_dac2_filt_en_i; - input fabric_dac2_op_en_i; - input fabric_dac2_reg_pwr_down_n_i; - input fabric_dac2_rstn_i; - input fabric_dac3_clk_en_i; - input fabric_dac3_clk_i; - input fabric_dac3_comp_en_i; - input fabric_dac3_comp_hyst_en_i; - input [3:0] fabric_dac3_comp_in_sel_i; - output fabric_dac3_comp_out_o; - input fabric_dac3_comp_ref_sel_i; - input [12:0] fabric_dac3_din_i; - input fabric_dac3_filt_en_i; - input fabric_dac3_op_en_i; - input fabric_dac3_reg_pwr_down_n_i; - input fabric_dac3_rstn_i; - output fabric_debug_access_reg_data_ready_o; - output [31:0] fabric_debug_bsec_core_status_o; - output [3:0] fabric_debug_cpt_retry_o; - output [3:0] fabric_debug_direct_permission_read_o; - output [3:0] fabric_debug_direct_permission_write_o; - output fabric_debug_error_o; - output [3:0] fabric_debug_frame_permission_frame_o; - output fabric_debug_frame_use_encryption_o; - output [2:0] fabric_debug_fsm_state_o; - output fabric_debug_key_correct_o; - output [3:0] fabric_debug_lifecycle_o; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output [2:0] fabric_debug_otpapb_state_o; - output [7:0] fabric_debug_otpboot_curr_addr_o; - output [2:0] fabric_debug_otpboot_state_o; - output [2:0] fabric_debug_otpmgmt_state_o; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - input [3:0] fabric_direct0_cfg_bank_i; - input [719:0] fabric_direct0_cfg_pad_i; - input [3:0] fabric_direct0_clock_fabric_i; - input [23:0] fabric_direct0_di_ena_i; - output [23:0] fabric_direct0_di_o; - input [23:0] fabric_direct0_di_rs_i; - input [23:0] fabric_direct0_do_ena_i; - input [23:0] fabric_direct0_do_i; - input [23:0] fabric_direct0_do_rs_i; - input fabric_direct0_loopback_en_i; - input fabric_direct0_loopback_mux_i; - input [23:0] fabric_direct0_oe_ena_i; - input [23:0] fabric_direct0_oe_i; - input [23:0] fabric_direct0_oe_rs_i; - input fabric_direct0_scan_en_i; - input [3:0] fabric_direct1_cfg_bank_i; - input [479:0] fabric_direct1_cfg_pad_i; - input [3:0] fabric_direct1_clock_fabric_i; - input [15:0] fabric_direct1_di_ena_i; - output [15:0] fabric_direct1_di_o; - input [15:0] fabric_direct1_di_rs_i; - input [15:0] fabric_direct1_do_ena_i; - input [15:0] fabric_direct1_do_i; - input [15:0] fabric_direct1_do_rs_i; - input fabric_direct1_loopback_en_i; - input fabric_direct1_loopback_mux_i; - input [15:0] fabric_direct1_oe_ena_i; - input [15:0] fabric_direct1_oe_i; - input [15:0] fabric_direct1_oe_rs_i; - input fabric_direct1_scan_en_i; - input [3:0] fabric_direct2_cfg_bank_i; - input [719:0] fabric_direct2_cfg_pad_i; - input [3:0] fabric_direct2_clock_fabric_i; - input [23:0] fabric_direct2_di_ena_i; - output [23:0] fabric_direct2_di_o; - input [23:0] fabric_direct2_di_rs_i; - input [23:0] fabric_direct2_do_ena_i; - input [23:0] fabric_direct2_do_i; - input [23:0] fabric_direct2_do_rs_i; - input fabric_direct2_loopback_en_i; - input fabric_direct2_loopback_mux_i; - input [23:0] fabric_direct2_oe_ena_i; - input [23:0] fabric_direct2_oe_i; - input [23:0] fabric_direct2_oe_rs_i; - input fabric_direct2_scan_en_i; - input [31:0] fabric_direct_data_i; - output [31:0] fabric_direct_data_o; - input [2:0] fabric_enable_TMR_i; - output [2:0] fabric_flag_ready_TMR_o; - output fabric_flag_trigger0_o; - output fabric_flag_trigger1_o; - input [34:0] fabric_io_in_i; - input [34:0] fabric_io_oe_i; - output [34:0] fabric_io_out_o; - output fabric_jtag_tck_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input [39:0] fabric_lowskew_i; - output [5:0] fabric_lowskew_o; - input fabric_mrepair_bend_i; - output fabric_mrepair_bist_mode_o; - output fabric_mrepair_bypass_o; - output [77:0] fabric_mrepair_chip_status_o; - input fabric_mrepair_cke_force_i; - input fabric_mrepair_cke_i; - input fabric_mrepair_clk_i; - input [25:0] fabric_mrepair_data_from_bist_i; - input fabric_mrepair_data_from_system_i; - input fabric_mrepair_data_shift_en_i; - output [25:0] fabric_mrepair_data_to_bist_o; - output fabric_mrepair_data_to_system_o; - output fabric_mrepair_decoder_init_ready_o; - input fabric_mrepair_end_encoding_i; - output fabric_mrepair_fuse_ack_o; - input [6:0] fabric_mrepair_fuse_add_i; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output [7:0] fabric_mrepair_fuse_bist1fail_o; - output [6:0] fabric_mrepair_fuse_bist2fail_o; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - output fabric_mrepair_fuse_ded_o; - input [38:0] fabric_mrepair_fuse_din_i; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output [40:0] fabric_mrepair_fuse_dout_o; - input fabric_mrepair_fuse_eccbypass_i; - output [3:0] fabric_mrepair_fuse_flagstate_o; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input [2:0] fabric_mrepair_fuse_prgwidth_i; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output [15:0] fabric_mrepair_fuse_startword_o; - output [2:0] fabric_mrepair_fuse_status_o; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input [4:0] fabric_mrepair_fuse_tst_scanin_i; - input fabric_mrepair_fuse_tstscanenable_i; - output [4:0] fabric_mrepair_fuse_tstscanout_o; - output [9:0] fabric_mrepair_fuse_wlromout_o; - input fabric_mrepair_fuse_wordlock_i; - input fabric_mrepair_global_bbad_i; - output [2:0] fabric_mrepair_global_chip_status_o; - input fabric_mrepair_global_repairable_i; - input fabric_mrepair_initn_i; - output fabric_mrepair_mem_atpg_mode_o; - output [4:0] fabric_mrepair_mem_type_sel_o; - output fabric_mrepair_memsafe_o; - input [3:0] fabric_mrepair_mode_i; - output [3:0] fabric_mrepair_mode_sel_o; - input [25:0] fabric_mrepair_pd_active_i; - output [25:0] fabric_mrepair_pd_ready_o; - input fabric_mrepair_por_i; - input fabric_mrepair_rst_n_i; - input [25:0] fabric_mrepair_shift_en_i; - output [25:0] fabric_mrepair_shift_en_to_bist_o; - input [25:0] fabric_mrepair_sif_load_en_i; - output [25:0] fabric_mrepair_sif_load_en_to_bist_o; - input [25:0] fabric_mrepair_sif_reg_en_i; - output [25:0] fabric_mrepair_sif_reg_en_to_bist_o; - input [25:0] fabric_mrepair_sif_update_en_i; - output [25:0] fabric_mrepair_sif_update_en_to_bist_o; - output [25:0] fabric_mrepair_system_data_from_mem_bist_o; - input [25:0] fabric_mrepair_system_data_to_mem_bist_i; - output fabric_mrepair_system_dataready_o; - output fabric_mrepair_test_se_o; - input fabric_mrepair_tst_atpg_mrepair_i; - output fabric_mrepair_tst_gatedclock_o; - input [31:0] fabric_otp_apb_addr_i; - input fabric_otp_apb_enable_i; - output [31:0] fabric_otp_apb_rdata_o; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input [31:0] fabric_otp_apb_wdata_i; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_clk_i; - input fabric_otp_rst_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output [6:0] fabric_otp_security_bist_fail1_o; - output [5:0] fabric_otp_security_bist_fail2_o; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input [3:0] fabric_otp_security_scanin_i; - output [3:0] fabric_otp_security_scanout_o; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input [6:0] fabric_otp_user_add_i; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output [7:0] fabric_otp_user_bist1fail_o; - output [6:0] fabric_otp_user_bist2fail_o; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clk_i; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input [38:0] fabric_otp_user_din_i; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output [40:0] fabric_otp_user_dout_o; - input fabric_otp_user_eccbypass_i; - output [3:0] fabric_otp_user_flagstate_o; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input [2:0] fabric_otp_user_prgwidth_i; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output [15:0] fabric_otp_user_startword_o; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input [4:0] fabric_otp_user_tst_scanin_i; - output [4:0] fabric_otp_user_tst_scanout_o; - output [9:0] fabric_otp_user_wlromout_o; - input fabric_otp_user_wordlock_i; - input fabric_parusr_clk_i; - input fabric_parusr_cs_i; - input [15:0] fabric_parusr_data_i; - output [15:0] fabric_parusr_data_o; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input [1:0] fabric_parusr_type_i; - input [127:0] fabric_spare_i; - output [127:0] fabric_spare_o; - input [8:0] fabric_spi_arst_tmr_n_i; - output [2:0] fabric_spi_bsm_release_o; - output [2:0] fabric_spi_busy_o; - input fabric_spi_clk_i0; - input fabric_spi_clk_i1; - input fabric_spi_clk_i2; - input [5:0] fabric_spi_cmd_bytes_i; - output [2:0] fabric_spi_cmd_full_o; - input [5:0] fabric_spi_cmd_mode_i; - input [2:0] fabric_spi_cmd_push_i; - input [5:0] fabric_spi_cmd_type_i; - input [2:0] fabric_spi_cpha_i; - input [2:0] fabric_spi_cpol_i; - input [11:0] fabric_spi_cs_holdtime_i; - input [11:0] fabric_spi_cs_offtime_i; - input [11:0] fabric_spi_cs_setuptime_i; - input [2:0] fabric_spi_data_in_unlimited_i; - input [2:0] fabric_spi_enable_i; - output [2:0] fabric_spi_error_endianness_o; - output [2:0] fabric_spi_error_loopback_o; - output [2:0] fabric_spi_error_mode_o; - output [2:0] fabric_spi_error_sel_o; - input [8:0] fabric_spi_fifo_arst_tmr_n_i; - output [2:0] fabric_spi_init_done_o; - input [2:0] fabric_spi_legacy_enable_i; - input [2:0] fabric_spi_legacy_master_i; - input [2:0] fabric_spi_loopback_i; - input [2:0] fabric_spi_lsb_first_i; - output [2:0] fabric_spi_miso_data_inv_o; - output [23:0] fabric_spi_miso_data_o; - output [2:0] fabric_spi_miso_empty_o; - input [2:0] fabric_spi_miso_pop_i; - input [23:0] fabric_spi_mosi_data_i; - input [2:0] fabric_spi_mosi_data_inv_i; - output [2:0] fabric_spi_mosi_full_o; - input [2:0] fabric_spi_mosi_push_i; - input [2:0] fabric_spi_needed_i; - input [47:0] fabric_spi_powerdown_cycle_i; - input [47:0] fabric_spi_powerup_cycle_i; - input [2:0] fabric_spi_rst_n_i; - input fabric_spi_sck_i0; - input fabric_spi_sck_i1; - input fabric_spi_sck_i2; - input [2:0] fabric_spi_vcc_enable_i; - output [2:0] fabric_spi_vcc_used_o; - input [6:2] fabric_spw0_apb_slv_paddr_i; - input fabric_spw0_apb_slv_penable_i; - output [30:0] fabric_spw0_apb_slv_prdata_o; - output fabric_spw0_apb_slv_pready_o; - input fabric_spw0_apb_slv_psel_i; - output fabric_spw0_apb_slv_pslverr_o; - input [30:0] fabric_spw0_apb_slv_pwdata_i; - input fabric_spw0_apb_slv_pwrite_i; - input fabric_spw0_clk_i; - input fabric_spw0_clk_tx_i; - input fabric_spw0_rst_n_i; - output [8:0] fabric_spw0_rx_fifo_data_o; - output fabric_spw0_rx_fifo_empty_o; - input fabric_spw0_rx_fifo_read_i; - input fabric_spw0_tick_ctm_i; - output fabric_spw0_tick_ctm_o; - input [8:0] fabric_spw0_tx_fifo_data_i; - output fabric_spw0_tx_fifo_full_o; - input fabric_spw0_tx_fifo_write_i; - output fabric_spw0_user_shared_o; - input [6:2] fabric_spw1_apb_slv_paddr_i; - input fabric_spw1_apb_slv_penable_i; - output [30:0] fabric_spw1_apb_slv_prdata_o; - output fabric_spw1_apb_slv_pready_o; - input fabric_spw1_apb_slv_psel_i; - output fabric_spw1_apb_slv_pslverr_o; - input [30:0] fabric_spw1_apb_slv_pwdata_i; - input fabric_spw1_apb_slv_pwrite_i; - input fabric_spw1_clk_i; - input fabric_spw1_clk_tx_i; - input fabric_spw1_rst_n_i; - output [8:0] fabric_spw1_rx_fifo_data_o; - output fabric_spw1_rx_fifo_empty_o; - input fabric_spw1_rx_fifo_read_i; - input fabric_spw1_tick_ctm_i; - output fabric_spw1_tick_ctm_o; - input [8:0] fabric_spw1_tx_fifo_data_i; - output fabric_spw1_tx_fifo_full_o; - input fabric_spw1_tx_fifo_write_i; - output fabric_spw1_user_shared_o; - output fabric_status_cold_start_o; - input [2:0] fabric_thsens_arst_tmr_n_i; - input [7:0] fabric_thsens_clk_div_ratio_i; - input fabric_thsens_clk_i; - output [26:0] fabric_thsens_fm_config_r_o; - input [26:0] fabric_thsens_fm_config_w_i; - input fabric_thsens_fm_config_wen_i; - output [13:0] fabric_thsens_fm_data_o; - input fabric_thsens_fm_enable_i; - output [31:0] fabric_thsens_fm_mode_r_o; - input [31:0] fabric_thsens_fm_mode_w_i; - input fabric_thsens_fm_mode_wen_i; - output fabric_thsens_fm_overflow_o; - output fabric_thsens_fm_valid_o; - output [26:0] fabric_thsens_otp_config_o; - input fabric_thsens_tst_scanenable_i; - input fabric_thsens_tst_scanin1_i; - input fabric_thsens_tst_scanin2_i; - output fabric_thsens_tst_scanout1_o; - output fabric_thsens_tst_scanout2_o; - input fabric_user_clk_i; - input [31:0] fabric_user_data_i; - output [31:0] fabric_user_data_o; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_IF_U_WRAP(fabric_otp_user_clk_i, fabric_otp_user_bistmode_i, fabric_otp_user_disturbcheck_i, fabric_otp_user_eccbypass_i, fabric_otp_user_pdn_i, fabric_otp_user_prog_i, fabric_otp_user_rbact1_i, fabric_otp_user_rbact2_i, fabric_otp_user_read_i, fabric_otp_user_redbypass_i, fabric_otp_user_suppadd_i, fabric_otp_user_tm_i, fabric_otp_user_tst_scanenable_i, fabric_otp_user_wordlock_i, fabric_otp_user_clock_frequency_range_i, fabric_otp_user_ack_o, fabric_otp_user_bbad_o, fabric_otp_user_bend1_o, fabric_otp_user_bend2_o, fabric_otp_user_calibrated_o, fabric_otp_user_ded_o -, fabric_otp_user_disturbed_o, fabric_otp_user_locked_o, fabric_otp_user_progfail_o, fabric_otp_user_pwok_o, fabric_otp_user_sec_o, fabric_clk_bsm_o, fabric_clk_otp_mux_i, fabric_clk_otp_o, fabric_clk_user0_o, fabric_clk_user1_o, fabric_user_clk_i, fabric_user_write_cycle_o, fabric_user_read_cycle_o, fabric_cfg_fabric_user_flag_o, fabric_cfg_fabric_user_enable_o, fabric_parusr_clk_i, fabric_parusr_enable_i, fabric_parusr_cs_i, fabric_parusr_data_val_o, fabric_jtag_tck_o, fabric_jtag_trst_n_o -, fabric_jtag_tms_o, fabric_jtag_tdi_o, fabric_jtag_usr1_o, fabric_jtag_usr2_o, fabric_jtag_tdo_usr1_i, fabric_jtag_tdo_usr2_i, fabric_status_cold_start_o, fabric_flag_trigger0_o, fabric_flag_trigger1_o, fabric_thsens_clk_i, fabric_thsens_fm_enable_i, fabric_thsens_fm_mode_wen_i, fabric_thsens_fm_config_wen_i, fabric_thsens_fm_valid_o, fabric_thsens_fm_overflow_o, fabric_spi_clk_i2, fabric_spi_sck_i2, fabric_spi_clk_i0, fabric_spi_sck_i0, fabric_spi_clk_i1, fabric_spi_sck_i1 -, fabric_spw0_clk_i, fabric_spw0_clk_tx_i, fabric_spw0_rst_n_i, fabric_spw0_user_shared_o, fabric_spw0_tx_fifo_write_i, fabric_spw0_tx_fifo_full_o, fabric_spw0_rx_fifo_read_i, fabric_spw0_rx_fifo_empty_o, fabric_spw0_tick_ctm_i, fabric_spw0_tick_ctm_o, fabric_spw0_apb_slv_psel_i, fabric_spw0_apb_slv_penable_i, fabric_spw0_apb_slv_pwrite_i, fabric_spw0_apb_slv_pready_o, fabric_spw0_apb_slv_pslverr_o, fabric_spw1_clk_i, fabric_spw1_clk_tx_i, fabric_spw1_rst_n_i, fabric_spw1_user_shared_o, fabric_spw1_tx_fifo_write_i, fabric_spw1_tx_fifo_full_o -, fabric_spw1_rx_fifo_read_i, fabric_spw1_rx_fifo_empty_o, fabric_spw1_tick_ctm_i, fabric_spw1_tick_ctm_o, fabric_spw1_apb_slv_psel_i, fabric_spw1_apb_slv_penable_i, fabric_spw1_apb_slv_pwrite_i, fabric_spw1_apb_slv_pready_o, fabric_spw1_apb_slv_pslverr_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i -, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o, fabric_flag_ready_TMR_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_spare_i, fabric_spare_o, fabric_thsens_arst_tmr_n_i, fabric_thsens_fm_mode_w_i, fabric_thsens_fm_config_w_i, fabric_thsens_fm_data_o, fabric_thsens_fm_mode_r_o, fabric_thsens_fm_config_r_o, fabric_thsens_clk_div_ratio_i, fabric_thsens_otp_config_o -, fabric_spi_needed_i, fabric_spi_bsm_release_o, fabric_spi_arst_tmr_n_i, fabric_spi_fifo_arst_tmr_n_i, fabric_spi_cpol_i, fabric_spi_cpha_i, fabric_spi_loopback_i, fabric_spi_lsb_first_i, fabric_spi_cs_setuptime_i, fabric_spi_cs_holdtime_i, fabric_spi_cs_offtime_i, fabric_spi_vcc_enable_i, fabric_spi_powerdown_cycle_i, fabric_spi_powerup_cycle_i, fabric_spi_legacy_enable_i, fabric_spi_legacy_master_i, fabric_spi_data_in_unlimited_i, fabric_spi_enable_i, fabric_spi_rst_n_i, fabric_spi_init_done_o, fabric_spi_busy_o -, fabric_spi_vcc_used_o, fabric_spi_error_sel_o, fabric_spi_error_loopback_o, fabric_spi_error_mode_o, fabric_spi_error_endianness_o, fabric_spi_cmd_push_i, fabric_spi_cmd_full_o, fabric_spi_cmd_type_i, fabric_spi_cmd_mode_i, fabric_spi_cmd_bytes_i, fabric_spi_mosi_push_i, fabric_spi_mosi_full_o, fabric_spi_mosi_data_i, fabric_spi_mosi_data_inv_i, fabric_spi_miso_pop_i, fabric_spi_miso_empty_o, fabric_spi_miso_data_o, fabric_spi_miso_data_inv_o, fabric_spw0_tx_fifo_data_i, fabric_spw0_rx_fifo_data_o, fabric_spw0_apb_slv_paddr_i -, fabric_spw0_apb_slv_pwdata_i, fabric_spw0_apb_slv_prdata_o, fabric_spw1_tx_fifo_data_i, fabric_spw1_rx_fifo_data_o, fabric_spw1_apb_slv_paddr_i, fabric_spw1_apb_slv_pwdata_i, fabric_spw1_apb_slv_prdata_o); - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_clk_bsm_o; - input fabric_clk_otp_mux_i; - output fabric_clk_otp_o; - output fabric_clk_user0_o; - output fabric_clk_user1_o; - input [2:0] fabric_enable_TMR_i; - output [2:0] fabric_flag_ready_TMR_o; - output fabric_flag_trigger0_o; - output fabric_flag_trigger1_o; - input [34:0] fabric_io_in_i; - input [34:0] fabric_io_oe_i; - output [34:0] fabric_io_out_o; - output fabric_jtag_tck_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input [39:0] fabric_lowskew_i; - output [5:0] fabric_lowskew_o; - output fabric_otp_user_ack_o; - input [6:0] fabric_otp_user_add_i; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output [7:0] fabric_otp_user_bist1fail_o; - output [6:0] fabric_otp_user_bist2fail_o; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clk_i; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input [38:0] fabric_otp_user_din_i; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output [40:0] fabric_otp_user_dout_o; - input fabric_otp_user_eccbypass_i; - output [3:0] fabric_otp_user_flagstate_o; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input [2:0] fabric_otp_user_prgwidth_i; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output [15:0] fabric_otp_user_startword_o; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input [4:0] fabric_otp_user_tst_scanin_i; - output [4:0] fabric_otp_user_tst_scanout_o; - output [9:0] fabric_otp_user_wlromout_o; - input fabric_otp_user_wordlock_i; - input fabric_parusr_clk_i; - input fabric_parusr_cs_i; - input [15:0] fabric_parusr_data_i; - output [15:0] fabric_parusr_data_o; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input [1:0] fabric_parusr_type_i; - input [127:0] fabric_spare_i; - output [127:0] fabric_spare_o; - input [8:0] fabric_spi_arst_tmr_n_i; - output [2:0] fabric_spi_bsm_release_o; - output [2:0] fabric_spi_busy_o; - input fabric_spi_clk_i0; - input fabric_spi_clk_i1; - input fabric_spi_clk_i2; - input [5:0] fabric_spi_cmd_bytes_i; - output [2:0] fabric_spi_cmd_full_o; - input [5:0] fabric_spi_cmd_mode_i; - input [2:0] fabric_spi_cmd_push_i; - input [5:0] fabric_spi_cmd_type_i; - input [2:0] fabric_spi_cpha_i; - input [2:0] fabric_spi_cpol_i; - input [11:0] fabric_spi_cs_holdtime_i; - input [11:0] fabric_spi_cs_offtime_i; - input [11:0] fabric_spi_cs_setuptime_i; - input [2:0] fabric_spi_data_in_unlimited_i; - input [2:0] fabric_spi_enable_i; - output [2:0] fabric_spi_error_endianness_o; - output [2:0] fabric_spi_error_loopback_o; - output [2:0] fabric_spi_error_mode_o; - output [2:0] fabric_spi_error_sel_o; - input [8:0] fabric_spi_fifo_arst_tmr_n_i; - output [2:0] fabric_spi_init_done_o; - input [2:0] fabric_spi_legacy_enable_i; - input [2:0] fabric_spi_legacy_master_i; - input [2:0] fabric_spi_loopback_i; - input [2:0] fabric_spi_lsb_first_i; - output [2:0] fabric_spi_miso_data_inv_o; - output [23:0] fabric_spi_miso_data_o; - output [2:0] fabric_spi_miso_empty_o; - input [2:0] fabric_spi_miso_pop_i; - input [23:0] fabric_spi_mosi_data_i; - input [2:0] fabric_spi_mosi_data_inv_i; - output [2:0] fabric_spi_mosi_full_o; - input [2:0] fabric_spi_mosi_push_i; - input [2:0] fabric_spi_needed_i; - input [47:0] fabric_spi_powerdown_cycle_i; - input [47:0] fabric_spi_powerup_cycle_i; - input [2:0] fabric_spi_rst_n_i; - input fabric_spi_sck_i0; - input fabric_spi_sck_i1; - input fabric_spi_sck_i2; - input [2:0] fabric_spi_vcc_enable_i; - output [2:0] fabric_spi_vcc_used_o; - input [6:2] fabric_spw0_apb_slv_paddr_i; - input fabric_spw0_apb_slv_penable_i; - output [30:0] fabric_spw0_apb_slv_prdata_o; - output fabric_spw0_apb_slv_pready_o; - input fabric_spw0_apb_slv_psel_i; - output fabric_spw0_apb_slv_pslverr_o; - input [30:0] fabric_spw0_apb_slv_pwdata_i; - input fabric_spw0_apb_slv_pwrite_i; - input fabric_spw0_clk_i; - input fabric_spw0_clk_tx_i; - input fabric_spw0_rst_n_i; - output [8:0] fabric_spw0_rx_fifo_data_o; - output fabric_spw0_rx_fifo_empty_o; - input fabric_spw0_rx_fifo_read_i; - input fabric_spw0_tick_ctm_i; - output fabric_spw0_tick_ctm_o; - input [8:0] fabric_spw0_tx_fifo_data_i; - output fabric_spw0_tx_fifo_full_o; - input fabric_spw0_tx_fifo_write_i; - output fabric_spw0_user_shared_o; - input [6:2] fabric_spw1_apb_slv_paddr_i; - input fabric_spw1_apb_slv_penable_i; - output [30:0] fabric_spw1_apb_slv_prdata_o; - output fabric_spw1_apb_slv_pready_o; - input fabric_spw1_apb_slv_psel_i; - output fabric_spw1_apb_slv_pslverr_o; - input [30:0] fabric_spw1_apb_slv_pwdata_i; - input fabric_spw1_apb_slv_pwrite_i; - input fabric_spw1_clk_i; - input fabric_spw1_clk_tx_i; - input fabric_spw1_rst_n_i; - output [8:0] fabric_spw1_rx_fifo_data_o; - output fabric_spw1_rx_fifo_empty_o; - input fabric_spw1_rx_fifo_read_i; - input fabric_spw1_tick_ctm_i; - output fabric_spw1_tick_ctm_o; - input [8:0] fabric_spw1_tx_fifo_data_i; - output fabric_spw1_tx_fifo_full_o; - input fabric_spw1_tx_fifo_write_i; - output fabric_spw1_user_shared_o; - output fabric_status_cold_start_o; - input [2:0] fabric_thsens_arst_tmr_n_i; - input [7:0] fabric_thsens_clk_div_ratio_i; - input fabric_thsens_clk_i; - output [26:0] fabric_thsens_fm_config_r_o; - input [26:0] fabric_thsens_fm_config_w_i; - input fabric_thsens_fm_config_wen_i; - output [13:0] fabric_thsens_fm_data_o; - input fabric_thsens_fm_enable_i; - output [31:0] fabric_thsens_fm_mode_r_o; - input [31:0] fabric_thsens_fm_mode_w_i; - input fabric_thsens_fm_mode_wen_i; - output fabric_thsens_fm_overflow_o; - output fabric_thsens_fm_valid_o; - output [26:0] fabric_thsens_otp_config_o; - input fabric_user_clk_i; - input [31:0] fabric_user_data_i; - output [31:0] fabric_user_data_o; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_U(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17 -, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38 -, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17 -, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i -, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i -, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16 -, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37 -, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58 -, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79 -, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100 -, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i -, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20 -, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13 -, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9 -, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30 -, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16 -, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4 -, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i -, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i -, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19 -, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15 -, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12 -, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33 -, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15 -, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i -, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20 -, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8 -, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4 -, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7 -, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22 -, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13, fabric_sif_update_en_i14 -, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2, fabric_debug_direct_permission_write_o3 -, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5, fabric_sif_update_en_to_bist_o6 -, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o, fabric_debug_frame_permission_frame_o1 -, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13, fabric_data_to_bist_o14 -, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10, fabric_otp_user_startword_o11 -, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15, fabric_ahb_direct_data_o16 -, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4, fabric_parusr_data_o5 -, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1, fabric_fuse_status_o2 -, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19, fabric_otp_apb_rdata_o20 -, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7, fabric_debug_bsec_core_status_o8 -, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28, fabric_debug_bsec_core_status_o29 -, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_TMR_o1, fabric_flag_ready_TMR_o2, fabric_flag_ready_TMR_o3, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7 -, fabric_mrepair_fuse_dout_o8, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28 -, fabric_mrepair_fuse_dout_o29, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5 -, fabric_shift_en_to_bist_o6, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2 -, fabric_sif_reg_en_to_bist_o3, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23 -, fabric_sif_reg_en_to_bist_o24, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44 -, fabric_sif_reg_en_to_bist_o45, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65 -, fabric_sif_reg_en_to_bist_o66, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86 -, fabric_sif_reg_en_to_bist_o87, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107 -, fabric_sif_reg_en_to_bist_o108, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6 -, fabric_otp_user_wlromout_o7, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12 -, fabric_system_data_from_mem_bist_o13, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9 -, fabric_direct_data_o10, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30 -, fabric_direct_data_o31, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17 -, fabric_chip_status_o18, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38 -, fabric_chip_status_o39, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59 -, fabric_chip_status_o60, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4 -, fabric_pd_ready_o5, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o -, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3 -, fabric_otp_user_bist2fail_o4, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17 -, fabric_user_data_o18, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o -, fabric_mrepair_fuse_wlromout_o1, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8 -, fabric_otp_security_bist_fail2_o1, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2 -, fabric_otp_user_flagstate_o3, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4 -, fabric_debug_otpboot_curr_addr_o5, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15 -, fabric_sif_load_en_to_bist_o16, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12 -, fabric_io_out_o13, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8 -, fabric_mrepair_fuse_startword_o9, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9 -, fabric_otp_user_dout_o10, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30 -, fabric_otp_user_dout_o31, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1 -, fabric_debug_direct_permission_read_o2, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i); - input fabric_ahb_direct_data_i1; - input fabric_ahb_direct_data_i10; - input fabric_ahb_direct_data_i11; - input fabric_ahb_direct_data_i12; - input fabric_ahb_direct_data_i13; - input fabric_ahb_direct_data_i14; - input fabric_ahb_direct_data_i15; - input fabric_ahb_direct_data_i16; - input fabric_ahb_direct_data_i17; - input fabric_ahb_direct_data_i18; - input fabric_ahb_direct_data_i19; - input fabric_ahb_direct_data_i2; - input fabric_ahb_direct_data_i20; - input fabric_ahb_direct_data_i21; - input fabric_ahb_direct_data_i22; - input fabric_ahb_direct_data_i23; - input fabric_ahb_direct_data_i24; - input fabric_ahb_direct_data_i25; - input fabric_ahb_direct_data_i26; - input fabric_ahb_direct_data_i27; - input fabric_ahb_direct_data_i28; - input fabric_ahb_direct_data_i29; - input fabric_ahb_direct_data_i3; - input fabric_ahb_direct_data_i30; - input fabric_ahb_direct_data_i31; - input fabric_ahb_direct_data_i32; - input fabric_ahb_direct_data_i4; - input fabric_ahb_direct_data_i5; - input fabric_ahb_direct_data_i6; - input fabric_ahb_direct_data_i7; - input fabric_ahb_direct_data_i8; - input fabric_ahb_direct_data_i9; - output fabric_ahb_direct_data_o1; - output fabric_ahb_direct_data_o10; - output fabric_ahb_direct_data_o11; - output fabric_ahb_direct_data_o12; - output fabric_ahb_direct_data_o13; - output fabric_ahb_direct_data_o14; - output fabric_ahb_direct_data_o15; - output fabric_ahb_direct_data_o16; - output fabric_ahb_direct_data_o17; - output fabric_ahb_direct_data_o18; - output fabric_ahb_direct_data_o19; - output fabric_ahb_direct_data_o2; - output fabric_ahb_direct_data_o20; - output fabric_ahb_direct_data_o21; - output fabric_ahb_direct_data_o22; - output fabric_ahb_direct_data_o23; - output fabric_ahb_direct_data_o24; - output fabric_ahb_direct_data_o25; - output fabric_ahb_direct_data_o26; - output fabric_ahb_direct_data_o27; - output fabric_ahb_direct_data_o28; - output fabric_ahb_direct_data_o29; - output fabric_ahb_direct_data_o3; - output fabric_ahb_direct_data_o30; - output fabric_ahb_direct_data_o31; - output fabric_ahb_direct_data_o32; - output fabric_ahb_direct_data_o4; - output fabric_ahb_direct_data_o5; - output fabric_ahb_direct_data_o6; - output fabric_ahb_direct_data_o7; - output fabric_ahb_direct_data_o8; - output fabric_ahb_direct_data_o9; - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_chip_status_o1; - output fabric_chip_status_o10; - output fabric_chip_status_o11; - output fabric_chip_status_o12; - output fabric_chip_status_o13; - output fabric_chip_status_o14; - output fabric_chip_status_o15; - output fabric_chip_status_o16; - output fabric_chip_status_o17; - output fabric_chip_status_o18; - output fabric_chip_status_o19; - output fabric_chip_status_o2; - output fabric_chip_status_o20; - output fabric_chip_status_o21; - output fabric_chip_status_o22; - output fabric_chip_status_o23; - output fabric_chip_status_o24; - output fabric_chip_status_o25; - output fabric_chip_status_o26; - output fabric_chip_status_o27; - output fabric_chip_status_o28; - output fabric_chip_status_o29; - output fabric_chip_status_o3; - output fabric_chip_status_o30; - output fabric_chip_status_o31; - output fabric_chip_status_o32; - output fabric_chip_status_o33; - output fabric_chip_status_o34; - output fabric_chip_status_o35; - output fabric_chip_status_o36; - output fabric_chip_status_o37; - output fabric_chip_status_o38; - output fabric_chip_status_o39; - output fabric_chip_status_o4; - output fabric_chip_status_o40; - output fabric_chip_status_o41; - output fabric_chip_status_o42; - output fabric_chip_status_o43; - output fabric_chip_status_o44; - output fabric_chip_status_o45; - output fabric_chip_status_o46; - output fabric_chip_status_o47; - output fabric_chip_status_o48; - output fabric_chip_status_o49; - output fabric_chip_status_o5; - output fabric_chip_status_o50; - output fabric_chip_status_o51; - output fabric_chip_status_o52; - output fabric_chip_status_o53; - output fabric_chip_status_o54; - output fabric_chip_status_o55; - output fabric_chip_status_o56; - output fabric_chip_status_o57; - output fabric_chip_status_o58; - output fabric_chip_status_o59; - output fabric_chip_status_o6; - output fabric_chip_status_o60; - output fabric_chip_status_o61; - output fabric_chip_status_o62; - output fabric_chip_status_o63; - output fabric_chip_status_o64; - output fabric_chip_status_o65; - output fabric_chip_status_o66; - output fabric_chip_status_o67; - output fabric_chip_status_o68; - output fabric_chip_status_o69; - output fabric_chip_status_o7; - output fabric_chip_status_o70; - output fabric_chip_status_o71; - output fabric_chip_status_o72; - output fabric_chip_status_o8; - output fabric_chip_status_o9; - input fabric_clk_otp_mux_i; - input fabric_data_from_bist_i1; - input fabric_data_from_bist_i10; - input fabric_data_from_bist_i11; - input fabric_data_from_bist_i12; - input fabric_data_from_bist_i13; - input fabric_data_from_bist_i14; - input fabric_data_from_bist_i15; - input fabric_data_from_bist_i16; - input fabric_data_from_bist_i17; - input fabric_data_from_bist_i18; - input fabric_data_from_bist_i19; - input fabric_data_from_bist_i2; - input fabric_data_from_bist_i20; - input fabric_data_from_bist_i21; - input fabric_data_from_bist_i22; - input fabric_data_from_bist_i23; - input fabric_data_from_bist_i24; - input fabric_data_from_bist_i3; - input fabric_data_from_bist_i4; - input fabric_data_from_bist_i5; - input fabric_data_from_bist_i6; - input fabric_data_from_bist_i7; - input fabric_data_from_bist_i8; - input fabric_data_from_bist_i9; - input fabric_data_from_system_i; - input fabric_data_shift_en_i; - output fabric_data_to_bist_o1; - output fabric_data_to_bist_o10; - output fabric_data_to_bist_o11; - output fabric_data_to_bist_o12; - output fabric_data_to_bist_o13; - output fabric_data_to_bist_o14; - output fabric_data_to_bist_o15; - output fabric_data_to_bist_o16; - output fabric_data_to_bist_o17; - output fabric_data_to_bist_o18; - output fabric_data_to_bist_o19; - output fabric_data_to_bist_o2; - output fabric_data_to_bist_o20; - output fabric_data_to_bist_o21; - output fabric_data_to_bist_o22; - output fabric_data_to_bist_o23; - output fabric_data_to_bist_o24; - output fabric_data_to_bist_o3; - output fabric_data_to_bist_o4; - output fabric_data_to_bist_o5; - output fabric_data_to_bist_o6; - output fabric_data_to_bist_o7; - output fabric_data_to_bist_o8; - output fabric_data_to_bist_o9; - output fabric_data_to_system_o; - output fabric_debug_access_reg_data_ready_o; - output fabric_debug_bsec_core_status_o1; - output fabric_debug_bsec_core_status_o10; - output fabric_debug_bsec_core_status_o11; - output fabric_debug_bsec_core_status_o12; - output fabric_debug_bsec_core_status_o13; - output fabric_debug_bsec_core_status_o14; - output fabric_debug_bsec_core_status_o15; - output fabric_debug_bsec_core_status_o16; - output fabric_debug_bsec_core_status_o17; - output fabric_debug_bsec_core_status_o18; - output fabric_debug_bsec_core_status_o19; - output fabric_debug_bsec_core_status_o2; - output fabric_debug_bsec_core_status_o20; - output fabric_debug_bsec_core_status_o21; - output fabric_debug_bsec_core_status_o22; - output fabric_debug_bsec_core_status_o23; - output fabric_debug_bsec_core_status_o24; - output fabric_debug_bsec_core_status_o25; - output fabric_debug_bsec_core_status_o26; - output fabric_debug_bsec_core_status_o27; - output fabric_debug_bsec_core_status_o28; - output fabric_debug_bsec_core_status_o29; - output fabric_debug_bsec_core_status_o3; - output fabric_debug_bsec_core_status_o30; - output fabric_debug_bsec_core_status_o31; - output fabric_debug_bsec_core_status_o32; - output fabric_debug_bsec_core_status_o4; - output fabric_debug_bsec_core_status_o5; - output fabric_debug_bsec_core_status_o6; - output fabric_debug_bsec_core_status_o7; - output fabric_debug_bsec_core_status_o8; - output fabric_debug_bsec_core_status_o9; - output fabric_debug_cpt_retry_o1; - output fabric_debug_cpt_retry_o2; - output fabric_debug_cpt_retry_o3; - output fabric_debug_cpt_retry_o4; - output fabric_debug_direct_permission_read_o1; - output fabric_debug_direct_permission_read_o2; - output fabric_debug_direct_permission_read_o3; - output fabric_debug_direct_permission_read_o4; - output fabric_debug_direct_permission_write_o1; - output fabric_debug_direct_permission_write_o2; - output fabric_debug_direct_permission_write_o3; - output fabric_debug_direct_permission_write_o4; - output fabric_debug_error_o; - output fabric_debug_frame_permission_frame_o1; - output fabric_debug_frame_permission_frame_o2; - output fabric_debug_frame_permission_frame_o3; - output fabric_debug_frame_permission_frame_o4; - output fabric_debug_frame_use_encryption_o; - output fabric_debug_fsm_state_o1; - output fabric_debug_fsm_state_o2; - output fabric_debug_fsm_state_o3; - output fabric_debug_key_correct_o; - output fabric_debug_lifecycle_o1; - output fabric_debug_lifecycle_o2; - output fabric_debug_lifecycle_o3; - output fabric_debug_lifecycle_o4; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output fabric_debug_otpapb_state_o1; - output fabric_debug_otpapb_state_o2; - output fabric_debug_otpapb_state_o3; - output fabric_debug_otpboot_curr_addr_o1; - output fabric_debug_otpboot_curr_addr_o2; - output fabric_debug_otpboot_curr_addr_o3; - output fabric_debug_otpboot_curr_addr_o4; - output fabric_debug_otpboot_curr_addr_o5; - output fabric_debug_otpboot_curr_addr_o6; - output fabric_debug_otpboot_curr_addr_o7; - output fabric_debug_otpboot_curr_addr_o8; - output fabric_debug_otpboot_state_o1; - output fabric_debug_otpboot_state_o2; - output fabric_debug_otpboot_state_o3; - output fabric_debug_otpmgmt_state_o1; - output fabric_debug_otpmgmt_state_o2; - output fabric_debug_otpmgmt_state_o3; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - output fabric_decoder_init_ready_o; - input fabric_direct_data_i1; - input fabric_direct_data_i10; - input fabric_direct_data_i11; - input fabric_direct_data_i12; - input fabric_direct_data_i13; - input fabric_direct_data_i14; - input fabric_direct_data_i15; - input fabric_direct_data_i16; - input fabric_direct_data_i17; - input fabric_direct_data_i18; - input fabric_direct_data_i19; - input fabric_direct_data_i2; - input fabric_direct_data_i20; - input fabric_direct_data_i21; - input fabric_direct_data_i22; - input fabric_direct_data_i23; - input fabric_direct_data_i24; - input fabric_direct_data_i25; - input fabric_direct_data_i26; - input fabric_direct_data_i27; - input fabric_direct_data_i28; - input fabric_direct_data_i29; - input fabric_direct_data_i3; - input fabric_direct_data_i30; - input fabric_direct_data_i31; - input fabric_direct_data_i32; - input fabric_direct_data_i4; - input fabric_direct_data_i5; - input fabric_direct_data_i6; - input fabric_direct_data_i7; - input fabric_direct_data_i8; - input fabric_direct_data_i9; - output fabric_direct_data_o1; - output fabric_direct_data_o10; - output fabric_direct_data_o11; - output fabric_direct_data_o12; - output fabric_direct_data_o13; - output fabric_direct_data_o14; - output fabric_direct_data_o15; - output fabric_direct_data_o16; - output fabric_direct_data_o17; - output fabric_direct_data_o18; - output fabric_direct_data_o19; - output fabric_direct_data_o2; - output fabric_direct_data_o20; - output fabric_direct_data_o21; - output fabric_direct_data_o22; - output fabric_direct_data_o23; - output fabric_direct_data_o24; - output fabric_direct_data_o25; - output fabric_direct_data_o26; - output fabric_direct_data_o27; - output fabric_direct_data_o28; - output fabric_direct_data_o29; - output fabric_direct_data_o3; - output fabric_direct_data_o30; - output fabric_direct_data_o31; - output fabric_direct_data_o32; - output fabric_direct_data_o4; - output fabric_direct_data_o5; - output fabric_direct_data_o6; - output fabric_direct_data_o7; - output fabric_direct_data_o8; - output fabric_direct_data_o9; - input fabric_end_encoding_i; - output fabric_flag_error_o; - output fabric_flag_ready_TMR_o1; - output fabric_flag_ready_TMR_o2; - output fabric_flag_ready_TMR_o3; - output fabric_flag_trigger_o; - output fabric_fuse_status_o1; - output fabric_fuse_status_o2; - output fabric_fuse_status_o3; - output fabric_global_chip_status_o1; - output fabric_global_chip_status_o2; - output fabric_global_chip_status_o3; - input fabric_io_in_i1; - input fabric_io_in_i10; - input fabric_io_in_i11; - input fabric_io_in_i12; - input fabric_io_in_i13; - input fabric_io_in_i14; - input fabric_io_in_i15; - input fabric_io_in_i16; - input fabric_io_in_i17; - input fabric_io_in_i18; - input fabric_io_in_i19; - input fabric_io_in_i2; - input fabric_io_in_i20; - input fabric_io_in_i21; - input fabric_io_in_i22; - input fabric_io_in_i23; - input fabric_io_in_i24; - input fabric_io_in_i25; - input fabric_io_in_i3; - input fabric_io_in_i4; - input fabric_io_in_i5; - input fabric_io_in_i6; - input fabric_io_in_i7; - input fabric_io_in_i8; - input fabric_io_in_i9; - input fabric_io_oe_i1; - input fabric_io_oe_i10; - input fabric_io_oe_i11; - input fabric_io_oe_i12; - input fabric_io_oe_i13; - input fabric_io_oe_i14; - input fabric_io_oe_i15; - input fabric_io_oe_i16; - input fabric_io_oe_i17; - input fabric_io_oe_i18; - input fabric_io_oe_i19; - input fabric_io_oe_i2; - input fabric_io_oe_i20; - input fabric_io_oe_i21; - input fabric_io_oe_i22; - input fabric_io_oe_i23; - input fabric_io_oe_i24; - input fabric_io_oe_i25; - input fabric_io_oe_i3; - input fabric_io_oe_i4; - input fabric_io_oe_i5; - input fabric_io_oe_i6; - input fabric_io_oe_i7; - input fabric_io_oe_i8; - input fabric_io_oe_i9; - output fabric_io_out_o1; - output fabric_io_out_o10; - output fabric_io_out_o11; - output fabric_io_out_o12; - output fabric_io_out_o13; - output fabric_io_out_o14; - output fabric_io_out_o15; - output fabric_io_out_o16; - output fabric_io_out_o17; - output fabric_io_out_o18; - output fabric_io_out_o19; - output fabric_io_out_o2; - output fabric_io_out_o20; - output fabric_io_out_o21; - output fabric_io_out_o22; - output fabric_io_out_o23; - output fabric_io_out_o24; - output fabric_io_out_o25; - output fabric_io_out_o3; - output fabric_io_out_o4; - output fabric_io_out_o5; - output fabric_io_out_o6; - output fabric_io_out_o7; - output fabric_io_out_o8; - output fabric_io_out_o9; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - input fabric_mrepair_cke_force_i; - input fabric_mrepair_cke_i; - output fabric_mrepair_fuse_ack_o; - input fabric_mrepair_fuse_add_i1; - input fabric_mrepair_fuse_add_i2; - input fabric_mrepair_fuse_add_i3; - input fabric_mrepair_fuse_add_i4; - input fabric_mrepair_fuse_add_i5; - input fabric_mrepair_fuse_add_i6; - input fabric_mrepair_fuse_add_i7; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output fabric_mrepair_fuse_bist1fail_o1; - output fabric_mrepair_fuse_bist1fail_o2; - output fabric_mrepair_fuse_bist1fail_o3; - output fabric_mrepair_fuse_bist1fail_o4; - output fabric_mrepair_fuse_bist1fail_o5; - output fabric_mrepair_fuse_bist1fail_o6; - output fabric_mrepair_fuse_bist1fail_o7; - output fabric_mrepair_fuse_bist1fail_o8; - output fabric_mrepair_fuse_bist2fail_o1; - output fabric_mrepair_fuse_bist2fail_o2; - output fabric_mrepair_fuse_bist2fail_o3; - output fabric_mrepair_fuse_bist2fail_o4; - output fabric_mrepair_fuse_bist2fail_o5; - output fabric_mrepair_fuse_bist2fail_o6; - output fabric_mrepair_fuse_bist2fail_o7; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - output fabric_mrepair_fuse_ded_o; - input fabric_mrepair_fuse_din_i1; - input fabric_mrepair_fuse_din_i10; - input fabric_mrepair_fuse_din_i11; - input fabric_mrepair_fuse_din_i12; - input fabric_mrepair_fuse_din_i13; - input fabric_mrepair_fuse_din_i14; - input fabric_mrepair_fuse_din_i15; - input fabric_mrepair_fuse_din_i16; - input fabric_mrepair_fuse_din_i17; - input fabric_mrepair_fuse_din_i18; - input fabric_mrepair_fuse_din_i19; - input fabric_mrepair_fuse_din_i2; - input fabric_mrepair_fuse_din_i20; - input fabric_mrepair_fuse_din_i21; - input fabric_mrepair_fuse_din_i22; - input fabric_mrepair_fuse_din_i23; - input fabric_mrepair_fuse_din_i24; - input fabric_mrepair_fuse_din_i25; - input fabric_mrepair_fuse_din_i26; - input fabric_mrepair_fuse_din_i27; - input fabric_mrepair_fuse_din_i28; - input fabric_mrepair_fuse_din_i29; - input fabric_mrepair_fuse_din_i3; - input fabric_mrepair_fuse_din_i30; - input fabric_mrepair_fuse_din_i31; - input fabric_mrepair_fuse_din_i32; - input fabric_mrepair_fuse_din_i33; - input fabric_mrepair_fuse_din_i34; - input fabric_mrepair_fuse_din_i35; - input fabric_mrepair_fuse_din_i36; - input fabric_mrepair_fuse_din_i37; - input fabric_mrepair_fuse_din_i38; - input fabric_mrepair_fuse_din_i39; - input fabric_mrepair_fuse_din_i4; - input fabric_mrepair_fuse_din_i5; - input fabric_mrepair_fuse_din_i6; - input fabric_mrepair_fuse_din_i7; - input fabric_mrepair_fuse_din_i8; - input fabric_mrepair_fuse_din_i9; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output fabric_mrepair_fuse_dout_o1; - output fabric_mrepair_fuse_dout_o10; - output fabric_mrepair_fuse_dout_o11; - output fabric_mrepair_fuse_dout_o12; - output fabric_mrepair_fuse_dout_o13; - output fabric_mrepair_fuse_dout_o14; - output fabric_mrepair_fuse_dout_o15; - output fabric_mrepair_fuse_dout_o16; - output fabric_mrepair_fuse_dout_o17; - output fabric_mrepair_fuse_dout_o18; - output fabric_mrepair_fuse_dout_o19; - output fabric_mrepair_fuse_dout_o2; - output fabric_mrepair_fuse_dout_o20; - output fabric_mrepair_fuse_dout_o21; - output fabric_mrepair_fuse_dout_o22; - output fabric_mrepair_fuse_dout_o23; - output fabric_mrepair_fuse_dout_o24; - output fabric_mrepair_fuse_dout_o25; - output fabric_mrepair_fuse_dout_o26; - output fabric_mrepair_fuse_dout_o27; - output fabric_mrepair_fuse_dout_o28; - output fabric_mrepair_fuse_dout_o29; - output fabric_mrepair_fuse_dout_o3; - output fabric_mrepair_fuse_dout_o30; - output fabric_mrepair_fuse_dout_o31; - output fabric_mrepair_fuse_dout_o32; - output fabric_mrepair_fuse_dout_o33; - output fabric_mrepair_fuse_dout_o34; - output fabric_mrepair_fuse_dout_o35; - output fabric_mrepair_fuse_dout_o36; - output fabric_mrepair_fuse_dout_o37; - output fabric_mrepair_fuse_dout_o38; - output fabric_mrepair_fuse_dout_o39; - output fabric_mrepair_fuse_dout_o4; - output fabric_mrepair_fuse_dout_o40; - output fabric_mrepair_fuse_dout_o41; - output fabric_mrepair_fuse_dout_o5; - output fabric_mrepair_fuse_dout_o6; - output fabric_mrepair_fuse_dout_o7; - output fabric_mrepair_fuse_dout_o8; - output fabric_mrepair_fuse_dout_o9; - input fabric_mrepair_fuse_eccbypass_i; - output fabric_mrepair_fuse_flagstate_o1; - output fabric_mrepair_fuse_flagstate_o2; - output fabric_mrepair_fuse_flagstate_o3; - output fabric_mrepair_fuse_flagstate_o4; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input fabric_mrepair_fuse_prgwidth_i1; - input fabric_mrepair_fuse_prgwidth_i2; - input fabric_mrepair_fuse_prgwidth_i3; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output fabric_mrepair_fuse_startword_o1; - output fabric_mrepair_fuse_startword_o10; - output fabric_mrepair_fuse_startword_o11; - output fabric_mrepair_fuse_startword_o12; - output fabric_mrepair_fuse_startword_o13; - output fabric_mrepair_fuse_startword_o14; - output fabric_mrepair_fuse_startword_o15; - output fabric_mrepair_fuse_startword_o16; - output fabric_mrepair_fuse_startword_o2; - output fabric_mrepair_fuse_startword_o3; - output fabric_mrepair_fuse_startword_o4; - output fabric_mrepair_fuse_startword_o5; - output fabric_mrepair_fuse_startword_o6; - output fabric_mrepair_fuse_startword_o7; - output fabric_mrepair_fuse_startword_o8; - output fabric_mrepair_fuse_startword_o9; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input fabric_mrepair_fuse_tst_scanin_i1; - input fabric_mrepair_fuse_tst_scanin_i2; - input fabric_mrepair_fuse_tst_scanin_i3; - input fabric_mrepair_fuse_tst_scanin_i4; - input fabric_mrepair_fuse_tst_scanin_i5; - input fabric_mrepair_fuse_tstscanenable_i; - output fabric_mrepair_fuse_tstscanout_o1; - output fabric_mrepair_fuse_tstscanout_o2; - output fabric_mrepair_fuse_tstscanout_o3; - output fabric_mrepair_fuse_tstscanout_o4; - output fabric_mrepair_fuse_tstscanout_o5; - output fabric_mrepair_fuse_wlromout_o1; - output fabric_mrepair_fuse_wlromout_o10; - output fabric_mrepair_fuse_wlromout_o2; - output fabric_mrepair_fuse_wlromout_o3; - output fabric_mrepair_fuse_wlromout_o4; - output fabric_mrepair_fuse_wlromout_o5; - output fabric_mrepair_fuse_wlromout_o6; - output fabric_mrepair_fuse_wlromout_o7; - output fabric_mrepair_fuse_wlromout_o8; - output fabric_mrepair_fuse_wlromout_o9; - input fabric_mrepair_fuse_wordlock_i; - input fabric_mrepair_initn_i; - input fabric_mrepair_mode_i1; - input fabric_mrepair_mode_i2; - input fabric_mrepair_mode_i3; - input fabric_mrepair_mode_i4; - input fabric_mrepair_por_i; - input fabric_mrepair_rst_n_i; - input fabric_otp_apb_addr_i1; - input fabric_otp_apb_addr_i10; - input fabric_otp_apb_addr_i11; - input fabric_otp_apb_addr_i12; - input fabric_otp_apb_addr_i13; - input fabric_otp_apb_addr_i14; - input fabric_otp_apb_addr_i15; - input fabric_otp_apb_addr_i16; - input fabric_otp_apb_addr_i17; - input fabric_otp_apb_addr_i18; - input fabric_otp_apb_addr_i19; - input fabric_otp_apb_addr_i2; - input fabric_otp_apb_addr_i20; - input fabric_otp_apb_addr_i21; - input fabric_otp_apb_addr_i22; - input fabric_otp_apb_addr_i23; - input fabric_otp_apb_addr_i24; - input fabric_otp_apb_addr_i25; - input fabric_otp_apb_addr_i26; - input fabric_otp_apb_addr_i27; - input fabric_otp_apb_addr_i28; - input fabric_otp_apb_addr_i29; - input fabric_otp_apb_addr_i3; - input fabric_otp_apb_addr_i30; - input fabric_otp_apb_addr_i31; - input fabric_otp_apb_addr_i32; - input fabric_otp_apb_addr_i4; - input fabric_otp_apb_addr_i5; - input fabric_otp_apb_addr_i6; - input fabric_otp_apb_addr_i7; - input fabric_otp_apb_addr_i8; - input fabric_otp_apb_addr_i9; - input fabric_otp_apb_enable_i; - output fabric_otp_apb_rdata_o1; - output fabric_otp_apb_rdata_o10; - output fabric_otp_apb_rdata_o11; - output fabric_otp_apb_rdata_o12; - output fabric_otp_apb_rdata_o13; - output fabric_otp_apb_rdata_o14; - output fabric_otp_apb_rdata_o15; - output fabric_otp_apb_rdata_o16; - output fabric_otp_apb_rdata_o17; - output fabric_otp_apb_rdata_o18; - output fabric_otp_apb_rdata_o19; - output fabric_otp_apb_rdata_o2; - output fabric_otp_apb_rdata_o20; - output fabric_otp_apb_rdata_o21; - output fabric_otp_apb_rdata_o22; - output fabric_otp_apb_rdata_o23; - output fabric_otp_apb_rdata_o24; - output fabric_otp_apb_rdata_o25; - output fabric_otp_apb_rdata_o26; - output fabric_otp_apb_rdata_o27; - output fabric_otp_apb_rdata_o28; - output fabric_otp_apb_rdata_o29; - output fabric_otp_apb_rdata_o3; - output fabric_otp_apb_rdata_o30; - output fabric_otp_apb_rdata_o31; - output fabric_otp_apb_rdata_o32; - output fabric_otp_apb_rdata_o4; - output fabric_otp_apb_rdata_o5; - output fabric_otp_apb_rdata_o6; - output fabric_otp_apb_rdata_o7; - output fabric_otp_apb_rdata_o8; - output fabric_otp_apb_rdata_o9; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input fabric_otp_apb_wdata_i1; - input fabric_otp_apb_wdata_i10; - input fabric_otp_apb_wdata_i11; - input fabric_otp_apb_wdata_i12; - input fabric_otp_apb_wdata_i13; - input fabric_otp_apb_wdata_i14; - input fabric_otp_apb_wdata_i15; - input fabric_otp_apb_wdata_i16; - input fabric_otp_apb_wdata_i17; - input fabric_otp_apb_wdata_i18; - input fabric_otp_apb_wdata_i19; - input fabric_otp_apb_wdata_i2; - input fabric_otp_apb_wdata_i20; - input fabric_otp_apb_wdata_i21; - input fabric_otp_apb_wdata_i22; - input fabric_otp_apb_wdata_i23; - input fabric_otp_apb_wdata_i24; - input fabric_otp_apb_wdata_i25; - input fabric_otp_apb_wdata_i26; - input fabric_otp_apb_wdata_i27; - input fabric_otp_apb_wdata_i28; - input fabric_otp_apb_wdata_i29; - input fabric_otp_apb_wdata_i3; - input fabric_otp_apb_wdata_i30; - input fabric_otp_apb_wdata_i31; - input fabric_otp_apb_wdata_i32; - input fabric_otp_apb_wdata_i4; - input fabric_otp_apb_wdata_i5; - input fabric_otp_apb_wdata_i6; - input fabric_otp_apb_wdata_i7; - input fabric_otp_apb_wdata_i8; - input fabric_otp_apb_wdata_i9; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_rst_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output fabric_otp_security_bist_fail1_o1; - output fabric_otp_security_bist_fail1_o2; - output fabric_otp_security_bist_fail1_o3; - output fabric_otp_security_bist_fail1_o4; - output fabric_otp_security_bist_fail1_o5; - output fabric_otp_security_bist_fail1_o6; - output fabric_otp_security_bist_fail1_o7; - output fabric_otp_security_bist_fail1_o8; - output fabric_otp_security_bist_fail2_o1; - output fabric_otp_security_bist_fail2_o2; - output fabric_otp_security_bist_fail2_o3; - output fabric_otp_security_bist_fail2_o4; - output fabric_otp_security_bist_fail2_o5; - output fabric_otp_security_bist_fail2_o6; - output fabric_otp_security_bist_fail2_o7; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input fabric_otp_security_scanin_i1; - input fabric_otp_security_scanin_i2; - input fabric_otp_security_scanin_i3; - input fabric_otp_security_scanin_i4; - input fabric_otp_security_scanin_i5; - output fabric_otp_security_scanout_o1; - output fabric_otp_security_scanout_o2; - output fabric_otp_security_scanout_o3; - output fabric_otp_security_scanout_o4; - output fabric_otp_security_scanout_o5; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input fabric_otp_user_add_i1; - input fabric_otp_user_add_i2; - input fabric_otp_user_add_i3; - input fabric_otp_user_add_i4; - input fabric_otp_user_add_i5; - input fabric_otp_user_add_i6; - input fabric_otp_user_add_i7; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output fabric_otp_user_bist1fail_o1; - output fabric_otp_user_bist1fail_o2; - output fabric_otp_user_bist1fail_o3; - output fabric_otp_user_bist1fail_o4; - output fabric_otp_user_bist1fail_o5; - output fabric_otp_user_bist1fail_o6; - output fabric_otp_user_bist1fail_o7; - output fabric_otp_user_bist1fail_o8; - output fabric_otp_user_bist2fail_o1; - output fabric_otp_user_bist2fail_o2; - output fabric_otp_user_bist2fail_o3; - output fabric_otp_user_bist2fail_o4; - output fabric_otp_user_bist2fail_o5; - output fabric_otp_user_bist2fail_o6; - output fabric_otp_user_bist2fail_o7; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input fabric_otp_user_din_i1; - input fabric_otp_user_din_i10; - input fabric_otp_user_din_i11; - input fabric_otp_user_din_i12; - input fabric_otp_user_din_i13; - input fabric_otp_user_din_i14; - input fabric_otp_user_din_i15; - input fabric_otp_user_din_i16; - input fabric_otp_user_din_i17; - input fabric_otp_user_din_i18; - input fabric_otp_user_din_i19; - input fabric_otp_user_din_i2; - input fabric_otp_user_din_i20; - input fabric_otp_user_din_i21; - input fabric_otp_user_din_i22; - input fabric_otp_user_din_i23; - input fabric_otp_user_din_i24; - input fabric_otp_user_din_i25; - input fabric_otp_user_din_i26; - input fabric_otp_user_din_i27; - input fabric_otp_user_din_i28; - input fabric_otp_user_din_i29; - input fabric_otp_user_din_i3; - input fabric_otp_user_din_i30; - input fabric_otp_user_din_i31; - input fabric_otp_user_din_i32; - input fabric_otp_user_din_i33; - input fabric_otp_user_din_i34; - input fabric_otp_user_din_i35; - input fabric_otp_user_din_i36; - input fabric_otp_user_din_i37; - input fabric_otp_user_din_i38; - input fabric_otp_user_din_i39; - input fabric_otp_user_din_i4; - input fabric_otp_user_din_i5; - input fabric_otp_user_din_i6; - input fabric_otp_user_din_i7; - input fabric_otp_user_din_i8; - input fabric_otp_user_din_i9; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output fabric_otp_user_dout_o1; - output fabric_otp_user_dout_o10; - output fabric_otp_user_dout_o11; - output fabric_otp_user_dout_o12; - output fabric_otp_user_dout_o13; - output fabric_otp_user_dout_o14; - output fabric_otp_user_dout_o15; - output fabric_otp_user_dout_o16; - output fabric_otp_user_dout_o17; - output fabric_otp_user_dout_o18; - output fabric_otp_user_dout_o19; - output fabric_otp_user_dout_o2; - output fabric_otp_user_dout_o20; - output fabric_otp_user_dout_o21; - output fabric_otp_user_dout_o22; - output fabric_otp_user_dout_o23; - output fabric_otp_user_dout_o24; - output fabric_otp_user_dout_o25; - output fabric_otp_user_dout_o26; - output fabric_otp_user_dout_o27; - output fabric_otp_user_dout_o28; - output fabric_otp_user_dout_o29; - output fabric_otp_user_dout_o3; - output fabric_otp_user_dout_o30; - output fabric_otp_user_dout_o31; - output fabric_otp_user_dout_o32; - output fabric_otp_user_dout_o33; - output fabric_otp_user_dout_o34; - output fabric_otp_user_dout_o35; - output fabric_otp_user_dout_o36; - output fabric_otp_user_dout_o37; - output fabric_otp_user_dout_o38; - output fabric_otp_user_dout_o39; - output fabric_otp_user_dout_o4; - output fabric_otp_user_dout_o40; - output fabric_otp_user_dout_o41; - output fabric_otp_user_dout_o5; - output fabric_otp_user_dout_o6; - output fabric_otp_user_dout_o7; - output fabric_otp_user_dout_o8; - output fabric_otp_user_dout_o9; - input fabric_otp_user_eccbypass_i; - output fabric_otp_user_flagstate_o1; - output fabric_otp_user_flagstate_o2; - output fabric_otp_user_flagstate_o3; - output fabric_otp_user_flagstate_o4; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input fabric_otp_user_prgwidth_i1; - input fabric_otp_user_prgwidth_i2; - input fabric_otp_user_prgwidth_i3; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output fabric_otp_user_startword_o1; - output fabric_otp_user_startword_o10; - output fabric_otp_user_startword_o11; - output fabric_otp_user_startword_o12; - output fabric_otp_user_startword_o13; - output fabric_otp_user_startword_o14; - output fabric_otp_user_startword_o15; - output fabric_otp_user_startword_o16; - output fabric_otp_user_startword_o2; - output fabric_otp_user_startword_o3; - output fabric_otp_user_startword_o4; - output fabric_otp_user_startword_o5; - output fabric_otp_user_startword_o6; - output fabric_otp_user_startword_o7; - output fabric_otp_user_startword_o8; - output fabric_otp_user_startword_o9; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input fabric_otp_user_tst_scanin_i1; - input fabric_otp_user_tst_scanin_i2; - input fabric_otp_user_tst_scanin_i3; - input fabric_otp_user_tst_scanin_i4; - input fabric_otp_user_tst_scanin_i5; - output fabric_otp_user_tst_scanout_o1; - output fabric_otp_user_tst_scanout_o2; - output fabric_otp_user_tst_scanout_o3; - output fabric_otp_user_tst_scanout_o4; - output fabric_otp_user_tst_scanout_o5; - output fabric_otp_user_wlromout_o1; - output fabric_otp_user_wlromout_o10; - output fabric_otp_user_wlromout_o2; - output fabric_otp_user_wlromout_o3; - output fabric_otp_user_wlromout_o4; - output fabric_otp_user_wlromout_o5; - output fabric_otp_user_wlromout_o6; - output fabric_otp_user_wlromout_o7; - output fabric_otp_user_wlromout_o8; - output fabric_otp_user_wlromout_o9; - input fabric_otp_user_wordlock_i; - input fabric_parusr_cs_i; - input fabric_parusr_data_i1; - input fabric_parusr_data_i10; - input fabric_parusr_data_i11; - input fabric_parusr_data_i12; - input fabric_parusr_data_i13; - input fabric_parusr_data_i14; - input fabric_parusr_data_i15; - input fabric_parusr_data_i16; - input fabric_parusr_data_i2; - input fabric_parusr_data_i3; - input fabric_parusr_data_i4; - input fabric_parusr_data_i5; - input fabric_parusr_data_i6; - input fabric_parusr_data_i7; - input fabric_parusr_data_i8; - input fabric_parusr_data_i9; - output fabric_parusr_data_o1; - output fabric_parusr_data_o10; - output fabric_parusr_data_o11; - output fabric_parusr_data_o12; - output fabric_parusr_data_o13; - output fabric_parusr_data_o14; - output fabric_parusr_data_o15; - output fabric_parusr_data_o16; - output fabric_parusr_data_o2; - output fabric_parusr_data_o3; - output fabric_parusr_data_o4; - output fabric_parusr_data_o5; - output fabric_parusr_data_o6; - output fabric_parusr_data_o7; - output fabric_parusr_data_o8; - output fabric_parusr_data_o9; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input fabric_parusr_type_i1; - input fabric_parusr_type_i2; - input fabric_pd_active_i1; - input fabric_pd_active_i10; - input fabric_pd_active_i11; - input fabric_pd_active_i12; - input fabric_pd_active_i13; - input fabric_pd_active_i14; - input fabric_pd_active_i15; - input fabric_pd_active_i16; - input fabric_pd_active_i17; - input fabric_pd_active_i18; - input fabric_pd_active_i19; - input fabric_pd_active_i2; - input fabric_pd_active_i20; - input fabric_pd_active_i21; - input fabric_pd_active_i22; - input fabric_pd_active_i23; - input fabric_pd_active_i24; - input fabric_pd_active_i3; - input fabric_pd_active_i4; - input fabric_pd_active_i5; - input fabric_pd_active_i6; - input fabric_pd_active_i7; - input fabric_pd_active_i8; - input fabric_pd_active_i9; - output fabric_pd_ready_o1; - output fabric_pd_ready_o10; - output fabric_pd_ready_o11; - output fabric_pd_ready_o12; - output fabric_pd_ready_o13; - output fabric_pd_ready_o14; - output fabric_pd_ready_o15; - output fabric_pd_ready_o16; - output fabric_pd_ready_o17; - output fabric_pd_ready_o18; - output fabric_pd_ready_o19; - output fabric_pd_ready_o2; - output fabric_pd_ready_o20; - output fabric_pd_ready_o21; - output fabric_pd_ready_o22; - output fabric_pd_ready_o23; - output fabric_pd_ready_o24; - output fabric_pd_ready_o3; - output fabric_pd_ready_o4; - output fabric_pd_ready_o5; - output fabric_pd_ready_o6; - output fabric_pd_ready_o7; - output fabric_pd_ready_o8; - output fabric_pd_ready_o9; - input fabric_shift_en_i1; - input fabric_shift_en_i10; - input fabric_shift_en_i11; - input fabric_shift_en_i12; - input fabric_shift_en_i13; - input fabric_shift_en_i14; - input fabric_shift_en_i15; - input fabric_shift_en_i16; - input fabric_shift_en_i17; - input fabric_shift_en_i18; - input fabric_shift_en_i19; - input fabric_shift_en_i2; - input fabric_shift_en_i20; - input fabric_shift_en_i21; - input fabric_shift_en_i22; - input fabric_shift_en_i23; - input fabric_shift_en_i24; - input fabric_shift_en_i3; - input fabric_shift_en_i4; - input fabric_shift_en_i5; - input fabric_shift_en_i6; - input fabric_shift_en_i7; - input fabric_shift_en_i8; - input fabric_shift_en_i9; - output fabric_shift_en_to_bist_o1; - output fabric_shift_en_to_bist_o10; - output fabric_shift_en_to_bist_o11; - output fabric_shift_en_to_bist_o12; - output fabric_shift_en_to_bist_o13; - output fabric_shift_en_to_bist_o14; - output fabric_shift_en_to_bist_o15; - output fabric_shift_en_to_bist_o16; - output fabric_shift_en_to_bist_o17; - output fabric_shift_en_to_bist_o18; - output fabric_shift_en_to_bist_o19; - output fabric_shift_en_to_bist_o2; - output fabric_shift_en_to_bist_o20; - output fabric_shift_en_to_bist_o21; - output fabric_shift_en_to_bist_o22; - output fabric_shift_en_to_bist_o23; - output fabric_shift_en_to_bist_o24; - output fabric_shift_en_to_bist_o3; - output fabric_shift_en_to_bist_o4; - output fabric_shift_en_to_bist_o5; - output fabric_shift_en_to_bist_o6; - output fabric_shift_en_to_bist_o7; - output fabric_shift_en_to_bist_o8; - output fabric_shift_en_to_bist_o9; - input fabric_sif_load_en_i1; - input fabric_sif_load_en_i10; - input fabric_sif_load_en_i11; - input fabric_sif_load_en_i12; - input fabric_sif_load_en_i13; - input fabric_sif_load_en_i14; - input fabric_sif_load_en_i15; - input fabric_sif_load_en_i16; - input fabric_sif_load_en_i17; - input fabric_sif_load_en_i18; - input fabric_sif_load_en_i19; - input fabric_sif_load_en_i2; - input fabric_sif_load_en_i20; - input fabric_sif_load_en_i21; - input fabric_sif_load_en_i22; - input fabric_sif_load_en_i23; - input fabric_sif_load_en_i24; - input fabric_sif_load_en_i3; - input fabric_sif_load_en_i4; - input fabric_sif_load_en_i5; - input fabric_sif_load_en_i6; - input fabric_sif_load_en_i7; - input fabric_sif_load_en_i8; - input fabric_sif_load_en_i9; - output fabric_sif_load_en_to_bist_o1; - output fabric_sif_load_en_to_bist_o10; - output fabric_sif_load_en_to_bist_o11; - output fabric_sif_load_en_to_bist_o12; - output fabric_sif_load_en_to_bist_o13; - output fabric_sif_load_en_to_bist_o14; - output fabric_sif_load_en_to_bist_o15; - output fabric_sif_load_en_to_bist_o16; - output fabric_sif_load_en_to_bist_o17; - output fabric_sif_load_en_to_bist_o18; - output fabric_sif_load_en_to_bist_o19; - output fabric_sif_load_en_to_bist_o2; - output fabric_sif_load_en_to_bist_o20; - output fabric_sif_load_en_to_bist_o21; - output fabric_sif_load_en_to_bist_o22; - output fabric_sif_load_en_to_bist_o23; - output fabric_sif_load_en_to_bist_o24; - output fabric_sif_load_en_to_bist_o3; - output fabric_sif_load_en_to_bist_o4; - output fabric_sif_load_en_to_bist_o5; - output fabric_sif_load_en_to_bist_o6; - output fabric_sif_load_en_to_bist_o7; - output fabric_sif_load_en_to_bist_o8; - output fabric_sif_load_en_to_bist_o9; - input fabric_sif_reg_en_i1; - input fabric_sif_reg_en_i10; - input fabric_sif_reg_en_i100; - input fabric_sif_reg_en_i101; - input fabric_sif_reg_en_i102; - input fabric_sif_reg_en_i103; - input fabric_sif_reg_en_i104; - input fabric_sif_reg_en_i105; - input fabric_sif_reg_en_i106; - input fabric_sif_reg_en_i107; - input fabric_sif_reg_en_i108; - input fabric_sif_reg_en_i109; - input fabric_sif_reg_en_i11; - input fabric_sif_reg_en_i110; - input fabric_sif_reg_en_i111; - input fabric_sif_reg_en_i112; - input fabric_sif_reg_en_i113; - input fabric_sif_reg_en_i114; - input fabric_sif_reg_en_i115; - input fabric_sif_reg_en_i116; - input fabric_sif_reg_en_i117; - input fabric_sif_reg_en_i118; - input fabric_sif_reg_en_i119; - input fabric_sif_reg_en_i12; - input fabric_sif_reg_en_i120; - input fabric_sif_reg_en_i13; - input fabric_sif_reg_en_i14; - input fabric_sif_reg_en_i15; - input fabric_sif_reg_en_i16; - input fabric_sif_reg_en_i17; - input fabric_sif_reg_en_i18; - input fabric_sif_reg_en_i19; - input fabric_sif_reg_en_i2; - input fabric_sif_reg_en_i20; - input fabric_sif_reg_en_i21; - input fabric_sif_reg_en_i22; - input fabric_sif_reg_en_i23; - input fabric_sif_reg_en_i24; - input fabric_sif_reg_en_i25; - input fabric_sif_reg_en_i26; - input fabric_sif_reg_en_i27; - input fabric_sif_reg_en_i28; - input fabric_sif_reg_en_i29; - input fabric_sif_reg_en_i3; - input fabric_sif_reg_en_i30; - input fabric_sif_reg_en_i31; - input fabric_sif_reg_en_i32; - input fabric_sif_reg_en_i33; - input fabric_sif_reg_en_i34; - input fabric_sif_reg_en_i35; - input fabric_sif_reg_en_i36; - input fabric_sif_reg_en_i37; - input fabric_sif_reg_en_i38; - input fabric_sif_reg_en_i39; - input fabric_sif_reg_en_i4; - input fabric_sif_reg_en_i40; - input fabric_sif_reg_en_i41; - input fabric_sif_reg_en_i42; - input fabric_sif_reg_en_i43; - input fabric_sif_reg_en_i44; - input fabric_sif_reg_en_i45; - input fabric_sif_reg_en_i46; - input fabric_sif_reg_en_i47; - input fabric_sif_reg_en_i48; - input fabric_sif_reg_en_i49; - input fabric_sif_reg_en_i5; - input fabric_sif_reg_en_i50; - input fabric_sif_reg_en_i51; - input fabric_sif_reg_en_i52; - input fabric_sif_reg_en_i53; - input fabric_sif_reg_en_i54; - input fabric_sif_reg_en_i55; - input fabric_sif_reg_en_i56; - input fabric_sif_reg_en_i57; - input fabric_sif_reg_en_i58; - input fabric_sif_reg_en_i59; - input fabric_sif_reg_en_i6; - input fabric_sif_reg_en_i60; - input fabric_sif_reg_en_i61; - input fabric_sif_reg_en_i62; - input fabric_sif_reg_en_i63; - input fabric_sif_reg_en_i64; - input fabric_sif_reg_en_i65; - input fabric_sif_reg_en_i66; - input fabric_sif_reg_en_i67; - input fabric_sif_reg_en_i68; - input fabric_sif_reg_en_i69; - input fabric_sif_reg_en_i7; - input fabric_sif_reg_en_i70; - input fabric_sif_reg_en_i71; - input fabric_sif_reg_en_i72; - input fabric_sif_reg_en_i73; - input fabric_sif_reg_en_i74; - input fabric_sif_reg_en_i75; - input fabric_sif_reg_en_i76; - input fabric_sif_reg_en_i77; - input fabric_sif_reg_en_i78; - input fabric_sif_reg_en_i79; - input fabric_sif_reg_en_i8; - input fabric_sif_reg_en_i80; - input fabric_sif_reg_en_i81; - input fabric_sif_reg_en_i82; - input fabric_sif_reg_en_i83; - input fabric_sif_reg_en_i84; - input fabric_sif_reg_en_i85; - input fabric_sif_reg_en_i86; - input fabric_sif_reg_en_i87; - input fabric_sif_reg_en_i88; - input fabric_sif_reg_en_i89; - input fabric_sif_reg_en_i9; - input fabric_sif_reg_en_i90; - input fabric_sif_reg_en_i91; - input fabric_sif_reg_en_i92; - input fabric_sif_reg_en_i93; - input fabric_sif_reg_en_i94; - input fabric_sif_reg_en_i95; - input fabric_sif_reg_en_i96; - input fabric_sif_reg_en_i97; - input fabric_sif_reg_en_i98; - input fabric_sif_reg_en_i99; - output fabric_sif_reg_en_to_bist_o1; - output fabric_sif_reg_en_to_bist_o10; - output fabric_sif_reg_en_to_bist_o100; - output fabric_sif_reg_en_to_bist_o101; - output fabric_sif_reg_en_to_bist_o102; - output fabric_sif_reg_en_to_bist_o103; - output fabric_sif_reg_en_to_bist_o104; - output fabric_sif_reg_en_to_bist_o105; - output fabric_sif_reg_en_to_bist_o106; - output fabric_sif_reg_en_to_bist_o107; - output fabric_sif_reg_en_to_bist_o108; - output fabric_sif_reg_en_to_bist_o109; - output fabric_sif_reg_en_to_bist_o11; - output fabric_sif_reg_en_to_bist_o110; - output fabric_sif_reg_en_to_bist_o111; - output fabric_sif_reg_en_to_bist_o112; - output fabric_sif_reg_en_to_bist_o113; - output fabric_sif_reg_en_to_bist_o114; - output fabric_sif_reg_en_to_bist_o115; - output fabric_sif_reg_en_to_bist_o116; - output fabric_sif_reg_en_to_bist_o117; - output fabric_sif_reg_en_to_bist_o118; - output fabric_sif_reg_en_to_bist_o119; - output fabric_sif_reg_en_to_bist_o12; - output fabric_sif_reg_en_to_bist_o120; - output fabric_sif_reg_en_to_bist_o13; - output fabric_sif_reg_en_to_bist_o14; - output fabric_sif_reg_en_to_bist_o15; - output fabric_sif_reg_en_to_bist_o16; - output fabric_sif_reg_en_to_bist_o17; - output fabric_sif_reg_en_to_bist_o18; - output fabric_sif_reg_en_to_bist_o19; - output fabric_sif_reg_en_to_bist_o2; - output fabric_sif_reg_en_to_bist_o20; - output fabric_sif_reg_en_to_bist_o21; - output fabric_sif_reg_en_to_bist_o22; - output fabric_sif_reg_en_to_bist_o23; - output fabric_sif_reg_en_to_bist_o24; - output fabric_sif_reg_en_to_bist_o25; - output fabric_sif_reg_en_to_bist_o26; - output fabric_sif_reg_en_to_bist_o27; - output fabric_sif_reg_en_to_bist_o28; - output fabric_sif_reg_en_to_bist_o29; - output fabric_sif_reg_en_to_bist_o3; - output fabric_sif_reg_en_to_bist_o30; - output fabric_sif_reg_en_to_bist_o31; - output fabric_sif_reg_en_to_bist_o32; - output fabric_sif_reg_en_to_bist_o33; - output fabric_sif_reg_en_to_bist_o34; - output fabric_sif_reg_en_to_bist_o35; - output fabric_sif_reg_en_to_bist_o36; - output fabric_sif_reg_en_to_bist_o37; - output fabric_sif_reg_en_to_bist_o38; - output fabric_sif_reg_en_to_bist_o39; - output fabric_sif_reg_en_to_bist_o4; - output fabric_sif_reg_en_to_bist_o40; - output fabric_sif_reg_en_to_bist_o41; - output fabric_sif_reg_en_to_bist_o42; - output fabric_sif_reg_en_to_bist_o43; - output fabric_sif_reg_en_to_bist_o44; - output fabric_sif_reg_en_to_bist_o45; - output fabric_sif_reg_en_to_bist_o46; - output fabric_sif_reg_en_to_bist_o47; - output fabric_sif_reg_en_to_bist_o48; - output fabric_sif_reg_en_to_bist_o49; - output fabric_sif_reg_en_to_bist_o5; - output fabric_sif_reg_en_to_bist_o50; - output fabric_sif_reg_en_to_bist_o51; - output fabric_sif_reg_en_to_bist_o52; - output fabric_sif_reg_en_to_bist_o53; - output fabric_sif_reg_en_to_bist_o54; - output fabric_sif_reg_en_to_bist_o55; - output fabric_sif_reg_en_to_bist_o56; - output fabric_sif_reg_en_to_bist_o57; - output fabric_sif_reg_en_to_bist_o58; - output fabric_sif_reg_en_to_bist_o59; - output fabric_sif_reg_en_to_bist_o6; - output fabric_sif_reg_en_to_bist_o60; - output fabric_sif_reg_en_to_bist_o61; - output fabric_sif_reg_en_to_bist_o62; - output fabric_sif_reg_en_to_bist_o63; - output fabric_sif_reg_en_to_bist_o64; - output fabric_sif_reg_en_to_bist_o65; - output fabric_sif_reg_en_to_bist_o66; - output fabric_sif_reg_en_to_bist_o67; - output fabric_sif_reg_en_to_bist_o68; - output fabric_sif_reg_en_to_bist_o69; - output fabric_sif_reg_en_to_bist_o7; - output fabric_sif_reg_en_to_bist_o70; - output fabric_sif_reg_en_to_bist_o71; - output fabric_sif_reg_en_to_bist_o72; - output fabric_sif_reg_en_to_bist_o73; - output fabric_sif_reg_en_to_bist_o74; - output fabric_sif_reg_en_to_bist_o75; - output fabric_sif_reg_en_to_bist_o76; - output fabric_sif_reg_en_to_bist_o77; - output fabric_sif_reg_en_to_bist_o78; - output fabric_sif_reg_en_to_bist_o79; - output fabric_sif_reg_en_to_bist_o8; - output fabric_sif_reg_en_to_bist_o80; - output fabric_sif_reg_en_to_bist_o81; - output fabric_sif_reg_en_to_bist_o82; - output fabric_sif_reg_en_to_bist_o83; - output fabric_sif_reg_en_to_bist_o84; - output fabric_sif_reg_en_to_bist_o85; - output fabric_sif_reg_en_to_bist_o86; - output fabric_sif_reg_en_to_bist_o87; - output fabric_sif_reg_en_to_bist_o88; - output fabric_sif_reg_en_to_bist_o89; - output fabric_sif_reg_en_to_bist_o9; - output fabric_sif_reg_en_to_bist_o90; - output fabric_sif_reg_en_to_bist_o91; - output fabric_sif_reg_en_to_bist_o92; - output fabric_sif_reg_en_to_bist_o93; - output fabric_sif_reg_en_to_bist_o94; - output fabric_sif_reg_en_to_bist_o95; - output fabric_sif_reg_en_to_bist_o96; - output fabric_sif_reg_en_to_bist_o97; - output fabric_sif_reg_en_to_bist_o98; - output fabric_sif_reg_en_to_bist_o99; - input fabric_sif_update_en_i1; - input fabric_sif_update_en_i10; - input fabric_sif_update_en_i11; - input fabric_sif_update_en_i12; - input fabric_sif_update_en_i13; - input fabric_sif_update_en_i14; - input fabric_sif_update_en_i15; - input fabric_sif_update_en_i16; - input fabric_sif_update_en_i17; - input fabric_sif_update_en_i18; - input fabric_sif_update_en_i19; - input fabric_sif_update_en_i2; - input fabric_sif_update_en_i20; - input fabric_sif_update_en_i21; - input fabric_sif_update_en_i22; - input fabric_sif_update_en_i23; - input fabric_sif_update_en_i24; - input fabric_sif_update_en_i3; - input fabric_sif_update_en_i4; - input fabric_sif_update_en_i5; - input fabric_sif_update_en_i6; - input fabric_sif_update_en_i7; - input fabric_sif_update_en_i8; - input fabric_sif_update_en_i9; - output fabric_sif_update_en_to_bist_o1; - output fabric_sif_update_en_to_bist_o10; - output fabric_sif_update_en_to_bist_o11; - output fabric_sif_update_en_to_bist_o12; - output fabric_sif_update_en_to_bist_o13; - output fabric_sif_update_en_to_bist_o14; - output fabric_sif_update_en_to_bist_o15; - output fabric_sif_update_en_to_bist_o16; - output fabric_sif_update_en_to_bist_o17; - output fabric_sif_update_en_to_bist_o18; - output fabric_sif_update_en_to_bist_o19; - output fabric_sif_update_en_to_bist_o2; - output fabric_sif_update_en_to_bist_o20; - output fabric_sif_update_en_to_bist_o21; - output fabric_sif_update_en_to_bist_o22; - output fabric_sif_update_en_to_bist_o23; - output fabric_sif_update_en_to_bist_o24; - output fabric_sif_update_en_to_bist_o3; - output fabric_sif_update_en_to_bist_o4; - output fabric_sif_update_en_to_bist_o5; - output fabric_sif_update_en_to_bist_o6; - output fabric_sif_update_en_to_bist_o7; - output fabric_sif_update_en_to_bist_o8; - output fabric_sif_update_en_to_bist_o9; - output fabric_status_cold_start_o; - output fabric_system_data_from_mem_bist_o1; - output fabric_system_data_from_mem_bist_o10; - output fabric_system_data_from_mem_bist_o11; - output fabric_system_data_from_mem_bist_o12; - output fabric_system_data_from_mem_bist_o13; - output fabric_system_data_from_mem_bist_o14; - output fabric_system_data_from_mem_bist_o15; - output fabric_system_data_from_mem_bist_o16; - output fabric_system_data_from_mem_bist_o17; - output fabric_system_data_from_mem_bist_o18; - output fabric_system_data_from_mem_bist_o19; - output fabric_system_data_from_mem_bist_o2; - output fabric_system_data_from_mem_bist_o20; - output fabric_system_data_from_mem_bist_o21; - output fabric_system_data_from_mem_bist_o22; - output fabric_system_data_from_mem_bist_o23; - output fabric_system_data_from_mem_bist_o24; - output fabric_system_data_from_mem_bist_o3; - output fabric_system_data_from_mem_bist_o4; - output fabric_system_data_from_mem_bist_o5; - output fabric_system_data_from_mem_bist_o6; - output fabric_system_data_from_mem_bist_o7; - output fabric_system_data_from_mem_bist_o8; - output fabric_system_data_from_mem_bist_o9; - input fabric_system_data_to_mem_bist_i1; - input fabric_system_data_to_mem_bist_i10; - input fabric_system_data_to_mem_bist_i11; - input fabric_system_data_to_mem_bist_i12; - input fabric_system_data_to_mem_bist_i13; - input fabric_system_data_to_mem_bist_i14; - input fabric_system_data_to_mem_bist_i15; - input fabric_system_data_to_mem_bist_i16; - input fabric_system_data_to_mem_bist_i17; - input fabric_system_data_to_mem_bist_i18; - input fabric_system_data_to_mem_bist_i19; - input fabric_system_data_to_mem_bist_i2; - input fabric_system_data_to_mem_bist_i20; - input fabric_system_data_to_mem_bist_i21; - input fabric_system_data_to_mem_bist_i22; - input fabric_system_data_to_mem_bist_i23; - input fabric_system_data_to_mem_bist_i24; - input fabric_system_data_to_mem_bist_i3; - input fabric_system_data_to_mem_bist_i4; - input fabric_system_data_to_mem_bist_i5; - input fabric_system_data_to_mem_bist_i6; - input fabric_system_data_to_mem_bist_i7; - input fabric_system_data_to_mem_bist_i8; - input fabric_system_data_to_mem_bist_i9; - output fabric_system_dataready_o; - input fabric_tst_atpg_mrepair_i; - input fabric_user_data_i1; - input fabric_user_data_i10; - input fabric_user_data_i11; - input fabric_user_data_i12; - input fabric_user_data_i13; - input fabric_user_data_i14; - input fabric_user_data_i15; - input fabric_user_data_i16; - input fabric_user_data_i17; - input fabric_user_data_i18; - input fabric_user_data_i19; - input fabric_user_data_i2; - input fabric_user_data_i20; - input fabric_user_data_i21; - input fabric_user_data_i22; - input fabric_user_data_i23; - input fabric_user_data_i24; - input fabric_user_data_i25; - input fabric_user_data_i26; - input fabric_user_data_i27; - input fabric_user_data_i28; - input fabric_user_data_i29; - input fabric_user_data_i3; - input fabric_user_data_i30; - input fabric_user_data_i31; - input fabric_user_data_i32; - input fabric_user_data_i4; - input fabric_user_data_i5; - input fabric_user_data_i6; - input fabric_user_data_i7; - input fabric_user_data_i8; - input fabric_user_data_i9; - output fabric_user_data_o1; - output fabric_user_data_o10; - output fabric_user_data_o11; - output fabric_user_data_o12; - output fabric_user_data_o13; - output fabric_user_data_o14; - output fabric_user_data_o15; - output fabric_user_data_o16; - output fabric_user_data_o17; - output fabric_user_data_o18; - output fabric_user_data_o19; - output fabric_user_data_o2; - output fabric_user_data_o20; - output fabric_user_data_o21; - output fabric_user_data_o22; - output fabric_user_data_o23; - output fabric_user_data_o24; - output fabric_user_data_o25; - output fabric_user_data_o26; - output fabric_user_data_o27; - output fabric_user_data_o28; - output fabric_user_data_o29; - output fabric_user_data_o3; - output fabric_user_data_o30; - output fabric_user_data_o31; - output fabric_user_data_o32; - output fabric_user_data_o4; - output fabric_user_data_o5; - output fabric_user_data_o6; - output fabric_user_data_o7; - output fabric_user_data_o8; - output fabric_user_data_o9; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_U_V1(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_user_din_i1, fabric_otp_user_din_i2, fabric_otp_user_din_i3, fabric_otp_user_din_i4, fabric_otp_user_din_i5, fabric_otp_user_din_i6, fabric_otp_user_din_i7, fabric_otp_user_din_i8, fabric_otp_user_din_i9, fabric_otp_user_din_i10, fabric_otp_user_din_i11, fabric_otp_user_din_i12, fabric_otp_user_din_i13, fabric_otp_user_din_i14, fabric_otp_user_din_i15, fabric_otp_user_din_i16, fabric_otp_user_din_i17 -, fabric_otp_user_din_i18, fabric_otp_user_din_i19, fabric_otp_user_din_i20, fabric_otp_user_din_i21, fabric_otp_user_din_i22, fabric_otp_user_din_i23, fabric_otp_user_din_i24, fabric_otp_user_din_i25, fabric_otp_user_din_i26, fabric_otp_user_din_i27, fabric_otp_user_din_i28, fabric_otp_user_din_i29, fabric_otp_user_din_i30, fabric_otp_user_din_i31, fabric_otp_user_din_i32, fabric_otp_user_din_i33, fabric_otp_user_din_i34, fabric_otp_user_din_i35, fabric_otp_user_din_i36, fabric_otp_user_din_i37, fabric_otp_user_din_i38 -, fabric_otp_user_din_i39, fabric_mrepair_fuse_prgwidth_i1, fabric_mrepair_fuse_prgwidth_i2, fabric_mrepair_fuse_prgwidth_i3, fabric_otp_apb_wdata_i1, fabric_otp_apb_wdata_i2, fabric_otp_apb_wdata_i3, fabric_otp_apb_wdata_i4, fabric_otp_apb_wdata_i5, fabric_otp_apb_wdata_i6, fabric_otp_apb_wdata_i7, fabric_otp_apb_wdata_i8, fabric_otp_apb_wdata_i9, fabric_otp_apb_wdata_i10, fabric_otp_apb_wdata_i11, fabric_otp_apb_wdata_i12, fabric_otp_apb_wdata_i13, fabric_otp_apb_wdata_i14, fabric_otp_apb_wdata_i15, fabric_otp_apb_wdata_i16, fabric_otp_apb_wdata_i17 -, fabric_otp_apb_wdata_i18, fabric_otp_apb_wdata_i19, fabric_otp_apb_wdata_i20, fabric_otp_apb_wdata_i21, fabric_otp_apb_wdata_i22, fabric_otp_apb_wdata_i23, fabric_otp_apb_wdata_i24, fabric_otp_apb_wdata_i25, fabric_otp_apb_wdata_i26, fabric_otp_apb_wdata_i27, fabric_otp_apb_wdata_i28, fabric_otp_apb_wdata_i29, fabric_otp_apb_wdata_i30, fabric_otp_apb_wdata_i31, fabric_otp_apb_wdata_i32, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i -, fabric_otp_user_add_i1, fabric_otp_user_add_i2, fabric_otp_user_add_i3, fabric_otp_user_add_i4, fabric_otp_user_add_i5, fabric_otp_user_add_i6, fabric_otp_user_add_i7, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_tst_scanin_i1, fabric_mrepair_fuse_tst_scanin_i2, fabric_mrepair_fuse_tst_scanin_i3, fabric_mrepair_fuse_tst_scanin_i4, fabric_mrepair_fuse_tst_scanin_i5, fabric_parusr_type_i1, fabric_parusr_type_i2, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i -, fabric_mrepair_mode_i1, fabric_mrepair_mode_i2, fabric_mrepair_mode_i3, fabric_mrepair_mode_i4, fabric_parusr_cs_i, fabric_sif_reg_en_i1, fabric_sif_reg_en_i2, fabric_sif_reg_en_i3, fabric_sif_reg_en_i4, fabric_sif_reg_en_i5, fabric_sif_reg_en_i6, fabric_sif_reg_en_i7, fabric_sif_reg_en_i8, fabric_sif_reg_en_i9, fabric_sif_reg_en_i10, fabric_sif_reg_en_i11, fabric_sif_reg_en_i12, fabric_sif_reg_en_i13, fabric_sif_reg_en_i14, fabric_sif_reg_en_i15, fabric_sif_reg_en_i16 -, fabric_sif_reg_en_i17, fabric_sif_reg_en_i18, fabric_sif_reg_en_i19, fabric_sif_reg_en_i20, fabric_sif_reg_en_i21, fabric_sif_reg_en_i22, fabric_sif_reg_en_i23, fabric_sif_reg_en_i24, fabric_sif_reg_en_i25, fabric_sif_reg_en_i26, fabric_sif_reg_en_i27, fabric_sif_reg_en_i28, fabric_sif_reg_en_i29, fabric_sif_reg_en_i30, fabric_sif_reg_en_i31, fabric_sif_reg_en_i32, fabric_sif_reg_en_i33, fabric_sif_reg_en_i34, fabric_sif_reg_en_i35, fabric_sif_reg_en_i36, fabric_sif_reg_en_i37 -, fabric_sif_reg_en_i38, fabric_sif_reg_en_i39, fabric_sif_reg_en_i40, fabric_sif_reg_en_i41, fabric_sif_reg_en_i42, fabric_sif_reg_en_i43, fabric_sif_reg_en_i44, fabric_sif_reg_en_i45, fabric_sif_reg_en_i46, fabric_sif_reg_en_i47, fabric_sif_reg_en_i48, fabric_sif_reg_en_i49, fabric_sif_reg_en_i50, fabric_sif_reg_en_i51, fabric_sif_reg_en_i52, fabric_sif_reg_en_i53, fabric_sif_reg_en_i54, fabric_sif_reg_en_i55, fabric_sif_reg_en_i56, fabric_sif_reg_en_i57, fabric_sif_reg_en_i58 -, fabric_sif_reg_en_i59, fabric_sif_reg_en_i60, fabric_sif_reg_en_i61, fabric_sif_reg_en_i62, fabric_sif_reg_en_i63, fabric_sif_reg_en_i64, fabric_sif_reg_en_i65, fabric_sif_reg_en_i66, fabric_sif_reg_en_i67, fabric_sif_reg_en_i68, fabric_sif_reg_en_i69, fabric_sif_reg_en_i70, fabric_sif_reg_en_i71, fabric_sif_reg_en_i72, fabric_sif_reg_en_i73, fabric_sif_reg_en_i74, fabric_sif_reg_en_i75, fabric_sif_reg_en_i76, fabric_sif_reg_en_i77, fabric_sif_reg_en_i78, fabric_sif_reg_en_i79 -, fabric_sif_reg_en_i80, fabric_sif_reg_en_i81, fabric_sif_reg_en_i82, fabric_sif_reg_en_i83, fabric_sif_reg_en_i84, fabric_sif_reg_en_i85, fabric_sif_reg_en_i86, fabric_sif_reg_en_i87, fabric_sif_reg_en_i88, fabric_sif_reg_en_i89, fabric_sif_reg_en_i90, fabric_sif_reg_en_i91, fabric_sif_reg_en_i92, fabric_sif_reg_en_i93, fabric_sif_reg_en_i94, fabric_sif_reg_en_i95, fabric_sif_reg_en_i96, fabric_sif_reg_en_i97, fabric_sif_reg_en_i98, fabric_sif_reg_en_i99, fabric_sif_reg_en_i100 -, fabric_sif_reg_en_i101, fabric_sif_reg_en_i102, fabric_sif_reg_en_i103, fabric_sif_reg_en_i104, fabric_sif_reg_en_i105, fabric_sif_reg_en_i106, fabric_sif_reg_en_i107, fabric_sif_reg_en_i108, fabric_sif_reg_en_i109, fabric_sif_reg_en_i110, fabric_sif_reg_en_i111, fabric_sif_reg_en_i112, fabric_sif_reg_en_i113, fabric_sif_reg_en_i114, fabric_sif_reg_en_i115, fabric_sif_reg_en_i116, fabric_sif_reg_en_i117, fabric_sif_reg_en_i118, fabric_sif_reg_en_i119, fabric_sif_reg_en_i120, fabric_mrepair_fuse_rbact2_i -, fabric_data_from_system_i, fabric_data_from_bist_i1, fabric_data_from_bist_i2, fabric_data_from_bist_i3, fabric_data_from_bist_i4, fabric_data_from_bist_i5, fabric_data_from_bist_i6, fabric_data_from_bist_i7, fabric_data_from_bist_i8, fabric_data_from_bist_i9, fabric_data_from_bist_i10, fabric_data_from_bist_i11, fabric_data_from_bist_i12, fabric_data_from_bist_i13, fabric_data_from_bist_i14, fabric_data_from_bist_i15, fabric_data_from_bist_i16, fabric_data_from_bist_i17, fabric_data_from_bist_i18, fabric_data_from_bist_i19, fabric_data_from_bist_i20 -, fabric_data_from_bist_i21, fabric_data_from_bist_i22, fabric_data_from_bist_i23, fabric_data_from_bist_i24, fabric_otp_apb_enable_i, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_shift_en_i1, fabric_shift_en_i2, fabric_shift_en_i3, fabric_shift_en_i4, fabric_shift_en_i5, fabric_shift_en_i6, fabric_shift_en_i7, fabric_shift_en_i8, fabric_shift_en_i9, fabric_shift_en_i10, fabric_shift_en_i11, fabric_shift_en_i12, fabric_shift_en_i13 -, fabric_shift_en_i14, fabric_shift_en_i15, fabric_shift_en_i16, fabric_shift_en_i17, fabric_shift_en_i18, fabric_shift_en_i19, fabric_shift_en_i20, fabric_shift_en_i21, fabric_shift_en_i22, fabric_shift_en_i23, fabric_shift_en_i24, fabric_otp_cfg_loader_write_en_i, fabric_user_data_i1, fabric_user_data_i2, fabric_user_data_i3, fabric_user_data_i4, fabric_user_data_i5, fabric_user_data_i6, fabric_user_data_i7, fabric_user_data_i8, fabric_user_data_i9 -, fabric_user_data_i10, fabric_user_data_i11, fabric_user_data_i12, fabric_user_data_i13, fabric_user_data_i14, fabric_user_data_i15, fabric_user_data_i16, fabric_user_data_i17, fabric_user_data_i18, fabric_user_data_i19, fabric_user_data_i20, fabric_user_data_i21, fabric_user_data_i22, fabric_user_data_i23, fabric_user_data_i24, fabric_user_data_i25, fabric_user_data_i26, fabric_user_data_i27, fabric_user_data_i28, fabric_user_data_i29, fabric_user_data_i30 -, fabric_user_data_i31, fabric_user_data_i32, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_ahb_direct_data_i1, fabric_ahb_direct_data_i2, fabric_ahb_direct_data_i3, fabric_ahb_direct_data_i4, fabric_ahb_direct_data_i5, fabric_ahb_direct_data_i6, fabric_ahb_direct_data_i7, fabric_ahb_direct_data_i8, fabric_ahb_direct_data_i9, fabric_ahb_direct_data_i10, fabric_ahb_direct_data_i11, fabric_ahb_direct_data_i12, fabric_ahb_direct_data_i13, fabric_ahb_direct_data_i14, fabric_ahb_direct_data_i15, fabric_ahb_direct_data_i16 -, fabric_ahb_direct_data_i17, fabric_ahb_direct_data_i18, fabric_ahb_direct_data_i19, fabric_ahb_direct_data_i20, fabric_ahb_direct_data_i21, fabric_ahb_direct_data_i22, fabric_ahb_direct_data_i23, fabric_ahb_direct_data_i24, fabric_ahb_direct_data_i25, fabric_ahb_direct_data_i26, fabric_ahb_direct_data_i27, fabric_ahb_direct_data_i28, fabric_ahb_direct_data_i29, fabric_ahb_direct_data_i30, fabric_ahb_direct_data_i31, fabric_ahb_direct_data_i32, fabric_otp_user_prog_i, fabric_pd_active_i1, fabric_pd_active_i2, fabric_pd_active_i3, fabric_pd_active_i4 -, fabric_pd_active_i5, fabric_pd_active_i6, fabric_pd_active_i7, fabric_pd_active_i8, fabric_pd_active_i9, fabric_pd_active_i10, fabric_pd_active_i11, fabric_pd_active_i12, fabric_pd_active_i13, fabric_pd_active_i14, fabric_pd_active_i15, fabric_pd_active_i16, fabric_pd_active_i17, fabric_pd_active_i18, fabric_pd_active_i19, fabric_pd_active_i20, fabric_pd_active_i21, fabric_pd_active_i22, fabric_pd_active_i23, fabric_pd_active_i24, fabric_otp_user_suppadd_i -, fabric_mrepair_fuse_pdn_i, fabric_otp_security_scanin_i1, fabric_otp_security_scanin_i2, fabric_otp_security_scanin_i3, fabric_otp_security_scanin_i4, fabric_otp_security_scanin_i5, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_prgwidth_i1, fabric_otp_user_prgwidth_i2, fabric_otp_user_prgwidth_i3, fabric_otp_user_read_i, fabric_mrepair_fuse_add_i1, fabric_mrepair_fuse_add_i2, fabric_mrepair_fuse_add_i3, fabric_mrepair_fuse_add_i4, fabric_mrepair_fuse_add_i5, fabric_mrepair_fuse_add_i6, fabric_mrepair_fuse_add_i7, fabric_mrepair_fuse_bistmode_i -, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_io_in_i1, fabric_io_in_i2, fabric_io_in_i3, fabric_io_in_i4, fabric_io_in_i5, fabric_io_in_i6, fabric_io_in_i7, fabric_io_in_i8, fabric_io_in_i9, fabric_io_in_i10, fabric_io_in_i11, fabric_io_in_i12, fabric_io_in_i13, fabric_io_in_i14, fabric_io_in_i15, fabric_io_in_i16, fabric_io_in_i17, fabric_io_in_i18, fabric_io_in_i19 -, fabric_io_in_i20, fabric_io_in_i21, fabric_io_in_i22, fabric_io_in_i23, fabric_io_in_i24, fabric_io_in_i25, fabric_sif_load_en_i1, fabric_sif_load_en_i2, fabric_sif_load_en_i3, fabric_sif_load_en_i4, fabric_sif_load_en_i5, fabric_sif_load_en_i6, fabric_sif_load_en_i7, fabric_sif_load_en_i8, fabric_sif_load_en_i9, fabric_sif_load_en_i10, fabric_sif_load_en_i11, fabric_sif_load_en_i12, fabric_sif_load_en_i13, fabric_sif_load_en_i14, fabric_sif_load_en_i15 -, fabric_sif_load_en_i16, fabric_sif_load_en_i17, fabric_sif_load_en_i18, fabric_sif_load_en_i19, fabric_sif_load_en_i20, fabric_sif_load_en_i21, fabric_sif_load_en_i22, fabric_sif_load_en_i23, fabric_sif_load_en_i24, fabric_mrepair_fuse_din_i1, fabric_mrepair_fuse_din_i2, fabric_mrepair_fuse_din_i3, fabric_mrepair_fuse_din_i4, fabric_mrepair_fuse_din_i5, fabric_mrepair_fuse_din_i6, fabric_mrepair_fuse_din_i7, fabric_mrepair_fuse_din_i8, fabric_mrepair_fuse_din_i9, fabric_mrepair_fuse_din_i10, fabric_mrepair_fuse_din_i11, fabric_mrepair_fuse_din_i12 -, fabric_mrepair_fuse_din_i13, fabric_mrepair_fuse_din_i14, fabric_mrepair_fuse_din_i15, fabric_mrepair_fuse_din_i16, fabric_mrepair_fuse_din_i17, fabric_mrepair_fuse_din_i18, fabric_mrepair_fuse_din_i19, fabric_mrepair_fuse_din_i20, fabric_mrepair_fuse_din_i21, fabric_mrepair_fuse_din_i22, fabric_mrepair_fuse_din_i23, fabric_mrepair_fuse_din_i24, fabric_mrepair_fuse_din_i25, fabric_mrepair_fuse_din_i26, fabric_mrepair_fuse_din_i27, fabric_mrepair_fuse_din_i28, fabric_mrepair_fuse_din_i29, fabric_mrepair_fuse_din_i30, fabric_mrepair_fuse_din_i31, fabric_mrepair_fuse_din_i32, fabric_mrepair_fuse_din_i33 -, fabric_mrepair_fuse_din_i34, fabric_mrepair_fuse_din_i35, fabric_mrepair_fuse_din_i36, fabric_mrepair_fuse_din_i37, fabric_mrepair_fuse_din_i38, fabric_mrepair_fuse_din_i39, fabric_otp_apb_addr_i1, fabric_otp_apb_addr_i2, fabric_otp_apb_addr_i3, fabric_otp_apb_addr_i4, fabric_otp_apb_addr_i5, fabric_otp_apb_addr_i6, fabric_otp_apb_addr_i7, fabric_otp_apb_addr_i8, fabric_otp_apb_addr_i9, fabric_otp_apb_addr_i10, fabric_otp_apb_addr_i11, fabric_otp_apb_addr_i12, fabric_otp_apb_addr_i13, fabric_otp_apb_addr_i14, fabric_otp_apb_addr_i15 -, fabric_otp_apb_addr_i16, fabric_otp_apb_addr_i17, fabric_otp_apb_addr_i18, fabric_otp_apb_addr_i19, fabric_otp_apb_addr_i20, fabric_otp_apb_addr_i21, fabric_otp_apb_addr_i22, fabric_otp_apb_addr_i23, fabric_otp_apb_addr_i24, fabric_otp_apb_addr_i25, fabric_otp_apb_addr_i26, fabric_otp_apb_addr_i27, fabric_otp_apb_addr_i28, fabric_otp_apb_addr_i29, fabric_otp_apb_addr_i30, fabric_otp_apb_addr_i31, fabric_otp_apb_addr_i32, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_mrepair_fuse_configreg_i1, fabric_mrepair_fuse_configreg_i2 -, fabric_mrepair_fuse_configreg_i3, fabric_mrepair_fuse_configreg_i4, fabric_mrepair_fuse_configreg_i5, fabric_mrepair_fuse_configreg_i6, fabric_mrepair_fuse_configreg_i7, fabric_mrepair_fuse_configreg_i8, fabric_mrepair_fuse_configreg_i9, fabric_mrepair_fuse_configreg_i10, fabric_mrepair_fuse_configreg_i11, fabric_mrepair_fuse_configreg_i12, fabric_mrepair_fuse_configreg_i13, fabric_mrepair_fuse_configreg_i14, fabric_mrepair_fuse_configreg_i15, fabric_mrepair_fuse_configreg_i16, fabric_mrepair_fuse_configreg_i17, fabric_mrepair_fuse_configreg_i18, fabric_mrepair_fuse_configreg_i19, fabric_mrepair_fuse_configreg_i20, fabric_mrepair_fuse_configreg_i21, fabric_mrepair_fuse_configreg_i22, fabric_mrepair_fuse_configreg_i23 -, fabric_mrepair_fuse_configreg_i24, fabric_mrepair_fuse_configreg_i25, fabric_mrepair_fuse_configreg_i26, fabric_mrepair_fuse_configreg_i27, fabric_mrepair_fuse_configreg_i28, fabric_mrepair_fuse_configreg_i29, fabric_mrepair_fuse_configreg_i30, fabric_mrepair_fuse_configreg_i31, fabric_mrepair_fuse_configreg_i32, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i, fabric_lowskew_i21, fabric_direct_data_i1, fabric_direct_data_i2, fabric_direct_data_i3, fabric_direct_data_i4, fabric_direct_data_i5, fabric_direct_data_i6, fabric_direct_data_i7, fabric_direct_data_i8, fabric_direct_data_i9 -, fabric_direct_data_i10, fabric_direct_data_i11, fabric_direct_data_i12, fabric_direct_data_i13, fabric_direct_data_i14, fabric_direct_data_i15, fabric_direct_data_i16, fabric_direct_data_i17, fabric_direct_data_i18, fabric_direct_data_i19, fabric_direct_data_i20, fabric_direct_data_i21, fabric_direct_data_i22, fabric_direct_data_i23, fabric_direct_data_i24, fabric_direct_data_i25, fabric_direct_data_i26, fabric_direct_data_i27, fabric_direct_data_i28, fabric_direct_data_i29, fabric_direct_data_i30 -, fabric_direct_data_i31, fabric_direct_data_i32, fabric_otp_user_pdn_i, fabric_io_oe_i1, fabric_io_oe_i2, fabric_io_oe_i3, fabric_io_oe_i4, fabric_io_oe_i5, fabric_io_oe_i6, fabric_io_oe_i7, fabric_io_oe_i8, fabric_io_oe_i9, fabric_io_oe_i10, fabric_io_oe_i11, fabric_io_oe_i12, fabric_io_oe_i13, fabric_io_oe_i14, fabric_io_oe_i15, fabric_io_oe_i16, fabric_io_oe_i17, fabric_io_oe_i18 -, fabric_io_oe_i19, fabric_io_oe_i20, fabric_io_oe_i21, fabric_io_oe_i22, fabric_io_oe_i23, fabric_io_oe_i24, fabric_io_oe_i25, fabric_parusr_data_i1, fabric_parusr_data_i2, fabric_parusr_data_i3, fabric_parusr_data_i4, fabric_parusr_data_i5, fabric_parusr_data_i6, fabric_parusr_data_i7, fabric_parusr_data_i8, fabric_parusr_data_i9, fabric_parusr_data_i10, fabric_parusr_data_i11, fabric_parusr_data_i12, fabric_parusr_data_i13, fabric_parusr_data_i14 -, fabric_parusr_data_i15, fabric_parusr_data_i16, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_system_data_to_mem_bist_i1, fabric_system_data_to_mem_bist_i2, fabric_system_data_to_mem_bist_i3, fabric_system_data_to_mem_bist_i4, fabric_system_data_to_mem_bist_i5, fabric_system_data_to_mem_bist_i6, fabric_system_data_to_mem_bist_i7, fabric_system_data_to_mem_bist_i8, fabric_system_data_to_mem_bist_i9, fabric_system_data_to_mem_bist_i10, fabric_system_data_to_mem_bist_i11, fabric_system_data_to_mem_bist_i12, fabric_system_data_to_mem_bist_i13, fabric_system_data_to_mem_bist_i14, fabric_system_data_to_mem_bist_i15, fabric_system_data_to_mem_bist_i16, fabric_system_data_to_mem_bist_i17 -, fabric_system_data_to_mem_bist_i18, fabric_system_data_to_mem_bist_i19, fabric_system_data_to_mem_bist_i20, fabric_system_data_to_mem_bist_i21, fabric_system_data_to_mem_bist_i22, fabric_system_data_to_mem_bist_i23, fabric_system_data_to_mem_bist_i24, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_otp_user_configreg_i1, fabric_otp_user_configreg_i2, fabric_otp_user_configreg_i3, fabric_otp_user_configreg_i4, fabric_otp_user_configreg_i5, fabric_otp_user_configreg_i6, fabric_otp_user_configreg_i7, fabric_otp_user_configreg_i8 -, fabric_otp_user_configreg_i9, fabric_otp_user_configreg_i10, fabric_otp_user_configreg_i11, fabric_otp_user_configreg_i12, fabric_otp_user_configreg_i13, fabric_otp_user_configreg_i14, fabric_otp_user_configreg_i15, fabric_otp_user_configreg_i16, fabric_otp_user_configreg_i17, fabric_otp_user_configreg_i18, fabric_otp_user_configreg_i19, fabric_otp_user_configreg_i20, fabric_otp_user_configreg_i21, fabric_otp_user_configreg_i22, fabric_otp_user_configreg_i23, fabric_otp_user_configreg_i24, fabric_otp_user_configreg_i25, fabric_otp_user_configreg_i26, fabric_otp_user_configreg_i27, fabric_otp_user_configreg_i28, fabric_otp_user_configreg_i29 -, fabric_otp_user_configreg_i30, fabric_otp_user_configreg_i31, fabric_otp_user_configreg_i32, fabric_otp_user_tst_scanin_i1, fabric_otp_user_tst_scanin_i2, fabric_otp_user_tst_scanin_i3, fabric_otp_user_tst_scanin_i4, fabric_otp_user_tst_scanin_i5, fabric_sif_update_en_i1, fabric_sif_update_en_i2, fabric_sif_update_en_i3, fabric_sif_update_en_i4, fabric_sif_update_en_i5, fabric_sif_update_en_i6, fabric_sif_update_en_i7, fabric_sif_update_en_i8, fabric_sif_update_en_i9, fabric_sif_update_en_i10, fabric_sif_update_en_i11, fabric_sif_update_en_i12, fabric_sif_update_en_i13 -, fabric_sif_update_en_i14, fabric_sif_update_en_i15, fabric_sif_update_en_i16, fabric_sif_update_en_i17, fabric_sif_update_en_i18, fabric_sif_update_en_i19, fabric_sif_update_en_i20, fabric_sif_update_en_i21, fabric_sif_update_en_i22, fabric_sif_update_en_i23, fabric_sif_update_en_i24, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_spare_i1, fabric_spare_i2, fabric_spare_i3, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_debug_direct_permission_write_o1, fabric_debug_direct_permission_write_o2 -, fabric_debug_direct_permission_write_o3, fabric_debug_direct_permission_write_o4, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_mrepair_fuse_tstscanout_o1, fabric_mrepair_fuse_tstscanout_o2, fabric_mrepair_fuse_tstscanout_o3, fabric_mrepair_fuse_tstscanout_o4, fabric_mrepair_fuse_tstscanout_o5, fabric_otp_user_tst_scanout_o1, fabric_otp_user_tst_scanout_o2, fabric_otp_user_tst_scanout_o3, fabric_otp_user_tst_scanout_o4, fabric_otp_user_tst_scanout_o5, fabric_sif_update_en_to_bist_o1, fabric_sif_update_en_to_bist_o2, fabric_sif_update_en_to_bist_o3, fabric_sif_update_en_to_bist_o4, fabric_sif_update_en_to_bist_o5 -, fabric_sif_update_en_to_bist_o6, fabric_sif_update_en_to_bist_o7, fabric_sif_update_en_to_bist_o8, fabric_sif_update_en_to_bist_o9, fabric_sif_update_en_to_bist_o10, fabric_sif_update_en_to_bist_o11, fabric_sif_update_en_to_bist_o12, fabric_sif_update_en_to_bist_o13, fabric_sif_update_en_to_bist_o14, fabric_sif_update_en_to_bist_o15, fabric_sif_update_en_to_bist_o16, fabric_sif_update_en_to_bist_o17, fabric_sif_update_en_to_bist_o18, fabric_sif_update_en_to_bist_o19, fabric_sif_update_en_to_bist_o20, fabric_sif_update_en_to_bist_o21, fabric_sif_update_en_to_bist_o22, fabric_sif_update_en_to_bist_o23, fabric_sif_update_en_to_bist_o24, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o -, fabric_debug_frame_permission_frame_o1, fabric_debug_frame_permission_frame_o2, fabric_debug_frame_permission_frame_o3, fabric_debug_frame_permission_frame_o4, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_data_to_bist_o1, fabric_data_to_bist_o2, fabric_data_to_bist_o3, fabric_data_to_bist_o4, fabric_data_to_bist_o5, fabric_data_to_bist_o6, fabric_data_to_bist_o7, fabric_data_to_bist_o8, fabric_data_to_bist_o9, fabric_data_to_bist_o10, fabric_data_to_bist_o11, fabric_data_to_bist_o12, fabric_data_to_bist_o13 -, fabric_data_to_bist_o14, fabric_data_to_bist_o15, fabric_data_to_bist_o16, fabric_data_to_bist_o17, fabric_data_to_bist_o18, fabric_data_to_bist_o19, fabric_data_to_bist_o20, fabric_data_to_bist_o21, fabric_data_to_bist_o22, fabric_data_to_bist_o23, fabric_data_to_bist_o24, fabric_otp_user_startword_o1, fabric_otp_user_startword_o2, fabric_otp_user_startword_o3, fabric_otp_user_startword_o4, fabric_otp_user_startword_o5, fabric_otp_user_startword_o6, fabric_otp_user_startword_o7, fabric_otp_user_startword_o8, fabric_otp_user_startword_o9, fabric_otp_user_startword_o10 -, fabric_otp_user_startword_o11, fabric_otp_user_startword_o12, fabric_otp_user_startword_o13, fabric_otp_user_startword_o14, fabric_otp_user_startword_o15, fabric_otp_user_startword_o16, fabric_ahb_direct_data_o1, fabric_ahb_direct_data_o2, fabric_ahb_direct_data_o3, fabric_ahb_direct_data_o4, fabric_ahb_direct_data_o5, fabric_ahb_direct_data_o6, fabric_ahb_direct_data_o7, fabric_ahb_direct_data_o8, fabric_ahb_direct_data_o9, fabric_ahb_direct_data_o10, fabric_ahb_direct_data_o11, fabric_ahb_direct_data_o12, fabric_ahb_direct_data_o13, fabric_ahb_direct_data_o14, fabric_ahb_direct_data_o15 -, fabric_ahb_direct_data_o16, fabric_ahb_direct_data_o17, fabric_ahb_direct_data_o18, fabric_ahb_direct_data_o19, fabric_ahb_direct_data_o20, fabric_ahb_direct_data_o21, fabric_ahb_direct_data_o22, fabric_ahb_direct_data_o23, fabric_ahb_direct_data_o24, fabric_ahb_direct_data_o25, fabric_ahb_direct_data_o26, fabric_ahb_direct_data_o27, fabric_ahb_direct_data_o28, fabric_ahb_direct_data_o29, fabric_ahb_direct_data_o30, fabric_ahb_direct_data_o31, fabric_ahb_direct_data_o32, fabric_parusr_data_o1, fabric_parusr_data_o2, fabric_parusr_data_o3, fabric_parusr_data_o4 -, fabric_parusr_data_o5, fabric_parusr_data_o6, fabric_parusr_data_o7, fabric_parusr_data_o8, fabric_parusr_data_o9, fabric_parusr_data_o10, fabric_parusr_data_o11, fabric_parusr_data_o12, fabric_parusr_data_o13, fabric_parusr_data_o14, fabric_parusr_data_o15, fabric_parusr_data_o16, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_global_chip_status_o1, fabric_global_chip_status_o2, fabric_global_chip_status_o3, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_fuse_status_o1 -, fabric_fuse_status_o2, fabric_fuse_status_o3, fabric_otp_apb_rdata_o1, fabric_otp_apb_rdata_o2, fabric_otp_apb_rdata_o3, fabric_otp_apb_rdata_o4, fabric_otp_apb_rdata_o5, fabric_otp_apb_rdata_o6, fabric_otp_apb_rdata_o7, fabric_otp_apb_rdata_o8, fabric_otp_apb_rdata_o9, fabric_otp_apb_rdata_o10, fabric_otp_apb_rdata_o11, fabric_otp_apb_rdata_o12, fabric_otp_apb_rdata_o13, fabric_otp_apb_rdata_o14, fabric_otp_apb_rdata_o15, fabric_otp_apb_rdata_o16, fabric_otp_apb_rdata_o17, fabric_otp_apb_rdata_o18, fabric_otp_apb_rdata_o19 -, fabric_otp_apb_rdata_o20, fabric_otp_apb_rdata_o21, fabric_otp_apb_rdata_o22, fabric_otp_apb_rdata_o23, fabric_otp_apb_rdata_o24, fabric_otp_apb_rdata_o25, fabric_otp_apb_rdata_o26, fabric_otp_apb_rdata_o27, fabric_otp_apb_rdata_o28, fabric_otp_apb_rdata_o29, fabric_otp_apb_rdata_o30, fabric_otp_apb_rdata_o31, fabric_otp_apb_rdata_o32, fabric_jtag_tms_o, fabric_debug_bsec_core_status_o1, fabric_debug_bsec_core_status_o2, fabric_debug_bsec_core_status_o3, fabric_debug_bsec_core_status_o4, fabric_debug_bsec_core_status_o5, fabric_debug_bsec_core_status_o6, fabric_debug_bsec_core_status_o7 -, fabric_debug_bsec_core_status_o8, fabric_debug_bsec_core_status_o9, fabric_debug_bsec_core_status_o10, fabric_debug_bsec_core_status_o11, fabric_debug_bsec_core_status_o12, fabric_debug_bsec_core_status_o13, fabric_debug_bsec_core_status_o14, fabric_debug_bsec_core_status_o15, fabric_debug_bsec_core_status_o16, fabric_debug_bsec_core_status_o17, fabric_debug_bsec_core_status_o18, fabric_debug_bsec_core_status_o19, fabric_debug_bsec_core_status_o20, fabric_debug_bsec_core_status_o21, fabric_debug_bsec_core_status_o22, fabric_debug_bsec_core_status_o23, fabric_debug_bsec_core_status_o24, fabric_debug_bsec_core_status_o25, fabric_debug_bsec_core_status_o26, fabric_debug_bsec_core_status_o27, fabric_debug_bsec_core_status_o28 -, fabric_debug_bsec_core_status_o29, fabric_debug_bsec_core_status_o30, fabric_debug_bsec_core_status_o31, fabric_debug_bsec_core_status_o32, fabric_mrepair_fuse_bist1fail_o1, fabric_mrepair_fuse_bist1fail_o2, fabric_mrepair_fuse_bist1fail_o3, fabric_mrepair_fuse_bist1fail_o4, fabric_mrepair_fuse_bist1fail_o5, fabric_mrepair_fuse_bist1fail_o6, fabric_mrepair_fuse_bist1fail_o7, fabric_mrepair_fuse_bist1fail_o8, fabric_flag_ready_o, fabric_mrepair_fuse_dout_o1, fabric_mrepair_fuse_dout_o2, fabric_mrepair_fuse_dout_o3, fabric_mrepair_fuse_dout_o4, fabric_mrepair_fuse_dout_o5, fabric_mrepair_fuse_dout_o6, fabric_mrepair_fuse_dout_o7, fabric_mrepair_fuse_dout_o8 -, fabric_mrepair_fuse_dout_o9, fabric_mrepair_fuse_dout_o10, fabric_mrepair_fuse_dout_o11, fabric_mrepair_fuse_dout_o12, fabric_mrepair_fuse_dout_o13, fabric_mrepair_fuse_dout_o14, fabric_mrepair_fuse_dout_o15, fabric_mrepair_fuse_dout_o16, fabric_mrepair_fuse_dout_o17, fabric_mrepair_fuse_dout_o18, fabric_mrepair_fuse_dout_o19, fabric_mrepair_fuse_dout_o20, fabric_mrepair_fuse_dout_o21, fabric_mrepair_fuse_dout_o22, fabric_mrepair_fuse_dout_o23, fabric_mrepair_fuse_dout_o24, fabric_mrepair_fuse_dout_o25, fabric_mrepair_fuse_dout_o26, fabric_mrepair_fuse_dout_o27, fabric_mrepair_fuse_dout_o28, fabric_mrepair_fuse_dout_o29 -, fabric_mrepair_fuse_dout_o30, fabric_mrepair_fuse_dout_o31, fabric_mrepair_fuse_dout_o32, fabric_mrepair_fuse_dout_o33, fabric_mrepair_fuse_dout_o34, fabric_mrepair_fuse_dout_o35, fabric_mrepair_fuse_dout_o36, fabric_mrepair_fuse_dout_o37, fabric_mrepair_fuse_dout_o38, fabric_mrepair_fuse_dout_o39, fabric_mrepair_fuse_dout_o40, fabric_mrepair_fuse_dout_o41, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_shift_en_to_bist_o1, fabric_shift_en_to_bist_o2, fabric_shift_en_to_bist_o3, fabric_shift_en_to_bist_o4, fabric_shift_en_to_bist_o5, fabric_shift_en_to_bist_o6 -, fabric_shift_en_to_bist_o7, fabric_shift_en_to_bist_o8, fabric_shift_en_to_bist_o9, fabric_shift_en_to_bist_o10, fabric_shift_en_to_bist_o11, fabric_shift_en_to_bist_o12, fabric_shift_en_to_bist_o13, fabric_shift_en_to_bist_o14, fabric_shift_en_to_bist_o15, fabric_shift_en_to_bist_o16, fabric_shift_en_to_bist_o17, fabric_shift_en_to_bist_o18, fabric_shift_en_to_bist_o19, fabric_shift_en_to_bist_o20, fabric_shift_en_to_bist_o21, fabric_shift_en_to_bist_o22, fabric_shift_en_to_bist_o23, fabric_shift_en_to_bist_o24, fabric_sif_reg_en_to_bist_o1, fabric_sif_reg_en_to_bist_o2, fabric_sif_reg_en_to_bist_o3 -, fabric_sif_reg_en_to_bist_o4, fabric_sif_reg_en_to_bist_o5, fabric_sif_reg_en_to_bist_o6, fabric_sif_reg_en_to_bist_o7, fabric_sif_reg_en_to_bist_o8, fabric_sif_reg_en_to_bist_o9, fabric_sif_reg_en_to_bist_o10, fabric_sif_reg_en_to_bist_o11, fabric_sif_reg_en_to_bist_o12, fabric_sif_reg_en_to_bist_o13, fabric_sif_reg_en_to_bist_o14, fabric_sif_reg_en_to_bist_o15, fabric_sif_reg_en_to_bist_o16, fabric_sif_reg_en_to_bist_o17, fabric_sif_reg_en_to_bist_o18, fabric_sif_reg_en_to_bist_o19, fabric_sif_reg_en_to_bist_o20, fabric_sif_reg_en_to_bist_o21, fabric_sif_reg_en_to_bist_o22, fabric_sif_reg_en_to_bist_o23, fabric_sif_reg_en_to_bist_o24 -, fabric_sif_reg_en_to_bist_o25, fabric_sif_reg_en_to_bist_o26, fabric_sif_reg_en_to_bist_o27, fabric_sif_reg_en_to_bist_o28, fabric_sif_reg_en_to_bist_o29, fabric_sif_reg_en_to_bist_o30, fabric_sif_reg_en_to_bist_o31, fabric_sif_reg_en_to_bist_o32, fabric_sif_reg_en_to_bist_o33, fabric_sif_reg_en_to_bist_o34, fabric_sif_reg_en_to_bist_o35, fabric_sif_reg_en_to_bist_o36, fabric_sif_reg_en_to_bist_o37, fabric_sif_reg_en_to_bist_o38, fabric_sif_reg_en_to_bist_o39, fabric_sif_reg_en_to_bist_o40, fabric_sif_reg_en_to_bist_o41, fabric_sif_reg_en_to_bist_o42, fabric_sif_reg_en_to_bist_o43, fabric_sif_reg_en_to_bist_o44, fabric_sif_reg_en_to_bist_o45 -, fabric_sif_reg_en_to_bist_o46, fabric_sif_reg_en_to_bist_o47, fabric_sif_reg_en_to_bist_o48, fabric_sif_reg_en_to_bist_o49, fabric_sif_reg_en_to_bist_o50, fabric_sif_reg_en_to_bist_o51, fabric_sif_reg_en_to_bist_o52, fabric_sif_reg_en_to_bist_o53, fabric_sif_reg_en_to_bist_o54, fabric_sif_reg_en_to_bist_o55, fabric_sif_reg_en_to_bist_o56, fabric_sif_reg_en_to_bist_o57, fabric_sif_reg_en_to_bist_o58, fabric_sif_reg_en_to_bist_o59, fabric_sif_reg_en_to_bist_o60, fabric_sif_reg_en_to_bist_o61, fabric_sif_reg_en_to_bist_o62, fabric_sif_reg_en_to_bist_o63, fabric_sif_reg_en_to_bist_o64, fabric_sif_reg_en_to_bist_o65, fabric_sif_reg_en_to_bist_o66 -, fabric_sif_reg_en_to_bist_o67, fabric_sif_reg_en_to_bist_o68, fabric_sif_reg_en_to_bist_o69, fabric_sif_reg_en_to_bist_o70, fabric_sif_reg_en_to_bist_o71, fabric_sif_reg_en_to_bist_o72, fabric_sif_reg_en_to_bist_o73, fabric_sif_reg_en_to_bist_o74, fabric_sif_reg_en_to_bist_o75, fabric_sif_reg_en_to_bist_o76, fabric_sif_reg_en_to_bist_o77, fabric_sif_reg_en_to_bist_o78, fabric_sif_reg_en_to_bist_o79, fabric_sif_reg_en_to_bist_o80, fabric_sif_reg_en_to_bist_o81, fabric_sif_reg_en_to_bist_o82, fabric_sif_reg_en_to_bist_o83, fabric_sif_reg_en_to_bist_o84, fabric_sif_reg_en_to_bist_o85, fabric_sif_reg_en_to_bist_o86, fabric_sif_reg_en_to_bist_o87 -, fabric_sif_reg_en_to_bist_o88, fabric_sif_reg_en_to_bist_o89, fabric_sif_reg_en_to_bist_o90, fabric_sif_reg_en_to_bist_o91, fabric_sif_reg_en_to_bist_o92, fabric_sif_reg_en_to_bist_o93, fabric_sif_reg_en_to_bist_o94, fabric_sif_reg_en_to_bist_o95, fabric_sif_reg_en_to_bist_o96, fabric_sif_reg_en_to_bist_o97, fabric_sif_reg_en_to_bist_o98, fabric_sif_reg_en_to_bist_o99, fabric_sif_reg_en_to_bist_o100, fabric_sif_reg_en_to_bist_o101, fabric_sif_reg_en_to_bist_o102, fabric_sif_reg_en_to_bist_o103, fabric_sif_reg_en_to_bist_o104, fabric_sif_reg_en_to_bist_o105, fabric_sif_reg_en_to_bist_o106, fabric_sif_reg_en_to_bist_o107, fabric_sif_reg_en_to_bist_o108 -, fabric_sif_reg_en_to_bist_o109, fabric_sif_reg_en_to_bist_o110, fabric_sif_reg_en_to_bist_o111, fabric_sif_reg_en_to_bist_o112, fabric_sif_reg_en_to_bist_o113, fabric_sif_reg_en_to_bist_o114, fabric_sif_reg_en_to_bist_o115, fabric_sif_reg_en_to_bist_o116, fabric_sif_reg_en_to_bist_o117, fabric_sif_reg_en_to_bist_o118, fabric_sif_reg_en_to_bist_o119, fabric_sif_reg_en_to_bist_o120, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_otp_user_wlromout_o1, fabric_otp_user_wlromout_o2, fabric_otp_user_wlromout_o3, fabric_otp_user_wlromout_o4, fabric_otp_user_wlromout_o5, fabric_otp_user_wlromout_o6, fabric_otp_user_wlromout_o7 -, fabric_otp_user_wlromout_o8, fabric_otp_user_wlromout_o9, fabric_otp_user_wlromout_o10, fabric_mrepair_fuse_bend1_o, fabric_mrepair_fuse_flagstate_o1, fabric_mrepair_fuse_flagstate_o2, fabric_mrepair_fuse_flagstate_o3, fabric_mrepair_fuse_flagstate_o4, fabric_system_data_from_mem_bist_o1, fabric_system_data_from_mem_bist_o2, fabric_system_data_from_mem_bist_o3, fabric_system_data_from_mem_bist_o4, fabric_system_data_from_mem_bist_o5, fabric_system_data_from_mem_bist_o6, fabric_system_data_from_mem_bist_o7, fabric_system_data_from_mem_bist_o8, fabric_system_data_from_mem_bist_o9, fabric_system_data_from_mem_bist_o10, fabric_system_data_from_mem_bist_o11, fabric_system_data_from_mem_bist_o12, fabric_system_data_from_mem_bist_o13 -, fabric_system_data_from_mem_bist_o14, fabric_system_data_from_mem_bist_o15, fabric_system_data_from_mem_bist_o16, fabric_system_data_from_mem_bist_o17, fabric_system_data_from_mem_bist_o18, fabric_system_data_from_mem_bist_o19, fabric_system_data_from_mem_bist_o20, fabric_system_data_from_mem_bist_o21, fabric_system_data_from_mem_bist_o22, fabric_system_data_from_mem_bist_o23, fabric_system_data_from_mem_bist_o24, fabric_direct_data_o1, fabric_direct_data_o2, fabric_direct_data_o3, fabric_direct_data_o4, fabric_direct_data_o5, fabric_direct_data_o6, fabric_direct_data_o7, fabric_direct_data_o8, fabric_direct_data_o9, fabric_direct_data_o10 -, fabric_direct_data_o11, fabric_direct_data_o12, fabric_direct_data_o13, fabric_direct_data_o14, fabric_direct_data_o15, fabric_direct_data_o16, fabric_direct_data_o17, fabric_direct_data_o18, fabric_direct_data_o19, fabric_direct_data_o20, fabric_direct_data_o21, fabric_direct_data_o22, fabric_direct_data_o23, fabric_direct_data_o24, fabric_direct_data_o25, fabric_direct_data_o26, fabric_direct_data_o27, fabric_direct_data_o28, fabric_direct_data_o29, fabric_direct_data_o30, fabric_direct_data_o31 -, fabric_direct_data_o32, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_chip_status_o1, fabric_chip_status_o2, fabric_chip_status_o3, fabric_chip_status_o4, fabric_chip_status_o5, fabric_chip_status_o6, fabric_chip_status_o7, fabric_chip_status_o8, fabric_chip_status_o9, fabric_chip_status_o10, fabric_chip_status_o11, fabric_chip_status_o12, fabric_chip_status_o13, fabric_chip_status_o14, fabric_chip_status_o15, fabric_chip_status_o16, fabric_chip_status_o17, fabric_chip_status_o18 -, fabric_chip_status_o19, fabric_chip_status_o20, fabric_chip_status_o21, fabric_chip_status_o22, fabric_chip_status_o23, fabric_chip_status_o24, fabric_chip_status_o25, fabric_chip_status_o26, fabric_chip_status_o27, fabric_chip_status_o28, fabric_chip_status_o29, fabric_chip_status_o30, fabric_chip_status_o31, fabric_chip_status_o32, fabric_chip_status_o33, fabric_chip_status_o34, fabric_chip_status_o35, fabric_chip_status_o36, fabric_chip_status_o37, fabric_chip_status_o38, fabric_chip_status_o39 -, fabric_chip_status_o40, fabric_chip_status_o41, fabric_chip_status_o42, fabric_chip_status_o43, fabric_chip_status_o44, fabric_chip_status_o45, fabric_chip_status_o46, fabric_chip_status_o47, fabric_chip_status_o48, fabric_chip_status_o49, fabric_chip_status_o50, fabric_chip_status_o51, fabric_chip_status_o52, fabric_chip_status_o53, fabric_chip_status_o54, fabric_chip_status_o55, fabric_chip_status_o56, fabric_chip_status_o57, fabric_chip_status_o58, fabric_chip_status_o59, fabric_chip_status_o60 -, fabric_chip_status_o61, fabric_chip_status_o62, fabric_chip_status_o63, fabric_chip_status_o64, fabric_chip_status_o65, fabric_chip_status_o66, fabric_chip_status_o67, fabric_chip_status_o68, fabric_chip_status_o69, fabric_chip_status_o70, fabric_chip_status_o71, fabric_chip_status_o72, fabric_mrepair_fuse_disturbed_o, fabric_debug_otpboot_state_o1, fabric_debug_otpboot_state_o2, fabric_debug_otpboot_state_o3, fabric_pd_ready_o1, fabric_pd_ready_o2, fabric_pd_ready_o3, fabric_pd_ready_o4, fabric_pd_ready_o5 -, fabric_pd_ready_o6, fabric_pd_ready_o7, fabric_pd_ready_o8, fabric_pd_ready_o9, fabric_pd_ready_o10, fabric_pd_ready_o11, fabric_pd_ready_o12, fabric_pd_ready_o13, fabric_pd_ready_o14, fabric_pd_ready_o15, fabric_pd_ready_o16, fabric_pd_ready_o17, fabric_pd_ready_o18, fabric_pd_ready_o19, fabric_pd_ready_o20, fabric_pd_ready_o21, fabric_pd_ready_o22, fabric_pd_ready_o23, fabric_pd_ready_o24, fabric_debug_key_correct_o, fabric_otp_apb_ready_o -, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_debug_lifecycle_o1, fabric_debug_lifecycle_o2, fabric_debug_lifecycle_o3, fabric_debug_lifecycle_o4, fabric_mrepair_fuse_ack_o, fabric_debug_cpt_retry_o1, fabric_debug_cpt_retry_o2, fabric_debug_cpt_retry_o3, fabric_debug_cpt_retry_o4, fabric_otp_security_ack_o, fabric_debug_otpmgmt_state_o1, fabric_debug_otpmgmt_state_o2, fabric_debug_otpmgmt_state_o3, fabric_mrepair_fuse_progfail_o, fabric_otp_user_bist2fail_o1, fabric_otp_user_bist2fail_o2, fabric_otp_user_bist2fail_o3, fabric_otp_user_bist2fail_o4 -, fabric_otp_user_bist2fail_o5, fabric_otp_user_bist2fail_o6, fabric_otp_user_bist2fail_o7, fabric_user_data_o1, fabric_user_data_o2, fabric_user_data_o3, fabric_user_data_o4, fabric_user_data_o5, fabric_user_data_o6, fabric_user_data_o7, fabric_user_data_o8, fabric_user_data_o9, fabric_user_data_o10, fabric_user_data_o11, fabric_user_data_o12, fabric_user_data_o13, fabric_user_data_o14, fabric_user_data_o15, fabric_user_data_o16, fabric_user_data_o17, fabric_user_data_o18 -, fabric_user_data_o19, fabric_user_data_o20, fabric_user_data_o21, fabric_user_data_o22, fabric_user_data_o23, fabric_user_data_o24, fabric_user_data_o25, fabric_user_data_o26, fabric_user_data_o27, fabric_user_data_o28, fabric_user_data_o29, fabric_user_data_o30, fabric_user_data_o31, fabric_user_data_o32, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_mrepair_fuse_wlromout_o1 -, fabric_mrepair_fuse_wlromout_o2, fabric_mrepair_fuse_wlromout_o3, fabric_mrepair_fuse_wlromout_o4, fabric_mrepair_fuse_wlromout_o5, fabric_mrepair_fuse_wlromout_o6, fabric_mrepair_fuse_wlromout_o7, fabric_mrepair_fuse_wlromout_o8, fabric_mrepair_fuse_wlromout_o9, fabric_mrepair_fuse_wlromout_o10, fabric_debug_otpapb_state_o1, fabric_debug_otpapb_state_o2, fabric_debug_otpapb_state_o3, fabric_otp_user_bist1fail_o1, fabric_otp_user_bist1fail_o2, fabric_otp_user_bist1fail_o3, fabric_otp_user_bist1fail_o4, fabric_otp_user_bist1fail_o5, fabric_otp_user_bist1fail_o6, fabric_otp_user_bist1fail_o7, fabric_otp_user_bist1fail_o8, fabric_otp_security_bist_fail2_o1 -, fabric_otp_security_bist_fail2_o2, fabric_otp_security_bist_fail2_o3, fabric_otp_security_bist_fail2_o4, fabric_otp_security_bist_fail2_o5, fabric_otp_security_bist_fail2_o6, fabric_otp_security_bist_fail2_o7, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_otp_security_bist_fail1_o1, fabric_otp_security_bist_fail1_o2, fabric_otp_security_bist_fail1_o3, fabric_otp_security_bist_fail1_o4, fabric_otp_security_bist_fail1_o5, fabric_otp_security_bist_fail1_o6, fabric_otp_security_bist_fail1_o7, fabric_otp_security_bist_fail1_o8, fabric_mrepair_fuse_locked_o, fabric_otp_user_flagstate_o1, fabric_otp_user_flagstate_o2, fabric_otp_user_flagstate_o3 -, fabric_otp_user_flagstate_o4, fabric_otp_security_scanout_o1, fabric_otp_security_scanout_o2, fabric_otp_security_scanout_o3, fabric_otp_security_scanout_o4, fabric_otp_security_scanout_o5, fabric_user_write_cycle_o, fabric_debug_fsm_state_o1, fabric_debug_fsm_state_o2, fabric_debug_fsm_state_o3, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_debug_otpboot_curr_addr_o1, fabric_debug_otpboot_curr_addr_o2, fabric_debug_otpboot_curr_addr_o3, fabric_debug_otpboot_curr_addr_o4, fabric_debug_otpboot_curr_addr_o5 -, fabric_debug_otpboot_curr_addr_o6, fabric_debug_otpboot_curr_addr_o7, fabric_debug_otpboot_curr_addr_o8, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_sif_load_en_to_bist_o1, fabric_sif_load_en_to_bist_o2, fabric_sif_load_en_to_bist_o3, fabric_sif_load_en_to_bist_o4, fabric_sif_load_en_to_bist_o5, fabric_sif_load_en_to_bist_o6, fabric_sif_load_en_to_bist_o7, fabric_sif_load_en_to_bist_o8, fabric_sif_load_en_to_bist_o9, fabric_sif_load_en_to_bist_o10, fabric_sif_load_en_to_bist_o11, fabric_sif_load_en_to_bist_o12, fabric_sif_load_en_to_bist_o13, fabric_sif_load_en_to_bist_o14, fabric_sif_load_en_to_bist_o15, fabric_sif_load_en_to_bist_o16 -, fabric_sif_load_en_to_bist_o17, fabric_sif_load_en_to_bist_o18, fabric_sif_load_en_to_bist_o19, fabric_sif_load_en_to_bist_o20, fabric_sif_load_en_to_bist_o21, fabric_sif_load_en_to_bist_o22, fabric_sif_load_en_to_bist_o23, fabric_sif_load_en_to_bist_o24, fabric_io_out_o1, fabric_io_out_o2, fabric_io_out_o3, fabric_io_out_o4, fabric_io_out_o5, fabric_io_out_o6, fabric_io_out_o7, fabric_io_out_o8, fabric_io_out_o9, fabric_io_out_o10, fabric_io_out_o11, fabric_io_out_o12, fabric_io_out_o13 -, fabric_io_out_o14, fabric_io_out_o15, fabric_io_out_o16, fabric_io_out_o17, fabric_io_out_o18, fabric_io_out_o19, fabric_io_out_o20, fabric_io_out_o21, fabric_io_out_o22, fabric_io_out_o23, fabric_io_out_o24, fabric_io_out_o25, fabric_mrepair_fuse_startword_o1, fabric_mrepair_fuse_startword_o2, fabric_mrepair_fuse_startword_o3, fabric_mrepair_fuse_startword_o4, fabric_mrepair_fuse_startword_o5, fabric_mrepair_fuse_startword_o6, fabric_mrepair_fuse_startword_o7, fabric_mrepair_fuse_startword_o8, fabric_mrepair_fuse_startword_o9 -, fabric_mrepair_fuse_startword_o10, fabric_mrepair_fuse_startword_o11, fabric_mrepair_fuse_startword_o12, fabric_mrepair_fuse_startword_o13, fabric_mrepair_fuse_startword_o14, fabric_mrepair_fuse_startword_o15, fabric_mrepair_fuse_startword_o16, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_otp_user_dout_o1, fabric_otp_user_dout_o2, fabric_otp_user_dout_o3, fabric_otp_user_dout_o4, fabric_otp_user_dout_o5, fabric_otp_user_dout_o6, fabric_otp_user_dout_o7, fabric_otp_user_dout_o8, fabric_otp_user_dout_o9, fabric_otp_user_dout_o10 -, fabric_otp_user_dout_o11, fabric_otp_user_dout_o12, fabric_otp_user_dout_o13, fabric_otp_user_dout_o14, fabric_otp_user_dout_o15, fabric_otp_user_dout_o16, fabric_otp_user_dout_o17, fabric_otp_user_dout_o18, fabric_otp_user_dout_o19, fabric_otp_user_dout_o20, fabric_otp_user_dout_o21, fabric_otp_user_dout_o22, fabric_otp_user_dout_o23, fabric_otp_user_dout_o24, fabric_otp_user_dout_o25, fabric_otp_user_dout_o26, fabric_otp_user_dout_o27, fabric_otp_user_dout_o28, fabric_otp_user_dout_o29, fabric_otp_user_dout_o30, fabric_otp_user_dout_o31 -, fabric_otp_user_dout_o32, fabric_otp_user_dout_o33, fabric_otp_user_dout_o34, fabric_otp_user_dout_o35, fabric_otp_user_dout_o36, fabric_otp_user_dout_o37, fabric_otp_user_dout_o38, fabric_otp_user_dout_o39, fabric_otp_user_dout_o40, fabric_otp_user_dout_o41, fabric_mrepair_fuse_bist2fail_o1, fabric_mrepair_fuse_bist2fail_o2, fabric_mrepair_fuse_bist2fail_o3, fabric_mrepair_fuse_bist2fail_o4, fabric_mrepair_fuse_bist2fail_o5, fabric_mrepair_fuse_bist2fail_o6, fabric_mrepair_fuse_bist2fail_o7, fabric_status_cold_start_o, fabric_flag_error_o, fabric_debug_direct_permission_read_o1, fabric_debug_direct_permission_read_o2 -, fabric_debug_direct_permission_read_o3, fabric_debug_direct_permission_read_o4); - input fabric_ahb_direct_data_i1; - input fabric_ahb_direct_data_i10; - input fabric_ahb_direct_data_i11; - input fabric_ahb_direct_data_i12; - input fabric_ahb_direct_data_i13; - input fabric_ahb_direct_data_i14; - input fabric_ahb_direct_data_i15; - input fabric_ahb_direct_data_i16; - input fabric_ahb_direct_data_i17; - input fabric_ahb_direct_data_i18; - input fabric_ahb_direct_data_i19; - input fabric_ahb_direct_data_i2; - input fabric_ahb_direct_data_i20; - input fabric_ahb_direct_data_i21; - input fabric_ahb_direct_data_i22; - input fabric_ahb_direct_data_i23; - input fabric_ahb_direct_data_i24; - input fabric_ahb_direct_data_i25; - input fabric_ahb_direct_data_i26; - input fabric_ahb_direct_data_i27; - input fabric_ahb_direct_data_i28; - input fabric_ahb_direct_data_i29; - input fabric_ahb_direct_data_i3; - input fabric_ahb_direct_data_i30; - input fabric_ahb_direct_data_i31; - input fabric_ahb_direct_data_i32; - input fabric_ahb_direct_data_i4; - input fabric_ahb_direct_data_i5; - input fabric_ahb_direct_data_i6; - input fabric_ahb_direct_data_i7; - input fabric_ahb_direct_data_i8; - input fabric_ahb_direct_data_i9; - output fabric_ahb_direct_data_o1; - output fabric_ahb_direct_data_o10; - output fabric_ahb_direct_data_o11; - output fabric_ahb_direct_data_o12; - output fabric_ahb_direct_data_o13; - output fabric_ahb_direct_data_o14; - output fabric_ahb_direct_data_o15; - output fabric_ahb_direct_data_o16; - output fabric_ahb_direct_data_o17; - output fabric_ahb_direct_data_o18; - output fabric_ahb_direct_data_o19; - output fabric_ahb_direct_data_o2; - output fabric_ahb_direct_data_o20; - output fabric_ahb_direct_data_o21; - output fabric_ahb_direct_data_o22; - output fabric_ahb_direct_data_o23; - output fabric_ahb_direct_data_o24; - output fabric_ahb_direct_data_o25; - output fabric_ahb_direct_data_o26; - output fabric_ahb_direct_data_o27; - output fabric_ahb_direct_data_o28; - output fabric_ahb_direct_data_o29; - output fabric_ahb_direct_data_o3; - output fabric_ahb_direct_data_o30; - output fabric_ahb_direct_data_o31; - output fabric_ahb_direct_data_o32; - output fabric_ahb_direct_data_o4; - output fabric_ahb_direct_data_o5; - output fabric_ahb_direct_data_o6; - output fabric_ahb_direct_data_o7; - output fabric_ahb_direct_data_o8; - output fabric_ahb_direct_data_o9; - output fabric_cfg_fabric_user_flag_o; - output fabric_cfg_fabric_user_unmask_o; - output fabric_chip_status_o1; - output fabric_chip_status_o10; - output fabric_chip_status_o11; - output fabric_chip_status_o12; - output fabric_chip_status_o13; - output fabric_chip_status_o14; - output fabric_chip_status_o15; - output fabric_chip_status_o16; - output fabric_chip_status_o17; - output fabric_chip_status_o18; - output fabric_chip_status_o19; - output fabric_chip_status_o2; - output fabric_chip_status_o20; - output fabric_chip_status_o21; - output fabric_chip_status_o22; - output fabric_chip_status_o23; - output fabric_chip_status_o24; - output fabric_chip_status_o25; - output fabric_chip_status_o26; - output fabric_chip_status_o27; - output fabric_chip_status_o28; - output fabric_chip_status_o29; - output fabric_chip_status_o3; - output fabric_chip_status_o30; - output fabric_chip_status_o31; - output fabric_chip_status_o32; - output fabric_chip_status_o33; - output fabric_chip_status_o34; - output fabric_chip_status_o35; - output fabric_chip_status_o36; - output fabric_chip_status_o37; - output fabric_chip_status_o38; - output fabric_chip_status_o39; - output fabric_chip_status_o4; - output fabric_chip_status_o40; - output fabric_chip_status_o41; - output fabric_chip_status_o42; - output fabric_chip_status_o43; - output fabric_chip_status_o44; - output fabric_chip_status_o45; - output fabric_chip_status_o46; - output fabric_chip_status_o47; - output fabric_chip_status_o48; - output fabric_chip_status_o49; - output fabric_chip_status_o5; - output fabric_chip_status_o50; - output fabric_chip_status_o51; - output fabric_chip_status_o52; - output fabric_chip_status_o53; - output fabric_chip_status_o54; - output fabric_chip_status_o55; - output fabric_chip_status_o56; - output fabric_chip_status_o57; - output fabric_chip_status_o58; - output fabric_chip_status_o59; - output fabric_chip_status_o6; - output fabric_chip_status_o60; - output fabric_chip_status_o61; - output fabric_chip_status_o62; - output fabric_chip_status_o63; - output fabric_chip_status_o64; - output fabric_chip_status_o65; - output fabric_chip_status_o66; - output fabric_chip_status_o67; - output fabric_chip_status_o68; - output fabric_chip_status_o69; - output fabric_chip_status_o7; - output fabric_chip_status_o70; - output fabric_chip_status_o71; - output fabric_chip_status_o72; - output fabric_chip_status_o8; - output fabric_chip_status_o9; - input fabric_data_from_bist_i1; - input fabric_data_from_bist_i10; - input fabric_data_from_bist_i11; - input fabric_data_from_bist_i12; - input fabric_data_from_bist_i13; - input fabric_data_from_bist_i14; - input fabric_data_from_bist_i15; - input fabric_data_from_bist_i16; - input fabric_data_from_bist_i17; - input fabric_data_from_bist_i18; - input fabric_data_from_bist_i19; - input fabric_data_from_bist_i2; - input fabric_data_from_bist_i20; - input fabric_data_from_bist_i21; - input fabric_data_from_bist_i22; - input fabric_data_from_bist_i23; - input fabric_data_from_bist_i24; - input fabric_data_from_bist_i3; - input fabric_data_from_bist_i4; - input fabric_data_from_bist_i5; - input fabric_data_from_bist_i6; - input fabric_data_from_bist_i7; - input fabric_data_from_bist_i8; - input fabric_data_from_bist_i9; - input fabric_data_from_system_i; - input fabric_data_shift_en_i; - output fabric_data_to_bist_o1; - output fabric_data_to_bist_o10; - output fabric_data_to_bist_o11; - output fabric_data_to_bist_o12; - output fabric_data_to_bist_o13; - output fabric_data_to_bist_o14; - output fabric_data_to_bist_o15; - output fabric_data_to_bist_o16; - output fabric_data_to_bist_o17; - output fabric_data_to_bist_o18; - output fabric_data_to_bist_o19; - output fabric_data_to_bist_o2; - output fabric_data_to_bist_o20; - output fabric_data_to_bist_o21; - output fabric_data_to_bist_o22; - output fabric_data_to_bist_o23; - output fabric_data_to_bist_o24; - output fabric_data_to_bist_o3; - output fabric_data_to_bist_o4; - output fabric_data_to_bist_o5; - output fabric_data_to_bist_o6; - output fabric_data_to_bist_o7; - output fabric_data_to_bist_o8; - output fabric_data_to_bist_o9; - output fabric_data_to_system_o; - output fabric_debug_access_reg_data_ready_o; - output fabric_debug_bsec_core_status_o1; - output fabric_debug_bsec_core_status_o10; - output fabric_debug_bsec_core_status_o11; - output fabric_debug_bsec_core_status_o12; - output fabric_debug_bsec_core_status_o13; - output fabric_debug_bsec_core_status_o14; - output fabric_debug_bsec_core_status_o15; - output fabric_debug_bsec_core_status_o16; - output fabric_debug_bsec_core_status_o17; - output fabric_debug_bsec_core_status_o18; - output fabric_debug_bsec_core_status_o19; - output fabric_debug_bsec_core_status_o2; - output fabric_debug_bsec_core_status_o20; - output fabric_debug_bsec_core_status_o21; - output fabric_debug_bsec_core_status_o22; - output fabric_debug_bsec_core_status_o23; - output fabric_debug_bsec_core_status_o24; - output fabric_debug_bsec_core_status_o25; - output fabric_debug_bsec_core_status_o26; - output fabric_debug_bsec_core_status_o27; - output fabric_debug_bsec_core_status_o28; - output fabric_debug_bsec_core_status_o29; - output fabric_debug_bsec_core_status_o3; - output fabric_debug_bsec_core_status_o30; - output fabric_debug_bsec_core_status_o31; - output fabric_debug_bsec_core_status_o32; - output fabric_debug_bsec_core_status_o4; - output fabric_debug_bsec_core_status_o5; - output fabric_debug_bsec_core_status_o6; - output fabric_debug_bsec_core_status_o7; - output fabric_debug_bsec_core_status_o8; - output fabric_debug_bsec_core_status_o9; - output fabric_debug_cpt_retry_o1; - output fabric_debug_cpt_retry_o2; - output fabric_debug_cpt_retry_o3; - output fabric_debug_cpt_retry_o4; - output fabric_debug_direct_permission_read_o1; - output fabric_debug_direct_permission_read_o2; - output fabric_debug_direct_permission_read_o3; - output fabric_debug_direct_permission_read_o4; - output fabric_debug_direct_permission_write_o1; - output fabric_debug_direct_permission_write_o2; - output fabric_debug_direct_permission_write_o3; - output fabric_debug_direct_permission_write_o4; - output fabric_debug_error_o; - output fabric_debug_frame_permission_frame_o1; - output fabric_debug_frame_permission_frame_o2; - output fabric_debug_frame_permission_frame_o3; - output fabric_debug_frame_permission_frame_o4; - output fabric_debug_frame_use_encryption_o; - output fabric_debug_fsm_state_o1; - output fabric_debug_fsm_state_o2; - output fabric_debug_fsm_state_o3; - output fabric_debug_key_correct_o; - output fabric_debug_lifecycle_o1; - output fabric_debug_lifecycle_o2; - output fabric_debug_lifecycle_o3; - output fabric_debug_lifecycle_o4; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output fabric_debug_otpapb_state_o1; - output fabric_debug_otpapb_state_o2; - output fabric_debug_otpapb_state_o3; - output fabric_debug_otpboot_curr_addr_o1; - output fabric_debug_otpboot_curr_addr_o2; - output fabric_debug_otpboot_curr_addr_o3; - output fabric_debug_otpboot_curr_addr_o4; - output fabric_debug_otpboot_curr_addr_o5; - output fabric_debug_otpboot_curr_addr_o6; - output fabric_debug_otpboot_curr_addr_o7; - output fabric_debug_otpboot_curr_addr_o8; - output fabric_debug_otpboot_state_o1; - output fabric_debug_otpboot_state_o2; - output fabric_debug_otpboot_state_o3; - output fabric_debug_otpmgmt_state_o1; - output fabric_debug_otpmgmt_state_o2; - output fabric_debug_otpmgmt_state_o3; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - output fabric_decoder_init_ready_o; - input fabric_direct_data_i1; - input fabric_direct_data_i10; - input fabric_direct_data_i11; - input fabric_direct_data_i12; - input fabric_direct_data_i13; - input fabric_direct_data_i14; - input fabric_direct_data_i15; - input fabric_direct_data_i16; - input fabric_direct_data_i17; - input fabric_direct_data_i18; - input fabric_direct_data_i19; - input fabric_direct_data_i2; - input fabric_direct_data_i20; - input fabric_direct_data_i21; - input fabric_direct_data_i22; - input fabric_direct_data_i23; - input fabric_direct_data_i24; - input fabric_direct_data_i25; - input fabric_direct_data_i26; - input fabric_direct_data_i27; - input fabric_direct_data_i28; - input fabric_direct_data_i29; - input fabric_direct_data_i3; - input fabric_direct_data_i30; - input fabric_direct_data_i31; - input fabric_direct_data_i32; - input fabric_direct_data_i4; - input fabric_direct_data_i5; - input fabric_direct_data_i6; - input fabric_direct_data_i7; - input fabric_direct_data_i8; - input fabric_direct_data_i9; - output fabric_direct_data_o1; - output fabric_direct_data_o10; - output fabric_direct_data_o11; - output fabric_direct_data_o12; - output fabric_direct_data_o13; - output fabric_direct_data_o14; - output fabric_direct_data_o15; - output fabric_direct_data_o16; - output fabric_direct_data_o17; - output fabric_direct_data_o18; - output fabric_direct_data_o19; - output fabric_direct_data_o2; - output fabric_direct_data_o20; - output fabric_direct_data_o21; - output fabric_direct_data_o22; - output fabric_direct_data_o23; - output fabric_direct_data_o24; - output fabric_direct_data_o25; - output fabric_direct_data_o26; - output fabric_direct_data_o27; - output fabric_direct_data_o28; - output fabric_direct_data_o29; - output fabric_direct_data_o3; - output fabric_direct_data_o30; - output fabric_direct_data_o31; - output fabric_direct_data_o32; - output fabric_direct_data_o4; - output fabric_direct_data_o5; - output fabric_direct_data_o6; - output fabric_direct_data_o7; - output fabric_direct_data_o8; - output fabric_direct_data_o9; - input fabric_end_encoding_i; - output fabric_flag_error_o; - output fabric_flag_ready_o; - output fabric_flag_trigger_o; - output fabric_fuse_status_o1; - output fabric_fuse_status_o2; - output fabric_fuse_status_o3; - output fabric_global_chip_status_o1; - output fabric_global_chip_status_o2; - output fabric_global_chip_status_o3; - input fabric_io_in_i1; - input fabric_io_in_i10; - input fabric_io_in_i11; - input fabric_io_in_i12; - input fabric_io_in_i13; - input fabric_io_in_i14; - input fabric_io_in_i15; - input fabric_io_in_i16; - input fabric_io_in_i17; - input fabric_io_in_i18; - input fabric_io_in_i19; - input fabric_io_in_i2; - input fabric_io_in_i20; - input fabric_io_in_i21; - input fabric_io_in_i22; - input fabric_io_in_i23; - input fabric_io_in_i24; - input fabric_io_in_i25; - input fabric_io_in_i3; - input fabric_io_in_i4; - input fabric_io_in_i5; - input fabric_io_in_i6; - input fabric_io_in_i7; - input fabric_io_in_i8; - input fabric_io_in_i9; - input fabric_io_oe_i1; - input fabric_io_oe_i10; - input fabric_io_oe_i11; - input fabric_io_oe_i12; - input fabric_io_oe_i13; - input fabric_io_oe_i14; - input fabric_io_oe_i15; - input fabric_io_oe_i16; - input fabric_io_oe_i17; - input fabric_io_oe_i18; - input fabric_io_oe_i19; - input fabric_io_oe_i2; - input fabric_io_oe_i20; - input fabric_io_oe_i21; - input fabric_io_oe_i22; - input fabric_io_oe_i23; - input fabric_io_oe_i24; - input fabric_io_oe_i25; - input fabric_io_oe_i3; - input fabric_io_oe_i4; - input fabric_io_oe_i5; - input fabric_io_oe_i6; - input fabric_io_oe_i7; - input fabric_io_oe_i8; - input fabric_io_oe_i9; - output fabric_io_out_o1; - output fabric_io_out_o10; - output fabric_io_out_o11; - output fabric_io_out_o12; - output fabric_io_out_o13; - output fabric_io_out_o14; - output fabric_io_out_o15; - output fabric_io_out_o16; - output fabric_io_out_o17; - output fabric_io_out_o18; - output fabric_io_out_o19; - output fabric_io_out_o2; - output fabric_io_out_o20; - output fabric_io_out_o21; - output fabric_io_out_o22; - output fabric_io_out_o23; - output fabric_io_out_o24; - output fabric_io_out_o25; - output fabric_io_out_o3; - output fabric_io_out_o4; - output fabric_io_out_o5; - output fabric_io_out_o6; - output fabric_io_out_o7; - output fabric_io_out_o8; - output fabric_io_out_o9; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - output fabric_mrepair_fuse_ack_o; - input fabric_mrepair_fuse_add_i1; - input fabric_mrepair_fuse_add_i2; - input fabric_mrepair_fuse_add_i3; - input fabric_mrepair_fuse_add_i4; - input fabric_mrepair_fuse_add_i5; - input fabric_mrepair_fuse_add_i6; - input fabric_mrepair_fuse_add_i7; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output fabric_mrepair_fuse_bist1fail_o1; - output fabric_mrepair_fuse_bist1fail_o2; - output fabric_mrepair_fuse_bist1fail_o3; - output fabric_mrepair_fuse_bist1fail_o4; - output fabric_mrepair_fuse_bist1fail_o5; - output fabric_mrepair_fuse_bist1fail_o6; - output fabric_mrepair_fuse_bist1fail_o7; - output fabric_mrepair_fuse_bist1fail_o8; - output fabric_mrepair_fuse_bist2fail_o1; - output fabric_mrepair_fuse_bist2fail_o2; - output fabric_mrepair_fuse_bist2fail_o3; - output fabric_mrepair_fuse_bist2fail_o4; - output fabric_mrepair_fuse_bist2fail_o5; - output fabric_mrepair_fuse_bist2fail_o6; - output fabric_mrepair_fuse_bist2fail_o7; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - input fabric_mrepair_fuse_configreg_i1; - input fabric_mrepair_fuse_configreg_i10; - input fabric_mrepair_fuse_configreg_i11; - input fabric_mrepair_fuse_configreg_i12; - input fabric_mrepair_fuse_configreg_i13; - input fabric_mrepair_fuse_configreg_i14; - input fabric_mrepair_fuse_configreg_i15; - input fabric_mrepair_fuse_configreg_i16; - input fabric_mrepair_fuse_configreg_i17; - input fabric_mrepair_fuse_configreg_i18; - input fabric_mrepair_fuse_configreg_i19; - input fabric_mrepair_fuse_configreg_i2; - input fabric_mrepair_fuse_configreg_i20; - input fabric_mrepair_fuse_configreg_i21; - input fabric_mrepair_fuse_configreg_i22; - input fabric_mrepair_fuse_configreg_i23; - input fabric_mrepair_fuse_configreg_i24; - input fabric_mrepair_fuse_configreg_i25; - input fabric_mrepair_fuse_configreg_i26; - input fabric_mrepair_fuse_configreg_i27; - input fabric_mrepair_fuse_configreg_i28; - input fabric_mrepair_fuse_configreg_i29; - input fabric_mrepair_fuse_configreg_i3; - input fabric_mrepair_fuse_configreg_i30; - input fabric_mrepair_fuse_configreg_i31; - input fabric_mrepair_fuse_configreg_i32; - input fabric_mrepair_fuse_configreg_i4; - input fabric_mrepair_fuse_configreg_i5; - input fabric_mrepair_fuse_configreg_i6; - input fabric_mrepair_fuse_configreg_i7; - input fabric_mrepair_fuse_configreg_i8; - input fabric_mrepair_fuse_configreg_i9; - output fabric_mrepair_fuse_ded_o; - input fabric_mrepair_fuse_din_i1; - input fabric_mrepair_fuse_din_i10; - input fabric_mrepair_fuse_din_i11; - input fabric_mrepair_fuse_din_i12; - input fabric_mrepair_fuse_din_i13; - input fabric_mrepair_fuse_din_i14; - input fabric_mrepair_fuse_din_i15; - input fabric_mrepair_fuse_din_i16; - input fabric_mrepair_fuse_din_i17; - input fabric_mrepair_fuse_din_i18; - input fabric_mrepair_fuse_din_i19; - input fabric_mrepair_fuse_din_i2; - input fabric_mrepair_fuse_din_i20; - input fabric_mrepair_fuse_din_i21; - input fabric_mrepair_fuse_din_i22; - input fabric_mrepair_fuse_din_i23; - input fabric_mrepair_fuse_din_i24; - input fabric_mrepair_fuse_din_i25; - input fabric_mrepair_fuse_din_i26; - input fabric_mrepair_fuse_din_i27; - input fabric_mrepair_fuse_din_i28; - input fabric_mrepair_fuse_din_i29; - input fabric_mrepair_fuse_din_i3; - input fabric_mrepair_fuse_din_i30; - input fabric_mrepair_fuse_din_i31; - input fabric_mrepair_fuse_din_i32; - input fabric_mrepair_fuse_din_i33; - input fabric_mrepair_fuse_din_i34; - input fabric_mrepair_fuse_din_i35; - input fabric_mrepair_fuse_din_i36; - input fabric_mrepair_fuse_din_i37; - input fabric_mrepair_fuse_din_i38; - input fabric_mrepair_fuse_din_i39; - input fabric_mrepair_fuse_din_i4; - input fabric_mrepair_fuse_din_i5; - input fabric_mrepair_fuse_din_i6; - input fabric_mrepair_fuse_din_i7; - input fabric_mrepair_fuse_din_i8; - input fabric_mrepair_fuse_din_i9; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output fabric_mrepair_fuse_dout_o1; - output fabric_mrepair_fuse_dout_o10; - output fabric_mrepair_fuse_dout_o11; - output fabric_mrepair_fuse_dout_o12; - output fabric_mrepair_fuse_dout_o13; - output fabric_mrepair_fuse_dout_o14; - output fabric_mrepair_fuse_dout_o15; - output fabric_mrepair_fuse_dout_o16; - output fabric_mrepair_fuse_dout_o17; - output fabric_mrepair_fuse_dout_o18; - output fabric_mrepair_fuse_dout_o19; - output fabric_mrepair_fuse_dout_o2; - output fabric_mrepair_fuse_dout_o20; - output fabric_mrepair_fuse_dout_o21; - output fabric_mrepair_fuse_dout_o22; - output fabric_mrepair_fuse_dout_o23; - output fabric_mrepair_fuse_dout_o24; - output fabric_mrepair_fuse_dout_o25; - output fabric_mrepair_fuse_dout_o26; - output fabric_mrepair_fuse_dout_o27; - output fabric_mrepair_fuse_dout_o28; - output fabric_mrepair_fuse_dout_o29; - output fabric_mrepair_fuse_dout_o3; - output fabric_mrepair_fuse_dout_o30; - output fabric_mrepair_fuse_dout_o31; - output fabric_mrepair_fuse_dout_o32; - output fabric_mrepair_fuse_dout_o33; - output fabric_mrepair_fuse_dout_o34; - output fabric_mrepair_fuse_dout_o35; - output fabric_mrepair_fuse_dout_o36; - output fabric_mrepair_fuse_dout_o37; - output fabric_mrepair_fuse_dout_o38; - output fabric_mrepair_fuse_dout_o39; - output fabric_mrepair_fuse_dout_o4; - output fabric_mrepair_fuse_dout_o40; - output fabric_mrepair_fuse_dout_o41; - output fabric_mrepair_fuse_dout_o5; - output fabric_mrepair_fuse_dout_o6; - output fabric_mrepair_fuse_dout_o7; - output fabric_mrepair_fuse_dout_o8; - output fabric_mrepair_fuse_dout_o9; - input fabric_mrepair_fuse_eccbypass_i; - output fabric_mrepair_fuse_flagstate_o1; - output fabric_mrepair_fuse_flagstate_o2; - output fabric_mrepair_fuse_flagstate_o3; - output fabric_mrepair_fuse_flagstate_o4; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input fabric_mrepair_fuse_prgwidth_i1; - input fabric_mrepair_fuse_prgwidth_i2; - input fabric_mrepair_fuse_prgwidth_i3; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output fabric_mrepair_fuse_startword_o1; - output fabric_mrepair_fuse_startword_o10; - output fabric_mrepair_fuse_startword_o11; - output fabric_mrepair_fuse_startword_o12; - output fabric_mrepair_fuse_startword_o13; - output fabric_mrepair_fuse_startword_o14; - output fabric_mrepair_fuse_startword_o15; - output fabric_mrepair_fuse_startword_o16; - output fabric_mrepair_fuse_startword_o2; - output fabric_mrepair_fuse_startword_o3; - output fabric_mrepair_fuse_startword_o4; - output fabric_mrepair_fuse_startword_o5; - output fabric_mrepair_fuse_startword_o6; - output fabric_mrepair_fuse_startword_o7; - output fabric_mrepair_fuse_startword_o8; - output fabric_mrepair_fuse_startword_o9; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input fabric_mrepair_fuse_tst_scanin_i1; - input fabric_mrepair_fuse_tst_scanin_i2; - input fabric_mrepair_fuse_tst_scanin_i3; - input fabric_mrepair_fuse_tst_scanin_i4; - input fabric_mrepair_fuse_tst_scanin_i5; - input fabric_mrepair_fuse_tstscanenable_i; - output fabric_mrepair_fuse_tstscanout_o1; - output fabric_mrepair_fuse_tstscanout_o2; - output fabric_mrepair_fuse_tstscanout_o3; - output fabric_mrepair_fuse_tstscanout_o4; - output fabric_mrepair_fuse_tstscanout_o5; - output fabric_mrepair_fuse_wlromout_o1; - output fabric_mrepair_fuse_wlromout_o10; - output fabric_mrepair_fuse_wlromout_o2; - output fabric_mrepair_fuse_wlromout_o3; - output fabric_mrepair_fuse_wlromout_o4; - output fabric_mrepair_fuse_wlromout_o5; - output fabric_mrepair_fuse_wlromout_o6; - output fabric_mrepair_fuse_wlromout_o7; - output fabric_mrepair_fuse_wlromout_o8; - output fabric_mrepair_fuse_wlromout_o9; - input fabric_mrepair_fuse_wordlock_i; - input fabric_mrepair_initn_i; - input fabric_mrepair_mode_i1; - input fabric_mrepair_mode_i2; - input fabric_mrepair_mode_i3; - input fabric_mrepair_mode_i4; - input fabric_mrepair_por_i; - input fabric_mrepair_rst_n_i; - input fabric_otp_apb_addr_i1; - input fabric_otp_apb_addr_i10; - input fabric_otp_apb_addr_i11; - input fabric_otp_apb_addr_i12; - input fabric_otp_apb_addr_i13; - input fabric_otp_apb_addr_i14; - input fabric_otp_apb_addr_i15; - input fabric_otp_apb_addr_i16; - input fabric_otp_apb_addr_i17; - input fabric_otp_apb_addr_i18; - input fabric_otp_apb_addr_i19; - input fabric_otp_apb_addr_i2; - input fabric_otp_apb_addr_i20; - input fabric_otp_apb_addr_i21; - input fabric_otp_apb_addr_i22; - input fabric_otp_apb_addr_i23; - input fabric_otp_apb_addr_i24; - input fabric_otp_apb_addr_i25; - input fabric_otp_apb_addr_i26; - input fabric_otp_apb_addr_i27; - input fabric_otp_apb_addr_i28; - input fabric_otp_apb_addr_i29; - input fabric_otp_apb_addr_i3; - input fabric_otp_apb_addr_i30; - input fabric_otp_apb_addr_i31; - input fabric_otp_apb_addr_i32; - input fabric_otp_apb_addr_i4; - input fabric_otp_apb_addr_i5; - input fabric_otp_apb_addr_i6; - input fabric_otp_apb_addr_i7; - input fabric_otp_apb_addr_i8; - input fabric_otp_apb_addr_i9; - input fabric_otp_apb_enable_i; - output fabric_otp_apb_rdata_o1; - output fabric_otp_apb_rdata_o10; - output fabric_otp_apb_rdata_o11; - output fabric_otp_apb_rdata_o12; - output fabric_otp_apb_rdata_o13; - output fabric_otp_apb_rdata_o14; - output fabric_otp_apb_rdata_o15; - output fabric_otp_apb_rdata_o16; - output fabric_otp_apb_rdata_o17; - output fabric_otp_apb_rdata_o18; - output fabric_otp_apb_rdata_o19; - output fabric_otp_apb_rdata_o2; - output fabric_otp_apb_rdata_o20; - output fabric_otp_apb_rdata_o21; - output fabric_otp_apb_rdata_o22; - output fabric_otp_apb_rdata_o23; - output fabric_otp_apb_rdata_o24; - output fabric_otp_apb_rdata_o25; - output fabric_otp_apb_rdata_o26; - output fabric_otp_apb_rdata_o27; - output fabric_otp_apb_rdata_o28; - output fabric_otp_apb_rdata_o29; - output fabric_otp_apb_rdata_o3; - output fabric_otp_apb_rdata_o30; - output fabric_otp_apb_rdata_o31; - output fabric_otp_apb_rdata_o32; - output fabric_otp_apb_rdata_o4; - output fabric_otp_apb_rdata_o5; - output fabric_otp_apb_rdata_o6; - output fabric_otp_apb_rdata_o7; - output fabric_otp_apb_rdata_o8; - output fabric_otp_apb_rdata_o9; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input fabric_otp_apb_wdata_i1; - input fabric_otp_apb_wdata_i10; - input fabric_otp_apb_wdata_i11; - input fabric_otp_apb_wdata_i12; - input fabric_otp_apb_wdata_i13; - input fabric_otp_apb_wdata_i14; - input fabric_otp_apb_wdata_i15; - input fabric_otp_apb_wdata_i16; - input fabric_otp_apb_wdata_i17; - input fabric_otp_apb_wdata_i18; - input fabric_otp_apb_wdata_i19; - input fabric_otp_apb_wdata_i2; - input fabric_otp_apb_wdata_i20; - input fabric_otp_apb_wdata_i21; - input fabric_otp_apb_wdata_i22; - input fabric_otp_apb_wdata_i23; - input fabric_otp_apb_wdata_i24; - input fabric_otp_apb_wdata_i25; - input fabric_otp_apb_wdata_i26; - input fabric_otp_apb_wdata_i27; - input fabric_otp_apb_wdata_i28; - input fabric_otp_apb_wdata_i29; - input fabric_otp_apb_wdata_i3; - input fabric_otp_apb_wdata_i30; - input fabric_otp_apb_wdata_i31; - input fabric_otp_apb_wdata_i32; - input fabric_otp_apb_wdata_i4; - input fabric_otp_apb_wdata_i5; - input fabric_otp_apb_wdata_i6; - input fabric_otp_apb_wdata_i7; - input fabric_otp_apb_wdata_i8; - input fabric_otp_apb_wdata_i9; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_rstn_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output fabric_otp_security_bist_fail1_o1; - output fabric_otp_security_bist_fail1_o2; - output fabric_otp_security_bist_fail1_o3; - output fabric_otp_security_bist_fail1_o4; - output fabric_otp_security_bist_fail1_o5; - output fabric_otp_security_bist_fail1_o6; - output fabric_otp_security_bist_fail1_o7; - output fabric_otp_security_bist_fail1_o8; - output fabric_otp_security_bist_fail2_o1; - output fabric_otp_security_bist_fail2_o2; - output fabric_otp_security_bist_fail2_o3; - output fabric_otp_security_bist_fail2_o4; - output fabric_otp_security_bist_fail2_o5; - output fabric_otp_security_bist_fail2_o6; - output fabric_otp_security_bist_fail2_o7; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input fabric_otp_security_scanin_i1; - input fabric_otp_security_scanin_i2; - input fabric_otp_security_scanin_i3; - input fabric_otp_security_scanin_i4; - input fabric_otp_security_scanin_i5; - output fabric_otp_security_scanout_o1; - output fabric_otp_security_scanout_o2; - output fabric_otp_security_scanout_o3; - output fabric_otp_security_scanout_o4; - output fabric_otp_security_scanout_o5; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input fabric_otp_user_add_i1; - input fabric_otp_user_add_i2; - input fabric_otp_user_add_i3; - input fabric_otp_user_add_i4; - input fabric_otp_user_add_i5; - input fabric_otp_user_add_i6; - input fabric_otp_user_add_i7; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output fabric_otp_user_bist1fail_o1; - output fabric_otp_user_bist1fail_o2; - output fabric_otp_user_bist1fail_o3; - output fabric_otp_user_bist1fail_o4; - output fabric_otp_user_bist1fail_o5; - output fabric_otp_user_bist1fail_o6; - output fabric_otp_user_bist1fail_o7; - output fabric_otp_user_bist1fail_o8; - output fabric_otp_user_bist2fail_o1; - output fabric_otp_user_bist2fail_o2; - output fabric_otp_user_bist2fail_o3; - output fabric_otp_user_bist2fail_o4; - output fabric_otp_user_bist2fail_o5; - output fabric_otp_user_bist2fail_o6; - output fabric_otp_user_bist2fail_o7; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_configreg_i1; - input fabric_otp_user_configreg_i10; - input fabric_otp_user_configreg_i11; - input fabric_otp_user_configreg_i12; - input fabric_otp_user_configreg_i13; - input fabric_otp_user_configreg_i14; - input fabric_otp_user_configreg_i15; - input fabric_otp_user_configreg_i16; - input fabric_otp_user_configreg_i17; - input fabric_otp_user_configreg_i18; - input fabric_otp_user_configreg_i19; - input fabric_otp_user_configreg_i2; - input fabric_otp_user_configreg_i20; - input fabric_otp_user_configreg_i21; - input fabric_otp_user_configreg_i22; - input fabric_otp_user_configreg_i23; - input fabric_otp_user_configreg_i24; - input fabric_otp_user_configreg_i25; - input fabric_otp_user_configreg_i26; - input fabric_otp_user_configreg_i27; - input fabric_otp_user_configreg_i28; - input fabric_otp_user_configreg_i29; - input fabric_otp_user_configreg_i3; - input fabric_otp_user_configreg_i30; - input fabric_otp_user_configreg_i31; - input fabric_otp_user_configreg_i32; - input fabric_otp_user_configreg_i4; - input fabric_otp_user_configreg_i5; - input fabric_otp_user_configreg_i6; - input fabric_otp_user_configreg_i7; - input fabric_otp_user_configreg_i8; - input fabric_otp_user_configreg_i9; - output fabric_otp_user_ded_o; - input fabric_otp_user_din_i1; - input fabric_otp_user_din_i10; - input fabric_otp_user_din_i11; - input fabric_otp_user_din_i12; - input fabric_otp_user_din_i13; - input fabric_otp_user_din_i14; - input fabric_otp_user_din_i15; - input fabric_otp_user_din_i16; - input fabric_otp_user_din_i17; - input fabric_otp_user_din_i18; - input fabric_otp_user_din_i19; - input fabric_otp_user_din_i2; - input fabric_otp_user_din_i20; - input fabric_otp_user_din_i21; - input fabric_otp_user_din_i22; - input fabric_otp_user_din_i23; - input fabric_otp_user_din_i24; - input fabric_otp_user_din_i25; - input fabric_otp_user_din_i26; - input fabric_otp_user_din_i27; - input fabric_otp_user_din_i28; - input fabric_otp_user_din_i29; - input fabric_otp_user_din_i3; - input fabric_otp_user_din_i30; - input fabric_otp_user_din_i31; - input fabric_otp_user_din_i32; - input fabric_otp_user_din_i33; - input fabric_otp_user_din_i34; - input fabric_otp_user_din_i35; - input fabric_otp_user_din_i36; - input fabric_otp_user_din_i37; - input fabric_otp_user_din_i38; - input fabric_otp_user_din_i39; - input fabric_otp_user_din_i4; - input fabric_otp_user_din_i5; - input fabric_otp_user_din_i6; - input fabric_otp_user_din_i7; - input fabric_otp_user_din_i8; - input fabric_otp_user_din_i9; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output fabric_otp_user_dout_o1; - output fabric_otp_user_dout_o10; - output fabric_otp_user_dout_o11; - output fabric_otp_user_dout_o12; - output fabric_otp_user_dout_o13; - output fabric_otp_user_dout_o14; - output fabric_otp_user_dout_o15; - output fabric_otp_user_dout_o16; - output fabric_otp_user_dout_o17; - output fabric_otp_user_dout_o18; - output fabric_otp_user_dout_o19; - output fabric_otp_user_dout_o2; - output fabric_otp_user_dout_o20; - output fabric_otp_user_dout_o21; - output fabric_otp_user_dout_o22; - output fabric_otp_user_dout_o23; - output fabric_otp_user_dout_o24; - output fabric_otp_user_dout_o25; - output fabric_otp_user_dout_o26; - output fabric_otp_user_dout_o27; - output fabric_otp_user_dout_o28; - output fabric_otp_user_dout_o29; - output fabric_otp_user_dout_o3; - output fabric_otp_user_dout_o30; - output fabric_otp_user_dout_o31; - output fabric_otp_user_dout_o32; - output fabric_otp_user_dout_o33; - output fabric_otp_user_dout_o34; - output fabric_otp_user_dout_o35; - output fabric_otp_user_dout_o36; - output fabric_otp_user_dout_o37; - output fabric_otp_user_dout_o38; - output fabric_otp_user_dout_o39; - output fabric_otp_user_dout_o4; - output fabric_otp_user_dout_o40; - output fabric_otp_user_dout_o41; - output fabric_otp_user_dout_o5; - output fabric_otp_user_dout_o6; - output fabric_otp_user_dout_o7; - output fabric_otp_user_dout_o8; - output fabric_otp_user_dout_o9; - input fabric_otp_user_eccbypass_i; - output fabric_otp_user_flagstate_o1; - output fabric_otp_user_flagstate_o2; - output fabric_otp_user_flagstate_o3; - output fabric_otp_user_flagstate_o4; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input fabric_otp_user_prgwidth_i1; - input fabric_otp_user_prgwidth_i2; - input fabric_otp_user_prgwidth_i3; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output fabric_otp_user_startword_o1; - output fabric_otp_user_startword_o10; - output fabric_otp_user_startword_o11; - output fabric_otp_user_startword_o12; - output fabric_otp_user_startword_o13; - output fabric_otp_user_startword_o14; - output fabric_otp_user_startword_o15; - output fabric_otp_user_startword_o16; - output fabric_otp_user_startword_o2; - output fabric_otp_user_startword_o3; - output fabric_otp_user_startword_o4; - output fabric_otp_user_startword_o5; - output fabric_otp_user_startword_o6; - output fabric_otp_user_startword_o7; - output fabric_otp_user_startword_o8; - output fabric_otp_user_startword_o9; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input fabric_otp_user_tst_scanin_i1; - input fabric_otp_user_tst_scanin_i2; - input fabric_otp_user_tst_scanin_i3; - input fabric_otp_user_tst_scanin_i4; - input fabric_otp_user_tst_scanin_i5; - output fabric_otp_user_tst_scanout_o1; - output fabric_otp_user_tst_scanout_o2; - output fabric_otp_user_tst_scanout_o3; - output fabric_otp_user_tst_scanout_o4; - output fabric_otp_user_tst_scanout_o5; - output fabric_otp_user_wlromout_o1; - output fabric_otp_user_wlromout_o10; - output fabric_otp_user_wlromout_o2; - output fabric_otp_user_wlromout_o3; - output fabric_otp_user_wlromout_o4; - output fabric_otp_user_wlromout_o5; - output fabric_otp_user_wlromout_o6; - output fabric_otp_user_wlromout_o7; - output fabric_otp_user_wlromout_o8; - output fabric_otp_user_wlromout_o9; - input fabric_otp_user_wordlock_i; - input fabric_parusr_cs_i; - input fabric_parusr_data_i1; - input fabric_parusr_data_i10; - input fabric_parusr_data_i11; - input fabric_parusr_data_i12; - input fabric_parusr_data_i13; - input fabric_parusr_data_i14; - input fabric_parusr_data_i15; - input fabric_parusr_data_i16; - input fabric_parusr_data_i2; - input fabric_parusr_data_i3; - input fabric_parusr_data_i4; - input fabric_parusr_data_i5; - input fabric_parusr_data_i6; - input fabric_parusr_data_i7; - input fabric_parusr_data_i8; - input fabric_parusr_data_i9; - output fabric_parusr_data_o1; - output fabric_parusr_data_o10; - output fabric_parusr_data_o11; - output fabric_parusr_data_o12; - output fabric_parusr_data_o13; - output fabric_parusr_data_o14; - output fabric_parusr_data_o15; - output fabric_parusr_data_o16; - output fabric_parusr_data_o2; - output fabric_parusr_data_o3; - output fabric_parusr_data_o4; - output fabric_parusr_data_o5; - output fabric_parusr_data_o6; - output fabric_parusr_data_o7; - output fabric_parusr_data_o8; - output fabric_parusr_data_o9; - output fabric_parusr_data_val_o; - input fabric_parusr_type_i1; - input fabric_parusr_type_i2; - input fabric_pd_active_i1; - input fabric_pd_active_i10; - input fabric_pd_active_i11; - input fabric_pd_active_i12; - input fabric_pd_active_i13; - input fabric_pd_active_i14; - input fabric_pd_active_i15; - input fabric_pd_active_i16; - input fabric_pd_active_i17; - input fabric_pd_active_i18; - input fabric_pd_active_i19; - input fabric_pd_active_i2; - input fabric_pd_active_i20; - input fabric_pd_active_i21; - input fabric_pd_active_i22; - input fabric_pd_active_i23; - input fabric_pd_active_i24; - input fabric_pd_active_i3; - input fabric_pd_active_i4; - input fabric_pd_active_i5; - input fabric_pd_active_i6; - input fabric_pd_active_i7; - input fabric_pd_active_i8; - input fabric_pd_active_i9; - output fabric_pd_ready_o1; - output fabric_pd_ready_o10; - output fabric_pd_ready_o11; - output fabric_pd_ready_o12; - output fabric_pd_ready_o13; - output fabric_pd_ready_o14; - output fabric_pd_ready_o15; - output fabric_pd_ready_o16; - output fabric_pd_ready_o17; - output fabric_pd_ready_o18; - output fabric_pd_ready_o19; - output fabric_pd_ready_o2; - output fabric_pd_ready_o20; - output fabric_pd_ready_o21; - output fabric_pd_ready_o22; - output fabric_pd_ready_o23; - output fabric_pd_ready_o24; - output fabric_pd_ready_o3; - output fabric_pd_ready_o4; - output fabric_pd_ready_o5; - output fabric_pd_ready_o6; - output fabric_pd_ready_o7; - output fabric_pd_ready_o8; - output fabric_pd_ready_o9; - input fabric_shift_en_i1; - input fabric_shift_en_i10; - input fabric_shift_en_i11; - input fabric_shift_en_i12; - input fabric_shift_en_i13; - input fabric_shift_en_i14; - input fabric_shift_en_i15; - input fabric_shift_en_i16; - input fabric_shift_en_i17; - input fabric_shift_en_i18; - input fabric_shift_en_i19; - input fabric_shift_en_i2; - input fabric_shift_en_i20; - input fabric_shift_en_i21; - input fabric_shift_en_i22; - input fabric_shift_en_i23; - input fabric_shift_en_i24; - input fabric_shift_en_i3; - input fabric_shift_en_i4; - input fabric_shift_en_i5; - input fabric_shift_en_i6; - input fabric_shift_en_i7; - input fabric_shift_en_i8; - input fabric_shift_en_i9; - output fabric_shift_en_to_bist_o1; - output fabric_shift_en_to_bist_o10; - output fabric_shift_en_to_bist_o11; - output fabric_shift_en_to_bist_o12; - output fabric_shift_en_to_bist_o13; - output fabric_shift_en_to_bist_o14; - output fabric_shift_en_to_bist_o15; - output fabric_shift_en_to_bist_o16; - output fabric_shift_en_to_bist_o17; - output fabric_shift_en_to_bist_o18; - output fabric_shift_en_to_bist_o19; - output fabric_shift_en_to_bist_o2; - output fabric_shift_en_to_bist_o20; - output fabric_shift_en_to_bist_o21; - output fabric_shift_en_to_bist_o22; - output fabric_shift_en_to_bist_o23; - output fabric_shift_en_to_bist_o24; - output fabric_shift_en_to_bist_o3; - output fabric_shift_en_to_bist_o4; - output fabric_shift_en_to_bist_o5; - output fabric_shift_en_to_bist_o6; - output fabric_shift_en_to_bist_o7; - output fabric_shift_en_to_bist_o8; - output fabric_shift_en_to_bist_o9; - input fabric_sif_load_en_i1; - input fabric_sif_load_en_i10; - input fabric_sif_load_en_i11; - input fabric_sif_load_en_i12; - input fabric_sif_load_en_i13; - input fabric_sif_load_en_i14; - input fabric_sif_load_en_i15; - input fabric_sif_load_en_i16; - input fabric_sif_load_en_i17; - input fabric_sif_load_en_i18; - input fabric_sif_load_en_i19; - input fabric_sif_load_en_i2; - input fabric_sif_load_en_i20; - input fabric_sif_load_en_i21; - input fabric_sif_load_en_i22; - input fabric_sif_load_en_i23; - input fabric_sif_load_en_i24; - input fabric_sif_load_en_i3; - input fabric_sif_load_en_i4; - input fabric_sif_load_en_i5; - input fabric_sif_load_en_i6; - input fabric_sif_load_en_i7; - input fabric_sif_load_en_i8; - input fabric_sif_load_en_i9; - output fabric_sif_load_en_to_bist_o1; - output fabric_sif_load_en_to_bist_o10; - output fabric_sif_load_en_to_bist_o11; - output fabric_sif_load_en_to_bist_o12; - output fabric_sif_load_en_to_bist_o13; - output fabric_sif_load_en_to_bist_o14; - output fabric_sif_load_en_to_bist_o15; - output fabric_sif_load_en_to_bist_o16; - output fabric_sif_load_en_to_bist_o17; - output fabric_sif_load_en_to_bist_o18; - output fabric_sif_load_en_to_bist_o19; - output fabric_sif_load_en_to_bist_o2; - output fabric_sif_load_en_to_bist_o20; - output fabric_sif_load_en_to_bist_o21; - output fabric_sif_load_en_to_bist_o22; - output fabric_sif_load_en_to_bist_o23; - output fabric_sif_load_en_to_bist_o24; - output fabric_sif_load_en_to_bist_o3; - output fabric_sif_load_en_to_bist_o4; - output fabric_sif_load_en_to_bist_o5; - output fabric_sif_load_en_to_bist_o6; - output fabric_sif_load_en_to_bist_o7; - output fabric_sif_load_en_to_bist_o8; - output fabric_sif_load_en_to_bist_o9; - input fabric_sif_reg_en_i1; - input fabric_sif_reg_en_i10; - input fabric_sif_reg_en_i100; - input fabric_sif_reg_en_i101; - input fabric_sif_reg_en_i102; - input fabric_sif_reg_en_i103; - input fabric_sif_reg_en_i104; - input fabric_sif_reg_en_i105; - input fabric_sif_reg_en_i106; - input fabric_sif_reg_en_i107; - input fabric_sif_reg_en_i108; - input fabric_sif_reg_en_i109; - input fabric_sif_reg_en_i11; - input fabric_sif_reg_en_i110; - input fabric_sif_reg_en_i111; - input fabric_sif_reg_en_i112; - input fabric_sif_reg_en_i113; - input fabric_sif_reg_en_i114; - input fabric_sif_reg_en_i115; - input fabric_sif_reg_en_i116; - input fabric_sif_reg_en_i117; - input fabric_sif_reg_en_i118; - input fabric_sif_reg_en_i119; - input fabric_sif_reg_en_i12; - input fabric_sif_reg_en_i120; - input fabric_sif_reg_en_i13; - input fabric_sif_reg_en_i14; - input fabric_sif_reg_en_i15; - input fabric_sif_reg_en_i16; - input fabric_sif_reg_en_i17; - input fabric_sif_reg_en_i18; - input fabric_sif_reg_en_i19; - input fabric_sif_reg_en_i2; - input fabric_sif_reg_en_i20; - input fabric_sif_reg_en_i21; - input fabric_sif_reg_en_i22; - input fabric_sif_reg_en_i23; - input fabric_sif_reg_en_i24; - input fabric_sif_reg_en_i25; - input fabric_sif_reg_en_i26; - input fabric_sif_reg_en_i27; - input fabric_sif_reg_en_i28; - input fabric_sif_reg_en_i29; - input fabric_sif_reg_en_i3; - input fabric_sif_reg_en_i30; - input fabric_sif_reg_en_i31; - input fabric_sif_reg_en_i32; - input fabric_sif_reg_en_i33; - input fabric_sif_reg_en_i34; - input fabric_sif_reg_en_i35; - input fabric_sif_reg_en_i36; - input fabric_sif_reg_en_i37; - input fabric_sif_reg_en_i38; - input fabric_sif_reg_en_i39; - input fabric_sif_reg_en_i4; - input fabric_sif_reg_en_i40; - input fabric_sif_reg_en_i41; - input fabric_sif_reg_en_i42; - input fabric_sif_reg_en_i43; - input fabric_sif_reg_en_i44; - input fabric_sif_reg_en_i45; - input fabric_sif_reg_en_i46; - input fabric_sif_reg_en_i47; - input fabric_sif_reg_en_i48; - input fabric_sif_reg_en_i49; - input fabric_sif_reg_en_i5; - input fabric_sif_reg_en_i50; - input fabric_sif_reg_en_i51; - input fabric_sif_reg_en_i52; - input fabric_sif_reg_en_i53; - input fabric_sif_reg_en_i54; - input fabric_sif_reg_en_i55; - input fabric_sif_reg_en_i56; - input fabric_sif_reg_en_i57; - input fabric_sif_reg_en_i58; - input fabric_sif_reg_en_i59; - input fabric_sif_reg_en_i6; - input fabric_sif_reg_en_i60; - input fabric_sif_reg_en_i61; - input fabric_sif_reg_en_i62; - input fabric_sif_reg_en_i63; - input fabric_sif_reg_en_i64; - input fabric_sif_reg_en_i65; - input fabric_sif_reg_en_i66; - input fabric_sif_reg_en_i67; - input fabric_sif_reg_en_i68; - input fabric_sif_reg_en_i69; - input fabric_sif_reg_en_i7; - input fabric_sif_reg_en_i70; - input fabric_sif_reg_en_i71; - input fabric_sif_reg_en_i72; - input fabric_sif_reg_en_i73; - input fabric_sif_reg_en_i74; - input fabric_sif_reg_en_i75; - input fabric_sif_reg_en_i76; - input fabric_sif_reg_en_i77; - input fabric_sif_reg_en_i78; - input fabric_sif_reg_en_i79; - input fabric_sif_reg_en_i8; - input fabric_sif_reg_en_i80; - input fabric_sif_reg_en_i81; - input fabric_sif_reg_en_i82; - input fabric_sif_reg_en_i83; - input fabric_sif_reg_en_i84; - input fabric_sif_reg_en_i85; - input fabric_sif_reg_en_i86; - input fabric_sif_reg_en_i87; - input fabric_sif_reg_en_i88; - input fabric_sif_reg_en_i89; - input fabric_sif_reg_en_i9; - input fabric_sif_reg_en_i90; - input fabric_sif_reg_en_i91; - input fabric_sif_reg_en_i92; - input fabric_sif_reg_en_i93; - input fabric_sif_reg_en_i94; - input fabric_sif_reg_en_i95; - input fabric_sif_reg_en_i96; - input fabric_sif_reg_en_i97; - input fabric_sif_reg_en_i98; - input fabric_sif_reg_en_i99; - output fabric_sif_reg_en_to_bist_o1; - output fabric_sif_reg_en_to_bist_o10; - output fabric_sif_reg_en_to_bist_o100; - output fabric_sif_reg_en_to_bist_o101; - output fabric_sif_reg_en_to_bist_o102; - output fabric_sif_reg_en_to_bist_o103; - output fabric_sif_reg_en_to_bist_o104; - output fabric_sif_reg_en_to_bist_o105; - output fabric_sif_reg_en_to_bist_o106; - output fabric_sif_reg_en_to_bist_o107; - output fabric_sif_reg_en_to_bist_o108; - output fabric_sif_reg_en_to_bist_o109; - output fabric_sif_reg_en_to_bist_o11; - output fabric_sif_reg_en_to_bist_o110; - output fabric_sif_reg_en_to_bist_o111; - output fabric_sif_reg_en_to_bist_o112; - output fabric_sif_reg_en_to_bist_o113; - output fabric_sif_reg_en_to_bist_o114; - output fabric_sif_reg_en_to_bist_o115; - output fabric_sif_reg_en_to_bist_o116; - output fabric_sif_reg_en_to_bist_o117; - output fabric_sif_reg_en_to_bist_o118; - output fabric_sif_reg_en_to_bist_o119; - output fabric_sif_reg_en_to_bist_o12; - output fabric_sif_reg_en_to_bist_o120; - output fabric_sif_reg_en_to_bist_o13; - output fabric_sif_reg_en_to_bist_o14; - output fabric_sif_reg_en_to_bist_o15; - output fabric_sif_reg_en_to_bist_o16; - output fabric_sif_reg_en_to_bist_o17; - output fabric_sif_reg_en_to_bist_o18; - output fabric_sif_reg_en_to_bist_o19; - output fabric_sif_reg_en_to_bist_o2; - output fabric_sif_reg_en_to_bist_o20; - output fabric_sif_reg_en_to_bist_o21; - output fabric_sif_reg_en_to_bist_o22; - output fabric_sif_reg_en_to_bist_o23; - output fabric_sif_reg_en_to_bist_o24; - output fabric_sif_reg_en_to_bist_o25; - output fabric_sif_reg_en_to_bist_o26; - output fabric_sif_reg_en_to_bist_o27; - output fabric_sif_reg_en_to_bist_o28; - output fabric_sif_reg_en_to_bist_o29; - output fabric_sif_reg_en_to_bist_o3; - output fabric_sif_reg_en_to_bist_o30; - output fabric_sif_reg_en_to_bist_o31; - output fabric_sif_reg_en_to_bist_o32; - output fabric_sif_reg_en_to_bist_o33; - output fabric_sif_reg_en_to_bist_o34; - output fabric_sif_reg_en_to_bist_o35; - output fabric_sif_reg_en_to_bist_o36; - output fabric_sif_reg_en_to_bist_o37; - output fabric_sif_reg_en_to_bist_o38; - output fabric_sif_reg_en_to_bist_o39; - output fabric_sif_reg_en_to_bist_o4; - output fabric_sif_reg_en_to_bist_o40; - output fabric_sif_reg_en_to_bist_o41; - output fabric_sif_reg_en_to_bist_o42; - output fabric_sif_reg_en_to_bist_o43; - output fabric_sif_reg_en_to_bist_o44; - output fabric_sif_reg_en_to_bist_o45; - output fabric_sif_reg_en_to_bist_o46; - output fabric_sif_reg_en_to_bist_o47; - output fabric_sif_reg_en_to_bist_o48; - output fabric_sif_reg_en_to_bist_o49; - output fabric_sif_reg_en_to_bist_o5; - output fabric_sif_reg_en_to_bist_o50; - output fabric_sif_reg_en_to_bist_o51; - output fabric_sif_reg_en_to_bist_o52; - output fabric_sif_reg_en_to_bist_o53; - output fabric_sif_reg_en_to_bist_o54; - output fabric_sif_reg_en_to_bist_o55; - output fabric_sif_reg_en_to_bist_o56; - output fabric_sif_reg_en_to_bist_o57; - output fabric_sif_reg_en_to_bist_o58; - output fabric_sif_reg_en_to_bist_o59; - output fabric_sif_reg_en_to_bist_o6; - output fabric_sif_reg_en_to_bist_o60; - output fabric_sif_reg_en_to_bist_o61; - output fabric_sif_reg_en_to_bist_o62; - output fabric_sif_reg_en_to_bist_o63; - output fabric_sif_reg_en_to_bist_o64; - output fabric_sif_reg_en_to_bist_o65; - output fabric_sif_reg_en_to_bist_o66; - output fabric_sif_reg_en_to_bist_o67; - output fabric_sif_reg_en_to_bist_o68; - output fabric_sif_reg_en_to_bist_o69; - output fabric_sif_reg_en_to_bist_o7; - output fabric_sif_reg_en_to_bist_o70; - output fabric_sif_reg_en_to_bist_o71; - output fabric_sif_reg_en_to_bist_o72; - output fabric_sif_reg_en_to_bist_o73; - output fabric_sif_reg_en_to_bist_o74; - output fabric_sif_reg_en_to_bist_o75; - output fabric_sif_reg_en_to_bist_o76; - output fabric_sif_reg_en_to_bist_o77; - output fabric_sif_reg_en_to_bist_o78; - output fabric_sif_reg_en_to_bist_o79; - output fabric_sif_reg_en_to_bist_o8; - output fabric_sif_reg_en_to_bist_o80; - output fabric_sif_reg_en_to_bist_o81; - output fabric_sif_reg_en_to_bist_o82; - output fabric_sif_reg_en_to_bist_o83; - output fabric_sif_reg_en_to_bist_o84; - output fabric_sif_reg_en_to_bist_o85; - output fabric_sif_reg_en_to_bist_o86; - output fabric_sif_reg_en_to_bist_o87; - output fabric_sif_reg_en_to_bist_o88; - output fabric_sif_reg_en_to_bist_o89; - output fabric_sif_reg_en_to_bist_o9; - output fabric_sif_reg_en_to_bist_o90; - output fabric_sif_reg_en_to_bist_o91; - output fabric_sif_reg_en_to_bist_o92; - output fabric_sif_reg_en_to_bist_o93; - output fabric_sif_reg_en_to_bist_o94; - output fabric_sif_reg_en_to_bist_o95; - output fabric_sif_reg_en_to_bist_o96; - output fabric_sif_reg_en_to_bist_o97; - output fabric_sif_reg_en_to_bist_o98; - output fabric_sif_reg_en_to_bist_o99; - input fabric_sif_update_en_i1; - input fabric_sif_update_en_i10; - input fabric_sif_update_en_i11; - input fabric_sif_update_en_i12; - input fabric_sif_update_en_i13; - input fabric_sif_update_en_i14; - input fabric_sif_update_en_i15; - input fabric_sif_update_en_i16; - input fabric_sif_update_en_i17; - input fabric_sif_update_en_i18; - input fabric_sif_update_en_i19; - input fabric_sif_update_en_i2; - input fabric_sif_update_en_i20; - input fabric_sif_update_en_i21; - input fabric_sif_update_en_i22; - input fabric_sif_update_en_i23; - input fabric_sif_update_en_i24; - input fabric_sif_update_en_i3; - input fabric_sif_update_en_i4; - input fabric_sif_update_en_i5; - input fabric_sif_update_en_i6; - input fabric_sif_update_en_i7; - input fabric_sif_update_en_i8; - input fabric_sif_update_en_i9; - output fabric_sif_update_en_to_bist_o1; - output fabric_sif_update_en_to_bist_o10; - output fabric_sif_update_en_to_bist_o11; - output fabric_sif_update_en_to_bist_o12; - output fabric_sif_update_en_to_bist_o13; - output fabric_sif_update_en_to_bist_o14; - output fabric_sif_update_en_to_bist_o15; - output fabric_sif_update_en_to_bist_o16; - output fabric_sif_update_en_to_bist_o17; - output fabric_sif_update_en_to_bist_o18; - output fabric_sif_update_en_to_bist_o19; - output fabric_sif_update_en_to_bist_o2; - output fabric_sif_update_en_to_bist_o20; - output fabric_sif_update_en_to_bist_o21; - output fabric_sif_update_en_to_bist_o22; - output fabric_sif_update_en_to_bist_o23; - output fabric_sif_update_en_to_bist_o24; - output fabric_sif_update_en_to_bist_o3; - output fabric_sif_update_en_to_bist_o4; - output fabric_sif_update_en_to_bist_o5; - output fabric_sif_update_en_to_bist_o6; - output fabric_sif_update_en_to_bist_o7; - output fabric_sif_update_en_to_bist_o8; - output fabric_sif_update_en_to_bist_o9; - input fabric_spare_i1; - input fabric_spare_i2; - input fabric_spare_i3; - output fabric_status_cold_start_o; - output fabric_system_data_from_mem_bist_o1; - output fabric_system_data_from_mem_bist_o10; - output fabric_system_data_from_mem_bist_o11; - output fabric_system_data_from_mem_bist_o12; - output fabric_system_data_from_mem_bist_o13; - output fabric_system_data_from_mem_bist_o14; - output fabric_system_data_from_mem_bist_o15; - output fabric_system_data_from_mem_bist_o16; - output fabric_system_data_from_mem_bist_o17; - output fabric_system_data_from_mem_bist_o18; - output fabric_system_data_from_mem_bist_o19; - output fabric_system_data_from_mem_bist_o2; - output fabric_system_data_from_mem_bist_o20; - output fabric_system_data_from_mem_bist_o21; - output fabric_system_data_from_mem_bist_o22; - output fabric_system_data_from_mem_bist_o23; - output fabric_system_data_from_mem_bist_o24; - output fabric_system_data_from_mem_bist_o3; - output fabric_system_data_from_mem_bist_o4; - output fabric_system_data_from_mem_bist_o5; - output fabric_system_data_from_mem_bist_o6; - output fabric_system_data_from_mem_bist_o7; - output fabric_system_data_from_mem_bist_o8; - output fabric_system_data_from_mem_bist_o9; - input fabric_system_data_to_mem_bist_i1; - input fabric_system_data_to_mem_bist_i10; - input fabric_system_data_to_mem_bist_i11; - input fabric_system_data_to_mem_bist_i12; - input fabric_system_data_to_mem_bist_i13; - input fabric_system_data_to_mem_bist_i14; - input fabric_system_data_to_mem_bist_i15; - input fabric_system_data_to_mem_bist_i16; - input fabric_system_data_to_mem_bist_i17; - input fabric_system_data_to_mem_bist_i18; - input fabric_system_data_to_mem_bist_i19; - input fabric_system_data_to_mem_bist_i2; - input fabric_system_data_to_mem_bist_i20; - input fabric_system_data_to_mem_bist_i21; - input fabric_system_data_to_mem_bist_i22; - input fabric_system_data_to_mem_bist_i23; - input fabric_system_data_to_mem_bist_i24; - input fabric_system_data_to_mem_bist_i3; - input fabric_system_data_to_mem_bist_i4; - input fabric_system_data_to_mem_bist_i5; - input fabric_system_data_to_mem_bist_i6; - input fabric_system_data_to_mem_bist_i7; - input fabric_system_data_to_mem_bist_i8; - input fabric_system_data_to_mem_bist_i9; - output fabric_system_dataready_o; - input fabric_tst_atpg_mrepair_i; - input fabric_user_data_i1; - input fabric_user_data_i10; - input fabric_user_data_i11; - input fabric_user_data_i12; - input fabric_user_data_i13; - input fabric_user_data_i14; - input fabric_user_data_i15; - input fabric_user_data_i16; - input fabric_user_data_i17; - input fabric_user_data_i18; - input fabric_user_data_i19; - input fabric_user_data_i2; - input fabric_user_data_i20; - input fabric_user_data_i21; - input fabric_user_data_i22; - input fabric_user_data_i23; - input fabric_user_data_i24; - input fabric_user_data_i25; - input fabric_user_data_i26; - input fabric_user_data_i27; - input fabric_user_data_i28; - input fabric_user_data_i29; - input fabric_user_data_i3; - input fabric_user_data_i30; - input fabric_user_data_i31; - input fabric_user_data_i32; - input fabric_user_data_i4; - input fabric_user_data_i5; - input fabric_user_data_i6; - input fabric_user_data_i7; - input fabric_user_data_i8; - input fabric_user_data_i9; - output fabric_user_data_o1; - output fabric_user_data_o10; - output fabric_user_data_o11; - output fabric_user_data_o12; - output fabric_user_data_o13; - output fabric_user_data_o14; - output fabric_user_data_o15; - output fabric_user_data_o16; - output fabric_user_data_o17; - output fabric_user_data_o18; - output fabric_user_data_o19; - output fabric_user_data_o2; - output fabric_user_data_o20; - output fabric_user_data_o21; - output fabric_user_data_o22; - output fabric_user_data_o23; - output fabric_user_data_o24; - output fabric_user_data_o25; - output fabric_user_data_o26; - output fabric_user_data_o27; - output fabric_user_data_o28; - output fabric_user_data_o29; - output fabric_user_data_o3; - output fabric_user_data_o30; - output fabric_user_data_o31; - output fabric_user_data_o32; - output fabric_user_data_o4; - output fabric_user_data_o5; - output fabric_user_data_o6; - output fabric_user_data_o7; - output fabric_user_data_o8; - output fabric_user_data_o9; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_U_V1_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rstn_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i -, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i -, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_rst_n_i, fabric_mrepair_initn_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o, fabric_otp_security_bist_bad_o -, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_unmask_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_flag_ready_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o -, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o -, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o -, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i, fabric_parusr_data_i, fabric_parusr_data_o -, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_spare_i -, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_mrepair_fuse_configreg_i, fabric_system_data_to_mem_bist_i, fabric_otp_user_configreg_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o -); - input [31:0] fabric_ahb_direct_data_i; - output [31:0] fabric_ahb_direct_data_o; - output fabric_cfg_fabric_user_flag_o; - output fabric_cfg_fabric_user_unmask_o; - output [71:0] fabric_chip_status_o; - input [23:0] fabric_data_from_bist_i; - input fabric_data_from_system_i; - input fabric_data_shift_en_i; - output [23:0] fabric_data_to_bist_o; - output fabric_data_to_system_o; - output fabric_debug_access_reg_data_ready_o; - output [31:0] fabric_debug_bsec_core_status_o; - output [3:0] fabric_debug_cpt_retry_o; - output [3:0] fabric_debug_direct_permission_read_o; - output [3:0] fabric_debug_direct_permission_write_o; - output fabric_debug_error_o; - output [3:0] fabric_debug_frame_permission_frame_o; - output fabric_debug_frame_use_encryption_o; - output [2:0] fabric_debug_fsm_state_o; - output fabric_debug_key_correct_o; - output [3:0] fabric_debug_lifecycle_o; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output [2:0] fabric_debug_otpapb_state_o; - output [7:0] fabric_debug_otpboot_curr_addr_o; - output [2:0] fabric_debug_otpboot_state_o; - output [2:0] fabric_debug_otpmgmt_state_o; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - output fabric_decoder_init_ready_o; - input [31:0] fabric_direct_data_i; - output [31:0] fabric_direct_data_o; - input fabric_end_encoding_i; - output fabric_flag_error_o; - output fabric_flag_ready_o; - output fabric_flag_trigger_o; - output [2:0] fabric_fuse_status_o; - output [2:0] fabric_global_chip_status_o; - input [24:0] fabric_io_in_i; - input [24:0] fabric_io_oe_i; - output [24:0] fabric_io_out_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - output fabric_mrepair_fuse_ack_o; - input [6:0] fabric_mrepair_fuse_add_i; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output [7:0] fabric_mrepair_fuse_bist1fail_o; - output [6:0] fabric_mrepair_fuse_bist2fail_o; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - input [31:0] fabric_mrepair_fuse_configreg_i; - output fabric_mrepair_fuse_ded_o; - input [38:0] fabric_mrepair_fuse_din_i; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output [40:0] fabric_mrepair_fuse_dout_o; - input fabric_mrepair_fuse_eccbypass_i; - output [3:0] fabric_mrepair_fuse_flagstate_o; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input [2:0] fabric_mrepair_fuse_prgwidth_i; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output [15:0] fabric_mrepair_fuse_startword_o; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input [4:0] fabric_mrepair_fuse_tst_scanin_i; - input fabric_mrepair_fuse_tstscanenable_i; - output [4:0] fabric_mrepair_fuse_tstscanout_o; - output [9:0] fabric_mrepair_fuse_wlromout_o; - input fabric_mrepair_fuse_wordlock_i; - input fabric_mrepair_initn_i; - input [3:0] fabric_mrepair_mode_i; - input fabric_mrepair_por_i; - input fabric_mrepair_rst_n_i; - input [31:0] fabric_otp_apb_addr_i; - input fabric_otp_apb_enable_i; - output [31:0] fabric_otp_apb_rdata_o; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input [31:0] fabric_otp_apb_wdata_i; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_rstn_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output [7:0] fabric_otp_security_bist_fail1_o; - output [6:0] fabric_otp_security_bist_fail2_o; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input [4:0] fabric_otp_security_scanin_i; - output [4:0] fabric_otp_security_scanout_o; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input [6:0] fabric_otp_user_add_i; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output [7:0] fabric_otp_user_bist1fail_o; - output [6:0] fabric_otp_user_bist2fail_o; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input [31:0] fabric_otp_user_configreg_i; - output fabric_otp_user_ded_o; - input [38:0] fabric_otp_user_din_i; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output [40:0] fabric_otp_user_dout_o; - input fabric_otp_user_eccbypass_i; - output [3:0] fabric_otp_user_flagstate_o; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input [2:0] fabric_otp_user_prgwidth_i; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output [15:0] fabric_otp_user_startword_o; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input [4:0] fabric_otp_user_tst_scanin_i; - output [4:0] fabric_otp_user_tst_scanout_o; - output [9:0] fabric_otp_user_wlromout_o; - input fabric_otp_user_wordlock_i; - input fabric_parusr_cs_i; - input [15:0] fabric_parusr_data_i; - output [15:0] fabric_parusr_data_o; - output fabric_parusr_data_val_o; - input [1:0] fabric_parusr_type_i; - input [23:0] fabric_pd_active_i; - output [23:0] fabric_pd_ready_o; - input [23:0] fabric_shift_en_i; - output [23:0] fabric_shift_en_to_bist_o; - input [23:0] fabric_sif_load_en_i; - output [23:0] fabric_sif_load_en_to_bist_o; - input [119:0] fabric_sif_reg_en_i; - output [119:0] fabric_sif_reg_en_to_bist_o; - input [23:0] fabric_sif_update_en_i; - output [23:0] fabric_sif_update_en_to_bist_o; - input [2:0] fabric_spare_i; - output fabric_status_cold_start_o; - output [23:0] fabric_system_data_from_mem_bist_o; - input [23:0] fabric_system_data_to_mem_bist_i; - output fabric_system_dataready_o; - input fabric_tst_atpg_mrepair_i; - input [31:0] fabric_user_data_i; - output [31:0] fabric_user_data_o; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SERVICE_U_WRAP(fabric_otp_user_tst_scanenable_i, fabric_otp_cfg_loader_read_en_i, fabric_otp_security_force_pdn1_i, fabric_otp_security_scanenable_i, fabric_otp_cfg_clk_otpm_disable_i, fabric_otp_user_disturbcheck_i, fabric_mrepair_fuse_read_i, fabric_otp_user_rbact2_i, fabric_mrepair_fuse_eccbypass_i, fabric_otp_user_bistmode_i, fabric_otp_user_tm_i, fabric_otp_rst_i, fabric_mrepair_fuse_disturbchecked_i, fabric_otp_user_rbact1_i, fabric_mrepair_fuse_redbypass_i, fabric_otp_user_eccbypass_i, fabric_otp_user_redbypass_i, fabric_parusr_cs_i, fabric_mrepair_fuse_rbact2_i, fabric_data_from_system_i, fabric_otp_apb_enable_i -, fabric_mrepair_fuse_tm_i, fabric_otp_security_rbact2_i, fabric_otp_security_rbact1_i, fabric_otp_cfg_loader_write_en_i, fabric_mrepair_fuse_suppadd_i, fabric_mrepair_fuse_prog_i, fabric_otp_user_wordlock_i, fabric_otp_user_prog_i, fabric_otp_user_suppadd_i, fabric_mrepair_fuse_pdn_i, fabric_end_encoding_i, fabric_jtag_tdo_usr2_i, fabric_mrepair_fuse_wordlock_i, fabric_otp_user_read_i, fabric_mrepair_fuse_bistmode_i, fabric_jtag_tdo_usr1_i, fabric_otp_cfg_clk_fab_en_i, fabric_otp_apb_sel_i, fabric_mrepair_fuse_rbact1_i, fabric_otp_cfg_fabric_apb_en_i, fabric_data_shift_en_i -, fabric_lowskew_i21, fabric_otp_user_pdn_i, fabric_otp_apb_write_i, fabric_otp_security_testmode_i, fabric_tst_atpg_mrepair_i, fabric_mrepair_fuse_tstscanenable_i, fabric_otp_security_bistmode_i, fabric_lowskew_i22, fabric_lowskew_i23, fabric_lowskew_i20, fabric_mrepair_por_i, fabric_mrepair_cke_i, fabric_clk_otp_mux_i, fabric_mrepair_cke_force_i, fabric_mrepair_fuse_bbad_o, fabric_jtag_trst_n_o, fabric_otp_security_bist_end1_o, fabric_parusr_data_val_o, fabric_debug_lock_reg_o, fabric_debug_security_error_read_o, fabric_otp_user_locked_o -, fabric_otp_security_bist_bad_o, fabric_otp_user_pwok_o, fabric_otp_user_bend2_o, fabric_mrepair_fuse_ded_o, fabric_debug_access_reg_data_ready_o, fabric_debug_otp_reload_err_o, fabric_cfg_fabric_user_enable_o, fabric_decoder_init_ready_o, fabric_debug_security_boot_done_o, fabric_otp_user_calibrated_o, fabric_jtag_tms_o, fabric_debug_rst_soft_o, fabric_otp_user_ack_o, fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o, fabric_debug_otp_manager_read_otp_o, fabric_otp_user_sec_o, fabric_mrepair_fuse_bend1_o, fabric_otp_user_bbad_o, fabric_user_read_cycle_o, fabric_mrepair_fuse_disturbed_o, fabric_debug_key_correct_o -, fabric_otp_apb_ready_o, fabric_otp_user_progfail_o, fabric_mrepair_fuse_sec_o, fabric_mrepair_fuse_bend2_o, fabric_mrepair_fuse_ack_o, fabric_otp_security_ack_o, fabric_mrepair_fuse_progfail_o, fabric_jtag_tdi_o, fabric_lowskew_o3, fabric_lowskew_o5, fabric_lowskew_o4, fabric_debug_error_o, fabric_jtag_usr2_o, fabric_otp_user_disturbed_o, fabric_flag_trigger_o, fabric_otp_security_bist_end2_o, fabric_mrepair_fuse_locked_o, fabric_user_write_cycle_o, fabric_otp_user_ded_o, fabric_debug_otp_manager_read_done_o, fabric_debug_frame_use_encryption_o -, fabric_data_to_system_o, fabric_jtag_usr1_o, fabric_otp_user_bend1_o, fabric_mrepair_fuse_ready_o, fabric_mrepair_fuse_calibrated_o, fabric_system_dataready_o, fabric_mrepair_fuse_pwok_o, fabric_lowskew_o6, fabric_cfg_fabric_user_flag_o, fabric_status_cold_start_o, fabric_flag_error_o, fabric_otp_user_clock_frequency_range_i, fabric_parusr_enable_i, fabric_mrepair_mode_i, fabric_mrepair_fuse_add_i, fabric_mrepair_fuse_din_i, fabric_mrepair_fuse_tst_scanin_i, fabric_mrepair_fuse_prgwidth_i, fabric_mrepair_fuse_dout_o, fabric_mrepair_fuse_startword_o, fabric_mrepair_fuse_wlromout_o -, fabric_mrepair_fuse_bist1fail_o, fabric_mrepair_fuse_bist2fail_o, fabric_mrepair_fuse_tstscanout_o, fabric_mrepair_fuse_flagstate_o, fabric_otp_user_add_i, fabric_otp_user_din_i, fabric_otp_user_prgwidth_i, fabric_otp_user_tst_scanin_i, fabric_otp_user_bist1fail_o, fabric_otp_user_bist2fail_o, fabric_otp_user_dout_o, fabric_otp_user_flagstate_o, fabric_otp_user_startword_o, fabric_otp_user_tst_scanout_o, fabric_otp_user_wlromout_o, fabric_io_in_i, fabric_io_oe_i, fabric_io_out_o, fabric_user_data_i, fabric_user_data_o, fabric_parusr_type_i -, fabric_parusr_data_i, fabric_parusr_data_o, fabric_direct_data_i, fabric_direct_data_o, fabric_otp_apb_addr_i, fabric_otp_apb_wdata_i, fabric_otp_apb_rdata_o, fabric_otp_security_bist_fail1_o, fabric_otp_security_bist_fail2_o, fabric_otp_security_scanin_i, fabric_otp_security_scanout_o, fabric_flag_ready_TMR_o, fabric_debug_lifecycle_o, fabric_debug_fsm_state_o, fabric_debug_direct_permission_write_o, fabric_debug_direct_permission_read_o, fabric_debug_frame_permission_frame_o, fabric_debug_otpmgmt_state_o, fabric_debug_otpapb_state_o, fabric_debug_otpboot_state_o, fabric_debug_cpt_retry_o -, fabric_debug_bsec_core_status_o, fabric_debug_otpboot_curr_addr_o, fabric_sif_reg_en_i, fabric_data_from_bist_i, fabric_shift_en_i, fabric_ahb_direct_data_i, fabric_pd_active_i, fabric_sif_load_en_i, fabric_system_data_to_mem_bist_i, fabric_sif_update_en_i, fabric_sif_update_en_to_bist_o, fabric_data_to_bist_o, fabric_ahb_direct_data_o, fabric_global_chip_status_o, fabric_fuse_status_o, fabric_shift_en_to_bist_o, fabric_sif_reg_en_to_bist_o, fabric_system_data_from_mem_bist_o, fabric_chip_status_o, fabric_pd_ready_o, fabric_sif_load_en_to_bist_o -); - input [31:0] fabric_ahb_direct_data_i; - output [31:0] fabric_ahb_direct_data_o; - output fabric_cfg_fabric_user_enable_o; - output fabric_cfg_fabric_user_flag_o; - output [71:0] fabric_chip_status_o; - input fabric_clk_otp_mux_i; - input [23:0] fabric_data_from_bist_i; - input fabric_data_from_system_i; - input fabric_data_shift_en_i; - output [23:0] fabric_data_to_bist_o; - output fabric_data_to_system_o; - output fabric_debug_access_reg_data_ready_o; - output [31:0] fabric_debug_bsec_core_status_o; - output [3:0] fabric_debug_cpt_retry_o; - output [3:0] fabric_debug_direct_permission_read_o; - output [3:0] fabric_debug_direct_permission_write_o; - output fabric_debug_error_o; - output [3:0] fabric_debug_frame_permission_frame_o; - output fabric_debug_frame_use_encryption_o; - output [2:0] fabric_debug_fsm_state_o; - output fabric_debug_key_correct_o; - output [3:0] fabric_debug_lifecycle_o; - output fabric_debug_lock_reg_o; - output fabric_debug_otp_manager_read_done_o; - output fabric_debug_otp_manager_read_otp_o; - output fabric_debug_otp_reload_err_o; - output [2:0] fabric_debug_otpapb_state_o; - output [7:0] fabric_debug_otpboot_curr_addr_o; - output [2:0] fabric_debug_otpboot_state_o; - output [2:0] fabric_debug_otpmgmt_state_o; - output fabric_debug_rst_soft_o; - output fabric_debug_security_boot_done_o; - output fabric_debug_security_error_read_o; - output fabric_decoder_init_ready_o; - input [31:0] fabric_direct_data_i; - output [31:0] fabric_direct_data_o; - input fabric_end_encoding_i; - output fabric_flag_error_o; - output [2:0] fabric_flag_ready_TMR_o; - output fabric_flag_trigger_o; - output [2:0] fabric_fuse_status_o; - output [2:0] fabric_global_chip_status_o; - input [24:0] fabric_io_in_i; - input [24:0] fabric_io_oe_i; - output [24:0] fabric_io_out_o; - output fabric_jtag_tdi_o; - input fabric_jtag_tdo_usr1_i; - input fabric_jtag_tdo_usr2_i; - output fabric_jtag_tms_o; - output fabric_jtag_trst_n_o; - output fabric_jtag_usr1_o; - output fabric_jtag_usr2_o; - input fabric_lowskew_i20; - input fabric_lowskew_i21; - input fabric_lowskew_i22; - input fabric_lowskew_i23; - output fabric_lowskew_o3; - output fabric_lowskew_o4; - output fabric_lowskew_o5; - output fabric_lowskew_o6; - input fabric_mrepair_cke_force_i; - input fabric_mrepair_cke_i; - output fabric_mrepair_fuse_ack_o; - input [6:0] fabric_mrepair_fuse_add_i; - output fabric_mrepair_fuse_bbad_o; - output fabric_mrepair_fuse_bend1_o; - output fabric_mrepair_fuse_bend2_o; - output [7:0] fabric_mrepair_fuse_bist1fail_o; - output [6:0] fabric_mrepair_fuse_bist2fail_o; - input fabric_mrepair_fuse_bistmode_i; - output fabric_mrepair_fuse_calibrated_o; - output fabric_mrepair_fuse_ded_o; - input [38:0] fabric_mrepair_fuse_din_i; - input fabric_mrepair_fuse_disturbchecked_i; - output fabric_mrepair_fuse_disturbed_o; - output [40:0] fabric_mrepair_fuse_dout_o; - input fabric_mrepair_fuse_eccbypass_i; - output [3:0] fabric_mrepair_fuse_flagstate_o; - output fabric_mrepair_fuse_locked_o; - input fabric_mrepair_fuse_pdn_i; - output fabric_mrepair_fuse_prg_block_space_read_error_flag_q_o; - input [2:0] fabric_mrepair_fuse_prgwidth_i; - input fabric_mrepair_fuse_prog_i; - output fabric_mrepair_fuse_progfail_o; - output fabric_mrepair_fuse_pwok_o; - input fabric_mrepair_fuse_rbact1_i; - input fabric_mrepair_fuse_rbact2_i; - input fabric_mrepair_fuse_read_i; - output fabric_mrepair_fuse_ready_o; - input fabric_mrepair_fuse_redbypass_i; - output fabric_mrepair_fuse_sec_o; - output [15:0] fabric_mrepair_fuse_startword_o; - input fabric_mrepair_fuse_suppadd_i; - input fabric_mrepair_fuse_tm_i; - input [4:0] fabric_mrepair_fuse_tst_scanin_i; - input fabric_mrepair_fuse_tstscanenable_i; - output [4:0] fabric_mrepair_fuse_tstscanout_o; - output [9:0] fabric_mrepair_fuse_wlromout_o; - input fabric_mrepair_fuse_wordlock_i; - input [3:0] fabric_mrepair_mode_i; - input fabric_mrepair_por_i; - input [31:0] fabric_otp_apb_addr_i; - input fabric_otp_apb_enable_i; - output [31:0] fabric_otp_apb_rdata_o; - output fabric_otp_apb_ready_o; - input fabric_otp_apb_sel_i; - input [31:0] fabric_otp_apb_wdata_i; - input fabric_otp_apb_write_i; - input fabric_otp_cfg_clk_fab_en_i; - input fabric_otp_cfg_clk_otpm_disable_i; - input fabric_otp_cfg_fabric_apb_en_i; - input fabric_otp_cfg_loader_read_en_i; - input fabric_otp_cfg_loader_write_en_i; - input fabric_otp_rst_i; - output fabric_otp_security_ack_o; - output fabric_otp_security_bist_bad_o; - output fabric_otp_security_bist_end1_o; - output fabric_otp_security_bist_end2_o; - output [7:0] fabric_otp_security_bist_fail1_o; - output [6:0] fabric_otp_security_bist_fail2_o; - input fabric_otp_security_bistmode_i; - input fabric_otp_security_force_pdn1_i; - input fabric_otp_security_rbact1_i; - input fabric_otp_security_rbact2_i; - input fabric_otp_security_scanenable_i; - input [4:0] fabric_otp_security_scanin_i; - output [4:0] fabric_otp_security_scanout_o; - input fabric_otp_security_testmode_i; - output fabric_otp_user_ack_o; - input [6:0] fabric_otp_user_add_i; - output fabric_otp_user_bbad_o; - output fabric_otp_user_bend1_o; - output fabric_otp_user_bend2_o; - output [7:0] fabric_otp_user_bist1fail_o; - output [6:0] fabric_otp_user_bist2fail_o; - input fabric_otp_user_bistmode_i; - output fabric_otp_user_calibrated_o; - input fabric_otp_user_clock_frequency_range_i; - output fabric_otp_user_ded_o; - input [38:0] fabric_otp_user_din_i; - input fabric_otp_user_disturbcheck_i; - output fabric_otp_user_disturbed_o; - output [40:0] fabric_otp_user_dout_o; - input fabric_otp_user_eccbypass_i; - output [3:0] fabric_otp_user_flagstate_o; - output fabric_otp_user_locked_o; - input fabric_otp_user_pdn_i; - input [2:0] fabric_otp_user_prgwidth_i; - input fabric_otp_user_prog_i; - output fabric_otp_user_progfail_o; - output fabric_otp_user_pwok_o; - input fabric_otp_user_rbact1_i; - input fabric_otp_user_rbact2_i; - input fabric_otp_user_read_i; - input fabric_otp_user_redbypass_i; - output fabric_otp_user_sec_o; - output [15:0] fabric_otp_user_startword_o; - input fabric_otp_user_suppadd_i; - input fabric_otp_user_tm_i; - input fabric_otp_user_tst_scanenable_i; - input [4:0] fabric_otp_user_tst_scanin_i; - output [4:0] fabric_otp_user_tst_scanout_o; - output [9:0] fabric_otp_user_wlromout_o; - input fabric_otp_user_wordlock_i; - input fabric_parusr_cs_i; - input [15:0] fabric_parusr_data_i; - output [15:0] fabric_parusr_data_o; - output fabric_parusr_data_val_o; - input fabric_parusr_enable_i; - input [1:0] fabric_parusr_type_i; - input [23:0] fabric_pd_active_i; - output [23:0] fabric_pd_ready_o; - input [23:0] fabric_shift_en_i; - output [23:0] fabric_shift_en_to_bist_o; - input [23:0] fabric_sif_load_en_i; - output [23:0] fabric_sif_load_en_to_bist_o; - input [119:0] fabric_sif_reg_en_i; - output [119:0] fabric_sif_reg_en_to_bist_o; - input [23:0] fabric_sif_update_en_i; - output [23:0] fabric_sif_update_en_to_bist_o; - output fabric_status_cold_start_o; - output [23:0] fabric_system_data_from_mem_bist_o; - input [23:0] fabric_system_data_to_mem_bist_i; - output fabric_system_dataready_o; - input fabric_tst_atpg_mrepair_i; - input [31:0] fabric_user_data_i; - output [31:0] fabric_user_data_o; - output fabric_user_read_cycle_o; - output fabric_user_write_cycle_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SOC_INTERFACE(fabric_lowskew_o1, fabric_lowskew_o2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_i11, fabric_lowskew_i12, fabric_lowskew_i13, fabric_lowskew_i14, fabric_lowskew_i15, fabric_lowskew_i16, fabric_lowskew_i17, fabric_lowskew_i18, fabric_lowskew_i19, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2 -, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3 -, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16 -, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37 -, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58 -, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79 -, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100 -, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i -, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21 -, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42 -, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3 -, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24 -, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3 -, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8 -, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5 -, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26 -, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1 -, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1 -, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6 -, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27 -, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48 -, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69 -, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90 -, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111 -, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3 -, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4 -, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10 -, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31 -, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52 -, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73 -, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94 -, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115 -, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8 -, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12 -, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33 -, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8 -, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1 -, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14 -, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35 -, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10 -, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3 -, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15 -, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36 -, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57 -, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, fabric_fpga_wdata_axi_s2_o68, fabric_fpga_wdata_axi_s2_o69, fabric_fpga_wdata_axi_s2_o70, fabric_fpga_wdata_axi_s2_o71, fabric_fpga_wdata_axi_s2_o72, fabric_fpga_wdata_axi_s2_o73, fabric_fpga_wdata_axi_s2_o74, fabric_fpga_wdata_axi_s2_o75, fabric_fpga_wdata_axi_s2_o76, fabric_fpga_wdata_axi_s2_o77, fabric_fpga_wdata_axi_s2_o78 -, fabric_fpga_wdata_axi_s2_o79, fabric_fpga_wdata_axi_s2_o80, fabric_fpga_wdata_axi_s2_o81, fabric_fpga_wdata_axi_s2_o82, fabric_fpga_wdata_axi_s2_o83, fabric_fpga_wdata_axi_s2_o84, fabric_fpga_wdata_axi_s2_o85, fabric_fpga_wdata_axi_s2_o86, fabric_fpga_wdata_axi_s2_o87, fabric_fpga_wdata_axi_s2_o88, fabric_fpga_wdata_axi_s2_o89, fabric_fpga_wdata_axi_s2_o90, fabric_fpga_wdata_axi_s2_o91, fabric_fpga_wdata_axi_s2_o92, fabric_fpga_wdata_axi_s2_o93, fabric_fpga_wdata_axi_s2_o94, fabric_fpga_wdata_axi_s2_o95, fabric_fpga_wdata_axi_s2_o96, fabric_fpga_wdata_axi_s2_o97, fabric_fpga_wdata_axi_s2_o98, fabric_fpga_wdata_axi_s2_o99 -, fabric_fpga_wdata_axi_s2_o100, fabric_fpga_wdata_axi_s2_o101, fabric_fpga_wdata_axi_s2_o102, fabric_fpga_wdata_axi_s2_o103, fabric_fpga_wdata_axi_s2_o104, fabric_fpga_wdata_axi_s2_o105, fabric_fpga_wdata_axi_s2_o106, fabric_fpga_wdata_axi_s2_o107, fabric_fpga_wdata_axi_s2_o108, fabric_fpga_wdata_axi_s2_o109, fabric_fpga_wdata_axi_s2_o110, fabric_fpga_wdata_axi_s2_o111, fabric_fpga_wdata_axi_s2_o112, fabric_fpga_wdata_axi_s2_o113, fabric_fpga_wdata_axi_s2_o114, fabric_fpga_wdata_axi_s2_o115, fabric_fpga_wdata_axi_s2_o116, fabric_fpga_wdata_axi_s2_o117, fabric_fpga_wdata_axi_s2_o118, fabric_fpga_wdata_axi_s2_o119, fabric_fpga_wdata_axi_s2_o120 -, fabric_fpga_wdata_axi_s2_o121, fabric_fpga_wdata_axi_s2_o122, fabric_fpga_wdata_axi_s2_o123, fabric_fpga_wdata_axi_s2_o124, fabric_fpga_wdata_axi_s2_o125, fabric_fpga_wdata_axi_s2_o126, fabric_fpga_wdata_axi_s2_o127, fabric_fpga_wdata_axi_s2_o128, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wstrb_axi_s2_o1, fabric_fpga_wstrb_axi_s2_o2, fabric_fpga_wstrb_axi_s2_o3, fabric_fpga_wstrb_axi_s2_o4, fabric_fpga_wstrb_axi_s2_o5, fabric_fpga_wstrb_axi_s2_o6, fabric_fpga_wstrb_axi_s2_o7, fabric_fpga_wstrb_axi_s2_o8, fabric_fpga_wstrb_axi_s2_o9, fabric_fpga_wstrb_axi_s2_o10, fabric_fpga_wstrb_axi_s2_o11, fabric_fpga_wstrb_axi_s2_o12 -, fabric_fpga_wstrb_axi_s2_o13, fabric_fpga_wstrb_axi_s2_o14, fabric_fpga_wstrb_axi_s2_o15, fabric_fpga_wstrb_axi_s2_o16, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bid_axi_s2_i1, fabric_fpga_bid_axi_s2_i2, fabric_fpga_bid_axi_s2_i3, fabric_fpga_bid_axi_s2_i4, fabric_fpga_bid_axi_s2_i5, fabric_fpga_bid_axi_s2_i6, fabric_fpga_bid_axi_s2_i7, fabric_fpga_bid_axi_s2_i8, fabric_fpga_bid_axi_s2_i9, fabric_fpga_bid_axi_s2_i10, fabric_fpga_bid_axi_s2_i11, fabric_fpga_bid_axi_s2_i12, fabric_fpga_bresp_axi_s2_i1 -, fabric_fpga_bresp_axi_s2_i2, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rdata_axi_s2_i1, fabric_fpga_rdata_axi_s2_i2, fabric_fpga_rdata_axi_s2_i3, fabric_fpga_rdata_axi_s2_i4, fabric_fpga_rdata_axi_s2_i5, fabric_fpga_rdata_axi_s2_i6, fabric_fpga_rdata_axi_s2_i7, fabric_fpga_rdata_axi_s2_i8, fabric_fpga_rdata_axi_s2_i9, fabric_fpga_rdata_axi_s2_i10, fabric_fpga_rdata_axi_s2_i11, fabric_fpga_rdata_axi_s2_i12, fabric_fpga_rdata_axi_s2_i13, fabric_fpga_rdata_axi_s2_i14, fabric_fpga_rdata_axi_s2_i15, fabric_fpga_rdata_axi_s2_i16, fabric_fpga_rdata_axi_s2_i17, fabric_fpga_rdata_axi_s2_i18, fabric_fpga_rdata_axi_s2_i19 -, fabric_fpga_rdata_axi_s2_i20, fabric_fpga_rdata_axi_s2_i21, fabric_fpga_rdata_axi_s2_i22, fabric_fpga_rdata_axi_s2_i23, fabric_fpga_rdata_axi_s2_i24, fabric_fpga_rdata_axi_s2_i25, fabric_fpga_rdata_axi_s2_i26, fabric_fpga_rdata_axi_s2_i27, fabric_fpga_rdata_axi_s2_i28, fabric_fpga_rdata_axi_s2_i29, fabric_fpga_rdata_axi_s2_i30, fabric_fpga_rdata_axi_s2_i31, fabric_fpga_rdata_axi_s2_i32, fabric_fpga_rdata_axi_s2_i33, fabric_fpga_rdata_axi_s2_i34, fabric_fpga_rdata_axi_s2_i35, fabric_fpga_rdata_axi_s2_i36, fabric_fpga_rdata_axi_s2_i37, fabric_fpga_rdata_axi_s2_i38, fabric_fpga_rdata_axi_s2_i39, fabric_fpga_rdata_axi_s2_i40 -, fabric_fpga_rdata_axi_s2_i41, fabric_fpga_rdata_axi_s2_i42, fabric_fpga_rdata_axi_s2_i43, fabric_fpga_rdata_axi_s2_i44, fabric_fpga_rdata_axi_s2_i45, fabric_fpga_rdata_axi_s2_i46, fabric_fpga_rdata_axi_s2_i47, fabric_fpga_rdata_axi_s2_i48, fabric_fpga_rdata_axi_s2_i49, fabric_fpga_rdata_axi_s2_i50, fabric_fpga_rdata_axi_s2_i51, fabric_fpga_rdata_axi_s2_i52, fabric_fpga_rdata_axi_s2_i53, fabric_fpga_rdata_axi_s2_i54, fabric_fpga_rdata_axi_s2_i55, fabric_fpga_rdata_axi_s2_i56, fabric_fpga_rdata_axi_s2_i57, fabric_fpga_rdata_axi_s2_i58, fabric_fpga_rdata_axi_s2_i59, fabric_fpga_rdata_axi_s2_i60, fabric_fpga_rdata_axi_s2_i61 -, fabric_fpga_rdata_axi_s2_i62, fabric_fpga_rdata_axi_s2_i63, fabric_fpga_rdata_axi_s2_i64, fabric_fpga_rdata_axi_s2_i65, fabric_fpga_rdata_axi_s2_i66, fabric_fpga_rdata_axi_s2_i67, fabric_fpga_rdata_axi_s2_i68, fabric_fpga_rdata_axi_s2_i69, fabric_fpga_rdata_axi_s2_i70, fabric_fpga_rdata_axi_s2_i71, fabric_fpga_rdata_axi_s2_i72, fabric_fpga_rdata_axi_s2_i73, fabric_fpga_rdata_axi_s2_i74, fabric_fpga_rdata_axi_s2_i75, fabric_fpga_rdata_axi_s2_i76, fabric_fpga_rdata_axi_s2_i77, fabric_fpga_rdata_axi_s2_i78, fabric_fpga_rdata_axi_s2_i79, fabric_fpga_rdata_axi_s2_i80, fabric_fpga_rdata_axi_s2_i81, fabric_fpga_rdata_axi_s2_i82 -, fabric_fpga_rdata_axi_s2_i83, fabric_fpga_rdata_axi_s2_i84, fabric_fpga_rdata_axi_s2_i85, fabric_fpga_rdata_axi_s2_i86, fabric_fpga_rdata_axi_s2_i87, fabric_fpga_rdata_axi_s2_i88, fabric_fpga_rdata_axi_s2_i89, fabric_fpga_rdata_axi_s2_i90, fabric_fpga_rdata_axi_s2_i91, fabric_fpga_rdata_axi_s2_i92, fabric_fpga_rdata_axi_s2_i93, fabric_fpga_rdata_axi_s2_i94, fabric_fpga_rdata_axi_s2_i95, fabric_fpga_rdata_axi_s2_i96, fabric_fpga_rdata_axi_s2_i97, fabric_fpga_rdata_axi_s2_i98, fabric_fpga_rdata_axi_s2_i99, fabric_fpga_rdata_axi_s2_i100, fabric_fpga_rdata_axi_s2_i101, fabric_fpga_rdata_axi_s2_i102, fabric_fpga_rdata_axi_s2_i103 -, fabric_fpga_rdata_axi_s2_i104, fabric_fpga_rdata_axi_s2_i105, fabric_fpga_rdata_axi_s2_i106, fabric_fpga_rdata_axi_s2_i107, fabric_fpga_rdata_axi_s2_i108, fabric_fpga_rdata_axi_s2_i109, fabric_fpga_rdata_axi_s2_i110, fabric_fpga_rdata_axi_s2_i111, fabric_fpga_rdata_axi_s2_i112, fabric_fpga_rdata_axi_s2_i113, fabric_fpga_rdata_axi_s2_i114, fabric_fpga_rdata_axi_s2_i115, fabric_fpga_rdata_axi_s2_i116, fabric_fpga_rdata_axi_s2_i117, fabric_fpga_rdata_axi_s2_i118, fabric_fpga_rdata_axi_s2_i119, fabric_fpga_rdata_axi_s2_i120, fabric_fpga_rdata_axi_s2_i121, fabric_fpga_rdata_axi_s2_i122, fabric_fpga_rdata_axi_s2_i123, fabric_fpga_rdata_axi_s2_i124 -, fabric_fpga_rdata_axi_s2_i125, fabric_fpga_rdata_axi_s2_i126, fabric_fpga_rdata_axi_s2_i127, fabric_fpga_rdata_axi_s2_i128, fabric_fpga_rid_axi_s2_i1, fabric_fpga_rid_axi_s2_i2, fabric_fpga_rid_axi_s2_i3, fabric_fpga_rid_axi_s2_i4, fabric_fpga_rid_axi_s2_i5, fabric_fpga_rid_axi_s2_i6, fabric_fpga_rid_axi_s2_i7, fabric_fpga_rid_axi_s2_i8, fabric_fpga_rid_axi_s2_i9, fabric_fpga_rid_axi_s2_i10, fabric_fpga_rid_axi_s2_i11, fabric_fpga_rid_axi_s2_i12, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rresp_axi_s2_i1, fabric_fpga_rresp_axi_s2_i2, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i -, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bid_axi_m1_o1, fabric_fpga_bid_axi_m1_o2, fabric_fpga_bid_axi_m1_o3, fabric_fpga_bid_axi_m1_o4, fabric_fpga_bid_axi_m1_o5, fabric_fpga_bresp_axi_m1_o1, fabric_fpga_bresp_axi_m1_o2, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_dma_ack_m1_o1, fabric_fpga_dma_ack_m1_o2, fabric_fpga_dma_ack_m1_o3, fabric_fpga_dma_ack_m1_o4, fabric_fpga_dma_ack_m1_o5, fabric_fpga_dma_ack_m1_o6, fabric_fpga_dma_finish_m1_o1, fabric_fpga_dma_finish_m1_o2, fabric_fpga_dma_finish_m1_o3, fabric_fpga_dma_finish_m1_o4, fabric_fpga_dma_finish_m1_o5 -, fabric_fpga_dma_finish_m1_o6, fabric_fpga_rdata_axi_m1_o1, fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20 -, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41 -, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62 -, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, fabric_fpga_rdata_axi_m1_o68, fabric_fpga_rdata_axi_m1_o69, fabric_fpga_rdata_axi_m1_o70, fabric_fpga_rdata_axi_m1_o71, fabric_fpga_rdata_axi_m1_o72, fabric_fpga_rdata_axi_m1_o73, fabric_fpga_rdata_axi_m1_o74, fabric_fpga_rdata_axi_m1_o75, fabric_fpga_rdata_axi_m1_o76, fabric_fpga_rdata_axi_m1_o77, fabric_fpga_rdata_axi_m1_o78, fabric_fpga_rdata_axi_m1_o79, fabric_fpga_rdata_axi_m1_o80, fabric_fpga_rdata_axi_m1_o81, fabric_fpga_rdata_axi_m1_o82, fabric_fpga_rdata_axi_m1_o83 -, fabric_fpga_rdata_axi_m1_o84, fabric_fpga_rdata_axi_m1_o85, fabric_fpga_rdata_axi_m1_o86, fabric_fpga_rdata_axi_m1_o87, fabric_fpga_rdata_axi_m1_o88, fabric_fpga_rdata_axi_m1_o89, fabric_fpga_rdata_axi_m1_o90, fabric_fpga_rdata_axi_m1_o91, fabric_fpga_rdata_axi_m1_o92, fabric_fpga_rdata_axi_m1_o93, fabric_fpga_rdata_axi_m1_o94, fabric_fpga_rdata_axi_m1_o95, fabric_fpga_rdata_axi_m1_o96, fabric_fpga_rdata_axi_m1_o97, fabric_fpga_rdata_axi_m1_o98, fabric_fpga_rdata_axi_m1_o99, fabric_fpga_rdata_axi_m1_o100, fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104 -, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125 -, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8 -, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29 -, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4 -, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i -, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21 -, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2 -, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3 -, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6 -, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14 -, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35 -, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56 -, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77 -, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98 -, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119 -, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11 -, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5 -, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14 -, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35 -, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56 -, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77 -, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98 -, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119 -, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2 -, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23 -, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2 -, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2 -, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15 -, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36 -, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6 -, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6 -, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8 -, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29 -, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50 -, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71 -, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92 -, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113 -, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5 -, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2 -, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20 -, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41 -, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62 -, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83 -, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104 -, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125 -, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8 -, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29 -, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4 -, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i -, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21 -, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2 -, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3 -, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11 -, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32 -, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53 -, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74 -, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95 -, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116 -, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8 -, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12 -, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o -, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20 -, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8 -, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29 -, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16 -, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3 -, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8 -, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9 -, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30 -, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1 -, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o -, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21 -, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2 -, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8 -, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29 -, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1 -, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22 -, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5 -, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s_o1, fabric_llpp1_arqos_s_o2 -, fabric_llpp1_arqos_s_o3, fabric_llpp1_arqos_s_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15 -, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2 -, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7 -, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6 -, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27 -, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8 -, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14 -, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3 -, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7 -, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28 -, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11 -, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o -, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21 -, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4 -, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1 -, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12 -, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o -, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2 -, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20 -, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9 -, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13 -, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2 -, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5 -, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6 -, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27 -, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10 -, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3 -, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18 -, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i -, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5 -, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26 -, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2 -, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19 -, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6 -, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27 -, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15 -, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o -, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20 -, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7 -, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28 -, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13 -, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o -, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21 -, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4 -, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25 -, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46 -, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67 -, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88 -, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109 -, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2 -, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13 -, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2 -, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23 -, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44 -, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1 -, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22 -, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4 -, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25 -, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46 -, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67 -, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88 -, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109 -, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2 -, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15 -, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i -, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i -, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3, fabric_spw_interrupts_toggle_o1 -, fabric_spw_interrupts_toggle_o2, fabric_spw_interrupts_toggle_o3, fabric_spw_interrupts_o1, fabric_spw_interrupts_o2, fabric_spw_interrupts_o3, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_fpga_dma_hs_rstn_i1, fabric_fpga_dma_hs_rstn_i2, fabric_fpga_dma_hs_rstn_i3, fabric_fpga_dma_hs_rstn_i4, fabric_fpga_dma_hs_rstn_i5, fabric_fpga_dma_hs_rstn_i6); - input fabric_enable_TMR_i1; - input fabric_enable_TMR_i2; - input fabric_enable_TMR_i3; - input fabric_erom_fpga_cpu0_dbgen_i; - input fabric_erom_fpga_cpu0_hiden_i; - input fabric_erom_fpga_cpu0_hniden_i; - input fabric_erom_fpga_cpu0_niden_i; - input fabric_erom_fpga_cpu1_dbgen_i; - input fabric_erom_fpga_cpu1_hiden_i; - input fabric_erom_fpga_cpu1_hniden_i; - input fabric_erom_fpga_cpu1_niden_i; - input fabric_erom_fpga_cpu2_dbgen_i; - input fabric_erom_fpga_cpu2_hiden_i; - input fabric_erom_fpga_cpu2_hniden_i; - input fabric_erom_fpga_cpu2_niden_i; - input fabric_erom_fpga_cpu3_dbgen_i; - input fabric_erom_fpga_cpu3_hiden_i; - input fabric_erom_fpga_cpu3_hniden_i; - input fabric_erom_fpga_cpu3_niden_i; - input fabric_erom_fpga_cs_dbgen_i; - input fabric_erom_fpga_cs_deviceen_i; - input fabric_erom_fpga_cs_niden_i; - input fabric_erom_fpga_cs_rst_n_i; - input fabric_erom_fpga_debug_en_i; - output fabric_flash_irq_o; - output fabric_flash_irq_toggle_o; - input fabric_fpga_araddr_axi_m1_i1; - input fabric_fpga_araddr_axi_m1_i10; - input fabric_fpga_araddr_axi_m1_i11; - input fabric_fpga_araddr_axi_m1_i12; - input fabric_fpga_araddr_axi_m1_i13; - input fabric_fpga_araddr_axi_m1_i14; - input fabric_fpga_araddr_axi_m1_i15; - input fabric_fpga_araddr_axi_m1_i16; - input fabric_fpga_araddr_axi_m1_i17; - input fabric_fpga_araddr_axi_m1_i18; - input fabric_fpga_araddr_axi_m1_i19; - input fabric_fpga_araddr_axi_m1_i2; - input fabric_fpga_araddr_axi_m1_i20; - input fabric_fpga_araddr_axi_m1_i21; - input fabric_fpga_araddr_axi_m1_i22; - input fabric_fpga_araddr_axi_m1_i23; - input fabric_fpga_araddr_axi_m1_i24; - input fabric_fpga_araddr_axi_m1_i25; - input fabric_fpga_araddr_axi_m1_i26; - input fabric_fpga_araddr_axi_m1_i27; - input fabric_fpga_araddr_axi_m1_i28; - input fabric_fpga_araddr_axi_m1_i29; - input fabric_fpga_araddr_axi_m1_i3; - input fabric_fpga_araddr_axi_m1_i30; - input fabric_fpga_araddr_axi_m1_i31; - input fabric_fpga_araddr_axi_m1_i32; - input fabric_fpga_araddr_axi_m1_i33; - input fabric_fpga_araddr_axi_m1_i34; - input fabric_fpga_araddr_axi_m1_i35; - input fabric_fpga_araddr_axi_m1_i36; - input fabric_fpga_araddr_axi_m1_i37; - input fabric_fpga_araddr_axi_m1_i38; - input fabric_fpga_araddr_axi_m1_i39; - input fabric_fpga_araddr_axi_m1_i4; - input fabric_fpga_araddr_axi_m1_i40; - input fabric_fpga_araddr_axi_m1_i5; - input fabric_fpga_araddr_axi_m1_i6; - input fabric_fpga_araddr_axi_m1_i7; - input fabric_fpga_araddr_axi_m1_i8; - input fabric_fpga_araddr_axi_m1_i9; - input fabric_fpga_araddr_axi_m2_i1; - input fabric_fpga_araddr_axi_m2_i10; - input fabric_fpga_araddr_axi_m2_i11; - input fabric_fpga_araddr_axi_m2_i12; - input fabric_fpga_araddr_axi_m2_i13; - input fabric_fpga_araddr_axi_m2_i14; - input fabric_fpga_araddr_axi_m2_i15; - input fabric_fpga_araddr_axi_m2_i16; - input fabric_fpga_araddr_axi_m2_i17; - input fabric_fpga_araddr_axi_m2_i18; - input fabric_fpga_araddr_axi_m2_i19; - input fabric_fpga_araddr_axi_m2_i2; - input fabric_fpga_araddr_axi_m2_i20; - input fabric_fpga_araddr_axi_m2_i21; - input fabric_fpga_araddr_axi_m2_i22; - input fabric_fpga_araddr_axi_m2_i23; - input fabric_fpga_araddr_axi_m2_i24; - input fabric_fpga_araddr_axi_m2_i25; - input fabric_fpga_araddr_axi_m2_i26; - input fabric_fpga_araddr_axi_m2_i27; - input fabric_fpga_araddr_axi_m2_i28; - input fabric_fpga_araddr_axi_m2_i29; - input fabric_fpga_araddr_axi_m2_i3; - input fabric_fpga_araddr_axi_m2_i30; - input fabric_fpga_araddr_axi_m2_i31; - input fabric_fpga_araddr_axi_m2_i32; - input fabric_fpga_araddr_axi_m2_i33; - input fabric_fpga_araddr_axi_m2_i34; - input fabric_fpga_araddr_axi_m2_i35; - input fabric_fpga_araddr_axi_m2_i36; - input fabric_fpga_araddr_axi_m2_i37; - input fabric_fpga_araddr_axi_m2_i38; - input fabric_fpga_araddr_axi_m2_i39; - input fabric_fpga_araddr_axi_m2_i4; - input fabric_fpga_araddr_axi_m2_i40; - input fabric_fpga_araddr_axi_m2_i5; - input fabric_fpga_araddr_axi_m2_i6; - input fabric_fpga_araddr_axi_m2_i7; - input fabric_fpga_araddr_axi_m2_i8; - input fabric_fpga_araddr_axi_m2_i9; - output fabric_fpga_araddr_axi_s1_o1; - output fabric_fpga_araddr_axi_s1_o10; - output fabric_fpga_araddr_axi_s1_o11; - output fabric_fpga_araddr_axi_s1_o12; - output fabric_fpga_araddr_axi_s1_o13; - output fabric_fpga_araddr_axi_s1_o14; - output fabric_fpga_araddr_axi_s1_o15; - output fabric_fpga_araddr_axi_s1_o16; - output fabric_fpga_araddr_axi_s1_o17; - output fabric_fpga_araddr_axi_s1_o18; - output fabric_fpga_araddr_axi_s1_o19; - output fabric_fpga_araddr_axi_s1_o2; - output fabric_fpga_araddr_axi_s1_o20; - output fabric_fpga_araddr_axi_s1_o21; - output fabric_fpga_araddr_axi_s1_o22; - output fabric_fpga_araddr_axi_s1_o23; - output fabric_fpga_araddr_axi_s1_o24; - output fabric_fpga_araddr_axi_s1_o25; - output fabric_fpga_araddr_axi_s1_o26; - output fabric_fpga_araddr_axi_s1_o27; - output fabric_fpga_araddr_axi_s1_o28; - output fabric_fpga_araddr_axi_s1_o29; - output fabric_fpga_araddr_axi_s1_o3; - output fabric_fpga_araddr_axi_s1_o30; - output fabric_fpga_araddr_axi_s1_o31; - output fabric_fpga_araddr_axi_s1_o32; - output fabric_fpga_araddr_axi_s1_o33; - output fabric_fpga_araddr_axi_s1_o34; - output fabric_fpga_araddr_axi_s1_o35; - output fabric_fpga_araddr_axi_s1_o36; - output fabric_fpga_araddr_axi_s1_o37; - output fabric_fpga_araddr_axi_s1_o38; - output fabric_fpga_araddr_axi_s1_o39; - output fabric_fpga_araddr_axi_s1_o4; - output fabric_fpga_araddr_axi_s1_o40; - output fabric_fpga_araddr_axi_s1_o5; - output fabric_fpga_araddr_axi_s1_o6; - output fabric_fpga_araddr_axi_s1_o7; - output fabric_fpga_araddr_axi_s1_o8; - output fabric_fpga_araddr_axi_s1_o9; - output fabric_fpga_araddr_axi_s2_o1; - output fabric_fpga_araddr_axi_s2_o10; - output fabric_fpga_araddr_axi_s2_o11; - output fabric_fpga_araddr_axi_s2_o12; - output fabric_fpga_araddr_axi_s2_o13; - output fabric_fpga_araddr_axi_s2_o14; - output fabric_fpga_araddr_axi_s2_o15; - output fabric_fpga_araddr_axi_s2_o16; - output fabric_fpga_araddr_axi_s2_o17; - output fabric_fpga_araddr_axi_s2_o18; - output fabric_fpga_araddr_axi_s2_o19; - output fabric_fpga_araddr_axi_s2_o2; - output fabric_fpga_araddr_axi_s2_o20; - output fabric_fpga_araddr_axi_s2_o21; - output fabric_fpga_araddr_axi_s2_o22; - output fabric_fpga_araddr_axi_s2_o23; - output fabric_fpga_araddr_axi_s2_o24; - output fabric_fpga_araddr_axi_s2_o25; - output fabric_fpga_araddr_axi_s2_o26; - output fabric_fpga_araddr_axi_s2_o27; - output fabric_fpga_araddr_axi_s2_o28; - output fabric_fpga_araddr_axi_s2_o29; - output fabric_fpga_araddr_axi_s2_o3; - output fabric_fpga_araddr_axi_s2_o30; - output fabric_fpga_araddr_axi_s2_o31; - output fabric_fpga_araddr_axi_s2_o32; - output fabric_fpga_araddr_axi_s2_o33; - output fabric_fpga_araddr_axi_s2_o34; - output fabric_fpga_araddr_axi_s2_o35; - output fabric_fpga_araddr_axi_s2_o36; - output fabric_fpga_araddr_axi_s2_o37; - output fabric_fpga_araddr_axi_s2_o38; - output fabric_fpga_araddr_axi_s2_o39; - output fabric_fpga_araddr_axi_s2_o4; - output fabric_fpga_araddr_axi_s2_o40; - output fabric_fpga_araddr_axi_s2_o5; - output fabric_fpga_araddr_axi_s2_o6; - output fabric_fpga_araddr_axi_s2_o7; - output fabric_fpga_araddr_axi_s2_o8; - output fabric_fpga_araddr_axi_s2_o9; - input fabric_fpga_arburst_axi_m1_i1; - input fabric_fpga_arburst_axi_m1_i2; - input fabric_fpga_arburst_axi_m2_i1; - input fabric_fpga_arburst_axi_m2_i2; - output fabric_fpga_arburst_axi_s1_o1; - output fabric_fpga_arburst_axi_s1_o2; - output fabric_fpga_arburst_axi_s2_o1; - output fabric_fpga_arburst_axi_s2_o2; - input fabric_fpga_arcache_axi_m1_i1; - input fabric_fpga_arcache_axi_m1_i2; - input fabric_fpga_arcache_axi_m1_i3; - input fabric_fpga_arcache_axi_m1_i4; - input fabric_fpga_arcache_axi_m2_i1; - input fabric_fpga_arcache_axi_m2_i2; - input fabric_fpga_arcache_axi_m2_i3; - input fabric_fpga_arcache_axi_m2_i4; - output fabric_fpga_arcache_axi_s1_o1; - output fabric_fpga_arcache_axi_s1_o2; - output fabric_fpga_arcache_axi_s1_o3; - output fabric_fpga_arcache_axi_s1_o4; - output fabric_fpga_arcache_axi_s2_o1; - output fabric_fpga_arcache_axi_s2_o2; - output fabric_fpga_arcache_axi_s2_o3; - output fabric_fpga_arcache_axi_s2_o4; - input fabric_fpga_arid_axi_m1_i1; - input fabric_fpga_arid_axi_m1_i2; - input fabric_fpga_arid_axi_m1_i3; - input fabric_fpga_arid_axi_m1_i4; - input fabric_fpga_arid_axi_m1_i5; - input fabric_fpga_arid_axi_m2_i1; - input fabric_fpga_arid_axi_m2_i2; - input fabric_fpga_arid_axi_m2_i3; - input fabric_fpga_arid_axi_m2_i4; - input fabric_fpga_arid_axi_m2_i5; - output fabric_fpga_arid_axi_s1_o1; - output fabric_fpga_arid_axi_s1_o10; - output fabric_fpga_arid_axi_s1_o11; - output fabric_fpga_arid_axi_s1_o12; - output fabric_fpga_arid_axi_s1_o2; - output fabric_fpga_arid_axi_s1_o3; - output fabric_fpga_arid_axi_s1_o4; - output fabric_fpga_arid_axi_s1_o5; - output fabric_fpga_arid_axi_s1_o6; - output fabric_fpga_arid_axi_s1_o7; - output fabric_fpga_arid_axi_s1_o8; - output fabric_fpga_arid_axi_s1_o9; - output fabric_fpga_arid_axi_s2_o1; - output fabric_fpga_arid_axi_s2_o10; - output fabric_fpga_arid_axi_s2_o11; - output fabric_fpga_arid_axi_s2_o12; - output fabric_fpga_arid_axi_s2_o2; - output fabric_fpga_arid_axi_s2_o3; - output fabric_fpga_arid_axi_s2_o4; - output fabric_fpga_arid_axi_s2_o5; - output fabric_fpga_arid_axi_s2_o6; - output fabric_fpga_arid_axi_s2_o7; - output fabric_fpga_arid_axi_s2_o8; - output fabric_fpga_arid_axi_s2_o9; - input fabric_fpga_arlen_axi_m1_i1; - input fabric_fpga_arlen_axi_m1_i2; - input fabric_fpga_arlen_axi_m1_i3; - input fabric_fpga_arlen_axi_m1_i4; - input fabric_fpga_arlen_axi_m1_i5; - input fabric_fpga_arlen_axi_m1_i6; - input fabric_fpga_arlen_axi_m1_i7; - input fabric_fpga_arlen_axi_m1_i8; - input fabric_fpga_arlen_axi_m2_i1; - input fabric_fpga_arlen_axi_m2_i2; - input fabric_fpga_arlen_axi_m2_i3; - input fabric_fpga_arlen_axi_m2_i4; - input fabric_fpga_arlen_axi_m2_i5; - input fabric_fpga_arlen_axi_m2_i6; - input fabric_fpga_arlen_axi_m2_i7; - input fabric_fpga_arlen_axi_m2_i8; - output fabric_fpga_arlen_axi_s1_o1; - output fabric_fpga_arlen_axi_s1_o2; - output fabric_fpga_arlen_axi_s1_o3; - output fabric_fpga_arlen_axi_s1_o4; - output fabric_fpga_arlen_axi_s1_o5; - output fabric_fpga_arlen_axi_s1_o6; - output fabric_fpga_arlen_axi_s1_o7; - output fabric_fpga_arlen_axi_s1_o8; - output fabric_fpga_arlen_axi_s2_o1; - output fabric_fpga_arlen_axi_s2_o2; - output fabric_fpga_arlen_axi_s2_o3; - output fabric_fpga_arlen_axi_s2_o4; - output fabric_fpga_arlen_axi_s2_o5; - output fabric_fpga_arlen_axi_s2_o6; - output fabric_fpga_arlen_axi_s2_o7; - output fabric_fpga_arlen_axi_s2_o8; - input fabric_fpga_arlock_axi_m1_i; - input fabric_fpga_arlock_axi_m2_i; - output fabric_fpga_arlock_axi_s1_o; - output fabric_fpga_arlock_axi_s2_o; - input fabric_fpga_arprot_axi_m1_i1; - input fabric_fpga_arprot_axi_m1_i2; - input fabric_fpga_arprot_axi_m1_i3; - input fabric_fpga_arprot_axi_m2_i1; - input fabric_fpga_arprot_axi_m2_i2; - input fabric_fpga_arprot_axi_m2_i3; - output fabric_fpga_arprot_axi_s1_o1; - output fabric_fpga_arprot_axi_s1_o2; - output fabric_fpga_arprot_axi_s1_o3; - output fabric_fpga_arprot_axi_s2_o1; - output fabric_fpga_arprot_axi_s2_o2; - output fabric_fpga_arprot_axi_s2_o3; - input fabric_fpga_arqos_axi_m1_i1; - input fabric_fpga_arqos_axi_m1_i2; - input fabric_fpga_arqos_axi_m1_i3; - input fabric_fpga_arqos_axi_m1_i4; - input fabric_fpga_arqos_axi_m2_i1; - input fabric_fpga_arqos_axi_m2_i2; - input fabric_fpga_arqos_axi_m2_i3; - input fabric_fpga_arqos_axi_m2_i4; - output fabric_fpga_arqos_axi_s1_o1; - output fabric_fpga_arqos_axi_s1_o2; - output fabric_fpga_arqos_axi_s1_o3; - output fabric_fpga_arqos_axi_s1_o4; - output fabric_fpga_arqos_axi_s2_o1; - output fabric_fpga_arqos_axi_s2_o2; - output fabric_fpga_arqos_axi_s2_o3; - output fabric_fpga_arqos_axi_s2_o4; - output fabric_fpga_arready_axi_m1_o; - output fabric_fpga_arready_axi_m2_o; - input fabric_fpga_arready_axi_s1_i; - input fabric_fpga_arready_axi_s2_i; - output fabric_fpga_arregion_axi_s1_o1; - output fabric_fpga_arregion_axi_s1_o2; - output fabric_fpga_arregion_axi_s1_o3; - output fabric_fpga_arregion_axi_s1_o4; - output fabric_fpga_arregion_axi_s2_o1; - output fabric_fpga_arregion_axi_s2_o2; - output fabric_fpga_arregion_axi_s2_o3; - output fabric_fpga_arregion_axi_s2_o4; - input fabric_fpga_arsize_axi_m1_i1; - input fabric_fpga_arsize_axi_m1_i2; - input fabric_fpga_arsize_axi_m1_i3; - input fabric_fpga_arsize_axi_m2_i1; - input fabric_fpga_arsize_axi_m2_i2; - input fabric_fpga_arsize_axi_m2_i3; - output fabric_fpga_arsize_axi_s1_o1; - output fabric_fpga_arsize_axi_s1_o2; - output fabric_fpga_arsize_axi_s1_o3; - output fabric_fpga_arsize_axi_s2_o1; - output fabric_fpga_arsize_axi_s2_o2; - output fabric_fpga_arsize_axi_s2_o3; - input fabric_fpga_arvalid_axi_m1_i; - input fabric_fpga_arvalid_axi_m2_i; - output fabric_fpga_arvalid_axi_s1_o; - output fabric_fpga_arvalid_axi_s2_o; - input fabric_fpga_awaddr_axi_m1_i1; - input fabric_fpga_awaddr_axi_m1_i10; - input fabric_fpga_awaddr_axi_m1_i11; - input fabric_fpga_awaddr_axi_m1_i12; - input fabric_fpga_awaddr_axi_m1_i13; - input fabric_fpga_awaddr_axi_m1_i14; - input fabric_fpga_awaddr_axi_m1_i15; - input fabric_fpga_awaddr_axi_m1_i16; - input fabric_fpga_awaddr_axi_m1_i17; - input fabric_fpga_awaddr_axi_m1_i18; - input fabric_fpga_awaddr_axi_m1_i19; - input fabric_fpga_awaddr_axi_m1_i2; - input fabric_fpga_awaddr_axi_m1_i20; - input fabric_fpga_awaddr_axi_m1_i21; - input fabric_fpga_awaddr_axi_m1_i22; - input fabric_fpga_awaddr_axi_m1_i23; - input fabric_fpga_awaddr_axi_m1_i24; - input fabric_fpga_awaddr_axi_m1_i25; - input fabric_fpga_awaddr_axi_m1_i26; - input fabric_fpga_awaddr_axi_m1_i27; - input fabric_fpga_awaddr_axi_m1_i28; - input fabric_fpga_awaddr_axi_m1_i29; - input fabric_fpga_awaddr_axi_m1_i3; - input fabric_fpga_awaddr_axi_m1_i30; - input fabric_fpga_awaddr_axi_m1_i31; - input fabric_fpga_awaddr_axi_m1_i32; - input fabric_fpga_awaddr_axi_m1_i33; - input fabric_fpga_awaddr_axi_m1_i34; - input fabric_fpga_awaddr_axi_m1_i35; - input fabric_fpga_awaddr_axi_m1_i36; - input fabric_fpga_awaddr_axi_m1_i37; - input fabric_fpga_awaddr_axi_m1_i38; - input fabric_fpga_awaddr_axi_m1_i39; - input fabric_fpga_awaddr_axi_m1_i4; - input fabric_fpga_awaddr_axi_m1_i40; - input fabric_fpga_awaddr_axi_m1_i5; - input fabric_fpga_awaddr_axi_m1_i6; - input fabric_fpga_awaddr_axi_m1_i7; - input fabric_fpga_awaddr_axi_m1_i8; - input fabric_fpga_awaddr_axi_m1_i9; - input fabric_fpga_awaddr_axi_m2_i1; - input fabric_fpga_awaddr_axi_m2_i10; - input fabric_fpga_awaddr_axi_m2_i11; - input fabric_fpga_awaddr_axi_m2_i12; - input fabric_fpga_awaddr_axi_m2_i13; - input fabric_fpga_awaddr_axi_m2_i14; - input fabric_fpga_awaddr_axi_m2_i15; - input fabric_fpga_awaddr_axi_m2_i16; - input fabric_fpga_awaddr_axi_m2_i17; - input fabric_fpga_awaddr_axi_m2_i18; - input fabric_fpga_awaddr_axi_m2_i19; - input fabric_fpga_awaddr_axi_m2_i2; - input fabric_fpga_awaddr_axi_m2_i20; - input fabric_fpga_awaddr_axi_m2_i21; - input fabric_fpga_awaddr_axi_m2_i22; - input fabric_fpga_awaddr_axi_m2_i23; - input fabric_fpga_awaddr_axi_m2_i24; - input fabric_fpga_awaddr_axi_m2_i25; - input fabric_fpga_awaddr_axi_m2_i26; - input fabric_fpga_awaddr_axi_m2_i27; - input fabric_fpga_awaddr_axi_m2_i28; - input fabric_fpga_awaddr_axi_m2_i29; - input fabric_fpga_awaddr_axi_m2_i3; - input fabric_fpga_awaddr_axi_m2_i30; - input fabric_fpga_awaddr_axi_m2_i31; - input fabric_fpga_awaddr_axi_m2_i32; - input fabric_fpga_awaddr_axi_m2_i33; - input fabric_fpga_awaddr_axi_m2_i34; - input fabric_fpga_awaddr_axi_m2_i35; - input fabric_fpga_awaddr_axi_m2_i36; - input fabric_fpga_awaddr_axi_m2_i37; - input fabric_fpga_awaddr_axi_m2_i38; - input fabric_fpga_awaddr_axi_m2_i39; - input fabric_fpga_awaddr_axi_m2_i4; - input fabric_fpga_awaddr_axi_m2_i40; - input fabric_fpga_awaddr_axi_m2_i5; - input fabric_fpga_awaddr_axi_m2_i6; - input fabric_fpga_awaddr_axi_m2_i7; - input fabric_fpga_awaddr_axi_m2_i8; - input fabric_fpga_awaddr_axi_m2_i9; - output fabric_fpga_awaddr_axi_s1_o1; - output fabric_fpga_awaddr_axi_s1_o10; - output fabric_fpga_awaddr_axi_s1_o11; - output fabric_fpga_awaddr_axi_s1_o12; - output fabric_fpga_awaddr_axi_s1_o13; - output fabric_fpga_awaddr_axi_s1_o14; - output fabric_fpga_awaddr_axi_s1_o15; - output fabric_fpga_awaddr_axi_s1_o16; - output fabric_fpga_awaddr_axi_s1_o17; - output fabric_fpga_awaddr_axi_s1_o18; - output fabric_fpga_awaddr_axi_s1_o19; - output fabric_fpga_awaddr_axi_s1_o2; - output fabric_fpga_awaddr_axi_s1_o20; - output fabric_fpga_awaddr_axi_s1_o21; - output fabric_fpga_awaddr_axi_s1_o22; - output fabric_fpga_awaddr_axi_s1_o23; - output fabric_fpga_awaddr_axi_s1_o24; - output fabric_fpga_awaddr_axi_s1_o25; - output fabric_fpga_awaddr_axi_s1_o26; - output fabric_fpga_awaddr_axi_s1_o27; - output fabric_fpga_awaddr_axi_s1_o28; - output fabric_fpga_awaddr_axi_s1_o29; - output fabric_fpga_awaddr_axi_s1_o3; - output fabric_fpga_awaddr_axi_s1_o30; - output fabric_fpga_awaddr_axi_s1_o31; - output fabric_fpga_awaddr_axi_s1_o32; - output fabric_fpga_awaddr_axi_s1_o33; - output fabric_fpga_awaddr_axi_s1_o34; - output fabric_fpga_awaddr_axi_s1_o35; - output fabric_fpga_awaddr_axi_s1_o36; - output fabric_fpga_awaddr_axi_s1_o37; - output fabric_fpga_awaddr_axi_s1_o38; - output fabric_fpga_awaddr_axi_s1_o39; - output fabric_fpga_awaddr_axi_s1_o4; - output fabric_fpga_awaddr_axi_s1_o40; - output fabric_fpga_awaddr_axi_s1_o5; - output fabric_fpga_awaddr_axi_s1_o6; - output fabric_fpga_awaddr_axi_s1_o7; - output fabric_fpga_awaddr_axi_s1_o8; - output fabric_fpga_awaddr_axi_s1_o9; - output fabric_fpga_awaddr_axi_s2_o1; - output fabric_fpga_awaddr_axi_s2_o10; - output fabric_fpga_awaddr_axi_s2_o11; - output fabric_fpga_awaddr_axi_s2_o12; - output fabric_fpga_awaddr_axi_s2_o13; - output fabric_fpga_awaddr_axi_s2_o14; - output fabric_fpga_awaddr_axi_s2_o15; - output fabric_fpga_awaddr_axi_s2_o16; - output fabric_fpga_awaddr_axi_s2_o17; - output fabric_fpga_awaddr_axi_s2_o18; - output fabric_fpga_awaddr_axi_s2_o19; - output fabric_fpga_awaddr_axi_s2_o2; - output fabric_fpga_awaddr_axi_s2_o20; - output fabric_fpga_awaddr_axi_s2_o21; - output fabric_fpga_awaddr_axi_s2_o22; - output fabric_fpga_awaddr_axi_s2_o23; - output fabric_fpga_awaddr_axi_s2_o24; - output fabric_fpga_awaddr_axi_s2_o25; - output fabric_fpga_awaddr_axi_s2_o26; - output fabric_fpga_awaddr_axi_s2_o27; - output fabric_fpga_awaddr_axi_s2_o28; - output fabric_fpga_awaddr_axi_s2_o29; - output fabric_fpga_awaddr_axi_s2_o3; - output fabric_fpga_awaddr_axi_s2_o30; - output fabric_fpga_awaddr_axi_s2_o31; - output fabric_fpga_awaddr_axi_s2_o32; - output fabric_fpga_awaddr_axi_s2_o33; - output fabric_fpga_awaddr_axi_s2_o34; - output fabric_fpga_awaddr_axi_s2_o35; - output fabric_fpga_awaddr_axi_s2_o36; - output fabric_fpga_awaddr_axi_s2_o37; - output fabric_fpga_awaddr_axi_s2_o38; - output fabric_fpga_awaddr_axi_s2_o39; - output fabric_fpga_awaddr_axi_s2_o4; - output fabric_fpga_awaddr_axi_s2_o40; - output fabric_fpga_awaddr_axi_s2_o5; - output fabric_fpga_awaddr_axi_s2_o6; - output fabric_fpga_awaddr_axi_s2_o7; - output fabric_fpga_awaddr_axi_s2_o8; - output fabric_fpga_awaddr_axi_s2_o9; - input fabric_fpga_awburst_axi_m1_i1; - input fabric_fpga_awburst_axi_m1_i2; - input fabric_fpga_awburst_axi_m2_i1; - input fabric_fpga_awburst_axi_m2_i2; - output fabric_fpga_awburst_axi_s1_o1; - output fabric_fpga_awburst_axi_s1_o2; - output fabric_fpga_awburst_axi_s2_o1; - output fabric_fpga_awburst_axi_s2_o2; - input fabric_fpga_awcache_axi_m1_i1; - input fabric_fpga_awcache_axi_m1_i2; - input fabric_fpga_awcache_axi_m1_i3; - input fabric_fpga_awcache_axi_m1_i4; - input fabric_fpga_awcache_axi_m2_i1; - input fabric_fpga_awcache_axi_m2_i2; - input fabric_fpga_awcache_axi_m2_i3; - input fabric_fpga_awcache_axi_m2_i4; - output fabric_fpga_awcache_axi_s1_o1; - output fabric_fpga_awcache_axi_s1_o2; - output fabric_fpga_awcache_axi_s1_o3; - output fabric_fpga_awcache_axi_s1_o4; - output fabric_fpga_awcache_axi_s2_o1; - output fabric_fpga_awcache_axi_s2_o2; - output fabric_fpga_awcache_axi_s2_o3; - output fabric_fpga_awcache_axi_s2_o4; - input fabric_fpga_awid_axi_m1_i1; - input fabric_fpga_awid_axi_m1_i2; - input fabric_fpga_awid_axi_m1_i3; - input fabric_fpga_awid_axi_m1_i4; - input fabric_fpga_awid_axi_m1_i5; - input fabric_fpga_awid_axi_m2_i1; - input fabric_fpga_awid_axi_m2_i2; - input fabric_fpga_awid_axi_m2_i3; - input fabric_fpga_awid_axi_m2_i4; - input fabric_fpga_awid_axi_m2_i5; - output fabric_fpga_awid_axi_s1_o1; - output fabric_fpga_awid_axi_s1_o10; - output fabric_fpga_awid_axi_s1_o11; - output fabric_fpga_awid_axi_s1_o12; - output fabric_fpga_awid_axi_s1_o2; - output fabric_fpga_awid_axi_s1_o3; - output fabric_fpga_awid_axi_s1_o4; - output fabric_fpga_awid_axi_s1_o5; - output fabric_fpga_awid_axi_s1_o6; - output fabric_fpga_awid_axi_s1_o7; - output fabric_fpga_awid_axi_s1_o8; - output fabric_fpga_awid_axi_s1_o9; - output fabric_fpga_awid_axi_s2_o1; - output fabric_fpga_awid_axi_s2_o10; - output fabric_fpga_awid_axi_s2_o11; - output fabric_fpga_awid_axi_s2_o12; - output fabric_fpga_awid_axi_s2_o2; - output fabric_fpga_awid_axi_s2_o3; - output fabric_fpga_awid_axi_s2_o4; - output fabric_fpga_awid_axi_s2_o5; - output fabric_fpga_awid_axi_s2_o6; - output fabric_fpga_awid_axi_s2_o7; - output fabric_fpga_awid_axi_s2_o8; - output fabric_fpga_awid_axi_s2_o9; - input fabric_fpga_awlen_axi_m1_i1; - input fabric_fpga_awlen_axi_m1_i2; - input fabric_fpga_awlen_axi_m1_i3; - input fabric_fpga_awlen_axi_m1_i4; - input fabric_fpga_awlen_axi_m1_i5; - input fabric_fpga_awlen_axi_m1_i6; - input fabric_fpga_awlen_axi_m1_i7; - input fabric_fpga_awlen_axi_m1_i8; - input fabric_fpga_awlen_axi_m2_i1; - input fabric_fpga_awlen_axi_m2_i2; - input fabric_fpga_awlen_axi_m2_i3; - input fabric_fpga_awlen_axi_m2_i4; - input fabric_fpga_awlen_axi_m2_i5; - input fabric_fpga_awlen_axi_m2_i6; - input fabric_fpga_awlen_axi_m2_i7; - input fabric_fpga_awlen_axi_m2_i8; - output fabric_fpga_awlen_axi_s1_o1; - output fabric_fpga_awlen_axi_s1_o2; - output fabric_fpga_awlen_axi_s1_o3; - output fabric_fpga_awlen_axi_s1_o4; - output fabric_fpga_awlen_axi_s1_o5; - output fabric_fpga_awlen_axi_s1_o6; - output fabric_fpga_awlen_axi_s1_o7; - output fabric_fpga_awlen_axi_s1_o8; - output fabric_fpga_awlen_axi_s2_o1; - output fabric_fpga_awlen_axi_s2_o2; - output fabric_fpga_awlen_axi_s2_o3; - output fabric_fpga_awlen_axi_s2_o4; - output fabric_fpga_awlen_axi_s2_o5; - output fabric_fpga_awlen_axi_s2_o6; - output fabric_fpga_awlen_axi_s2_o7; - output fabric_fpga_awlen_axi_s2_o8; - input fabric_fpga_awlock_axi_m1_i; - input fabric_fpga_awlock_axi_m2_i; - output fabric_fpga_awlock_axi_s1_o; - output fabric_fpga_awlock_axi_s2_o; - input fabric_fpga_awprot_axi_m1_i1; - input fabric_fpga_awprot_axi_m1_i2; - input fabric_fpga_awprot_axi_m1_i3; - input fabric_fpga_awprot_axi_m2_i1; - input fabric_fpga_awprot_axi_m2_i2; - input fabric_fpga_awprot_axi_m2_i3; - output fabric_fpga_awprot_axi_s1_o1; - output fabric_fpga_awprot_axi_s1_o2; - output fabric_fpga_awprot_axi_s1_o3; - output fabric_fpga_awprot_axi_s2_o1; - output fabric_fpga_awprot_axi_s2_o2; - output fabric_fpga_awprot_axi_s2_o3; - input fabric_fpga_awqos_axi_m1_i1; - input fabric_fpga_awqos_axi_m1_i2; - input fabric_fpga_awqos_axi_m1_i3; - input fabric_fpga_awqos_axi_m1_i4; - input fabric_fpga_awqos_axi_m2_i1; - input fabric_fpga_awqos_axi_m2_i2; - input fabric_fpga_awqos_axi_m2_i3; - input fabric_fpga_awqos_axi_m2_i4; - output fabric_fpga_awqos_axi_s1_o1; - output fabric_fpga_awqos_axi_s1_o2; - output fabric_fpga_awqos_axi_s1_o3; - output fabric_fpga_awqos_axi_s1_o4; - output fabric_fpga_awqos_axi_s2_o1; - output fabric_fpga_awqos_axi_s2_o2; - output fabric_fpga_awqos_axi_s2_o3; - output fabric_fpga_awqos_axi_s2_o4; - output fabric_fpga_awready_axi_m1_o; - output fabric_fpga_awready_axi_m2_o; - input fabric_fpga_awready_axi_s1_i; - input fabric_fpga_awready_axi_s2_i; - output fabric_fpga_awregion_axi_s1_o1; - output fabric_fpga_awregion_axi_s1_o2; - output fabric_fpga_awregion_axi_s1_o3; - output fabric_fpga_awregion_axi_s1_o4; - output fabric_fpga_awregion_axi_s2_o1; - output fabric_fpga_awregion_axi_s2_o2; - output fabric_fpga_awregion_axi_s2_o3; - output fabric_fpga_awregion_axi_s2_o4; - input fabric_fpga_awsize_axi_m1_i1; - input fabric_fpga_awsize_axi_m1_i2; - input fabric_fpga_awsize_axi_m1_i3; - input fabric_fpga_awsize_axi_m2_i1; - input fabric_fpga_awsize_axi_m2_i2; - input fabric_fpga_awsize_axi_m2_i3; - output fabric_fpga_awsize_axi_s1_o1; - output fabric_fpga_awsize_axi_s1_o2; - output fabric_fpga_awsize_axi_s1_o3; - output fabric_fpga_awsize_axi_s2_o1; - output fabric_fpga_awsize_axi_s2_o2; - output fabric_fpga_awsize_axi_s2_o3; - input fabric_fpga_awvalid_axi_m1_i; - input fabric_fpga_awvalid_axi_m2_i; - output fabric_fpga_awvalid_axi_s1_o; - output fabric_fpga_awvalid_axi_s2_o; - output fabric_fpga_bid_axi_m1_o1; - output fabric_fpga_bid_axi_m1_o2; - output fabric_fpga_bid_axi_m1_o3; - output fabric_fpga_bid_axi_m1_o4; - output fabric_fpga_bid_axi_m1_o5; - output fabric_fpga_bid_axi_m2_o1; - output fabric_fpga_bid_axi_m2_o2; - output fabric_fpga_bid_axi_m2_o3; - output fabric_fpga_bid_axi_m2_o4; - output fabric_fpga_bid_axi_m2_o5; - input fabric_fpga_bid_axi_s1_i1; - input fabric_fpga_bid_axi_s1_i10; - input fabric_fpga_bid_axi_s1_i11; - input fabric_fpga_bid_axi_s1_i12; - input fabric_fpga_bid_axi_s1_i2; - input fabric_fpga_bid_axi_s1_i3; - input fabric_fpga_bid_axi_s1_i4; - input fabric_fpga_bid_axi_s1_i5; - input fabric_fpga_bid_axi_s1_i6; - input fabric_fpga_bid_axi_s1_i7; - input fabric_fpga_bid_axi_s1_i8; - input fabric_fpga_bid_axi_s1_i9; - input fabric_fpga_bid_axi_s2_i1; - input fabric_fpga_bid_axi_s2_i10; - input fabric_fpga_bid_axi_s2_i11; - input fabric_fpga_bid_axi_s2_i12; - input fabric_fpga_bid_axi_s2_i2; - input fabric_fpga_bid_axi_s2_i3; - input fabric_fpga_bid_axi_s2_i4; - input fabric_fpga_bid_axi_s2_i5; - input fabric_fpga_bid_axi_s2_i6; - input fabric_fpga_bid_axi_s2_i7; - input fabric_fpga_bid_axi_s2_i8; - input fabric_fpga_bid_axi_s2_i9; - input fabric_fpga_bready_axi_m1_i; - input fabric_fpga_bready_axi_m2_i; - output fabric_fpga_bready_axi_s1_o; - output fabric_fpga_bready_axi_s2_o; - output fabric_fpga_bresp_axi_m1_o1; - output fabric_fpga_bresp_axi_m1_o2; - output fabric_fpga_bresp_axi_m2_o1; - output fabric_fpga_bresp_axi_m2_o2; - input fabric_fpga_bresp_axi_s1_i1; - input fabric_fpga_bresp_axi_s1_i2; - input fabric_fpga_bresp_axi_s2_i1; - input fabric_fpga_bresp_axi_s2_i2; - output fabric_fpga_bvalid_axi_m1_o; - output fabric_fpga_bvalid_axi_m2_o; - input fabric_fpga_bvalid_axi_s1_i; - input fabric_fpga_bvalid_axi_s2_i; - input fabric_fpga_ddr0_araddr_i1; - input fabric_fpga_ddr0_araddr_i10; - input fabric_fpga_ddr0_araddr_i11; - input fabric_fpga_ddr0_araddr_i12; - input fabric_fpga_ddr0_araddr_i13; - input fabric_fpga_ddr0_araddr_i14; - input fabric_fpga_ddr0_araddr_i15; - input fabric_fpga_ddr0_araddr_i16; - input fabric_fpga_ddr0_araddr_i17; - input fabric_fpga_ddr0_araddr_i18; - input fabric_fpga_ddr0_araddr_i19; - input fabric_fpga_ddr0_araddr_i2; - input fabric_fpga_ddr0_araddr_i20; - input fabric_fpga_ddr0_araddr_i21; - input fabric_fpga_ddr0_araddr_i22; - input fabric_fpga_ddr0_araddr_i23; - input fabric_fpga_ddr0_araddr_i24; - input fabric_fpga_ddr0_araddr_i25; - input fabric_fpga_ddr0_araddr_i26; - input fabric_fpga_ddr0_araddr_i27; - input fabric_fpga_ddr0_araddr_i28; - input fabric_fpga_ddr0_araddr_i29; - input fabric_fpga_ddr0_araddr_i3; - input fabric_fpga_ddr0_araddr_i30; - input fabric_fpga_ddr0_araddr_i31; - input fabric_fpga_ddr0_araddr_i32; - input fabric_fpga_ddr0_araddr_i33; - input fabric_fpga_ddr0_araddr_i34; - input fabric_fpga_ddr0_araddr_i35; - input fabric_fpga_ddr0_araddr_i36; - input fabric_fpga_ddr0_araddr_i37; - input fabric_fpga_ddr0_araddr_i38; - input fabric_fpga_ddr0_araddr_i39; - input fabric_fpga_ddr0_araddr_i4; - input fabric_fpga_ddr0_araddr_i40; - input fabric_fpga_ddr0_araddr_i5; - input fabric_fpga_ddr0_araddr_i6; - input fabric_fpga_ddr0_araddr_i7; - input fabric_fpga_ddr0_araddr_i8; - input fabric_fpga_ddr0_araddr_i9; - input fabric_fpga_ddr0_arburst_i1; - input fabric_fpga_ddr0_arburst_i2; - input fabric_fpga_ddr0_arcache_i1; - input fabric_fpga_ddr0_arcache_i2; - input fabric_fpga_ddr0_arcache_i3; - input fabric_fpga_ddr0_arcache_i4; - input fabric_fpga_ddr0_arid_i1; - input fabric_fpga_ddr0_arid_i2; - input fabric_fpga_ddr0_arid_i3; - input fabric_fpga_ddr0_arid_i4; - input fabric_fpga_ddr0_arid_i5; - input fabric_fpga_ddr0_arlen_i1; - input fabric_fpga_ddr0_arlen_i2; - input fabric_fpga_ddr0_arlen_i3; - input fabric_fpga_ddr0_arlen_i4; - input fabric_fpga_ddr0_arlen_i5; - input fabric_fpga_ddr0_arlen_i6; - input fabric_fpga_ddr0_arlen_i7; - input fabric_fpga_ddr0_arlen_i8; - input fabric_fpga_ddr0_arlock_i; - input fabric_fpga_ddr0_arprot_i1; - input fabric_fpga_ddr0_arprot_i2; - input fabric_fpga_ddr0_arprot_i3; - input fabric_fpga_ddr0_arqos_i1; - input fabric_fpga_ddr0_arqos_i2; - input fabric_fpga_ddr0_arqos_i3; - input fabric_fpga_ddr0_arqos_i4; - output fabric_fpga_ddr0_arready_o; - input fabric_fpga_ddr0_arsize_i1; - input fabric_fpga_ddr0_arsize_i2; - input fabric_fpga_ddr0_arsize_i3; - input fabric_fpga_ddr0_arvalid_i; - input fabric_fpga_ddr0_awaddr_i1; - input fabric_fpga_ddr0_awaddr_i10; - input fabric_fpga_ddr0_awaddr_i11; - input fabric_fpga_ddr0_awaddr_i12; - input fabric_fpga_ddr0_awaddr_i13; - input fabric_fpga_ddr0_awaddr_i14; - input fabric_fpga_ddr0_awaddr_i15; - input fabric_fpga_ddr0_awaddr_i16; - input fabric_fpga_ddr0_awaddr_i17; - input fabric_fpga_ddr0_awaddr_i18; - input fabric_fpga_ddr0_awaddr_i19; - input fabric_fpga_ddr0_awaddr_i2; - input fabric_fpga_ddr0_awaddr_i20; - input fabric_fpga_ddr0_awaddr_i21; - input fabric_fpga_ddr0_awaddr_i22; - input fabric_fpga_ddr0_awaddr_i23; - input fabric_fpga_ddr0_awaddr_i24; - input fabric_fpga_ddr0_awaddr_i25; - input fabric_fpga_ddr0_awaddr_i26; - input fabric_fpga_ddr0_awaddr_i27; - input fabric_fpga_ddr0_awaddr_i28; - input fabric_fpga_ddr0_awaddr_i29; - input fabric_fpga_ddr0_awaddr_i3; - input fabric_fpga_ddr0_awaddr_i30; - input fabric_fpga_ddr0_awaddr_i31; - input fabric_fpga_ddr0_awaddr_i32; - input fabric_fpga_ddr0_awaddr_i33; - input fabric_fpga_ddr0_awaddr_i34; - input fabric_fpga_ddr0_awaddr_i35; - input fabric_fpga_ddr0_awaddr_i36; - input fabric_fpga_ddr0_awaddr_i37; - input fabric_fpga_ddr0_awaddr_i38; - input fabric_fpga_ddr0_awaddr_i39; - input fabric_fpga_ddr0_awaddr_i4; - input fabric_fpga_ddr0_awaddr_i40; - input fabric_fpga_ddr0_awaddr_i5; - input fabric_fpga_ddr0_awaddr_i6; - input fabric_fpga_ddr0_awaddr_i7; - input fabric_fpga_ddr0_awaddr_i8; - input fabric_fpga_ddr0_awaddr_i9; - input fabric_fpga_ddr0_awburst_i1; - input fabric_fpga_ddr0_awburst_i2; - input fabric_fpga_ddr0_awcache_i1; - input fabric_fpga_ddr0_awcache_i2; - input fabric_fpga_ddr0_awcache_i3; - input fabric_fpga_ddr0_awcache_i4; - input fabric_fpga_ddr0_awid_i1; - input fabric_fpga_ddr0_awid_i2; - input fabric_fpga_ddr0_awid_i3; - input fabric_fpga_ddr0_awid_i4; - input fabric_fpga_ddr0_awid_i5; - input fabric_fpga_ddr0_awlen_i1; - input fabric_fpga_ddr0_awlen_i2; - input fabric_fpga_ddr0_awlen_i3; - input fabric_fpga_ddr0_awlen_i4; - input fabric_fpga_ddr0_awlen_i5; - input fabric_fpga_ddr0_awlen_i6; - input fabric_fpga_ddr0_awlen_i7; - input fabric_fpga_ddr0_awlen_i8; - input fabric_fpga_ddr0_awlock_i; - input fabric_fpga_ddr0_awprot_i1; - input fabric_fpga_ddr0_awprot_i2; - input fabric_fpga_ddr0_awprot_i3; - input fabric_fpga_ddr0_awqos_i1; - input fabric_fpga_ddr0_awqos_i2; - input fabric_fpga_ddr0_awqos_i3; - input fabric_fpga_ddr0_awqos_i4; - output fabric_fpga_ddr0_awready_o; - input fabric_fpga_ddr0_awsize_i1; - input fabric_fpga_ddr0_awsize_i2; - input fabric_fpga_ddr0_awsize_i3; - input fabric_fpga_ddr0_awvalid_i; - output fabric_fpga_ddr0_bid_o1; - output fabric_fpga_ddr0_bid_o2; - output fabric_fpga_ddr0_bid_o3; - output fabric_fpga_ddr0_bid_o4; - output fabric_fpga_ddr0_bid_o5; - input fabric_fpga_ddr0_bready_i; - output fabric_fpga_ddr0_bresp_o1; - output fabric_fpga_ddr0_bresp_o2; - output fabric_fpga_ddr0_bvalid_o; - output fabric_fpga_ddr0_rdata_o1; - output fabric_fpga_ddr0_rdata_o10; - output fabric_fpga_ddr0_rdata_o100; - output fabric_fpga_ddr0_rdata_o101; - output fabric_fpga_ddr0_rdata_o102; - output fabric_fpga_ddr0_rdata_o103; - output fabric_fpga_ddr0_rdata_o104; - output fabric_fpga_ddr0_rdata_o105; - output fabric_fpga_ddr0_rdata_o106; - output fabric_fpga_ddr0_rdata_o107; - output fabric_fpga_ddr0_rdata_o108; - output fabric_fpga_ddr0_rdata_o109; - output fabric_fpga_ddr0_rdata_o11; - output fabric_fpga_ddr0_rdata_o110; - output fabric_fpga_ddr0_rdata_o111; - output fabric_fpga_ddr0_rdata_o112; - output fabric_fpga_ddr0_rdata_o113; - output fabric_fpga_ddr0_rdata_o114; - output fabric_fpga_ddr0_rdata_o115; - output fabric_fpga_ddr0_rdata_o116; - output fabric_fpga_ddr0_rdata_o117; - output fabric_fpga_ddr0_rdata_o118; - output fabric_fpga_ddr0_rdata_o119; - output fabric_fpga_ddr0_rdata_o12; - output fabric_fpga_ddr0_rdata_o120; - output fabric_fpga_ddr0_rdata_o121; - output fabric_fpga_ddr0_rdata_o122; - output fabric_fpga_ddr0_rdata_o123; - output fabric_fpga_ddr0_rdata_o124; - output fabric_fpga_ddr0_rdata_o125; - output fabric_fpga_ddr0_rdata_o126; - output fabric_fpga_ddr0_rdata_o127; - output fabric_fpga_ddr0_rdata_o128; - output fabric_fpga_ddr0_rdata_o13; - output fabric_fpga_ddr0_rdata_o14; - output fabric_fpga_ddr0_rdata_o15; - output fabric_fpga_ddr0_rdata_o16; - output fabric_fpga_ddr0_rdata_o17; - output fabric_fpga_ddr0_rdata_o18; - output fabric_fpga_ddr0_rdata_o19; - output fabric_fpga_ddr0_rdata_o2; - output fabric_fpga_ddr0_rdata_o20; - output fabric_fpga_ddr0_rdata_o21; - output fabric_fpga_ddr0_rdata_o22; - output fabric_fpga_ddr0_rdata_o23; - output fabric_fpga_ddr0_rdata_o24; - output fabric_fpga_ddr0_rdata_o25; - output fabric_fpga_ddr0_rdata_o26; - output fabric_fpga_ddr0_rdata_o27; - output fabric_fpga_ddr0_rdata_o28; - output fabric_fpga_ddr0_rdata_o29; - output fabric_fpga_ddr0_rdata_o3; - output fabric_fpga_ddr0_rdata_o30; - output fabric_fpga_ddr0_rdata_o31; - output fabric_fpga_ddr0_rdata_o32; - output fabric_fpga_ddr0_rdata_o33; - output fabric_fpga_ddr0_rdata_o34; - output fabric_fpga_ddr0_rdata_o35; - output fabric_fpga_ddr0_rdata_o36; - output fabric_fpga_ddr0_rdata_o37; - output fabric_fpga_ddr0_rdata_o38; - output fabric_fpga_ddr0_rdata_o39; - output fabric_fpga_ddr0_rdata_o4; - output fabric_fpga_ddr0_rdata_o40; - output fabric_fpga_ddr0_rdata_o41; - output fabric_fpga_ddr0_rdata_o42; - output fabric_fpga_ddr0_rdata_o43; - output fabric_fpga_ddr0_rdata_o44; - output fabric_fpga_ddr0_rdata_o45; - output fabric_fpga_ddr0_rdata_o46; - output fabric_fpga_ddr0_rdata_o47; - output fabric_fpga_ddr0_rdata_o48; - output fabric_fpga_ddr0_rdata_o49; - output fabric_fpga_ddr0_rdata_o5; - output fabric_fpga_ddr0_rdata_o50; - output fabric_fpga_ddr0_rdata_o51; - output fabric_fpga_ddr0_rdata_o52; - output fabric_fpga_ddr0_rdata_o53; - output fabric_fpga_ddr0_rdata_o54; - output fabric_fpga_ddr0_rdata_o55; - output fabric_fpga_ddr0_rdata_o56; - output fabric_fpga_ddr0_rdata_o57; - output fabric_fpga_ddr0_rdata_o58; - output fabric_fpga_ddr0_rdata_o59; - output fabric_fpga_ddr0_rdata_o6; - output fabric_fpga_ddr0_rdata_o60; - output fabric_fpga_ddr0_rdata_o61; - output fabric_fpga_ddr0_rdata_o62; - output fabric_fpga_ddr0_rdata_o63; - output fabric_fpga_ddr0_rdata_o64; - output fabric_fpga_ddr0_rdata_o65; - output fabric_fpga_ddr0_rdata_o66; - output fabric_fpga_ddr0_rdata_o67; - output fabric_fpga_ddr0_rdata_o68; - output fabric_fpga_ddr0_rdata_o69; - output fabric_fpga_ddr0_rdata_o7; - output fabric_fpga_ddr0_rdata_o70; - output fabric_fpga_ddr0_rdata_o71; - output fabric_fpga_ddr0_rdata_o72; - output fabric_fpga_ddr0_rdata_o73; - output fabric_fpga_ddr0_rdata_o74; - output fabric_fpga_ddr0_rdata_o75; - output fabric_fpga_ddr0_rdata_o76; - output fabric_fpga_ddr0_rdata_o77; - output fabric_fpga_ddr0_rdata_o78; - output fabric_fpga_ddr0_rdata_o79; - output fabric_fpga_ddr0_rdata_o8; - output fabric_fpga_ddr0_rdata_o80; - output fabric_fpga_ddr0_rdata_o81; - output fabric_fpga_ddr0_rdata_o82; - output fabric_fpga_ddr0_rdata_o83; - output fabric_fpga_ddr0_rdata_o84; - output fabric_fpga_ddr0_rdata_o85; - output fabric_fpga_ddr0_rdata_o86; - output fabric_fpga_ddr0_rdata_o87; - output fabric_fpga_ddr0_rdata_o88; - output fabric_fpga_ddr0_rdata_o89; - output fabric_fpga_ddr0_rdata_o9; - output fabric_fpga_ddr0_rdata_o90; - output fabric_fpga_ddr0_rdata_o91; - output fabric_fpga_ddr0_rdata_o92; - output fabric_fpga_ddr0_rdata_o93; - output fabric_fpga_ddr0_rdata_o94; - output fabric_fpga_ddr0_rdata_o95; - output fabric_fpga_ddr0_rdata_o96; - output fabric_fpga_ddr0_rdata_o97; - output fabric_fpga_ddr0_rdata_o98; - output fabric_fpga_ddr0_rdata_o99; - output fabric_fpga_ddr0_rid_o1; - output fabric_fpga_ddr0_rid_o2; - output fabric_fpga_ddr0_rid_o3; - output fabric_fpga_ddr0_rid_o4; - output fabric_fpga_ddr0_rid_o5; - output fabric_fpga_ddr0_rlast_o; - input fabric_fpga_ddr0_rready_i; - output fabric_fpga_ddr0_rresp_o1; - output fabric_fpga_ddr0_rresp_o2; - output fabric_fpga_ddr0_rvalid_o; - input fabric_fpga_ddr0_wdata_i1; - input fabric_fpga_ddr0_wdata_i10; - input fabric_fpga_ddr0_wdata_i100; - input fabric_fpga_ddr0_wdata_i101; - input fabric_fpga_ddr0_wdata_i102; - input fabric_fpga_ddr0_wdata_i103; - input fabric_fpga_ddr0_wdata_i104; - input fabric_fpga_ddr0_wdata_i105; - input fabric_fpga_ddr0_wdata_i106; - input fabric_fpga_ddr0_wdata_i107; - input fabric_fpga_ddr0_wdata_i108; - input fabric_fpga_ddr0_wdata_i109; - input fabric_fpga_ddr0_wdata_i11; - input fabric_fpga_ddr0_wdata_i110; - input fabric_fpga_ddr0_wdata_i111; - input fabric_fpga_ddr0_wdata_i112; - input fabric_fpga_ddr0_wdata_i113; - input fabric_fpga_ddr0_wdata_i114; - input fabric_fpga_ddr0_wdata_i115; - input fabric_fpga_ddr0_wdata_i116; - input fabric_fpga_ddr0_wdata_i117; - input fabric_fpga_ddr0_wdata_i118; - input fabric_fpga_ddr0_wdata_i119; - input fabric_fpga_ddr0_wdata_i12; - input fabric_fpga_ddr0_wdata_i120; - input fabric_fpga_ddr0_wdata_i121; - input fabric_fpga_ddr0_wdata_i122; - input fabric_fpga_ddr0_wdata_i123; - input fabric_fpga_ddr0_wdata_i124; - input fabric_fpga_ddr0_wdata_i125; - input fabric_fpga_ddr0_wdata_i126; - input fabric_fpga_ddr0_wdata_i127; - input fabric_fpga_ddr0_wdata_i128; - input fabric_fpga_ddr0_wdata_i13; - input fabric_fpga_ddr0_wdata_i14; - input fabric_fpga_ddr0_wdata_i15; - input fabric_fpga_ddr0_wdata_i16; - input fabric_fpga_ddr0_wdata_i17; - input fabric_fpga_ddr0_wdata_i18; - input fabric_fpga_ddr0_wdata_i19; - input fabric_fpga_ddr0_wdata_i2; - input fabric_fpga_ddr0_wdata_i20; - input fabric_fpga_ddr0_wdata_i21; - input fabric_fpga_ddr0_wdata_i22; - input fabric_fpga_ddr0_wdata_i23; - input fabric_fpga_ddr0_wdata_i24; - input fabric_fpga_ddr0_wdata_i25; - input fabric_fpga_ddr0_wdata_i26; - input fabric_fpga_ddr0_wdata_i27; - input fabric_fpga_ddr0_wdata_i28; - input fabric_fpga_ddr0_wdata_i29; - input fabric_fpga_ddr0_wdata_i3; - input fabric_fpga_ddr0_wdata_i30; - input fabric_fpga_ddr0_wdata_i31; - input fabric_fpga_ddr0_wdata_i32; - input fabric_fpga_ddr0_wdata_i33; - input fabric_fpga_ddr0_wdata_i34; - input fabric_fpga_ddr0_wdata_i35; - input fabric_fpga_ddr0_wdata_i36; - input fabric_fpga_ddr0_wdata_i37; - input fabric_fpga_ddr0_wdata_i38; - input fabric_fpga_ddr0_wdata_i39; - input fabric_fpga_ddr0_wdata_i4; - input fabric_fpga_ddr0_wdata_i40; - input fabric_fpga_ddr0_wdata_i41; - input fabric_fpga_ddr0_wdata_i42; - input fabric_fpga_ddr0_wdata_i43; - input fabric_fpga_ddr0_wdata_i44; - input fabric_fpga_ddr0_wdata_i45; - input fabric_fpga_ddr0_wdata_i46; - input fabric_fpga_ddr0_wdata_i47; - input fabric_fpga_ddr0_wdata_i48; - input fabric_fpga_ddr0_wdata_i49; - input fabric_fpga_ddr0_wdata_i5; - input fabric_fpga_ddr0_wdata_i50; - input fabric_fpga_ddr0_wdata_i51; - input fabric_fpga_ddr0_wdata_i52; - input fabric_fpga_ddr0_wdata_i53; - input fabric_fpga_ddr0_wdata_i54; - input fabric_fpga_ddr0_wdata_i55; - input fabric_fpga_ddr0_wdata_i56; - input fabric_fpga_ddr0_wdata_i57; - input fabric_fpga_ddr0_wdata_i58; - input fabric_fpga_ddr0_wdata_i59; - input fabric_fpga_ddr0_wdata_i6; - input fabric_fpga_ddr0_wdata_i60; - input fabric_fpga_ddr0_wdata_i61; - input fabric_fpga_ddr0_wdata_i62; - input fabric_fpga_ddr0_wdata_i63; - input fabric_fpga_ddr0_wdata_i64; - input fabric_fpga_ddr0_wdata_i65; - input fabric_fpga_ddr0_wdata_i66; - input fabric_fpga_ddr0_wdata_i67; - input fabric_fpga_ddr0_wdata_i68; - input fabric_fpga_ddr0_wdata_i69; - input fabric_fpga_ddr0_wdata_i7; - input fabric_fpga_ddr0_wdata_i70; - input fabric_fpga_ddr0_wdata_i71; - input fabric_fpga_ddr0_wdata_i72; - input fabric_fpga_ddr0_wdata_i73; - input fabric_fpga_ddr0_wdata_i74; - input fabric_fpga_ddr0_wdata_i75; - input fabric_fpga_ddr0_wdata_i76; - input fabric_fpga_ddr0_wdata_i77; - input fabric_fpga_ddr0_wdata_i78; - input fabric_fpga_ddr0_wdata_i79; - input fabric_fpga_ddr0_wdata_i8; - input fabric_fpga_ddr0_wdata_i80; - input fabric_fpga_ddr0_wdata_i81; - input fabric_fpga_ddr0_wdata_i82; - input fabric_fpga_ddr0_wdata_i83; - input fabric_fpga_ddr0_wdata_i84; - input fabric_fpga_ddr0_wdata_i85; - input fabric_fpga_ddr0_wdata_i86; - input fabric_fpga_ddr0_wdata_i87; - input fabric_fpga_ddr0_wdata_i88; - input fabric_fpga_ddr0_wdata_i89; - input fabric_fpga_ddr0_wdata_i9; - input fabric_fpga_ddr0_wdata_i90; - input fabric_fpga_ddr0_wdata_i91; - input fabric_fpga_ddr0_wdata_i92; - input fabric_fpga_ddr0_wdata_i93; - input fabric_fpga_ddr0_wdata_i94; - input fabric_fpga_ddr0_wdata_i95; - input fabric_fpga_ddr0_wdata_i96; - input fabric_fpga_ddr0_wdata_i97; - input fabric_fpga_ddr0_wdata_i98; - input fabric_fpga_ddr0_wdata_i99; - input fabric_fpga_ddr0_wlast_i; - output fabric_fpga_ddr0_wready_o; - input fabric_fpga_ddr0_wstrb_i1; - input fabric_fpga_ddr0_wstrb_i10; - input fabric_fpga_ddr0_wstrb_i11; - input fabric_fpga_ddr0_wstrb_i12; - input fabric_fpga_ddr0_wstrb_i13; - input fabric_fpga_ddr0_wstrb_i14; - input fabric_fpga_ddr0_wstrb_i15; - input fabric_fpga_ddr0_wstrb_i16; - input fabric_fpga_ddr0_wstrb_i2; - input fabric_fpga_ddr0_wstrb_i3; - input fabric_fpga_ddr0_wstrb_i4; - input fabric_fpga_ddr0_wstrb_i5; - input fabric_fpga_ddr0_wstrb_i6; - input fabric_fpga_ddr0_wstrb_i7; - input fabric_fpga_ddr0_wstrb_i8; - input fabric_fpga_ddr0_wstrb_i9; - input fabric_fpga_ddr0_wvalid_i; - output fabric_fpga_dma_ack_m1_o1; - output fabric_fpga_dma_ack_m1_o2; - output fabric_fpga_dma_ack_m1_o3; - output fabric_fpga_dma_ack_m1_o4; - output fabric_fpga_dma_ack_m1_o5; - output fabric_fpga_dma_ack_m1_o6; - output fabric_fpga_dma_ack_m2_o1; - output fabric_fpga_dma_ack_m2_o2; - output fabric_fpga_dma_ack_m2_o3; - output fabric_fpga_dma_ack_m2_o4; - output fabric_fpga_dma_ack_m2_o5; - output fabric_fpga_dma_ack_m2_o6; - output fabric_fpga_dma_finish_m1_o1; - output fabric_fpga_dma_finish_m1_o2; - output fabric_fpga_dma_finish_m1_o3; - output fabric_fpga_dma_finish_m1_o4; - output fabric_fpga_dma_finish_m1_o5; - output fabric_fpga_dma_finish_m1_o6; - output fabric_fpga_dma_finish_m2_o1; - output fabric_fpga_dma_finish_m2_o2; - output fabric_fpga_dma_finish_m2_o3; - output fabric_fpga_dma_finish_m2_o4; - output fabric_fpga_dma_finish_m2_o5; - output fabric_fpga_dma_finish_m2_o6; - input fabric_fpga_dma_hs_rstn_i1; - input fabric_fpga_dma_hs_rstn_i2; - input fabric_fpga_dma_hs_rstn_i3; - input fabric_fpga_dma_hs_rstn_i4; - input fabric_fpga_dma_hs_rstn_i5; - input fabric_fpga_dma_hs_rstn_i6; - input fabric_fpga_dma_last_m1_i1; - input fabric_fpga_dma_last_m1_i2; - input fabric_fpga_dma_last_m1_i3; - input fabric_fpga_dma_last_m1_i4; - input fabric_fpga_dma_last_m1_i5; - input fabric_fpga_dma_last_m1_i6; - input fabric_fpga_dma_last_m2_i1; - input fabric_fpga_dma_last_m2_i2; - input fabric_fpga_dma_last_m2_i3; - input fabric_fpga_dma_last_m2_i4; - input fabric_fpga_dma_last_m2_i5; - input fabric_fpga_dma_last_m2_i6; - input fabric_fpga_dma_req_m1_i1; - input fabric_fpga_dma_req_m1_i2; - input fabric_fpga_dma_req_m1_i3; - input fabric_fpga_dma_req_m1_i4; - input fabric_fpga_dma_req_m1_i5; - input fabric_fpga_dma_req_m1_i6; - input fabric_fpga_dma_req_m2_i1; - input fabric_fpga_dma_req_m2_i2; - input fabric_fpga_dma_req_m2_i3; - input fabric_fpga_dma_req_m2_i4; - input fabric_fpga_dma_req_m2_i5; - input fabric_fpga_dma_req_m2_i6; - input fabric_fpga_dma_single_m1_i1; - input fabric_fpga_dma_single_m1_i2; - input fabric_fpga_dma_single_m1_i3; - input fabric_fpga_dma_single_m1_i4; - input fabric_fpga_dma_single_m1_i5; - input fabric_fpga_dma_single_m1_i6; - input fabric_fpga_dma_single_m2_i1; - input fabric_fpga_dma_single_m2_i2; - input fabric_fpga_dma_single_m2_i3; - input fabric_fpga_dma_single_m2_i4; - input fabric_fpga_dma_single_m2_i5; - input fabric_fpga_dma_single_m2_i6; - input fabric_fpga_events60_i1; - input fabric_fpga_events60_i10; - input fabric_fpga_events60_i11; - input fabric_fpga_events60_i12; - input fabric_fpga_events60_i13; - input fabric_fpga_events60_i14; - input fabric_fpga_events60_i15; - input fabric_fpga_events60_i16; - input fabric_fpga_events60_i17; - input fabric_fpga_events60_i18; - input fabric_fpga_events60_i19; - input fabric_fpga_events60_i2; - input fabric_fpga_events60_i20; - input fabric_fpga_events60_i21; - input fabric_fpga_events60_i22; - input fabric_fpga_events60_i23; - input fabric_fpga_events60_i24; - input fabric_fpga_events60_i25; - input fabric_fpga_events60_i26; - input fabric_fpga_events60_i27; - input fabric_fpga_events60_i28; - input fabric_fpga_events60_i29; - input fabric_fpga_events60_i3; - input fabric_fpga_events60_i30; - input fabric_fpga_events60_i31; - input fabric_fpga_events60_i32; - input fabric_fpga_events60_i33; - input fabric_fpga_events60_i34; - input fabric_fpga_events60_i35; - input fabric_fpga_events60_i36; - input fabric_fpga_events60_i37; - input fabric_fpga_events60_i38; - input fabric_fpga_events60_i39; - input fabric_fpga_events60_i4; - input fabric_fpga_events60_i40; - input fabric_fpga_events60_i41; - input fabric_fpga_events60_i42; - input fabric_fpga_events60_i43; - input fabric_fpga_events60_i44; - input fabric_fpga_events60_i45; - input fabric_fpga_events60_i46; - input fabric_fpga_events60_i47; - input fabric_fpga_events60_i48; - input fabric_fpga_events60_i49; - input fabric_fpga_events60_i5; - input fabric_fpga_events60_i50; - input fabric_fpga_events60_i51; - input fabric_fpga_events60_i52; - input fabric_fpga_events60_i53; - input fabric_fpga_events60_i54; - input fabric_fpga_events60_i55; - input fabric_fpga_events60_i56; - input fabric_fpga_events60_i57; - input fabric_fpga_events60_i58; - input fabric_fpga_events60_i59; - input fabric_fpga_events60_i6; - input fabric_fpga_events60_i60; - input fabric_fpga_events60_i7; - input fabric_fpga_events60_i8; - input fabric_fpga_events60_i9; - input fabric_fpga_interrupt_in_i1; - input fabric_fpga_interrupt_in_i10; - input fabric_fpga_interrupt_in_i100; - input fabric_fpga_interrupt_in_i101; - input fabric_fpga_interrupt_in_i102; - input fabric_fpga_interrupt_in_i103; - input fabric_fpga_interrupt_in_i104; - input fabric_fpga_interrupt_in_i105; - input fabric_fpga_interrupt_in_i106; - input fabric_fpga_interrupt_in_i107; - input fabric_fpga_interrupt_in_i108; - input fabric_fpga_interrupt_in_i109; - input fabric_fpga_interrupt_in_i11; - input fabric_fpga_interrupt_in_i110; - input fabric_fpga_interrupt_in_i111; - input fabric_fpga_interrupt_in_i112; - input fabric_fpga_interrupt_in_i113; - input fabric_fpga_interrupt_in_i114; - input fabric_fpga_interrupt_in_i115; - input fabric_fpga_interrupt_in_i116; - input fabric_fpga_interrupt_in_i117; - input fabric_fpga_interrupt_in_i118; - input fabric_fpga_interrupt_in_i119; - input fabric_fpga_interrupt_in_i12; - input fabric_fpga_interrupt_in_i120; - input fabric_fpga_interrupt_in_i13; - input fabric_fpga_interrupt_in_i14; - input fabric_fpga_interrupt_in_i15; - input fabric_fpga_interrupt_in_i16; - input fabric_fpga_interrupt_in_i17; - input fabric_fpga_interrupt_in_i18; - input fabric_fpga_interrupt_in_i19; - input fabric_fpga_interrupt_in_i2; - input fabric_fpga_interrupt_in_i20; - input fabric_fpga_interrupt_in_i21; - input fabric_fpga_interrupt_in_i22; - input fabric_fpga_interrupt_in_i23; - input fabric_fpga_interrupt_in_i24; - input fabric_fpga_interrupt_in_i25; - input fabric_fpga_interrupt_in_i26; - input fabric_fpga_interrupt_in_i27; - input fabric_fpga_interrupt_in_i28; - input fabric_fpga_interrupt_in_i29; - input fabric_fpga_interrupt_in_i3; - input fabric_fpga_interrupt_in_i30; - input fabric_fpga_interrupt_in_i31; - input fabric_fpga_interrupt_in_i32; - input fabric_fpga_interrupt_in_i33; - input fabric_fpga_interrupt_in_i34; - input fabric_fpga_interrupt_in_i35; - input fabric_fpga_interrupt_in_i36; - input fabric_fpga_interrupt_in_i37; - input fabric_fpga_interrupt_in_i38; - input fabric_fpga_interrupt_in_i39; - input fabric_fpga_interrupt_in_i4; - input fabric_fpga_interrupt_in_i40; - input fabric_fpga_interrupt_in_i41; - input fabric_fpga_interrupt_in_i42; - input fabric_fpga_interrupt_in_i43; - input fabric_fpga_interrupt_in_i44; - input fabric_fpga_interrupt_in_i45; - input fabric_fpga_interrupt_in_i46; - input fabric_fpga_interrupt_in_i47; - input fabric_fpga_interrupt_in_i48; - input fabric_fpga_interrupt_in_i49; - input fabric_fpga_interrupt_in_i5; - input fabric_fpga_interrupt_in_i50; - input fabric_fpga_interrupt_in_i51; - input fabric_fpga_interrupt_in_i52; - input fabric_fpga_interrupt_in_i53; - input fabric_fpga_interrupt_in_i54; - input fabric_fpga_interrupt_in_i55; - input fabric_fpga_interrupt_in_i56; - input fabric_fpga_interrupt_in_i57; - input fabric_fpga_interrupt_in_i58; - input fabric_fpga_interrupt_in_i59; - input fabric_fpga_interrupt_in_i6; - input fabric_fpga_interrupt_in_i60; - input fabric_fpga_interrupt_in_i61; - input fabric_fpga_interrupt_in_i62; - input fabric_fpga_interrupt_in_i63; - input fabric_fpga_interrupt_in_i64; - input fabric_fpga_interrupt_in_i65; - input fabric_fpga_interrupt_in_i66; - input fabric_fpga_interrupt_in_i67; - input fabric_fpga_interrupt_in_i68; - input fabric_fpga_interrupt_in_i69; - input fabric_fpga_interrupt_in_i7; - input fabric_fpga_interrupt_in_i70; - input fabric_fpga_interrupt_in_i71; - input fabric_fpga_interrupt_in_i72; - input fabric_fpga_interrupt_in_i73; - input fabric_fpga_interrupt_in_i74; - input fabric_fpga_interrupt_in_i75; - input fabric_fpga_interrupt_in_i76; - input fabric_fpga_interrupt_in_i77; - input fabric_fpga_interrupt_in_i78; - input fabric_fpga_interrupt_in_i79; - input fabric_fpga_interrupt_in_i8; - input fabric_fpga_interrupt_in_i80; - input fabric_fpga_interrupt_in_i81; - input fabric_fpga_interrupt_in_i82; - input fabric_fpga_interrupt_in_i83; - input fabric_fpga_interrupt_in_i84; - input fabric_fpga_interrupt_in_i85; - input fabric_fpga_interrupt_in_i86; - input fabric_fpga_interrupt_in_i87; - input fabric_fpga_interrupt_in_i88; - input fabric_fpga_interrupt_in_i89; - input fabric_fpga_interrupt_in_i9; - input fabric_fpga_interrupt_in_i90; - input fabric_fpga_interrupt_in_i91; - input fabric_fpga_interrupt_in_i92; - input fabric_fpga_interrupt_in_i93; - input fabric_fpga_interrupt_in_i94; - input fabric_fpga_interrupt_in_i95; - input fabric_fpga_interrupt_in_i96; - input fabric_fpga_interrupt_in_i97; - input fabric_fpga_interrupt_in_i98; - input fabric_fpga_interrupt_in_i99; - input fabric_fpga_nic_rstn_i1; - input fabric_fpga_nic_rstn_i10; - input fabric_fpga_nic_rstn_i2; - input fabric_fpga_nic_rstn_i3; - input fabric_fpga_nic_rstn_i4; - input fabric_fpga_nic_rstn_i5; - input fabric_fpga_nic_rstn_i6; - input fabric_fpga_nic_rstn_i7; - input fabric_fpga_nic_rstn_i8; - input fabric_fpga_nic_rstn_i9; - output fabric_fpga_paddr_apb_o1; - output fabric_fpga_paddr_apb_o10; - output fabric_fpga_paddr_apb_o11; - output fabric_fpga_paddr_apb_o12; - output fabric_fpga_paddr_apb_o13; - output fabric_fpga_paddr_apb_o14; - output fabric_fpga_paddr_apb_o15; - output fabric_fpga_paddr_apb_o16; - output fabric_fpga_paddr_apb_o17; - output fabric_fpga_paddr_apb_o18; - output fabric_fpga_paddr_apb_o19; - output fabric_fpga_paddr_apb_o2; - output fabric_fpga_paddr_apb_o20; - output fabric_fpga_paddr_apb_o21; - output fabric_fpga_paddr_apb_o22; - output fabric_fpga_paddr_apb_o23; - output fabric_fpga_paddr_apb_o24; - output fabric_fpga_paddr_apb_o25; - output fabric_fpga_paddr_apb_o26; - output fabric_fpga_paddr_apb_o27; - output fabric_fpga_paddr_apb_o28; - output fabric_fpga_paddr_apb_o29; - output fabric_fpga_paddr_apb_o3; - output fabric_fpga_paddr_apb_o30; - output fabric_fpga_paddr_apb_o31; - output fabric_fpga_paddr_apb_o32; - output fabric_fpga_paddr_apb_o4; - output fabric_fpga_paddr_apb_o5; - output fabric_fpga_paddr_apb_o6; - output fabric_fpga_paddr_apb_o7; - output fabric_fpga_paddr_apb_o8; - output fabric_fpga_paddr_apb_o9; - output fabric_fpga_penable_apb_o; - input fabric_fpga_pmrstn_i; - input fabric_fpga_prdata_apb_i1; - input fabric_fpga_prdata_apb_i10; - input fabric_fpga_prdata_apb_i11; - input fabric_fpga_prdata_apb_i12; - input fabric_fpga_prdata_apb_i13; - input fabric_fpga_prdata_apb_i14; - input fabric_fpga_prdata_apb_i15; - input fabric_fpga_prdata_apb_i16; - input fabric_fpga_prdata_apb_i17; - input fabric_fpga_prdata_apb_i18; - input fabric_fpga_prdata_apb_i19; - input fabric_fpga_prdata_apb_i2; - input fabric_fpga_prdata_apb_i20; - input fabric_fpga_prdata_apb_i21; - input fabric_fpga_prdata_apb_i22; - input fabric_fpga_prdata_apb_i23; - input fabric_fpga_prdata_apb_i24; - input fabric_fpga_prdata_apb_i25; - input fabric_fpga_prdata_apb_i26; - input fabric_fpga_prdata_apb_i27; - input fabric_fpga_prdata_apb_i28; - input fabric_fpga_prdata_apb_i29; - input fabric_fpga_prdata_apb_i3; - input fabric_fpga_prdata_apb_i30; - input fabric_fpga_prdata_apb_i31; - input fabric_fpga_prdata_apb_i32; - input fabric_fpga_prdata_apb_i4; - input fabric_fpga_prdata_apb_i5; - input fabric_fpga_prdata_apb_i6; - input fabric_fpga_prdata_apb_i7; - input fabric_fpga_prdata_apb_i8; - input fabric_fpga_prdata_apb_i9; - input fabric_fpga_pready_apb_i; - output fabric_fpga_psel_apb_o; - input fabric_fpga_pslverr_apb_i; - output fabric_fpga_pwdata_apb_o1; - output fabric_fpga_pwdata_apb_o10; - output fabric_fpga_pwdata_apb_o11; - output fabric_fpga_pwdata_apb_o12; - output fabric_fpga_pwdata_apb_o13; - output fabric_fpga_pwdata_apb_o14; - output fabric_fpga_pwdata_apb_o15; - output fabric_fpga_pwdata_apb_o16; - output fabric_fpga_pwdata_apb_o17; - output fabric_fpga_pwdata_apb_o18; - output fabric_fpga_pwdata_apb_o19; - output fabric_fpga_pwdata_apb_o2; - output fabric_fpga_pwdata_apb_o20; - output fabric_fpga_pwdata_apb_o21; - output fabric_fpga_pwdata_apb_o22; - output fabric_fpga_pwdata_apb_o23; - output fabric_fpga_pwdata_apb_o24; - output fabric_fpga_pwdata_apb_o25; - output fabric_fpga_pwdata_apb_o26; - output fabric_fpga_pwdata_apb_o27; - output fabric_fpga_pwdata_apb_o28; - output fabric_fpga_pwdata_apb_o29; - output fabric_fpga_pwdata_apb_o3; - output fabric_fpga_pwdata_apb_o30; - output fabric_fpga_pwdata_apb_o31; - output fabric_fpga_pwdata_apb_o32; - output fabric_fpga_pwdata_apb_o4; - output fabric_fpga_pwdata_apb_o5; - output fabric_fpga_pwdata_apb_o6; - output fabric_fpga_pwdata_apb_o7; - output fabric_fpga_pwdata_apb_o8; - output fabric_fpga_pwdata_apb_o9; - output fabric_fpga_pwrite_apb_o; - output fabric_fpga_rdata_axi_m1_o1; - output fabric_fpga_rdata_axi_m1_o10; - output fabric_fpga_rdata_axi_m1_o100; - output fabric_fpga_rdata_axi_m1_o101; - output fabric_fpga_rdata_axi_m1_o102; - output fabric_fpga_rdata_axi_m1_o103; - output fabric_fpga_rdata_axi_m1_o104; - output fabric_fpga_rdata_axi_m1_o105; - output fabric_fpga_rdata_axi_m1_o106; - output fabric_fpga_rdata_axi_m1_o107; - output fabric_fpga_rdata_axi_m1_o108; - output fabric_fpga_rdata_axi_m1_o109; - output fabric_fpga_rdata_axi_m1_o11; - output fabric_fpga_rdata_axi_m1_o110; - output fabric_fpga_rdata_axi_m1_o111; - output fabric_fpga_rdata_axi_m1_o112; - output fabric_fpga_rdata_axi_m1_o113; - output fabric_fpga_rdata_axi_m1_o114; - output fabric_fpga_rdata_axi_m1_o115; - output fabric_fpga_rdata_axi_m1_o116; - output fabric_fpga_rdata_axi_m1_o117; - output fabric_fpga_rdata_axi_m1_o118; - output fabric_fpga_rdata_axi_m1_o119; - output fabric_fpga_rdata_axi_m1_o12; - output fabric_fpga_rdata_axi_m1_o120; - output fabric_fpga_rdata_axi_m1_o121; - output fabric_fpga_rdata_axi_m1_o122; - output fabric_fpga_rdata_axi_m1_o123; - output fabric_fpga_rdata_axi_m1_o124; - output fabric_fpga_rdata_axi_m1_o125; - output fabric_fpga_rdata_axi_m1_o126; - output fabric_fpga_rdata_axi_m1_o127; - output fabric_fpga_rdata_axi_m1_o128; - output fabric_fpga_rdata_axi_m1_o13; - output fabric_fpga_rdata_axi_m1_o14; - output fabric_fpga_rdata_axi_m1_o15; - output fabric_fpga_rdata_axi_m1_o16; - output fabric_fpga_rdata_axi_m1_o17; - output fabric_fpga_rdata_axi_m1_o18; - output fabric_fpga_rdata_axi_m1_o19; - output fabric_fpga_rdata_axi_m1_o2; - output fabric_fpga_rdata_axi_m1_o20; - output fabric_fpga_rdata_axi_m1_o21; - output fabric_fpga_rdata_axi_m1_o22; - output fabric_fpga_rdata_axi_m1_o23; - output fabric_fpga_rdata_axi_m1_o24; - output fabric_fpga_rdata_axi_m1_o25; - output fabric_fpga_rdata_axi_m1_o26; - output fabric_fpga_rdata_axi_m1_o27; - output fabric_fpga_rdata_axi_m1_o28; - output fabric_fpga_rdata_axi_m1_o29; - output fabric_fpga_rdata_axi_m1_o3; - output fabric_fpga_rdata_axi_m1_o30; - output fabric_fpga_rdata_axi_m1_o31; - output fabric_fpga_rdata_axi_m1_o32; - output fabric_fpga_rdata_axi_m1_o33; - output fabric_fpga_rdata_axi_m1_o34; - output fabric_fpga_rdata_axi_m1_o35; - output fabric_fpga_rdata_axi_m1_o36; - output fabric_fpga_rdata_axi_m1_o37; - output fabric_fpga_rdata_axi_m1_o38; - output fabric_fpga_rdata_axi_m1_o39; - output fabric_fpga_rdata_axi_m1_o4; - output fabric_fpga_rdata_axi_m1_o40; - output fabric_fpga_rdata_axi_m1_o41; - output fabric_fpga_rdata_axi_m1_o42; - output fabric_fpga_rdata_axi_m1_o43; - output fabric_fpga_rdata_axi_m1_o44; - output fabric_fpga_rdata_axi_m1_o45; - output fabric_fpga_rdata_axi_m1_o46; - output fabric_fpga_rdata_axi_m1_o47; - output fabric_fpga_rdata_axi_m1_o48; - output fabric_fpga_rdata_axi_m1_o49; - output fabric_fpga_rdata_axi_m1_o5; - output fabric_fpga_rdata_axi_m1_o50; - output fabric_fpga_rdata_axi_m1_o51; - output fabric_fpga_rdata_axi_m1_o52; - output fabric_fpga_rdata_axi_m1_o53; - output fabric_fpga_rdata_axi_m1_o54; - output fabric_fpga_rdata_axi_m1_o55; - output fabric_fpga_rdata_axi_m1_o56; - output fabric_fpga_rdata_axi_m1_o57; - output fabric_fpga_rdata_axi_m1_o58; - output fabric_fpga_rdata_axi_m1_o59; - output fabric_fpga_rdata_axi_m1_o6; - output fabric_fpga_rdata_axi_m1_o60; - output fabric_fpga_rdata_axi_m1_o61; - output fabric_fpga_rdata_axi_m1_o62; - output fabric_fpga_rdata_axi_m1_o63; - output fabric_fpga_rdata_axi_m1_o64; - output fabric_fpga_rdata_axi_m1_o65; - output fabric_fpga_rdata_axi_m1_o66; - output fabric_fpga_rdata_axi_m1_o67; - output fabric_fpga_rdata_axi_m1_o68; - output fabric_fpga_rdata_axi_m1_o69; - output fabric_fpga_rdata_axi_m1_o7; - output fabric_fpga_rdata_axi_m1_o70; - output fabric_fpga_rdata_axi_m1_o71; - output fabric_fpga_rdata_axi_m1_o72; - output fabric_fpga_rdata_axi_m1_o73; - output fabric_fpga_rdata_axi_m1_o74; - output fabric_fpga_rdata_axi_m1_o75; - output fabric_fpga_rdata_axi_m1_o76; - output fabric_fpga_rdata_axi_m1_o77; - output fabric_fpga_rdata_axi_m1_o78; - output fabric_fpga_rdata_axi_m1_o79; - output fabric_fpga_rdata_axi_m1_o8; - output fabric_fpga_rdata_axi_m1_o80; - output fabric_fpga_rdata_axi_m1_o81; - output fabric_fpga_rdata_axi_m1_o82; - output fabric_fpga_rdata_axi_m1_o83; - output fabric_fpga_rdata_axi_m1_o84; - output fabric_fpga_rdata_axi_m1_o85; - output fabric_fpga_rdata_axi_m1_o86; - output fabric_fpga_rdata_axi_m1_o87; - output fabric_fpga_rdata_axi_m1_o88; - output fabric_fpga_rdata_axi_m1_o89; - output fabric_fpga_rdata_axi_m1_o9; - output fabric_fpga_rdata_axi_m1_o90; - output fabric_fpga_rdata_axi_m1_o91; - output fabric_fpga_rdata_axi_m1_o92; - output fabric_fpga_rdata_axi_m1_o93; - output fabric_fpga_rdata_axi_m1_o94; - output fabric_fpga_rdata_axi_m1_o95; - output fabric_fpga_rdata_axi_m1_o96; - output fabric_fpga_rdata_axi_m1_o97; - output fabric_fpga_rdata_axi_m1_o98; - output fabric_fpga_rdata_axi_m1_o99; - output fabric_fpga_rdata_axi_m2_o1; - output fabric_fpga_rdata_axi_m2_o10; - output fabric_fpga_rdata_axi_m2_o100; - output fabric_fpga_rdata_axi_m2_o101; - output fabric_fpga_rdata_axi_m2_o102; - output fabric_fpga_rdata_axi_m2_o103; - output fabric_fpga_rdata_axi_m2_o104; - output fabric_fpga_rdata_axi_m2_o105; - output fabric_fpga_rdata_axi_m2_o106; - output fabric_fpga_rdata_axi_m2_o107; - output fabric_fpga_rdata_axi_m2_o108; - output fabric_fpga_rdata_axi_m2_o109; - output fabric_fpga_rdata_axi_m2_o11; - output fabric_fpga_rdata_axi_m2_o110; - output fabric_fpga_rdata_axi_m2_o111; - output fabric_fpga_rdata_axi_m2_o112; - output fabric_fpga_rdata_axi_m2_o113; - output fabric_fpga_rdata_axi_m2_o114; - output fabric_fpga_rdata_axi_m2_o115; - output fabric_fpga_rdata_axi_m2_o116; - output fabric_fpga_rdata_axi_m2_o117; - output fabric_fpga_rdata_axi_m2_o118; - output fabric_fpga_rdata_axi_m2_o119; - output fabric_fpga_rdata_axi_m2_o12; - output fabric_fpga_rdata_axi_m2_o120; - output fabric_fpga_rdata_axi_m2_o121; - output fabric_fpga_rdata_axi_m2_o122; - output fabric_fpga_rdata_axi_m2_o123; - output fabric_fpga_rdata_axi_m2_o124; - output fabric_fpga_rdata_axi_m2_o125; - output fabric_fpga_rdata_axi_m2_o126; - output fabric_fpga_rdata_axi_m2_o127; - output fabric_fpga_rdata_axi_m2_o128; - output fabric_fpga_rdata_axi_m2_o13; - output fabric_fpga_rdata_axi_m2_o14; - output fabric_fpga_rdata_axi_m2_o15; - output fabric_fpga_rdata_axi_m2_o16; - output fabric_fpga_rdata_axi_m2_o17; - output fabric_fpga_rdata_axi_m2_o18; - output fabric_fpga_rdata_axi_m2_o19; - output fabric_fpga_rdata_axi_m2_o2; - output fabric_fpga_rdata_axi_m2_o20; - output fabric_fpga_rdata_axi_m2_o21; - output fabric_fpga_rdata_axi_m2_o22; - output fabric_fpga_rdata_axi_m2_o23; - output fabric_fpga_rdata_axi_m2_o24; - output fabric_fpga_rdata_axi_m2_o25; - output fabric_fpga_rdata_axi_m2_o26; - output fabric_fpga_rdata_axi_m2_o27; - output fabric_fpga_rdata_axi_m2_o28; - output fabric_fpga_rdata_axi_m2_o29; - output fabric_fpga_rdata_axi_m2_o3; - output fabric_fpga_rdata_axi_m2_o30; - output fabric_fpga_rdata_axi_m2_o31; - output fabric_fpga_rdata_axi_m2_o32; - output fabric_fpga_rdata_axi_m2_o33; - output fabric_fpga_rdata_axi_m2_o34; - output fabric_fpga_rdata_axi_m2_o35; - output fabric_fpga_rdata_axi_m2_o36; - output fabric_fpga_rdata_axi_m2_o37; - output fabric_fpga_rdata_axi_m2_o38; - output fabric_fpga_rdata_axi_m2_o39; - output fabric_fpga_rdata_axi_m2_o4; - output fabric_fpga_rdata_axi_m2_o40; - output fabric_fpga_rdata_axi_m2_o41; - output fabric_fpga_rdata_axi_m2_o42; - output fabric_fpga_rdata_axi_m2_o43; - output fabric_fpga_rdata_axi_m2_o44; - output fabric_fpga_rdata_axi_m2_o45; - output fabric_fpga_rdata_axi_m2_o46; - output fabric_fpga_rdata_axi_m2_o47; - output fabric_fpga_rdata_axi_m2_o48; - output fabric_fpga_rdata_axi_m2_o49; - output fabric_fpga_rdata_axi_m2_o5; - output fabric_fpga_rdata_axi_m2_o50; - output fabric_fpga_rdata_axi_m2_o51; - output fabric_fpga_rdata_axi_m2_o52; - output fabric_fpga_rdata_axi_m2_o53; - output fabric_fpga_rdata_axi_m2_o54; - output fabric_fpga_rdata_axi_m2_o55; - output fabric_fpga_rdata_axi_m2_o56; - output fabric_fpga_rdata_axi_m2_o57; - output fabric_fpga_rdata_axi_m2_o58; - output fabric_fpga_rdata_axi_m2_o59; - output fabric_fpga_rdata_axi_m2_o6; - output fabric_fpga_rdata_axi_m2_o60; - output fabric_fpga_rdata_axi_m2_o61; - output fabric_fpga_rdata_axi_m2_o62; - output fabric_fpga_rdata_axi_m2_o63; - output fabric_fpga_rdata_axi_m2_o64; - output fabric_fpga_rdata_axi_m2_o65; - output fabric_fpga_rdata_axi_m2_o66; - output fabric_fpga_rdata_axi_m2_o67; - output fabric_fpga_rdata_axi_m2_o68; - output fabric_fpga_rdata_axi_m2_o69; - output fabric_fpga_rdata_axi_m2_o7; - output fabric_fpga_rdata_axi_m2_o70; - output fabric_fpga_rdata_axi_m2_o71; - output fabric_fpga_rdata_axi_m2_o72; - output fabric_fpga_rdata_axi_m2_o73; - output fabric_fpga_rdata_axi_m2_o74; - output fabric_fpga_rdata_axi_m2_o75; - output fabric_fpga_rdata_axi_m2_o76; - output fabric_fpga_rdata_axi_m2_o77; - output fabric_fpga_rdata_axi_m2_o78; - output fabric_fpga_rdata_axi_m2_o79; - output fabric_fpga_rdata_axi_m2_o8; - output fabric_fpga_rdata_axi_m2_o80; - output fabric_fpga_rdata_axi_m2_o81; - output fabric_fpga_rdata_axi_m2_o82; - output fabric_fpga_rdata_axi_m2_o83; - output fabric_fpga_rdata_axi_m2_o84; - output fabric_fpga_rdata_axi_m2_o85; - output fabric_fpga_rdata_axi_m2_o86; - output fabric_fpga_rdata_axi_m2_o87; - output fabric_fpga_rdata_axi_m2_o88; - output fabric_fpga_rdata_axi_m2_o89; - output fabric_fpga_rdata_axi_m2_o9; - output fabric_fpga_rdata_axi_m2_o90; - output fabric_fpga_rdata_axi_m2_o91; - output fabric_fpga_rdata_axi_m2_o92; - output fabric_fpga_rdata_axi_m2_o93; - output fabric_fpga_rdata_axi_m2_o94; - output fabric_fpga_rdata_axi_m2_o95; - output fabric_fpga_rdata_axi_m2_o96; - output fabric_fpga_rdata_axi_m2_o97; - output fabric_fpga_rdata_axi_m2_o98; - output fabric_fpga_rdata_axi_m2_o99; - input fabric_fpga_rdata_axi_s1_i1; - input fabric_fpga_rdata_axi_s1_i10; - input fabric_fpga_rdata_axi_s1_i100; - input fabric_fpga_rdata_axi_s1_i101; - input fabric_fpga_rdata_axi_s1_i102; - input fabric_fpga_rdata_axi_s1_i103; - input fabric_fpga_rdata_axi_s1_i104; - input fabric_fpga_rdata_axi_s1_i105; - input fabric_fpga_rdata_axi_s1_i106; - input fabric_fpga_rdata_axi_s1_i107; - input fabric_fpga_rdata_axi_s1_i108; - input fabric_fpga_rdata_axi_s1_i109; - input fabric_fpga_rdata_axi_s1_i11; - input fabric_fpga_rdata_axi_s1_i110; - input fabric_fpga_rdata_axi_s1_i111; - input fabric_fpga_rdata_axi_s1_i112; - input fabric_fpga_rdata_axi_s1_i113; - input fabric_fpga_rdata_axi_s1_i114; - input fabric_fpga_rdata_axi_s1_i115; - input fabric_fpga_rdata_axi_s1_i116; - input fabric_fpga_rdata_axi_s1_i117; - input fabric_fpga_rdata_axi_s1_i118; - input fabric_fpga_rdata_axi_s1_i119; - input fabric_fpga_rdata_axi_s1_i12; - input fabric_fpga_rdata_axi_s1_i120; - input fabric_fpga_rdata_axi_s1_i121; - input fabric_fpga_rdata_axi_s1_i122; - input fabric_fpga_rdata_axi_s1_i123; - input fabric_fpga_rdata_axi_s1_i124; - input fabric_fpga_rdata_axi_s1_i125; - input fabric_fpga_rdata_axi_s1_i126; - input fabric_fpga_rdata_axi_s1_i127; - input fabric_fpga_rdata_axi_s1_i128; - input fabric_fpga_rdata_axi_s1_i13; - input fabric_fpga_rdata_axi_s1_i14; - input fabric_fpga_rdata_axi_s1_i15; - input fabric_fpga_rdata_axi_s1_i16; - input fabric_fpga_rdata_axi_s1_i17; - input fabric_fpga_rdata_axi_s1_i18; - input fabric_fpga_rdata_axi_s1_i19; - input fabric_fpga_rdata_axi_s1_i2; - input fabric_fpga_rdata_axi_s1_i20; - input fabric_fpga_rdata_axi_s1_i21; - input fabric_fpga_rdata_axi_s1_i22; - input fabric_fpga_rdata_axi_s1_i23; - input fabric_fpga_rdata_axi_s1_i24; - input fabric_fpga_rdata_axi_s1_i25; - input fabric_fpga_rdata_axi_s1_i26; - input fabric_fpga_rdata_axi_s1_i27; - input fabric_fpga_rdata_axi_s1_i28; - input fabric_fpga_rdata_axi_s1_i29; - input fabric_fpga_rdata_axi_s1_i3; - input fabric_fpga_rdata_axi_s1_i30; - input fabric_fpga_rdata_axi_s1_i31; - input fabric_fpga_rdata_axi_s1_i32; - input fabric_fpga_rdata_axi_s1_i33; - input fabric_fpga_rdata_axi_s1_i34; - input fabric_fpga_rdata_axi_s1_i35; - input fabric_fpga_rdata_axi_s1_i36; - input fabric_fpga_rdata_axi_s1_i37; - input fabric_fpga_rdata_axi_s1_i38; - input fabric_fpga_rdata_axi_s1_i39; - input fabric_fpga_rdata_axi_s1_i4; - input fabric_fpga_rdata_axi_s1_i40; - input fabric_fpga_rdata_axi_s1_i41; - input fabric_fpga_rdata_axi_s1_i42; - input fabric_fpga_rdata_axi_s1_i43; - input fabric_fpga_rdata_axi_s1_i44; - input fabric_fpga_rdata_axi_s1_i45; - input fabric_fpga_rdata_axi_s1_i46; - input fabric_fpga_rdata_axi_s1_i47; - input fabric_fpga_rdata_axi_s1_i48; - input fabric_fpga_rdata_axi_s1_i49; - input fabric_fpga_rdata_axi_s1_i5; - input fabric_fpga_rdata_axi_s1_i50; - input fabric_fpga_rdata_axi_s1_i51; - input fabric_fpga_rdata_axi_s1_i52; - input fabric_fpga_rdata_axi_s1_i53; - input fabric_fpga_rdata_axi_s1_i54; - input fabric_fpga_rdata_axi_s1_i55; - input fabric_fpga_rdata_axi_s1_i56; - input fabric_fpga_rdata_axi_s1_i57; - input fabric_fpga_rdata_axi_s1_i58; - input fabric_fpga_rdata_axi_s1_i59; - input fabric_fpga_rdata_axi_s1_i6; - input fabric_fpga_rdata_axi_s1_i60; - input fabric_fpga_rdata_axi_s1_i61; - input fabric_fpga_rdata_axi_s1_i62; - input fabric_fpga_rdata_axi_s1_i63; - input fabric_fpga_rdata_axi_s1_i64; - input fabric_fpga_rdata_axi_s1_i65; - input fabric_fpga_rdata_axi_s1_i66; - input fabric_fpga_rdata_axi_s1_i67; - input fabric_fpga_rdata_axi_s1_i68; - input fabric_fpga_rdata_axi_s1_i69; - input fabric_fpga_rdata_axi_s1_i7; - input fabric_fpga_rdata_axi_s1_i70; - input fabric_fpga_rdata_axi_s1_i71; - input fabric_fpga_rdata_axi_s1_i72; - input fabric_fpga_rdata_axi_s1_i73; - input fabric_fpga_rdata_axi_s1_i74; - input fabric_fpga_rdata_axi_s1_i75; - input fabric_fpga_rdata_axi_s1_i76; - input fabric_fpga_rdata_axi_s1_i77; - input fabric_fpga_rdata_axi_s1_i78; - input fabric_fpga_rdata_axi_s1_i79; - input fabric_fpga_rdata_axi_s1_i8; - input fabric_fpga_rdata_axi_s1_i80; - input fabric_fpga_rdata_axi_s1_i81; - input fabric_fpga_rdata_axi_s1_i82; - input fabric_fpga_rdata_axi_s1_i83; - input fabric_fpga_rdata_axi_s1_i84; - input fabric_fpga_rdata_axi_s1_i85; - input fabric_fpga_rdata_axi_s1_i86; - input fabric_fpga_rdata_axi_s1_i87; - input fabric_fpga_rdata_axi_s1_i88; - input fabric_fpga_rdata_axi_s1_i89; - input fabric_fpga_rdata_axi_s1_i9; - input fabric_fpga_rdata_axi_s1_i90; - input fabric_fpga_rdata_axi_s1_i91; - input fabric_fpga_rdata_axi_s1_i92; - input fabric_fpga_rdata_axi_s1_i93; - input fabric_fpga_rdata_axi_s1_i94; - input fabric_fpga_rdata_axi_s1_i95; - input fabric_fpga_rdata_axi_s1_i96; - input fabric_fpga_rdata_axi_s1_i97; - input fabric_fpga_rdata_axi_s1_i98; - input fabric_fpga_rdata_axi_s1_i99; - input fabric_fpga_rdata_axi_s2_i1; - input fabric_fpga_rdata_axi_s2_i10; - input fabric_fpga_rdata_axi_s2_i100; - input fabric_fpga_rdata_axi_s2_i101; - input fabric_fpga_rdata_axi_s2_i102; - input fabric_fpga_rdata_axi_s2_i103; - input fabric_fpga_rdata_axi_s2_i104; - input fabric_fpga_rdata_axi_s2_i105; - input fabric_fpga_rdata_axi_s2_i106; - input fabric_fpga_rdata_axi_s2_i107; - input fabric_fpga_rdata_axi_s2_i108; - input fabric_fpga_rdata_axi_s2_i109; - input fabric_fpga_rdata_axi_s2_i11; - input fabric_fpga_rdata_axi_s2_i110; - input fabric_fpga_rdata_axi_s2_i111; - input fabric_fpga_rdata_axi_s2_i112; - input fabric_fpga_rdata_axi_s2_i113; - input fabric_fpga_rdata_axi_s2_i114; - input fabric_fpga_rdata_axi_s2_i115; - input fabric_fpga_rdata_axi_s2_i116; - input fabric_fpga_rdata_axi_s2_i117; - input fabric_fpga_rdata_axi_s2_i118; - input fabric_fpga_rdata_axi_s2_i119; - input fabric_fpga_rdata_axi_s2_i12; - input fabric_fpga_rdata_axi_s2_i120; - input fabric_fpga_rdata_axi_s2_i121; - input fabric_fpga_rdata_axi_s2_i122; - input fabric_fpga_rdata_axi_s2_i123; - input fabric_fpga_rdata_axi_s2_i124; - input fabric_fpga_rdata_axi_s2_i125; - input fabric_fpga_rdata_axi_s2_i126; - input fabric_fpga_rdata_axi_s2_i127; - input fabric_fpga_rdata_axi_s2_i128; - input fabric_fpga_rdata_axi_s2_i13; - input fabric_fpga_rdata_axi_s2_i14; - input fabric_fpga_rdata_axi_s2_i15; - input fabric_fpga_rdata_axi_s2_i16; - input fabric_fpga_rdata_axi_s2_i17; - input fabric_fpga_rdata_axi_s2_i18; - input fabric_fpga_rdata_axi_s2_i19; - input fabric_fpga_rdata_axi_s2_i2; - input fabric_fpga_rdata_axi_s2_i20; - input fabric_fpga_rdata_axi_s2_i21; - input fabric_fpga_rdata_axi_s2_i22; - input fabric_fpga_rdata_axi_s2_i23; - input fabric_fpga_rdata_axi_s2_i24; - input fabric_fpga_rdata_axi_s2_i25; - input fabric_fpga_rdata_axi_s2_i26; - input fabric_fpga_rdata_axi_s2_i27; - input fabric_fpga_rdata_axi_s2_i28; - input fabric_fpga_rdata_axi_s2_i29; - input fabric_fpga_rdata_axi_s2_i3; - input fabric_fpga_rdata_axi_s2_i30; - input fabric_fpga_rdata_axi_s2_i31; - input fabric_fpga_rdata_axi_s2_i32; - input fabric_fpga_rdata_axi_s2_i33; - input fabric_fpga_rdata_axi_s2_i34; - input fabric_fpga_rdata_axi_s2_i35; - input fabric_fpga_rdata_axi_s2_i36; - input fabric_fpga_rdata_axi_s2_i37; - input fabric_fpga_rdata_axi_s2_i38; - input fabric_fpga_rdata_axi_s2_i39; - input fabric_fpga_rdata_axi_s2_i4; - input fabric_fpga_rdata_axi_s2_i40; - input fabric_fpga_rdata_axi_s2_i41; - input fabric_fpga_rdata_axi_s2_i42; - input fabric_fpga_rdata_axi_s2_i43; - input fabric_fpga_rdata_axi_s2_i44; - input fabric_fpga_rdata_axi_s2_i45; - input fabric_fpga_rdata_axi_s2_i46; - input fabric_fpga_rdata_axi_s2_i47; - input fabric_fpga_rdata_axi_s2_i48; - input fabric_fpga_rdata_axi_s2_i49; - input fabric_fpga_rdata_axi_s2_i5; - input fabric_fpga_rdata_axi_s2_i50; - input fabric_fpga_rdata_axi_s2_i51; - input fabric_fpga_rdata_axi_s2_i52; - input fabric_fpga_rdata_axi_s2_i53; - input fabric_fpga_rdata_axi_s2_i54; - input fabric_fpga_rdata_axi_s2_i55; - input fabric_fpga_rdata_axi_s2_i56; - input fabric_fpga_rdata_axi_s2_i57; - input fabric_fpga_rdata_axi_s2_i58; - input fabric_fpga_rdata_axi_s2_i59; - input fabric_fpga_rdata_axi_s2_i6; - input fabric_fpga_rdata_axi_s2_i60; - input fabric_fpga_rdata_axi_s2_i61; - input fabric_fpga_rdata_axi_s2_i62; - input fabric_fpga_rdata_axi_s2_i63; - input fabric_fpga_rdata_axi_s2_i64; - input fabric_fpga_rdata_axi_s2_i65; - input fabric_fpga_rdata_axi_s2_i66; - input fabric_fpga_rdata_axi_s2_i67; - input fabric_fpga_rdata_axi_s2_i68; - input fabric_fpga_rdata_axi_s2_i69; - input fabric_fpga_rdata_axi_s2_i7; - input fabric_fpga_rdata_axi_s2_i70; - input fabric_fpga_rdata_axi_s2_i71; - input fabric_fpga_rdata_axi_s2_i72; - input fabric_fpga_rdata_axi_s2_i73; - input fabric_fpga_rdata_axi_s2_i74; - input fabric_fpga_rdata_axi_s2_i75; - input fabric_fpga_rdata_axi_s2_i76; - input fabric_fpga_rdata_axi_s2_i77; - input fabric_fpga_rdata_axi_s2_i78; - input fabric_fpga_rdata_axi_s2_i79; - input fabric_fpga_rdata_axi_s2_i8; - input fabric_fpga_rdata_axi_s2_i80; - input fabric_fpga_rdata_axi_s2_i81; - input fabric_fpga_rdata_axi_s2_i82; - input fabric_fpga_rdata_axi_s2_i83; - input fabric_fpga_rdata_axi_s2_i84; - input fabric_fpga_rdata_axi_s2_i85; - input fabric_fpga_rdata_axi_s2_i86; - input fabric_fpga_rdata_axi_s2_i87; - input fabric_fpga_rdata_axi_s2_i88; - input fabric_fpga_rdata_axi_s2_i89; - input fabric_fpga_rdata_axi_s2_i9; - input fabric_fpga_rdata_axi_s2_i90; - input fabric_fpga_rdata_axi_s2_i91; - input fabric_fpga_rdata_axi_s2_i92; - input fabric_fpga_rdata_axi_s2_i93; - input fabric_fpga_rdata_axi_s2_i94; - input fabric_fpga_rdata_axi_s2_i95; - input fabric_fpga_rdata_axi_s2_i96; - input fabric_fpga_rdata_axi_s2_i97; - input fabric_fpga_rdata_axi_s2_i98; - input fabric_fpga_rdata_axi_s2_i99; - output fabric_fpga_rid_axi_m1_o1; - output fabric_fpga_rid_axi_m1_o2; - output fabric_fpga_rid_axi_m1_o3; - output fabric_fpga_rid_axi_m1_o4; - output fabric_fpga_rid_axi_m1_o5; - output fabric_fpga_rid_axi_m2_o1; - output fabric_fpga_rid_axi_m2_o2; - output fabric_fpga_rid_axi_m2_o3; - output fabric_fpga_rid_axi_m2_o4; - output fabric_fpga_rid_axi_m2_o5; - input fabric_fpga_rid_axi_s1_i1; - input fabric_fpga_rid_axi_s1_i10; - input fabric_fpga_rid_axi_s1_i11; - input fabric_fpga_rid_axi_s1_i12; - input fabric_fpga_rid_axi_s1_i2; - input fabric_fpga_rid_axi_s1_i3; - input fabric_fpga_rid_axi_s1_i4; - input fabric_fpga_rid_axi_s1_i5; - input fabric_fpga_rid_axi_s1_i6; - input fabric_fpga_rid_axi_s1_i7; - input fabric_fpga_rid_axi_s1_i8; - input fabric_fpga_rid_axi_s1_i9; - input fabric_fpga_rid_axi_s2_i1; - input fabric_fpga_rid_axi_s2_i10; - input fabric_fpga_rid_axi_s2_i11; - input fabric_fpga_rid_axi_s2_i12; - input fabric_fpga_rid_axi_s2_i2; - input fabric_fpga_rid_axi_s2_i3; - input fabric_fpga_rid_axi_s2_i4; - input fabric_fpga_rid_axi_s2_i5; - input fabric_fpga_rid_axi_s2_i6; - input fabric_fpga_rid_axi_s2_i7; - input fabric_fpga_rid_axi_s2_i8; - input fabric_fpga_rid_axi_s2_i9; - output fabric_fpga_rlast_axi_m1_o; - output fabric_fpga_rlast_axi_m2_o; - input fabric_fpga_rlast_axi_s1_i; - input fabric_fpga_rlast_axi_s2_i; - input fabric_fpga_rready_axi_m1_i; - input fabric_fpga_rready_axi_m2_i; - output fabric_fpga_rready_axi_s1_o; - output fabric_fpga_rready_axi_s2_o; - output fabric_fpga_rresp_axi_m1_o1; - output fabric_fpga_rresp_axi_m1_o2; - output fabric_fpga_rresp_axi_m2_o1; - output fabric_fpga_rresp_axi_m2_o2; - input fabric_fpga_rresp_axi_s1_i1; - input fabric_fpga_rresp_axi_s1_i2; - input fabric_fpga_rresp_axi_s2_i1; - input fabric_fpga_rresp_axi_s2_i2; - output fabric_fpga_rvalid_axi_m1_o; - output fabric_fpga_rvalid_axi_m2_o; - input fabric_fpga_rvalid_axi_s1_i; - input fabric_fpga_rvalid_axi_s2_i; - input fabric_fpga_sysrstn_i; - output fabric_fpga_trigger_in_o1; - output fabric_fpga_trigger_in_o2; - output fabric_fpga_trigger_in_o3; - output fabric_fpga_trigger_in_o4; - output fabric_fpga_trigger_in_o5; - output fabric_fpga_trigger_in_o6; - output fabric_fpga_trigger_in_o7; - output fabric_fpga_trigger_in_o8; - input fabric_fpga_trigger_out_i1; - input fabric_fpga_trigger_out_i2; - input fabric_fpga_trigger_out_i3; - input fabric_fpga_trigger_out_i4; - input fabric_fpga_trigger_out_i5; - input fabric_fpga_trigger_out_i6; - input fabric_fpga_trigger_out_i7; - input fabric_fpga_trigger_out_i8; - input fabric_fpga_wdata_axi_m1_i1; - input fabric_fpga_wdata_axi_m1_i10; - input fabric_fpga_wdata_axi_m1_i100; - input fabric_fpga_wdata_axi_m1_i101; - input fabric_fpga_wdata_axi_m1_i102; - input fabric_fpga_wdata_axi_m1_i103; - input fabric_fpga_wdata_axi_m1_i104; - input fabric_fpga_wdata_axi_m1_i105; - input fabric_fpga_wdata_axi_m1_i106; - input fabric_fpga_wdata_axi_m1_i107; - input fabric_fpga_wdata_axi_m1_i108; - input fabric_fpga_wdata_axi_m1_i109; - input fabric_fpga_wdata_axi_m1_i11; - input fabric_fpga_wdata_axi_m1_i110; - input fabric_fpga_wdata_axi_m1_i111; - input fabric_fpga_wdata_axi_m1_i112; - input fabric_fpga_wdata_axi_m1_i113; - input fabric_fpga_wdata_axi_m1_i114; - input fabric_fpga_wdata_axi_m1_i115; - input fabric_fpga_wdata_axi_m1_i116; - input fabric_fpga_wdata_axi_m1_i117; - input fabric_fpga_wdata_axi_m1_i118; - input fabric_fpga_wdata_axi_m1_i119; - input fabric_fpga_wdata_axi_m1_i12; - input fabric_fpga_wdata_axi_m1_i120; - input fabric_fpga_wdata_axi_m1_i121; - input fabric_fpga_wdata_axi_m1_i122; - input fabric_fpga_wdata_axi_m1_i123; - input fabric_fpga_wdata_axi_m1_i124; - input fabric_fpga_wdata_axi_m1_i125; - input fabric_fpga_wdata_axi_m1_i126; - input fabric_fpga_wdata_axi_m1_i127; - input fabric_fpga_wdata_axi_m1_i128; - input fabric_fpga_wdata_axi_m1_i13; - input fabric_fpga_wdata_axi_m1_i14; - input fabric_fpga_wdata_axi_m1_i15; - input fabric_fpga_wdata_axi_m1_i16; - input fabric_fpga_wdata_axi_m1_i17; - input fabric_fpga_wdata_axi_m1_i18; - input fabric_fpga_wdata_axi_m1_i19; - input fabric_fpga_wdata_axi_m1_i2; - input fabric_fpga_wdata_axi_m1_i20; - input fabric_fpga_wdata_axi_m1_i21; - input fabric_fpga_wdata_axi_m1_i22; - input fabric_fpga_wdata_axi_m1_i23; - input fabric_fpga_wdata_axi_m1_i24; - input fabric_fpga_wdata_axi_m1_i25; - input fabric_fpga_wdata_axi_m1_i26; - input fabric_fpga_wdata_axi_m1_i27; - input fabric_fpga_wdata_axi_m1_i28; - input fabric_fpga_wdata_axi_m1_i29; - input fabric_fpga_wdata_axi_m1_i3; - input fabric_fpga_wdata_axi_m1_i30; - input fabric_fpga_wdata_axi_m1_i31; - input fabric_fpga_wdata_axi_m1_i32; - input fabric_fpga_wdata_axi_m1_i33; - input fabric_fpga_wdata_axi_m1_i34; - input fabric_fpga_wdata_axi_m1_i35; - input fabric_fpga_wdata_axi_m1_i36; - input fabric_fpga_wdata_axi_m1_i37; - input fabric_fpga_wdata_axi_m1_i38; - input fabric_fpga_wdata_axi_m1_i39; - input fabric_fpga_wdata_axi_m1_i4; - input fabric_fpga_wdata_axi_m1_i40; - input fabric_fpga_wdata_axi_m1_i41; - input fabric_fpga_wdata_axi_m1_i42; - input fabric_fpga_wdata_axi_m1_i43; - input fabric_fpga_wdata_axi_m1_i44; - input fabric_fpga_wdata_axi_m1_i45; - input fabric_fpga_wdata_axi_m1_i46; - input fabric_fpga_wdata_axi_m1_i47; - input fabric_fpga_wdata_axi_m1_i48; - input fabric_fpga_wdata_axi_m1_i49; - input fabric_fpga_wdata_axi_m1_i5; - input fabric_fpga_wdata_axi_m1_i50; - input fabric_fpga_wdata_axi_m1_i51; - input fabric_fpga_wdata_axi_m1_i52; - input fabric_fpga_wdata_axi_m1_i53; - input fabric_fpga_wdata_axi_m1_i54; - input fabric_fpga_wdata_axi_m1_i55; - input fabric_fpga_wdata_axi_m1_i56; - input fabric_fpga_wdata_axi_m1_i57; - input fabric_fpga_wdata_axi_m1_i58; - input fabric_fpga_wdata_axi_m1_i59; - input fabric_fpga_wdata_axi_m1_i6; - input fabric_fpga_wdata_axi_m1_i60; - input fabric_fpga_wdata_axi_m1_i61; - input fabric_fpga_wdata_axi_m1_i62; - input fabric_fpga_wdata_axi_m1_i63; - input fabric_fpga_wdata_axi_m1_i64; - input fabric_fpga_wdata_axi_m1_i65; - input fabric_fpga_wdata_axi_m1_i66; - input fabric_fpga_wdata_axi_m1_i67; - input fabric_fpga_wdata_axi_m1_i68; - input fabric_fpga_wdata_axi_m1_i69; - input fabric_fpga_wdata_axi_m1_i7; - input fabric_fpga_wdata_axi_m1_i70; - input fabric_fpga_wdata_axi_m1_i71; - input fabric_fpga_wdata_axi_m1_i72; - input fabric_fpga_wdata_axi_m1_i73; - input fabric_fpga_wdata_axi_m1_i74; - input fabric_fpga_wdata_axi_m1_i75; - input fabric_fpga_wdata_axi_m1_i76; - input fabric_fpga_wdata_axi_m1_i77; - input fabric_fpga_wdata_axi_m1_i78; - input fabric_fpga_wdata_axi_m1_i79; - input fabric_fpga_wdata_axi_m1_i8; - input fabric_fpga_wdata_axi_m1_i80; - input fabric_fpga_wdata_axi_m1_i81; - input fabric_fpga_wdata_axi_m1_i82; - input fabric_fpga_wdata_axi_m1_i83; - input fabric_fpga_wdata_axi_m1_i84; - input fabric_fpga_wdata_axi_m1_i85; - input fabric_fpga_wdata_axi_m1_i86; - input fabric_fpga_wdata_axi_m1_i87; - input fabric_fpga_wdata_axi_m1_i88; - input fabric_fpga_wdata_axi_m1_i89; - input fabric_fpga_wdata_axi_m1_i9; - input fabric_fpga_wdata_axi_m1_i90; - input fabric_fpga_wdata_axi_m1_i91; - input fabric_fpga_wdata_axi_m1_i92; - input fabric_fpga_wdata_axi_m1_i93; - input fabric_fpga_wdata_axi_m1_i94; - input fabric_fpga_wdata_axi_m1_i95; - input fabric_fpga_wdata_axi_m1_i96; - input fabric_fpga_wdata_axi_m1_i97; - input fabric_fpga_wdata_axi_m1_i98; - input fabric_fpga_wdata_axi_m1_i99; - input fabric_fpga_wdata_axi_m2_i1; - input fabric_fpga_wdata_axi_m2_i10; - input fabric_fpga_wdata_axi_m2_i100; - input fabric_fpga_wdata_axi_m2_i101; - input fabric_fpga_wdata_axi_m2_i102; - input fabric_fpga_wdata_axi_m2_i103; - input fabric_fpga_wdata_axi_m2_i104; - input fabric_fpga_wdata_axi_m2_i105; - input fabric_fpga_wdata_axi_m2_i106; - input fabric_fpga_wdata_axi_m2_i107; - input fabric_fpga_wdata_axi_m2_i108; - input fabric_fpga_wdata_axi_m2_i109; - input fabric_fpga_wdata_axi_m2_i11; - input fabric_fpga_wdata_axi_m2_i110; - input fabric_fpga_wdata_axi_m2_i111; - input fabric_fpga_wdata_axi_m2_i112; - input fabric_fpga_wdata_axi_m2_i113; - input fabric_fpga_wdata_axi_m2_i114; - input fabric_fpga_wdata_axi_m2_i115; - input fabric_fpga_wdata_axi_m2_i116; - input fabric_fpga_wdata_axi_m2_i117; - input fabric_fpga_wdata_axi_m2_i118; - input fabric_fpga_wdata_axi_m2_i119; - input fabric_fpga_wdata_axi_m2_i12; - input fabric_fpga_wdata_axi_m2_i120; - input fabric_fpga_wdata_axi_m2_i121; - input fabric_fpga_wdata_axi_m2_i122; - input fabric_fpga_wdata_axi_m2_i123; - input fabric_fpga_wdata_axi_m2_i124; - input fabric_fpga_wdata_axi_m2_i125; - input fabric_fpga_wdata_axi_m2_i126; - input fabric_fpga_wdata_axi_m2_i127; - input fabric_fpga_wdata_axi_m2_i128; - input fabric_fpga_wdata_axi_m2_i13; - input fabric_fpga_wdata_axi_m2_i14; - input fabric_fpga_wdata_axi_m2_i15; - input fabric_fpga_wdata_axi_m2_i16; - input fabric_fpga_wdata_axi_m2_i17; - input fabric_fpga_wdata_axi_m2_i18; - input fabric_fpga_wdata_axi_m2_i19; - input fabric_fpga_wdata_axi_m2_i2; - input fabric_fpga_wdata_axi_m2_i20; - input fabric_fpga_wdata_axi_m2_i21; - input fabric_fpga_wdata_axi_m2_i22; - input fabric_fpga_wdata_axi_m2_i23; - input fabric_fpga_wdata_axi_m2_i24; - input fabric_fpga_wdata_axi_m2_i25; - input fabric_fpga_wdata_axi_m2_i26; - input fabric_fpga_wdata_axi_m2_i27; - input fabric_fpga_wdata_axi_m2_i28; - input fabric_fpga_wdata_axi_m2_i29; - input fabric_fpga_wdata_axi_m2_i3; - input fabric_fpga_wdata_axi_m2_i30; - input fabric_fpga_wdata_axi_m2_i31; - input fabric_fpga_wdata_axi_m2_i32; - input fabric_fpga_wdata_axi_m2_i33; - input fabric_fpga_wdata_axi_m2_i34; - input fabric_fpga_wdata_axi_m2_i35; - input fabric_fpga_wdata_axi_m2_i36; - input fabric_fpga_wdata_axi_m2_i37; - input fabric_fpga_wdata_axi_m2_i38; - input fabric_fpga_wdata_axi_m2_i39; - input fabric_fpga_wdata_axi_m2_i4; - input fabric_fpga_wdata_axi_m2_i40; - input fabric_fpga_wdata_axi_m2_i41; - input fabric_fpga_wdata_axi_m2_i42; - input fabric_fpga_wdata_axi_m2_i43; - input fabric_fpga_wdata_axi_m2_i44; - input fabric_fpga_wdata_axi_m2_i45; - input fabric_fpga_wdata_axi_m2_i46; - input fabric_fpga_wdata_axi_m2_i47; - input fabric_fpga_wdata_axi_m2_i48; - input fabric_fpga_wdata_axi_m2_i49; - input fabric_fpga_wdata_axi_m2_i5; - input fabric_fpga_wdata_axi_m2_i50; - input fabric_fpga_wdata_axi_m2_i51; - input fabric_fpga_wdata_axi_m2_i52; - input fabric_fpga_wdata_axi_m2_i53; - input fabric_fpga_wdata_axi_m2_i54; - input fabric_fpga_wdata_axi_m2_i55; - input fabric_fpga_wdata_axi_m2_i56; - input fabric_fpga_wdata_axi_m2_i57; - input fabric_fpga_wdata_axi_m2_i58; - input fabric_fpga_wdata_axi_m2_i59; - input fabric_fpga_wdata_axi_m2_i6; - input fabric_fpga_wdata_axi_m2_i60; - input fabric_fpga_wdata_axi_m2_i61; - input fabric_fpga_wdata_axi_m2_i62; - input fabric_fpga_wdata_axi_m2_i63; - input fabric_fpga_wdata_axi_m2_i64; - input fabric_fpga_wdata_axi_m2_i65; - input fabric_fpga_wdata_axi_m2_i66; - input fabric_fpga_wdata_axi_m2_i67; - input fabric_fpga_wdata_axi_m2_i68; - input fabric_fpga_wdata_axi_m2_i69; - input fabric_fpga_wdata_axi_m2_i7; - input fabric_fpga_wdata_axi_m2_i70; - input fabric_fpga_wdata_axi_m2_i71; - input fabric_fpga_wdata_axi_m2_i72; - input fabric_fpga_wdata_axi_m2_i73; - input fabric_fpga_wdata_axi_m2_i74; - input fabric_fpga_wdata_axi_m2_i75; - input fabric_fpga_wdata_axi_m2_i76; - input fabric_fpga_wdata_axi_m2_i77; - input fabric_fpga_wdata_axi_m2_i78; - input fabric_fpga_wdata_axi_m2_i79; - input fabric_fpga_wdata_axi_m2_i8; - input fabric_fpga_wdata_axi_m2_i80; - input fabric_fpga_wdata_axi_m2_i81; - input fabric_fpga_wdata_axi_m2_i82; - input fabric_fpga_wdata_axi_m2_i83; - input fabric_fpga_wdata_axi_m2_i84; - input fabric_fpga_wdata_axi_m2_i85; - input fabric_fpga_wdata_axi_m2_i86; - input fabric_fpga_wdata_axi_m2_i87; - input fabric_fpga_wdata_axi_m2_i88; - input fabric_fpga_wdata_axi_m2_i89; - input fabric_fpga_wdata_axi_m2_i9; - input fabric_fpga_wdata_axi_m2_i90; - input fabric_fpga_wdata_axi_m2_i91; - input fabric_fpga_wdata_axi_m2_i92; - input fabric_fpga_wdata_axi_m2_i93; - input fabric_fpga_wdata_axi_m2_i94; - input fabric_fpga_wdata_axi_m2_i95; - input fabric_fpga_wdata_axi_m2_i96; - input fabric_fpga_wdata_axi_m2_i97; - input fabric_fpga_wdata_axi_m2_i98; - input fabric_fpga_wdata_axi_m2_i99; - output fabric_fpga_wdata_axi_s1_o1; - output fabric_fpga_wdata_axi_s1_o10; - output fabric_fpga_wdata_axi_s1_o100; - output fabric_fpga_wdata_axi_s1_o101; - output fabric_fpga_wdata_axi_s1_o102; - output fabric_fpga_wdata_axi_s1_o103; - output fabric_fpga_wdata_axi_s1_o104; - output fabric_fpga_wdata_axi_s1_o105; - output fabric_fpga_wdata_axi_s1_o106; - output fabric_fpga_wdata_axi_s1_o107; - output fabric_fpga_wdata_axi_s1_o108; - output fabric_fpga_wdata_axi_s1_o109; - output fabric_fpga_wdata_axi_s1_o11; - output fabric_fpga_wdata_axi_s1_o110; - output fabric_fpga_wdata_axi_s1_o111; - output fabric_fpga_wdata_axi_s1_o112; - output fabric_fpga_wdata_axi_s1_o113; - output fabric_fpga_wdata_axi_s1_o114; - output fabric_fpga_wdata_axi_s1_o115; - output fabric_fpga_wdata_axi_s1_o116; - output fabric_fpga_wdata_axi_s1_o117; - output fabric_fpga_wdata_axi_s1_o118; - output fabric_fpga_wdata_axi_s1_o119; - output fabric_fpga_wdata_axi_s1_o12; - output fabric_fpga_wdata_axi_s1_o120; - output fabric_fpga_wdata_axi_s1_o121; - output fabric_fpga_wdata_axi_s1_o122; - output fabric_fpga_wdata_axi_s1_o123; - output fabric_fpga_wdata_axi_s1_o124; - output fabric_fpga_wdata_axi_s1_o125; - output fabric_fpga_wdata_axi_s1_o126; - output fabric_fpga_wdata_axi_s1_o127; - output fabric_fpga_wdata_axi_s1_o128; - output fabric_fpga_wdata_axi_s1_o13; - output fabric_fpga_wdata_axi_s1_o14; - output fabric_fpga_wdata_axi_s1_o15; - output fabric_fpga_wdata_axi_s1_o16; - output fabric_fpga_wdata_axi_s1_o17; - output fabric_fpga_wdata_axi_s1_o18; - output fabric_fpga_wdata_axi_s1_o19; - output fabric_fpga_wdata_axi_s1_o2; - output fabric_fpga_wdata_axi_s1_o20; - output fabric_fpga_wdata_axi_s1_o21; - output fabric_fpga_wdata_axi_s1_o22; - output fabric_fpga_wdata_axi_s1_o23; - output fabric_fpga_wdata_axi_s1_o24; - output fabric_fpga_wdata_axi_s1_o25; - output fabric_fpga_wdata_axi_s1_o26; - output fabric_fpga_wdata_axi_s1_o27; - output fabric_fpga_wdata_axi_s1_o28; - output fabric_fpga_wdata_axi_s1_o29; - output fabric_fpga_wdata_axi_s1_o3; - output fabric_fpga_wdata_axi_s1_o30; - output fabric_fpga_wdata_axi_s1_o31; - output fabric_fpga_wdata_axi_s1_o32; - output fabric_fpga_wdata_axi_s1_o33; - output fabric_fpga_wdata_axi_s1_o34; - output fabric_fpga_wdata_axi_s1_o35; - output fabric_fpga_wdata_axi_s1_o36; - output fabric_fpga_wdata_axi_s1_o37; - output fabric_fpga_wdata_axi_s1_o38; - output fabric_fpga_wdata_axi_s1_o39; - output fabric_fpga_wdata_axi_s1_o4; - output fabric_fpga_wdata_axi_s1_o40; - output fabric_fpga_wdata_axi_s1_o41; - output fabric_fpga_wdata_axi_s1_o42; - output fabric_fpga_wdata_axi_s1_o43; - output fabric_fpga_wdata_axi_s1_o44; - output fabric_fpga_wdata_axi_s1_o45; - output fabric_fpga_wdata_axi_s1_o46; - output fabric_fpga_wdata_axi_s1_o47; - output fabric_fpga_wdata_axi_s1_o48; - output fabric_fpga_wdata_axi_s1_o49; - output fabric_fpga_wdata_axi_s1_o5; - output fabric_fpga_wdata_axi_s1_o50; - output fabric_fpga_wdata_axi_s1_o51; - output fabric_fpga_wdata_axi_s1_o52; - output fabric_fpga_wdata_axi_s1_o53; - output fabric_fpga_wdata_axi_s1_o54; - output fabric_fpga_wdata_axi_s1_o55; - output fabric_fpga_wdata_axi_s1_o56; - output fabric_fpga_wdata_axi_s1_o57; - output fabric_fpga_wdata_axi_s1_o58; - output fabric_fpga_wdata_axi_s1_o59; - output fabric_fpga_wdata_axi_s1_o6; - output fabric_fpga_wdata_axi_s1_o60; - output fabric_fpga_wdata_axi_s1_o61; - output fabric_fpga_wdata_axi_s1_o62; - output fabric_fpga_wdata_axi_s1_o63; - output fabric_fpga_wdata_axi_s1_o64; - output fabric_fpga_wdata_axi_s1_o65; - output fabric_fpga_wdata_axi_s1_o66; - output fabric_fpga_wdata_axi_s1_o67; - output fabric_fpga_wdata_axi_s1_o68; - output fabric_fpga_wdata_axi_s1_o69; - output fabric_fpga_wdata_axi_s1_o7; - output fabric_fpga_wdata_axi_s1_o70; - output fabric_fpga_wdata_axi_s1_o71; - output fabric_fpga_wdata_axi_s1_o72; - output fabric_fpga_wdata_axi_s1_o73; - output fabric_fpga_wdata_axi_s1_o74; - output fabric_fpga_wdata_axi_s1_o75; - output fabric_fpga_wdata_axi_s1_o76; - output fabric_fpga_wdata_axi_s1_o77; - output fabric_fpga_wdata_axi_s1_o78; - output fabric_fpga_wdata_axi_s1_o79; - output fabric_fpga_wdata_axi_s1_o8; - output fabric_fpga_wdata_axi_s1_o80; - output fabric_fpga_wdata_axi_s1_o81; - output fabric_fpga_wdata_axi_s1_o82; - output fabric_fpga_wdata_axi_s1_o83; - output fabric_fpga_wdata_axi_s1_o84; - output fabric_fpga_wdata_axi_s1_o85; - output fabric_fpga_wdata_axi_s1_o86; - output fabric_fpga_wdata_axi_s1_o87; - output fabric_fpga_wdata_axi_s1_o88; - output fabric_fpga_wdata_axi_s1_o89; - output fabric_fpga_wdata_axi_s1_o9; - output fabric_fpga_wdata_axi_s1_o90; - output fabric_fpga_wdata_axi_s1_o91; - output fabric_fpga_wdata_axi_s1_o92; - output fabric_fpga_wdata_axi_s1_o93; - output fabric_fpga_wdata_axi_s1_o94; - output fabric_fpga_wdata_axi_s1_o95; - output fabric_fpga_wdata_axi_s1_o96; - output fabric_fpga_wdata_axi_s1_o97; - output fabric_fpga_wdata_axi_s1_o98; - output fabric_fpga_wdata_axi_s1_o99; - output fabric_fpga_wdata_axi_s2_o1; - output fabric_fpga_wdata_axi_s2_o10; - output fabric_fpga_wdata_axi_s2_o100; - output fabric_fpga_wdata_axi_s2_o101; - output fabric_fpga_wdata_axi_s2_o102; - output fabric_fpga_wdata_axi_s2_o103; - output fabric_fpga_wdata_axi_s2_o104; - output fabric_fpga_wdata_axi_s2_o105; - output fabric_fpga_wdata_axi_s2_o106; - output fabric_fpga_wdata_axi_s2_o107; - output fabric_fpga_wdata_axi_s2_o108; - output fabric_fpga_wdata_axi_s2_o109; - output fabric_fpga_wdata_axi_s2_o11; - output fabric_fpga_wdata_axi_s2_o110; - output fabric_fpga_wdata_axi_s2_o111; - output fabric_fpga_wdata_axi_s2_o112; - output fabric_fpga_wdata_axi_s2_o113; - output fabric_fpga_wdata_axi_s2_o114; - output fabric_fpga_wdata_axi_s2_o115; - output fabric_fpga_wdata_axi_s2_o116; - output fabric_fpga_wdata_axi_s2_o117; - output fabric_fpga_wdata_axi_s2_o118; - output fabric_fpga_wdata_axi_s2_o119; - output fabric_fpga_wdata_axi_s2_o12; - output fabric_fpga_wdata_axi_s2_o120; - output fabric_fpga_wdata_axi_s2_o121; - output fabric_fpga_wdata_axi_s2_o122; - output fabric_fpga_wdata_axi_s2_o123; - output fabric_fpga_wdata_axi_s2_o124; - output fabric_fpga_wdata_axi_s2_o125; - output fabric_fpga_wdata_axi_s2_o126; - output fabric_fpga_wdata_axi_s2_o127; - output fabric_fpga_wdata_axi_s2_o128; - output fabric_fpga_wdata_axi_s2_o13; - output fabric_fpga_wdata_axi_s2_o14; - output fabric_fpga_wdata_axi_s2_o15; - output fabric_fpga_wdata_axi_s2_o16; - output fabric_fpga_wdata_axi_s2_o17; - output fabric_fpga_wdata_axi_s2_o18; - output fabric_fpga_wdata_axi_s2_o19; - output fabric_fpga_wdata_axi_s2_o2; - output fabric_fpga_wdata_axi_s2_o20; - output fabric_fpga_wdata_axi_s2_o21; - output fabric_fpga_wdata_axi_s2_o22; - output fabric_fpga_wdata_axi_s2_o23; - output fabric_fpga_wdata_axi_s2_o24; - output fabric_fpga_wdata_axi_s2_o25; - output fabric_fpga_wdata_axi_s2_o26; - output fabric_fpga_wdata_axi_s2_o27; - output fabric_fpga_wdata_axi_s2_o28; - output fabric_fpga_wdata_axi_s2_o29; - output fabric_fpga_wdata_axi_s2_o3; - output fabric_fpga_wdata_axi_s2_o30; - output fabric_fpga_wdata_axi_s2_o31; - output fabric_fpga_wdata_axi_s2_o32; - output fabric_fpga_wdata_axi_s2_o33; - output fabric_fpga_wdata_axi_s2_o34; - output fabric_fpga_wdata_axi_s2_o35; - output fabric_fpga_wdata_axi_s2_o36; - output fabric_fpga_wdata_axi_s2_o37; - output fabric_fpga_wdata_axi_s2_o38; - output fabric_fpga_wdata_axi_s2_o39; - output fabric_fpga_wdata_axi_s2_o4; - output fabric_fpga_wdata_axi_s2_o40; - output fabric_fpga_wdata_axi_s2_o41; - output fabric_fpga_wdata_axi_s2_o42; - output fabric_fpga_wdata_axi_s2_o43; - output fabric_fpga_wdata_axi_s2_o44; - output fabric_fpga_wdata_axi_s2_o45; - output fabric_fpga_wdata_axi_s2_o46; - output fabric_fpga_wdata_axi_s2_o47; - output fabric_fpga_wdata_axi_s2_o48; - output fabric_fpga_wdata_axi_s2_o49; - output fabric_fpga_wdata_axi_s2_o5; - output fabric_fpga_wdata_axi_s2_o50; - output fabric_fpga_wdata_axi_s2_o51; - output fabric_fpga_wdata_axi_s2_o52; - output fabric_fpga_wdata_axi_s2_o53; - output fabric_fpga_wdata_axi_s2_o54; - output fabric_fpga_wdata_axi_s2_o55; - output fabric_fpga_wdata_axi_s2_o56; - output fabric_fpga_wdata_axi_s2_o57; - output fabric_fpga_wdata_axi_s2_o58; - output fabric_fpga_wdata_axi_s2_o59; - output fabric_fpga_wdata_axi_s2_o6; - output fabric_fpga_wdata_axi_s2_o60; - output fabric_fpga_wdata_axi_s2_o61; - output fabric_fpga_wdata_axi_s2_o62; - output fabric_fpga_wdata_axi_s2_o63; - output fabric_fpga_wdata_axi_s2_o64; - output fabric_fpga_wdata_axi_s2_o65; - output fabric_fpga_wdata_axi_s2_o66; - output fabric_fpga_wdata_axi_s2_o67; - output fabric_fpga_wdata_axi_s2_o68; - output fabric_fpga_wdata_axi_s2_o69; - output fabric_fpga_wdata_axi_s2_o7; - output fabric_fpga_wdata_axi_s2_o70; - output fabric_fpga_wdata_axi_s2_o71; - output fabric_fpga_wdata_axi_s2_o72; - output fabric_fpga_wdata_axi_s2_o73; - output fabric_fpga_wdata_axi_s2_o74; - output fabric_fpga_wdata_axi_s2_o75; - output fabric_fpga_wdata_axi_s2_o76; - output fabric_fpga_wdata_axi_s2_o77; - output fabric_fpga_wdata_axi_s2_o78; - output fabric_fpga_wdata_axi_s2_o79; - output fabric_fpga_wdata_axi_s2_o8; - output fabric_fpga_wdata_axi_s2_o80; - output fabric_fpga_wdata_axi_s2_o81; - output fabric_fpga_wdata_axi_s2_o82; - output fabric_fpga_wdata_axi_s2_o83; - output fabric_fpga_wdata_axi_s2_o84; - output fabric_fpga_wdata_axi_s2_o85; - output fabric_fpga_wdata_axi_s2_o86; - output fabric_fpga_wdata_axi_s2_o87; - output fabric_fpga_wdata_axi_s2_o88; - output fabric_fpga_wdata_axi_s2_o89; - output fabric_fpga_wdata_axi_s2_o9; - output fabric_fpga_wdata_axi_s2_o90; - output fabric_fpga_wdata_axi_s2_o91; - output fabric_fpga_wdata_axi_s2_o92; - output fabric_fpga_wdata_axi_s2_o93; - output fabric_fpga_wdata_axi_s2_o94; - output fabric_fpga_wdata_axi_s2_o95; - output fabric_fpga_wdata_axi_s2_o96; - output fabric_fpga_wdata_axi_s2_o97; - output fabric_fpga_wdata_axi_s2_o98; - output fabric_fpga_wdata_axi_s2_o99; - input fabric_fpga_wlast_axi_m1_i; - input fabric_fpga_wlast_axi_m2_i; - output fabric_fpga_wlast_axi_s1_o; - output fabric_fpga_wlast_axi_s2_o; - output fabric_fpga_wready_axi_m1_o; - output fabric_fpga_wready_axi_m2_o; - input fabric_fpga_wready_axi_s1_i; - input fabric_fpga_wready_axi_s2_i; - input fabric_fpga_wstrb_axi_m1_i1; - input fabric_fpga_wstrb_axi_m1_i10; - input fabric_fpga_wstrb_axi_m1_i11; - input fabric_fpga_wstrb_axi_m1_i12; - input fabric_fpga_wstrb_axi_m1_i13; - input fabric_fpga_wstrb_axi_m1_i14; - input fabric_fpga_wstrb_axi_m1_i15; - input fabric_fpga_wstrb_axi_m1_i16; - input fabric_fpga_wstrb_axi_m1_i2; - input fabric_fpga_wstrb_axi_m1_i3; - input fabric_fpga_wstrb_axi_m1_i4; - input fabric_fpga_wstrb_axi_m1_i5; - input fabric_fpga_wstrb_axi_m1_i6; - input fabric_fpga_wstrb_axi_m1_i7; - input fabric_fpga_wstrb_axi_m1_i8; - input fabric_fpga_wstrb_axi_m1_i9; - input fabric_fpga_wstrb_axi_m2_i1; - input fabric_fpga_wstrb_axi_m2_i10; - input fabric_fpga_wstrb_axi_m2_i11; - input fabric_fpga_wstrb_axi_m2_i12; - input fabric_fpga_wstrb_axi_m2_i13; - input fabric_fpga_wstrb_axi_m2_i14; - input fabric_fpga_wstrb_axi_m2_i15; - input fabric_fpga_wstrb_axi_m2_i16; - input fabric_fpga_wstrb_axi_m2_i2; - input fabric_fpga_wstrb_axi_m2_i3; - input fabric_fpga_wstrb_axi_m2_i4; - input fabric_fpga_wstrb_axi_m2_i5; - input fabric_fpga_wstrb_axi_m2_i6; - input fabric_fpga_wstrb_axi_m2_i7; - input fabric_fpga_wstrb_axi_m2_i8; - input fabric_fpga_wstrb_axi_m2_i9; - output fabric_fpga_wstrb_axi_s1_o1; - output fabric_fpga_wstrb_axi_s1_o10; - output fabric_fpga_wstrb_axi_s1_o11; - output fabric_fpga_wstrb_axi_s1_o12; - output fabric_fpga_wstrb_axi_s1_o13; - output fabric_fpga_wstrb_axi_s1_o14; - output fabric_fpga_wstrb_axi_s1_o15; - output fabric_fpga_wstrb_axi_s1_o16; - output fabric_fpga_wstrb_axi_s1_o2; - output fabric_fpga_wstrb_axi_s1_o3; - output fabric_fpga_wstrb_axi_s1_o4; - output fabric_fpga_wstrb_axi_s1_o5; - output fabric_fpga_wstrb_axi_s1_o6; - output fabric_fpga_wstrb_axi_s1_o7; - output fabric_fpga_wstrb_axi_s1_o8; - output fabric_fpga_wstrb_axi_s1_o9; - output fabric_fpga_wstrb_axi_s2_o1; - output fabric_fpga_wstrb_axi_s2_o10; - output fabric_fpga_wstrb_axi_s2_o11; - output fabric_fpga_wstrb_axi_s2_o12; - output fabric_fpga_wstrb_axi_s2_o13; - output fabric_fpga_wstrb_axi_s2_o14; - output fabric_fpga_wstrb_axi_s2_o15; - output fabric_fpga_wstrb_axi_s2_o16; - output fabric_fpga_wstrb_axi_s2_o2; - output fabric_fpga_wstrb_axi_s2_o3; - output fabric_fpga_wstrb_axi_s2_o4; - output fabric_fpga_wstrb_axi_s2_o5; - output fabric_fpga_wstrb_axi_s2_o6; - output fabric_fpga_wstrb_axi_s2_o7; - output fabric_fpga_wstrb_axi_s2_o8; - output fabric_fpga_wstrb_axi_s2_o9; - input fabric_fpga_wvalid_axi_m1_i; - input fabric_fpga_wvalid_axi_m2_i; - output fabric_fpga_wvalid_axi_s1_o; - output fabric_fpga_wvalid_axi_s2_o; - output fabric_llpp0_araddr_s_o1; - output fabric_llpp0_araddr_s_o10; - output fabric_llpp0_araddr_s_o11; - output fabric_llpp0_araddr_s_o12; - output fabric_llpp0_araddr_s_o13; - output fabric_llpp0_araddr_s_o14; - output fabric_llpp0_araddr_s_o15; - output fabric_llpp0_araddr_s_o16; - output fabric_llpp0_araddr_s_o17; - output fabric_llpp0_araddr_s_o18; - output fabric_llpp0_araddr_s_o19; - output fabric_llpp0_araddr_s_o2; - output fabric_llpp0_araddr_s_o20; - output fabric_llpp0_araddr_s_o21; - output fabric_llpp0_araddr_s_o22; - output fabric_llpp0_araddr_s_o23; - output fabric_llpp0_araddr_s_o24; - output fabric_llpp0_araddr_s_o25; - output fabric_llpp0_araddr_s_o26; - output fabric_llpp0_araddr_s_o27; - output fabric_llpp0_araddr_s_o28; - output fabric_llpp0_araddr_s_o29; - output fabric_llpp0_araddr_s_o3; - output fabric_llpp0_araddr_s_o30; - output fabric_llpp0_araddr_s_o31; - output fabric_llpp0_araddr_s_o32; - output fabric_llpp0_araddr_s_o4; - output fabric_llpp0_araddr_s_o5; - output fabric_llpp0_araddr_s_o6; - output fabric_llpp0_araddr_s_o7; - output fabric_llpp0_araddr_s_o8; - output fabric_llpp0_araddr_s_o9; - output fabric_llpp0_arburst_s_o1; - output fabric_llpp0_arburst_s_o2; - output fabric_llpp0_arcache_s_o1; - output fabric_llpp0_arcache_s_o2; - output fabric_llpp0_arcache_s_o3; - output fabric_llpp0_arcache_s_o4; - output fabric_llpp0_arid_s_o1; - output fabric_llpp0_arid_s_o10; - output fabric_llpp0_arid_s_o11; - output fabric_llpp0_arid_s_o12; - output fabric_llpp0_arid_s_o2; - output fabric_llpp0_arid_s_o3; - output fabric_llpp0_arid_s_o4; - output fabric_llpp0_arid_s_o5; - output fabric_llpp0_arid_s_o6; - output fabric_llpp0_arid_s_o7; - output fabric_llpp0_arid_s_o8; - output fabric_llpp0_arid_s_o9; - output fabric_llpp0_arlen_s_o1; - output fabric_llpp0_arlen_s_o2; - output fabric_llpp0_arlen_s_o3; - output fabric_llpp0_arlen_s_o4; - output fabric_llpp0_arlen_s_o5; - output fabric_llpp0_arlen_s_o6; - output fabric_llpp0_arlen_s_o7; - output fabric_llpp0_arlen_s_o8; - output fabric_llpp0_arlock_s_o; - output fabric_llpp0_arprot_s_o1; - output fabric_llpp0_arprot_s_o2; - output fabric_llpp0_arprot_s_o3; - output fabric_llpp0_arqos_s_o1; - output fabric_llpp0_arqos_s_o2; - output fabric_llpp0_arqos_s_o3; - output fabric_llpp0_arqos_s_o4; - input fabric_llpp0_arready_s_i; - output fabric_llpp0_arsize_s_o1; - output fabric_llpp0_arsize_s_o2; - output fabric_llpp0_arsize_s_o3; - output fabric_llpp0_arvalid_s_o; - output fabric_llpp0_awaddr_s_o1; - output fabric_llpp0_awaddr_s_o10; - output fabric_llpp0_awaddr_s_o11; - output fabric_llpp0_awaddr_s_o12; - output fabric_llpp0_awaddr_s_o13; - output fabric_llpp0_awaddr_s_o14; - output fabric_llpp0_awaddr_s_o15; - output fabric_llpp0_awaddr_s_o16; - output fabric_llpp0_awaddr_s_o17; - output fabric_llpp0_awaddr_s_o18; - output fabric_llpp0_awaddr_s_o19; - output fabric_llpp0_awaddr_s_o2; - output fabric_llpp0_awaddr_s_o20; - output fabric_llpp0_awaddr_s_o21; - output fabric_llpp0_awaddr_s_o22; - output fabric_llpp0_awaddr_s_o23; - output fabric_llpp0_awaddr_s_o24; - output fabric_llpp0_awaddr_s_o25; - output fabric_llpp0_awaddr_s_o26; - output fabric_llpp0_awaddr_s_o27; - output fabric_llpp0_awaddr_s_o28; - output fabric_llpp0_awaddr_s_o29; - output fabric_llpp0_awaddr_s_o3; - output fabric_llpp0_awaddr_s_o30; - output fabric_llpp0_awaddr_s_o31; - output fabric_llpp0_awaddr_s_o32; - output fabric_llpp0_awaddr_s_o4; - output fabric_llpp0_awaddr_s_o5; - output fabric_llpp0_awaddr_s_o6; - output fabric_llpp0_awaddr_s_o7; - output fabric_llpp0_awaddr_s_o8; - output fabric_llpp0_awaddr_s_o9; - output fabric_llpp0_awburst_s_o1; - output fabric_llpp0_awburst_s_o2; - output fabric_llpp0_awcache_s_o1; - output fabric_llpp0_awcache_s_o2; - output fabric_llpp0_awcache_s_o3; - output fabric_llpp0_awcache_s_o4; - output fabric_llpp0_awid_s_o1; - output fabric_llpp0_awid_s_o10; - output fabric_llpp0_awid_s_o11; - output fabric_llpp0_awid_s_o12; - output fabric_llpp0_awid_s_o2; - output fabric_llpp0_awid_s_o3; - output fabric_llpp0_awid_s_o4; - output fabric_llpp0_awid_s_o5; - output fabric_llpp0_awid_s_o6; - output fabric_llpp0_awid_s_o7; - output fabric_llpp0_awid_s_o8; - output fabric_llpp0_awid_s_o9; - output fabric_llpp0_awlen_s_o1; - output fabric_llpp0_awlen_s_o2; - output fabric_llpp0_awlen_s_o3; - output fabric_llpp0_awlen_s_o4; - output fabric_llpp0_awlen_s_o5; - output fabric_llpp0_awlen_s_o6; - output fabric_llpp0_awlen_s_o7; - output fabric_llpp0_awlen_s_o8; - output fabric_llpp0_awlock_s_o; - output fabric_llpp0_awprot_s_o1; - output fabric_llpp0_awprot_s_o2; - output fabric_llpp0_awprot_s_o3; - output fabric_llpp0_awqos_s_o1; - output fabric_llpp0_awqos_s_o2; - output fabric_llpp0_awqos_s_o3; - output fabric_llpp0_awqos_s_o4; - input fabric_llpp0_awready_s_i; - output fabric_llpp0_awsize_s_o1; - output fabric_llpp0_awsize_s_o2; - output fabric_llpp0_awsize_s_o3; - output fabric_llpp0_awvalid_s_o; - input fabric_llpp0_bid_s_i1; - input fabric_llpp0_bid_s_i10; - input fabric_llpp0_bid_s_i11; - input fabric_llpp0_bid_s_i12; - input fabric_llpp0_bid_s_i2; - input fabric_llpp0_bid_s_i3; - input fabric_llpp0_bid_s_i4; - input fabric_llpp0_bid_s_i5; - input fabric_llpp0_bid_s_i6; - input fabric_llpp0_bid_s_i7; - input fabric_llpp0_bid_s_i8; - input fabric_llpp0_bid_s_i9; - output fabric_llpp0_bready_s_o; - input fabric_llpp0_bresp_s_i1; - input fabric_llpp0_bresp_s_i2; - input fabric_llpp0_bvalid_s_i; - input fabric_llpp0_rdata_s_i1; - input fabric_llpp0_rdata_s_i10; - input fabric_llpp0_rdata_s_i11; - input fabric_llpp0_rdata_s_i12; - input fabric_llpp0_rdata_s_i13; - input fabric_llpp0_rdata_s_i14; - input fabric_llpp0_rdata_s_i15; - input fabric_llpp0_rdata_s_i16; - input fabric_llpp0_rdata_s_i17; - input fabric_llpp0_rdata_s_i18; - input fabric_llpp0_rdata_s_i19; - input fabric_llpp0_rdata_s_i2; - input fabric_llpp0_rdata_s_i20; - input fabric_llpp0_rdata_s_i21; - input fabric_llpp0_rdata_s_i22; - input fabric_llpp0_rdata_s_i23; - input fabric_llpp0_rdata_s_i24; - input fabric_llpp0_rdata_s_i25; - input fabric_llpp0_rdata_s_i26; - input fabric_llpp0_rdata_s_i27; - input fabric_llpp0_rdata_s_i28; - input fabric_llpp0_rdata_s_i29; - input fabric_llpp0_rdata_s_i3; - input fabric_llpp0_rdata_s_i30; - input fabric_llpp0_rdata_s_i31; - input fabric_llpp0_rdata_s_i32; - input fabric_llpp0_rdata_s_i4; - input fabric_llpp0_rdata_s_i5; - input fabric_llpp0_rdata_s_i6; - input fabric_llpp0_rdata_s_i7; - input fabric_llpp0_rdata_s_i8; - input fabric_llpp0_rdata_s_i9; - input fabric_llpp0_rid_s_i1; - input fabric_llpp0_rid_s_i10; - input fabric_llpp0_rid_s_i11; - input fabric_llpp0_rid_s_i12; - input fabric_llpp0_rid_s_i2; - input fabric_llpp0_rid_s_i3; - input fabric_llpp0_rid_s_i4; - input fabric_llpp0_rid_s_i5; - input fabric_llpp0_rid_s_i6; - input fabric_llpp0_rid_s_i7; - input fabric_llpp0_rid_s_i8; - input fabric_llpp0_rid_s_i9; - input fabric_llpp0_rlast_s_i; - output fabric_llpp0_rready_s_o; - input fabric_llpp0_rresp_s_i1; - input fabric_llpp0_rresp_s_i2; - input fabric_llpp0_rvalid_s_i; - output fabric_llpp0_wdata_s_o1; - output fabric_llpp0_wdata_s_o10; - output fabric_llpp0_wdata_s_o11; - output fabric_llpp0_wdata_s_o12; - output fabric_llpp0_wdata_s_o13; - output fabric_llpp0_wdata_s_o14; - output fabric_llpp0_wdata_s_o15; - output fabric_llpp0_wdata_s_o16; - output fabric_llpp0_wdata_s_o17; - output fabric_llpp0_wdata_s_o18; - output fabric_llpp0_wdata_s_o19; - output fabric_llpp0_wdata_s_o2; - output fabric_llpp0_wdata_s_o20; - output fabric_llpp0_wdata_s_o21; - output fabric_llpp0_wdata_s_o22; - output fabric_llpp0_wdata_s_o23; - output fabric_llpp0_wdata_s_o24; - output fabric_llpp0_wdata_s_o25; - output fabric_llpp0_wdata_s_o26; - output fabric_llpp0_wdata_s_o27; - output fabric_llpp0_wdata_s_o28; - output fabric_llpp0_wdata_s_o29; - output fabric_llpp0_wdata_s_o3; - output fabric_llpp0_wdata_s_o30; - output fabric_llpp0_wdata_s_o31; - output fabric_llpp0_wdata_s_o32; - output fabric_llpp0_wdata_s_o4; - output fabric_llpp0_wdata_s_o5; - output fabric_llpp0_wdata_s_o6; - output fabric_llpp0_wdata_s_o7; - output fabric_llpp0_wdata_s_o8; - output fabric_llpp0_wdata_s_o9; - output fabric_llpp0_wlast_s_o; - input fabric_llpp0_wready_s_i; - output fabric_llpp0_wstrb_s_o1; - output fabric_llpp0_wstrb_s_o2; - output fabric_llpp0_wstrb_s_o3; - output fabric_llpp0_wstrb_s_o4; - output fabric_llpp0_wvalid_s_o; - output fabric_llpp1_araddr_s_o1; - output fabric_llpp1_araddr_s_o10; - output fabric_llpp1_araddr_s_o11; - output fabric_llpp1_araddr_s_o12; - output fabric_llpp1_araddr_s_o13; - output fabric_llpp1_araddr_s_o14; - output fabric_llpp1_araddr_s_o15; - output fabric_llpp1_araddr_s_o16; - output fabric_llpp1_araddr_s_o17; - output fabric_llpp1_araddr_s_o18; - output fabric_llpp1_araddr_s_o19; - output fabric_llpp1_araddr_s_o2; - output fabric_llpp1_araddr_s_o20; - output fabric_llpp1_araddr_s_o21; - output fabric_llpp1_araddr_s_o22; - output fabric_llpp1_araddr_s_o23; - output fabric_llpp1_araddr_s_o24; - output fabric_llpp1_araddr_s_o25; - output fabric_llpp1_araddr_s_o26; - output fabric_llpp1_araddr_s_o27; - output fabric_llpp1_araddr_s_o28; - output fabric_llpp1_araddr_s_o29; - output fabric_llpp1_araddr_s_o3; - output fabric_llpp1_araddr_s_o30; - output fabric_llpp1_araddr_s_o31; - output fabric_llpp1_araddr_s_o32; - output fabric_llpp1_araddr_s_o4; - output fabric_llpp1_araddr_s_o5; - output fabric_llpp1_araddr_s_o6; - output fabric_llpp1_araddr_s_o7; - output fabric_llpp1_araddr_s_o8; - output fabric_llpp1_araddr_s_o9; - output fabric_llpp1_arburst_s_o1; - output fabric_llpp1_arburst_s_o2; - output fabric_llpp1_arcache_s_o1; - output fabric_llpp1_arcache_s_o2; - output fabric_llpp1_arcache_s_o3; - output fabric_llpp1_arcache_s_o4; - output fabric_llpp1_arid_s_o1; - output fabric_llpp1_arid_s_o10; - output fabric_llpp1_arid_s_o11; - output fabric_llpp1_arid_s_o12; - output fabric_llpp1_arid_s_o2; - output fabric_llpp1_arid_s_o3; - output fabric_llpp1_arid_s_o4; - output fabric_llpp1_arid_s_o5; - output fabric_llpp1_arid_s_o6; - output fabric_llpp1_arid_s_o7; - output fabric_llpp1_arid_s_o8; - output fabric_llpp1_arid_s_o9; - output fabric_llpp1_arlen_s_o1; - output fabric_llpp1_arlen_s_o2; - output fabric_llpp1_arlen_s_o3; - output fabric_llpp1_arlen_s_o4; - output fabric_llpp1_arlen_s_o5; - output fabric_llpp1_arlen_s_o6; - output fabric_llpp1_arlen_s_o7; - output fabric_llpp1_arlen_s_o8; - output fabric_llpp1_arlock_s_o; - output fabric_llpp1_arprot_s_o1; - output fabric_llpp1_arprot_s_o2; - output fabric_llpp1_arprot_s_o3; - output fabric_llpp1_arqos_s_o1; - output fabric_llpp1_arqos_s_o2; - output fabric_llpp1_arqos_s_o3; - output fabric_llpp1_arqos_s_o4; - input fabric_llpp1_arready_s_i; - output fabric_llpp1_arsize_s_o1; - output fabric_llpp1_arsize_s_o2; - output fabric_llpp1_arsize_s_o3; - output fabric_llpp1_arvalid_s_o; - output fabric_llpp1_awaddr_s_o1; - output fabric_llpp1_awaddr_s_o10; - output fabric_llpp1_awaddr_s_o11; - output fabric_llpp1_awaddr_s_o12; - output fabric_llpp1_awaddr_s_o13; - output fabric_llpp1_awaddr_s_o14; - output fabric_llpp1_awaddr_s_o15; - output fabric_llpp1_awaddr_s_o16; - output fabric_llpp1_awaddr_s_o17; - output fabric_llpp1_awaddr_s_o18; - output fabric_llpp1_awaddr_s_o19; - output fabric_llpp1_awaddr_s_o2; - output fabric_llpp1_awaddr_s_o20; - output fabric_llpp1_awaddr_s_o21; - output fabric_llpp1_awaddr_s_o22; - output fabric_llpp1_awaddr_s_o23; - output fabric_llpp1_awaddr_s_o24; - output fabric_llpp1_awaddr_s_o25; - output fabric_llpp1_awaddr_s_o26; - output fabric_llpp1_awaddr_s_o27; - output fabric_llpp1_awaddr_s_o28; - output fabric_llpp1_awaddr_s_o29; - output fabric_llpp1_awaddr_s_o3; - output fabric_llpp1_awaddr_s_o30; - output fabric_llpp1_awaddr_s_o31; - output fabric_llpp1_awaddr_s_o32; - output fabric_llpp1_awaddr_s_o4; - output fabric_llpp1_awaddr_s_o5; - output fabric_llpp1_awaddr_s_o6; - output fabric_llpp1_awaddr_s_o7; - output fabric_llpp1_awaddr_s_o8; - output fabric_llpp1_awaddr_s_o9; - output fabric_llpp1_awburst_s_o1; - output fabric_llpp1_awburst_s_o2; - output fabric_llpp1_awcache_s_o1; - output fabric_llpp1_awcache_s_o2; - output fabric_llpp1_awcache_s_o3; - output fabric_llpp1_awcache_s_o4; - output fabric_llpp1_awid_s_o1; - output fabric_llpp1_awid_s_o10; - output fabric_llpp1_awid_s_o11; - output fabric_llpp1_awid_s_o12; - output fabric_llpp1_awid_s_o2; - output fabric_llpp1_awid_s_o3; - output fabric_llpp1_awid_s_o4; - output fabric_llpp1_awid_s_o5; - output fabric_llpp1_awid_s_o6; - output fabric_llpp1_awid_s_o7; - output fabric_llpp1_awid_s_o8; - output fabric_llpp1_awid_s_o9; - output fabric_llpp1_awlen_s_o1; - output fabric_llpp1_awlen_s_o2; - output fabric_llpp1_awlen_s_o3; - output fabric_llpp1_awlen_s_o4; - output fabric_llpp1_awlen_s_o5; - output fabric_llpp1_awlen_s_o6; - output fabric_llpp1_awlen_s_o7; - output fabric_llpp1_awlen_s_o8; - output fabric_llpp1_awlock_s_o; - output fabric_llpp1_awprot_s_o1; - output fabric_llpp1_awprot_s_o2; - output fabric_llpp1_awprot_s_o3; - output fabric_llpp1_awqos_s_o1; - output fabric_llpp1_awqos_s_o2; - output fabric_llpp1_awqos_s_o3; - output fabric_llpp1_awqos_s_o4; - input fabric_llpp1_awready_s_i; - output fabric_llpp1_awsize_s_o1; - output fabric_llpp1_awsize_s_o2; - output fabric_llpp1_awsize_s_o3; - output fabric_llpp1_awvalid_s_o; - input fabric_llpp1_bid_s_i1; - input fabric_llpp1_bid_s_i10; - input fabric_llpp1_bid_s_i11; - input fabric_llpp1_bid_s_i12; - input fabric_llpp1_bid_s_i2; - input fabric_llpp1_bid_s_i3; - input fabric_llpp1_bid_s_i4; - input fabric_llpp1_bid_s_i5; - input fabric_llpp1_bid_s_i6; - input fabric_llpp1_bid_s_i7; - input fabric_llpp1_bid_s_i8; - input fabric_llpp1_bid_s_i9; - output fabric_llpp1_bready_s_o; - input fabric_llpp1_bresp_s_i1; - input fabric_llpp1_bresp_s_i2; - input fabric_llpp1_bvalid_s_i; - input fabric_llpp1_rdata_s_i1; - input fabric_llpp1_rdata_s_i10; - input fabric_llpp1_rdata_s_i11; - input fabric_llpp1_rdata_s_i12; - input fabric_llpp1_rdata_s_i13; - input fabric_llpp1_rdata_s_i14; - input fabric_llpp1_rdata_s_i15; - input fabric_llpp1_rdata_s_i16; - input fabric_llpp1_rdata_s_i17; - input fabric_llpp1_rdata_s_i18; - input fabric_llpp1_rdata_s_i19; - input fabric_llpp1_rdata_s_i2; - input fabric_llpp1_rdata_s_i20; - input fabric_llpp1_rdata_s_i21; - input fabric_llpp1_rdata_s_i22; - input fabric_llpp1_rdata_s_i23; - input fabric_llpp1_rdata_s_i24; - input fabric_llpp1_rdata_s_i25; - input fabric_llpp1_rdata_s_i26; - input fabric_llpp1_rdata_s_i27; - input fabric_llpp1_rdata_s_i28; - input fabric_llpp1_rdata_s_i29; - input fabric_llpp1_rdata_s_i3; - input fabric_llpp1_rdata_s_i30; - input fabric_llpp1_rdata_s_i31; - input fabric_llpp1_rdata_s_i32; - input fabric_llpp1_rdata_s_i4; - input fabric_llpp1_rdata_s_i5; - input fabric_llpp1_rdata_s_i6; - input fabric_llpp1_rdata_s_i7; - input fabric_llpp1_rdata_s_i8; - input fabric_llpp1_rdata_s_i9; - input fabric_llpp1_rid_s_i1; - input fabric_llpp1_rid_s_i10; - input fabric_llpp1_rid_s_i11; - input fabric_llpp1_rid_s_i12; - input fabric_llpp1_rid_s_i2; - input fabric_llpp1_rid_s_i3; - input fabric_llpp1_rid_s_i4; - input fabric_llpp1_rid_s_i5; - input fabric_llpp1_rid_s_i6; - input fabric_llpp1_rid_s_i7; - input fabric_llpp1_rid_s_i8; - input fabric_llpp1_rid_s_i9; - input fabric_llpp1_rlast_s_i; - output fabric_llpp1_rready_s_o; - input fabric_llpp1_rresp_s_i1; - input fabric_llpp1_rresp_s_i2; - input fabric_llpp1_rvalid_s_i; - output fabric_llpp1_wdata_s_o1; - output fabric_llpp1_wdata_s_o10; - output fabric_llpp1_wdata_s_o11; - output fabric_llpp1_wdata_s_o12; - output fabric_llpp1_wdata_s_o13; - output fabric_llpp1_wdata_s_o14; - output fabric_llpp1_wdata_s_o15; - output fabric_llpp1_wdata_s_o16; - output fabric_llpp1_wdata_s_o17; - output fabric_llpp1_wdata_s_o18; - output fabric_llpp1_wdata_s_o19; - output fabric_llpp1_wdata_s_o2; - output fabric_llpp1_wdata_s_o20; - output fabric_llpp1_wdata_s_o21; - output fabric_llpp1_wdata_s_o22; - output fabric_llpp1_wdata_s_o23; - output fabric_llpp1_wdata_s_o24; - output fabric_llpp1_wdata_s_o25; - output fabric_llpp1_wdata_s_o26; - output fabric_llpp1_wdata_s_o27; - output fabric_llpp1_wdata_s_o28; - output fabric_llpp1_wdata_s_o29; - output fabric_llpp1_wdata_s_o3; - output fabric_llpp1_wdata_s_o30; - output fabric_llpp1_wdata_s_o31; - output fabric_llpp1_wdata_s_o32; - output fabric_llpp1_wdata_s_o4; - output fabric_llpp1_wdata_s_o5; - output fabric_llpp1_wdata_s_o6; - output fabric_llpp1_wdata_s_o7; - output fabric_llpp1_wdata_s_o8; - output fabric_llpp1_wdata_s_o9; - output fabric_llpp1_wlast_s_o; - input fabric_llpp1_wready_s_i; - output fabric_llpp1_wstrb_s_o1; - output fabric_llpp1_wstrb_s_o2; - output fabric_llpp1_wstrb_s_o3; - output fabric_llpp1_wstrb_s_o4; - output fabric_llpp1_wvalid_s_o; - output fabric_llpp2_araddr_s_o1; - output fabric_llpp2_araddr_s_o10; - output fabric_llpp2_araddr_s_o11; - output fabric_llpp2_araddr_s_o12; - output fabric_llpp2_araddr_s_o13; - output fabric_llpp2_araddr_s_o14; - output fabric_llpp2_araddr_s_o15; - output fabric_llpp2_araddr_s_o16; - output fabric_llpp2_araddr_s_o17; - output fabric_llpp2_araddr_s_o18; - output fabric_llpp2_araddr_s_o19; - output fabric_llpp2_araddr_s_o2; - output fabric_llpp2_araddr_s_o20; - output fabric_llpp2_araddr_s_o21; - output fabric_llpp2_araddr_s_o22; - output fabric_llpp2_araddr_s_o23; - output fabric_llpp2_araddr_s_o24; - output fabric_llpp2_araddr_s_o25; - output fabric_llpp2_araddr_s_o26; - output fabric_llpp2_araddr_s_o27; - output fabric_llpp2_araddr_s_o28; - output fabric_llpp2_araddr_s_o29; - output fabric_llpp2_araddr_s_o3; - output fabric_llpp2_araddr_s_o30; - output fabric_llpp2_araddr_s_o31; - output fabric_llpp2_araddr_s_o32; - output fabric_llpp2_araddr_s_o4; - output fabric_llpp2_araddr_s_o5; - output fabric_llpp2_araddr_s_o6; - output fabric_llpp2_araddr_s_o7; - output fabric_llpp2_araddr_s_o8; - output fabric_llpp2_araddr_s_o9; - output fabric_llpp2_arburst_s_o1; - output fabric_llpp2_arburst_s_o2; - output fabric_llpp2_arcache_s_o1; - output fabric_llpp2_arcache_s_o2; - output fabric_llpp2_arcache_s_o3; - output fabric_llpp2_arcache_s_o4; - output fabric_llpp2_arid_s_o1; - output fabric_llpp2_arid_s_o10; - output fabric_llpp2_arid_s_o11; - output fabric_llpp2_arid_s_o12; - output fabric_llpp2_arid_s_o2; - output fabric_llpp2_arid_s_o3; - output fabric_llpp2_arid_s_o4; - output fabric_llpp2_arid_s_o5; - output fabric_llpp2_arid_s_o6; - output fabric_llpp2_arid_s_o7; - output fabric_llpp2_arid_s_o8; - output fabric_llpp2_arid_s_o9; - output fabric_llpp2_arlen_s_o1; - output fabric_llpp2_arlen_s_o2; - output fabric_llpp2_arlen_s_o3; - output fabric_llpp2_arlen_s_o4; - output fabric_llpp2_arlen_s_o5; - output fabric_llpp2_arlen_s_o6; - output fabric_llpp2_arlen_s_o7; - output fabric_llpp2_arlen_s_o8; - output fabric_llpp2_arlock_s_o; - output fabric_llpp2_arprot_s_o1; - output fabric_llpp2_arprot_s_o2; - output fabric_llpp2_arprot_s_o3; - output fabric_llpp2_arqos_s_o1; - output fabric_llpp2_arqos_s_o2; - output fabric_llpp2_arqos_s_o3; - output fabric_llpp2_arqos_s_o4; - input fabric_llpp2_arready_s_i; - output fabric_llpp2_arsize_s_o1; - output fabric_llpp2_arsize_s_o2; - output fabric_llpp2_arsize_s_o3; - output fabric_llpp2_arvalid_s_o; - output fabric_llpp2_awaddr_s_o1; - output fabric_llpp2_awaddr_s_o10; - output fabric_llpp2_awaddr_s_o11; - output fabric_llpp2_awaddr_s_o12; - output fabric_llpp2_awaddr_s_o13; - output fabric_llpp2_awaddr_s_o14; - output fabric_llpp2_awaddr_s_o15; - output fabric_llpp2_awaddr_s_o16; - output fabric_llpp2_awaddr_s_o17; - output fabric_llpp2_awaddr_s_o18; - output fabric_llpp2_awaddr_s_o19; - output fabric_llpp2_awaddr_s_o2; - output fabric_llpp2_awaddr_s_o20; - output fabric_llpp2_awaddr_s_o21; - output fabric_llpp2_awaddr_s_o22; - output fabric_llpp2_awaddr_s_o23; - output fabric_llpp2_awaddr_s_o24; - output fabric_llpp2_awaddr_s_o25; - output fabric_llpp2_awaddr_s_o26; - output fabric_llpp2_awaddr_s_o27; - output fabric_llpp2_awaddr_s_o28; - output fabric_llpp2_awaddr_s_o29; - output fabric_llpp2_awaddr_s_o3; - output fabric_llpp2_awaddr_s_o30; - output fabric_llpp2_awaddr_s_o31; - output fabric_llpp2_awaddr_s_o32; - output fabric_llpp2_awaddr_s_o4; - output fabric_llpp2_awaddr_s_o5; - output fabric_llpp2_awaddr_s_o6; - output fabric_llpp2_awaddr_s_o7; - output fabric_llpp2_awaddr_s_o8; - output fabric_llpp2_awaddr_s_o9; - output fabric_llpp2_awburst_s_o1; - output fabric_llpp2_awburst_s_o2; - output fabric_llpp2_awcache_s_o1; - output fabric_llpp2_awcache_s_o2; - output fabric_llpp2_awcache_s_o3; - output fabric_llpp2_awcache_s_o4; - output fabric_llpp2_awid_s_o1; - output fabric_llpp2_awid_s_o10; - output fabric_llpp2_awid_s_o11; - output fabric_llpp2_awid_s_o12; - output fabric_llpp2_awid_s_o2; - output fabric_llpp2_awid_s_o3; - output fabric_llpp2_awid_s_o4; - output fabric_llpp2_awid_s_o5; - output fabric_llpp2_awid_s_o6; - output fabric_llpp2_awid_s_o7; - output fabric_llpp2_awid_s_o8; - output fabric_llpp2_awid_s_o9; - output fabric_llpp2_awlen_s_o1; - output fabric_llpp2_awlen_s_o2; - output fabric_llpp2_awlen_s_o3; - output fabric_llpp2_awlen_s_o4; - output fabric_llpp2_awlen_s_o5; - output fabric_llpp2_awlen_s_o6; - output fabric_llpp2_awlen_s_o7; - output fabric_llpp2_awlen_s_o8; - output fabric_llpp2_awlock_s_o; - output fabric_llpp2_awprot_s_o1; - output fabric_llpp2_awprot_s_o2; - output fabric_llpp2_awprot_s_o3; - output fabric_llpp2_awqos_s_o1; - output fabric_llpp2_awqos_s_o2; - output fabric_llpp2_awqos_s_o3; - output fabric_llpp2_awqos_s_o4; - input fabric_llpp2_awready_s_i; - output fabric_llpp2_awsize_s_o1; - output fabric_llpp2_awsize_s_o2; - output fabric_llpp2_awsize_s_o3; - output fabric_llpp2_awvalid_s_o; - input fabric_llpp2_bid_s_i1; - input fabric_llpp2_bid_s_i10; - input fabric_llpp2_bid_s_i11; - input fabric_llpp2_bid_s_i12; - input fabric_llpp2_bid_s_i2; - input fabric_llpp2_bid_s_i3; - input fabric_llpp2_bid_s_i4; - input fabric_llpp2_bid_s_i5; - input fabric_llpp2_bid_s_i6; - input fabric_llpp2_bid_s_i7; - input fabric_llpp2_bid_s_i8; - input fabric_llpp2_bid_s_i9; - output fabric_llpp2_bready_s_o; - input fabric_llpp2_bresp_s_i1; - input fabric_llpp2_bresp_s_i2; - input fabric_llpp2_bvalid_s_i; - input fabric_llpp2_rdata_s_i1; - input fabric_llpp2_rdata_s_i10; - input fabric_llpp2_rdata_s_i11; - input fabric_llpp2_rdata_s_i12; - input fabric_llpp2_rdata_s_i13; - input fabric_llpp2_rdata_s_i14; - input fabric_llpp2_rdata_s_i15; - input fabric_llpp2_rdata_s_i16; - input fabric_llpp2_rdata_s_i17; - input fabric_llpp2_rdata_s_i18; - input fabric_llpp2_rdata_s_i19; - input fabric_llpp2_rdata_s_i2; - input fabric_llpp2_rdata_s_i20; - input fabric_llpp2_rdata_s_i21; - input fabric_llpp2_rdata_s_i22; - input fabric_llpp2_rdata_s_i23; - input fabric_llpp2_rdata_s_i24; - input fabric_llpp2_rdata_s_i25; - input fabric_llpp2_rdata_s_i26; - input fabric_llpp2_rdata_s_i27; - input fabric_llpp2_rdata_s_i28; - input fabric_llpp2_rdata_s_i29; - input fabric_llpp2_rdata_s_i3; - input fabric_llpp2_rdata_s_i30; - input fabric_llpp2_rdata_s_i31; - input fabric_llpp2_rdata_s_i32; - input fabric_llpp2_rdata_s_i4; - input fabric_llpp2_rdata_s_i5; - input fabric_llpp2_rdata_s_i6; - input fabric_llpp2_rdata_s_i7; - input fabric_llpp2_rdata_s_i8; - input fabric_llpp2_rdata_s_i9; - input fabric_llpp2_rid_s_i1; - input fabric_llpp2_rid_s_i10; - input fabric_llpp2_rid_s_i11; - input fabric_llpp2_rid_s_i12; - input fabric_llpp2_rid_s_i2; - input fabric_llpp2_rid_s_i3; - input fabric_llpp2_rid_s_i4; - input fabric_llpp2_rid_s_i5; - input fabric_llpp2_rid_s_i6; - input fabric_llpp2_rid_s_i7; - input fabric_llpp2_rid_s_i8; - input fabric_llpp2_rid_s_i9; - input fabric_llpp2_rlast_s_i; - output fabric_llpp2_rready_s_o; - input fabric_llpp2_rresp_s_i1; - input fabric_llpp2_rresp_s_i2; - input fabric_llpp2_rvalid_s_i; - output fabric_llpp2_wdata_s_o1; - output fabric_llpp2_wdata_s_o10; - output fabric_llpp2_wdata_s_o11; - output fabric_llpp2_wdata_s_o12; - output fabric_llpp2_wdata_s_o13; - output fabric_llpp2_wdata_s_o14; - output fabric_llpp2_wdata_s_o15; - output fabric_llpp2_wdata_s_o16; - output fabric_llpp2_wdata_s_o17; - output fabric_llpp2_wdata_s_o18; - output fabric_llpp2_wdata_s_o19; - output fabric_llpp2_wdata_s_o2; - output fabric_llpp2_wdata_s_o20; - output fabric_llpp2_wdata_s_o21; - output fabric_llpp2_wdata_s_o22; - output fabric_llpp2_wdata_s_o23; - output fabric_llpp2_wdata_s_o24; - output fabric_llpp2_wdata_s_o25; - output fabric_llpp2_wdata_s_o26; - output fabric_llpp2_wdata_s_o27; - output fabric_llpp2_wdata_s_o28; - output fabric_llpp2_wdata_s_o29; - output fabric_llpp2_wdata_s_o3; - output fabric_llpp2_wdata_s_o30; - output fabric_llpp2_wdata_s_o31; - output fabric_llpp2_wdata_s_o32; - output fabric_llpp2_wdata_s_o4; - output fabric_llpp2_wdata_s_o5; - output fabric_llpp2_wdata_s_o6; - output fabric_llpp2_wdata_s_o7; - output fabric_llpp2_wdata_s_o8; - output fabric_llpp2_wdata_s_o9; - output fabric_llpp2_wlast_s_o; - input fabric_llpp2_wready_s_i; - output fabric_llpp2_wstrb_s_o1; - output fabric_llpp2_wstrb_s_o2; - output fabric_llpp2_wstrb_s_o3; - output fabric_llpp2_wstrb_s_o4; - output fabric_llpp2_wvalid_s_o; - output fabric_llpp3_araddr_s_o1; - output fabric_llpp3_araddr_s_o10; - output fabric_llpp3_araddr_s_o11; - output fabric_llpp3_araddr_s_o12; - output fabric_llpp3_araddr_s_o13; - output fabric_llpp3_araddr_s_o14; - output fabric_llpp3_araddr_s_o15; - output fabric_llpp3_araddr_s_o16; - output fabric_llpp3_araddr_s_o17; - output fabric_llpp3_araddr_s_o18; - output fabric_llpp3_araddr_s_o19; - output fabric_llpp3_araddr_s_o2; - output fabric_llpp3_araddr_s_o20; - output fabric_llpp3_araddr_s_o21; - output fabric_llpp3_araddr_s_o22; - output fabric_llpp3_araddr_s_o23; - output fabric_llpp3_araddr_s_o24; - output fabric_llpp3_araddr_s_o25; - output fabric_llpp3_araddr_s_o26; - output fabric_llpp3_araddr_s_o27; - output fabric_llpp3_araddr_s_o28; - output fabric_llpp3_araddr_s_o29; - output fabric_llpp3_araddr_s_o3; - output fabric_llpp3_araddr_s_o30; - output fabric_llpp3_araddr_s_o31; - output fabric_llpp3_araddr_s_o32; - output fabric_llpp3_araddr_s_o4; - output fabric_llpp3_araddr_s_o5; - output fabric_llpp3_araddr_s_o6; - output fabric_llpp3_araddr_s_o7; - output fabric_llpp3_araddr_s_o8; - output fabric_llpp3_araddr_s_o9; - output fabric_llpp3_arburst_s_o1; - output fabric_llpp3_arburst_s_o2; - output fabric_llpp3_arcache_s_o1; - output fabric_llpp3_arcache_s_o2; - output fabric_llpp3_arcache_s_o3; - output fabric_llpp3_arcache_s_o4; - output fabric_llpp3_arid_s_o1; - output fabric_llpp3_arid_s_o10; - output fabric_llpp3_arid_s_o11; - output fabric_llpp3_arid_s_o12; - output fabric_llpp3_arid_s_o2; - output fabric_llpp3_arid_s_o3; - output fabric_llpp3_arid_s_o4; - output fabric_llpp3_arid_s_o5; - output fabric_llpp3_arid_s_o6; - output fabric_llpp3_arid_s_o7; - output fabric_llpp3_arid_s_o8; - output fabric_llpp3_arid_s_o9; - output fabric_llpp3_arlen_s_o1; - output fabric_llpp3_arlen_s_o2; - output fabric_llpp3_arlen_s_o3; - output fabric_llpp3_arlen_s_o4; - output fabric_llpp3_arlen_s_o5; - output fabric_llpp3_arlen_s_o6; - output fabric_llpp3_arlen_s_o7; - output fabric_llpp3_arlen_s_o8; - output fabric_llpp3_arlock_s_o; - output fabric_llpp3_arprot_s_o1; - output fabric_llpp3_arprot_s_o2; - output fabric_llpp3_arprot_s_o3; - output fabric_llpp3_arqos_s_o1; - output fabric_llpp3_arqos_s_o2; - output fabric_llpp3_arqos_s_o3; - output fabric_llpp3_arqos_s_o4; - input fabric_llpp3_arready_s_i; - output fabric_llpp3_arsize_s_o1; - output fabric_llpp3_arsize_s_o2; - output fabric_llpp3_arsize_s_o3; - output fabric_llpp3_arvalid_s_o; - output fabric_llpp3_awaddr_s_o1; - output fabric_llpp3_awaddr_s_o10; - output fabric_llpp3_awaddr_s_o11; - output fabric_llpp3_awaddr_s_o12; - output fabric_llpp3_awaddr_s_o13; - output fabric_llpp3_awaddr_s_o14; - output fabric_llpp3_awaddr_s_o15; - output fabric_llpp3_awaddr_s_o16; - output fabric_llpp3_awaddr_s_o17; - output fabric_llpp3_awaddr_s_o18; - output fabric_llpp3_awaddr_s_o19; - output fabric_llpp3_awaddr_s_o2; - output fabric_llpp3_awaddr_s_o20; - output fabric_llpp3_awaddr_s_o21; - output fabric_llpp3_awaddr_s_o22; - output fabric_llpp3_awaddr_s_o23; - output fabric_llpp3_awaddr_s_o24; - output fabric_llpp3_awaddr_s_o25; - output fabric_llpp3_awaddr_s_o26; - output fabric_llpp3_awaddr_s_o27; - output fabric_llpp3_awaddr_s_o28; - output fabric_llpp3_awaddr_s_o29; - output fabric_llpp3_awaddr_s_o3; - output fabric_llpp3_awaddr_s_o30; - output fabric_llpp3_awaddr_s_o31; - output fabric_llpp3_awaddr_s_o32; - output fabric_llpp3_awaddr_s_o4; - output fabric_llpp3_awaddr_s_o5; - output fabric_llpp3_awaddr_s_o6; - output fabric_llpp3_awaddr_s_o7; - output fabric_llpp3_awaddr_s_o8; - output fabric_llpp3_awaddr_s_o9; - output fabric_llpp3_awburst_s_o1; - output fabric_llpp3_awburst_s_o2; - output fabric_llpp3_awcache_s_o1; - output fabric_llpp3_awcache_s_o2; - output fabric_llpp3_awcache_s_o3; - output fabric_llpp3_awcache_s_o4; - output fabric_llpp3_awid_s_o1; - output fabric_llpp3_awid_s_o10; - output fabric_llpp3_awid_s_o11; - output fabric_llpp3_awid_s_o12; - output fabric_llpp3_awid_s_o2; - output fabric_llpp3_awid_s_o3; - output fabric_llpp3_awid_s_o4; - output fabric_llpp3_awid_s_o5; - output fabric_llpp3_awid_s_o6; - output fabric_llpp3_awid_s_o7; - output fabric_llpp3_awid_s_o8; - output fabric_llpp3_awid_s_o9; - output fabric_llpp3_awlen_s_o1; - output fabric_llpp3_awlen_s_o2; - output fabric_llpp3_awlen_s_o3; - output fabric_llpp3_awlen_s_o4; - output fabric_llpp3_awlen_s_o5; - output fabric_llpp3_awlen_s_o6; - output fabric_llpp3_awlen_s_o7; - output fabric_llpp3_awlen_s_o8; - output fabric_llpp3_awlock_s_o; - output fabric_llpp3_awprot_s_o1; - output fabric_llpp3_awprot_s_o2; - output fabric_llpp3_awprot_s_o3; - output fabric_llpp3_awqos_s_o1; - output fabric_llpp3_awqos_s_o2; - output fabric_llpp3_awqos_s_o3; - output fabric_llpp3_awqos_s_o4; - input fabric_llpp3_awready_s_i; - output fabric_llpp3_awsize_s_o1; - output fabric_llpp3_awsize_s_o2; - output fabric_llpp3_awsize_s_o3; - output fabric_llpp3_awvalid_s_o; - input fabric_llpp3_bid_s_i1; - input fabric_llpp3_bid_s_i10; - input fabric_llpp3_bid_s_i11; - input fabric_llpp3_bid_s_i12; - input fabric_llpp3_bid_s_i2; - input fabric_llpp3_bid_s_i3; - input fabric_llpp3_bid_s_i4; - input fabric_llpp3_bid_s_i5; - input fabric_llpp3_bid_s_i6; - input fabric_llpp3_bid_s_i7; - input fabric_llpp3_bid_s_i8; - input fabric_llpp3_bid_s_i9; - output fabric_llpp3_bready_s_o; - input fabric_llpp3_bresp_s_i1; - input fabric_llpp3_bresp_s_i2; - input fabric_llpp3_bvalid_s_i; - input fabric_llpp3_rdata_s_i1; - input fabric_llpp3_rdata_s_i10; - input fabric_llpp3_rdata_s_i11; - input fabric_llpp3_rdata_s_i12; - input fabric_llpp3_rdata_s_i13; - input fabric_llpp3_rdata_s_i14; - input fabric_llpp3_rdata_s_i15; - input fabric_llpp3_rdata_s_i16; - input fabric_llpp3_rdata_s_i17; - input fabric_llpp3_rdata_s_i18; - input fabric_llpp3_rdata_s_i19; - input fabric_llpp3_rdata_s_i2; - input fabric_llpp3_rdata_s_i20; - input fabric_llpp3_rdata_s_i21; - input fabric_llpp3_rdata_s_i22; - input fabric_llpp3_rdata_s_i23; - input fabric_llpp3_rdata_s_i24; - input fabric_llpp3_rdata_s_i25; - input fabric_llpp3_rdata_s_i26; - input fabric_llpp3_rdata_s_i27; - input fabric_llpp3_rdata_s_i28; - input fabric_llpp3_rdata_s_i29; - input fabric_llpp3_rdata_s_i3; - input fabric_llpp3_rdata_s_i30; - input fabric_llpp3_rdata_s_i31; - input fabric_llpp3_rdata_s_i32; - input fabric_llpp3_rdata_s_i4; - input fabric_llpp3_rdata_s_i5; - input fabric_llpp3_rdata_s_i6; - input fabric_llpp3_rdata_s_i7; - input fabric_llpp3_rdata_s_i8; - input fabric_llpp3_rdata_s_i9; - input fabric_llpp3_rid_s_i1; - input fabric_llpp3_rid_s_i10; - input fabric_llpp3_rid_s_i11; - input fabric_llpp3_rid_s_i12; - input fabric_llpp3_rid_s_i2; - input fabric_llpp3_rid_s_i3; - input fabric_llpp3_rid_s_i4; - input fabric_llpp3_rid_s_i5; - input fabric_llpp3_rid_s_i6; - input fabric_llpp3_rid_s_i7; - input fabric_llpp3_rid_s_i8; - input fabric_llpp3_rid_s_i9; - input fabric_llpp3_rlast_s_i; - output fabric_llpp3_rready_s_o; - input fabric_llpp3_rresp_s_i1; - input fabric_llpp3_rresp_s_i2; - input fabric_llpp3_rvalid_s_i; - output fabric_llpp3_wdata_s_o1; - output fabric_llpp3_wdata_s_o10; - output fabric_llpp3_wdata_s_o11; - output fabric_llpp3_wdata_s_o12; - output fabric_llpp3_wdata_s_o13; - output fabric_llpp3_wdata_s_o14; - output fabric_llpp3_wdata_s_o15; - output fabric_llpp3_wdata_s_o16; - output fabric_llpp3_wdata_s_o17; - output fabric_llpp3_wdata_s_o18; - output fabric_llpp3_wdata_s_o19; - output fabric_llpp3_wdata_s_o2; - output fabric_llpp3_wdata_s_o20; - output fabric_llpp3_wdata_s_o21; - output fabric_llpp3_wdata_s_o22; - output fabric_llpp3_wdata_s_o23; - output fabric_llpp3_wdata_s_o24; - output fabric_llpp3_wdata_s_o25; - output fabric_llpp3_wdata_s_o26; - output fabric_llpp3_wdata_s_o27; - output fabric_llpp3_wdata_s_o28; - output fabric_llpp3_wdata_s_o29; - output fabric_llpp3_wdata_s_o3; - output fabric_llpp3_wdata_s_o30; - output fabric_llpp3_wdata_s_o31; - output fabric_llpp3_wdata_s_o32; - output fabric_llpp3_wdata_s_o4; - output fabric_llpp3_wdata_s_o5; - output fabric_llpp3_wdata_s_o6; - output fabric_llpp3_wdata_s_o7; - output fabric_llpp3_wdata_s_o8; - output fabric_llpp3_wdata_s_o9; - output fabric_llpp3_wlast_s_o; - input fabric_llpp3_wready_s_i; - output fabric_llpp3_wstrb_s_o1; - output fabric_llpp3_wstrb_s_o2; - output fabric_llpp3_wstrb_s_o3; - output fabric_llpp3_wstrb_s_o4; - output fabric_llpp3_wvalid_s_o; - input fabric_lowskew_i10; - input fabric_lowskew_i11; - input fabric_lowskew_i12; - input fabric_lowskew_i13; - input fabric_lowskew_i14; - input fabric_lowskew_i15; - input fabric_lowskew_i16; - input fabric_lowskew_i17; - input fabric_lowskew_i18; - input fabric_lowskew_i19; - input fabric_lowskew_i3; - input fabric_lowskew_i4; - input fabric_lowskew_i5; - input fabric_lowskew_i6; - input fabric_lowskew_i7; - input fabric_lowskew_i8; - input fabric_lowskew_i9; - output fabric_lowskew_o1; - output fabric_lowskew_o2; - input fabric_qos_ppaddr_i1; - input fabric_qos_ppaddr_i10; - input fabric_qos_ppaddr_i11; - input fabric_qos_ppaddr_i12; - input fabric_qos_ppaddr_i13; - input fabric_qos_ppaddr_i14; - input fabric_qos_ppaddr_i15; - input fabric_qos_ppaddr_i16; - input fabric_qos_ppaddr_i17; - input fabric_qos_ppaddr_i18; - input fabric_qos_ppaddr_i19; - input fabric_qos_ppaddr_i2; - input fabric_qos_ppaddr_i20; - input fabric_qos_ppaddr_i21; - input fabric_qos_ppaddr_i22; - input fabric_qos_ppaddr_i23; - input fabric_qos_ppaddr_i24; - input fabric_qos_ppaddr_i25; - input fabric_qos_ppaddr_i26; - input fabric_qos_ppaddr_i27; - input fabric_qos_ppaddr_i28; - input fabric_qos_ppaddr_i29; - input fabric_qos_ppaddr_i3; - input fabric_qos_ppaddr_i30; - input fabric_qos_ppaddr_i31; - input fabric_qos_ppaddr_i32; - input fabric_qos_ppaddr_i4; - input fabric_qos_ppaddr_i5; - input fabric_qos_ppaddr_i6; - input fabric_qos_ppaddr_i7; - input fabric_qos_ppaddr_i8; - input fabric_qos_ppaddr_i9; - input fabric_qos_ppenable_i; - output fabric_qos_pprdata_o1; - output fabric_qos_pprdata_o10; - output fabric_qos_pprdata_o11; - output fabric_qos_pprdata_o12; - output fabric_qos_pprdata_o13; - output fabric_qos_pprdata_o14; - output fabric_qos_pprdata_o15; - output fabric_qos_pprdata_o16; - output fabric_qos_pprdata_o17; - output fabric_qos_pprdata_o18; - output fabric_qos_pprdata_o19; - output fabric_qos_pprdata_o2; - output fabric_qos_pprdata_o20; - output fabric_qos_pprdata_o21; - output fabric_qos_pprdata_o22; - output fabric_qos_pprdata_o23; - output fabric_qos_pprdata_o24; - output fabric_qos_pprdata_o25; - output fabric_qos_pprdata_o26; - output fabric_qos_pprdata_o27; - output fabric_qos_pprdata_o28; - output fabric_qos_pprdata_o29; - output fabric_qos_pprdata_o3; - output fabric_qos_pprdata_o30; - output fabric_qos_pprdata_o31; - output fabric_qos_pprdata_o32; - output fabric_qos_pprdata_o4; - output fabric_qos_pprdata_o5; - output fabric_qos_pprdata_o6; - output fabric_qos_pprdata_o7; - output fabric_qos_pprdata_o8; - output fabric_qos_pprdata_o9; - output fabric_qos_ppready_o; - output fabric_qos_ppslverr_o; - input fabric_qos_ppwdata_i1; - input fabric_qos_ppwdata_i10; - input fabric_qos_ppwdata_i11; - input fabric_qos_ppwdata_i12; - input fabric_qos_ppwdata_i13; - input fabric_qos_ppwdata_i14; - input fabric_qos_ppwdata_i15; - input fabric_qos_ppwdata_i16; - input fabric_qos_ppwdata_i17; - input fabric_qos_ppwdata_i18; - input fabric_qos_ppwdata_i19; - input fabric_qos_ppwdata_i2; - input fabric_qos_ppwdata_i20; - input fabric_qos_ppwdata_i21; - input fabric_qos_ppwdata_i22; - input fabric_qos_ppwdata_i23; - input fabric_qos_ppwdata_i24; - input fabric_qos_ppwdata_i25; - input fabric_qos_ppwdata_i26; - input fabric_qos_ppwdata_i27; - input fabric_qos_ppwdata_i28; - input fabric_qos_ppwdata_i29; - input fabric_qos_ppwdata_i3; - input fabric_qos_ppwdata_i30; - input fabric_qos_ppwdata_i31; - input fabric_qos_ppwdata_i32; - input fabric_qos_ppwdata_i4; - input fabric_qos_ppwdata_i5; - input fabric_qos_ppwdata_i6; - input fabric_qos_ppwdata_i7; - input fabric_qos_ppwdata_i8; - input fabric_qos_ppwdata_i9; - input fabric_qos_ppwrite_i; - input fabric_qos_presetn_i; - input fabric_qos_psel_i; - output fabric_soc_mon_sensor_alarm_o; - output fabric_spw_interrupts_o1; - output fabric_spw_interrupts_o2; - output fabric_spw_interrupts_o3; - output fabric_spw_interrupts_toggle_o1; - output fabric_spw_interrupts_toggle_o2; - output fabric_spw_interrupts_toggle_o3; - input fabric_sysc_hold_on_debug_i; - output fabric_tnd_fpga_apb_master_paddr_o1; - output fabric_tnd_fpga_apb_master_paddr_o10; - output fabric_tnd_fpga_apb_master_paddr_o11; - output fabric_tnd_fpga_apb_master_paddr_o12; - output fabric_tnd_fpga_apb_master_paddr_o13; - output fabric_tnd_fpga_apb_master_paddr_o14; - output fabric_tnd_fpga_apb_master_paddr_o15; - output fabric_tnd_fpga_apb_master_paddr_o16; - output fabric_tnd_fpga_apb_master_paddr_o17; - output fabric_tnd_fpga_apb_master_paddr_o18; - output fabric_tnd_fpga_apb_master_paddr_o19; - output fabric_tnd_fpga_apb_master_paddr_o2; - output fabric_tnd_fpga_apb_master_paddr_o20; - output fabric_tnd_fpga_apb_master_paddr_o21; - output fabric_tnd_fpga_apb_master_paddr_o22; - output fabric_tnd_fpga_apb_master_paddr_o23; - output fabric_tnd_fpga_apb_master_paddr_o24; - output fabric_tnd_fpga_apb_master_paddr_o25; - output fabric_tnd_fpga_apb_master_paddr_o26; - output fabric_tnd_fpga_apb_master_paddr_o27; - output fabric_tnd_fpga_apb_master_paddr_o28; - output fabric_tnd_fpga_apb_master_paddr_o29; - output fabric_tnd_fpga_apb_master_paddr_o3; - output fabric_tnd_fpga_apb_master_paddr_o30; - output fabric_tnd_fpga_apb_master_paddr_o31; - output fabric_tnd_fpga_apb_master_paddr_o32; - output fabric_tnd_fpga_apb_master_paddr_o4; - output fabric_tnd_fpga_apb_master_paddr_o5; - output fabric_tnd_fpga_apb_master_paddr_o6; - output fabric_tnd_fpga_apb_master_paddr_o7; - output fabric_tnd_fpga_apb_master_paddr_o8; - output fabric_tnd_fpga_apb_master_paddr_o9; - output fabric_tnd_fpga_apb_master_penable_o; - input fabric_tnd_fpga_apb_master_prdata_i1; - input fabric_tnd_fpga_apb_master_prdata_i10; - input fabric_tnd_fpga_apb_master_prdata_i11; - input fabric_tnd_fpga_apb_master_prdata_i12; - input fabric_tnd_fpga_apb_master_prdata_i13; - input fabric_tnd_fpga_apb_master_prdata_i14; - input fabric_tnd_fpga_apb_master_prdata_i15; - input fabric_tnd_fpga_apb_master_prdata_i16; - input fabric_tnd_fpga_apb_master_prdata_i17; - input fabric_tnd_fpga_apb_master_prdata_i18; - input fabric_tnd_fpga_apb_master_prdata_i19; - input fabric_tnd_fpga_apb_master_prdata_i2; - input fabric_tnd_fpga_apb_master_prdata_i20; - input fabric_tnd_fpga_apb_master_prdata_i21; - input fabric_tnd_fpga_apb_master_prdata_i22; - input fabric_tnd_fpga_apb_master_prdata_i23; - input fabric_tnd_fpga_apb_master_prdata_i24; - input fabric_tnd_fpga_apb_master_prdata_i25; - input fabric_tnd_fpga_apb_master_prdata_i26; - input fabric_tnd_fpga_apb_master_prdata_i27; - input fabric_tnd_fpga_apb_master_prdata_i28; - input fabric_tnd_fpga_apb_master_prdata_i29; - input fabric_tnd_fpga_apb_master_prdata_i3; - input fabric_tnd_fpga_apb_master_prdata_i30; - input fabric_tnd_fpga_apb_master_prdata_i31; - input fabric_tnd_fpga_apb_master_prdata_i32; - input fabric_tnd_fpga_apb_master_prdata_i4; - input fabric_tnd_fpga_apb_master_prdata_i5; - input fabric_tnd_fpga_apb_master_prdata_i6; - input fabric_tnd_fpga_apb_master_prdata_i7; - input fabric_tnd_fpga_apb_master_prdata_i8; - input fabric_tnd_fpga_apb_master_prdata_i9; - input fabric_tnd_fpga_apb_master_pready_i; - output fabric_tnd_fpga_apb_master_psel_o; - input fabric_tnd_fpga_apb_master_pslverr_i; - output fabric_tnd_fpga_apb_master_pwdata_o1; - output fabric_tnd_fpga_apb_master_pwdata_o10; - output fabric_tnd_fpga_apb_master_pwdata_o11; - output fabric_tnd_fpga_apb_master_pwdata_o12; - output fabric_tnd_fpga_apb_master_pwdata_o13; - output fabric_tnd_fpga_apb_master_pwdata_o14; - output fabric_tnd_fpga_apb_master_pwdata_o15; - output fabric_tnd_fpga_apb_master_pwdata_o16; - output fabric_tnd_fpga_apb_master_pwdata_o17; - output fabric_tnd_fpga_apb_master_pwdata_o18; - output fabric_tnd_fpga_apb_master_pwdata_o19; - output fabric_tnd_fpga_apb_master_pwdata_o2; - output fabric_tnd_fpga_apb_master_pwdata_o20; - output fabric_tnd_fpga_apb_master_pwdata_o21; - output fabric_tnd_fpga_apb_master_pwdata_o22; - output fabric_tnd_fpga_apb_master_pwdata_o23; - output fabric_tnd_fpga_apb_master_pwdata_o24; - output fabric_tnd_fpga_apb_master_pwdata_o25; - output fabric_tnd_fpga_apb_master_pwdata_o26; - output fabric_tnd_fpga_apb_master_pwdata_o27; - output fabric_tnd_fpga_apb_master_pwdata_o28; - output fabric_tnd_fpga_apb_master_pwdata_o29; - output fabric_tnd_fpga_apb_master_pwdata_o3; - output fabric_tnd_fpga_apb_master_pwdata_o30; - output fabric_tnd_fpga_apb_master_pwdata_o31; - output fabric_tnd_fpga_apb_master_pwdata_o32; - output fabric_tnd_fpga_apb_master_pwdata_o4; - output fabric_tnd_fpga_apb_master_pwdata_o5; - output fabric_tnd_fpga_apb_master_pwdata_o6; - output fabric_tnd_fpga_apb_master_pwdata_o7; - output fabric_tnd_fpga_apb_master_pwdata_o8; - output fabric_tnd_fpga_apb_master_pwdata_o9; - output fabric_tnd_fpga_apb_master_pwrite_o; - input fabric_tnd_fpga_atb_master_afready_i; - output fabric_tnd_fpga_atb_master_afvalid_o; - input fabric_tnd_fpga_atb_master_atbytes_i1; - input fabric_tnd_fpga_atb_master_atbytes_i2; - input fabric_tnd_fpga_atb_master_atbytes_i3; - input fabric_tnd_fpga_atb_master_atbytes_i4; - input fabric_tnd_fpga_atb_master_atdata_i1; - input fabric_tnd_fpga_atb_master_atdata_i10; - input fabric_tnd_fpga_atb_master_atdata_i100; - input fabric_tnd_fpga_atb_master_atdata_i101; - input fabric_tnd_fpga_atb_master_atdata_i102; - input fabric_tnd_fpga_atb_master_atdata_i103; - input fabric_tnd_fpga_atb_master_atdata_i104; - input fabric_tnd_fpga_atb_master_atdata_i105; - input fabric_tnd_fpga_atb_master_atdata_i106; - input fabric_tnd_fpga_atb_master_atdata_i107; - input fabric_tnd_fpga_atb_master_atdata_i108; - input fabric_tnd_fpga_atb_master_atdata_i109; - input fabric_tnd_fpga_atb_master_atdata_i11; - input fabric_tnd_fpga_atb_master_atdata_i110; - input fabric_tnd_fpga_atb_master_atdata_i111; - input fabric_tnd_fpga_atb_master_atdata_i112; - input fabric_tnd_fpga_atb_master_atdata_i113; - input fabric_tnd_fpga_atb_master_atdata_i114; - input fabric_tnd_fpga_atb_master_atdata_i115; - input fabric_tnd_fpga_atb_master_atdata_i116; - input fabric_tnd_fpga_atb_master_atdata_i117; - input fabric_tnd_fpga_atb_master_atdata_i118; - input fabric_tnd_fpga_atb_master_atdata_i119; - input fabric_tnd_fpga_atb_master_atdata_i12; - input fabric_tnd_fpga_atb_master_atdata_i120; - input fabric_tnd_fpga_atb_master_atdata_i121; - input fabric_tnd_fpga_atb_master_atdata_i122; - input fabric_tnd_fpga_atb_master_atdata_i123; - input fabric_tnd_fpga_atb_master_atdata_i124; - input fabric_tnd_fpga_atb_master_atdata_i125; - input fabric_tnd_fpga_atb_master_atdata_i126; - input fabric_tnd_fpga_atb_master_atdata_i127; - input fabric_tnd_fpga_atb_master_atdata_i128; - input fabric_tnd_fpga_atb_master_atdata_i13; - input fabric_tnd_fpga_atb_master_atdata_i14; - input fabric_tnd_fpga_atb_master_atdata_i15; - input fabric_tnd_fpga_atb_master_atdata_i16; - input fabric_tnd_fpga_atb_master_atdata_i17; - input fabric_tnd_fpga_atb_master_atdata_i18; - input fabric_tnd_fpga_atb_master_atdata_i19; - input fabric_tnd_fpga_atb_master_atdata_i2; - input fabric_tnd_fpga_atb_master_atdata_i20; - input fabric_tnd_fpga_atb_master_atdata_i21; - input fabric_tnd_fpga_atb_master_atdata_i22; - input fabric_tnd_fpga_atb_master_atdata_i23; - input fabric_tnd_fpga_atb_master_atdata_i24; - input fabric_tnd_fpga_atb_master_atdata_i25; - input fabric_tnd_fpga_atb_master_atdata_i26; - input fabric_tnd_fpga_atb_master_atdata_i27; - input fabric_tnd_fpga_atb_master_atdata_i28; - input fabric_tnd_fpga_atb_master_atdata_i29; - input fabric_tnd_fpga_atb_master_atdata_i3; - input fabric_tnd_fpga_atb_master_atdata_i30; - input fabric_tnd_fpga_atb_master_atdata_i31; - input fabric_tnd_fpga_atb_master_atdata_i32; - input fabric_tnd_fpga_atb_master_atdata_i33; - input fabric_tnd_fpga_atb_master_atdata_i34; - input fabric_tnd_fpga_atb_master_atdata_i35; - input fabric_tnd_fpga_atb_master_atdata_i36; - input fabric_tnd_fpga_atb_master_atdata_i37; - input fabric_tnd_fpga_atb_master_atdata_i38; - input fabric_tnd_fpga_atb_master_atdata_i39; - input fabric_tnd_fpga_atb_master_atdata_i4; - input fabric_tnd_fpga_atb_master_atdata_i40; - input fabric_tnd_fpga_atb_master_atdata_i41; - input fabric_tnd_fpga_atb_master_atdata_i42; - input fabric_tnd_fpga_atb_master_atdata_i43; - input fabric_tnd_fpga_atb_master_atdata_i44; - input fabric_tnd_fpga_atb_master_atdata_i45; - input fabric_tnd_fpga_atb_master_atdata_i46; - input fabric_tnd_fpga_atb_master_atdata_i47; - input fabric_tnd_fpga_atb_master_atdata_i48; - input fabric_tnd_fpga_atb_master_atdata_i49; - input fabric_tnd_fpga_atb_master_atdata_i5; - input fabric_tnd_fpga_atb_master_atdata_i50; - input fabric_tnd_fpga_atb_master_atdata_i51; - input fabric_tnd_fpga_atb_master_atdata_i52; - input fabric_tnd_fpga_atb_master_atdata_i53; - input fabric_tnd_fpga_atb_master_atdata_i54; - input fabric_tnd_fpga_atb_master_atdata_i55; - input fabric_tnd_fpga_atb_master_atdata_i56; - input fabric_tnd_fpga_atb_master_atdata_i57; - input fabric_tnd_fpga_atb_master_atdata_i58; - input fabric_tnd_fpga_atb_master_atdata_i59; - input fabric_tnd_fpga_atb_master_atdata_i6; - input fabric_tnd_fpga_atb_master_atdata_i60; - input fabric_tnd_fpga_atb_master_atdata_i61; - input fabric_tnd_fpga_atb_master_atdata_i62; - input fabric_tnd_fpga_atb_master_atdata_i63; - input fabric_tnd_fpga_atb_master_atdata_i64; - input fabric_tnd_fpga_atb_master_atdata_i65; - input fabric_tnd_fpga_atb_master_atdata_i66; - input fabric_tnd_fpga_atb_master_atdata_i67; - input fabric_tnd_fpga_atb_master_atdata_i68; - input fabric_tnd_fpga_atb_master_atdata_i69; - input fabric_tnd_fpga_atb_master_atdata_i7; - input fabric_tnd_fpga_atb_master_atdata_i70; - input fabric_tnd_fpga_atb_master_atdata_i71; - input fabric_tnd_fpga_atb_master_atdata_i72; - input fabric_tnd_fpga_atb_master_atdata_i73; - input fabric_tnd_fpga_atb_master_atdata_i74; - input fabric_tnd_fpga_atb_master_atdata_i75; - input fabric_tnd_fpga_atb_master_atdata_i76; - input fabric_tnd_fpga_atb_master_atdata_i77; - input fabric_tnd_fpga_atb_master_atdata_i78; - input fabric_tnd_fpga_atb_master_atdata_i79; - input fabric_tnd_fpga_atb_master_atdata_i8; - input fabric_tnd_fpga_atb_master_atdata_i80; - input fabric_tnd_fpga_atb_master_atdata_i81; - input fabric_tnd_fpga_atb_master_atdata_i82; - input fabric_tnd_fpga_atb_master_atdata_i83; - input fabric_tnd_fpga_atb_master_atdata_i84; - input fabric_tnd_fpga_atb_master_atdata_i85; - input fabric_tnd_fpga_atb_master_atdata_i86; - input fabric_tnd_fpga_atb_master_atdata_i87; - input fabric_tnd_fpga_atb_master_atdata_i88; - input fabric_tnd_fpga_atb_master_atdata_i89; - input fabric_tnd_fpga_atb_master_atdata_i9; - input fabric_tnd_fpga_atb_master_atdata_i90; - input fabric_tnd_fpga_atb_master_atdata_i91; - input fabric_tnd_fpga_atb_master_atdata_i92; - input fabric_tnd_fpga_atb_master_atdata_i93; - input fabric_tnd_fpga_atb_master_atdata_i94; - input fabric_tnd_fpga_atb_master_atdata_i95; - input fabric_tnd_fpga_atb_master_atdata_i96; - input fabric_tnd_fpga_atb_master_atdata_i97; - input fabric_tnd_fpga_atb_master_atdata_i98; - input fabric_tnd_fpga_atb_master_atdata_i99; - input fabric_tnd_fpga_atb_master_atid_i1; - input fabric_tnd_fpga_atb_master_atid_i2; - input fabric_tnd_fpga_atb_master_atid_i3; - input fabric_tnd_fpga_atb_master_atid_i4; - input fabric_tnd_fpga_atb_master_atid_i5; - input fabric_tnd_fpga_atb_master_atid_i6; - input fabric_tnd_fpga_atb_master_atid_i7; - output fabric_tnd_fpga_atb_master_atready_o; - input fabric_tnd_fpga_atb_master_atvalid_i; - output fabric_tnd_fpga_atb_master_syncreq_o; - output fabric_tnd_hssl_apb_master_paddr_o1; - output fabric_tnd_hssl_apb_master_paddr_o10; - output fabric_tnd_hssl_apb_master_paddr_o11; - output fabric_tnd_hssl_apb_master_paddr_o12; - output fabric_tnd_hssl_apb_master_paddr_o13; - output fabric_tnd_hssl_apb_master_paddr_o14; - output fabric_tnd_hssl_apb_master_paddr_o15; - output fabric_tnd_hssl_apb_master_paddr_o16; - output fabric_tnd_hssl_apb_master_paddr_o17; - output fabric_tnd_hssl_apb_master_paddr_o18; - output fabric_tnd_hssl_apb_master_paddr_o19; - output fabric_tnd_hssl_apb_master_paddr_o2; - output fabric_tnd_hssl_apb_master_paddr_o20; - output fabric_tnd_hssl_apb_master_paddr_o21; - output fabric_tnd_hssl_apb_master_paddr_o22; - output fabric_tnd_hssl_apb_master_paddr_o23; - output fabric_tnd_hssl_apb_master_paddr_o24; - output fabric_tnd_hssl_apb_master_paddr_o25; - output fabric_tnd_hssl_apb_master_paddr_o26; - output fabric_tnd_hssl_apb_master_paddr_o27; - output fabric_tnd_hssl_apb_master_paddr_o28; - output fabric_tnd_hssl_apb_master_paddr_o29; - output fabric_tnd_hssl_apb_master_paddr_o3; - output fabric_tnd_hssl_apb_master_paddr_o30; - output fabric_tnd_hssl_apb_master_paddr_o31; - output fabric_tnd_hssl_apb_master_paddr_o32; - output fabric_tnd_hssl_apb_master_paddr_o4; - output fabric_tnd_hssl_apb_master_paddr_o5; - output fabric_tnd_hssl_apb_master_paddr_o6; - output fabric_tnd_hssl_apb_master_paddr_o7; - output fabric_tnd_hssl_apb_master_paddr_o8; - output fabric_tnd_hssl_apb_master_paddr_o9; - output fabric_tnd_hssl_apb_master_penable_o; - input fabric_tnd_hssl_apb_master_prdata_i1; - input fabric_tnd_hssl_apb_master_prdata_i10; - input fabric_tnd_hssl_apb_master_prdata_i11; - input fabric_tnd_hssl_apb_master_prdata_i12; - input fabric_tnd_hssl_apb_master_prdata_i13; - input fabric_tnd_hssl_apb_master_prdata_i14; - input fabric_tnd_hssl_apb_master_prdata_i15; - input fabric_tnd_hssl_apb_master_prdata_i16; - input fabric_tnd_hssl_apb_master_prdata_i17; - input fabric_tnd_hssl_apb_master_prdata_i18; - input fabric_tnd_hssl_apb_master_prdata_i19; - input fabric_tnd_hssl_apb_master_prdata_i2; - input fabric_tnd_hssl_apb_master_prdata_i20; - input fabric_tnd_hssl_apb_master_prdata_i21; - input fabric_tnd_hssl_apb_master_prdata_i22; - input fabric_tnd_hssl_apb_master_prdata_i23; - input fabric_tnd_hssl_apb_master_prdata_i24; - input fabric_tnd_hssl_apb_master_prdata_i25; - input fabric_tnd_hssl_apb_master_prdata_i26; - input fabric_tnd_hssl_apb_master_prdata_i27; - input fabric_tnd_hssl_apb_master_prdata_i28; - input fabric_tnd_hssl_apb_master_prdata_i29; - input fabric_tnd_hssl_apb_master_prdata_i3; - input fabric_tnd_hssl_apb_master_prdata_i30; - input fabric_tnd_hssl_apb_master_prdata_i31; - input fabric_tnd_hssl_apb_master_prdata_i32; - input fabric_tnd_hssl_apb_master_prdata_i4; - input fabric_tnd_hssl_apb_master_prdata_i5; - input fabric_tnd_hssl_apb_master_prdata_i6; - input fabric_tnd_hssl_apb_master_prdata_i7; - input fabric_tnd_hssl_apb_master_prdata_i8; - input fabric_tnd_hssl_apb_master_prdata_i9; - input fabric_tnd_hssl_apb_master_pready_i; - output fabric_tnd_hssl_apb_master_psel_o; - input fabric_tnd_hssl_apb_master_pslverr_i; - output fabric_tnd_hssl_apb_master_pwdata_o1; - output fabric_tnd_hssl_apb_master_pwdata_o10; - output fabric_tnd_hssl_apb_master_pwdata_o11; - output fabric_tnd_hssl_apb_master_pwdata_o12; - output fabric_tnd_hssl_apb_master_pwdata_o13; - output fabric_tnd_hssl_apb_master_pwdata_o14; - output fabric_tnd_hssl_apb_master_pwdata_o15; - output fabric_tnd_hssl_apb_master_pwdata_o16; - output fabric_tnd_hssl_apb_master_pwdata_o17; - output fabric_tnd_hssl_apb_master_pwdata_o18; - output fabric_tnd_hssl_apb_master_pwdata_o19; - output fabric_tnd_hssl_apb_master_pwdata_o2; - output fabric_tnd_hssl_apb_master_pwdata_o20; - output fabric_tnd_hssl_apb_master_pwdata_o21; - output fabric_tnd_hssl_apb_master_pwdata_o22; - output fabric_tnd_hssl_apb_master_pwdata_o23; - output fabric_tnd_hssl_apb_master_pwdata_o24; - output fabric_tnd_hssl_apb_master_pwdata_o25; - output fabric_tnd_hssl_apb_master_pwdata_o26; - output fabric_tnd_hssl_apb_master_pwdata_o27; - output fabric_tnd_hssl_apb_master_pwdata_o28; - output fabric_tnd_hssl_apb_master_pwdata_o29; - output fabric_tnd_hssl_apb_master_pwdata_o3; - output fabric_tnd_hssl_apb_master_pwdata_o30; - output fabric_tnd_hssl_apb_master_pwdata_o31; - output fabric_tnd_hssl_apb_master_pwdata_o32; - output fabric_tnd_hssl_apb_master_pwdata_o4; - output fabric_tnd_hssl_apb_master_pwdata_o5; - output fabric_tnd_hssl_apb_master_pwdata_o6; - output fabric_tnd_hssl_apb_master_pwdata_o7; - output fabric_tnd_hssl_apb_master_pwdata_o8; - output fabric_tnd_hssl_apb_master_pwdata_o9; - output fabric_tnd_hssl_apb_master_pwrite_o; - output fabric_tnd_hssl_atb_master_afready_o; - input fabric_tnd_hssl_atb_master_afvalid_i; - output fabric_tnd_hssl_atb_master_atbytes_o1; - output fabric_tnd_hssl_atb_master_atbytes_o2; - output fabric_tnd_hssl_atb_master_atbytes_o3; - output fabric_tnd_hssl_atb_master_atbytes_o4; - output fabric_tnd_hssl_atb_master_atdata_o1; - output fabric_tnd_hssl_atb_master_atdata_o10; - output fabric_tnd_hssl_atb_master_atdata_o100; - output fabric_tnd_hssl_atb_master_atdata_o101; - output fabric_tnd_hssl_atb_master_atdata_o102; - output fabric_tnd_hssl_atb_master_atdata_o103; - output fabric_tnd_hssl_atb_master_atdata_o104; - output fabric_tnd_hssl_atb_master_atdata_o105; - output fabric_tnd_hssl_atb_master_atdata_o106; - output fabric_tnd_hssl_atb_master_atdata_o107; - output fabric_tnd_hssl_atb_master_atdata_o108; - output fabric_tnd_hssl_atb_master_atdata_o109; - output fabric_tnd_hssl_atb_master_atdata_o11; - output fabric_tnd_hssl_atb_master_atdata_o110; - output fabric_tnd_hssl_atb_master_atdata_o111; - output fabric_tnd_hssl_atb_master_atdata_o112; - output fabric_tnd_hssl_atb_master_atdata_o113; - output fabric_tnd_hssl_atb_master_atdata_o114; - output fabric_tnd_hssl_atb_master_atdata_o115; - output fabric_tnd_hssl_atb_master_atdata_o116; - output fabric_tnd_hssl_atb_master_atdata_o117; - output fabric_tnd_hssl_atb_master_atdata_o118; - output fabric_tnd_hssl_atb_master_atdata_o119; - output fabric_tnd_hssl_atb_master_atdata_o12; - output fabric_tnd_hssl_atb_master_atdata_o120; - output fabric_tnd_hssl_atb_master_atdata_o121; - output fabric_tnd_hssl_atb_master_atdata_o122; - output fabric_tnd_hssl_atb_master_atdata_o123; - output fabric_tnd_hssl_atb_master_atdata_o124; - output fabric_tnd_hssl_atb_master_atdata_o125; - output fabric_tnd_hssl_atb_master_atdata_o126; - output fabric_tnd_hssl_atb_master_atdata_o127; - output fabric_tnd_hssl_atb_master_atdata_o128; - output fabric_tnd_hssl_atb_master_atdata_o13; - output fabric_tnd_hssl_atb_master_atdata_o14; - output fabric_tnd_hssl_atb_master_atdata_o15; - output fabric_tnd_hssl_atb_master_atdata_o16; - output fabric_tnd_hssl_atb_master_atdata_o17; - output fabric_tnd_hssl_atb_master_atdata_o18; - output fabric_tnd_hssl_atb_master_atdata_o19; - output fabric_tnd_hssl_atb_master_atdata_o2; - output fabric_tnd_hssl_atb_master_atdata_o20; - output fabric_tnd_hssl_atb_master_atdata_o21; - output fabric_tnd_hssl_atb_master_atdata_o22; - output fabric_tnd_hssl_atb_master_atdata_o23; - output fabric_tnd_hssl_atb_master_atdata_o24; - output fabric_tnd_hssl_atb_master_atdata_o25; - output fabric_tnd_hssl_atb_master_atdata_o26; - output fabric_tnd_hssl_atb_master_atdata_o27; - output fabric_tnd_hssl_atb_master_atdata_o28; - output fabric_tnd_hssl_atb_master_atdata_o29; - output fabric_tnd_hssl_atb_master_atdata_o3; - output fabric_tnd_hssl_atb_master_atdata_o30; - output fabric_tnd_hssl_atb_master_atdata_o31; - output fabric_tnd_hssl_atb_master_atdata_o32; - output fabric_tnd_hssl_atb_master_atdata_o33; - output fabric_tnd_hssl_atb_master_atdata_o34; - output fabric_tnd_hssl_atb_master_atdata_o35; - output fabric_tnd_hssl_atb_master_atdata_o36; - output fabric_tnd_hssl_atb_master_atdata_o37; - output fabric_tnd_hssl_atb_master_atdata_o38; - output fabric_tnd_hssl_atb_master_atdata_o39; - output fabric_tnd_hssl_atb_master_atdata_o4; - output fabric_tnd_hssl_atb_master_atdata_o40; - output fabric_tnd_hssl_atb_master_atdata_o41; - output fabric_tnd_hssl_atb_master_atdata_o42; - output fabric_tnd_hssl_atb_master_atdata_o43; - output fabric_tnd_hssl_atb_master_atdata_o44; - output fabric_tnd_hssl_atb_master_atdata_o45; - output fabric_tnd_hssl_atb_master_atdata_o46; - output fabric_tnd_hssl_atb_master_atdata_o47; - output fabric_tnd_hssl_atb_master_atdata_o48; - output fabric_tnd_hssl_atb_master_atdata_o49; - output fabric_tnd_hssl_atb_master_atdata_o5; - output fabric_tnd_hssl_atb_master_atdata_o50; - output fabric_tnd_hssl_atb_master_atdata_o51; - output fabric_tnd_hssl_atb_master_atdata_o52; - output fabric_tnd_hssl_atb_master_atdata_o53; - output fabric_tnd_hssl_atb_master_atdata_o54; - output fabric_tnd_hssl_atb_master_atdata_o55; - output fabric_tnd_hssl_atb_master_atdata_o56; - output fabric_tnd_hssl_atb_master_atdata_o57; - output fabric_tnd_hssl_atb_master_atdata_o58; - output fabric_tnd_hssl_atb_master_atdata_o59; - output fabric_tnd_hssl_atb_master_atdata_o6; - output fabric_tnd_hssl_atb_master_atdata_o60; - output fabric_tnd_hssl_atb_master_atdata_o61; - output fabric_tnd_hssl_atb_master_atdata_o62; - output fabric_tnd_hssl_atb_master_atdata_o63; - output fabric_tnd_hssl_atb_master_atdata_o64; - output fabric_tnd_hssl_atb_master_atdata_o65; - output fabric_tnd_hssl_atb_master_atdata_o66; - output fabric_tnd_hssl_atb_master_atdata_o67; - output fabric_tnd_hssl_atb_master_atdata_o68; - output fabric_tnd_hssl_atb_master_atdata_o69; - output fabric_tnd_hssl_atb_master_atdata_o7; - output fabric_tnd_hssl_atb_master_atdata_o70; - output fabric_tnd_hssl_atb_master_atdata_o71; - output fabric_tnd_hssl_atb_master_atdata_o72; - output fabric_tnd_hssl_atb_master_atdata_o73; - output fabric_tnd_hssl_atb_master_atdata_o74; - output fabric_tnd_hssl_atb_master_atdata_o75; - output fabric_tnd_hssl_atb_master_atdata_o76; - output fabric_tnd_hssl_atb_master_atdata_o77; - output fabric_tnd_hssl_atb_master_atdata_o78; - output fabric_tnd_hssl_atb_master_atdata_o79; - output fabric_tnd_hssl_atb_master_atdata_o8; - output fabric_tnd_hssl_atb_master_atdata_o80; - output fabric_tnd_hssl_atb_master_atdata_o81; - output fabric_tnd_hssl_atb_master_atdata_o82; - output fabric_tnd_hssl_atb_master_atdata_o83; - output fabric_tnd_hssl_atb_master_atdata_o84; - output fabric_tnd_hssl_atb_master_atdata_o85; - output fabric_tnd_hssl_atb_master_atdata_o86; - output fabric_tnd_hssl_atb_master_atdata_o87; - output fabric_tnd_hssl_atb_master_atdata_o88; - output fabric_tnd_hssl_atb_master_atdata_o89; - output fabric_tnd_hssl_atb_master_atdata_o9; - output fabric_tnd_hssl_atb_master_atdata_o90; - output fabric_tnd_hssl_atb_master_atdata_o91; - output fabric_tnd_hssl_atb_master_atdata_o92; - output fabric_tnd_hssl_atb_master_atdata_o93; - output fabric_tnd_hssl_atb_master_atdata_o94; - output fabric_tnd_hssl_atb_master_atdata_o95; - output fabric_tnd_hssl_atb_master_atdata_o96; - output fabric_tnd_hssl_atb_master_atdata_o97; - output fabric_tnd_hssl_atb_master_atdata_o98; - output fabric_tnd_hssl_atb_master_atdata_o99; - output fabric_tnd_hssl_atb_master_atid_o1; - output fabric_tnd_hssl_atb_master_atid_o2; - output fabric_tnd_hssl_atb_master_atid_o3; - output fabric_tnd_hssl_atb_master_atid_o4; - output fabric_tnd_hssl_atb_master_atid_o5; - output fabric_tnd_hssl_atb_master_atid_o6; - output fabric_tnd_hssl_atb_master_atid_o7; - input fabric_tnd_hssl_atb_master_atready_i; - output fabric_tnd_hssl_atb_master_atvalid_o; - input fabric_tnd_hssl_atb_master_syncreq_i; - output fabric_tnd_hssl_flushin_o; - output fabric_tnd_hssl_trigin_o; - output fabric_tnd_trace_clk_traceoutportintf_o; - output fabric_tnd_trace_ctl_traceoutportintf_o; - output fabric_tnd_trace_data_traceoutportintf_o1; - output fabric_tnd_trace_data_traceoutportintf_o10; - output fabric_tnd_trace_data_traceoutportintf_o11; - output fabric_tnd_trace_data_traceoutportintf_o12; - output fabric_tnd_trace_data_traceoutportintf_o13; - output fabric_tnd_trace_data_traceoutportintf_o14; - output fabric_tnd_trace_data_traceoutportintf_o15; - output fabric_tnd_trace_data_traceoutportintf_o16; - output fabric_tnd_trace_data_traceoutportintf_o17; - output fabric_tnd_trace_data_traceoutportintf_o18; - output fabric_tnd_trace_data_traceoutportintf_o19; - output fabric_tnd_trace_data_traceoutportintf_o2; - output fabric_tnd_trace_data_traceoutportintf_o20; - output fabric_tnd_trace_data_traceoutportintf_o21; - output fabric_tnd_trace_data_traceoutportintf_o22; - output fabric_tnd_trace_data_traceoutportintf_o23; - output fabric_tnd_trace_data_traceoutportintf_o24; - output fabric_tnd_trace_data_traceoutportintf_o25; - output fabric_tnd_trace_data_traceoutportintf_o26; - output fabric_tnd_trace_data_traceoutportintf_o27; - output fabric_tnd_trace_data_traceoutportintf_o28; - output fabric_tnd_trace_data_traceoutportintf_o29; - output fabric_tnd_trace_data_traceoutportintf_o3; - output fabric_tnd_trace_data_traceoutportintf_o30; - output fabric_tnd_trace_data_traceoutportintf_o31; - output fabric_tnd_trace_data_traceoutportintf_o32; - output fabric_tnd_trace_data_traceoutportintf_o4; - output fabric_tnd_trace_data_traceoutportintf_o5; - output fabric_tnd_trace_data_traceoutportintf_o6; - output fabric_tnd_trace_data_traceoutportintf_o7; - output fabric_tnd_trace_data_traceoutportintf_o8; - output fabric_tnd_trace_data_traceoutportintf_o9; - output fabric_tst_pll_lock_o1; - output fabric_tst_pll_lock_o2; - output fabric_tst_pll_lock_o3; - output fabric_tst_pll_lock_o4; - output fabric_tst_pll_lock_o5; - output fabric_tst_pll_lock_o6; - output fabric_tst_pll_lock_o7; - output fabric_tsvalue_tsgen_fpga_o1; - output fabric_tsvalue_tsgen_fpga_o10; - output fabric_tsvalue_tsgen_fpga_o11; - output fabric_tsvalue_tsgen_fpga_o12; - output fabric_tsvalue_tsgen_fpga_o13; - output fabric_tsvalue_tsgen_fpga_o14; - output fabric_tsvalue_tsgen_fpga_o15; - output fabric_tsvalue_tsgen_fpga_o16; - output fabric_tsvalue_tsgen_fpga_o17; - output fabric_tsvalue_tsgen_fpga_o18; - output fabric_tsvalue_tsgen_fpga_o19; - output fabric_tsvalue_tsgen_fpga_o2; - output fabric_tsvalue_tsgen_fpga_o20; - output fabric_tsvalue_tsgen_fpga_o21; - output fabric_tsvalue_tsgen_fpga_o22; - output fabric_tsvalue_tsgen_fpga_o23; - output fabric_tsvalue_tsgen_fpga_o24; - output fabric_tsvalue_tsgen_fpga_o25; - output fabric_tsvalue_tsgen_fpga_o26; - output fabric_tsvalue_tsgen_fpga_o27; - output fabric_tsvalue_tsgen_fpga_o28; - output fabric_tsvalue_tsgen_fpga_o29; - output fabric_tsvalue_tsgen_fpga_o3; - output fabric_tsvalue_tsgen_fpga_o30; - output fabric_tsvalue_tsgen_fpga_o31; - output fabric_tsvalue_tsgen_fpga_o32; - output fabric_tsvalue_tsgen_fpga_o33; - output fabric_tsvalue_tsgen_fpga_o34; - output fabric_tsvalue_tsgen_fpga_o35; - output fabric_tsvalue_tsgen_fpga_o36; - output fabric_tsvalue_tsgen_fpga_o37; - output fabric_tsvalue_tsgen_fpga_o38; - output fabric_tsvalue_tsgen_fpga_o39; - output fabric_tsvalue_tsgen_fpga_o4; - output fabric_tsvalue_tsgen_fpga_o40; - output fabric_tsvalue_tsgen_fpga_o41; - output fabric_tsvalue_tsgen_fpga_o42; - output fabric_tsvalue_tsgen_fpga_o43; - output fabric_tsvalue_tsgen_fpga_o44; - output fabric_tsvalue_tsgen_fpga_o45; - output fabric_tsvalue_tsgen_fpga_o46; - output fabric_tsvalue_tsgen_fpga_o47; - output fabric_tsvalue_tsgen_fpga_o48; - output fabric_tsvalue_tsgen_fpga_o49; - output fabric_tsvalue_tsgen_fpga_o5; - output fabric_tsvalue_tsgen_fpga_o50; - output fabric_tsvalue_tsgen_fpga_o51; - output fabric_tsvalue_tsgen_fpga_o52; - output fabric_tsvalue_tsgen_fpga_o53; - output fabric_tsvalue_tsgen_fpga_o54; - output fabric_tsvalue_tsgen_fpga_o55; - output fabric_tsvalue_tsgen_fpga_o56; - output fabric_tsvalue_tsgen_fpga_o57; - output fabric_tsvalue_tsgen_fpga_o58; - output fabric_tsvalue_tsgen_fpga_o59; - output fabric_tsvalue_tsgen_fpga_o6; - output fabric_tsvalue_tsgen_fpga_o60; - output fabric_tsvalue_tsgen_fpga_o61; - output fabric_tsvalue_tsgen_fpga_o62; - output fabric_tsvalue_tsgen_fpga_o63; - output fabric_tsvalue_tsgen_fpga_o64; - output fabric_tsvalue_tsgen_fpga_o7; - output fabric_tsvalue_tsgen_fpga_o8; - output fabric_tsvalue_tsgen_fpga_o9; - output fabric_watchdog0_signal_0_o; - output fabric_watchdog0_signal_1_o; - output fabric_watchdog1_signal_0_o; - output fabric_watchdog1_signal_1_o; - output fabric_watchdog2_signal_0_o; - output fabric_watchdog2_signal_1_o; - output fabric_watchdog3_signal_0_o; - output fabric_watchdog3_signal_1_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SOC_INTERFACE_V1(fabric_lowskew_o1, fabric_lowskew_i1, fabric_lowskew_i2, fabric_lowskew_i3, fabric_lowskew_i4, fabric_lowskew_i5, fabric_lowskew_i6, fabric_lowskew_i7, fabric_lowskew_i8, fabric_lowskew_i9, fabric_lowskew_i10, fabric_lowskew_o2, fabric_fpga_nic_rstn_i1, fabric_fpga_nic_rstn_i2, fabric_fpga_nic_rstn_i3, fabric_fpga_nic_rstn_i4, fabric_fpga_nic_rstn_i5, fabric_fpga_nic_rstn_i6, fabric_fpga_nic_rstn_i7, fabric_fpga_nic_rstn_i8, fabric_fpga_nic_rstn_i9 -, fabric_fpga_nic_rstn_i10, fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_fpga_trigger_in_o1, fabric_fpga_trigger_in_o2, fabric_fpga_trigger_in_o3, fabric_fpga_trigger_in_o4, fabric_fpga_trigger_in_o5, fabric_fpga_trigger_in_o6, fabric_fpga_trigger_in_o7, fabric_fpga_trigger_in_o8, fabric_fpga_trigger_out_i1, fabric_fpga_trigger_out_i2, fabric_fpga_trigger_out_i3, fabric_fpga_trigger_out_i4, fabric_fpga_trigger_out_i5, fabric_fpga_trigger_out_i6, fabric_fpga_trigger_out_i7, fabric_fpga_trigger_out_i8, fabric_fpga_interrupt_in_i1, fabric_fpga_interrupt_in_i2 -, fabric_fpga_interrupt_in_i3, fabric_fpga_interrupt_in_i4, fabric_fpga_interrupt_in_i5, fabric_fpga_interrupt_in_i6, fabric_fpga_interrupt_in_i7, fabric_fpga_interrupt_in_i8, fabric_fpga_interrupt_in_i9, fabric_fpga_interrupt_in_i10, fabric_fpga_interrupt_in_i11, fabric_fpga_interrupt_in_i12, fabric_fpga_interrupt_in_i13, fabric_fpga_interrupt_in_i14, fabric_fpga_interrupt_in_i15, fabric_fpga_interrupt_in_i16, fabric_fpga_interrupt_in_i17, fabric_fpga_interrupt_in_i18, fabric_fpga_interrupt_in_i19, fabric_fpga_interrupt_in_i20, fabric_fpga_interrupt_in_i21, fabric_fpga_interrupt_in_i22, fabric_fpga_interrupt_in_i23 -, fabric_fpga_interrupt_in_i24, fabric_fpga_interrupt_in_i25, fabric_fpga_interrupt_in_i26, fabric_fpga_interrupt_in_i27, fabric_fpga_interrupt_in_i28, fabric_fpga_interrupt_in_i29, fabric_fpga_interrupt_in_i30, fabric_fpga_interrupt_in_i31, fabric_fpga_interrupt_in_i32, fabric_fpga_interrupt_in_i33, fabric_fpga_interrupt_in_i34, fabric_fpga_interrupt_in_i35, fabric_fpga_interrupt_in_i36, fabric_fpga_interrupt_in_i37, fabric_fpga_interrupt_in_i38, fabric_fpga_interrupt_in_i39, fabric_fpga_interrupt_in_i40, fabric_fpga_interrupt_in_i41, fabric_fpga_interrupt_in_i42, fabric_fpga_interrupt_in_i43, fabric_fpga_interrupt_in_i44 -, fabric_fpga_interrupt_in_i45, fabric_fpga_interrupt_in_i46, fabric_fpga_interrupt_in_i47, fabric_fpga_interrupt_in_i48, fabric_fpga_interrupt_in_i49, fabric_fpga_interrupt_in_i50, fabric_fpga_interrupt_in_i51, fabric_fpga_interrupt_in_i52, fabric_fpga_interrupt_in_i53, fabric_fpga_interrupt_in_i54, fabric_fpga_interrupt_in_i55, fabric_fpga_interrupt_in_i56, fabric_fpga_interrupt_in_i57, fabric_fpga_interrupt_in_i58, fabric_fpga_interrupt_in_i59, fabric_fpga_interrupt_in_i60, fabric_fpga_interrupt_in_i61, fabric_fpga_interrupt_in_i62, fabric_fpga_interrupt_in_i63, fabric_fpga_interrupt_in_i64, fabric_fpga_interrupt_in_i65 -, fabric_fpga_interrupt_in_i66, fabric_fpga_interrupt_in_i67, fabric_fpga_interrupt_in_i68, fabric_fpga_interrupt_in_i69, fabric_fpga_interrupt_in_i70, fabric_fpga_interrupt_in_i71, fabric_fpga_interrupt_in_i72, fabric_fpga_interrupt_in_i73, fabric_fpga_interrupt_in_i74, fabric_fpga_interrupt_in_i75, fabric_fpga_interrupt_in_i76, fabric_fpga_interrupt_in_i77, fabric_fpga_interrupt_in_i78, fabric_fpga_interrupt_in_i79, fabric_fpga_interrupt_in_i80, fabric_fpga_interrupt_in_i81, fabric_fpga_interrupt_in_i82, fabric_fpga_interrupt_in_i83, fabric_fpga_interrupt_in_i84, fabric_fpga_interrupt_in_i85, fabric_fpga_interrupt_in_i86 -, fabric_fpga_interrupt_in_i87, fabric_fpga_interrupt_in_i88, fabric_fpga_interrupt_in_i89, fabric_fpga_interrupt_in_i90, fabric_fpga_interrupt_in_i91, fabric_fpga_interrupt_in_i92, fabric_fpga_interrupt_in_i93, fabric_fpga_interrupt_in_i94, fabric_fpga_interrupt_in_i95, fabric_fpga_interrupt_in_i96, fabric_fpga_interrupt_in_i97, fabric_fpga_interrupt_in_i98, fabric_fpga_interrupt_in_i99, fabric_fpga_interrupt_in_i100, fabric_fpga_interrupt_in_i101, fabric_fpga_interrupt_in_i102, fabric_fpga_interrupt_in_i103, fabric_fpga_interrupt_in_i104, fabric_fpga_interrupt_in_i105, fabric_fpga_interrupt_in_i106, fabric_fpga_interrupt_in_i107 -, fabric_fpga_interrupt_in_i108, fabric_fpga_interrupt_in_i109, fabric_fpga_interrupt_in_i110, fabric_fpga_interrupt_in_i111, fabric_fpga_interrupt_in_i112, fabric_fpga_interrupt_in_i113, fabric_fpga_interrupt_in_i114, fabric_fpga_interrupt_in_i115, fabric_fpga_interrupt_in_i116, fabric_fpga_interrupt_in_i117, fabric_fpga_interrupt_in_i118, fabric_fpga_interrupt_in_i119, fabric_fpga_interrupt_in_i120, fabric_sysc_hold_on_debug_i, fabric_fpga_events60_i1, fabric_fpga_events60_i2, fabric_fpga_events60_i3, fabric_fpga_events60_i4, fabric_fpga_events60_i5, fabric_fpga_events60_i6, fabric_fpga_events60_i7 -, fabric_fpga_events60_i8, fabric_fpga_events60_i9, fabric_fpga_events60_i10, fabric_fpga_events60_i11, fabric_fpga_events60_i12, fabric_fpga_events60_i13, fabric_fpga_events60_i14, fabric_fpga_events60_i15, fabric_fpga_events60_i16, fabric_fpga_events60_i17, fabric_fpga_events60_i18, fabric_fpga_events60_i19, fabric_fpga_events60_i20, fabric_fpga_events60_i21, fabric_fpga_events60_i22, fabric_fpga_events60_i23, fabric_fpga_events60_i24, fabric_fpga_events60_i25, fabric_fpga_events60_i26, fabric_fpga_events60_i27, fabric_fpga_events60_i28 -, fabric_fpga_events60_i29, fabric_fpga_events60_i30, fabric_fpga_events60_i31, fabric_fpga_events60_i32, fabric_fpga_events60_i33, fabric_fpga_events60_i34, fabric_fpga_events60_i35, fabric_fpga_events60_i36, fabric_fpga_events60_i37, fabric_fpga_events60_i38, fabric_fpga_events60_i39, fabric_fpga_events60_i40, fabric_fpga_events60_i41, fabric_fpga_events60_i42, fabric_fpga_events60_i43, fabric_fpga_events60_i44, fabric_fpga_events60_i45, fabric_fpga_events60_i46, fabric_fpga_events60_i47, fabric_fpga_events60_i48, fabric_fpga_events60_i49 -, fabric_fpga_events60_i50, fabric_fpga_events60_i51, fabric_fpga_events60_i52, fabric_fpga_events60_i53, fabric_fpga_events60_i54, fabric_fpga_events60_i55, fabric_fpga_events60_i56, fabric_fpga_events60_i57, fabric_fpga_events60_i58, fabric_fpga_events60_i59, fabric_fpga_events60_i60, fabric_fpga_araddr_axi_s1_o1, fabric_fpga_araddr_axi_s1_o2, fabric_fpga_araddr_axi_s1_o3, fabric_fpga_araddr_axi_s1_o4, fabric_fpga_araddr_axi_s1_o5, fabric_fpga_araddr_axi_s1_o6, fabric_fpga_araddr_axi_s1_o7, fabric_fpga_araddr_axi_s1_o8, fabric_fpga_araddr_axi_s1_o9, fabric_fpga_araddr_axi_s1_o10 -, fabric_fpga_araddr_axi_s1_o11, fabric_fpga_araddr_axi_s1_o12, fabric_fpga_araddr_axi_s1_o13, fabric_fpga_araddr_axi_s1_o14, fabric_fpga_araddr_axi_s1_o15, fabric_fpga_araddr_axi_s1_o16, fabric_fpga_araddr_axi_s1_o17, fabric_fpga_araddr_axi_s1_o18, fabric_fpga_araddr_axi_s1_o19, fabric_fpga_araddr_axi_s1_o20, fabric_fpga_araddr_axi_s1_o21, fabric_fpga_araddr_axi_s1_o22, fabric_fpga_araddr_axi_s1_o23, fabric_fpga_araddr_axi_s1_o24, fabric_fpga_araddr_axi_s1_o25, fabric_fpga_araddr_axi_s1_o26, fabric_fpga_araddr_axi_s1_o27, fabric_fpga_araddr_axi_s1_o28, fabric_fpga_araddr_axi_s1_o29, fabric_fpga_araddr_axi_s1_o30, fabric_fpga_araddr_axi_s1_o31 -, fabric_fpga_araddr_axi_s1_o32, fabric_fpga_araddr_axi_s1_o33, fabric_fpga_araddr_axi_s1_o34, fabric_fpga_araddr_axi_s1_o35, fabric_fpga_araddr_axi_s1_o36, fabric_fpga_araddr_axi_s1_o37, fabric_fpga_araddr_axi_s1_o38, fabric_fpga_araddr_axi_s1_o39, fabric_fpga_araddr_axi_s1_o40, fabric_fpga_arburst_axi_s1_o1, fabric_fpga_arburst_axi_s1_o2, fabric_fpga_arcache_axi_s1_o1, fabric_fpga_arcache_axi_s1_o2, fabric_fpga_arcache_axi_s1_o3, fabric_fpga_arcache_axi_s1_o4, fabric_fpga_arid_axi_s1_o1, fabric_fpga_arid_axi_s1_o2, fabric_fpga_arid_axi_s1_o3, fabric_fpga_arid_axi_s1_o4, fabric_fpga_arid_axi_s1_o5, fabric_fpga_arid_axi_s1_o6 -, fabric_fpga_arid_axi_s1_o7, fabric_fpga_arid_axi_s1_o8, fabric_fpga_arid_axi_s1_o9, fabric_fpga_arid_axi_s1_o10, fabric_fpga_arid_axi_s1_o11, fabric_fpga_arid_axi_s1_o12, fabric_fpga_arlen_axi_s1_o1, fabric_fpga_arlen_axi_s1_o2, fabric_fpga_arlen_axi_s1_o3, fabric_fpga_arlen_axi_s1_o4, fabric_fpga_arlen_axi_s1_o5, fabric_fpga_arlen_axi_s1_o6, fabric_fpga_arlen_axi_s1_o7, fabric_fpga_arlen_axi_s1_o8, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arprot_axi_s1_o1, fabric_fpga_arprot_axi_s1_o2, fabric_fpga_arprot_axi_s1_o3, fabric_fpga_arqos_axi_s1_o1, fabric_fpga_arqos_axi_s1_o2, fabric_fpga_arqos_axi_s1_o3 -, fabric_fpga_arqos_axi_s1_o4, fabric_fpga_arregion_axi_s1_o1, fabric_fpga_arregion_axi_s1_o2, fabric_fpga_arregion_axi_s1_o3, fabric_fpga_arregion_axi_s1_o4, fabric_fpga_arsize_axi_s1_o1, fabric_fpga_arsize_axi_s1_o2, fabric_fpga_arsize_axi_s1_o3, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awaddr_axi_s1_o1, fabric_fpga_awaddr_axi_s1_o2, fabric_fpga_awaddr_axi_s1_o3, fabric_fpga_awaddr_axi_s1_o4, fabric_fpga_awaddr_axi_s1_o5, fabric_fpga_awaddr_axi_s1_o6, fabric_fpga_awaddr_axi_s1_o7, fabric_fpga_awaddr_axi_s1_o8, fabric_fpga_awaddr_axi_s1_o9, fabric_fpga_awaddr_axi_s1_o10, fabric_fpga_awaddr_axi_s1_o11, fabric_fpga_awaddr_axi_s1_o12 -, fabric_fpga_awaddr_axi_s1_o13, fabric_fpga_awaddr_axi_s1_o14, fabric_fpga_awaddr_axi_s1_o15, fabric_fpga_awaddr_axi_s1_o16, fabric_fpga_awaddr_axi_s1_o17, fabric_fpga_awaddr_axi_s1_o18, fabric_fpga_awaddr_axi_s1_o19, fabric_fpga_awaddr_axi_s1_o20, fabric_fpga_awaddr_axi_s1_o21, fabric_fpga_awaddr_axi_s1_o22, fabric_fpga_awaddr_axi_s1_o23, fabric_fpga_awaddr_axi_s1_o24, fabric_fpga_awaddr_axi_s1_o25, fabric_fpga_awaddr_axi_s1_o26, fabric_fpga_awaddr_axi_s1_o27, fabric_fpga_awaddr_axi_s1_o28, fabric_fpga_awaddr_axi_s1_o29, fabric_fpga_awaddr_axi_s1_o30, fabric_fpga_awaddr_axi_s1_o31, fabric_fpga_awaddr_axi_s1_o32, fabric_fpga_awaddr_axi_s1_o33 -, fabric_fpga_awaddr_axi_s1_o34, fabric_fpga_awaddr_axi_s1_o35, fabric_fpga_awaddr_axi_s1_o36, fabric_fpga_awaddr_axi_s1_o37, fabric_fpga_awaddr_axi_s1_o38, fabric_fpga_awaddr_axi_s1_o39, fabric_fpga_awaddr_axi_s1_o40, fabric_fpga_awburst_axi_s1_o1, fabric_fpga_awburst_axi_s1_o2, fabric_fpga_awcache_axi_s1_o1, fabric_fpga_awcache_axi_s1_o2, fabric_fpga_awcache_axi_s1_o3, fabric_fpga_awcache_axi_s1_o4, fabric_fpga_awid_axi_s1_o1, fabric_fpga_awid_axi_s1_o2, fabric_fpga_awid_axi_s1_o3, fabric_fpga_awid_axi_s1_o4, fabric_fpga_awid_axi_s1_o5, fabric_fpga_awid_axi_s1_o6, fabric_fpga_awid_axi_s1_o7, fabric_fpga_awid_axi_s1_o8 -, fabric_fpga_awid_axi_s1_o9, fabric_fpga_awid_axi_s1_o10, fabric_fpga_awid_axi_s1_o11, fabric_fpga_awid_axi_s1_o12, fabric_fpga_awlen_axi_s1_o1, fabric_fpga_awlen_axi_s1_o2, fabric_fpga_awlen_axi_s1_o3, fabric_fpga_awlen_axi_s1_o4, fabric_fpga_awlen_axi_s1_o5, fabric_fpga_awlen_axi_s1_o6, fabric_fpga_awlen_axi_s1_o7, fabric_fpga_awlen_axi_s1_o8, fabric_fpga_awlock_axi_s1_o, fabric_fpga_awprot_axi_s1_o1, fabric_fpga_awprot_axi_s1_o2, fabric_fpga_awprot_axi_s1_o3, fabric_fpga_awqos_axi_s1_o1, fabric_fpga_awqos_axi_s1_o2, fabric_fpga_awqos_axi_s1_o3, fabric_fpga_awqos_axi_s1_o4, fabric_fpga_awregion_axi_s1_o1 -, fabric_fpga_awregion_axi_s1_o2, fabric_fpga_awregion_axi_s1_o3, fabric_fpga_awregion_axi_s1_o4, fabric_fpga_awsize_axi_s1_o1, fabric_fpga_awsize_axi_s1_o2, fabric_fpga_awsize_axi_s1_o3, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wdata_axi_s1_o1, fabric_fpga_wdata_axi_s1_o2, fabric_fpga_wdata_axi_s1_o3, fabric_fpga_wdata_axi_s1_o4, fabric_fpga_wdata_axi_s1_o5, fabric_fpga_wdata_axi_s1_o6, fabric_fpga_wdata_axi_s1_o7, fabric_fpga_wdata_axi_s1_o8, fabric_fpga_wdata_axi_s1_o9, fabric_fpga_wdata_axi_s1_o10, fabric_fpga_wdata_axi_s1_o11, fabric_fpga_wdata_axi_s1_o12, fabric_fpga_wdata_axi_s1_o13 -, fabric_fpga_wdata_axi_s1_o14, fabric_fpga_wdata_axi_s1_o15, fabric_fpga_wdata_axi_s1_o16, fabric_fpga_wdata_axi_s1_o17, fabric_fpga_wdata_axi_s1_o18, fabric_fpga_wdata_axi_s1_o19, fabric_fpga_wdata_axi_s1_o20, fabric_fpga_wdata_axi_s1_o21, fabric_fpga_wdata_axi_s1_o22, fabric_fpga_wdata_axi_s1_o23, fabric_fpga_wdata_axi_s1_o24, fabric_fpga_wdata_axi_s1_o25, fabric_fpga_wdata_axi_s1_o26, fabric_fpga_wdata_axi_s1_o27, fabric_fpga_wdata_axi_s1_o28, fabric_fpga_wdata_axi_s1_o29, fabric_fpga_wdata_axi_s1_o30, fabric_fpga_wdata_axi_s1_o31, fabric_fpga_wdata_axi_s1_o32, fabric_fpga_wdata_axi_s1_o33, fabric_fpga_wdata_axi_s1_o34 -, fabric_fpga_wdata_axi_s1_o35, fabric_fpga_wdata_axi_s1_o36, fabric_fpga_wdata_axi_s1_o37, fabric_fpga_wdata_axi_s1_o38, fabric_fpga_wdata_axi_s1_o39, fabric_fpga_wdata_axi_s1_o40, fabric_fpga_wdata_axi_s1_o41, fabric_fpga_wdata_axi_s1_o42, fabric_fpga_wdata_axi_s1_o43, fabric_fpga_wdata_axi_s1_o44, fabric_fpga_wdata_axi_s1_o45, fabric_fpga_wdata_axi_s1_o46, fabric_fpga_wdata_axi_s1_o47, fabric_fpga_wdata_axi_s1_o48, fabric_fpga_wdata_axi_s1_o49, fabric_fpga_wdata_axi_s1_o50, fabric_fpga_wdata_axi_s1_o51, fabric_fpga_wdata_axi_s1_o52, fabric_fpga_wdata_axi_s1_o53, fabric_fpga_wdata_axi_s1_o54, fabric_fpga_wdata_axi_s1_o55 -, fabric_fpga_wdata_axi_s1_o56, fabric_fpga_wdata_axi_s1_o57, fabric_fpga_wdata_axi_s1_o58, fabric_fpga_wdata_axi_s1_o59, fabric_fpga_wdata_axi_s1_o60, fabric_fpga_wdata_axi_s1_o61, fabric_fpga_wdata_axi_s1_o62, fabric_fpga_wdata_axi_s1_o63, fabric_fpga_wdata_axi_s1_o64, fabric_fpga_wdata_axi_s1_o65, fabric_fpga_wdata_axi_s1_o66, fabric_fpga_wdata_axi_s1_o67, fabric_fpga_wdata_axi_s1_o68, fabric_fpga_wdata_axi_s1_o69, fabric_fpga_wdata_axi_s1_o70, fabric_fpga_wdata_axi_s1_o71, fabric_fpga_wdata_axi_s1_o72, fabric_fpga_wdata_axi_s1_o73, fabric_fpga_wdata_axi_s1_o74, fabric_fpga_wdata_axi_s1_o75, fabric_fpga_wdata_axi_s1_o76 -, fabric_fpga_wdata_axi_s1_o77, fabric_fpga_wdata_axi_s1_o78, fabric_fpga_wdata_axi_s1_o79, fabric_fpga_wdata_axi_s1_o80, fabric_fpga_wdata_axi_s1_o81, fabric_fpga_wdata_axi_s1_o82, fabric_fpga_wdata_axi_s1_o83, fabric_fpga_wdata_axi_s1_o84, fabric_fpga_wdata_axi_s1_o85, fabric_fpga_wdata_axi_s1_o86, fabric_fpga_wdata_axi_s1_o87, fabric_fpga_wdata_axi_s1_o88, fabric_fpga_wdata_axi_s1_o89, fabric_fpga_wdata_axi_s1_o90, fabric_fpga_wdata_axi_s1_o91, fabric_fpga_wdata_axi_s1_o92, fabric_fpga_wdata_axi_s1_o93, fabric_fpga_wdata_axi_s1_o94, fabric_fpga_wdata_axi_s1_o95, fabric_fpga_wdata_axi_s1_o96, fabric_fpga_wdata_axi_s1_o97 -, fabric_fpga_wdata_axi_s1_o98, fabric_fpga_wdata_axi_s1_o99, fabric_fpga_wdata_axi_s1_o100, fabric_fpga_wdata_axi_s1_o101, fabric_fpga_wdata_axi_s1_o102, fabric_fpga_wdata_axi_s1_o103, fabric_fpga_wdata_axi_s1_o104, fabric_fpga_wdata_axi_s1_o105, fabric_fpga_wdata_axi_s1_o106, fabric_fpga_wdata_axi_s1_o107, fabric_fpga_wdata_axi_s1_o108, fabric_fpga_wdata_axi_s1_o109, fabric_fpga_wdata_axi_s1_o110, fabric_fpga_wdata_axi_s1_o111, fabric_fpga_wdata_axi_s1_o112, fabric_fpga_wdata_axi_s1_o113, fabric_fpga_wdata_axi_s1_o114, fabric_fpga_wdata_axi_s1_o115, fabric_fpga_wdata_axi_s1_o116, fabric_fpga_wdata_axi_s1_o117, fabric_fpga_wdata_axi_s1_o118 -, fabric_fpga_wdata_axi_s1_o119, fabric_fpga_wdata_axi_s1_o120, fabric_fpga_wdata_axi_s1_o121, fabric_fpga_wdata_axi_s1_o122, fabric_fpga_wdata_axi_s1_o123, fabric_fpga_wdata_axi_s1_o124, fabric_fpga_wdata_axi_s1_o125, fabric_fpga_wdata_axi_s1_o126, fabric_fpga_wdata_axi_s1_o127, fabric_fpga_wdata_axi_s1_o128, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wstrb_axi_s1_o1, fabric_fpga_wstrb_axi_s1_o2, fabric_fpga_wstrb_axi_s1_o3, fabric_fpga_wstrb_axi_s1_o4, fabric_fpga_wstrb_axi_s1_o5, fabric_fpga_wstrb_axi_s1_o6, fabric_fpga_wstrb_axi_s1_o7, fabric_fpga_wstrb_axi_s1_o8, fabric_fpga_wstrb_axi_s1_o9, fabric_fpga_wstrb_axi_s1_o10 -, fabric_fpga_wstrb_axi_s1_o11, fabric_fpga_wstrb_axi_s1_o12, fabric_fpga_wstrb_axi_s1_o13, fabric_fpga_wstrb_axi_s1_o14, fabric_fpga_wstrb_axi_s1_o15, fabric_fpga_wstrb_axi_s1_o16, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bid_axi_s1_i1, fabric_fpga_bid_axi_s1_i2, fabric_fpga_bid_axi_s1_i3, fabric_fpga_bid_axi_s1_i4, fabric_fpga_bid_axi_s1_i5, fabric_fpga_bid_axi_s1_i6, fabric_fpga_bid_axi_s1_i7, fabric_fpga_bid_axi_s1_i8, fabric_fpga_bid_axi_s1_i9, fabric_fpga_bid_axi_s1_i10, fabric_fpga_bid_axi_s1_i11 -, fabric_fpga_bid_axi_s1_i12, fabric_fpga_bresp_axi_s1_i1, fabric_fpga_bresp_axi_s1_i2, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rdata_axi_s1_i1, fabric_fpga_rdata_axi_s1_i2, fabric_fpga_rdata_axi_s1_i3, fabric_fpga_rdata_axi_s1_i4, fabric_fpga_rdata_axi_s1_i5, fabric_fpga_rdata_axi_s1_i6, fabric_fpga_rdata_axi_s1_i7, fabric_fpga_rdata_axi_s1_i8, fabric_fpga_rdata_axi_s1_i9, fabric_fpga_rdata_axi_s1_i10, fabric_fpga_rdata_axi_s1_i11, fabric_fpga_rdata_axi_s1_i12, fabric_fpga_rdata_axi_s1_i13, fabric_fpga_rdata_axi_s1_i14, fabric_fpga_rdata_axi_s1_i15, fabric_fpga_rdata_axi_s1_i16, fabric_fpga_rdata_axi_s1_i17 -, fabric_fpga_rdata_axi_s1_i18, fabric_fpga_rdata_axi_s1_i19, fabric_fpga_rdata_axi_s1_i20, fabric_fpga_rdata_axi_s1_i21, fabric_fpga_rdata_axi_s1_i22, fabric_fpga_rdata_axi_s1_i23, fabric_fpga_rdata_axi_s1_i24, fabric_fpga_rdata_axi_s1_i25, fabric_fpga_rdata_axi_s1_i26, fabric_fpga_rdata_axi_s1_i27, fabric_fpga_rdata_axi_s1_i28, fabric_fpga_rdata_axi_s1_i29, fabric_fpga_rdata_axi_s1_i30, fabric_fpga_rdata_axi_s1_i31, fabric_fpga_rdata_axi_s1_i32, fabric_fpga_rdata_axi_s1_i33, fabric_fpga_rdata_axi_s1_i34, fabric_fpga_rdata_axi_s1_i35, fabric_fpga_rdata_axi_s1_i36, fabric_fpga_rdata_axi_s1_i37, fabric_fpga_rdata_axi_s1_i38 -, fabric_fpga_rdata_axi_s1_i39, fabric_fpga_rdata_axi_s1_i40, fabric_fpga_rdata_axi_s1_i41, fabric_fpga_rdata_axi_s1_i42, fabric_fpga_rdata_axi_s1_i43, fabric_fpga_rdata_axi_s1_i44, fabric_fpga_rdata_axi_s1_i45, fabric_fpga_rdata_axi_s1_i46, fabric_fpga_rdata_axi_s1_i47, fabric_fpga_rdata_axi_s1_i48, fabric_fpga_rdata_axi_s1_i49, fabric_fpga_rdata_axi_s1_i50, fabric_fpga_rdata_axi_s1_i51, fabric_fpga_rdata_axi_s1_i52, fabric_fpga_rdata_axi_s1_i53, fabric_fpga_rdata_axi_s1_i54, fabric_fpga_rdata_axi_s1_i55, fabric_fpga_rdata_axi_s1_i56, fabric_fpga_rdata_axi_s1_i57, fabric_fpga_rdata_axi_s1_i58, fabric_fpga_rdata_axi_s1_i59 -, fabric_fpga_rdata_axi_s1_i60, fabric_fpga_rdata_axi_s1_i61, fabric_fpga_rdata_axi_s1_i62, fabric_fpga_rdata_axi_s1_i63, fabric_fpga_rdata_axi_s1_i64, fabric_fpga_rdata_axi_s1_i65, fabric_fpga_rdata_axi_s1_i66, fabric_fpga_rdata_axi_s1_i67, fabric_fpga_rdata_axi_s1_i68, fabric_fpga_rdata_axi_s1_i69, fabric_fpga_rdata_axi_s1_i70, fabric_fpga_rdata_axi_s1_i71, fabric_fpga_rdata_axi_s1_i72, fabric_fpga_rdata_axi_s1_i73, fabric_fpga_rdata_axi_s1_i74, fabric_fpga_rdata_axi_s1_i75, fabric_fpga_rdata_axi_s1_i76, fabric_fpga_rdata_axi_s1_i77, fabric_fpga_rdata_axi_s1_i78, fabric_fpga_rdata_axi_s1_i79, fabric_fpga_rdata_axi_s1_i80 -, fabric_fpga_rdata_axi_s1_i81, fabric_fpga_rdata_axi_s1_i82, fabric_fpga_rdata_axi_s1_i83, fabric_fpga_rdata_axi_s1_i84, fabric_fpga_rdata_axi_s1_i85, fabric_fpga_rdata_axi_s1_i86, fabric_fpga_rdata_axi_s1_i87, fabric_fpga_rdata_axi_s1_i88, fabric_fpga_rdata_axi_s1_i89, fabric_fpga_rdata_axi_s1_i90, fabric_fpga_rdata_axi_s1_i91, fabric_fpga_rdata_axi_s1_i92, fabric_fpga_rdata_axi_s1_i93, fabric_fpga_rdata_axi_s1_i94, fabric_fpga_rdata_axi_s1_i95, fabric_fpga_rdata_axi_s1_i96, fabric_fpga_rdata_axi_s1_i97, fabric_fpga_rdata_axi_s1_i98, fabric_fpga_rdata_axi_s1_i99, fabric_fpga_rdata_axi_s1_i100, fabric_fpga_rdata_axi_s1_i101 -, fabric_fpga_rdata_axi_s1_i102, fabric_fpga_rdata_axi_s1_i103, fabric_fpga_rdata_axi_s1_i104, fabric_fpga_rdata_axi_s1_i105, fabric_fpga_rdata_axi_s1_i106, fabric_fpga_rdata_axi_s1_i107, fabric_fpga_rdata_axi_s1_i108, fabric_fpga_rdata_axi_s1_i109, fabric_fpga_rdata_axi_s1_i110, fabric_fpga_rdata_axi_s1_i111, fabric_fpga_rdata_axi_s1_i112, fabric_fpga_rdata_axi_s1_i113, fabric_fpga_rdata_axi_s1_i114, fabric_fpga_rdata_axi_s1_i115, fabric_fpga_rdata_axi_s1_i116, fabric_fpga_rdata_axi_s1_i117, fabric_fpga_rdata_axi_s1_i118, fabric_fpga_rdata_axi_s1_i119, fabric_fpga_rdata_axi_s1_i120, fabric_fpga_rdata_axi_s1_i121, fabric_fpga_rdata_axi_s1_i122 -, fabric_fpga_rdata_axi_s1_i123, fabric_fpga_rdata_axi_s1_i124, fabric_fpga_rdata_axi_s1_i125, fabric_fpga_rdata_axi_s1_i126, fabric_fpga_rdata_axi_s1_i127, fabric_fpga_rdata_axi_s1_i128, fabric_fpga_rid_axi_s1_i1, fabric_fpga_rid_axi_s1_i2, fabric_fpga_rid_axi_s1_i3, fabric_fpga_rid_axi_s1_i4, fabric_fpga_rid_axi_s1_i5, fabric_fpga_rid_axi_s1_i6, fabric_fpga_rid_axi_s1_i7, fabric_fpga_rid_axi_s1_i8, fabric_fpga_rid_axi_s1_i9, fabric_fpga_rid_axi_s1_i10, fabric_fpga_rid_axi_s1_i11, fabric_fpga_rid_axi_s1_i12, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rresp_axi_s1_i1, fabric_fpga_rresp_axi_s1_i2 -, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_araddr_axi_s2_o1, fabric_fpga_araddr_axi_s2_o2, fabric_fpga_araddr_axi_s2_o3, fabric_fpga_araddr_axi_s2_o4, fabric_fpga_araddr_axi_s2_o5, fabric_fpga_araddr_axi_s2_o6, fabric_fpga_araddr_axi_s2_o7, fabric_fpga_araddr_axi_s2_o8, fabric_fpga_araddr_axi_s2_o9, fabric_fpga_araddr_axi_s2_o10, fabric_fpga_araddr_axi_s2_o11, fabric_fpga_araddr_axi_s2_o12, fabric_fpga_araddr_axi_s2_o13, fabric_fpga_araddr_axi_s2_o14, fabric_fpga_araddr_axi_s2_o15, fabric_fpga_araddr_axi_s2_o16, fabric_fpga_araddr_axi_s2_o17, fabric_fpga_araddr_axi_s2_o18, fabric_fpga_araddr_axi_s2_o19 -, fabric_fpga_araddr_axi_s2_o20, fabric_fpga_araddr_axi_s2_o21, fabric_fpga_araddr_axi_s2_o22, fabric_fpga_araddr_axi_s2_o23, fabric_fpga_araddr_axi_s2_o24, fabric_fpga_araddr_axi_s2_o25, fabric_fpga_araddr_axi_s2_o26, fabric_fpga_araddr_axi_s2_o27, fabric_fpga_araddr_axi_s2_o28, fabric_fpga_araddr_axi_s2_o29, fabric_fpga_araddr_axi_s2_o30, fabric_fpga_araddr_axi_s2_o31, fabric_fpga_araddr_axi_s2_o32, fabric_fpga_araddr_axi_s2_o33, fabric_fpga_araddr_axi_s2_o34, fabric_fpga_araddr_axi_s2_o35, fabric_fpga_araddr_axi_s2_o36, fabric_fpga_araddr_axi_s2_o37, fabric_fpga_araddr_axi_s2_o38, fabric_fpga_araddr_axi_s2_o39, fabric_fpga_araddr_axi_s2_o40 -, fabric_fpga_arburst_axi_s2_o1, fabric_fpga_arburst_axi_s2_o2, fabric_fpga_arcache_axi_s2_o1, fabric_fpga_arcache_axi_s2_o2, fabric_fpga_arcache_axi_s2_o3, fabric_fpga_arcache_axi_s2_o4, fabric_fpga_arid_axi_s2_o1, fabric_fpga_arid_axi_s2_o2, fabric_fpga_arid_axi_s2_o3, fabric_fpga_arid_axi_s2_o4, fabric_fpga_arid_axi_s2_o5, fabric_fpga_arid_axi_s2_o6, fabric_fpga_arid_axi_s2_o7, fabric_fpga_arid_axi_s2_o8, fabric_fpga_arid_axi_s2_o9, fabric_fpga_arid_axi_s2_o10, fabric_fpga_arid_axi_s2_o11, fabric_fpga_arid_axi_s2_o12, fabric_fpga_arlen_axi_s2_o1, fabric_fpga_arlen_axi_s2_o2, fabric_fpga_arlen_axi_s2_o3 -, fabric_fpga_arlen_axi_s2_o4, fabric_fpga_arlen_axi_s2_o5, fabric_fpga_arlen_axi_s2_o6, fabric_fpga_arlen_axi_s2_o7, fabric_fpga_arlen_axi_s2_o8, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arprot_axi_s2_o1, fabric_fpga_arprot_axi_s2_o2, fabric_fpga_arprot_axi_s2_o3, fabric_fpga_arqos_axi_s2_o1, fabric_fpga_arqos_axi_s2_o2, fabric_fpga_arqos_axi_s2_o3, fabric_fpga_arqos_axi_s2_o4, fabric_fpga_arregion_axi_s2_o1, fabric_fpga_arregion_axi_s2_o2, fabric_fpga_arregion_axi_s2_o3, fabric_fpga_arregion_axi_s2_o4, fabric_fpga_arsize_axi_s2_o1, fabric_fpga_arsize_axi_s2_o2, fabric_fpga_arsize_axi_s2_o3, fabric_fpga_arvalid_axi_s2_o -, fabric_fpga_awaddr_axi_s2_o1, fabric_fpga_awaddr_axi_s2_o2, fabric_fpga_awaddr_axi_s2_o3, fabric_fpga_awaddr_axi_s2_o4, fabric_fpga_awaddr_axi_s2_o5, fabric_fpga_awaddr_axi_s2_o6, fabric_fpga_awaddr_axi_s2_o7, fabric_fpga_awaddr_axi_s2_o8, fabric_fpga_awaddr_axi_s2_o9, fabric_fpga_awaddr_axi_s2_o10, fabric_fpga_awaddr_axi_s2_o11, fabric_fpga_awaddr_axi_s2_o12, fabric_fpga_awaddr_axi_s2_o13, fabric_fpga_awaddr_axi_s2_o14, fabric_fpga_awaddr_axi_s2_o15, fabric_fpga_awaddr_axi_s2_o16, fabric_fpga_awaddr_axi_s2_o17, fabric_fpga_awaddr_axi_s2_o18, fabric_fpga_awaddr_axi_s2_o19, fabric_fpga_awaddr_axi_s2_o20, fabric_fpga_awaddr_axi_s2_o21 -, fabric_fpga_awaddr_axi_s2_o22, fabric_fpga_awaddr_axi_s2_o23, fabric_fpga_awaddr_axi_s2_o24, fabric_fpga_awaddr_axi_s2_o25, fabric_fpga_awaddr_axi_s2_o26, fabric_fpga_awaddr_axi_s2_o27, fabric_fpga_awaddr_axi_s2_o28, fabric_fpga_awaddr_axi_s2_o29, fabric_fpga_awaddr_axi_s2_o30, fabric_fpga_awaddr_axi_s2_o31, fabric_fpga_awaddr_axi_s2_o32, fabric_fpga_awaddr_axi_s2_o33, fabric_fpga_awaddr_axi_s2_o34, fabric_fpga_awaddr_axi_s2_o35, fabric_fpga_awaddr_axi_s2_o36, fabric_fpga_awaddr_axi_s2_o37, fabric_fpga_awaddr_axi_s2_o38, fabric_fpga_awaddr_axi_s2_o39, fabric_fpga_awaddr_axi_s2_o40, fabric_fpga_awburst_axi_s2_o1, fabric_fpga_awburst_axi_s2_o2 -, fabric_fpga_awcache_axi_s2_o1, fabric_fpga_awcache_axi_s2_o2, fabric_fpga_awcache_axi_s2_o3, fabric_fpga_awcache_axi_s2_o4, fabric_fpga_awid_axi_s2_o1, fabric_fpga_awid_axi_s2_o2, fabric_fpga_awid_axi_s2_o3, fabric_fpga_awid_axi_s2_o4, fabric_fpga_awid_axi_s2_o5, fabric_fpga_awid_axi_s2_o6, fabric_fpga_awid_axi_s2_o7, fabric_fpga_awid_axi_s2_o8, fabric_fpga_awid_axi_s2_o9, fabric_fpga_awid_axi_s2_o10, fabric_fpga_awid_axi_s2_o11, fabric_fpga_awid_axi_s2_o12, fabric_fpga_awlen_axi_s2_o1, fabric_fpga_awlen_axi_s2_o2, fabric_fpga_awlen_axi_s2_o3, fabric_fpga_awlen_axi_s2_o4, fabric_fpga_awlen_axi_s2_o5 -, fabric_fpga_awlen_axi_s2_o6, fabric_fpga_awlen_axi_s2_o7, fabric_fpga_awlen_axi_s2_o8, fabric_fpga_awlock_axi_s2_o, fabric_fpga_awprot_axi_s2_o1, fabric_fpga_awprot_axi_s2_o2, fabric_fpga_awprot_axi_s2_o3, fabric_fpga_awqos_axi_s2_o1, fabric_fpga_awqos_axi_s2_o2, fabric_fpga_awqos_axi_s2_o3, fabric_fpga_awqos_axi_s2_o4, fabric_fpga_awregion_axi_s2_o1, fabric_fpga_awregion_axi_s2_o2, fabric_fpga_awregion_axi_s2_o3, fabric_fpga_awregion_axi_s2_o4, fabric_fpga_awsize_axi_s2_o1, fabric_fpga_awsize_axi_s2_o2, fabric_fpga_awsize_axi_s2_o3, fabric_fpga_bready_axi_s2_o, fabric_fpga_rready_axi_s2_o, fabric_fpga_wdata_axi_s2_o1 -, fabric_fpga_wdata_axi_s2_o2, fabric_fpga_wdata_axi_s2_o3, fabric_fpga_wdata_axi_s2_o4, fabric_fpga_wdata_axi_s2_o5, fabric_fpga_wdata_axi_s2_o6, fabric_fpga_wdata_axi_s2_o7, fabric_fpga_wdata_axi_s2_o8, fabric_fpga_wdata_axi_s2_o9, fabric_fpga_wdata_axi_s2_o10, fabric_fpga_wdata_axi_s2_o11, fabric_fpga_wdata_axi_s2_o12, fabric_fpga_wdata_axi_s2_o13, fabric_fpga_wdata_axi_s2_o14, fabric_fpga_wdata_axi_s2_o15, fabric_fpga_wdata_axi_s2_o16, fabric_fpga_wdata_axi_s2_o17, fabric_fpga_wdata_axi_s2_o18, fabric_fpga_wdata_axi_s2_o19, fabric_fpga_wdata_axi_s2_o20, fabric_fpga_wdata_axi_s2_o21, fabric_fpga_wdata_axi_s2_o22 -, fabric_fpga_wdata_axi_s2_o23, fabric_fpga_wdata_axi_s2_o24, fabric_fpga_wdata_axi_s2_o25, fabric_fpga_wdata_axi_s2_o26, fabric_fpga_wdata_axi_s2_o27, fabric_fpga_wdata_axi_s2_o28, fabric_fpga_wdata_axi_s2_o29, fabric_fpga_wdata_axi_s2_o30, fabric_fpga_wdata_axi_s2_o31, fabric_fpga_wdata_axi_s2_o32, fabric_fpga_wdata_axi_s2_o33, fabric_fpga_wdata_axi_s2_o34, fabric_fpga_wdata_axi_s2_o35, fabric_fpga_wdata_axi_s2_o36, fabric_fpga_wdata_axi_s2_o37, fabric_fpga_wdata_axi_s2_o38, fabric_fpga_wdata_axi_s2_o39, fabric_fpga_wdata_axi_s2_o40, fabric_fpga_wdata_axi_s2_o41, fabric_fpga_wdata_axi_s2_o42, fabric_fpga_wdata_axi_s2_o43 -, fabric_fpga_wdata_axi_s2_o44, fabric_fpga_wdata_axi_s2_o45, fabric_fpga_wdata_axi_s2_o46, fabric_fpga_wdata_axi_s2_o47, fabric_fpga_wdata_axi_s2_o48, fabric_fpga_wdata_axi_s2_o49, fabric_fpga_wdata_axi_s2_o50, fabric_fpga_wdata_axi_s2_o51, fabric_fpga_wdata_axi_s2_o52, fabric_fpga_wdata_axi_s2_o53, fabric_fpga_wdata_axi_s2_o54, fabric_fpga_wdata_axi_s2_o55, fabric_fpga_wdata_axi_s2_o56, fabric_fpga_wdata_axi_s2_o57, fabric_fpga_wdata_axi_s2_o58, fabric_fpga_wdata_axi_s2_o59, fabric_fpga_wdata_axi_s2_o60, fabric_fpga_wdata_axi_s2_o61, fabric_fpga_wdata_axi_s2_o62, fabric_fpga_wdata_axi_s2_o63, fabric_fpga_wdata_axi_s2_o64 -, fabric_fpga_wdata_axi_s2_o65, fabric_fpga_wdata_axi_s2_o66, fabric_fpga_wdata_axi_s2_o67, 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fabric_fpga_rdata_axi_m1_o2, fabric_fpga_rdata_axi_m1_o3, fabric_fpga_rdata_axi_m1_o4, fabric_fpga_rdata_axi_m1_o5, fabric_fpga_rdata_axi_m1_o6 -, fabric_fpga_rdata_axi_m1_o7, fabric_fpga_rdata_axi_m1_o8, fabric_fpga_rdata_axi_m1_o9, fabric_fpga_rdata_axi_m1_o10, fabric_fpga_rdata_axi_m1_o11, fabric_fpga_rdata_axi_m1_o12, fabric_fpga_rdata_axi_m1_o13, fabric_fpga_rdata_axi_m1_o14, fabric_fpga_rdata_axi_m1_o15, fabric_fpga_rdata_axi_m1_o16, fabric_fpga_rdata_axi_m1_o17, fabric_fpga_rdata_axi_m1_o18, fabric_fpga_rdata_axi_m1_o19, fabric_fpga_rdata_axi_m1_o20, fabric_fpga_rdata_axi_m1_o21, fabric_fpga_rdata_axi_m1_o22, fabric_fpga_rdata_axi_m1_o23, fabric_fpga_rdata_axi_m1_o24, fabric_fpga_rdata_axi_m1_o25, fabric_fpga_rdata_axi_m1_o26, fabric_fpga_rdata_axi_m1_o27 -, fabric_fpga_rdata_axi_m1_o28, fabric_fpga_rdata_axi_m1_o29, fabric_fpga_rdata_axi_m1_o30, fabric_fpga_rdata_axi_m1_o31, fabric_fpga_rdata_axi_m1_o32, fabric_fpga_rdata_axi_m1_o33, fabric_fpga_rdata_axi_m1_o34, fabric_fpga_rdata_axi_m1_o35, fabric_fpga_rdata_axi_m1_o36, fabric_fpga_rdata_axi_m1_o37, fabric_fpga_rdata_axi_m1_o38, fabric_fpga_rdata_axi_m1_o39, fabric_fpga_rdata_axi_m1_o40, fabric_fpga_rdata_axi_m1_o41, fabric_fpga_rdata_axi_m1_o42, fabric_fpga_rdata_axi_m1_o43, fabric_fpga_rdata_axi_m1_o44, fabric_fpga_rdata_axi_m1_o45, fabric_fpga_rdata_axi_m1_o46, fabric_fpga_rdata_axi_m1_o47, fabric_fpga_rdata_axi_m1_o48 -, fabric_fpga_rdata_axi_m1_o49, fabric_fpga_rdata_axi_m1_o50, fabric_fpga_rdata_axi_m1_o51, fabric_fpga_rdata_axi_m1_o52, fabric_fpga_rdata_axi_m1_o53, fabric_fpga_rdata_axi_m1_o54, fabric_fpga_rdata_axi_m1_o55, fabric_fpga_rdata_axi_m1_o56, fabric_fpga_rdata_axi_m1_o57, fabric_fpga_rdata_axi_m1_o58, fabric_fpga_rdata_axi_m1_o59, fabric_fpga_rdata_axi_m1_o60, fabric_fpga_rdata_axi_m1_o61, fabric_fpga_rdata_axi_m1_o62, fabric_fpga_rdata_axi_m1_o63, fabric_fpga_rdata_axi_m1_o64, fabric_fpga_rdata_axi_m1_o65, fabric_fpga_rdata_axi_m1_o66, fabric_fpga_rdata_axi_m1_o67, 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fabric_fpga_rdata_axi_m1_o101, fabric_fpga_rdata_axi_m1_o102, fabric_fpga_rdata_axi_m1_o103, fabric_fpga_rdata_axi_m1_o104, fabric_fpga_rdata_axi_m1_o105, fabric_fpga_rdata_axi_m1_o106, fabric_fpga_rdata_axi_m1_o107, fabric_fpga_rdata_axi_m1_o108, fabric_fpga_rdata_axi_m1_o109, fabric_fpga_rdata_axi_m1_o110, fabric_fpga_rdata_axi_m1_o111 -, fabric_fpga_rdata_axi_m1_o112, fabric_fpga_rdata_axi_m1_o113, fabric_fpga_rdata_axi_m1_o114, fabric_fpga_rdata_axi_m1_o115, fabric_fpga_rdata_axi_m1_o116, fabric_fpga_rdata_axi_m1_o117, fabric_fpga_rdata_axi_m1_o118, fabric_fpga_rdata_axi_m1_o119, fabric_fpga_rdata_axi_m1_o120, fabric_fpga_rdata_axi_m1_o121, fabric_fpga_rdata_axi_m1_o122, fabric_fpga_rdata_axi_m1_o123, fabric_fpga_rdata_axi_m1_o124, fabric_fpga_rdata_axi_m1_o125, fabric_fpga_rdata_axi_m1_o126, fabric_fpga_rdata_axi_m1_o127, fabric_fpga_rdata_axi_m1_o128, fabric_fpga_rid_axi_m1_o1, fabric_fpga_rid_axi_m1_o2, fabric_fpga_rid_axi_m1_o3, fabric_fpga_rid_axi_m1_o4 -, fabric_fpga_rid_axi_m1_o5, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rresp_axi_m1_o1, fabric_fpga_rresp_axi_m1_o2, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_araddr_axi_m1_i1, fabric_fpga_araddr_axi_m1_i2, fabric_fpga_araddr_axi_m1_i3, fabric_fpga_araddr_axi_m1_i4, fabric_fpga_araddr_axi_m1_i5, fabric_fpga_araddr_axi_m1_i6, fabric_fpga_araddr_axi_m1_i7, fabric_fpga_araddr_axi_m1_i8, fabric_fpga_araddr_axi_m1_i9, fabric_fpga_araddr_axi_m1_i10, fabric_fpga_araddr_axi_m1_i11, fabric_fpga_araddr_axi_m1_i12, fabric_fpga_araddr_axi_m1_i13, fabric_fpga_araddr_axi_m1_i14, fabric_fpga_araddr_axi_m1_i15 -, fabric_fpga_araddr_axi_m1_i16, fabric_fpga_araddr_axi_m1_i17, fabric_fpga_araddr_axi_m1_i18, fabric_fpga_araddr_axi_m1_i19, fabric_fpga_araddr_axi_m1_i20, fabric_fpga_araddr_axi_m1_i21, fabric_fpga_araddr_axi_m1_i22, fabric_fpga_araddr_axi_m1_i23, fabric_fpga_araddr_axi_m1_i24, fabric_fpga_araddr_axi_m1_i25, fabric_fpga_araddr_axi_m1_i26, fabric_fpga_araddr_axi_m1_i27, fabric_fpga_araddr_axi_m1_i28, fabric_fpga_araddr_axi_m1_i29, fabric_fpga_araddr_axi_m1_i30, fabric_fpga_araddr_axi_m1_i31, fabric_fpga_araddr_axi_m1_i32, fabric_fpga_araddr_axi_m1_i33, fabric_fpga_araddr_axi_m1_i34, fabric_fpga_araddr_axi_m1_i35, fabric_fpga_araddr_axi_m1_i36 -, fabric_fpga_araddr_axi_m1_i37, fabric_fpga_araddr_axi_m1_i38, fabric_fpga_araddr_axi_m1_i39, fabric_fpga_araddr_axi_m1_i40, fabric_fpga_arburst_axi_m1_i1, fabric_fpga_arburst_axi_m1_i2, fabric_fpga_arcache_axi_m1_i1, fabric_fpga_arcache_axi_m1_i2, fabric_fpga_arcache_axi_m1_i3, fabric_fpga_arcache_axi_m1_i4, fabric_fpga_arid_axi_m1_i1, fabric_fpga_arid_axi_m1_i2, fabric_fpga_arid_axi_m1_i3, fabric_fpga_arid_axi_m1_i4, fabric_fpga_arid_axi_m1_i5, fabric_fpga_arlen_axi_m1_i1, fabric_fpga_arlen_axi_m1_i2, fabric_fpga_arlen_axi_m1_i3, fabric_fpga_arlen_axi_m1_i4, fabric_fpga_arlen_axi_m1_i5, fabric_fpga_arlen_axi_m1_i6 -, fabric_fpga_arlen_axi_m1_i7, fabric_fpga_arlen_axi_m1_i8, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arprot_axi_m1_i1, fabric_fpga_arprot_axi_m1_i2, fabric_fpga_arprot_axi_m1_i3, fabric_fpga_arqos_axi_m1_i1, fabric_fpga_arqos_axi_m1_i2, fabric_fpga_arqos_axi_m1_i3, fabric_fpga_arqos_axi_m1_i4, fabric_fpga_arsize_axi_m1_i1, fabric_fpga_arsize_axi_m1_i2, fabric_fpga_arsize_axi_m1_i3, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awaddr_axi_m1_i1, fabric_fpga_awaddr_axi_m1_i2, fabric_fpga_awaddr_axi_m1_i3, fabric_fpga_awaddr_axi_m1_i4, fabric_fpga_awaddr_axi_m1_i5, fabric_fpga_awaddr_axi_m1_i6, fabric_fpga_awaddr_axi_m1_i7 -, fabric_fpga_awaddr_axi_m1_i8, fabric_fpga_awaddr_axi_m1_i9, fabric_fpga_awaddr_axi_m1_i10, fabric_fpga_awaddr_axi_m1_i11, fabric_fpga_awaddr_axi_m1_i12, fabric_fpga_awaddr_axi_m1_i13, fabric_fpga_awaddr_axi_m1_i14, fabric_fpga_awaddr_axi_m1_i15, fabric_fpga_awaddr_axi_m1_i16, fabric_fpga_awaddr_axi_m1_i17, fabric_fpga_awaddr_axi_m1_i18, fabric_fpga_awaddr_axi_m1_i19, fabric_fpga_awaddr_axi_m1_i20, fabric_fpga_awaddr_axi_m1_i21, fabric_fpga_awaddr_axi_m1_i22, fabric_fpga_awaddr_axi_m1_i23, fabric_fpga_awaddr_axi_m1_i24, fabric_fpga_awaddr_axi_m1_i25, fabric_fpga_awaddr_axi_m1_i26, fabric_fpga_awaddr_axi_m1_i27, fabric_fpga_awaddr_axi_m1_i28 -, fabric_fpga_awaddr_axi_m1_i29, fabric_fpga_awaddr_axi_m1_i30, fabric_fpga_awaddr_axi_m1_i31, fabric_fpga_awaddr_axi_m1_i32, fabric_fpga_awaddr_axi_m1_i33, fabric_fpga_awaddr_axi_m1_i34, fabric_fpga_awaddr_axi_m1_i35, fabric_fpga_awaddr_axi_m1_i36, fabric_fpga_awaddr_axi_m1_i37, fabric_fpga_awaddr_axi_m1_i38, fabric_fpga_awaddr_axi_m1_i39, fabric_fpga_awaddr_axi_m1_i40, fabric_fpga_awburst_axi_m1_i1, fabric_fpga_awburst_axi_m1_i2, fabric_fpga_awcache_axi_m1_i1, fabric_fpga_awcache_axi_m1_i2, fabric_fpga_awcache_axi_m1_i3, fabric_fpga_awcache_axi_m1_i4, fabric_fpga_awid_axi_m1_i1, fabric_fpga_awid_axi_m1_i2, fabric_fpga_awid_axi_m1_i3 -, fabric_fpga_awid_axi_m1_i4, fabric_fpga_awid_axi_m1_i5, fabric_fpga_awlen_axi_m1_i1, fabric_fpga_awlen_axi_m1_i2, fabric_fpga_awlen_axi_m1_i3, fabric_fpga_awlen_axi_m1_i4, fabric_fpga_awlen_axi_m1_i5, fabric_fpga_awlen_axi_m1_i6, fabric_fpga_awlen_axi_m1_i7, fabric_fpga_awlen_axi_m1_i8, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awprot_axi_m1_i1, fabric_fpga_awprot_axi_m1_i2, fabric_fpga_awprot_axi_m1_i3, fabric_fpga_awqos_axi_m1_i1, fabric_fpga_awqos_axi_m1_i2, fabric_fpga_awqos_axi_m1_i3, fabric_fpga_awqos_axi_m1_i4, fabric_fpga_awsize_axi_m1_i1, fabric_fpga_awsize_axi_m1_i2, fabric_fpga_awsize_axi_m1_i3 -, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i, fabric_fpga_dma_last_m1_i1, fabric_fpga_dma_last_m1_i2, fabric_fpga_dma_last_m1_i3, fabric_fpga_dma_last_m1_i4, fabric_fpga_dma_last_m1_i5, fabric_fpga_dma_last_m1_i6, fabric_fpga_dma_req_m1_i1, fabric_fpga_dma_req_m1_i2, fabric_fpga_dma_req_m1_i3, fabric_fpga_dma_req_m1_i4, fabric_fpga_dma_req_m1_i5, fabric_fpga_dma_req_m1_i6, fabric_fpga_dma_single_m1_i1, fabric_fpga_dma_single_m1_i2, fabric_fpga_dma_single_m1_i3, fabric_fpga_dma_single_m1_i4, fabric_fpga_dma_single_m1_i5, fabric_fpga_dma_single_m1_i6, fabric_fpga_rready_axi_m1_i -, fabric_fpga_wdata_axi_m1_i1, fabric_fpga_wdata_axi_m1_i2, fabric_fpga_wdata_axi_m1_i3, fabric_fpga_wdata_axi_m1_i4, fabric_fpga_wdata_axi_m1_i5, fabric_fpga_wdata_axi_m1_i6, fabric_fpga_wdata_axi_m1_i7, fabric_fpga_wdata_axi_m1_i8, fabric_fpga_wdata_axi_m1_i9, fabric_fpga_wdata_axi_m1_i10, fabric_fpga_wdata_axi_m1_i11, fabric_fpga_wdata_axi_m1_i12, fabric_fpga_wdata_axi_m1_i13, fabric_fpga_wdata_axi_m1_i14, fabric_fpga_wdata_axi_m1_i15, fabric_fpga_wdata_axi_m1_i16, fabric_fpga_wdata_axi_m1_i17, fabric_fpga_wdata_axi_m1_i18, fabric_fpga_wdata_axi_m1_i19, fabric_fpga_wdata_axi_m1_i20, fabric_fpga_wdata_axi_m1_i21 -, fabric_fpga_wdata_axi_m1_i22, fabric_fpga_wdata_axi_m1_i23, fabric_fpga_wdata_axi_m1_i24, fabric_fpga_wdata_axi_m1_i25, fabric_fpga_wdata_axi_m1_i26, fabric_fpga_wdata_axi_m1_i27, fabric_fpga_wdata_axi_m1_i28, fabric_fpga_wdata_axi_m1_i29, fabric_fpga_wdata_axi_m1_i30, fabric_fpga_wdata_axi_m1_i31, fabric_fpga_wdata_axi_m1_i32, fabric_fpga_wdata_axi_m1_i33, fabric_fpga_wdata_axi_m1_i34, fabric_fpga_wdata_axi_m1_i35, fabric_fpga_wdata_axi_m1_i36, fabric_fpga_wdata_axi_m1_i37, fabric_fpga_wdata_axi_m1_i38, fabric_fpga_wdata_axi_m1_i39, fabric_fpga_wdata_axi_m1_i40, fabric_fpga_wdata_axi_m1_i41, fabric_fpga_wdata_axi_m1_i42 -, fabric_fpga_wdata_axi_m1_i43, fabric_fpga_wdata_axi_m1_i44, fabric_fpga_wdata_axi_m1_i45, fabric_fpga_wdata_axi_m1_i46, fabric_fpga_wdata_axi_m1_i47, fabric_fpga_wdata_axi_m1_i48, fabric_fpga_wdata_axi_m1_i49, fabric_fpga_wdata_axi_m1_i50, fabric_fpga_wdata_axi_m1_i51, fabric_fpga_wdata_axi_m1_i52, fabric_fpga_wdata_axi_m1_i53, fabric_fpga_wdata_axi_m1_i54, fabric_fpga_wdata_axi_m1_i55, fabric_fpga_wdata_axi_m1_i56, fabric_fpga_wdata_axi_m1_i57, fabric_fpga_wdata_axi_m1_i58, fabric_fpga_wdata_axi_m1_i59, fabric_fpga_wdata_axi_m1_i60, fabric_fpga_wdata_axi_m1_i61, fabric_fpga_wdata_axi_m1_i62, fabric_fpga_wdata_axi_m1_i63 -, fabric_fpga_wdata_axi_m1_i64, fabric_fpga_wdata_axi_m1_i65, fabric_fpga_wdata_axi_m1_i66, fabric_fpga_wdata_axi_m1_i67, fabric_fpga_wdata_axi_m1_i68, fabric_fpga_wdata_axi_m1_i69, fabric_fpga_wdata_axi_m1_i70, fabric_fpga_wdata_axi_m1_i71, fabric_fpga_wdata_axi_m1_i72, fabric_fpga_wdata_axi_m1_i73, fabric_fpga_wdata_axi_m1_i74, fabric_fpga_wdata_axi_m1_i75, fabric_fpga_wdata_axi_m1_i76, fabric_fpga_wdata_axi_m1_i77, fabric_fpga_wdata_axi_m1_i78, fabric_fpga_wdata_axi_m1_i79, fabric_fpga_wdata_axi_m1_i80, fabric_fpga_wdata_axi_m1_i81, fabric_fpga_wdata_axi_m1_i82, fabric_fpga_wdata_axi_m1_i83, fabric_fpga_wdata_axi_m1_i84 -, fabric_fpga_wdata_axi_m1_i85, fabric_fpga_wdata_axi_m1_i86, fabric_fpga_wdata_axi_m1_i87, fabric_fpga_wdata_axi_m1_i88, fabric_fpga_wdata_axi_m1_i89, fabric_fpga_wdata_axi_m1_i90, fabric_fpga_wdata_axi_m1_i91, fabric_fpga_wdata_axi_m1_i92, fabric_fpga_wdata_axi_m1_i93, fabric_fpga_wdata_axi_m1_i94, fabric_fpga_wdata_axi_m1_i95, fabric_fpga_wdata_axi_m1_i96, fabric_fpga_wdata_axi_m1_i97, fabric_fpga_wdata_axi_m1_i98, fabric_fpga_wdata_axi_m1_i99, fabric_fpga_wdata_axi_m1_i100, fabric_fpga_wdata_axi_m1_i101, fabric_fpga_wdata_axi_m1_i102, fabric_fpga_wdata_axi_m1_i103, fabric_fpga_wdata_axi_m1_i104, fabric_fpga_wdata_axi_m1_i105 -, fabric_fpga_wdata_axi_m1_i106, fabric_fpga_wdata_axi_m1_i107, fabric_fpga_wdata_axi_m1_i108, fabric_fpga_wdata_axi_m1_i109, fabric_fpga_wdata_axi_m1_i110, fabric_fpga_wdata_axi_m1_i111, fabric_fpga_wdata_axi_m1_i112, fabric_fpga_wdata_axi_m1_i113, fabric_fpga_wdata_axi_m1_i114, fabric_fpga_wdata_axi_m1_i115, fabric_fpga_wdata_axi_m1_i116, fabric_fpga_wdata_axi_m1_i117, fabric_fpga_wdata_axi_m1_i118, fabric_fpga_wdata_axi_m1_i119, fabric_fpga_wdata_axi_m1_i120, fabric_fpga_wdata_axi_m1_i121, fabric_fpga_wdata_axi_m1_i122, fabric_fpga_wdata_axi_m1_i123, fabric_fpga_wdata_axi_m1_i124, fabric_fpga_wdata_axi_m1_i125, fabric_fpga_wdata_axi_m1_i126 -, fabric_fpga_wdata_axi_m1_i127, fabric_fpga_wdata_axi_m1_i128, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wstrb_axi_m1_i1, fabric_fpga_wstrb_axi_m1_i2, fabric_fpga_wstrb_axi_m1_i3, fabric_fpga_wstrb_axi_m1_i4, fabric_fpga_wstrb_axi_m1_i5, fabric_fpga_wstrb_axi_m1_i6, fabric_fpga_wstrb_axi_m1_i7, fabric_fpga_wstrb_axi_m1_i8, fabric_fpga_wstrb_axi_m1_i9, fabric_fpga_wstrb_axi_m1_i10, fabric_fpga_wstrb_axi_m1_i11, fabric_fpga_wstrb_axi_m1_i12, fabric_fpga_wstrb_axi_m1_i13, fabric_fpga_wstrb_axi_m1_i14, fabric_fpga_wstrb_axi_m1_i15, fabric_fpga_wstrb_axi_m1_i16, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o -, fabric_fpga_awready_axi_m2_o, fabric_fpga_bid_axi_m2_o1, fabric_fpga_bid_axi_m2_o2, fabric_fpga_bid_axi_m2_o3, fabric_fpga_bid_axi_m2_o4, fabric_fpga_bid_axi_m2_o5, fabric_fpga_bresp_axi_m2_o1, fabric_fpga_bresp_axi_m2_o2, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_dma_ack_m2_o1, fabric_fpga_dma_ack_m2_o2, fabric_fpga_dma_ack_m2_o3, fabric_fpga_dma_ack_m2_o4, fabric_fpga_dma_ack_m2_o5, fabric_fpga_dma_ack_m2_o6, fabric_fpga_dma_finish_m2_o1, fabric_fpga_dma_finish_m2_o2, fabric_fpga_dma_finish_m2_o3, fabric_fpga_dma_finish_m2_o4, fabric_fpga_dma_finish_m2_o5, fabric_fpga_dma_finish_m2_o6 -, fabric_fpga_rdata_axi_m2_o1, fabric_fpga_rdata_axi_m2_o2, fabric_fpga_rdata_axi_m2_o3, fabric_fpga_rdata_axi_m2_o4, fabric_fpga_rdata_axi_m2_o5, fabric_fpga_rdata_axi_m2_o6, fabric_fpga_rdata_axi_m2_o7, fabric_fpga_rdata_axi_m2_o8, fabric_fpga_rdata_axi_m2_o9, fabric_fpga_rdata_axi_m2_o10, fabric_fpga_rdata_axi_m2_o11, fabric_fpga_rdata_axi_m2_o12, fabric_fpga_rdata_axi_m2_o13, fabric_fpga_rdata_axi_m2_o14, fabric_fpga_rdata_axi_m2_o15, fabric_fpga_rdata_axi_m2_o16, fabric_fpga_rdata_axi_m2_o17, fabric_fpga_rdata_axi_m2_o18, fabric_fpga_rdata_axi_m2_o19, fabric_fpga_rdata_axi_m2_o20, fabric_fpga_rdata_axi_m2_o21 -, fabric_fpga_rdata_axi_m2_o22, fabric_fpga_rdata_axi_m2_o23, fabric_fpga_rdata_axi_m2_o24, fabric_fpga_rdata_axi_m2_o25, fabric_fpga_rdata_axi_m2_o26, fabric_fpga_rdata_axi_m2_o27, fabric_fpga_rdata_axi_m2_o28, fabric_fpga_rdata_axi_m2_o29, fabric_fpga_rdata_axi_m2_o30, fabric_fpga_rdata_axi_m2_o31, fabric_fpga_rdata_axi_m2_o32, fabric_fpga_rdata_axi_m2_o33, fabric_fpga_rdata_axi_m2_o34, fabric_fpga_rdata_axi_m2_o35, fabric_fpga_rdata_axi_m2_o36, fabric_fpga_rdata_axi_m2_o37, fabric_fpga_rdata_axi_m2_o38, fabric_fpga_rdata_axi_m2_o39, fabric_fpga_rdata_axi_m2_o40, fabric_fpga_rdata_axi_m2_o41, fabric_fpga_rdata_axi_m2_o42 -, fabric_fpga_rdata_axi_m2_o43, fabric_fpga_rdata_axi_m2_o44, fabric_fpga_rdata_axi_m2_o45, fabric_fpga_rdata_axi_m2_o46, fabric_fpga_rdata_axi_m2_o47, fabric_fpga_rdata_axi_m2_o48, fabric_fpga_rdata_axi_m2_o49, fabric_fpga_rdata_axi_m2_o50, fabric_fpga_rdata_axi_m2_o51, fabric_fpga_rdata_axi_m2_o52, fabric_fpga_rdata_axi_m2_o53, fabric_fpga_rdata_axi_m2_o54, fabric_fpga_rdata_axi_m2_o55, fabric_fpga_rdata_axi_m2_o56, fabric_fpga_rdata_axi_m2_o57, fabric_fpga_rdata_axi_m2_o58, fabric_fpga_rdata_axi_m2_o59, fabric_fpga_rdata_axi_m2_o60, fabric_fpga_rdata_axi_m2_o61, fabric_fpga_rdata_axi_m2_o62, fabric_fpga_rdata_axi_m2_o63 -, fabric_fpga_rdata_axi_m2_o64, fabric_fpga_rdata_axi_m2_o65, fabric_fpga_rdata_axi_m2_o66, fabric_fpga_rdata_axi_m2_o67, fabric_fpga_rdata_axi_m2_o68, fabric_fpga_rdata_axi_m2_o69, fabric_fpga_rdata_axi_m2_o70, fabric_fpga_rdata_axi_m2_o71, fabric_fpga_rdata_axi_m2_o72, fabric_fpga_rdata_axi_m2_o73, fabric_fpga_rdata_axi_m2_o74, fabric_fpga_rdata_axi_m2_o75, fabric_fpga_rdata_axi_m2_o76, fabric_fpga_rdata_axi_m2_o77, fabric_fpga_rdata_axi_m2_o78, fabric_fpga_rdata_axi_m2_o79, fabric_fpga_rdata_axi_m2_o80, fabric_fpga_rdata_axi_m2_o81, fabric_fpga_rdata_axi_m2_o82, fabric_fpga_rdata_axi_m2_o83, fabric_fpga_rdata_axi_m2_o84 -, fabric_fpga_rdata_axi_m2_o85, fabric_fpga_rdata_axi_m2_o86, fabric_fpga_rdata_axi_m2_o87, fabric_fpga_rdata_axi_m2_o88, fabric_fpga_rdata_axi_m2_o89, fabric_fpga_rdata_axi_m2_o90, fabric_fpga_rdata_axi_m2_o91, fabric_fpga_rdata_axi_m2_o92, fabric_fpga_rdata_axi_m2_o93, fabric_fpga_rdata_axi_m2_o94, fabric_fpga_rdata_axi_m2_o95, fabric_fpga_rdata_axi_m2_o96, fabric_fpga_rdata_axi_m2_o97, fabric_fpga_rdata_axi_m2_o98, fabric_fpga_rdata_axi_m2_o99, fabric_fpga_rdata_axi_m2_o100, fabric_fpga_rdata_axi_m2_o101, fabric_fpga_rdata_axi_m2_o102, fabric_fpga_rdata_axi_m2_o103, fabric_fpga_rdata_axi_m2_o104, fabric_fpga_rdata_axi_m2_o105 -, fabric_fpga_rdata_axi_m2_o106, fabric_fpga_rdata_axi_m2_o107, fabric_fpga_rdata_axi_m2_o108, fabric_fpga_rdata_axi_m2_o109, fabric_fpga_rdata_axi_m2_o110, fabric_fpga_rdata_axi_m2_o111, fabric_fpga_rdata_axi_m2_o112, fabric_fpga_rdata_axi_m2_o113, fabric_fpga_rdata_axi_m2_o114, fabric_fpga_rdata_axi_m2_o115, fabric_fpga_rdata_axi_m2_o116, fabric_fpga_rdata_axi_m2_o117, fabric_fpga_rdata_axi_m2_o118, fabric_fpga_rdata_axi_m2_o119, fabric_fpga_rdata_axi_m2_o120, fabric_fpga_rdata_axi_m2_o121, fabric_fpga_rdata_axi_m2_o122, fabric_fpga_rdata_axi_m2_o123, fabric_fpga_rdata_axi_m2_o124, fabric_fpga_rdata_axi_m2_o125, fabric_fpga_rdata_axi_m2_o126 -, fabric_fpga_rdata_axi_m2_o127, fabric_fpga_rdata_axi_m2_o128, fabric_fpga_rid_axi_m2_o1, fabric_fpga_rid_axi_m2_o2, fabric_fpga_rid_axi_m2_o3, fabric_fpga_rid_axi_m2_o4, fabric_fpga_rid_axi_m2_o5, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rresp_axi_m2_o1, fabric_fpga_rresp_axi_m2_o2, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_araddr_axi_m2_i1, fabric_fpga_araddr_axi_m2_i2, fabric_fpga_araddr_axi_m2_i3, fabric_fpga_araddr_axi_m2_i4, fabric_fpga_araddr_axi_m2_i5, fabric_fpga_araddr_axi_m2_i6, fabric_fpga_araddr_axi_m2_i7, fabric_fpga_araddr_axi_m2_i8, fabric_fpga_araddr_axi_m2_i9 -, fabric_fpga_araddr_axi_m2_i10, fabric_fpga_araddr_axi_m2_i11, fabric_fpga_araddr_axi_m2_i12, fabric_fpga_araddr_axi_m2_i13, fabric_fpga_araddr_axi_m2_i14, fabric_fpga_araddr_axi_m2_i15, fabric_fpga_araddr_axi_m2_i16, fabric_fpga_araddr_axi_m2_i17, fabric_fpga_araddr_axi_m2_i18, fabric_fpga_araddr_axi_m2_i19, fabric_fpga_araddr_axi_m2_i20, fabric_fpga_araddr_axi_m2_i21, fabric_fpga_araddr_axi_m2_i22, fabric_fpga_araddr_axi_m2_i23, fabric_fpga_araddr_axi_m2_i24, fabric_fpga_araddr_axi_m2_i25, fabric_fpga_araddr_axi_m2_i26, fabric_fpga_araddr_axi_m2_i27, fabric_fpga_araddr_axi_m2_i28, fabric_fpga_araddr_axi_m2_i29, fabric_fpga_araddr_axi_m2_i30 -, fabric_fpga_araddr_axi_m2_i31, fabric_fpga_araddr_axi_m2_i32, fabric_fpga_araddr_axi_m2_i33, fabric_fpga_araddr_axi_m2_i34, fabric_fpga_araddr_axi_m2_i35, fabric_fpga_araddr_axi_m2_i36, fabric_fpga_araddr_axi_m2_i37, fabric_fpga_araddr_axi_m2_i38, fabric_fpga_araddr_axi_m2_i39, fabric_fpga_araddr_axi_m2_i40, fabric_fpga_arburst_axi_m2_i1, fabric_fpga_arburst_axi_m2_i2, fabric_fpga_arcache_axi_m2_i1, fabric_fpga_arcache_axi_m2_i2, fabric_fpga_arcache_axi_m2_i3, fabric_fpga_arcache_axi_m2_i4, fabric_fpga_arid_axi_m2_i1, fabric_fpga_arid_axi_m2_i2, fabric_fpga_arid_axi_m2_i3, fabric_fpga_arid_axi_m2_i4, fabric_fpga_arid_axi_m2_i5 -, fabric_fpga_arlen_axi_m2_i1, fabric_fpga_arlen_axi_m2_i2, fabric_fpga_arlen_axi_m2_i3, fabric_fpga_arlen_axi_m2_i4, fabric_fpga_arlen_axi_m2_i5, fabric_fpga_arlen_axi_m2_i6, fabric_fpga_arlen_axi_m2_i7, fabric_fpga_arlen_axi_m2_i8, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arprot_axi_m2_i1, fabric_fpga_arprot_axi_m2_i2, fabric_fpga_arprot_axi_m2_i3, fabric_fpga_arqos_axi_m2_i1, fabric_fpga_arqos_axi_m2_i2, fabric_fpga_arqos_axi_m2_i3, fabric_fpga_arqos_axi_m2_i4, fabric_fpga_arsize_axi_m2_i1, fabric_fpga_arsize_axi_m2_i2, fabric_fpga_arsize_axi_m2_i3, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awaddr_axi_m2_i1 -, fabric_fpga_awaddr_axi_m2_i2, fabric_fpga_awaddr_axi_m2_i3, fabric_fpga_awaddr_axi_m2_i4, fabric_fpga_awaddr_axi_m2_i5, fabric_fpga_awaddr_axi_m2_i6, fabric_fpga_awaddr_axi_m2_i7, fabric_fpga_awaddr_axi_m2_i8, fabric_fpga_awaddr_axi_m2_i9, fabric_fpga_awaddr_axi_m2_i10, fabric_fpga_awaddr_axi_m2_i11, fabric_fpga_awaddr_axi_m2_i12, fabric_fpga_awaddr_axi_m2_i13, fabric_fpga_awaddr_axi_m2_i14, fabric_fpga_awaddr_axi_m2_i15, fabric_fpga_awaddr_axi_m2_i16, fabric_fpga_awaddr_axi_m2_i17, fabric_fpga_awaddr_axi_m2_i18, fabric_fpga_awaddr_axi_m2_i19, fabric_fpga_awaddr_axi_m2_i20, fabric_fpga_awaddr_axi_m2_i21, fabric_fpga_awaddr_axi_m2_i22 -, fabric_fpga_awaddr_axi_m2_i23, fabric_fpga_awaddr_axi_m2_i24, fabric_fpga_awaddr_axi_m2_i25, fabric_fpga_awaddr_axi_m2_i26, fabric_fpga_awaddr_axi_m2_i27, fabric_fpga_awaddr_axi_m2_i28, fabric_fpga_awaddr_axi_m2_i29, fabric_fpga_awaddr_axi_m2_i30, fabric_fpga_awaddr_axi_m2_i31, fabric_fpga_awaddr_axi_m2_i32, fabric_fpga_awaddr_axi_m2_i33, fabric_fpga_awaddr_axi_m2_i34, fabric_fpga_awaddr_axi_m2_i35, fabric_fpga_awaddr_axi_m2_i36, fabric_fpga_awaddr_axi_m2_i37, fabric_fpga_awaddr_axi_m2_i38, fabric_fpga_awaddr_axi_m2_i39, fabric_fpga_awaddr_axi_m2_i40, fabric_fpga_awburst_axi_m2_i1, fabric_fpga_awburst_axi_m2_i2, fabric_fpga_awcache_axi_m2_i1 -, fabric_fpga_awcache_axi_m2_i2, fabric_fpga_awcache_axi_m2_i3, fabric_fpga_awcache_axi_m2_i4, fabric_fpga_awid_axi_m2_i1, fabric_fpga_awid_axi_m2_i2, fabric_fpga_awid_axi_m2_i3, fabric_fpga_awid_axi_m2_i4, fabric_fpga_awid_axi_m2_i5, fabric_fpga_awlen_axi_m2_i1, fabric_fpga_awlen_axi_m2_i2, fabric_fpga_awlen_axi_m2_i3, fabric_fpga_awlen_axi_m2_i4, fabric_fpga_awlen_axi_m2_i5, fabric_fpga_awlen_axi_m2_i6, fabric_fpga_awlen_axi_m2_i7, fabric_fpga_awlen_axi_m2_i8, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awprot_axi_m2_i1, fabric_fpga_awprot_axi_m2_i2, fabric_fpga_awprot_axi_m2_i3, fabric_fpga_awqos_axi_m2_i1 -, fabric_fpga_awqos_axi_m2_i2, fabric_fpga_awqos_axi_m2_i3, fabric_fpga_awqos_axi_m2_i4, fabric_fpga_awsize_axi_m2_i1, fabric_fpga_awsize_axi_m2_i2, fabric_fpga_awsize_axi_m2_i3, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_dma_last_m2_i1, fabric_fpga_dma_last_m2_i2, fabric_fpga_dma_last_m2_i3, fabric_fpga_dma_last_m2_i4, fabric_fpga_dma_last_m2_i5, fabric_fpga_dma_last_m2_i6, fabric_fpga_dma_req_m2_i1, fabric_fpga_dma_req_m2_i2, fabric_fpga_dma_req_m2_i3, fabric_fpga_dma_req_m2_i4, fabric_fpga_dma_req_m2_i5, fabric_fpga_dma_req_m2_i6, fabric_fpga_dma_single_m2_i1 -, fabric_fpga_dma_single_m2_i2, fabric_fpga_dma_single_m2_i3, fabric_fpga_dma_single_m2_i4, fabric_fpga_dma_single_m2_i5, fabric_fpga_dma_single_m2_i6, fabric_fpga_rready_axi_m2_i, fabric_fpga_wdata_axi_m2_i1, fabric_fpga_wdata_axi_m2_i2, fabric_fpga_wdata_axi_m2_i3, fabric_fpga_wdata_axi_m2_i4, fabric_fpga_wdata_axi_m2_i5, fabric_fpga_wdata_axi_m2_i6, fabric_fpga_wdata_axi_m2_i7, fabric_fpga_wdata_axi_m2_i8, fabric_fpga_wdata_axi_m2_i9, fabric_fpga_wdata_axi_m2_i10, fabric_fpga_wdata_axi_m2_i11, fabric_fpga_wdata_axi_m2_i12, fabric_fpga_wdata_axi_m2_i13, fabric_fpga_wdata_axi_m2_i14, fabric_fpga_wdata_axi_m2_i15 -, fabric_fpga_wdata_axi_m2_i16, fabric_fpga_wdata_axi_m2_i17, fabric_fpga_wdata_axi_m2_i18, fabric_fpga_wdata_axi_m2_i19, fabric_fpga_wdata_axi_m2_i20, fabric_fpga_wdata_axi_m2_i21, fabric_fpga_wdata_axi_m2_i22, fabric_fpga_wdata_axi_m2_i23, fabric_fpga_wdata_axi_m2_i24, fabric_fpga_wdata_axi_m2_i25, fabric_fpga_wdata_axi_m2_i26, fabric_fpga_wdata_axi_m2_i27, fabric_fpga_wdata_axi_m2_i28, fabric_fpga_wdata_axi_m2_i29, fabric_fpga_wdata_axi_m2_i30, fabric_fpga_wdata_axi_m2_i31, fabric_fpga_wdata_axi_m2_i32, fabric_fpga_wdata_axi_m2_i33, fabric_fpga_wdata_axi_m2_i34, fabric_fpga_wdata_axi_m2_i35, fabric_fpga_wdata_axi_m2_i36 -, fabric_fpga_wdata_axi_m2_i37, fabric_fpga_wdata_axi_m2_i38, fabric_fpga_wdata_axi_m2_i39, fabric_fpga_wdata_axi_m2_i40, fabric_fpga_wdata_axi_m2_i41, fabric_fpga_wdata_axi_m2_i42, fabric_fpga_wdata_axi_m2_i43, fabric_fpga_wdata_axi_m2_i44, fabric_fpga_wdata_axi_m2_i45, fabric_fpga_wdata_axi_m2_i46, fabric_fpga_wdata_axi_m2_i47, fabric_fpga_wdata_axi_m2_i48, fabric_fpga_wdata_axi_m2_i49, fabric_fpga_wdata_axi_m2_i50, fabric_fpga_wdata_axi_m2_i51, fabric_fpga_wdata_axi_m2_i52, fabric_fpga_wdata_axi_m2_i53, fabric_fpga_wdata_axi_m2_i54, fabric_fpga_wdata_axi_m2_i55, fabric_fpga_wdata_axi_m2_i56, fabric_fpga_wdata_axi_m2_i57 -, fabric_fpga_wdata_axi_m2_i58, fabric_fpga_wdata_axi_m2_i59, fabric_fpga_wdata_axi_m2_i60, fabric_fpga_wdata_axi_m2_i61, fabric_fpga_wdata_axi_m2_i62, fabric_fpga_wdata_axi_m2_i63, fabric_fpga_wdata_axi_m2_i64, fabric_fpga_wdata_axi_m2_i65, fabric_fpga_wdata_axi_m2_i66, fabric_fpga_wdata_axi_m2_i67, fabric_fpga_wdata_axi_m2_i68, fabric_fpga_wdata_axi_m2_i69, fabric_fpga_wdata_axi_m2_i70, fabric_fpga_wdata_axi_m2_i71, fabric_fpga_wdata_axi_m2_i72, fabric_fpga_wdata_axi_m2_i73, fabric_fpga_wdata_axi_m2_i74, fabric_fpga_wdata_axi_m2_i75, fabric_fpga_wdata_axi_m2_i76, fabric_fpga_wdata_axi_m2_i77, fabric_fpga_wdata_axi_m2_i78 -, fabric_fpga_wdata_axi_m2_i79, fabric_fpga_wdata_axi_m2_i80, fabric_fpga_wdata_axi_m2_i81, fabric_fpga_wdata_axi_m2_i82, fabric_fpga_wdata_axi_m2_i83, fabric_fpga_wdata_axi_m2_i84, fabric_fpga_wdata_axi_m2_i85, fabric_fpga_wdata_axi_m2_i86, fabric_fpga_wdata_axi_m2_i87, fabric_fpga_wdata_axi_m2_i88, fabric_fpga_wdata_axi_m2_i89, fabric_fpga_wdata_axi_m2_i90, fabric_fpga_wdata_axi_m2_i91, fabric_fpga_wdata_axi_m2_i92, fabric_fpga_wdata_axi_m2_i93, fabric_fpga_wdata_axi_m2_i94, fabric_fpga_wdata_axi_m2_i95, fabric_fpga_wdata_axi_m2_i96, fabric_fpga_wdata_axi_m2_i97, fabric_fpga_wdata_axi_m2_i98, fabric_fpga_wdata_axi_m2_i99 -, fabric_fpga_wdata_axi_m2_i100, fabric_fpga_wdata_axi_m2_i101, fabric_fpga_wdata_axi_m2_i102, fabric_fpga_wdata_axi_m2_i103, fabric_fpga_wdata_axi_m2_i104, fabric_fpga_wdata_axi_m2_i105, fabric_fpga_wdata_axi_m2_i106, fabric_fpga_wdata_axi_m2_i107, fabric_fpga_wdata_axi_m2_i108, fabric_fpga_wdata_axi_m2_i109, fabric_fpga_wdata_axi_m2_i110, fabric_fpga_wdata_axi_m2_i111, fabric_fpga_wdata_axi_m2_i112, fabric_fpga_wdata_axi_m2_i113, fabric_fpga_wdata_axi_m2_i114, fabric_fpga_wdata_axi_m2_i115, fabric_fpga_wdata_axi_m2_i116, fabric_fpga_wdata_axi_m2_i117, fabric_fpga_wdata_axi_m2_i118, fabric_fpga_wdata_axi_m2_i119, fabric_fpga_wdata_axi_m2_i120 -, fabric_fpga_wdata_axi_m2_i121, fabric_fpga_wdata_axi_m2_i122, fabric_fpga_wdata_axi_m2_i123, fabric_fpga_wdata_axi_m2_i124, fabric_fpga_wdata_axi_m2_i125, fabric_fpga_wdata_axi_m2_i126, fabric_fpga_wdata_axi_m2_i127, fabric_fpga_wdata_axi_m2_i128, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wstrb_axi_m2_i1, fabric_fpga_wstrb_axi_m2_i2, fabric_fpga_wstrb_axi_m2_i3, fabric_fpga_wstrb_axi_m2_i4, fabric_fpga_wstrb_axi_m2_i5, fabric_fpga_wstrb_axi_m2_i6, fabric_fpga_wstrb_axi_m2_i7, fabric_fpga_wstrb_axi_m2_i8, fabric_fpga_wstrb_axi_m2_i9, fabric_fpga_wstrb_axi_m2_i10, fabric_fpga_wstrb_axi_m2_i11, fabric_fpga_wstrb_axi_m2_i12 -, fabric_fpga_wstrb_axi_m2_i13, fabric_fpga_wstrb_axi_m2_i14, fabric_fpga_wstrb_axi_m2_i15, fabric_fpga_wstrb_axi_m2_i16, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bid_o1, fabric_fpga_ddr0_bid_o2, fabric_fpga_ddr0_bid_o3, fabric_fpga_ddr0_bid_o4, fabric_fpga_ddr0_bid_o5, fabric_fpga_ddr0_bresp_o1, fabric_fpga_ddr0_bresp_o2, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rdata_o1, fabric_fpga_ddr0_rdata_o2, fabric_fpga_ddr0_rdata_o3, fabric_fpga_ddr0_rdata_o4, fabric_fpga_ddr0_rdata_o5, fabric_fpga_ddr0_rdata_o6 -, fabric_fpga_ddr0_rdata_o7, fabric_fpga_ddr0_rdata_o8, fabric_fpga_ddr0_rdata_o9, fabric_fpga_ddr0_rdata_o10, fabric_fpga_ddr0_rdata_o11, fabric_fpga_ddr0_rdata_o12, fabric_fpga_ddr0_rdata_o13, fabric_fpga_ddr0_rdata_o14, fabric_fpga_ddr0_rdata_o15, fabric_fpga_ddr0_rdata_o16, fabric_fpga_ddr0_rdata_o17, fabric_fpga_ddr0_rdata_o18, fabric_fpga_ddr0_rdata_o19, fabric_fpga_ddr0_rdata_o20, fabric_fpga_ddr0_rdata_o21, fabric_fpga_ddr0_rdata_o22, fabric_fpga_ddr0_rdata_o23, fabric_fpga_ddr0_rdata_o24, fabric_fpga_ddr0_rdata_o25, fabric_fpga_ddr0_rdata_o26, fabric_fpga_ddr0_rdata_o27 -, fabric_fpga_ddr0_rdata_o28, fabric_fpga_ddr0_rdata_o29, fabric_fpga_ddr0_rdata_o30, fabric_fpga_ddr0_rdata_o31, fabric_fpga_ddr0_rdata_o32, fabric_fpga_ddr0_rdata_o33, fabric_fpga_ddr0_rdata_o34, fabric_fpga_ddr0_rdata_o35, fabric_fpga_ddr0_rdata_o36, fabric_fpga_ddr0_rdata_o37, fabric_fpga_ddr0_rdata_o38, fabric_fpga_ddr0_rdata_o39, fabric_fpga_ddr0_rdata_o40, fabric_fpga_ddr0_rdata_o41, fabric_fpga_ddr0_rdata_o42, fabric_fpga_ddr0_rdata_o43, fabric_fpga_ddr0_rdata_o44, fabric_fpga_ddr0_rdata_o45, fabric_fpga_ddr0_rdata_o46, fabric_fpga_ddr0_rdata_o47, fabric_fpga_ddr0_rdata_o48 -, fabric_fpga_ddr0_rdata_o49, fabric_fpga_ddr0_rdata_o50, fabric_fpga_ddr0_rdata_o51, fabric_fpga_ddr0_rdata_o52, fabric_fpga_ddr0_rdata_o53, fabric_fpga_ddr0_rdata_o54, fabric_fpga_ddr0_rdata_o55, fabric_fpga_ddr0_rdata_o56, fabric_fpga_ddr0_rdata_o57, fabric_fpga_ddr0_rdata_o58, fabric_fpga_ddr0_rdata_o59, fabric_fpga_ddr0_rdata_o60, fabric_fpga_ddr0_rdata_o61, fabric_fpga_ddr0_rdata_o62, fabric_fpga_ddr0_rdata_o63, fabric_fpga_ddr0_rdata_o64, fabric_fpga_ddr0_rdata_o65, fabric_fpga_ddr0_rdata_o66, fabric_fpga_ddr0_rdata_o67, fabric_fpga_ddr0_rdata_o68, fabric_fpga_ddr0_rdata_o69 -, fabric_fpga_ddr0_rdata_o70, fabric_fpga_ddr0_rdata_o71, fabric_fpga_ddr0_rdata_o72, fabric_fpga_ddr0_rdata_o73, fabric_fpga_ddr0_rdata_o74, fabric_fpga_ddr0_rdata_o75, fabric_fpga_ddr0_rdata_o76, fabric_fpga_ddr0_rdata_o77, fabric_fpga_ddr0_rdata_o78, fabric_fpga_ddr0_rdata_o79, fabric_fpga_ddr0_rdata_o80, fabric_fpga_ddr0_rdata_o81, fabric_fpga_ddr0_rdata_o82, fabric_fpga_ddr0_rdata_o83, fabric_fpga_ddr0_rdata_o84, fabric_fpga_ddr0_rdata_o85, fabric_fpga_ddr0_rdata_o86, fabric_fpga_ddr0_rdata_o87, fabric_fpga_ddr0_rdata_o88, fabric_fpga_ddr0_rdata_o89, fabric_fpga_ddr0_rdata_o90 -, fabric_fpga_ddr0_rdata_o91, fabric_fpga_ddr0_rdata_o92, fabric_fpga_ddr0_rdata_o93, fabric_fpga_ddr0_rdata_o94, fabric_fpga_ddr0_rdata_o95, fabric_fpga_ddr0_rdata_o96, fabric_fpga_ddr0_rdata_o97, fabric_fpga_ddr0_rdata_o98, fabric_fpga_ddr0_rdata_o99, fabric_fpga_ddr0_rdata_o100, fabric_fpga_ddr0_rdata_o101, fabric_fpga_ddr0_rdata_o102, fabric_fpga_ddr0_rdata_o103, fabric_fpga_ddr0_rdata_o104, fabric_fpga_ddr0_rdata_o105, fabric_fpga_ddr0_rdata_o106, fabric_fpga_ddr0_rdata_o107, fabric_fpga_ddr0_rdata_o108, fabric_fpga_ddr0_rdata_o109, fabric_fpga_ddr0_rdata_o110, fabric_fpga_ddr0_rdata_o111 -, fabric_fpga_ddr0_rdata_o112, fabric_fpga_ddr0_rdata_o113, fabric_fpga_ddr0_rdata_o114, fabric_fpga_ddr0_rdata_o115, fabric_fpga_ddr0_rdata_o116, fabric_fpga_ddr0_rdata_o117, fabric_fpga_ddr0_rdata_o118, fabric_fpga_ddr0_rdata_o119, fabric_fpga_ddr0_rdata_o120, fabric_fpga_ddr0_rdata_o121, fabric_fpga_ddr0_rdata_o122, fabric_fpga_ddr0_rdata_o123, fabric_fpga_ddr0_rdata_o124, fabric_fpga_ddr0_rdata_o125, fabric_fpga_ddr0_rdata_o126, fabric_fpga_ddr0_rdata_o127, fabric_fpga_ddr0_rdata_o128, fabric_fpga_ddr0_rid_o1, fabric_fpga_ddr0_rid_o2, fabric_fpga_ddr0_rid_o3, fabric_fpga_ddr0_rid_o4 -, fabric_fpga_ddr0_rid_o5, fabric_fpga_ddr0_rlast_o, fabric_fpga_ddr0_rresp_o1, fabric_fpga_ddr0_rresp_o2, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_araddr_i1, fabric_fpga_ddr0_araddr_i2, fabric_fpga_ddr0_araddr_i3, fabric_fpga_ddr0_araddr_i4, fabric_fpga_ddr0_araddr_i5, fabric_fpga_ddr0_araddr_i6, fabric_fpga_ddr0_araddr_i7, fabric_fpga_ddr0_araddr_i8, fabric_fpga_ddr0_araddr_i9, fabric_fpga_ddr0_araddr_i10, fabric_fpga_ddr0_araddr_i11, fabric_fpga_ddr0_araddr_i12, fabric_fpga_ddr0_araddr_i13, fabric_fpga_ddr0_araddr_i14, fabric_fpga_ddr0_araddr_i15 -, fabric_fpga_ddr0_araddr_i16, fabric_fpga_ddr0_araddr_i17, fabric_fpga_ddr0_araddr_i18, fabric_fpga_ddr0_araddr_i19, fabric_fpga_ddr0_araddr_i20, fabric_fpga_ddr0_araddr_i21, fabric_fpga_ddr0_araddr_i22, fabric_fpga_ddr0_araddr_i23, fabric_fpga_ddr0_araddr_i24, fabric_fpga_ddr0_araddr_i25, fabric_fpga_ddr0_araddr_i26, fabric_fpga_ddr0_araddr_i27, fabric_fpga_ddr0_araddr_i28, fabric_fpga_ddr0_araddr_i29, fabric_fpga_ddr0_araddr_i30, fabric_fpga_ddr0_araddr_i31, fabric_fpga_ddr0_araddr_i32, fabric_fpga_ddr0_araddr_i33, fabric_fpga_ddr0_araddr_i34, fabric_fpga_ddr0_araddr_i35, fabric_fpga_ddr0_araddr_i36 -, fabric_fpga_ddr0_araddr_i37, fabric_fpga_ddr0_araddr_i38, fabric_fpga_ddr0_araddr_i39, fabric_fpga_ddr0_araddr_i40, fabric_fpga_ddr0_arburst_i1, fabric_fpga_ddr0_arburst_i2, fabric_fpga_ddr0_arcache_i1, fabric_fpga_ddr0_arcache_i2, fabric_fpga_ddr0_arcache_i3, fabric_fpga_ddr0_arcache_i4, fabric_fpga_ddr0_arid_i1, fabric_fpga_ddr0_arid_i2, fabric_fpga_ddr0_arid_i3, fabric_fpga_ddr0_arid_i4, fabric_fpga_ddr0_arid_i5, fabric_fpga_ddr0_arlen_i1, fabric_fpga_ddr0_arlen_i2, fabric_fpga_ddr0_arlen_i3, fabric_fpga_ddr0_arlen_i4, fabric_fpga_ddr0_arlen_i5, fabric_fpga_ddr0_arlen_i6 -, fabric_fpga_ddr0_arlen_i7, fabric_fpga_ddr0_arlen_i8, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arprot_i1, fabric_fpga_ddr0_arprot_i2, fabric_fpga_ddr0_arprot_i3, fabric_fpga_ddr0_arqos_i1, fabric_fpga_ddr0_arqos_i2, fabric_fpga_ddr0_arqos_i3, fabric_fpga_ddr0_arqos_i4, fabric_fpga_ddr0_arsize_i1, fabric_fpga_ddr0_arsize_i2, fabric_fpga_ddr0_arsize_i3, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awaddr_i1, fabric_fpga_ddr0_awaddr_i2, fabric_fpga_ddr0_awaddr_i3, fabric_fpga_ddr0_awaddr_i4, fabric_fpga_ddr0_awaddr_i5, fabric_fpga_ddr0_awaddr_i6, fabric_fpga_ddr0_awaddr_i7 -, fabric_fpga_ddr0_awaddr_i8, fabric_fpga_ddr0_awaddr_i9, fabric_fpga_ddr0_awaddr_i10, fabric_fpga_ddr0_awaddr_i11, fabric_fpga_ddr0_awaddr_i12, fabric_fpga_ddr0_awaddr_i13, fabric_fpga_ddr0_awaddr_i14, fabric_fpga_ddr0_awaddr_i15, fabric_fpga_ddr0_awaddr_i16, fabric_fpga_ddr0_awaddr_i17, fabric_fpga_ddr0_awaddr_i18, fabric_fpga_ddr0_awaddr_i19, fabric_fpga_ddr0_awaddr_i20, fabric_fpga_ddr0_awaddr_i21, fabric_fpga_ddr0_awaddr_i22, fabric_fpga_ddr0_awaddr_i23, fabric_fpga_ddr0_awaddr_i24, fabric_fpga_ddr0_awaddr_i25, fabric_fpga_ddr0_awaddr_i26, fabric_fpga_ddr0_awaddr_i27, fabric_fpga_ddr0_awaddr_i28 -, fabric_fpga_ddr0_awaddr_i29, fabric_fpga_ddr0_awaddr_i30, fabric_fpga_ddr0_awaddr_i31, fabric_fpga_ddr0_awaddr_i32, fabric_fpga_ddr0_awaddr_i33, fabric_fpga_ddr0_awaddr_i34, fabric_fpga_ddr0_awaddr_i35, fabric_fpga_ddr0_awaddr_i36, fabric_fpga_ddr0_awaddr_i37, fabric_fpga_ddr0_awaddr_i38, fabric_fpga_ddr0_awaddr_i39, fabric_fpga_ddr0_awaddr_i40, fabric_fpga_ddr0_awburst_i1, fabric_fpga_ddr0_awburst_i2, fabric_fpga_ddr0_awcache_i1, fabric_fpga_ddr0_awcache_i2, fabric_fpga_ddr0_awcache_i3, fabric_fpga_ddr0_awcache_i4, fabric_fpga_ddr0_awid_i1, fabric_fpga_ddr0_awid_i2, fabric_fpga_ddr0_awid_i3 -, fabric_fpga_ddr0_awid_i4, fabric_fpga_ddr0_awid_i5, fabric_fpga_ddr0_awlen_i1, fabric_fpga_ddr0_awlen_i2, fabric_fpga_ddr0_awlen_i3, fabric_fpga_ddr0_awlen_i4, fabric_fpga_ddr0_awlen_i5, fabric_fpga_ddr0_awlen_i6, fabric_fpga_ddr0_awlen_i7, fabric_fpga_ddr0_awlen_i8, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awprot_i1, fabric_fpga_ddr0_awprot_i2, fabric_fpga_ddr0_awprot_i3, fabric_fpga_ddr0_awqos_i1, fabric_fpga_ddr0_awqos_i2, fabric_fpga_ddr0_awqos_i3, fabric_fpga_ddr0_awqos_i4, fabric_fpga_ddr0_awsize_i1, fabric_fpga_ddr0_awsize_i2, fabric_fpga_ddr0_awsize_i3 -, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wdata_i1, fabric_fpga_ddr0_wdata_i2, fabric_fpga_ddr0_wdata_i3, fabric_fpga_ddr0_wdata_i4, fabric_fpga_ddr0_wdata_i5, fabric_fpga_ddr0_wdata_i6, fabric_fpga_ddr0_wdata_i7, fabric_fpga_ddr0_wdata_i8, fabric_fpga_ddr0_wdata_i9, fabric_fpga_ddr0_wdata_i10, fabric_fpga_ddr0_wdata_i11, fabric_fpga_ddr0_wdata_i12, fabric_fpga_ddr0_wdata_i13, fabric_fpga_ddr0_wdata_i14, fabric_fpga_ddr0_wdata_i15, fabric_fpga_ddr0_wdata_i16, fabric_fpga_ddr0_wdata_i17, fabric_fpga_ddr0_wdata_i18 -, fabric_fpga_ddr0_wdata_i19, fabric_fpga_ddr0_wdata_i20, fabric_fpga_ddr0_wdata_i21, fabric_fpga_ddr0_wdata_i22, fabric_fpga_ddr0_wdata_i23, fabric_fpga_ddr0_wdata_i24, fabric_fpga_ddr0_wdata_i25, fabric_fpga_ddr0_wdata_i26, fabric_fpga_ddr0_wdata_i27, fabric_fpga_ddr0_wdata_i28, fabric_fpga_ddr0_wdata_i29, fabric_fpga_ddr0_wdata_i30, fabric_fpga_ddr0_wdata_i31, fabric_fpga_ddr0_wdata_i32, fabric_fpga_ddr0_wdata_i33, fabric_fpga_ddr0_wdata_i34, fabric_fpga_ddr0_wdata_i35, fabric_fpga_ddr0_wdata_i36, fabric_fpga_ddr0_wdata_i37, fabric_fpga_ddr0_wdata_i38, fabric_fpga_ddr0_wdata_i39 -, fabric_fpga_ddr0_wdata_i40, fabric_fpga_ddr0_wdata_i41, fabric_fpga_ddr0_wdata_i42, fabric_fpga_ddr0_wdata_i43, fabric_fpga_ddr0_wdata_i44, fabric_fpga_ddr0_wdata_i45, fabric_fpga_ddr0_wdata_i46, fabric_fpga_ddr0_wdata_i47, fabric_fpga_ddr0_wdata_i48, fabric_fpga_ddr0_wdata_i49, fabric_fpga_ddr0_wdata_i50, fabric_fpga_ddr0_wdata_i51, fabric_fpga_ddr0_wdata_i52, fabric_fpga_ddr0_wdata_i53, fabric_fpga_ddr0_wdata_i54, fabric_fpga_ddr0_wdata_i55, fabric_fpga_ddr0_wdata_i56, fabric_fpga_ddr0_wdata_i57, fabric_fpga_ddr0_wdata_i58, fabric_fpga_ddr0_wdata_i59, fabric_fpga_ddr0_wdata_i60 -, fabric_fpga_ddr0_wdata_i61, fabric_fpga_ddr0_wdata_i62, fabric_fpga_ddr0_wdata_i63, fabric_fpga_ddr0_wdata_i64, fabric_fpga_ddr0_wdata_i65, fabric_fpga_ddr0_wdata_i66, fabric_fpga_ddr0_wdata_i67, fabric_fpga_ddr0_wdata_i68, fabric_fpga_ddr0_wdata_i69, fabric_fpga_ddr0_wdata_i70, fabric_fpga_ddr0_wdata_i71, fabric_fpga_ddr0_wdata_i72, fabric_fpga_ddr0_wdata_i73, fabric_fpga_ddr0_wdata_i74, fabric_fpga_ddr0_wdata_i75, fabric_fpga_ddr0_wdata_i76, fabric_fpga_ddr0_wdata_i77, fabric_fpga_ddr0_wdata_i78, fabric_fpga_ddr0_wdata_i79, fabric_fpga_ddr0_wdata_i80, fabric_fpga_ddr0_wdata_i81 -, fabric_fpga_ddr0_wdata_i82, fabric_fpga_ddr0_wdata_i83, fabric_fpga_ddr0_wdata_i84, fabric_fpga_ddr0_wdata_i85, fabric_fpga_ddr0_wdata_i86, fabric_fpga_ddr0_wdata_i87, fabric_fpga_ddr0_wdata_i88, fabric_fpga_ddr0_wdata_i89, fabric_fpga_ddr0_wdata_i90, fabric_fpga_ddr0_wdata_i91, fabric_fpga_ddr0_wdata_i92, fabric_fpga_ddr0_wdata_i93, fabric_fpga_ddr0_wdata_i94, fabric_fpga_ddr0_wdata_i95, fabric_fpga_ddr0_wdata_i96, fabric_fpga_ddr0_wdata_i97, fabric_fpga_ddr0_wdata_i98, fabric_fpga_ddr0_wdata_i99, fabric_fpga_ddr0_wdata_i100, fabric_fpga_ddr0_wdata_i101, fabric_fpga_ddr0_wdata_i102 -, fabric_fpga_ddr0_wdata_i103, fabric_fpga_ddr0_wdata_i104, fabric_fpga_ddr0_wdata_i105, fabric_fpga_ddr0_wdata_i106, fabric_fpga_ddr0_wdata_i107, fabric_fpga_ddr0_wdata_i108, fabric_fpga_ddr0_wdata_i109, fabric_fpga_ddr0_wdata_i110, fabric_fpga_ddr0_wdata_i111, fabric_fpga_ddr0_wdata_i112, fabric_fpga_ddr0_wdata_i113, fabric_fpga_ddr0_wdata_i114, fabric_fpga_ddr0_wdata_i115, fabric_fpga_ddr0_wdata_i116, fabric_fpga_ddr0_wdata_i117, fabric_fpga_ddr0_wdata_i118, fabric_fpga_ddr0_wdata_i119, fabric_fpga_ddr0_wdata_i120, fabric_fpga_ddr0_wdata_i121, fabric_fpga_ddr0_wdata_i122, fabric_fpga_ddr0_wdata_i123 -, fabric_fpga_ddr0_wdata_i124, fabric_fpga_ddr0_wdata_i125, fabric_fpga_ddr0_wdata_i126, fabric_fpga_ddr0_wdata_i127, fabric_fpga_ddr0_wdata_i128, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wstrb_i1, fabric_fpga_ddr0_wstrb_i2, fabric_fpga_ddr0_wstrb_i3, fabric_fpga_ddr0_wstrb_i4, fabric_fpga_ddr0_wstrb_i5, fabric_fpga_ddr0_wstrb_i6, fabric_fpga_ddr0_wstrb_i7, fabric_fpga_ddr0_wstrb_i8, fabric_fpga_ddr0_wstrb_i9, fabric_fpga_ddr0_wstrb_i10, fabric_fpga_ddr0_wstrb_i11, fabric_fpga_ddr0_wstrb_i12, fabric_fpga_ddr0_wstrb_i13, fabric_fpga_ddr0_wstrb_i14, fabric_fpga_ddr0_wstrb_i15 -, fabric_fpga_ddr0_wstrb_i16, fabric_fpga_ddr0_wvalid_i, fabric_fpga_paddr_apb_o1, fabric_fpga_paddr_apb_o2, fabric_fpga_paddr_apb_o3, fabric_fpga_paddr_apb_o4, fabric_fpga_paddr_apb_o5, fabric_fpga_paddr_apb_o6, fabric_fpga_paddr_apb_o7, fabric_fpga_paddr_apb_o8, fabric_fpga_paddr_apb_o9, fabric_fpga_paddr_apb_o10, fabric_fpga_paddr_apb_o11, fabric_fpga_paddr_apb_o12, fabric_fpga_paddr_apb_o13, fabric_fpga_paddr_apb_o14, fabric_fpga_paddr_apb_o15, fabric_fpga_paddr_apb_o16, fabric_fpga_paddr_apb_o17, fabric_fpga_paddr_apb_o18, fabric_fpga_paddr_apb_o19 -, fabric_fpga_paddr_apb_o20, fabric_fpga_paddr_apb_o21, fabric_fpga_paddr_apb_o22, fabric_fpga_paddr_apb_o23, fabric_fpga_paddr_apb_o24, fabric_fpga_paddr_apb_o25, fabric_fpga_paddr_apb_o26, fabric_fpga_paddr_apb_o27, fabric_fpga_paddr_apb_o28, fabric_fpga_paddr_apb_o29, fabric_fpga_paddr_apb_o30, fabric_fpga_paddr_apb_o31, fabric_fpga_paddr_apb_o32, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwdata_apb_o1, fabric_fpga_pwdata_apb_o2, fabric_fpga_pwdata_apb_o3, fabric_fpga_pwdata_apb_o4, fabric_fpga_pwdata_apb_o5, fabric_fpga_pwdata_apb_o6 -, fabric_fpga_pwdata_apb_o7, fabric_fpga_pwdata_apb_o8, fabric_fpga_pwdata_apb_o9, fabric_fpga_pwdata_apb_o10, fabric_fpga_pwdata_apb_o11, fabric_fpga_pwdata_apb_o12, fabric_fpga_pwdata_apb_o13, fabric_fpga_pwdata_apb_o14, fabric_fpga_pwdata_apb_o15, fabric_fpga_pwdata_apb_o16, fabric_fpga_pwdata_apb_o17, fabric_fpga_pwdata_apb_o18, fabric_fpga_pwdata_apb_o19, fabric_fpga_pwdata_apb_o20, fabric_fpga_pwdata_apb_o21, fabric_fpga_pwdata_apb_o22, fabric_fpga_pwdata_apb_o23, fabric_fpga_pwdata_apb_o24, fabric_fpga_pwdata_apb_o25, fabric_fpga_pwdata_apb_o26, fabric_fpga_pwdata_apb_o27 -, fabric_fpga_pwdata_apb_o28, fabric_fpga_pwdata_apb_o29, fabric_fpga_pwdata_apb_o30, fabric_fpga_pwdata_apb_o31, fabric_fpga_pwdata_apb_o32, fabric_fpga_pwrite_apb_o, fabric_fpga_prdata_apb_i1, fabric_fpga_prdata_apb_i2, fabric_fpga_prdata_apb_i3, fabric_fpga_prdata_apb_i4, fabric_fpga_prdata_apb_i5, fabric_fpga_prdata_apb_i6, fabric_fpga_prdata_apb_i7, fabric_fpga_prdata_apb_i8, fabric_fpga_prdata_apb_i9, fabric_fpga_prdata_apb_i10, fabric_fpga_prdata_apb_i11, fabric_fpga_prdata_apb_i12, fabric_fpga_prdata_apb_i13, fabric_fpga_prdata_apb_i14, fabric_fpga_prdata_apb_i15 -, fabric_fpga_prdata_apb_i16, fabric_fpga_prdata_apb_i17, fabric_fpga_prdata_apb_i18, fabric_fpga_prdata_apb_i19, fabric_fpga_prdata_apb_i20, fabric_fpga_prdata_apb_i21, fabric_fpga_prdata_apb_i22, fabric_fpga_prdata_apb_i23, fabric_fpga_prdata_apb_i24, fabric_fpga_prdata_apb_i25, fabric_fpga_prdata_apb_i26, fabric_fpga_prdata_apb_i27, fabric_fpga_prdata_apb_i28, fabric_fpga_prdata_apb_i29, fabric_fpga_prdata_apb_i30, fabric_fpga_prdata_apb_i31, fabric_fpga_prdata_apb_i32, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_araddr_s_o1, fabric_llpp0_araddr_s_o2 -, fabric_llpp0_araddr_s_o3, fabric_llpp0_araddr_s_o4, fabric_llpp0_araddr_s_o5, fabric_llpp0_araddr_s_o6, fabric_llpp0_araddr_s_o7, fabric_llpp0_araddr_s_o8, fabric_llpp0_araddr_s_o9, fabric_llpp0_araddr_s_o10, fabric_llpp0_araddr_s_o11, fabric_llpp0_araddr_s_o12, fabric_llpp0_araddr_s_o13, fabric_llpp0_araddr_s_o14, fabric_llpp0_araddr_s_o15, fabric_llpp0_araddr_s_o16, fabric_llpp0_araddr_s_o17, fabric_llpp0_araddr_s_o18, fabric_llpp0_araddr_s_o19, fabric_llpp0_araddr_s_o20, fabric_llpp0_araddr_s_o21, fabric_llpp0_araddr_s_o22, fabric_llpp0_araddr_s_o23 -, fabric_llpp0_araddr_s_o24, fabric_llpp0_araddr_s_o25, fabric_llpp0_araddr_s_o26, fabric_llpp0_araddr_s_o27, fabric_llpp0_araddr_s_o28, fabric_llpp0_araddr_s_o29, fabric_llpp0_araddr_s_o30, fabric_llpp0_araddr_s_o31, fabric_llpp0_araddr_s_o32, fabric_llpp0_arburst_s_o1, fabric_llpp0_arburst_s_o2, fabric_llpp0_arcache_s_o1, fabric_llpp0_arcache_s_o2, fabric_llpp0_arcache_s_o3, fabric_llpp0_arcache_s_o4, fabric_llpp0_arid_s_o1, fabric_llpp0_arid_s_o2, fabric_llpp0_arid_s_o3, fabric_llpp0_arid_s_o4, fabric_llpp0_arid_s_o5, fabric_llpp0_arid_s_o6 -, fabric_llpp0_arid_s_o7, fabric_llpp0_arid_s_o8, fabric_llpp0_arid_s_o9, fabric_llpp0_arid_s_o10, fabric_llpp0_arid_s_o11, fabric_llpp0_arid_s_o12, fabric_llpp0_arlen_s_o1, fabric_llpp0_arlen_s_o2, fabric_llpp0_arlen_s_o3, fabric_llpp0_arlen_s_o4, fabric_llpp0_arlen_s_o5, fabric_llpp0_arlen_s_o6, fabric_llpp0_arlen_s_o7, fabric_llpp0_arlen_s_o8, fabric_llpp0_arlock_s_o, fabric_llpp0_arprot_s_o1, fabric_llpp0_arprot_s_o2, fabric_llpp0_arprot_s_o3, fabric_llpp0_arqos_s_o1, fabric_llpp0_arqos_s_o2, fabric_llpp0_arqos_s_o3 -, fabric_llpp0_arqos_s_o4, fabric_llpp0_arsize_s_o1, fabric_llpp0_arsize_s_o2, fabric_llpp0_arsize_s_o3, fabric_llpp0_arvalid_s_o, fabric_llpp0_awaddr_s_o1, fabric_llpp0_awaddr_s_o2, fabric_llpp0_awaddr_s_o3, fabric_llpp0_awaddr_s_o4, fabric_llpp0_awaddr_s_o5, fabric_llpp0_awaddr_s_o6, fabric_llpp0_awaddr_s_o7, fabric_llpp0_awaddr_s_o8, fabric_llpp0_awaddr_s_o9, fabric_llpp0_awaddr_s_o10, fabric_llpp0_awaddr_s_o11, fabric_llpp0_awaddr_s_o12, fabric_llpp0_awaddr_s_o13, fabric_llpp0_awaddr_s_o14, fabric_llpp0_awaddr_s_o15, fabric_llpp0_awaddr_s_o16 -, fabric_llpp0_awaddr_s_o17, fabric_llpp0_awaddr_s_o18, fabric_llpp0_awaddr_s_o19, fabric_llpp0_awaddr_s_o20, fabric_llpp0_awaddr_s_o21, fabric_llpp0_awaddr_s_o22, fabric_llpp0_awaddr_s_o23, fabric_llpp0_awaddr_s_o24, fabric_llpp0_awaddr_s_o25, fabric_llpp0_awaddr_s_o26, fabric_llpp0_awaddr_s_o27, fabric_llpp0_awaddr_s_o28, fabric_llpp0_awaddr_s_o29, fabric_llpp0_awaddr_s_o30, fabric_llpp0_awaddr_s_o31, fabric_llpp0_awaddr_s_o32, fabric_llpp0_awburst_s_o1, fabric_llpp0_awburst_s_o2, fabric_llpp0_awcache_s_o1, fabric_llpp0_awcache_s_o2, fabric_llpp0_awcache_s_o3 -, fabric_llpp0_awcache_s_o4, fabric_llpp0_awid_s_o1, fabric_llpp0_awid_s_o2, fabric_llpp0_awid_s_o3, fabric_llpp0_awid_s_o4, fabric_llpp0_awid_s_o5, fabric_llpp0_awid_s_o6, fabric_llpp0_awid_s_o7, fabric_llpp0_awid_s_o8, fabric_llpp0_awid_s_o9, fabric_llpp0_awid_s_o10, fabric_llpp0_awid_s_o11, fabric_llpp0_awid_s_o12, fabric_llpp0_awlen_s_o1, fabric_llpp0_awlen_s_o2, fabric_llpp0_awlen_s_o3, fabric_llpp0_awlen_s_o4, fabric_llpp0_awlen_s_o5, fabric_llpp0_awlen_s_o6, fabric_llpp0_awlen_s_o7, fabric_llpp0_awlen_s_o8 -, fabric_llpp0_awlock_s_o, fabric_llpp0_awprot_s_o1, fabric_llpp0_awprot_s_o2, fabric_llpp0_awprot_s_o3, fabric_llpp0_awqos_s_o1, fabric_llpp0_awqos_s_o2, fabric_llpp0_awqos_s_o3, fabric_llpp0_awqos_s_o4, fabric_llpp0_awsize_s_o1, fabric_llpp0_awsize_s_o2, fabric_llpp0_awsize_s_o3, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o, fabric_llpp0_wdata_s_o1, fabric_llpp0_wdata_s_o2, fabric_llpp0_wdata_s_o3, fabric_llpp0_wdata_s_o4, fabric_llpp0_wdata_s_o5, fabric_llpp0_wdata_s_o6, fabric_llpp0_wdata_s_o7 -, fabric_llpp0_wdata_s_o8, fabric_llpp0_wdata_s_o9, fabric_llpp0_wdata_s_o10, fabric_llpp0_wdata_s_o11, fabric_llpp0_wdata_s_o12, fabric_llpp0_wdata_s_o13, fabric_llpp0_wdata_s_o14, fabric_llpp0_wdata_s_o15, fabric_llpp0_wdata_s_o16, fabric_llpp0_wdata_s_o17, fabric_llpp0_wdata_s_o18, fabric_llpp0_wdata_s_o19, fabric_llpp0_wdata_s_o20, fabric_llpp0_wdata_s_o21, fabric_llpp0_wdata_s_o22, fabric_llpp0_wdata_s_o23, fabric_llpp0_wdata_s_o24, fabric_llpp0_wdata_s_o25, fabric_llpp0_wdata_s_o26, fabric_llpp0_wdata_s_o27, fabric_llpp0_wdata_s_o28 -, fabric_llpp0_wdata_s_o29, fabric_llpp0_wdata_s_o30, fabric_llpp0_wdata_s_o31, fabric_llpp0_wdata_s_o32, fabric_llpp0_wlast_s_o, fabric_llpp0_wstrb_s_o1, fabric_llpp0_wstrb_s_o2, fabric_llpp0_wstrb_s_o3, fabric_llpp0_wstrb_s_o4, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bid_s_i1, fabric_llpp0_bid_s_i2, fabric_llpp0_bid_s_i3, fabric_llpp0_bid_s_i4, fabric_llpp0_bid_s_i5, fabric_llpp0_bid_s_i6, fabric_llpp0_bid_s_i7, fabric_llpp0_bid_s_i8, fabric_llpp0_bid_s_i9 -, fabric_llpp0_bid_s_i10, fabric_llpp0_bid_s_i11, fabric_llpp0_bid_s_i12, fabric_llpp0_bresp_s_i1, fabric_llpp0_bresp_s_i2, fabric_llpp0_bvalid_s_i, fabric_llpp0_rdata_s_i1, fabric_llpp0_rdata_s_i2, fabric_llpp0_rdata_s_i3, fabric_llpp0_rdata_s_i4, fabric_llpp0_rdata_s_i5, fabric_llpp0_rdata_s_i6, fabric_llpp0_rdata_s_i7, fabric_llpp0_rdata_s_i8, fabric_llpp0_rdata_s_i9, fabric_llpp0_rdata_s_i10, fabric_llpp0_rdata_s_i11, fabric_llpp0_rdata_s_i12, fabric_llpp0_rdata_s_i13, fabric_llpp0_rdata_s_i14, fabric_llpp0_rdata_s_i15 -, fabric_llpp0_rdata_s_i16, fabric_llpp0_rdata_s_i17, fabric_llpp0_rdata_s_i18, fabric_llpp0_rdata_s_i19, fabric_llpp0_rdata_s_i20, fabric_llpp0_rdata_s_i21, fabric_llpp0_rdata_s_i22, fabric_llpp0_rdata_s_i23, fabric_llpp0_rdata_s_i24, fabric_llpp0_rdata_s_i25, fabric_llpp0_rdata_s_i26, fabric_llpp0_rdata_s_i27, fabric_llpp0_rdata_s_i28, fabric_llpp0_rdata_s_i29, fabric_llpp0_rdata_s_i30, fabric_llpp0_rdata_s_i31, fabric_llpp0_rdata_s_i32, fabric_llpp0_rid_s_i1, fabric_llpp0_rid_s_i2, fabric_llpp0_rid_s_i3, fabric_llpp0_rid_s_i4 -, fabric_llpp0_rid_s_i5, fabric_llpp0_rid_s_i6, fabric_llpp0_rid_s_i7, fabric_llpp0_rid_s_i8, fabric_llpp0_rid_s_i9, fabric_llpp0_rid_s_i10, fabric_llpp0_rid_s_i11, fabric_llpp0_rid_s_i12, fabric_llpp0_rlast_s_i, fabric_llpp0_rresp_s_i1, fabric_llpp0_rresp_s_i2, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_araddr_s_o1, fabric_llpp1_araddr_s_o2, fabric_llpp1_araddr_s_o3, fabric_llpp1_araddr_s_o4, fabric_llpp1_araddr_s_o5, fabric_llpp1_araddr_s_o6, fabric_llpp1_araddr_s_o7, fabric_llpp1_araddr_s_o8 -, fabric_llpp1_araddr_s_o9, fabric_llpp1_araddr_s_o10, fabric_llpp1_araddr_s_o11, fabric_llpp1_araddr_s_o12, fabric_llpp1_araddr_s_o13, fabric_llpp1_araddr_s_o14, fabric_llpp1_araddr_s_o15, fabric_llpp1_araddr_s_o16, fabric_llpp1_araddr_s_o17, fabric_llpp1_araddr_s_o18, fabric_llpp1_araddr_s_o19, fabric_llpp1_araddr_s_o20, fabric_llpp1_araddr_s_o21, fabric_llpp1_araddr_s_o22, fabric_llpp1_araddr_s_o23, fabric_llpp1_araddr_s_o24, fabric_llpp1_araddr_s_o25, fabric_llpp1_araddr_s_o26, fabric_llpp1_araddr_s_o27, fabric_llpp1_araddr_s_o28, fabric_llpp1_araddr_s_o29 -, fabric_llpp1_araddr_s_o30, fabric_llpp1_araddr_s_o31, fabric_llpp1_araddr_s_o32, fabric_llpp1_arburst_s_o1, fabric_llpp1_arburst_s_o2, fabric_llpp1_arcache_s_o1, fabric_llpp1_arcache_s_o2, fabric_llpp1_arcache_s_o3, fabric_llpp1_arcache_s_o4, fabric_llpp1_arid_s_o1, fabric_llpp1_arid_s_o2, fabric_llpp1_arid_s_o3, fabric_llpp1_arid_s_o4, fabric_llpp1_arid_s_o5, fabric_llpp1_arid_s_o6, fabric_llpp1_arid_s_o7, fabric_llpp1_arid_s_o8, fabric_llpp1_arid_s_o9, fabric_llpp1_arid_s_o10, fabric_llpp1_arid_s_o11, fabric_llpp1_arid_s_o12 -, fabric_llpp1_arlen_s_o1, fabric_llpp1_arlen_s_o2, fabric_llpp1_arlen_s_o3, fabric_llpp1_arlen_s_o4, fabric_llpp1_arlen_s_o5, fabric_llpp1_arlen_s_o6, fabric_llpp1_arlen_s_o7, fabric_llpp1_arlen_s_o8, fabric_llpp1_arlock_s_o, fabric_llpp1_arprot_s_o1, fabric_llpp1_arprot_s_o2, fabric_llpp1_arprot_s_o3, fabric_llpp1_arqos_s1_o1, fabric_llpp1_arqos_s1_o2, fabric_llpp1_arqos_s1_o3, fabric_llpp1_arqos_s1_o4, fabric_llpp1_arsize_s_o1, fabric_llpp1_arsize_s_o2, fabric_llpp1_arsize_s_o3, fabric_llpp1_arvalid_s_o, fabric_llpp1_awaddr_s_o1 -, fabric_llpp1_awaddr_s_o2, fabric_llpp1_awaddr_s_o3, fabric_llpp1_awaddr_s_o4, fabric_llpp1_awaddr_s_o5, fabric_llpp1_awaddr_s_o6, fabric_llpp1_awaddr_s_o7, fabric_llpp1_awaddr_s_o8, fabric_llpp1_awaddr_s_o9, fabric_llpp1_awaddr_s_o10, fabric_llpp1_awaddr_s_o11, fabric_llpp1_awaddr_s_o12, fabric_llpp1_awaddr_s_o13, fabric_llpp1_awaddr_s_o14, fabric_llpp1_awaddr_s_o15, fabric_llpp1_awaddr_s_o16, fabric_llpp1_awaddr_s_o17, fabric_llpp1_awaddr_s_o18, fabric_llpp1_awaddr_s_o19, fabric_llpp1_awaddr_s_o20, fabric_llpp1_awaddr_s_o21, fabric_llpp1_awaddr_s_o22 -, fabric_llpp1_awaddr_s_o23, fabric_llpp1_awaddr_s_o24, fabric_llpp1_awaddr_s_o25, fabric_llpp1_awaddr_s_o26, fabric_llpp1_awaddr_s_o27, fabric_llpp1_awaddr_s_o28, fabric_llpp1_awaddr_s_o29, fabric_llpp1_awaddr_s_o30, fabric_llpp1_awaddr_s_o31, fabric_llpp1_awaddr_s_o32, fabric_llpp1_awburst_s_o1, fabric_llpp1_awburst_s_o2, fabric_llpp1_awcache_s_o1, fabric_llpp1_awcache_s_o2, fabric_llpp1_awcache_s_o3, fabric_llpp1_awcache_s_o4, fabric_llpp1_awid_s_o1, fabric_llpp1_awid_s_o2, fabric_llpp1_awid_s_o3, fabric_llpp1_awid_s_o4, fabric_llpp1_awid_s_o5 -, fabric_llpp1_awid_s_o6, fabric_llpp1_awid_s_o7, fabric_llpp1_awid_s_o8, fabric_llpp1_awid_s_o9, fabric_llpp1_awid_s_o10, fabric_llpp1_awid_s_o11, fabric_llpp1_awid_s_o12, fabric_llpp1_awlen_s_o1, fabric_llpp1_awlen_s_o2, fabric_llpp1_awlen_s_o3, fabric_llpp1_awlen_s_o4, fabric_llpp1_awlen_s_o5, fabric_llpp1_awlen_s_o6, fabric_llpp1_awlen_s_o7, fabric_llpp1_awlen_s_o8, fabric_llpp1_awlock_s_o, fabric_llpp1_awprot_s_o1, fabric_llpp1_awprot_s_o2, fabric_llpp1_awprot_s_o3, fabric_llpp1_awqos_s_o1, fabric_llpp1_awqos_s_o2 -, fabric_llpp1_awqos_s_o3, fabric_llpp1_awqos_s_o4, fabric_llpp1_awsize_s_o1, fabric_llpp1_awsize_s_o2, fabric_llpp1_awsize_s_o3, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wdata_s_o1, fabric_llpp1_wdata_s_o2, fabric_llpp1_wdata_s_o3, fabric_llpp1_wdata_s_o4, fabric_llpp1_wdata_s_o5, fabric_llpp1_wdata_s_o6, fabric_llpp1_wdata_s_o7, fabric_llpp1_wdata_s_o8, fabric_llpp1_wdata_s_o9, fabric_llpp1_wdata_s_o10, fabric_llpp1_wdata_s_o11, fabric_llpp1_wdata_s_o12, fabric_llpp1_wdata_s_o13 -, fabric_llpp1_wdata_s_o14, fabric_llpp1_wdata_s_o15, fabric_llpp1_wdata_s_o16, fabric_llpp1_wdata_s_o17, fabric_llpp1_wdata_s_o18, fabric_llpp1_wdata_s_o19, fabric_llpp1_wdata_s_o20, fabric_llpp1_wdata_s_o21, fabric_llpp1_wdata_s_o22, fabric_llpp1_wdata_s_o23, fabric_llpp1_wdata_s_o24, fabric_llpp1_wdata_s_o25, fabric_llpp1_wdata_s_o26, fabric_llpp1_wdata_s_o27, fabric_llpp1_wdata_s_o28, fabric_llpp1_wdata_s_o29, fabric_llpp1_wdata_s_o30, fabric_llpp1_wdata_s_o31, fabric_llpp1_wdata_s_o32, fabric_llpp1_wlast_s_o, fabric_llpp1_wstrb_s_o1 -, fabric_llpp1_wstrb_s_o2, fabric_llpp1_wstrb_s_o3, fabric_llpp1_wstrb_s_o4, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bid_s_i1, fabric_llpp1_bid_s_i2, fabric_llpp1_bid_s_i3, fabric_llpp1_bid_s_i4, fabric_llpp1_bid_s_i5, fabric_llpp1_bid_s_i6, fabric_llpp1_bid_s_i7, fabric_llpp1_bid_s_i8, fabric_llpp1_bid_s_i9, fabric_llpp1_bid_s_i10, fabric_llpp1_bid_s_i11, fabric_llpp1_bid_s_i12, fabric_llpp1_bresp_s_i1, fabric_llpp1_bresp_s_i2, fabric_llpp1_bvalid_s_i -, fabric_llpp1_rdata_s_i1, fabric_llpp1_rdata_s_i2, fabric_llpp1_rdata_s_i3, fabric_llpp1_rdata_s_i4, fabric_llpp1_rdata_s_i5, fabric_llpp1_rdata_s_i6, fabric_llpp1_rdata_s_i7, fabric_llpp1_rdata_s_i8, fabric_llpp1_rdata_s_i9, fabric_llpp1_rdata_s_i10, fabric_llpp1_rdata_s_i11, fabric_llpp1_rdata_s_i12, fabric_llpp1_rdata_s_i13, fabric_llpp1_rdata_s_i14, fabric_llpp1_rdata_s_i15, fabric_llpp1_rdata_s_i16, fabric_llpp1_rdata_s_i17, fabric_llpp1_rdata_s_i18, fabric_llpp1_rdata_s_i19, fabric_llpp1_rdata_s_i20, fabric_llpp1_rdata_s_i21 -, fabric_llpp1_rdata_s_i22, fabric_llpp1_rdata_s_i23, fabric_llpp1_rdata_s_i24, fabric_llpp1_rdata_s_i25, fabric_llpp1_rdata_s_i26, fabric_llpp1_rdata_s_i27, fabric_llpp1_rdata_s_i28, fabric_llpp1_rdata_s_i29, fabric_llpp1_rdata_s_i30, fabric_llpp1_rdata_s_i31, fabric_llpp1_rdata_s_i32, fabric_llpp1_rid_s_i1, fabric_llpp1_rid_s_i2, fabric_llpp1_rid_s_i3, fabric_llpp1_rid_s_i4, fabric_llpp1_rid_s_i5, fabric_llpp1_rid_s_i6, fabric_llpp1_rid_s_i7, fabric_llpp1_rid_s_i8, fabric_llpp1_rid_s_i9, fabric_llpp1_rid_s_i10 -, fabric_llpp1_rid_s_i11, fabric_llpp1_rid_s_i12, fabric_llpp1_rlast_s_i, fabric_llpp1_rresp_s_i1, fabric_llpp1_rresp_s_i2, fabric_llpp1_rvalid_s_i, fabric_llpp1_wready_s_i, fabric_llpp2_araddr_s_o1, fabric_llpp2_araddr_s_o2, fabric_llpp2_araddr_s_o3, fabric_llpp2_araddr_s_o4, fabric_llpp2_araddr_s_o5, fabric_llpp2_araddr_s_o6, fabric_llpp2_araddr_s_o7, fabric_llpp2_araddr_s_o8, fabric_llpp2_araddr_s_o9, fabric_llpp2_araddr_s_o10, fabric_llpp2_araddr_s_o11, fabric_llpp2_araddr_s_o12, fabric_llpp2_araddr_s_o13, fabric_llpp2_araddr_s_o14 -, fabric_llpp2_araddr_s_o15, fabric_llpp2_araddr_s_o16, fabric_llpp2_araddr_s_o17, fabric_llpp2_araddr_s_o18, fabric_llpp2_araddr_s_o19, fabric_llpp2_araddr_s_o20, fabric_llpp2_araddr_s_o21, fabric_llpp2_araddr_s_o22, fabric_llpp2_araddr_s_o23, fabric_llpp2_araddr_s_o24, fabric_llpp2_araddr_s_o25, fabric_llpp2_araddr_s_o26, fabric_llpp2_araddr_s_o27, fabric_llpp2_araddr_s_o28, fabric_llpp2_araddr_s_o29, fabric_llpp2_araddr_s_o30, fabric_llpp2_araddr_s_o31, fabric_llpp2_araddr_s_o32, fabric_llpp2_arburst_s_o1, fabric_llpp2_arburst_s_o2, fabric_llpp2_arcache_s_o1 -, fabric_llpp2_arcache_s_o2, fabric_llpp2_arcache_s_o3, fabric_llpp2_arcache_s_o4, fabric_llpp2_arid_s_o1, fabric_llpp2_arid_s_o2, fabric_llpp2_arid_s_o3, fabric_llpp2_arid_s_o4, fabric_llpp2_arid_s_o5, fabric_llpp2_arid_s_o6, fabric_llpp2_arid_s_o7, fabric_llpp2_arid_s_o8, fabric_llpp2_arid_s_o9, fabric_llpp2_arid_s_o10, fabric_llpp2_arid_s_o11, fabric_llpp2_arid_s_o12, fabric_llpp2_arlen_s_o1, fabric_llpp2_arlen_s_o2, fabric_llpp2_arlen_s_o3, fabric_llpp2_arlen_s_o4, fabric_llpp2_arlen_s_o5, fabric_llpp2_arlen_s_o6 -, fabric_llpp2_arlen_s_o7, fabric_llpp2_arlen_s_o8, fabric_llpp2_arlock_s_o, fabric_llpp2_arprot_s_o1, fabric_llpp2_arprot_s_o2, fabric_llpp2_arprot_s_o3, fabric_llpp2_arqos_s_o1, fabric_llpp2_arqos_s_o2, fabric_llpp2_arqos_s_o3, fabric_llpp2_arqos_s_o4, fabric_llpp2_arsize_s_o1, fabric_llpp2_arsize_s_o2, fabric_llpp2_arsize_s_o3, fabric_llpp2_arvalid_s_o, fabric_llpp2_awaddr_s_o1, fabric_llpp2_awaddr_s_o2, fabric_llpp2_awaddr_s_o3, fabric_llpp2_awaddr_s_o4, fabric_llpp2_awaddr_s_o5, fabric_llpp2_awaddr_s_o6, fabric_llpp2_awaddr_s_o7 -, fabric_llpp2_awaddr_s_o8, fabric_llpp2_awaddr_s_o9, fabric_llpp2_awaddr_s_o10, fabric_llpp2_awaddr_s_o11, fabric_llpp2_awaddr_s_o12, fabric_llpp2_awaddr_s_o13, fabric_llpp2_awaddr_s_o14, fabric_llpp2_awaddr_s_o15, fabric_llpp2_awaddr_s_o16, fabric_llpp2_awaddr_s_o17, fabric_llpp2_awaddr_s_o18, fabric_llpp2_awaddr_s_o19, fabric_llpp2_awaddr_s_o20, fabric_llpp2_awaddr_s_o21, fabric_llpp2_awaddr_s_o22, fabric_llpp2_awaddr_s_o23, fabric_llpp2_awaddr_s_o24, fabric_llpp2_awaddr_s_o25, fabric_llpp2_awaddr_s_o26, fabric_llpp2_awaddr_s_o27, fabric_llpp2_awaddr_s_o28 -, fabric_llpp2_awaddr_s_o29, fabric_llpp2_awaddr_s_o30, fabric_llpp2_awaddr_s_o31, fabric_llpp2_awaddr_s_o32, fabric_llpp2_awburst_s_o1, fabric_llpp2_awburst_s_o2, fabric_llpp2_awcache_s_o1, fabric_llpp2_awcache_s_o2, fabric_llpp2_awcache_s_o3, fabric_llpp2_awcache_s_o4, fabric_llpp2_awid_s_o1, fabric_llpp2_awid_s_o2, fabric_llpp2_awid_s_o3, fabric_llpp2_awid_s_o4, fabric_llpp2_awid_s_o5, fabric_llpp2_awid_s_o6, fabric_llpp2_awid_s_o7, fabric_llpp2_awid_s_o8, fabric_llpp2_awid_s_o9, fabric_llpp2_awid_s_o10, fabric_llpp2_awid_s_o11 -, fabric_llpp2_awid_s_o12, fabric_llpp2_awlen_s_o1, fabric_llpp2_awlen_s_o2, fabric_llpp2_awlen_s_o3, fabric_llpp2_awlen_s_o4, fabric_llpp2_awlen_s_o5, fabric_llpp2_awlen_s_o6, fabric_llpp2_awlen_s_o7, fabric_llpp2_awlen_s_o8, fabric_llpp2_awlock_s_o, fabric_llpp2_awprot_s_o1, fabric_llpp2_awprot_s_o2, fabric_llpp2_awprot_s_o3, fabric_llpp2_awqos_s_o1, fabric_llpp2_awqos_s_o2, fabric_llpp2_awqos_s_o3, fabric_llpp2_awqos_s_o4, fabric_llpp2_awsize_s_o1, fabric_llpp2_awsize_s_o2, fabric_llpp2_awsize_s_o3, fabric_llpp2_awvalid_s_o -, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wdata_s_o1, fabric_llpp2_wdata_s_o2, fabric_llpp2_wdata_s_o3, fabric_llpp2_wdata_s_o4, fabric_llpp2_wdata_s_o5, fabric_llpp2_wdata_s_o6, fabric_llpp2_wdata_s_o7, fabric_llpp2_wdata_s_o8, fabric_llpp2_wdata_s_o9, fabric_llpp2_wdata_s_o10, fabric_llpp2_wdata_s_o11, fabric_llpp2_wdata_s_o12, fabric_llpp2_wdata_s_o13, fabric_llpp2_wdata_s_o14, fabric_llpp2_wdata_s_o15, fabric_llpp2_wdata_s_o16, fabric_llpp2_wdata_s_o17, fabric_llpp2_wdata_s_o18, fabric_llpp2_wdata_s_o19 -, fabric_llpp2_wdata_s_o20, fabric_llpp2_wdata_s_o21, fabric_llpp2_wdata_s_o22, fabric_llpp2_wdata_s_o23, fabric_llpp2_wdata_s_o24, fabric_llpp2_wdata_s_o25, fabric_llpp2_wdata_s_o26, fabric_llpp2_wdata_s_o27, fabric_llpp2_wdata_s_o28, fabric_llpp2_wdata_s_o29, fabric_llpp2_wdata_s_o30, fabric_llpp2_wdata_s_o31, fabric_llpp2_wdata_s_o32, fabric_llpp2_wlast_s_o, fabric_llpp2_wstrb_s_o1, fabric_llpp2_wstrb_s_o2, fabric_llpp2_wstrb_s_o3, fabric_llpp2_wstrb_s_o4, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i -, fabric_llpp2_bid_s_i1, fabric_llpp2_bid_s_i2, fabric_llpp2_bid_s_i3, fabric_llpp2_bid_s_i4, fabric_llpp2_bid_s_i5, fabric_llpp2_bid_s_i6, fabric_llpp2_bid_s_i7, fabric_llpp2_bid_s_i8, fabric_llpp2_bid_s_i9, fabric_llpp2_bid_s_i10, fabric_llpp2_bid_s_i11, fabric_llpp2_bid_s_i12, fabric_llpp2_bresp_s_i1, fabric_llpp2_bresp_s_i2, fabric_llpp2_bvalid_s_i, fabric_llpp2_rdata_s_i1, fabric_llpp2_rdata_s_i2, fabric_llpp2_rdata_s_i3, fabric_llpp2_rdata_s_i4, fabric_llpp2_rdata_s_i5, fabric_llpp2_rdata_s_i6 -, fabric_llpp2_rdata_s_i7, fabric_llpp2_rdata_s_i8, fabric_llpp2_rdata_s_i9, fabric_llpp2_rdata_s_i10, fabric_llpp2_rdata_s_i11, fabric_llpp2_rdata_s_i12, fabric_llpp2_rdata_s_i13, fabric_llpp2_rdata_s_i14, fabric_llpp2_rdata_s_i15, fabric_llpp2_rdata_s_i16, fabric_llpp2_rdata_s_i17, fabric_llpp2_rdata_s_i18, fabric_llpp2_rdata_s_i19, fabric_llpp2_rdata_s_i20, fabric_llpp2_rdata_s_i21, fabric_llpp2_rdata_s_i22, fabric_llpp2_rdata_s_i23, fabric_llpp2_rdata_s_i24, fabric_llpp2_rdata_s_i25, fabric_llpp2_rdata_s_i26, fabric_llpp2_rdata_s_i27 -, fabric_llpp2_rdata_s_i28, fabric_llpp2_rdata_s_i29, fabric_llpp2_rdata_s_i30, fabric_llpp2_rdata_s_i31, fabric_llpp2_rdata_s_i32, fabric_llpp2_rid_s_i1, fabric_llpp2_rid_s_i2, fabric_llpp2_rid_s_i3, fabric_llpp2_rid_s_i4, fabric_llpp2_rid_s_i5, fabric_llpp2_rid_s_i6, fabric_llpp2_rid_s_i7, fabric_llpp2_rid_s_i8, fabric_llpp2_rid_s_i9, fabric_llpp2_rid_s_i10, fabric_llpp2_rid_s_i11, fabric_llpp2_rid_s_i12, fabric_llpp2_rlast_s_i, fabric_llpp2_rresp_s_i1, fabric_llpp2_rresp_s_i2, fabric_llpp2_rvalid_s_i -, fabric_llpp2_wready_s_i, fabric_llpp3_araddr_s_o1, fabric_llpp3_araddr_s_o2, fabric_llpp3_araddr_s_o3, fabric_llpp3_araddr_s_o4, fabric_llpp3_araddr_s_o5, fabric_llpp3_araddr_s_o6, fabric_llpp3_araddr_s_o7, fabric_llpp3_araddr_s_o8, fabric_llpp3_araddr_s_o9, fabric_llpp3_araddr_s_o10, fabric_llpp3_araddr_s_o11, fabric_llpp3_araddr_s_o12, fabric_llpp3_araddr_s_o13, fabric_llpp3_araddr_s_o14, fabric_llpp3_araddr_s_o15, fabric_llpp3_araddr_s_o16, fabric_llpp3_araddr_s_o17, fabric_llpp3_araddr_s_o18, fabric_llpp3_araddr_s_o19, fabric_llpp3_araddr_s_o20 -, fabric_llpp3_araddr_s_o21, fabric_llpp3_araddr_s_o22, fabric_llpp3_araddr_s_o23, fabric_llpp3_araddr_s_o24, fabric_llpp3_araddr_s_o25, fabric_llpp3_araddr_s_o26, fabric_llpp3_araddr_s_o27, fabric_llpp3_araddr_s_o28, fabric_llpp3_araddr_s_o29, fabric_llpp3_araddr_s_o30, fabric_llpp3_araddr_s_o31, fabric_llpp3_araddr_s_o32, fabric_llpp3_arburst_s_o1, fabric_llpp3_arburst_s_o2, fabric_llpp3_arcache_s_o1, fabric_llpp3_arcache_s_o2, fabric_llpp3_arcache_s_o3, fabric_llpp3_arcache_s_o4, fabric_llpp3_arid_s_o1, fabric_llpp3_arid_s_o2, fabric_llpp3_arid_s_o3 -, fabric_llpp3_arid_s_o4, fabric_llpp3_arid_s_o5, fabric_llpp3_arid_s_o6, fabric_llpp3_arid_s_o7, fabric_llpp3_arid_s_o8, fabric_llpp3_arid_s_o9, fabric_llpp3_arid_s_o10, fabric_llpp3_arid_s_o11, fabric_llpp3_arid_s_o12, fabric_llpp3_arlen_s_o1, fabric_llpp3_arlen_s_o2, fabric_llpp3_arlen_s_o3, fabric_llpp3_arlen_s_o4, fabric_llpp3_arlen_s_o5, fabric_llpp3_arlen_s_o6, fabric_llpp3_arlen_s_o7, fabric_llpp3_arlen_s_o8, fabric_llpp3_arlock_s_o, fabric_llpp3_arprot_s_o1, fabric_llpp3_arprot_s_o2, fabric_llpp3_arprot_s_o3 -, fabric_llpp3_arqos_s_o1, fabric_llpp3_arqos_s_o2, fabric_llpp3_arqos_s_o3, fabric_llpp3_arqos_s_o4, fabric_llpp3_arsize_s_o1, fabric_llpp3_arsize_s_o2, fabric_llpp3_arsize_s_o3, fabric_llpp3_arvalid_s_o, fabric_llpp3_awaddr_s_o1, fabric_llpp3_awaddr_s_o2, fabric_llpp3_awaddr_s_o3, fabric_llpp3_awaddr_s_o4, fabric_llpp3_awaddr_s_o5, fabric_llpp3_awaddr_s_o6, fabric_llpp3_awaddr_s_o7, fabric_llpp3_awaddr_s_o8, fabric_llpp3_awaddr_s_o9, fabric_llpp3_awaddr_s_o10, fabric_llpp3_awaddr_s_o11, fabric_llpp3_awaddr_s_o12, fabric_llpp3_awaddr_s_o13 -, fabric_llpp3_awaddr_s_o14, fabric_llpp3_awaddr_s_o15, fabric_llpp3_awaddr_s_o16, fabric_llpp3_awaddr_s_o17, fabric_llpp3_awaddr_s_o18, fabric_llpp3_awaddr_s_o19, fabric_llpp3_awaddr_s_o20, fabric_llpp3_awaddr_s_o21, fabric_llpp3_awaddr_s_o22, fabric_llpp3_awaddr_s_o23, fabric_llpp3_awaddr_s_o24, fabric_llpp3_awaddr_s_o25, fabric_llpp3_awaddr_s_o26, fabric_llpp3_awaddr_s_o27, fabric_llpp3_awaddr_s_o28, fabric_llpp3_awaddr_s_o29, fabric_llpp3_awaddr_s_o30, fabric_llpp3_awaddr_s_o31, fabric_llpp3_awaddr_s_o32, fabric_llpp3_awburst_s_o1, fabric_llpp3_awburst_s_o2 -, fabric_llpp3_awcache_s_o1, fabric_llpp3_awcache_s_o2, fabric_llpp3_awcache_s_o3, fabric_llpp3_awcache_s_o4, fabric_llpp3_awid_s_o1, fabric_llpp3_awid_s_o2, fabric_llpp3_awid_s_o3, fabric_llpp3_awid_s_o4, fabric_llpp3_awid_s_o5, fabric_llpp3_awid_s_o6, fabric_llpp3_awid_s_o7, fabric_llpp3_awid_s_o8, fabric_llpp3_awid_s_o9, fabric_llpp3_awid_s_o10, fabric_llpp3_awid_s_o11, fabric_llpp3_awid_s_o12, fabric_llpp3_awlen_s_o1, fabric_llpp3_awlen_s_o2, fabric_llpp3_awlen_s_o3, fabric_llpp3_awlen_s_o4, fabric_llpp3_awlen_s_o5 -, fabric_llpp3_awlen_s_o6, fabric_llpp3_awlen_s_o7, fabric_llpp3_awlen_s_o8, fabric_llpp3_awlock_s_o, fabric_llpp3_awprot_s_o1, fabric_llpp3_awprot_s_o2, fabric_llpp3_awprot_s_o3, fabric_llpp3_awqos_s_o1, fabric_llpp3_awqos_s_o2, fabric_llpp3_awqos_s_o3, fabric_llpp3_awqos_s_o4, fabric_llpp3_awsize_s_o1, fabric_llpp3_awsize_s_o2, fabric_llpp3_awsize_s_o3, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o, fabric_llpp3_wdata_s_o1, fabric_llpp3_wdata_s_o2, fabric_llpp3_wdata_s_o3, fabric_llpp3_wdata_s_o4 -, fabric_llpp3_wdata_s_o5, fabric_llpp3_wdata_s_o6, fabric_llpp3_wdata_s_o7, fabric_llpp3_wdata_s_o8, fabric_llpp3_wdata_s_o9, fabric_llpp3_wdata_s_o10, fabric_llpp3_wdata_s_o11, fabric_llpp3_wdata_s_o12, fabric_llpp3_wdata_s_o13, fabric_llpp3_wdata_s_o14, fabric_llpp3_wdata_s_o15, fabric_llpp3_wdata_s_o16, fabric_llpp3_wdata_s_o17, fabric_llpp3_wdata_s_o18, fabric_llpp3_wdata_s_o19, fabric_llpp3_wdata_s_o20, fabric_llpp3_wdata_s_o21, fabric_llpp3_wdata_s_o22, fabric_llpp3_wdata_s_o23, fabric_llpp3_wdata_s_o24, fabric_llpp3_wdata_s_o25 -, fabric_llpp3_wdata_s_o26, fabric_llpp3_wdata_s_o27, fabric_llpp3_wdata_s_o28, fabric_llpp3_wdata_s_o29, fabric_llpp3_wdata_s_o30, fabric_llpp3_wdata_s_o31, fabric_llpp3_wdata_s_o32, fabric_llpp3_wlast_s_o, fabric_llpp3_wstrb_s_o1, fabric_llpp3_wstrb_s_o2, fabric_llpp3_wstrb_s_o3, fabric_llpp3_wstrb_s_o4, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bid_s_i1, fabric_llpp3_bid_s_i2, fabric_llpp3_bid_s_i3, fabric_llpp3_bid_s_i4, fabric_llpp3_bid_s_i5, fabric_llpp3_bid_s_i6 -, fabric_llpp3_bid_s_i7, fabric_llpp3_bid_s_i8, fabric_llpp3_bid_s_i9, fabric_llpp3_bid_s_i10, fabric_llpp3_bid_s_i11, fabric_llpp3_bid_s_i12, fabric_llpp3_bresp_s_i1, fabric_llpp3_bresp_s_i2, fabric_llpp3_bvalid_s_i, fabric_llpp3_rdata_s_i1, fabric_llpp3_rdata_s_i2, fabric_llpp3_rdata_s_i3, fabric_llpp3_rdata_s_i4, fabric_llpp3_rdata_s_i5, fabric_llpp3_rdata_s_i6, fabric_llpp3_rdata_s_i7, fabric_llpp3_rdata_s_i8, fabric_llpp3_rdata_s_i9, fabric_llpp3_rdata_s_i10, fabric_llpp3_rdata_s_i11, fabric_llpp3_rdata_s_i12 -, fabric_llpp3_rdata_s_i13, fabric_llpp3_rdata_s_i14, fabric_llpp3_rdata_s_i15, fabric_llpp3_rdata_s_i16, fabric_llpp3_rdata_s_i17, fabric_llpp3_rdata_s_i18, fabric_llpp3_rdata_s_i19, fabric_llpp3_rdata_s_i20, fabric_llpp3_rdata_s_i21, fabric_llpp3_rdata_s_i22, fabric_llpp3_rdata_s_i23, fabric_llpp3_rdata_s_i24, fabric_llpp3_rdata_s_i25, fabric_llpp3_rdata_s_i26, fabric_llpp3_rdata_s_i27, fabric_llpp3_rdata_s_i28, fabric_llpp3_rdata_s_i29, fabric_llpp3_rdata_s_i30, fabric_llpp3_rdata_s_i31, fabric_llpp3_rdata_s_i32, fabric_llpp3_rid_s_i1 -, fabric_llpp3_rid_s_i2, fabric_llpp3_rid_s_i3, fabric_llpp3_rid_s_i4, fabric_llpp3_rid_s_i5, fabric_llpp3_rid_s_i6, fabric_llpp3_rid_s_i7, fabric_llpp3_rid_s_i8, fabric_llpp3_rid_s_i9, fabric_llpp3_rid_s_i10, fabric_llpp3_rid_s_i11, fabric_llpp3_rid_s_i12, fabric_llpp3_rlast_s_i, fabric_llpp3_rresp_s_i1, fabric_llpp3_rresp_s_i2, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_pprdata_o1, fabric_qos_pprdata_o2, fabric_qos_pprdata_o3, fabric_qos_pprdata_o4, fabric_qos_pprdata_o5 -, fabric_qos_pprdata_o6, fabric_qos_pprdata_o7, fabric_qos_pprdata_o8, fabric_qos_pprdata_o9, fabric_qos_pprdata_o10, fabric_qos_pprdata_o11, fabric_qos_pprdata_o12, fabric_qos_pprdata_o13, fabric_qos_pprdata_o14, fabric_qos_pprdata_o15, fabric_qos_pprdata_o16, fabric_qos_pprdata_o17, fabric_qos_pprdata_o18, fabric_qos_pprdata_o19, fabric_qos_pprdata_o20, fabric_qos_pprdata_o21, fabric_qos_pprdata_o22, fabric_qos_pprdata_o23, fabric_qos_pprdata_o24, fabric_qos_pprdata_o25, fabric_qos_pprdata_o26 -, fabric_qos_pprdata_o27, fabric_qos_pprdata_o28, fabric_qos_pprdata_o29, fabric_qos_pprdata_o30, fabric_qos_pprdata_o31, fabric_qos_pprdata_o32, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppaddr_i1, fabric_qos_ppaddr_i2, fabric_qos_ppaddr_i3, fabric_qos_ppaddr_i4, fabric_qos_ppaddr_i5, fabric_qos_ppaddr_i6, fabric_qos_ppaddr_i7, fabric_qos_ppaddr_i8, fabric_qos_ppaddr_i9, fabric_qos_ppaddr_i10, fabric_qos_ppaddr_i11, fabric_qos_ppaddr_i12 -, fabric_qos_ppaddr_i13, fabric_qos_ppaddr_i14, fabric_qos_ppaddr_i15, fabric_qos_ppaddr_i16, fabric_qos_ppaddr_i17, fabric_qos_ppaddr_i18, fabric_qos_ppaddr_i19, fabric_qos_ppaddr_i20, fabric_qos_ppaddr_i21, fabric_qos_ppaddr_i22, fabric_qos_ppaddr_i23, fabric_qos_ppaddr_i24, fabric_qos_ppaddr_i25, fabric_qos_ppaddr_i26, fabric_qos_ppaddr_i27, fabric_qos_ppaddr_i28, fabric_qos_ppaddr_i29, fabric_qos_ppaddr_i30, fabric_qos_ppaddr_i31, fabric_qos_ppaddr_i32, fabric_qos_ppenable_i -, fabric_qos_ppwdata_i1, fabric_qos_ppwdata_i2, fabric_qos_ppwdata_i3, fabric_qos_ppwdata_i4, fabric_qos_ppwdata_i5, fabric_qos_ppwdata_i6, fabric_qos_ppwdata_i7, fabric_qos_ppwdata_i8, fabric_qos_ppwdata_i9, fabric_qos_ppwdata_i10, fabric_qos_ppwdata_i11, fabric_qos_ppwdata_i12, fabric_qos_ppwdata_i13, fabric_qos_ppwdata_i14, fabric_qos_ppwdata_i15, fabric_qos_ppwdata_i16, fabric_qos_ppwdata_i17, fabric_qos_ppwdata_i18, fabric_qos_ppwdata_i19, fabric_qos_ppwdata_i20, fabric_qos_ppwdata_i21 -, fabric_qos_ppwdata_i22, fabric_qos_ppwdata_i23, fabric_qos_ppwdata_i24, fabric_qos_ppwdata_i25, fabric_qos_ppwdata_i26, fabric_qos_ppwdata_i27, fabric_qos_ppwdata_i28, fabric_qos_ppwdata_i29, fabric_qos_ppwdata_i30, fabric_qos_ppwdata_i31, fabric_qos_ppwdata_i32, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_paddr_o1, fabric_tnd_fpga_apb_master_paddr_o2, fabric_tnd_fpga_apb_master_paddr_o3, fabric_tnd_fpga_apb_master_paddr_o4, fabric_tnd_fpga_apb_master_paddr_o5 -, fabric_tnd_fpga_apb_master_paddr_o6, fabric_tnd_fpga_apb_master_paddr_o7, fabric_tnd_fpga_apb_master_paddr_o8, fabric_tnd_fpga_apb_master_paddr_o9, fabric_tnd_fpga_apb_master_paddr_o10, fabric_tnd_fpga_apb_master_paddr_o11, fabric_tnd_fpga_apb_master_paddr_o12, fabric_tnd_fpga_apb_master_paddr_o13, fabric_tnd_fpga_apb_master_paddr_o14, fabric_tnd_fpga_apb_master_paddr_o15, fabric_tnd_fpga_apb_master_paddr_o16, fabric_tnd_fpga_apb_master_paddr_o17, fabric_tnd_fpga_apb_master_paddr_o18, fabric_tnd_fpga_apb_master_paddr_o19, fabric_tnd_fpga_apb_master_paddr_o20, fabric_tnd_fpga_apb_master_paddr_o21, fabric_tnd_fpga_apb_master_paddr_o22, fabric_tnd_fpga_apb_master_paddr_o23, fabric_tnd_fpga_apb_master_paddr_o24, fabric_tnd_fpga_apb_master_paddr_o25, fabric_tnd_fpga_apb_master_paddr_o26 -, fabric_tnd_fpga_apb_master_paddr_o27, fabric_tnd_fpga_apb_master_paddr_o28, fabric_tnd_fpga_apb_master_paddr_o29, fabric_tnd_fpga_apb_master_paddr_o30, fabric_tnd_fpga_apb_master_paddr_o31, fabric_tnd_fpga_apb_master_paddr_o32, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwdata_o1, fabric_tnd_fpga_apb_master_pwdata_o2, fabric_tnd_fpga_apb_master_pwdata_o3, fabric_tnd_fpga_apb_master_pwdata_o4, fabric_tnd_fpga_apb_master_pwdata_o5, fabric_tnd_fpga_apb_master_pwdata_o6, fabric_tnd_fpga_apb_master_pwdata_o7, fabric_tnd_fpga_apb_master_pwdata_o8, fabric_tnd_fpga_apb_master_pwdata_o9, fabric_tnd_fpga_apb_master_pwdata_o10, fabric_tnd_fpga_apb_master_pwdata_o11, fabric_tnd_fpga_apb_master_pwdata_o12, fabric_tnd_fpga_apb_master_pwdata_o13 -, fabric_tnd_fpga_apb_master_pwdata_o14, fabric_tnd_fpga_apb_master_pwdata_o15, fabric_tnd_fpga_apb_master_pwdata_o16, fabric_tnd_fpga_apb_master_pwdata_o17, fabric_tnd_fpga_apb_master_pwdata_o18, fabric_tnd_fpga_apb_master_pwdata_o19, fabric_tnd_fpga_apb_master_pwdata_o20, fabric_tnd_fpga_apb_master_pwdata_o21, fabric_tnd_fpga_apb_master_pwdata_o22, fabric_tnd_fpga_apb_master_pwdata_o23, fabric_tnd_fpga_apb_master_pwdata_o24, fabric_tnd_fpga_apb_master_pwdata_o25, fabric_tnd_fpga_apb_master_pwdata_o26, fabric_tnd_fpga_apb_master_pwdata_o27, fabric_tnd_fpga_apb_master_pwdata_o28, fabric_tnd_fpga_apb_master_pwdata_o29, fabric_tnd_fpga_apb_master_pwdata_o30, fabric_tnd_fpga_apb_master_pwdata_o31, fabric_tnd_fpga_apb_master_pwdata_o32, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o -, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_paddr_o1, fabric_tnd_hssl_apb_master_paddr_o2, fabric_tnd_hssl_apb_master_paddr_o3, fabric_tnd_hssl_apb_master_paddr_o4, fabric_tnd_hssl_apb_master_paddr_o5, fabric_tnd_hssl_apb_master_paddr_o6, fabric_tnd_hssl_apb_master_paddr_o7, fabric_tnd_hssl_apb_master_paddr_o8, fabric_tnd_hssl_apb_master_paddr_o9, fabric_tnd_hssl_apb_master_paddr_o10, fabric_tnd_hssl_apb_master_paddr_o11, fabric_tnd_hssl_apb_master_paddr_o12, fabric_tnd_hssl_apb_master_paddr_o13, fabric_tnd_hssl_apb_master_paddr_o14, fabric_tnd_hssl_apb_master_paddr_o15, fabric_tnd_hssl_apb_master_paddr_o16, fabric_tnd_hssl_apb_master_paddr_o17, fabric_tnd_hssl_apb_master_paddr_o18, fabric_tnd_hssl_apb_master_paddr_o19 -, fabric_tnd_hssl_apb_master_paddr_o20, fabric_tnd_hssl_apb_master_paddr_o21, fabric_tnd_hssl_apb_master_paddr_o22, fabric_tnd_hssl_apb_master_paddr_o23, fabric_tnd_hssl_apb_master_paddr_o24, fabric_tnd_hssl_apb_master_paddr_o25, fabric_tnd_hssl_apb_master_paddr_o26, fabric_tnd_hssl_apb_master_paddr_o27, fabric_tnd_hssl_apb_master_paddr_o28, fabric_tnd_hssl_apb_master_paddr_o29, fabric_tnd_hssl_apb_master_paddr_o30, fabric_tnd_hssl_apb_master_paddr_o31, fabric_tnd_hssl_apb_master_paddr_o32, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwdata_o1, fabric_tnd_hssl_apb_master_pwdata_o2, fabric_tnd_hssl_apb_master_pwdata_o3, fabric_tnd_hssl_apb_master_pwdata_o4, fabric_tnd_hssl_apb_master_pwdata_o5, fabric_tnd_hssl_apb_master_pwdata_o6 -, fabric_tnd_hssl_apb_master_pwdata_o7, fabric_tnd_hssl_apb_master_pwdata_o8, fabric_tnd_hssl_apb_master_pwdata_o9, fabric_tnd_hssl_apb_master_pwdata_o10, fabric_tnd_hssl_apb_master_pwdata_o11, fabric_tnd_hssl_apb_master_pwdata_o12, fabric_tnd_hssl_apb_master_pwdata_o13, fabric_tnd_hssl_apb_master_pwdata_o14, fabric_tnd_hssl_apb_master_pwdata_o15, fabric_tnd_hssl_apb_master_pwdata_o16, fabric_tnd_hssl_apb_master_pwdata_o17, fabric_tnd_hssl_apb_master_pwdata_o18, fabric_tnd_hssl_apb_master_pwdata_o19, fabric_tnd_hssl_apb_master_pwdata_o20, fabric_tnd_hssl_apb_master_pwdata_o21, fabric_tnd_hssl_apb_master_pwdata_o22, fabric_tnd_hssl_apb_master_pwdata_o23, fabric_tnd_hssl_apb_master_pwdata_o24, fabric_tnd_hssl_apb_master_pwdata_o25, fabric_tnd_hssl_apb_master_pwdata_o26, fabric_tnd_hssl_apb_master_pwdata_o27 -, fabric_tnd_hssl_apb_master_pwdata_o28, fabric_tnd_hssl_apb_master_pwdata_o29, fabric_tnd_hssl_apb_master_pwdata_o30, fabric_tnd_hssl_apb_master_pwdata_o31, fabric_tnd_hssl_apb_master_pwdata_o32, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atbytes_o1, fabric_tnd_hssl_atb_master_atbytes_o2, fabric_tnd_hssl_atb_master_atbytes_o3, fabric_tnd_hssl_atb_master_atbytes_o4, fabric_tnd_hssl_atb_master_atdata_o1, fabric_tnd_hssl_atb_master_atdata_o2, fabric_tnd_hssl_atb_master_atdata_o3, fabric_tnd_hssl_atb_master_atdata_o4, fabric_tnd_hssl_atb_master_atdata_o5, fabric_tnd_hssl_atb_master_atdata_o6, fabric_tnd_hssl_atb_master_atdata_o7, fabric_tnd_hssl_atb_master_atdata_o8, fabric_tnd_hssl_atb_master_atdata_o9, fabric_tnd_hssl_atb_master_atdata_o10 -, fabric_tnd_hssl_atb_master_atdata_o11, fabric_tnd_hssl_atb_master_atdata_o12, fabric_tnd_hssl_atb_master_atdata_o13, fabric_tnd_hssl_atb_master_atdata_o14, fabric_tnd_hssl_atb_master_atdata_o15, fabric_tnd_hssl_atb_master_atdata_o16, fabric_tnd_hssl_atb_master_atdata_o17, fabric_tnd_hssl_atb_master_atdata_o18, fabric_tnd_hssl_atb_master_atdata_o19, fabric_tnd_hssl_atb_master_atdata_o20, fabric_tnd_hssl_atb_master_atdata_o21, fabric_tnd_hssl_atb_master_atdata_o22, fabric_tnd_hssl_atb_master_atdata_o23, fabric_tnd_hssl_atb_master_atdata_o24, fabric_tnd_hssl_atb_master_atdata_o25, fabric_tnd_hssl_atb_master_atdata_o26, fabric_tnd_hssl_atb_master_atdata_o27, fabric_tnd_hssl_atb_master_atdata_o28, fabric_tnd_hssl_atb_master_atdata_o29, fabric_tnd_hssl_atb_master_atdata_o30, fabric_tnd_hssl_atb_master_atdata_o31 -, fabric_tnd_hssl_atb_master_atdata_o32, fabric_tnd_hssl_atb_master_atdata_o33, fabric_tnd_hssl_atb_master_atdata_o34, fabric_tnd_hssl_atb_master_atdata_o35, fabric_tnd_hssl_atb_master_atdata_o36, fabric_tnd_hssl_atb_master_atdata_o37, fabric_tnd_hssl_atb_master_atdata_o38, fabric_tnd_hssl_atb_master_atdata_o39, fabric_tnd_hssl_atb_master_atdata_o40, fabric_tnd_hssl_atb_master_atdata_o41, fabric_tnd_hssl_atb_master_atdata_o42, fabric_tnd_hssl_atb_master_atdata_o43, fabric_tnd_hssl_atb_master_atdata_o44, fabric_tnd_hssl_atb_master_atdata_o45, fabric_tnd_hssl_atb_master_atdata_o46, fabric_tnd_hssl_atb_master_atdata_o47, fabric_tnd_hssl_atb_master_atdata_o48, fabric_tnd_hssl_atb_master_atdata_o49, fabric_tnd_hssl_atb_master_atdata_o50, fabric_tnd_hssl_atb_master_atdata_o51, fabric_tnd_hssl_atb_master_atdata_o52 -, fabric_tnd_hssl_atb_master_atdata_o53, fabric_tnd_hssl_atb_master_atdata_o54, fabric_tnd_hssl_atb_master_atdata_o55, fabric_tnd_hssl_atb_master_atdata_o56, fabric_tnd_hssl_atb_master_atdata_o57, fabric_tnd_hssl_atb_master_atdata_o58, fabric_tnd_hssl_atb_master_atdata_o59, fabric_tnd_hssl_atb_master_atdata_o60, fabric_tnd_hssl_atb_master_atdata_o61, fabric_tnd_hssl_atb_master_atdata_o62, fabric_tnd_hssl_atb_master_atdata_o63, fabric_tnd_hssl_atb_master_atdata_o64, fabric_tnd_hssl_atb_master_atdata_o65, fabric_tnd_hssl_atb_master_atdata_o66, fabric_tnd_hssl_atb_master_atdata_o67, fabric_tnd_hssl_atb_master_atdata_o68, fabric_tnd_hssl_atb_master_atdata_o69, fabric_tnd_hssl_atb_master_atdata_o70, fabric_tnd_hssl_atb_master_atdata_o71, fabric_tnd_hssl_atb_master_atdata_o72, fabric_tnd_hssl_atb_master_atdata_o73 -, fabric_tnd_hssl_atb_master_atdata_o74, fabric_tnd_hssl_atb_master_atdata_o75, fabric_tnd_hssl_atb_master_atdata_o76, fabric_tnd_hssl_atb_master_atdata_o77, fabric_tnd_hssl_atb_master_atdata_o78, fabric_tnd_hssl_atb_master_atdata_o79, fabric_tnd_hssl_atb_master_atdata_o80, fabric_tnd_hssl_atb_master_atdata_o81, fabric_tnd_hssl_atb_master_atdata_o82, fabric_tnd_hssl_atb_master_atdata_o83, fabric_tnd_hssl_atb_master_atdata_o84, fabric_tnd_hssl_atb_master_atdata_o85, fabric_tnd_hssl_atb_master_atdata_o86, fabric_tnd_hssl_atb_master_atdata_o87, fabric_tnd_hssl_atb_master_atdata_o88, fabric_tnd_hssl_atb_master_atdata_o89, fabric_tnd_hssl_atb_master_atdata_o90, fabric_tnd_hssl_atb_master_atdata_o91, fabric_tnd_hssl_atb_master_atdata_o92, fabric_tnd_hssl_atb_master_atdata_o93, fabric_tnd_hssl_atb_master_atdata_o94 -, fabric_tnd_hssl_atb_master_atdata_o95, fabric_tnd_hssl_atb_master_atdata_o96, fabric_tnd_hssl_atb_master_atdata_o97, fabric_tnd_hssl_atb_master_atdata_o98, fabric_tnd_hssl_atb_master_atdata_o99, fabric_tnd_hssl_atb_master_atdata_o100, fabric_tnd_hssl_atb_master_atdata_o101, fabric_tnd_hssl_atb_master_atdata_o102, fabric_tnd_hssl_atb_master_atdata_o103, fabric_tnd_hssl_atb_master_atdata_o104, fabric_tnd_hssl_atb_master_atdata_o105, fabric_tnd_hssl_atb_master_atdata_o106, fabric_tnd_hssl_atb_master_atdata_o107, fabric_tnd_hssl_atb_master_atdata_o108, fabric_tnd_hssl_atb_master_atdata_o109, fabric_tnd_hssl_atb_master_atdata_o110, fabric_tnd_hssl_atb_master_atdata_o111, fabric_tnd_hssl_atb_master_atdata_o112, fabric_tnd_hssl_atb_master_atdata_o113, fabric_tnd_hssl_atb_master_atdata_o114, fabric_tnd_hssl_atb_master_atdata_o115 -, fabric_tnd_hssl_atb_master_atdata_o116, fabric_tnd_hssl_atb_master_atdata_o117, fabric_tnd_hssl_atb_master_atdata_o118, fabric_tnd_hssl_atb_master_atdata_o119, fabric_tnd_hssl_atb_master_atdata_o120, fabric_tnd_hssl_atb_master_atdata_o121, fabric_tnd_hssl_atb_master_atdata_o122, fabric_tnd_hssl_atb_master_atdata_o123, fabric_tnd_hssl_atb_master_atdata_o124, fabric_tnd_hssl_atb_master_atdata_o125, fabric_tnd_hssl_atb_master_atdata_o126, fabric_tnd_hssl_atb_master_atdata_o127, fabric_tnd_hssl_atb_master_atdata_o128, fabric_tnd_hssl_atb_master_atid_o1, fabric_tnd_hssl_atb_master_atid_o2, fabric_tnd_hssl_atb_master_atid_o3, fabric_tnd_hssl_atb_master_atid_o4, fabric_tnd_hssl_atb_master_atid_o5, fabric_tnd_hssl_atb_master_atid_o6, fabric_tnd_hssl_atb_master_atid_o7, fabric_tnd_hssl_atb_master_atvalid_o -, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_trace_data_traceoutportintf_o1, fabric_tnd_trace_data_traceoutportintf_o2, fabric_tnd_trace_data_traceoutportintf_o3, fabric_tnd_trace_data_traceoutportintf_o4, fabric_tnd_trace_data_traceoutportintf_o5, fabric_tnd_trace_data_traceoutportintf_o6, fabric_tnd_trace_data_traceoutportintf_o7, fabric_tnd_trace_data_traceoutportintf_o8, fabric_tnd_trace_data_traceoutportintf_o9, fabric_tnd_trace_data_traceoutportintf_o10, fabric_tnd_trace_data_traceoutportintf_o11, fabric_tnd_trace_data_traceoutportintf_o12, fabric_tnd_trace_data_traceoutportintf_o13, fabric_tnd_trace_data_traceoutportintf_o14, fabric_tnd_trace_data_traceoutportintf_o15, fabric_tnd_trace_data_traceoutportintf_o16, fabric_tnd_trace_data_traceoutportintf_o17, fabric_tnd_trace_data_traceoutportintf_o18, fabric_tnd_trace_data_traceoutportintf_o19 -, fabric_tnd_trace_data_traceoutportintf_o20, fabric_tnd_trace_data_traceoutportintf_o21, fabric_tnd_trace_data_traceoutportintf_o22, fabric_tnd_trace_data_traceoutportintf_o23, fabric_tnd_trace_data_traceoutportintf_o24, fabric_tnd_trace_data_traceoutportintf_o25, fabric_tnd_trace_data_traceoutportintf_o26, fabric_tnd_trace_data_traceoutportintf_o27, fabric_tnd_trace_data_traceoutportintf_o28, fabric_tnd_trace_data_traceoutportintf_o29, fabric_tnd_trace_data_traceoutportintf_o30, fabric_tnd_trace_data_traceoutportintf_o31, fabric_tnd_trace_data_traceoutportintf_o32, fabric_tsvalue_tsgen_fpga_o1, fabric_tsvalue_tsgen_fpga_o2, fabric_tsvalue_tsgen_fpga_o3, fabric_tsvalue_tsgen_fpga_o4, fabric_tsvalue_tsgen_fpga_o5, fabric_tsvalue_tsgen_fpga_o6, fabric_tsvalue_tsgen_fpga_o7, fabric_tsvalue_tsgen_fpga_o8 -, fabric_tsvalue_tsgen_fpga_o9, fabric_tsvalue_tsgen_fpga_o10, fabric_tsvalue_tsgen_fpga_o11, fabric_tsvalue_tsgen_fpga_o12, fabric_tsvalue_tsgen_fpga_o13, fabric_tsvalue_tsgen_fpga_o14, fabric_tsvalue_tsgen_fpga_o15, fabric_tsvalue_tsgen_fpga_o16, fabric_tsvalue_tsgen_fpga_o17, fabric_tsvalue_tsgen_fpga_o18, fabric_tsvalue_tsgen_fpga_o19, fabric_tsvalue_tsgen_fpga_o20, fabric_tsvalue_tsgen_fpga_o21, fabric_tsvalue_tsgen_fpga_o22, fabric_tsvalue_tsgen_fpga_o23, fabric_tsvalue_tsgen_fpga_o24, fabric_tsvalue_tsgen_fpga_o25, fabric_tsvalue_tsgen_fpga_o26, fabric_tsvalue_tsgen_fpga_o27, fabric_tsvalue_tsgen_fpga_o28, fabric_tsvalue_tsgen_fpga_o29 -, fabric_tsvalue_tsgen_fpga_o30, fabric_tsvalue_tsgen_fpga_o31, fabric_tsvalue_tsgen_fpga_o32, fabric_tsvalue_tsgen_fpga_o33, fabric_tsvalue_tsgen_fpga_o34, fabric_tsvalue_tsgen_fpga_o35, fabric_tsvalue_tsgen_fpga_o36, fabric_tsvalue_tsgen_fpga_o37, fabric_tsvalue_tsgen_fpga_o38, fabric_tsvalue_tsgen_fpga_o39, fabric_tsvalue_tsgen_fpga_o40, fabric_tsvalue_tsgen_fpga_o41, fabric_tsvalue_tsgen_fpga_o42, fabric_tsvalue_tsgen_fpga_o43, fabric_tsvalue_tsgen_fpga_o44, fabric_tsvalue_tsgen_fpga_o45, fabric_tsvalue_tsgen_fpga_o46, fabric_tsvalue_tsgen_fpga_o47, fabric_tsvalue_tsgen_fpga_o48, fabric_tsvalue_tsgen_fpga_o49, fabric_tsvalue_tsgen_fpga_o50 -, fabric_tsvalue_tsgen_fpga_o51, fabric_tsvalue_tsgen_fpga_o52, fabric_tsvalue_tsgen_fpga_o53, fabric_tsvalue_tsgen_fpga_o54, fabric_tsvalue_tsgen_fpga_o55, fabric_tsvalue_tsgen_fpga_o56, fabric_tsvalue_tsgen_fpga_o57, fabric_tsvalue_tsgen_fpga_o58, fabric_tsvalue_tsgen_fpga_o59, fabric_tsvalue_tsgen_fpga_o60, fabric_tsvalue_tsgen_fpga_o61, fabric_tsvalue_tsgen_fpga_o62, fabric_tsvalue_tsgen_fpga_o63, fabric_tsvalue_tsgen_fpga_o64, fabric_tnd_fpga_apb_master_prdata_i1, fabric_tnd_fpga_apb_master_prdata_i2, fabric_tnd_fpga_apb_master_prdata_i3, fabric_tnd_fpga_apb_master_prdata_i4, fabric_tnd_fpga_apb_master_prdata_i5, fabric_tnd_fpga_apb_master_prdata_i6, fabric_tnd_fpga_apb_master_prdata_i7 -, fabric_tnd_fpga_apb_master_prdata_i8, fabric_tnd_fpga_apb_master_prdata_i9, fabric_tnd_fpga_apb_master_prdata_i10, fabric_tnd_fpga_apb_master_prdata_i11, fabric_tnd_fpga_apb_master_prdata_i12, fabric_tnd_fpga_apb_master_prdata_i13, fabric_tnd_fpga_apb_master_prdata_i14, fabric_tnd_fpga_apb_master_prdata_i15, fabric_tnd_fpga_apb_master_prdata_i16, fabric_tnd_fpga_apb_master_prdata_i17, fabric_tnd_fpga_apb_master_prdata_i18, fabric_tnd_fpga_apb_master_prdata_i19, fabric_tnd_fpga_apb_master_prdata_i20, fabric_tnd_fpga_apb_master_prdata_i21, fabric_tnd_fpga_apb_master_prdata_i22, fabric_tnd_fpga_apb_master_prdata_i23, fabric_tnd_fpga_apb_master_prdata_i24, fabric_tnd_fpga_apb_master_prdata_i25, fabric_tnd_fpga_apb_master_prdata_i26, fabric_tnd_fpga_apb_master_prdata_i27, fabric_tnd_fpga_apb_master_prdata_i28 -, fabric_tnd_fpga_apb_master_prdata_i29, fabric_tnd_fpga_apb_master_prdata_i30, fabric_tnd_fpga_apb_master_prdata_i31, fabric_tnd_fpga_apb_master_prdata_i32, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atbytes_i1, fabric_tnd_fpga_atb_master_atbytes_i2, fabric_tnd_fpga_atb_master_atbytes_i3, fabric_tnd_fpga_atb_master_atbytes_i4, fabric_tnd_fpga_atb_master_atdata_i1, fabric_tnd_fpga_atb_master_atdata_i2, fabric_tnd_fpga_atb_master_atdata_i3, fabric_tnd_fpga_atb_master_atdata_i4, fabric_tnd_fpga_atb_master_atdata_i5, fabric_tnd_fpga_atb_master_atdata_i6, fabric_tnd_fpga_atb_master_atdata_i7, fabric_tnd_fpga_atb_master_atdata_i8, fabric_tnd_fpga_atb_master_atdata_i9, fabric_tnd_fpga_atb_master_atdata_i10 -, fabric_tnd_fpga_atb_master_atdata_i11, fabric_tnd_fpga_atb_master_atdata_i12, fabric_tnd_fpga_atb_master_atdata_i13, fabric_tnd_fpga_atb_master_atdata_i14, fabric_tnd_fpga_atb_master_atdata_i15, fabric_tnd_fpga_atb_master_atdata_i16, fabric_tnd_fpga_atb_master_atdata_i17, fabric_tnd_fpga_atb_master_atdata_i18, fabric_tnd_fpga_atb_master_atdata_i19, fabric_tnd_fpga_atb_master_atdata_i20, fabric_tnd_fpga_atb_master_atdata_i21, fabric_tnd_fpga_atb_master_atdata_i22, fabric_tnd_fpga_atb_master_atdata_i23, fabric_tnd_fpga_atb_master_atdata_i24, fabric_tnd_fpga_atb_master_atdata_i25, fabric_tnd_fpga_atb_master_atdata_i26, fabric_tnd_fpga_atb_master_atdata_i27, fabric_tnd_fpga_atb_master_atdata_i28, fabric_tnd_fpga_atb_master_atdata_i29, fabric_tnd_fpga_atb_master_atdata_i30, fabric_tnd_fpga_atb_master_atdata_i31 -, fabric_tnd_fpga_atb_master_atdata_i32, fabric_tnd_fpga_atb_master_atdata_i33, fabric_tnd_fpga_atb_master_atdata_i34, fabric_tnd_fpga_atb_master_atdata_i35, fabric_tnd_fpga_atb_master_atdata_i36, fabric_tnd_fpga_atb_master_atdata_i37, fabric_tnd_fpga_atb_master_atdata_i38, fabric_tnd_fpga_atb_master_atdata_i39, fabric_tnd_fpga_atb_master_atdata_i40, fabric_tnd_fpga_atb_master_atdata_i41, fabric_tnd_fpga_atb_master_atdata_i42, fabric_tnd_fpga_atb_master_atdata_i43, fabric_tnd_fpga_atb_master_atdata_i44, fabric_tnd_fpga_atb_master_atdata_i45, fabric_tnd_fpga_atb_master_atdata_i46, fabric_tnd_fpga_atb_master_atdata_i47, fabric_tnd_fpga_atb_master_atdata_i48, fabric_tnd_fpga_atb_master_atdata_i49, fabric_tnd_fpga_atb_master_atdata_i50, fabric_tnd_fpga_atb_master_atdata_i51, fabric_tnd_fpga_atb_master_atdata_i52 -, fabric_tnd_fpga_atb_master_atdata_i53, fabric_tnd_fpga_atb_master_atdata_i54, fabric_tnd_fpga_atb_master_atdata_i55, fabric_tnd_fpga_atb_master_atdata_i56, fabric_tnd_fpga_atb_master_atdata_i57, fabric_tnd_fpga_atb_master_atdata_i58, fabric_tnd_fpga_atb_master_atdata_i59, fabric_tnd_fpga_atb_master_atdata_i60, fabric_tnd_fpga_atb_master_atdata_i61, fabric_tnd_fpga_atb_master_atdata_i62, fabric_tnd_fpga_atb_master_atdata_i63, fabric_tnd_fpga_atb_master_atdata_i64, fabric_tnd_fpga_atb_master_atdata_i65, fabric_tnd_fpga_atb_master_atdata_i66, fabric_tnd_fpga_atb_master_atdata_i67, fabric_tnd_fpga_atb_master_atdata_i68, fabric_tnd_fpga_atb_master_atdata_i69, fabric_tnd_fpga_atb_master_atdata_i70, fabric_tnd_fpga_atb_master_atdata_i71, fabric_tnd_fpga_atb_master_atdata_i72, fabric_tnd_fpga_atb_master_atdata_i73 -, fabric_tnd_fpga_atb_master_atdata_i74, fabric_tnd_fpga_atb_master_atdata_i75, fabric_tnd_fpga_atb_master_atdata_i76, fabric_tnd_fpga_atb_master_atdata_i77, fabric_tnd_fpga_atb_master_atdata_i78, fabric_tnd_fpga_atb_master_atdata_i79, fabric_tnd_fpga_atb_master_atdata_i80, fabric_tnd_fpga_atb_master_atdata_i81, fabric_tnd_fpga_atb_master_atdata_i82, fabric_tnd_fpga_atb_master_atdata_i83, fabric_tnd_fpga_atb_master_atdata_i84, fabric_tnd_fpga_atb_master_atdata_i85, fabric_tnd_fpga_atb_master_atdata_i86, fabric_tnd_fpga_atb_master_atdata_i87, fabric_tnd_fpga_atb_master_atdata_i88, fabric_tnd_fpga_atb_master_atdata_i89, fabric_tnd_fpga_atb_master_atdata_i90, fabric_tnd_fpga_atb_master_atdata_i91, fabric_tnd_fpga_atb_master_atdata_i92, fabric_tnd_fpga_atb_master_atdata_i93, fabric_tnd_fpga_atb_master_atdata_i94 -, fabric_tnd_fpga_atb_master_atdata_i95, fabric_tnd_fpga_atb_master_atdata_i96, fabric_tnd_fpga_atb_master_atdata_i97, fabric_tnd_fpga_atb_master_atdata_i98, fabric_tnd_fpga_atb_master_atdata_i99, fabric_tnd_fpga_atb_master_atdata_i100, fabric_tnd_fpga_atb_master_atdata_i101, fabric_tnd_fpga_atb_master_atdata_i102, fabric_tnd_fpga_atb_master_atdata_i103, fabric_tnd_fpga_atb_master_atdata_i104, fabric_tnd_fpga_atb_master_atdata_i105, fabric_tnd_fpga_atb_master_atdata_i106, fabric_tnd_fpga_atb_master_atdata_i107, fabric_tnd_fpga_atb_master_atdata_i108, fabric_tnd_fpga_atb_master_atdata_i109, fabric_tnd_fpga_atb_master_atdata_i110, fabric_tnd_fpga_atb_master_atdata_i111, fabric_tnd_fpga_atb_master_atdata_i112, fabric_tnd_fpga_atb_master_atdata_i113, fabric_tnd_fpga_atb_master_atdata_i114, fabric_tnd_fpga_atb_master_atdata_i115 -, fabric_tnd_fpga_atb_master_atdata_i116, fabric_tnd_fpga_atb_master_atdata_i117, fabric_tnd_fpga_atb_master_atdata_i118, fabric_tnd_fpga_atb_master_atdata_i119, fabric_tnd_fpga_atb_master_atdata_i120, fabric_tnd_fpga_atb_master_atdata_i121, fabric_tnd_fpga_atb_master_atdata_i122, fabric_tnd_fpga_atb_master_atdata_i123, fabric_tnd_fpga_atb_master_atdata_i124, fabric_tnd_fpga_atb_master_atdata_i125, fabric_tnd_fpga_atb_master_atdata_i126, fabric_tnd_fpga_atb_master_atdata_i127, fabric_tnd_fpga_atb_master_atdata_i128, fabric_tnd_fpga_atb_master_atid_i1, fabric_tnd_fpga_atb_master_atid_i2, fabric_tnd_fpga_atb_master_atid_i3, fabric_tnd_fpga_atb_master_atid_i4, fabric_tnd_fpga_atb_master_atid_i5, fabric_tnd_fpga_atb_master_atid_i6, fabric_tnd_fpga_atb_master_atid_i7, fabric_tnd_fpga_atb_master_atvalid_i -, fabric_tnd_hssl_apb_master_prdata_i1, fabric_tnd_hssl_apb_master_prdata_i2, fabric_tnd_hssl_apb_master_prdata_i3, fabric_tnd_hssl_apb_master_prdata_i4, fabric_tnd_hssl_apb_master_prdata_i5, fabric_tnd_hssl_apb_master_prdata_i6, fabric_tnd_hssl_apb_master_prdata_i7, fabric_tnd_hssl_apb_master_prdata_i8, fabric_tnd_hssl_apb_master_prdata_i9, fabric_tnd_hssl_apb_master_prdata_i10, fabric_tnd_hssl_apb_master_prdata_i11, fabric_tnd_hssl_apb_master_prdata_i12, fabric_tnd_hssl_apb_master_prdata_i13, fabric_tnd_hssl_apb_master_prdata_i14, fabric_tnd_hssl_apb_master_prdata_i15, fabric_tnd_hssl_apb_master_prdata_i16, fabric_tnd_hssl_apb_master_prdata_i17, fabric_tnd_hssl_apb_master_prdata_i18, fabric_tnd_hssl_apb_master_prdata_i19, fabric_tnd_hssl_apb_master_prdata_i20, fabric_tnd_hssl_apb_master_prdata_i21 -, fabric_tnd_hssl_apb_master_prdata_i22, fabric_tnd_hssl_apb_master_prdata_i23, fabric_tnd_hssl_apb_master_prdata_i24, fabric_tnd_hssl_apb_master_prdata_i25, fabric_tnd_hssl_apb_master_prdata_i26, fabric_tnd_hssl_apb_master_prdata_i27, fabric_tnd_hssl_apb_master_prdata_i28, fabric_tnd_hssl_apb_master_prdata_i29, fabric_tnd_hssl_apb_master_prdata_i30, fabric_tnd_hssl_apb_master_prdata_i31, fabric_tnd_hssl_apb_master_prdata_i32, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o -, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_tst_pll_lock_o1, fabric_tst_pll_lock_o2, fabric_tst_pll_lock_o3, fabric_tst_pll_lock_o4, fabric_tst_pll_lock_o5, fabric_tst_pll_lock_o6, fabric_tst_pll_lock_o7, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i -, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i1, fabric_enable_TMR_i2, fabric_enable_TMR_i3); - input fabric_enable_TMR_i1; - input fabric_enable_TMR_i2; - input fabric_enable_TMR_i3; - input fabric_erom_fpga_cpu0_dbgen_i; - input fabric_erom_fpga_cpu0_hiden_i; - input fabric_erom_fpga_cpu0_hniden_i; - input fabric_erom_fpga_cpu0_niden_i; - input fabric_erom_fpga_cpu1_dbgen_i; - input fabric_erom_fpga_cpu1_hiden_i; - input fabric_erom_fpga_cpu1_hniden_i; - input fabric_erom_fpga_cpu1_niden_i; - input fabric_erom_fpga_cpu2_dbgen_i; - input fabric_erom_fpga_cpu2_hiden_i; - input fabric_erom_fpga_cpu2_hniden_i; - input fabric_erom_fpga_cpu2_niden_i; - input fabric_erom_fpga_cpu3_dbgen_i; - input fabric_erom_fpga_cpu3_hiden_i; - input fabric_erom_fpga_cpu3_hniden_i; - input fabric_erom_fpga_cpu3_niden_i; - input fabric_erom_fpga_cs_dbgen_i; - input fabric_erom_fpga_cs_deviceen_i; - input fabric_erom_fpga_cs_niden_i; - input fabric_erom_fpga_cs_rst_n_i; - input fabric_erom_fpga_debug_en_i; - input fabric_fpga_araddr_axi_m1_i1; - input fabric_fpga_araddr_axi_m1_i10; - input fabric_fpga_araddr_axi_m1_i11; - input fabric_fpga_araddr_axi_m1_i12; - input fabric_fpga_araddr_axi_m1_i13; - input fabric_fpga_araddr_axi_m1_i14; - input fabric_fpga_araddr_axi_m1_i15; - input fabric_fpga_araddr_axi_m1_i16; - input fabric_fpga_araddr_axi_m1_i17; - input fabric_fpga_araddr_axi_m1_i18; - input fabric_fpga_araddr_axi_m1_i19; - input fabric_fpga_araddr_axi_m1_i2; - input fabric_fpga_araddr_axi_m1_i20; - input fabric_fpga_araddr_axi_m1_i21; - input fabric_fpga_araddr_axi_m1_i22; - input fabric_fpga_araddr_axi_m1_i23; - input fabric_fpga_araddr_axi_m1_i24; - input fabric_fpga_araddr_axi_m1_i25; - input fabric_fpga_araddr_axi_m1_i26; - input fabric_fpga_araddr_axi_m1_i27; - input fabric_fpga_araddr_axi_m1_i28; - input fabric_fpga_araddr_axi_m1_i29; - input fabric_fpga_araddr_axi_m1_i3; - input fabric_fpga_araddr_axi_m1_i30; - input fabric_fpga_araddr_axi_m1_i31; - input fabric_fpga_araddr_axi_m1_i32; - input fabric_fpga_araddr_axi_m1_i33; - input fabric_fpga_araddr_axi_m1_i34; - input fabric_fpga_araddr_axi_m1_i35; - input fabric_fpga_araddr_axi_m1_i36; - input fabric_fpga_araddr_axi_m1_i37; - input fabric_fpga_araddr_axi_m1_i38; - input fabric_fpga_araddr_axi_m1_i39; - input fabric_fpga_araddr_axi_m1_i4; - input fabric_fpga_araddr_axi_m1_i40; - input fabric_fpga_araddr_axi_m1_i5; - input fabric_fpga_araddr_axi_m1_i6; - input fabric_fpga_araddr_axi_m1_i7; - input fabric_fpga_araddr_axi_m1_i8; - input fabric_fpga_araddr_axi_m1_i9; - input fabric_fpga_araddr_axi_m2_i1; - input fabric_fpga_araddr_axi_m2_i10; - input fabric_fpga_araddr_axi_m2_i11; - input fabric_fpga_araddr_axi_m2_i12; - input fabric_fpga_araddr_axi_m2_i13; - input fabric_fpga_araddr_axi_m2_i14; - input fabric_fpga_araddr_axi_m2_i15; - input fabric_fpga_araddr_axi_m2_i16; - input fabric_fpga_araddr_axi_m2_i17; - input fabric_fpga_araddr_axi_m2_i18; - input fabric_fpga_araddr_axi_m2_i19; - input fabric_fpga_araddr_axi_m2_i2; - input fabric_fpga_araddr_axi_m2_i20; - input fabric_fpga_araddr_axi_m2_i21; - input fabric_fpga_araddr_axi_m2_i22; - input fabric_fpga_araddr_axi_m2_i23; - input fabric_fpga_araddr_axi_m2_i24; - input fabric_fpga_araddr_axi_m2_i25; - input fabric_fpga_araddr_axi_m2_i26; - input fabric_fpga_araddr_axi_m2_i27; - input fabric_fpga_araddr_axi_m2_i28; - input fabric_fpga_araddr_axi_m2_i29; - input fabric_fpga_araddr_axi_m2_i3; - input fabric_fpga_araddr_axi_m2_i30; - input fabric_fpga_araddr_axi_m2_i31; - input fabric_fpga_araddr_axi_m2_i32; - input fabric_fpga_araddr_axi_m2_i33; - input fabric_fpga_araddr_axi_m2_i34; - input fabric_fpga_araddr_axi_m2_i35; - input fabric_fpga_araddr_axi_m2_i36; - input fabric_fpga_araddr_axi_m2_i37; - input fabric_fpga_araddr_axi_m2_i38; - input fabric_fpga_araddr_axi_m2_i39; - input fabric_fpga_araddr_axi_m2_i4; - input fabric_fpga_araddr_axi_m2_i40; - input fabric_fpga_araddr_axi_m2_i5; - input fabric_fpga_araddr_axi_m2_i6; - input fabric_fpga_araddr_axi_m2_i7; - input fabric_fpga_araddr_axi_m2_i8; - input fabric_fpga_araddr_axi_m2_i9; - output fabric_fpga_araddr_axi_s1_o1; - output fabric_fpga_araddr_axi_s1_o10; - output fabric_fpga_araddr_axi_s1_o11; - output fabric_fpga_araddr_axi_s1_o12; - output fabric_fpga_araddr_axi_s1_o13; - output fabric_fpga_araddr_axi_s1_o14; - output fabric_fpga_araddr_axi_s1_o15; - output fabric_fpga_araddr_axi_s1_o16; - output fabric_fpga_araddr_axi_s1_o17; - output fabric_fpga_araddr_axi_s1_o18; - output fabric_fpga_araddr_axi_s1_o19; - output fabric_fpga_araddr_axi_s1_o2; - output fabric_fpga_araddr_axi_s1_o20; - output fabric_fpga_araddr_axi_s1_o21; - output fabric_fpga_araddr_axi_s1_o22; - output fabric_fpga_araddr_axi_s1_o23; - output fabric_fpga_araddr_axi_s1_o24; - output fabric_fpga_araddr_axi_s1_o25; - output fabric_fpga_araddr_axi_s1_o26; - output fabric_fpga_araddr_axi_s1_o27; - output fabric_fpga_araddr_axi_s1_o28; - output fabric_fpga_araddr_axi_s1_o29; - output fabric_fpga_araddr_axi_s1_o3; - output fabric_fpga_araddr_axi_s1_o30; - output fabric_fpga_araddr_axi_s1_o31; - output fabric_fpga_araddr_axi_s1_o32; - output fabric_fpga_araddr_axi_s1_o33; - output fabric_fpga_araddr_axi_s1_o34; - output fabric_fpga_araddr_axi_s1_o35; - output fabric_fpga_araddr_axi_s1_o36; - output fabric_fpga_araddr_axi_s1_o37; - output fabric_fpga_araddr_axi_s1_o38; - output fabric_fpga_araddr_axi_s1_o39; - output fabric_fpga_araddr_axi_s1_o4; - output fabric_fpga_araddr_axi_s1_o40; - output fabric_fpga_araddr_axi_s1_o5; - output fabric_fpga_araddr_axi_s1_o6; - output fabric_fpga_araddr_axi_s1_o7; - output fabric_fpga_araddr_axi_s1_o8; - output fabric_fpga_araddr_axi_s1_o9; - output fabric_fpga_araddr_axi_s2_o1; - output fabric_fpga_araddr_axi_s2_o10; - output fabric_fpga_araddr_axi_s2_o11; - output fabric_fpga_araddr_axi_s2_o12; - output fabric_fpga_araddr_axi_s2_o13; - output fabric_fpga_araddr_axi_s2_o14; - output fabric_fpga_araddr_axi_s2_o15; - output fabric_fpga_araddr_axi_s2_o16; - output fabric_fpga_araddr_axi_s2_o17; - output fabric_fpga_araddr_axi_s2_o18; - output fabric_fpga_araddr_axi_s2_o19; - output fabric_fpga_araddr_axi_s2_o2; - output fabric_fpga_araddr_axi_s2_o20; - output fabric_fpga_araddr_axi_s2_o21; - output fabric_fpga_araddr_axi_s2_o22; - output fabric_fpga_araddr_axi_s2_o23; - output fabric_fpga_araddr_axi_s2_o24; - output fabric_fpga_araddr_axi_s2_o25; - output fabric_fpga_araddr_axi_s2_o26; - output fabric_fpga_araddr_axi_s2_o27; - output fabric_fpga_araddr_axi_s2_o28; - output fabric_fpga_araddr_axi_s2_o29; - output fabric_fpga_araddr_axi_s2_o3; - output fabric_fpga_araddr_axi_s2_o30; - output fabric_fpga_araddr_axi_s2_o31; - output fabric_fpga_araddr_axi_s2_o32; - output fabric_fpga_araddr_axi_s2_o33; - output fabric_fpga_araddr_axi_s2_o34; - output fabric_fpga_araddr_axi_s2_o35; - output fabric_fpga_araddr_axi_s2_o36; - output fabric_fpga_araddr_axi_s2_o37; - output fabric_fpga_araddr_axi_s2_o38; - output fabric_fpga_araddr_axi_s2_o39; - output fabric_fpga_araddr_axi_s2_o4; - output fabric_fpga_araddr_axi_s2_o40; - output fabric_fpga_araddr_axi_s2_o5; - output fabric_fpga_araddr_axi_s2_o6; - output fabric_fpga_araddr_axi_s2_o7; - output fabric_fpga_araddr_axi_s2_o8; - output fabric_fpga_araddr_axi_s2_o9; - input fabric_fpga_arburst_axi_m1_i1; - input fabric_fpga_arburst_axi_m1_i2; - input fabric_fpga_arburst_axi_m2_i1; - input fabric_fpga_arburst_axi_m2_i2; - output fabric_fpga_arburst_axi_s1_o1; - output fabric_fpga_arburst_axi_s1_o2; - output fabric_fpga_arburst_axi_s2_o1; - output fabric_fpga_arburst_axi_s2_o2; - input fabric_fpga_arcache_axi_m1_i1; - input fabric_fpga_arcache_axi_m1_i2; - input fabric_fpga_arcache_axi_m1_i3; - input fabric_fpga_arcache_axi_m1_i4; - input fabric_fpga_arcache_axi_m2_i1; - input fabric_fpga_arcache_axi_m2_i2; - input fabric_fpga_arcache_axi_m2_i3; - input fabric_fpga_arcache_axi_m2_i4; - output fabric_fpga_arcache_axi_s1_o1; - output fabric_fpga_arcache_axi_s1_o2; - output fabric_fpga_arcache_axi_s1_o3; - output fabric_fpga_arcache_axi_s1_o4; - output fabric_fpga_arcache_axi_s2_o1; - output fabric_fpga_arcache_axi_s2_o2; - output fabric_fpga_arcache_axi_s2_o3; - output fabric_fpga_arcache_axi_s2_o4; - input fabric_fpga_arid_axi_m1_i1; - input fabric_fpga_arid_axi_m1_i2; - input fabric_fpga_arid_axi_m1_i3; - input fabric_fpga_arid_axi_m1_i4; - input fabric_fpga_arid_axi_m1_i5; - input fabric_fpga_arid_axi_m2_i1; - input fabric_fpga_arid_axi_m2_i2; - input fabric_fpga_arid_axi_m2_i3; - input fabric_fpga_arid_axi_m2_i4; - input fabric_fpga_arid_axi_m2_i5; - output fabric_fpga_arid_axi_s1_o1; - output fabric_fpga_arid_axi_s1_o10; - output fabric_fpga_arid_axi_s1_o11; - output fabric_fpga_arid_axi_s1_o12; - output fabric_fpga_arid_axi_s1_o2; - output fabric_fpga_arid_axi_s1_o3; - output fabric_fpga_arid_axi_s1_o4; - output fabric_fpga_arid_axi_s1_o5; - output fabric_fpga_arid_axi_s1_o6; - output fabric_fpga_arid_axi_s1_o7; - output fabric_fpga_arid_axi_s1_o8; - output fabric_fpga_arid_axi_s1_o9; - output fabric_fpga_arid_axi_s2_o1; - output fabric_fpga_arid_axi_s2_o10; - output fabric_fpga_arid_axi_s2_o11; - output fabric_fpga_arid_axi_s2_o12; - output fabric_fpga_arid_axi_s2_o2; - output fabric_fpga_arid_axi_s2_o3; - output fabric_fpga_arid_axi_s2_o4; - output fabric_fpga_arid_axi_s2_o5; - output fabric_fpga_arid_axi_s2_o6; - output fabric_fpga_arid_axi_s2_o7; - output fabric_fpga_arid_axi_s2_o8; - output fabric_fpga_arid_axi_s2_o9; - input fabric_fpga_arlen_axi_m1_i1; - input fabric_fpga_arlen_axi_m1_i2; - input fabric_fpga_arlen_axi_m1_i3; - input fabric_fpga_arlen_axi_m1_i4; - input fabric_fpga_arlen_axi_m1_i5; - input fabric_fpga_arlen_axi_m1_i6; - input fabric_fpga_arlen_axi_m1_i7; - input fabric_fpga_arlen_axi_m1_i8; - input fabric_fpga_arlen_axi_m2_i1; - input fabric_fpga_arlen_axi_m2_i2; - input fabric_fpga_arlen_axi_m2_i3; - input fabric_fpga_arlen_axi_m2_i4; - input fabric_fpga_arlen_axi_m2_i5; - input fabric_fpga_arlen_axi_m2_i6; - input fabric_fpga_arlen_axi_m2_i7; - input fabric_fpga_arlen_axi_m2_i8; - output fabric_fpga_arlen_axi_s1_o1; - output fabric_fpga_arlen_axi_s1_o2; - output fabric_fpga_arlen_axi_s1_o3; - output fabric_fpga_arlen_axi_s1_o4; - output fabric_fpga_arlen_axi_s1_o5; - output fabric_fpga_arlen_axi_s1_o6; - output fabric_fpga_arlen_axi_s1_o7; - output fabric_fpga_arlen_axi_s1_o8; - output fabric_fpga_arlen_axi_s2_o1; - output fabric_fpga_arlen_axi_s2_o2; - output fabric_fpga_arlen_axi_s2_o3; - output fabric_fpga_arlen_axi_s2_o4; - output fabric_fpga_arlen_axi_s2_o5; - output fabric_fpga_arlen_axi_s2_o6; - output fabric_fpga_arlen_axi_s2_o7; - output fabric_fpga_arlen_axi_s2_o8; - input fabric_fpga_arlock_axi_m1_i; - input fabric_fpga_arlock_axi_m2_i; - output fabric_fpga_arlock_axi_s1_o; - output fabric_fpga_arlock_axi_s2_o; - input fabric_fpga_arprot_axi_m1_i1; - input fabric_fpga_arprot_axi_m1_i2; - input fabric_fpga_arprot_axi_m1_i3; - input fabric_fpga_arprot_axi_m2_i1; - input fabric_fpga_arprot_axi_m2_i2; - input fabric_fpga_arprot_axi_m2_i3; - output fabric_fpga_arprot_axi_s1_o1; - output fabric_fpga_arprot_axi_s1_o2; - output fabric_fpga_arprot_axi_s1_o3; - output fabric_fpga_arprot_axi_s2_o1; - output fabric_fpga_arprot_axi_s2_o2; - output fabric_fpga_arprot_axi_s2_o3; - input fabric_fpga_arqos_axi_m1_i1; - input fabric_fpga_arqos_axi_m1_i2; - input fabric_fpga_arqos_axi_m1_i3; - input fabric_fpga_arqos_axi_m1_i4; - input fabric_fpga_arqos_axi_m2_i1; - input fabric_fpga_arqos_axi_m2_i2; - input fabric_fpga_arqos_axi_m2_i3; - input fabric_fpga_arqos_axi_m2_i4; - output fabric_fpga_arqos_axi_s1_o1; - output fabric_fpga_arqos_axi_s1_o2; - output fabric_fpga_arqos_axi_s1_o3; - output fabric_fpga_arqos_axi_s1_o4; - output fabric_fpga_arqos_axi_s2_o1; - output fabric_fpga_arqos_axi_s2_o2; - output fabric_fpga_arqos_axi_s2_o3; - output fabric_fpga_arqos_axi_s2_o4; - output fabric_fpga_arready_axi_m1_o; - output fabric_fpga_arready_axi_m2_o; - input fabric_fpga_arready_axi_s1_i; - input fabric_fpga_arready_axi_s2_i; - output fabric_fpga_arregion_axi_s1_o1; - output fabric_fpga_arregion_axi_s1_o2; - output fabric_fpga_arregion_axi_s1_o3; - output fabric_fpga_arregion_axi_s1_o4; - output fabric_fpga_arregion_axi_s2_o1; - output fabric_fpga_arregion_axi_s2_o2; - output fabric_fpga_arregion_axi_s2_o3; - output fabric_fpga_arregion_axi_s2_o4; - input fabric_fpga_arsize_axi_m1_i1; - input fabric_fpga_arsize_axi_m1_i2; - input fabric_fpga_arsize_axi_m1_i3; - input fabric_fpga_arsize_axi_m2_i1; - input fabric_fpga_arsize_axi_m2_i2; - input fabric_fpga_arsize_axi_m2_i3; - output fabric_fpga_arsize_axi_s1_o1; - output fabric_fpga_arsize_axi_s1_o2; - output fabric_fpga_arsize_axi_s1_o3; - output fabric_fpga_arsize_axi_s2_o1; - output fabric_fpga_arsize_axi_s2_o2; - output fabric_fpga_arsize_axi_s2_o3; - input fabric_fpga_arvalid_axi_m1_i; - input fabric_fpga_arvalid_axi_m2_i; - output fabric_fpga_arvalid_axi_s1_o; - output fabric_fpga_arvalid_axi_s2_o; - input fabric_fpga_awaddr_axi_m1_i1; - input fabric_fpga_awaddr_axi_m1_i10; - input fabric_fpga_awaddr_axi_m1_i11; - input fabric_fpga_awaddr_axi_m1_i12; - input fabric_fpga_awaddr_axi_m1_i13; - input fabric_fpga_awaddr_axi_m1_i14; - input fabric_fpga_awaddr_axi_m1_i15; - input fabric_fpga_awaddr_axi_m1_i16; - input fabric_fpga_awaddr_axi_m1_i17; - input fabric_fpga_awaddr_axi_m1_i18; - input fabric_fpga_awaddr_axi_m1_i19; - input fabric_fpga_awaddr_axi_m1_i2; - input fabric_fpga_awaddr_axi_m1_i20; - input fabric_fpga_awaddr_axi_m1_i21; - input fabric_fpga_awaddr_axi_m1_i22; - input fabric_fpga_awaddr_axi_m1_i23; - input fabric_fpga_awaddr_axi_m1_i24; - input fabric_fpga_awaddr_axi_m1_i25; - input fabric_fpga_awaddr_axi_m1_i26; - input fabric_fpga_awaddr_axi_m1_i27; - input fabric_fpga_awaddr_axi_m1_i28; - input fabric_fpga_awaddr_axi_m1_i29; - input fabric_fpga_awaddr_axi_m1_i3; - input fabric_fpga_awaddr_axi_m1_i30; - input fabric_fpga_awaddr_axi_m1_i31; - input fabric_fpga_awaddr_axi_m1_i32; - input fabric_fpga_awaddr_axi_m1_i33; - input fabric_fpga_awaddr_axi_m1_i34; - input fabric_fpga_awaddr_axi_m1_i35; - input fabric_fpga_awaddr_axi_m1_i36; - input fabric_fpga_awaddr_axi_m1_i37; - input fabric_fpga_awaddr_axi_m1_i38; - input fabric_fpga_awaddr_axi_m1_i39; - input fabric_fpga_awaddr_axi_m1_i4; - input fabric_fpga_awaddr_axi_m1_i40; - input fabric_fpga_awaddr_axi_m1_i5; - input fabric_fpga_awaddr_axi_m1_i6; - input fabric_fpga_awaddr_axi_m1_i7; - input fabric_fpga_awaddr_axi_m1_i8; - input fabric_fpga_awaddr_axi_m1_i9; - input fabric_fpga_awaddr_axi_m2_i1; - input fabric_fpga_awaddr_axi_m2_i10; - input fabric_fpga_awaddr_axi_m2_i11; - input fabric_fpga_awaddr_axi_m2_i12; - input fabric_fpga_awaddr_axi_m2_i13; - input fabric_fpga_awaddr_axi_m2_i14; - input fabric_fpga_awaddr_axi_m2_i15; - input fabric_fpga_awaddr_axi_m2_i16; - input fabric_fpga_awaddr_axi_m2_i17; - input fabric_fpga_awaddr_axi_m2_i18; - input fabric_fpga_awaddr_axi_m2_i19; - input fabric_fpga_awaddr_axi_m2_i2; - input fabric_fpga_awaddr_axi_m2_i20; - input fabric_fpga_awaddr_axi_m2_i21; - input fabric_fpga_awaddr_axi_m2_i22; - input fabric_fpga_awaddr_axi_m2_i23; - input fabric_fpga_awaddr_axi_m2_i24; - input fabric_fpga_awaddr_axi_m2_i25; - input fabric_fpga_awaddr_axi_m2_i26; - input fabric_fpga_awaddr_axi_m2_i27; - input fabric_fpga_awaddr_axi_m2_i28; - input fabric_fpga_awaddr_axi_m2_i29; - input fabric_fpga_awaddr_axi_m2_i3; - input fabric_fpga_awaddr_axi_m2_i30; - input fabric_fpga_awaddr_axi_m2_i31; - input fabric_fpga_awaddr_axi_m2_i32; - input fabric_fpga_awaddr_axi_m2_i33; - input fabric_fpga_awaddr_axi_m2_i34; - input fabric_fpga_awaddr_axi_m2_i35; - input fabric_fpga_awaddr_axi_m2_i36; - input fabric_fpga_awaddr_axi_m2_i37; - input fabric_fpga_awaddr_axi_m2_i38; - input fabric_fpga_awaddr_axi_m2_i39; - input fabric_fpga_awaddr_axi_m2_i4; - input fabric_fpga_awaddr_axi_m2_i40; - input fabric_fpga_awaddr_axi_m2_i5; - input fabric_fpga_awaddr_axi_m2_i6; - input fabric_fpga_awaddr_axi_m2_i7; - input fabric_fpga_awaddr_axi_m2_i8; - input fabric_fpga_awaddr_axi_m2_i9; - output fabric_fpga_awaddr_axi_s1_o1; - output fabric_fpga_awaddr_axi_s1_o10; - output fabric_fpga_awaddr_axi_s1_o11; - output fabric_fpga_awaddr_axi_s1_o12; - output fabric_fpga_awaddr_axi_s1_o13; - output fabric_fpga_awaddr_axi_s1_o14; - output fabric_fpga_awaddr_axi_s1_o15; - output fabric_fpga_awaddr_axi_s1_o16; - output fabric_fpga_awaddr_axi_s1_o17; - output fabric_fpga_awaddr_axi_s1_o18; - output fabric_fpga_awaddr_axi_s1_o19; - output fabric_fpga_awaddr_axi_s1_o2; - output fabric_fpga_awaddr_axi_s1_o20; - output fabric_fpga_awaddr_axi_s1_o21; - output fabric_fpga_awaddr_axi_s1_o22; - output fabric_fpga_awaddr_axi_s1_o23; - output fabric_fpga_awaddr_axi_s1_o24; - output fabric_fpga_awaddr_axi_s1_o25; - output fabric_fpga_awaddr_axi_s1_o26; - output fabric_fpga_awaddr_axi_s1_o27; - output fabric_fpga_awaddr_axi_s1_o28; - output fabric_fpga_awaddr_axi_s1_o29; - output fabric_fpga_awaddr_axi_s1_o3; - output fabric_fpga_awaddr_axi_s1_o30; - output fabric_fpga_awaddr_axi_s1_o31; - output fabric_fpga_awaddr_axi_s1_o32; - output fabric_fpga_awaddr_axi_s1_o33; - output fabric_fpga_awaddr_axi_s1_o34; - output fabric_fpga_awaddr_axi_s1_o35; - output fabric_fpga_awaddr_axi_s1_o36; - output fabric_fpga_awaddr_axi_s1_o37; - output fabric_fpga_awaddr_axi_s1_o38; - output fabric_fpga_awaddr_axi_s1_o39; - output fabric_fpga_awaddr_axi_s1_o4; - output fabric_fpga_awaddr_axi_s1_o40; - output fabric_fpga_awaddr_axi_s1_o5; - output fabric_fpga_awaddr_axi_s1_o6; - output fabric_fpga_awaddr_axi_s1_o7; - output fabric_fpga_awaddr_axi_s1_o8; - output fabric_fpga_awaddr_axi_s1_o9; - output fabric_fpga_awaddr_axi_s2_o1; - output fabric_fpga_awaddr_axi_s2_o10; - output fabric_fpga_awaddr_axi_s2_o11; - output fabric_fpga_awaddr_axi_s2_o12; - output fabric_fpga_awaddr_axi_s2_o13; - output fabric_fpga_awaddr_axi_s2_o14; - output fabric_fpga_awaddr_axi_s2_o15; - output fabric_fpga_awaddr_axi_s2_o16; - output fabric_fpga_awaddr_axi_s2_o17; - output fabric_fpga_awaddr_axi_s2_o18; - output fabric_fpga_awaddr_axi_s2_o19; - output fabric_fpga_awaddr_axi_s2_o2; - output fabric_fpga_awaddr_axi_s2_o20; - output fabric_fpga_awaddr_axi_s2_o21; - output fabric_fpga_awaddr_axi_s2_o22; - output fabric_fpga_awaddr_axi_s2_o23; - output fabric_fpga_awaddr_axi_s2_o24; - output fabric_fpga_awaddr_axi_s2_o25; - output fabric_fpga_awaddr_axi_s2_o26; - output fabric_fpga_awaddr_axi_s2_o27; - output fabric_fpga_awaddr_axi_s2_o28; - output fabric_fpga_awaddr_axi_s2_o29; - output fabric_fpga_awaddr_axi_s2_o3; - output fabric_fpga_awaddr_axi_s2_o30; - output fabric_fpga_awaddr_axi_s2_o31; - output fabric_fpga_awaddr_axi_s2_o32; - output fabric_fpga_awaddr_axi_s2_o33; - output fabric_fpga_awaddr_axi_s2_o34; - output fabric_fpga_awaddr_axi_s2_o35; - output fabric_fpga_awaddr_axi_s2_o36; - output fabric_fpga_awaddr_axi_s2_o37; - output fabric_fpga_awaddr_axi_s2_o38; - output fabric_fpga_awaddr_axi_s2_o39; - output fabric_fpga_awaddr_axi_s2_o4; - output fabric_fpga_awaddr_axi_s2_o40; - output fabric_fpga_awaddr_axi_s2_o5; - output fabric_fpga_awaddr_axi_s2_o6; - output fabric_fpga_awaddr_axi_s2_o7; - output fabric_fpga_awaddr_axi_s2_o8; - output fabric_fpga_awaddr_axi_s2_o9; - input fabric_fpga_awburst_axi_m1_i1; - input fabric_fpga_awburst_axi_m1_i2; - input fabric_fpga_awburst_axi_m2_i1; - input fabric_fpga_awburst_axi_m2_i2; - output fabric_fpga_awburst_axi_s1_o1; - output fabric_fpga_awburst_axi_s1_o2; - output fabric_fpga_awburst_axi_s2_o1; - output fabric_fpga_awburst_axi_s2_o2; - input fabric_fpga_awcache_axi_m1_i1; - input fabric_fpga_awcache_axi_m1_i2; - input fabric_fpga_awcache_axi_m1_i3; - input fabric_fpga_awcache_axi_m1_i4; - input fabric_fpga_awcache_axi_m2_i1; - input fabric_fpga_awcache_axi_m2_i2; - input fabric_fpga_awcache_axi_m2_i3; - input fabric_fpga_awcache_axi_m2_i4; - output fabric_fpga_awcache_axi_s1_o1; - output fabric_fpga_awcache_axi_s1_o2; - output fabric_fpga_awcache_axi_s1_o3; - output fabric_fpga_awcache_axi_s1_o4; - output fabric_fpga_awcache_axi_s2_o1; - output fabric_fpga_awcache_axi_s2_o2; - output fabric_fpga_awcache_axi_s2_o3; - output fabric_fpga_awcache_axi_s2_o4; - input fabric_fpga_awid_axi_m1_i1; - input fabric_fpga_awid_axi_m1_i2; - input fabric_fpga_awid_axi_m1_i3; - input fabric_fpga_awid_axi_m1_i4; - input fabric_fpga_awid_axi_m1_i5; - input fabric_fpga_awid_axi_m2_i1; - input fabric_fpga_awid_axi_m2_i2; - input fabric_fpga_awid_axi_m2_i3; - input fabric_fpga_awid_axi_m2_i4; - input fabric_fpga_awid_axi_m2_i5; - output fabric_fpga_awid_axi_s1_o1; - output fabric_fpga_awid_axi_s1_o10; - output fabric_fpga_awid_axi_s1_o11; - output fabric_fpga_awid_axi_s1_o12; - output fabric_fpga_awid_axi_s1_o2; - output fabric_fpga_awid_axi_s1_o3; - output fabric_fpga_awid_axi_s1_o4; - output fabric_fpga_awid_axi_s1_o5; - output fabric_fpga_awid_axi_s1_o6; - output fabric_fpga_awid_axi_s1_o7; - output fabric_fpga_awid_axi_s1_o8; - output fabric_fpga_awid_axi_s1_o9; - output fabric_fpga_awid_axi_s2_o1; - output fabric_fpga_awid_axi_s2_o10; - output fabric_fpga_awid_axi_s2_o11; - output fabric_fpga_awid_axi_s2_o12; - output fabric_fpga_awid_axi_s2_o2; - output fabric_fpga_awid_axi_s2_o3; - output fabric_fpga_awid_axi_s2_o4; - output fabric_fpga_awid_axi_s2_o5; - output fabric_fpga_awid_axi_s2_o6; - output fabric_fpga_awid_axi_s2_o7; - output fabric_fpga_awid_axi_s2_o8; - output fabric_fpga_awid_axi_s2_o9; - input fabric_fpga_awlen_axi_m1_i1; - input fabric_fpga_awlen_axi_m1_i2; - input fabric_fpga_awlen_axi_m1_i3; - input fabric_fpga_awlen_axi_m1_i4; - input fabric_fpga_awlen_axi_m1_i5; - input fabric_fpga_awlen_axi_m1_i6; - input fabric_fpga_awlen_axi_m1_i7; - input fabric_fpga_awlen_axi_m1_i8; - input fabric_fpga_awlen_axi_m2_i1; - input fabric_fpga_awlen_axi_m2_i2; - input fabric_fpga_awlen_axi_m2_i3; - input fabric_fpga_awlen_axi_m2_i4; - input fabric_fpga_awlen_axi_m2_i5; - input fabric_fpga_awlen_axi_m2_i6; - input fabric_fpga_awlen_axi_m2_i7; - input fabric_fpga_awlen_axi_m2_i8; - output fabric_fpga_awlen_axi_s1_o1; - output fabric_fpga_awlen_axi_s1_o2; - output fabric_fpga_awlen_axi_s1_o3; - output fabric_fpga_awlen_axi_s1_o4; - output fabric_fpga_awlen_axi_s1_o5; - output fabric_fpga_awlen_axi_s1_o6; - output fabric_fpga_awlen_axi_s1_o7; - output fabric_fpga_awlen_axi_s1_o8; - output fabric_fpga_awlen_axi_s2_o1; - output fabric_fpga_awlen_axi_s2_o2; - output fabric_fpga_awlen_axi_s2_o3; - output fabric_fpga_awlen_axi_s2_o4; - output fabric_fpga_awlen_axi_s2_o5; - output fabric_fpga_awlen_axi_s2_o6; - output fabric_fpga_awlen_axi_s2_o7; - output fabric_fpga_awlen_axi_s2_o8; - input fabric_fpga_awlock_axi_m1_i; - input fabric_fpga_awlock_axi_m2_i; - output fabric_fpga_awlock_axi_s1_o; - output fabric_fpga_awlock_axi_s2_o; - input fabric_fpga_awprot_axi_m1_i1; - input fabric_fpga_awprot_axi_m1_i2; - input fabric_fpga_awprot_axi_m1_i3; - input fabric_fpga_awprot_axi_m2_i1; - input fabric_fpga_awprot_axi_m2_i2; - input fabric_fpga_awprot_axi_m2_i3; - output fabric_fpga_awprot_axi_s1_o1; - output fabric_fpga_awprot_axi_s1_o2; - output fabric_fpga_awprot_axi_s1_o3; - output fabric_fpga_awprot_axi_s2_o1; - output fabric_fpga_awprot_axi_s2_o2; - output fabric_fpga_awprot_axi_s2_o3; - input fabric_fpga_awqos_axi_m1_i1; - input fabric_fpga_awqos_axi_m1_i2; - input fabric_fpga_awqos_axi_m1_i3; - input fabric_fpga_awqos_axi_m1_i4; - input fabric_fpga_awqos_axi_m2_i1; - input fabric_fpga_awqos_axi_m2_i2; - input fabric_fpga_awqos_axi_m2_i3; - input fabric_fpga_awqos_axi_m2_i4; - output fabric_fpga_awqos_axi_s1_o1; - output fabric_fpga_awqos_axi_s1_o2; - output fabric_fpga_awqos_axi_s1_o3; - output fabric_fpga_awqos_axi_s1_o4; - output fabric_fpga_awqos_axi_s2_o1; - output fabric_fpga_awqos_axi_s2_o2; - output fabric_fpga_awqos_axi_s2_o3; - output fabric_fpga_awqos_axi_s2_o4; - output fabric_fpga_awready_axi_m1_o; - output fabric_fpga_awready_axi_m2_o; - input fabric_fpga_awready_axi_s1_i; - input fabric_fpga_awready_axi_s2_i; - output fabric_fpga_awregion_axi_s1_o1; - output fabric_fpga_awregion_axi_s1_o2; - output fabric_fpga_awregion_axi_s1_o3; - output fabric_fpga_awregion_axi_s1_o4; - output fabric_fpga_awregion_axi_s2_o1; - output fabric_fpga_awregion_axi_s2_o2; - output fabric_fpga_awregion_axi_s2_o3; - output fabric_fpga_awregion_axi_s2_o4; - input fabric_fpga_awsize_axi_m1_i1; - input fabric_fpga_awsize_axi_m1_i2; - input fabric_fpga_awsize_axi_m1_i3; - input fabric_fpga_awsize_axi_m2_i1; - input fabric_fpga_awsize_axi_m2_i2; - input fabric_fpga_awsize_axi_m2_i3; - output fabric_fpga_awsize_axi_s1_o1; - output fabric_fpga_awsize_axi_s1_o2; - output fabric_fpga_awsize_axi_s1_o3; - output fabric_fpga_awsize_axi_s2_o1; - output fabric_fpga_awsize_axi_s2_o2; - output fabric_fpga_awsize_axi_s2_o3; - input fabric_fpga_awvalid_axi_m1_i; - input fabric_fpga_awvalid_axi_m2_i; - output fabric_fpga_awvalid_axi_s1_o; - output fabric_fpga_awvalid_axi_s2_o; - output fabric_fpga_bid_axi_m1_o1; - output fabric_fpga_bid_axi_m1_o2; - output fabric_fpga_bid_axi_m1_o3; - output fabric_fpga_bid_axi_m1_o4; - output fabric_fpga_bid_axi_m1_o5; - output fabric_fpga_bid_axi_m2_o1; - output fabric_fpga_bid_axi_m2_o2; - output fabric_fpga_bid_axi_m2_o3; - output fabric_fpga_bid_axi_m2_o4; - output fabric_fpga_bid_axi_m2_o5; - input fabric_fpga_bid_axi_s1_i1; - input fabric_fpga_bid_axi_s1_i10; - input fabric_fpga_bid_axi_s1_i11; - input fabric_fpga_bid_axi_s1_i12; - input fabric_fpga_bid_axi_s1_i2; - input fabric_fpga_bid_axi_s1_i3; - input fabric_fpga_bid_axi_s1_i4; - input fabric_fpga_bid_axi_s1_i5; - input fabric_fpga_bid_axi_s1_i6; - input fabric_fpga_bid_axi_s1_i7; - input fabric_fpga_bid_axi_s1_i8; - input fabric_fpga_bid_axi_s1_i9; - input fabric_fpga_bid_axi_s2_i1; - input fabric_fpga_bid_axi_s2_i10; - input fabric_fpga_bid_axi_s2_i11; - input fabric_fpga_bid_axi_s2_i12; - input fabric_fpga_bid_axi_s2_i2; - input fabric_fpga_bid_axi_s2_i3; - input fabric_fpga_bid_axi_s2_i4; - input fabric_fpga_bid_axi_s2_i5; - input fabric_fpga_bid_axi_s2_i6; - input fabric_fpga_bid_axi_s2_i7; - input fabric_fpga_bid_axi_s2_i8; - input fabric_fpga_bid_axi_s2_i9; - input fabric_fpga_bready_axi_m1_i; - input fabric_fpga_bready_axi_m2_i; - output fabric_fpga_bready_axi_s1_o; - output fabric_fpga_bready_axi_s2_o; - output fabric_fpga_bresp_axi_m1_o1; - output fabric_fpga_bresp_axi_m1_o2; - output fabric_fpga_bresp_axi_m2_o1; - output fabric_fpga_bresp_axi_m2_o2; - input fabric_fpga_bresp_axi_s1_i1; - input fabric_fpga_bresp_axi_s1_i2; - input fabric_fpga_bresp_axi_s2_i1; - input fabric_fpga_bresp_axi_s2_i2; - output fabric_fpga_bvalid_axi_m1_o; - output fabric_fpga_bvalid_axi_m2_o; - input fabric_fpga_bvalid_axi_s1_i; - input fabric_fpga_bvalid_axi_s2_i; - input fabric_fpga_ddr0_araddr_i1; - input fabric_fpga_ddr0_araddr_i10; - input fabric_fpga_ddr0_araddr_i11; - input fabric_fpga_ddr0_araddr_i12; - input fabric_fpga_ddr0_araddr_i13; - input fabric_fpga_ddr0_araddr_i14; - input fabric_fpga_ddr0_araddr_i15; - input fabric_fpga_ddr0_araddr_i16; - input fabric_fpga_ddr0_araddr_i17; - input fabric_fpga_ddr0_araddr_i18; - input fabric_fpga_ddr0_araddr_i19; - input fabric_fpga_ddr0_araddr_i2; - input fabric_fpga_ddr0_araddr_i20; - input fabric_fpga_ddr0_araddr_i21; - input fabric_fpga_ddr0_araddr_i22; - input fabric_fpga_ddr0_araddr_i23; - input fabric_fpga_ddr0_araddr_i24; - input fabric_fpga_ddr0_araddr_i25; - input fabric_fpga_ddr0_araddr_i26; - input fabric_fpga_ddr0_araddr_i27; - input fabric_fpga_ddr0_araddr_i28; - input fabric_fpga_ddr0_araddr_i29; - input fabric_fpga_ddr0_araddr_i3; - input fabric_fpga_ddr0_araddr_i30; - input fabric_fpga_ddr0_araddr_i31; - input fabric_fpga_ddr0_araddr_i32; - input fabric_fpga_ddr0_araddr_i33; - input fabric_fpga_ddr0_araddr_i34; - input fabric_fpga_ddr0_araddr_i35; - input fabric_fpga_ddr0_araddr_i36; - input fabric_fpga_ddr0_araddr_i37; - input fabric_fpga_ddr0_araddr_i38; - input fabric_fpga_ddr0_araddr_i39; - input fabric_fpga_ddr0_araddr_i4; - input fabric_fpga_ddr0_araddr_i40; - input fabric_fpga_ddr0_araddr_i5; - input fabric_fpga_ddr0_araddr_i6; - input fabric_fpga_ddr0_araddr_i7; - input fabric_fpga_ddr0_araddr_i8; - input fabric_fpga_ddr0_araddr_i9; - input fabric_fpga_ddr0_arburst_i1; - input fabric_fpga_ddr0_arburst_i2; - input fabric_fpga_ddr0_arcache_i1; - input fabric_fpga_ddr0_arcache_i2; - input fabric_fpga_ddr0_arcache_i3; - input fabric_fpga_ddr0_arcache_i4; - input fabric_fpga_ddr0_arid_i1; - input fabric_fpga_ddr0_arid_i2; - input fabric_fpga_ddr0_arid_i3; - input fabric_fpga_ddr0_arid_i4; - input fabric_fpga_ddr0_arid_i5; - input fabric_fpga_ddr0_arlen_i1; - input fabric_fpga_ddr0_arlen_i2; - input fabric_fpga_ddr0_arlen_i3; - input fabric_fpga_ddr0_arlen_i4; - input fabric_fpga_ddr0_arlen_i5; - input fabric_fpga_ddr0_arlen_i6; - input fabric_fpga_ddr0_arlen_i7; - input fabric_fpga_ddr0_arlen_i8; - input fabric_fpga_ddr0_arlock_i; - input fabric_fpga_ddr0_arprot_i1; - input fabric_fpga_ddr0_arprot_i2; - input fabric_fpga_ddr0_arprot_i3; - input fabric_fpga_ddr0_arqos_i1; - input fabric_fpga_ddr0_arqos_i2; - input fabric_fpga_ddr0_arqos_i3; - input fabric_fpga_ddr0_arqos_i4; - output fabric_fpga_ddr0_arready_o; - input fabric_fpga_ddr0_arsize_i1; - input fabric_fpga_ddr0_arsize_i2; - input fabric_fpga_ddr0_arsize_i3; - input fabric_fpga_ddr0_arvalid_i; - input fabric_fpga_ddr0_awaddr_i1; - input fabric_fpga_ddr0_awaddr_i10; - input fabric_fpga_ddr0_awaddr_i11; - input fabric_fpga_ddr0_awaddr_i12; - input fabric_fpga_ddr0_awaddr_i13; - input fabric_fpga_ddr0_awaddr_i14; - input fabric_fpga_ddr0_awaddr_i15; - input fabric_fpga_ddr0_awaddr_i16; - input fabric_fpga_ddr0_awaddr_i17; - input fabric_fpga_ddr0_awaddr_i18; - input fabric_fpga_ddr0_awaddr_i19; - input fabric_fpga_ddr0_awaddr_i2; - input fabric_fpga_ddr0_awaddr_i20; - input fabric_fpga_ddr0_awaddr_i21; - input fabric_fpga_ddr0_awaddr_i22; - input fabric_fpga_ddr0_awaddr_i23; - input fabric_fpga_ddr0_awaddr_i24; - input fabric_fpga_ddr0_awaddr_i25; - input fabric_fpga_ddr0_awaddr_i26; - input fabric_fpga_ddr0_awaddr_i27; - input fabric_fpga_ddr0_awaddr_i28; - input fabric_fpga_ddr0_awaddr_i29; - input fabric_fpga_ddr0_awaddr_i3; - input fabric_fpga_ddr0_awaddr_i30; - input fabric_fpga_ddr0_awaddr_i31; - input fabric_fpga_ddr0_awaddr_i32; - input fabric_fpga_ddr0_awaddr_i33; - input fabric_fpga_ddr0_awaddr_i34; - input fabric_fpga_ddr0_awaddr_i35; - input fabric_fpga_ddr0_awaddr_i36; - input fabric_fpga_ddr0_awaddr_i37; - input fabric_fpga_ddr0_awaddr_i38; - input fabric_fpga_ddr0_awaddr_i39; - input fabric_fpga_ddr0_awaddr_i4; - input fabric_fpga_ddr0_awaddr_i40; - input fabric_fpga_ddr0_awaddr_i5; - input fabric_fpga_ddr0_awaddr_i6; - input fabric_fpga_ddr0_awaddr_i7; - input fabric_fpga_ddr0_awaddr_i8; - input fabric_fpga_ddr0_awaddr_i9; - input fabric_fpga_ddr0_awburst_i1; - input fabric_fpga_ddr0_awburst_i2; - input fabric_fpga_ddr0_awcache_i1; - input fabric_fpga_ddr0_awcache_i2; - input fabric_fpga_ddr0_awcache_i3; - input fabric_fpga_ddr0_awcache_i4; - input fabric_fpga_ddr0_awid_i1; - input fabric_fpga_ddr0_awid_i2; - input fabric_fpga_ddr0_awid_i3; - input fabric_fpga_ddr0_awid_i4; - input fabric_fpga_ddr0_awid_i5; - input fabric_fpga_ddr0_awlen_i1; - input fabric_fpga_ddr0_awlen_i2; - input fabric_fpga_ddr0_awlen_i3; - input fabric_fpga_ddr0_awlen_i4; - input fabric_fpga_ddr0_awlen_i5; - input fabric_fpga_ddr0_awlen_i6; - input fabric_fpga_ddr0_awlen_i7; - input fabric_fpga_ddr0_awlen_i8; - input fabric_fpga_ddr0_awlock_i; - input fabric_fpga_ddr0_awprot_i1; - input fabric_fpga_ddr0_awprot_i2; - input fabric_fpga_ddr0_awprot_i3; - input fabric_fpga_ddr0_awqos_i1; - input fabric_fpga_ddr0_awqos_i2; - input fabric_fpga_ddr0_awqos_i3; - input fabric_fpga_ddr0_awqos_i4; - output fabric_fpga_ddr0_awready_o; - input fabric_fpga_ddr0_awsize_i1; - input fabric_fpga_ddr0_awsize_i2; - input fabric_fpga_ddr0_awsize_i3; - input fabric_fpga_ddr0_awvalid_i; - output fabric_fpga_ddr0_bid_o1; - output fabric_fpga_ddr0_bid_o2; - output fabric_fpga_ddr0_bid_o3; - output fabric_fpga_ddr0_bid_o4; - output fabric_fpga_ddr0_bid_o5; - input fabric_fpga_ddr0_bready_i; - output fabric_fpga_ddr0_bresp_o1; - output fabric_fpga_ddr0_bresp_o2; - output fabric_fpga_ddr0_bvalid_o; - output fabric_fpga_ddr0_rdata_o1; - output fabric_fpga_ddr0_rdata_o10; - output fabric_fpga_ddr0_rdata_o100; - output fabric_fpga_ddr0_rdata_o101; - output fabric_fpga_ddr0_rdata_o102; - output fabric_fpga_ddr0_rdata_o103; - output fabric_fpga_ddr0_rdata_o104; - output fabric_fpga_ddr0_rdata_o105; - output fabric_fpga_ddr0_rdata_o106; - output fabric_fpga_ddr0_rdata_o107; - output fabric_fpga_ddr0_rdata_o108; - output fabric_fpga_ddr0_rdata_o109; - output fabric_fpga_ddr0_rdata_o11; - output fabric_fpga_ddr0_rdata_o110; - output fabric_fpga_ddr0_rdata_o111; - output fabric_fpga_ddr0_rdata_o112; - output fabric_fpga_ddr0_rdata_o113; - output fabric_fpga_ddr0_rdata_o114; - output fabric_fpga_ddr0_rdata_o115; - output fabric_fpga_ddr0_rdata_o116; - output fabric_fpga_ddr0_rdata_o117; - output fabric_fpga_ddr0_rdata_o118; - output fabric_fpga_ddr0_rdata_o119; - output fabric_fpga_ddr0_rdata_o12; - output fabric_fpga_ddr0_rdata_o120; - output fabric_fpga_ddr0_rdata_o121; - output fabric_fpga_ddr0_rdata_o122; - output fabric_fpga_ddr0_rdata_o123; - output fabric_fpga_ddr0_rdata_o124; - output fabric_fpga_ddr0_rdata_o125; - output fabric_fpga_ddr0_rdata_o126; - output fabric_fpga_ddr0_rdata_o127; - output fabric_fpga_ddr0_rdata_o128; - output fabric_fpga_ddr0_rdata_o13; - output fabric_fpga_ddr0_rdata_o14; - output fabric_fpga_ddr0_rdata_o15; - output fabric_fpga_ddr0_rdata_o16; - output fabric_fpga_ddr0_rdata_o17; - output fabric_fpga_ddr0_rdata_o18; - output fabric_fpga_ddr0_rdata_o19; - output fabric_fpga_ddr0_rdata_o2; - output fabric_fpga_ddr0_rdata_o20; - output fabric_fpga_ddr0_rdata_o21; - output fabric_fpga_ddr0_rdata_o22; - output fabric_fpga_ddr0_rdata_o23; - output fabric_fpga_ddr0_rdata_o24; - output fabric_fpga_ddr0_rdata_o25; - output fabric_fpga_ddr0_rdata_o26; - output fabric_fpga_ddr0_rdata_o27; - output fabric_fpga_ddr0_rdata_o28; - output fabric_fpga_ddr0_rdata_o29; - output fabric_fpga_ddr0_rdata_o3; - output fabric_fpga_ddr0_rdata_o30; - output fabric_fpga_ddr0_rdata_o31; - output fabric_fpga_ddr0_rdata_o32; - output fabric_fpga_ddr0_rdata_o33; - output fabric_fpga_ddr0_rdata_o34; - output fabric_fpga_ddr0_rdata_o35; - output fabric_fpga_ddr0_rdata_o36; - output fabric_fpga_ddr0_rdata_o37; - output fabric_fpga_ddr0_rdata_o38; - output fabric_fpga_ddr0_rdata_o39; - output fabric_fpga_ddr0_rdata_o4; - output fabric_fpga_ddr0_rdata_o40; - output fabric_fpga_ddr0_rdata_o41; - output fabric_fpga_ddr0_rdata_o42; - output fabric_fpga_ddr0_rdata_o43; - output fabric_fpga_ddr0_rdata_o44; - output fabric_fpga_ddr0_rdata_o45; - output fabric_fpga_ddr0_rdata_o46; - output fabric_fpga_ddr0_rdata_o47; - output fabric_fpga_ddr0_rdata_o48; - output fabric_fpga_ddr0_rdata_o49; - output fabric_fpga_ddr0_rdata_o5; - output fabric_fpga_ddr0_rdata_o50; - output fabric_fpga_ddr0_rdata_o51; - output fabric_fpga_ddr0_rdata_o52; - output fabric_fpga_ddr0_rdata_o53; - output fabric_fpga_ddr0_rdata_o54; - output fabric_fpga_ddr0_rdata_o55; - output fabric_fpga_ddr0_rdata_o56; - output fabric_fpga_ddr0_rdata_o57; - output fabric_fpga_ddr0_rdata_o58; - output fabric_fpga_ddr0_rdata_o59; - output fabric_fpga_ddr0_rdata_o6; - output fabric_fpga_ddr0_rdata_o60; - output fabric_fpga_ddr0_rdata_o61; - output fabric_fpga_ddr0_rdata_o62; - output fabric_fpga_ddr0_rdata_o63; - output fabric_fpga_ddr0_rdata_o64; - output fabric_fpga_ddr0_rdata_o65; - output fabric_fpga_ddr0_rdata_o66; - output fabric_fpga_ddr0_rdata_o67; - output fabric_fpga_ddr0_rdata_o68; - output fabric_fpga_ddr0_rdata_o69; - output fabric_fpga_ddr0_rdata_o7; - output fabric_fpga_ddr0_rdata_o70; - output fabric_fpga_ddr0_rdata_o71; - output fabric_fpga_ddr0_rdata_o72; - output fabric_fpga_ddr0_rdata_o73; - output fabric_fpga_ddr0_rdata_o74; - output fabric_fpga_ddr0_rdata_o75; - output fabric_fpga_ddr0_rdata_o76; - output fabric_fpga_ddr0_rdata_o77; - output fabric_fpga_ddr0_rdata_o78; - output fabric_fpga_ddr0_rdata_o79; - output fabric_fpga_ddr0_rdata_o8; - output fabric_fpga_ddr0_rdata_o80; - output fabric_fpga_ddr0_rdata_o81; - output fabric_fpga_ddr0_rdata_o82; - output fabric_fpga_ddr0_rdata_o83; - output fabric_fpga_ddr0_rdata_o84; - output fabric_fpga_ddr0_rdata_o85; - output fabric_fpga_ddr0_rdata_o86; - output fabric_fpga_ddr0_rdata_o87; - output fabric_fpga_ddr0_rdata_o88; - output fabric_fpga_ddr0_rdata_o89; - output fabric_fpga_ddr0_rdata_o9; - output fabric_fpga_ddr0_rdata_o90; - output fabric_fpga_ddr0_rdata_o91; - output fabric_fpga_ddr0_rdata_o92; - output fabric_fpga_ddr0_rdata_o93; - output fabric_fpga_ddr0_rdata_o94; - output fabric_fpga_ddr0_rdata_o95; - output fabric_fpga_ddr0_rdata_o96; - output fabric_fpga_ddr0_rdata_o97; - output fabric_fpga_ddr0_rdata_o98; - output fabric_fpga_ddr0_rdata_o99; - output fabric_fpga_ddr0_rid_o1; - output fabric_fpga_ddr0_rid_o2; - output fabric_fpga_ddr0_rid_o3; - output fabric_fpga_ddr0_rid_o4; - output fabric_fpga_ddr0_rid_o5; - output fabric_fpga_ddr0_rlast_o; - input fabric_fpga_ddr0_rready_i; - output fabric_fpga_ddr0_rresp_o1; - output fabric_fpga_ddr0_rresp_o2; - output fabric_fpga_ddr0_rvalid_o; - input fabric_fpga_ddr0_wdata_i1; - input fabric_fpga_ddr0_wdata_i10; - input fabric_fpga_ddr0_wdata_i100; - input fabric_fpga_ddr0_wdata_i101; - input fabric_fpga_ddr0_wdata_i102; - input fabric_fpga_ddr0_wdata_i103; - input fabric_fpga_ddr0_wdata_i104; - input fabric_fpga_ddr0_wdata_i105; - input fabric_fpga_ddr0_wdata_i106; - input fabric_fpga_ddr0_wdata_i107; - input fabric_fpga_ddr0_wdata_i108; - input fabric_fpga_ddr0_wdata_i109; - input fabric_fpga_ddr0_wdata_i11; - input fabric_fpga_ddr0_wdata_i110; - input fabric_fpga_ddr0_wdata_i111; - input fabric_fpga_ddr0_wdata_i112; - input fabric_fpga_ddr0_wdata_i113; - input fabric_fpga_ddr0_wdata_i114; - input fabric_fpga_ddr0_wdata_i115; - input fabric_fpga_ddr0_wdata_i116; - input fabric_fpga_ddr0_wdata_i117; - input fabric_fpga_ddr0_wdata_i118; - input fabric_fpga_ddr0_wdata_i119; - input fabric_fpga_ddr0_wdata_i12; - input fabric_fpga_ddr0_wdata_i120; - input fabric_fpga_ddr0_wdata_i121; - input fabric_fpga_ddr0_wdata_i122; - input fabric_fpga_ddr0_wdata_i123; - input fabric_fpga_ddr0_wdata_i124; - input fabric_fpga_ddr0_wdata_i125; - input fabric_fpga_ddr0_wdata_i126; - input fabric_fpga_ddr0_wdata_i127; - input fabric_fpga_ddr0_wdata_i128; - input fabric_fpga_ddr0_wdata_i13; - input fabric_fpga_ddr0_wdata_i14; - input fabric_fpga_ddr0_wdata_i15; - input fabric_fpga_ddr0_wdata_i16; - input fabric_fpga_ddr0_wdata_i17; - input fabric_fpga_ddr0_wdata_i18; - input fabric_fpga_ddr0_wdata_i19; - input fabric_fpga_ddr0_wdata_i2; - input fabric_fpga_ddr0_wdata_i20; - input fabric_fpga_ddr0_wdata_i21; - input fabric_fpga_ddr0_wdata_i22; - input fabric_fpga_ddr0_wdata_i23; - input fabric_fpga_ddr0_wdata_i24; - input fabric_fpga_ddr0_wdata_i25; - input fabric_fpga_ddr0_wdata_i26; - input fabric_fpga_ddr0_wdata_i27; - input fabric_fpga_ddr0_wdata_i28; - input fabric_fpga_ddr0_wdata_i29; - input fabric_fpga_ddr0_wdata_i3; - input fabric_fpga_ddr0_wdata_i30; - input fabric_fpga_ddr0_wdata_i31; - input fabric_fpga_ddr0_wdata_i32; - input fabric_fpga_ddr0_wdata_i33; - input fabric_fpga_ddr0_wdata_i34; - input fabric_fpga_ddr0_wdata_i35; - input fabric_fpga_ddr0_wdata_i36; - input fabric_fpga_ddr0_wdata_i37; - input fabric_fpga_ddr0_wdata_i38; - input fabric_fpga_ddr0_wdata_i39; - input fabric_fpga_ddr0_wdata_i4; - input fabric_fpga_ddr0_wdata_i40; - input fabric_fpga_ddr0_wdata_i41; - input fabric_fpga_ddr0_wdata_i42; - input fabric_fpga_ddr0_wdata_i43; - input fabric_fpga_ddr0_wdata_i44; - input fabric_fpga_ddr0_wdata_i45; - input fabric_fpga_ddr0_wdata_i46; - input fabric_fpga_ddr0_wdata_i47; - input fabric_fpga_ddr0_wdata_i48; - input fabric_fpga_ddr0_wdata_i49; - input fabric_fpga_ddr0_wdata_i5; - input fabric_fpga_ddr0_wdata_i50; - input fabric_fpga_ddr0_wdata_i51; - input fabric_fpga_ddr0_wdata_i52; - input fabric_fpga_ddr0_wdata_i53; - input fabric_fpga_ddr0_wdata_i54; - input fabric_fpga_ddr0_wdata_i55; - input fabric_fpga_ddr0_wdata_i56; - input fabric_fpga_ddr0_wdata_i57; - input fabric_fpga_ddr0_wdata_i58; - input fabric_fpga_ddr0_wdata_i59; - input fabric_fpga_ddr0_wdata_i6; - input fabric_fpga_ddr0_wdata_i60; - input fabric_fpga_ddr0_wdata_i61; - input fabric_fpga_ddr0_wdata_i62; - input fabric_fpga_ddr0_wdata_i63; - input fabric_fpga_ddr0_wdata_i64; - input fabric_fpga_ddr0_wdata_i65; - input fabric_fpga_ddr0_wdata_i66; - input fabric_fpga_ddr0_wdata_i67; - input fabric_fpga_ddr0_wdata_i68; - input fabric_fpga_ddr0_wdata_i69; - input fabric_fpga_ddr0_wdata_i7; - input fabric_fpga_ddr0_wdata_i70; - input fabric_fpga_ddr0_wdata_i71; - input fabric_fpga_ddr0_wdata_i72; - input fabric_fpga_ddr0_wdata_i73; - input fabric_fpga_ddr0_wdata_i74; - input fabric_fpga_ddr0_wdata_i75; - input fabric_fpga_ddr0_wdata_i76; - input fabric_fpga_ddr0_wdata_i77; - input fabric_fpga_ddr0_wdata_i78; - input fabric_fpga_ddr0_wdata_i79; - input fabric_fpga_ddr0_wdata_i8; - input fabric_fpga_ddr0_wdata_i80; - input fabric_fpga_ddr0_wdata_i81; - input fabric_fpga_ddr0_wdata_i82; - input fabric_fpga_ddr0_wdata_i83; - input fabric_fpga_ddr0_wdata_i84; - input fabric_fpga_ddr0_wdata_i85; - input fabric_fpga_ddr0_wdata_i86; - input fabric_fpga_ddr0_wdata_i87; - input fabric_fpga_ddr0_wdata_i88; - input fabric_fpga_ddr0_wdata_i89; - input fabric_fpga_ddr0_wdata_i9; - input fabric_fpga_ddr0_wdata_i90; - input fabric_fpga_ddr0_wdata_i91; - input fabric_fpga_ddr0_wdata_i92; - input fabric_fpga_ddr0_wdata_i93; - input fabric_fpga_ddr0_wdata_i94; - input fabric_fpga_ddr0_wdata_i95; - input fabric_fpga_ddr0_wdata_i96; - input fabric_fpga_ddr0_wdata_i97; - input fabric_fpga_ddr0_wdata_i98; - input fabric_fpga_ddr0_wdata_i99; - input fabric_fpga_ddr0_wlast_i; - output fabric_fpga_ddr0_wready_o; - input fabric_fpga_ddr0_wstrb_i1; - input fabric_fpga_ddr0_wstrb_i10; - input fabric_fpga_ddr0_wstrb_i11; - input fabric_fpga_ddr0_wstrb_i12; - input fabric_fpga_ddr0_wstrb_i13; - input fabric_fpga_ddr0_wstrb_i14; - input fabric_fpga_ddr0_wstrb_i15; - input fabric_fpga_ddr0_wstrb_i16; - input fabric_fpga_ddr0_wstrb_i2; - input fabric_fpga_ddr0_wstrb_i3; - input fabric_fpga_ddr0_wstrb_i4; - input fabric_fpga_ddr0_wstrb_i5; - input fabric_fpga_ddr0_wstrb_i6; - input fabric_fpga_ddr0_wstrb_i7; - input fabric_fpga_ddr0_wstrb_i8; - input fabric_fpga_ddr0_wstrb_i9; - input fabric_fpga_ddr0_wvalid_i; - output fabric_fpga_dma_ack_m1_o1; - output fabric_fpga_dma_ack_m1_o2; - output fabric_fpga_dma_ack_m1_o3; - output fabric_fpga_dma_ack_m1_o4; - output fabric_fpga_dma_ack_m1_o5; - output fabric_fpga_dma_ack_m1_o6; - output fabric_fpga_dma_ack_m2_o1; - output fabric_fpga_dma_ack_m2_o2; - output fabric_fpga_dma_ack_m2_o3; - output fabric_fpga_dma_ack_m2_o4; - output fabric_fpga_dma_ack_m2_o5; - output fabric_fpga_dma_ack_m2_o6; - output fabric_fpga_dma_finish_m1_o1; - output fabric_fpga_dma_finish_m1_o2; - output fabric_fpga_dma_finish_m1_o3; - output fabric_fpga_dma_finish_m1_o4; - output fabric_fpga_dma_finish_m1_o5; - output fabric_fpga_dma_finish_m1_o6; - output fabric_fpga_dma_finish_m2_o1; - output fabric_fpga_dma_finish_m2_o2; - output fabric_fpga_dma_finish_m2_o3; - output fabric_fpga_dma_finish_m2_o4; - output fabric_fpga_dma_finish_m2_o5; - output fabric_fpga_dma_finish_m2_o6; - input fabric_fpga_dma_last_m1_i1; - input fabric_fpga_dma_last_m1_i2; - input fabric_fpga_dma_last_m1_i3; - input fabric_fpga_dma_last_m1_i4; - input fabric_fpga_dma_last_m1_i5; - input fabric_fpga_dma_last_m1_i6; - input fabric_fpga_dma_last_m2_i1; - input fabric_fpga_dma_last_m2_i2; - input fabric_fpga_dma_last_m2_i3; - input fabric_fpga_dma_last_m2_i4; - input fabric_fpga_dma_last_m2_i5; - input fabric_fpga_dma_last_m2_i6; - input fabric_fpga_dma_req_m1_i1; - input fabric_fpga_dma_req_m1_i2; - input fabric_fpga_dma_req_m1_i3; - input fabric_fpga_dma_req_m1_i4; - input fabric_fpga_dma_req_m1_i5; - input fabric_fpga_dma_req_m1_i6; - input fabric_fpga_dma_req_m2_i1; - input fabric_fpga_dma_req_m2_i2; - input fabric_fpga_dma_req_m2_i3; - input fabric_fpga_dma_req_m2_i4; - input fabric_fpga_dma_req_m2_i5; - input fabric_fpga_dma_req_m2_i6; - input fabric_fpga_dma_single_m1_i1; - input fabric_fpga_dma_single_m1_i2; - input fabric_fpga_dma_single_m1_i3; - input fabric_fpga_dma_single_m1_i4; - input fabric_fpga_dma_single_m1_i5; - input fabric_fpga_dma_single_m1_i6; - input fabric_fpga_dma_single_m2_i1; - input fabric_fpga_dma_single_m2_i2; - input fabric_fpga_dma_single_m2_i3; - input fabric_fpga_dma_single_m2_i4; - input fabric_fpga_dma_single_m2_i5; - input fabric_fpga_dma_single_m2_i6; - input fabric_fpga_events60_i1; - input fabric_fpga_events60_i10; - input fabric_fpga_events60_i11; - input fabric_fpga_events60_i12; - input fabric_fpga_events60_i13; - input fabric_fpga_events60_i14; - input fabric_fpga_events60_i15; - input fabric_fpga_events60_i16; - input fabric_fpga_events60_i17; - input fabric_fpga_events60_i18; - input fabric_fpga_events60_i19; - input fabric_fpga_events60_i2; - input fabric_fpga_events60_i20; - input fabric_fpga_events60_i21; - input fabric_fpga_events60_i22; - input fabric_fpga_events60_i23; - input fabric_fpga_events60_i24; - input fabric_fpga_events60_i25; - input fabric_fpga_events60_i26; - input fabric_fpga_events60_i27; - input fabric_fpga_events60_i28; - input fabric_fpga_events60_i29; - input fabric_fpga_events60_i3; - input fabric_fpga_events60_i30; - input fabric_fpga_events60_i31; - input fabric_fpga_events60_i32; - input fabric_fpga_events60_i33; - input fabric_fpga_events60_i34; - input fabric_fpga_events60_i35; - input fabric_fpga_events60_i36; - input fabric_fpga_events60_i37; - input fabric_fpga_events60_i38; - input fabric_fpga_events60_i39; - input fabric_fpga_events60_i4; - input fabric_fpga_events60_i40; - input fabric_fpga_events60_i41; - input fabric_fpga_events60_i42; - input fabric_fpga_events60_i43; - input fabric_fpga_events60_i44; - input fabric_fpga_events60_i45; - input fabric_fpga_events60_i46; - input fabric_fpga_events60_i47; - input fabric_fpga_events60_i48; - input fabric_fpga_events60_i49; - input fabric_fpga_events60_i5; - input fabric_fpga_events60_i50; - input fabric_fpga_events60_i51; - input fabric_fpga_events60_i52; - input fabric_fpga_events60_i53; - input fabric_fpga_events60_i54; - input fabric_fpga_events60_i55; - input fabric_fpga_events60_i56; - input fabric_fpga_events60_i57; - input fabric_fpga_events60_i58; - input fabric_fpga_events60_i59; - input fabric_fpga_events60_i6; - input fabric_fpga_events60_i60; - input fabric_fpga_events60_i7; - input fabric_fpga_events60_i8; - input fabric_fpga_events60_i9; - input fabric_fpga_interrupt_in_i1; - input fabric_fpga_interrupt_in_i10; - input fabric_fpga_interrupt_in_i100; - input fabric_fpga_interrupt_in_i101; - input fabric_fpga_interrupt_in_i102; - input fabric_fpga_interrupt_in_i103; - input fabric_fpga_interrupt_in_i104; - input fabric_fpga_interrupt_in_i105; - input fabric_fpga_interrupt_in_i106; - input fabric_fpga_interrupt_in_i107; - input fabric_fpga_interrupt_in_i108; - input fabric_fpga_interrupt_in_i109; - input fabric_fpga_interrupt_in_i11; - input fabric_fpga_interrupt_in_i110; - input fabric_fpga_interrupt_in_i111; - input fabric_fpga_interrupt_in_i112; - input fabric_fpga_interrupt_in_i113; - input fabric_fpga_interrupt_in_i114; - input fabric_fpga_interrupt_in_i115; - input fabric_fpga_interrupt_in_i116; - input fabric_fpga_interrupt_in_i117; - input fabric_fpga_interrupt_in_i118; - input fabric_fpga_interrupt_in_i119; - input fabric_fpga_interrupt_in_i12; - input fabric_fpga_interrupt_in_i120; - input fabric_fpga_interrupt_in_i13; - input fabric_fpga_interrupt_in_i14; - input fabric_fpga_interrupt_in_i15; - input fabric_fpga_interrupt_in_i16; - input fabric_fpga_interrupt_in_i17; - input fabric_fpga_interrupt_in_i18; - input fabric_fpga_interrupt_in_i19; - input fabric_fpga_interrupt_in_i2; - input fabric_fpga_interrupt_in_i20; - input fabric_fpga_interrupt_in_i21; - input fabric_fpga_interrupt_in_i22; - input fabric_fpga_interrupt_in_i23; - input fabric_fpga_interrupt_in_i24; - input fabric_fpga_interrupt_in_i25; - input fabric_fpga_interrupt_in_i26; - input fabric_fpga_interrupt_in_i27; - input fabric_fpga_interrupt_in_i28; - input fabric_fpga_interrupt_in_i29; - input fabric_fpga_interrupt_in_i3; - input fabric_fpga_interrupt_in_i30; - input fabric_fpga_interrupt_in_i31; - input fabric_fpga_interrupt_in_i32; - input fabric_fpga_interrupt_in_i33; - input fabric_fpga_interrupt_in_i34; - input fabric_fpga_interrupt_in_i35; - input fabric_fpga_interrupt_in_i36; - input fabric_fpga_interrupt_in_i37; - input fabric_fpga_interrupt_in_i38; - input fabric_fpga_interrupt_in_i39; - input fabric_fpga_interrupt_in_i4; - input fabric_fpga_interrupt_in_i40; - input fabric_fpga_interrupt_in_i41; - input fabric_fpga_interrupt_in_i42; - input fabric_fpga_interrupt_in_i43; - input fabric_fpga_interrupt_in_i44; - input fabric_fpga_interrupt_in_i45; - input fabric_fpga_interrupt_in_i46; - input fabric_fpga_interrupt_in_i47; - input fabric_fpga_interrupt_in_i48; - input fabric_fpga_interrupt_in_i49; - input fabric_fpga_interrupt_in_i5; - input fabric_fpga_interrupt_in_i50; - input fabric_fpga_interrupt_in_i51; - input fabric_fpga_interrupt_in_i52; - input fabric_fpga_interrupt_in_i53; - input fabric_fpga_interrupt_in_i54; - input fabric_fpga_interrupt_in_i55; - input fabric_fpga_interrupt_in_i56; - input fabric_fpga_interrupt_in_i57; - input fabric_fpga_interrupt_in_i58; - input fabric_fpga_interrupt_in_i59; - input fabric_fpga_interrupt_in_i6; - input fabric_fpga_interrupt_in_i60; - input fabric_fpga_interrupt_in_i61; - input fabric_fpga_interrupt_in_i62; - input fabric_fpga_interrupt_in_i63; - input fabric_fpga_interrupt_in_i64; - input fabric_fpga_interrupt_in_i65; - input fabric_fpga_interrupt_in_i66; - input fabric_fpga_interrupt_in_i67; - input fabric_fpga_interrupt_in_i68; - input fabric_fpga_interrupt_in_i69; - input fabric_fpga_interrupt_in_i7; - input fabric_fpga_interrupt_in_i70; - input fabric_fpga_interrupt_in_i71; - input fabric_fpga_interrupt_in_i72; - input fabric_fpga_interrupt_in_i73; - input fabric_fpga_interrupt_in_i74; - input fabric_fpga_interrupt_in_i75; - input fabric_fpga_interrupt_in_i76; - input fabric_fpga_interrupt_in_i77; - input fabric_fpga_interrupt_in_i78; - input fabric_fpga_interrupt_in_i79; - input fabric_fpga_interrupt_in_i8; - input fabric_fpga_interrupt_in_i80; - input fabric_fpga_interrupt_in_i81; - input fabric_fpga_interrupt_in_i82; - input fabric_fpga_interrupt_in_i83; - input fabric_fpga_interrupt_in_i84; - input fabric_fpga_interrupt_in_i85; - input fabric_fpga_interrupt_in_i86; - input fabric_fpga_interrupt_in_i87; - input fabric_fpga_interrupt_in_i88; - input fabric_fpga_interrupt_in_i89; - input fabric_fpga_interrupt_in_i9; - input fabric_fpga_interrupt_in_i90; - input fabric_fpga_interrupt_in_i91; - input fabric_fpga_interrupt_in_i92; - input fabric_fpga_interrupt_in_i93; - input fabric_fpga_interrupt_in_i94; - input fabric_fpga_interrupt_in_i95; - input fabric_fpga_interrupt_in_i96; - input fabric_fpga_interrupt_in_i97; - input fabric_fpga_interrupt_in_i98; - input fabric_fpga_interrupt_in_i99; - input fabric_fpga_nic_rstn_i1; - input fabric_fpga_nic_rstn_i10; - input fabric_fpga_nic_rstn_i2; - input fabric_fpga_nic_rstn_i3; - input fabric_fpga_nic_rstn_i4; - input fabric_fpga_nic_rstn_i5; - input fabric_fpga_nic_rstn_i6; - input fabric_fpga_nic_rstn_i7; - input fabric_fpga_nic_rstn_i8; - input fabric_fpga_nic_rstn_i9; - output fabric_fpga_paddr_apb_o1; - output fabric_fpga_paddr_apb_o10; - output fabric_fpga_paddr_apb_o11; - output fabric_fpga_paddr_apb_o12; - output fabric_fpga_paddr_apb_o13; - output fabric_fpga_paddr_apb_o14; - output fabric_fpga_paddr_apb_o15; - output fabric_fpga_paddr_apb_o16; - output fabric_fpga_paddr_apb_o17; - output fabric_fpga_paddr_apb_o18; - output fabric_fpga_paddr_apb_o19; - output fabric_fpga_paddr_apb_o2; - output fabric_fpga_paddr_apb_o20; - output fabric_fpga_paddr_apb_o21; - output fabric_fpga_paddr_apb_o22; - output fabric_fpga_paddr_apb_o23; - output fabric_fpga_paddr_apb_o24; - output fabric_fpga_paddr_apb_o25; - output fabric_fpga_paddr_apb_o26; - output fabric_fpga_paddr_apb_o27; - output fabric_fpga_paddr_apb_o28; - output fabric_fpga_paddr_apb_o29; - output fabric_fpga_paddr_apb_o3; - output fabric_fpga_paddr_apb_o30; - output fabric_fpga_paddr_apb_o31; - output fabric_fpga_paddr_apb_o32; - output fabric_fpga_paddr_apb_o4; - output fabric_fpga_paddr_apb_o5; - output fabric_fpga_paddr_apb_o6; - output fabric_fpga_paddr_apb_o7; - output fabric_fpga_paddr_apb_o8; - output fabric_fpga_paddr_apb_o9; - output fabric_fpga_penable_apb_o; - input fabric_fpga_pmrstn_i; - input fabric_fpga_prdata_apb_i1; - input fabric_fpga_prdata_apb_i10; - input fabric_fpga_prdata_apb_i11; - input fabric_fpga_prdata_apb_i12; - input fabric_fpga_prdata_apb_i13; - input fabric_fpga_prdata_apb_i14; - input fabric_fpga_prdata_apb_i15; - input fabric_fpga_prdata_apb_i16; - input fabric_fpga_prdata_apb_i17; - input fabric_fpga_prdata_apb_i18; - input fabric_fpga_prdata_apb_i19; - input fabric_fpga_prdata_apb_i2; - input fabric_fpga_prdata_apb_i20; - input fabric_fpga_prdata_apb_i21; - input fabric_fpga_prdata_apb_i22; - input fabric_fpga_prdata_apb_i23; - input fabric_fpga_prdata_apb_i24; - input fabric_fpga_prdata_apb_i25; - input fabric_fpga_prdata_apb_i26; - input fabric_fpga_prdata_apb_i27; - input fabric_fpga_prdata_apb_i28; - input fabric_fpga_prdata_apb_i29; - input fabric_fpga_prdata_apb_i3; - input fabric_fpga_prdata_apb_i30; - input fabric_fpga_prdata_apb_i31; - input fabric_fpga_prdata_apb_i32; - input fabric_fpga_prdata_apb_i4; - input fabric_fpga_prdata_apb_i5; - input fabric_fpga_prdata_apb_i6; - input fabric_fpga_prdata_apb_i7; - input fabric_fpga_prdata_apb_i8; - input fabric_fpga_prdata_apb_i9; - input fabric_fpga_pready_apb_i; - output fabric_fpga_psel_apb_o; - input fabric_fpga_pslverr_apb_i; - output fabric_fpga_pwdata_apb_o1; - output fabric_fpga_pwdata_apb_o10; - output fabric_fpga_pwdata_apb_o11; - output fabric_fpga_pwdata_apb_o12; - output fabric_fpga_pwdata_apb_o13; - output fabric_fpga_pwdata_apb_o14; - output fabric_fpga_pwdata_apb_o15; - output fabric_fpga_pwdata_apb_o16; - output fabric_fpga_pwdata_apb_o17; - output fabric_fpga_pwdata_apb_o18; - output fabric_fpga_pwdata_apb_o19; - output fabric_fpga_pwdata_apb_o2; - output fabric_fpga_pwdata_apb_o20; - output fabric_fpga_pwdata_apb_o21; - output fabric_fpga_pwdata_apb_o22; - output fabric_fpga_pwdata_apb_o23; - output fabric_fpga_pwdata_apb_o24; - output fabric_fpga_pwdata_apb_o25; - output fabric_fpga_pwdata_apb_o26; - output fabric_fpga_pwdata_apb_o27; - output fabric_fpga_pwdata_apb_o28; - output fabric_fpga_pwdata_apb_o29; - output fabric_fpga_pwdata_apb_o3; - output fabric_fpga_pwdata_apb_o30; - output fabric_fpga_pwdata_apb_o31; - output fabric_fpga_pwdata_apb_o32; - output fabric_fpga_pwdata_apb_o4; - output fabric_fpga_pwdata_apb_o5; - output fabric_fpga_pwdata_apb_o6; - output fabric_fpga_pwdata_apb_o7; - output fabric_fpga_pwdata_apb_o8; - output fabric_fpga_pwdata_apb_o9; - output fabric_fpga_pwrite_apb_o; - output fabric_fpga_rdata_axi_m1_o1; - output fabric_fpga_rdata_axi_m1_o10; - output fabric_fpga_rdata_axi_m1_o100; - output fabric_fpga_rdata_axi_m1_o101; - output fabric_fpga_rdata_axi_m1_o102; - output fabric_fpga_rdata_axi_m1_o103; - output fabric_fpga_rdata_axi_m1_o104; - output fabric_fpga_rdata_axi_m1_o105; - output fabric_fpga_rdata_axi_m1_o106; - output fabric_fpga_rdata_axi_m1_o107; - output fabric_fpga_rdata_axi_m1_o108; - output fabric_fpga_rdata_axi_m1_o109; - output fabric_fpga_rdata_axi_m1_o11; - output fabric_fpga_rdata_axi_m1_o110; - output fabric_fpga_rdata_axi_m1_o111; - output fabric_fpga_rdata_axi_m1_o112; - output fabric_fpga_rdata_axi_m1_o113; - output fabric_fpga_rdata_axi_m1_o114; - output fabric_fpga_rdata_axi_m1_o115; - output fabric_fpga_rdata_axi_m1_o116; - output fabric_fpga_rdata_axi_m1_o117; - output fabric_fpga_rdata_axi_m1_o118; - output fabric_fpga_rdata_axi_m1_o119; - output fabric_fpga_rdata_axi_m1_o12; - output fabric_fpga_rdata_axi_m1_o120; - output fabric_fpga_rdata_axi_m1_o121; - output fabric_fpga_rdata_axi_m1_o122; - output fabric_fpga_rdata_axi_m1_o123; - output fabric_fpga_rdata_axi_m1_o124; - output fabric_fpga_rdata_axi_m1_o125; - output fabric_fpga_rdata_axi_m1_o126; - output fabric_fpga_rdata_axi_m1_o127; - output fabric_fpga_rdata_axi_m1_o128; - output fabric_fpga_rdata_axi_m1_o13; - output fabric_fpga_rdata_axi_m1_o14; - output fabric_fpga_rdata_axi_m1_o15; - output fabric_fpga_rdata_axi_m1_o16; - output fabric_fpga_rdata_axi_m1_o17; - output fabric_fpga_rdata_axi_m1_o18; - output fabric_fpga_rdata_axi_m1_o19; - output fabric_fpga_rdata_axi_m1_o2; - output fabric_fpga_rdata_axi_m1_o20; - output fabric_fpga_rdata_axi_m1_o21; - output fabric_fpga_rdata_axi_m1_o22; - output fabric_fpga_rdata_axi_m1_o23; - output fabric_fpga_rdata_axi_m1_o24; - output fabric_fpga_rdata_axi_m1_o25; - output fabric_fpga_rdata_axi_m1_o26; - output fabric_fpga_rdata_axi_m1_o27; - output fabric_fpga_rdata_axi_m1_o28; - output fabric_fpga_rdata_axi_m1_o29; - output fabric_fpga_rdata_axi_m1_o3; - output fabric_fpga_rdata_axi_m1_o30; - output fabric_fpga_rdata_axi_m1_o31; - output fabric_fpga_rdata_axi_m1_o32; - output fabric_fpga_rdata_axi_m1_o33; - output fabric_fpga_rdata_axi_m1_o34; - output fabric_fpga_rdata_axi_m1_o35; - output fabric_fpga_rdata_axi_m1_o36; - output fabric_fpga_rdata_axi_m1_o37; - output fabric_fpga_rdata_axi_m1_o38; - output fabric_fpga_rdata_axi_m1_o39; - output fabric_fpga_rdata_axi_m1_o4; - output fabric_fpga_rdata_axi_m1_o40; - output fabric_fpga_rdata_axi_m1_o41; - output fabric_fpga_rdata_axi_m1_o42; - output fabric_fpga_rdata_axi_m1_o43; - output fabric_fpga_rdata_axi_m1_o44; - output fabric_fpga_rdata_axi_m1_o45; - output fabric_fpga_rdata_axi_m1_o46; - output fabric_fpga_rdata_axi_m1_o47; - output fabric_fpga_rdata_axi_m1_o48; - output fabric_fpga_rdata_axi_m1_o49; - output fabric_fpga_rdata_axi_m1_o5; - output fabric_fpga_rdata_axi_m1_o50; - output fabric_fpga_rdata_axi_m1_o51; - output fabric_fpga_rdata_axi_m1_o52; - output fabric_fpga_rdata_axi_m1_o53; - output fabric_fpga_rdata_axi_m1_o54; - output fabric_fpga_rdata_axi_m1_o55; - output fabric_fpga_rdata_axi_m1_o56; - output fabric_fpga_rdata_axi_m1_o57; - output fabric_fpga_rdata_axi_m1_o58; - output fabric_fpga_rdata_axi_m1_o59; - output fabric_fpga_rdata_axi_m1_o6; - output fabric_fpga_rdata_axi_m1_o60; - output fabric_fpga_rdata_axi_m1_o61; - output fabric_fpga_rdata_axi_m1_o62; - output fabric_fpga_rdata_axi_m1_o63; - output fabric_fpga_rdata_axi_m1_o64; - output fabric_fpga_rdata_axi_m1_o65; - output fabric_fpga_rdata_axi_m1_o66; - output fabric_fpga_rdata_axi_m1_o67; - output fabric_fpga_rdata_axi_m1_o68; - output fabric_fpga_rdata_axi_m1_o69; - output fabric_fpga_rdata_axi_m1_o7; - output fabric_fpga_rdata_axi_m1_o70; - output fabric_fpga_rdata_axi_m1_o71; - output fabric_fpga_rdata_axi_m1_o72; - output fabric_fpga_rdata_axi_m1_o73; - output fabric_fpga_rdata_axi_m1_o74; - output fabric_fpga_rdata_axi_m1_o75; - output fabric_fpga_rdata_axi_m1_o76; - output fabric_fpga_rdata_axi_m1_o77; - output fabric_fpga_rdata_axi_m1_o78; - output fabric_fpga_rdata_axi_m1_o79; - output fabric_fpga_rdata_axi_m1_o8; - output fabric_fpga_rdata_axi_m1_o80; - output fabric_fpga_rdata_axi_m1_o81; - output fabric_fpga_rdata_axi_m1_o82; - output fabric_fpga_rdata_axi_m1_o83; - output fabric_fpga_rdata_axi_m1_o84; - output fabric_fpga_rdata_axi_m1_o85; - output fabric_fpga_rdata_axi_m1_o86; - output fabric_fpga_rdata_axi_m1_o87; - output fabric_fpga_rdata_axi_m1_o88; - output fabric_fpga_rdata_axi_m1_o89; - output fabric_fpga_rdata_axi_m1_o9; - output fabric_fpga_rdata_axi_m1_o90; - output fabric_fpga_rdata_axi_m1_o91; - output fabric_fpga_rdata_axi_m1_o92; - output fabric_fpga_rdata_axi_m1_o93; - output fabric_fpga_rdata_axi_m1_o94; - output fabric_fpga_rdata_axi_m1_o95; - output fabric_fpga_rdata_axi_m1_o96; - output fabric_fpga_rdata_axi_m1_o97; - output fabric_fpga_rdata_axi_m1_o98; - output fabric_fpga_rdata_axi_m1_o99; - output fabric_fpga_rdata_axi_m2_o1; - output fabric_fpga_rdata_axi_m2_o10; - output fabric_fpga_rdata_axi_m2_o100; - output fabric_fpga_rdata_axi_m2_o101; - output fabric_fpga_rdata_axi_m2_o102; - output fabric_fpga_rdata_axi_m2_o103; - output fabric_fpga_rdata_axi_m2_o104; - output fabric_fpga_rdata_axi_m2_o105; - output fabric_fpga_rdata_axi_m2_o106; - output fabric_fpga_rdata_axi_m2_o107; - output fabric_fpga_rdata_axi_m2_o108; - output fabric_fpga_rdata_axi_m2_o109; - output fabric_fpga_rdata_axi_m2_o11; - output fabric_fpga_rdata_axi_m2_o110; - output fabric_fpga_rdata_axi_m2_o111; - output fabric_fpga_rdata_axi_m2_o112; - output fabric_fpga_rdata_axi_m2_o113; - output fabric_fpga_rdata_axi_m2_o114; - output fabric_fpga_rdata_axi_m2_o115; - output fabric_fpga_rdata_axi_m2_o116; - output fabric_fpga_rdata_axi_m2_o117; - output fabric_fpga_rdata_axi_m2_o118; - output fabric_fpga_rdata_axi_m2_o119; - output fabric_fpga_rdata_axi_m2_o12; - output fabric_fpga_rdata_axi_m2_o120; - output fabric_fpga_rdata_axi_m2_o121; - output fabric_fpga_rdata_axi_m2_o122; - output fabric_fpga_rdata_axi_m2_o123; - output fabric_fpga_rdata_axi_m2_o124; - output fabric_fpga_rdata_axi_m2_o125; - output fabric_fpga_rdata_axi_m2_o126; - output fabric_fpga_rdata_axi_m2_o127; - output fabric_fpga_rdata_axi_m2_o128; - output fabric_fpga_rdata_axi_m2_o13; - output fabric_fpga_rdata_axi_m2_o14; - output fabric_fpga_rdata_axi_m2_o15; - output fabric_fpga_rdata_axi_m2_o16; - output fabric_fpga_rdata_axi_m2_o17; - output fabric_fpga_rdata_axi_m2_o18; - output fabric_fpga_rdata_axi_m2_o19; - output fabric_fpga_rdata_axi_m2_o2; - output fabric_fpga_rdata_axi_m2_o20; - output fabric_fpga_rdata_axi_m2_o21; - output fabric_fpga_rdata_axi_m2_o22; - output fabric_fpga_rdata_axi_m2_o23; - output fabric_fpga_rdata_axi_m2_o24; - output fabric_fpga_rdata_axi_m2_o25; - output fabric_fpga_rdata_axi_m2_o26; - output fabric_fpga_rdata_axi_m2_o27; - output fabric_fpga_rdata_axi_m2_o28; - output fabric_fpga_rdata_axi_m2_o29; - output fabric_fpga_rdata_axi_m2_o3; - output fabric_fpga_rdata_axi_m2_o30; - output fabric_fpga_rdata_axi_m2_o31; - output fabric_fpga_rdata_axi_m2_o32; - output fabric_fpga_rdata_axi_m2_o33; - output fabric_fpga_rdata_axi_m2_o34; - output fabric_fpga_rdata_axi_m2_o35; - output fabric_fpga_rdata_axi_m2_o36; - output fabric_fpga_rdata_axi_m2_o37; - output fabric_fpga_rdata_axi_m2_o38; - output fabric_fpga_rdata_axi_m2_o39; - output fabric_fpga_rdata_axi_m2_o4; - output fabric_fpga_rdata_axi_m2_o40; - output fabric_fpga_rdata_axi_m2_o41; - output fabric_fpga_rdata_axi_m2_o42; - output fabric_fpga_rdata_axi_m2_o43; - output fabric_fpga_rdata_axi_m2_o44; - output fabric_fpga_rdata_axi_m2_o45; - output fabric_fpga_rdata_axi_m2_o46; - output fabric_fpga_rdata_axi_m2_o47; - output fabric_fpga_rdata_axi_m2_o48; - output fabric_fpga_rdata_axi_m2_o49; - output fabric_fpga_rdata_axi_m2_o5; - output fabric_fpga_rdata_axi_m2_o50; - output fabric_fpga_rdata_axi_m2_o51; - output fabric_fpga_rdata_axi_m2_o52; - output fabric_fpga_rdata_axi_m2_o53; - output fabric_fpga_rdata_axi_m2_o54; - output fabric_fpga_rdata_axi_m2_o55; - output fabric_fpga_rdata_axi_m2_o56; - output fabric_fpga_rdata_axi_m2_o57; - output fabric_fpga_rdata_axi_m2_o58; - output fabric_fpga_rdata_axi_m2_o59; - output fabric_fpga_rdata_axi_m2_o6; - output fabric_fpga_rdata_axi_m2_o60; - output fabric_fpga_rdata_axi_m2_o61; - output fabric_fpga_rdata_axi_m2_o62; - output fabric_fpga_rdata_axi_m2_o63; - output fabric_fpga_rdata_axi_m2_o64; - output fabric_fpga_rdata_axi_m2_o65; - output fabric_fpga_rdata_axi_m2_o66; - output fabric_fpga_rdata_axi_m2_o67; - output fabric_fpga_rdata_axi_m2_o68; - output fabric_fpga_rdata_axi_m2_o69; - output fabric_fpga_rdata_axi_m2_o7; - output fabric_fpga_rdata_axi_m2_o70; - output fabric_fpga_rdata_axi_m2_o71; - output fabric_fpga_rdata_axi_m2_o72; - output fabric_fpga_rdata_axi_m2_o73; - output fabric_fpga_rdata_axi_m2_o74; - output fabric_fpga_rdata_axi_m2_o75; - output fabric_fpga_rdata_axi_m2_o76; - output fabric_fpga_rdata_axi_m2_o77; - output fabric_fpga_rdata_axi_m2_o78; - output fabric_fpga_rdata_axi_m2_o79; - output fabric_fpga_rdata_axi_m2_o8; - output fabric_fpga_rdata_axi_m2_o80; - output fabric_fpga_rdata_axi_m2_o81; - output fabric_fpga_rdata_axi_m2_o82; - output fabric_fpga_rdata_axi_m2_o83; - output fabric_fpga_rdata_axi_m2_o84; - output fabric_fpga_rdata_axi_m2_o85; - output fabric_fpga_rdata_axi_m2_o86; - output fabric_fpga_rdata_axi_m2_o87; - output fabric_fpga_rdata_axi_m2_o88; - output fabric_fpga_rdata_axi_m2_o89; - output fabric_fpga_rdata_axi_m2_o9; - output fabric_fpga_rdata_axi_m2_o90; - output fabric_fpga_rdata_axi_m2_o91; - output fabric_fpga_rdata_axi_m2_o92; - output fabric_fpga_rdata_axi_m2_o93; - output fabric_fpga_rdata_axi_m2_o94; - output fabric_fpga_rdata_axi_m2_o95; - output fabric_fpga_rdata_axi_m2_o96; - output fabric_fpga_rdata_axi_m2_o97; - output fabric_fpga_rdata_axi_m2_o98; - output fabric_fpga_rdata_axi_m2_o99; - input fabric_fpga_rdata_axi_s1_i1; - input fabric_fpga_rdata_axi_s1_i10; - input fabric_fpga_rdata_axi_s1_i100; - input fabric_fpga_rdata_axi_s1_i101; - input fabric_fpga_rdata_axi_s1_i102; - input fabric_fpga_rdata_axi_s1_i103; - input fabric_fpga_rdata_axi_s1_i104; - input fabric_fpga_rdata_axi_s1_i105; - input fabric_fpga_rdata_axi_s1_i106; - input fabric_fpga_rdata_axi_s1_i107; - input fabric_fpga_rdata_axi_s1_i108; - input fabric_fpga_rdata_axi_s1_i109; - input fabric_fpga_rdata_axi_s1_i11; - input fabric_fpga_rdata_axi_s1_i110; - input fabric_fpga_rdata_axi_s1_i111; - input fabric_fpga_rdata_axi_s1_i112; - input fabric_fpga_rdata_axi_s1_i113; - input fabric_fpga_rdata_axi_s1_i114; - input fabric_fpga_rdata_axi_s1_i115; - input fabric_fpga_rdata_axi_s1_i116; - input fabric_fpga_rdata_axi_s1_i117; - input fabric_fpga_rdata_axi_s1_i118; - input fabric_fpga_rdata_axi_s1_i119; - input fabric_fpga_rdata_axi_s1_i12; - input fabric_fpga_rdata_axi_s1_i120; - input fabric_fpga_rdata_axi_s1_i121; - input fabric_fpga_rdata_axi_s1_i122; - input fabric_fpga_rdata_axi_s1_i123; - input fabric_fpga_rdata_axi_s1_i124; - input fabric_fpga_rdata_axi_s1_i125; - input fabric_fpga_rdata_axi_s1_i126; - input fabric_fpga_rdata_axi_s1_i127; - input fabric_fpga_rdata_axi_s1_i128; - input fabric_fpga_rdata_axi_s1_i13; - input fabric_fpga_rdata_axi_s1_i14; - input fabric_fpga_rdata_axi_s1_i15; - input fabric_fpga_rdata_axi_s1_i16; - input fabric_fpga_rdata_axi_s1_i17; - input fabric_fpga_rdata_axi_s1_i18; - input fabric_fpga_rdata_axi_s1_i19; - input fabric_fpga_rdata_axi_s1_i2; - input fabric_fpga_rdata_axi_s1_i20; - input fabric_fpga_rdata_axi_s1_i21; - input fabric_fpga_rdata_axi_s1_i22; - input fabric_fpga_rdata_axi_s1_i23; - input fabric_fpga_rdata_axi_s1_i24; - input fabric_fpga_rdata_axi_s1_i25; - input fabric_fpga_rdata_axi_s1_i26; - input fabric_fpga_rdata_axi_s1_i27; - input fabric_fpga_rdata_axi_s1_i28; - input fabric_fpga_rdata_axi_s1_i29; - input fabric_fpga_rdata_axi_s1_i3; - input fabric_fpga_rdata_axi_s1_i30; - input fabric_fpga_rdata_axi_s1_i31; - input fabric_fpga_rdata_axi_s1_i32; - input fabric_fpga_rdata_axi_s1_i33; - input fabric_fpga_rdata_axi_s1_i34; - input fabric_fpga_rdata_axi_s1_i35; - input fabric_fpga_rdata_axi_s1_i36; - input fabric_fpga_rdata_axi_s1_i37; - input fabric_fpga_rdata_axi_s1_i38; - input fabric_fpga_rdata_axi_s1_i39; - input fabric_fpga_rdata_axi_s1_i4; - input fabric_fpga_rdata_axi_s1_i40; - input fabric_fpga_rdata_axi_s1_i41; - input fabric_fpga_rdata_axi_s1_i42; - input fabric_fpga_rdata_axi_s1_i43; - input fabric_fpga_rdata_axi_s1_i44; - input fabric_fpga_rdata_axi_s1_i45; - input fabric_fpga_rdata_axi_s1_i46; - input fabric_fpga_rdata_axi_s1_i47; - input fabric_fpga_rdata_axi_s1_i48; - input fabric_fpga_rdata_axi_s1_i49; - input fabric_fpga_rdata_axi_s1_i5; - input fabric_fpga_rdata_axi_s1_i50; - input fabric_fpga_rdata_axi_s1_i51; - input fabric_fpga_rdata_axi_s1_i52; - input fabric_fpga_rdata_axi_s1_i53; - input fabric_fpga_rdata_axi_s1_i54; - input fabric_fpga_rdata_axi_s1_i55; - input fabric_fpga_rdata_axi_s1_i56; - input fabric_fpga_rdata_axi_s1_i57; - input fabric_fpga_rdata_axi_s1_i58; - input fabric_fpga_rdata_axi_s1_i59; - input fabric_fpga_rdata_axi_s1_i6; - input fabric_fpga_rdata_axi_s1_i60; - input fabric_fpga_rdata_axi_s1_i61; - input fabric_fpga_rdata_axi_s1_i62; - input fabric_fpga_rdata_axi_s1_i63; - input fabric_fpga_rdata_axi_s1_i64; - input fabric_fpga_rdata_axi_s1_i65; - input fabric_fpga_rdata_axi_s1_i66; - input fabric_fpga_rdata_axi_s1_i67; - input fabric_fpga_rdata_axi_s1_i68; - input fabric_fpga_rdata_axi_s1_i69; - input fabric_fpga_rdata_axi_s1_i7; - input fabric_fpga_rdata_axi_s1_i70; - input fabric_fpga_rdata_axi_s1_i71; - input fabric_fpga_rdata_axi_s1_i72; - input fabric_fpga_rdata_axi_s1_i73; - input fabric_fpga_rdata_axi_s1_i74; - input fabric_fpga_rdata_axi_s1_i75; - input fabric_fpga_rdata_axi_s1_i76; - input fabric_fpga_rdata_axi_s1_i77; - input fabric_fpga_rdata_axi_s1_i78; - input fabric_fpga_rdata_axi_s1_i79; - input fabric_fpga_rdata_axi_s1_i8; - input fabric_fpga_rdata_axi_s1_i80; - input fabric_fpga_rdata_axi_s1_i81; - input fabric_fpga_rdata_axi_s1_i82; - input fabric_fpga_rdata_axi_s1_i83; - input fabric_fpga_rdata_axi_s1_i84; - input fabric_fpga_rdata_axi_s1_i85; - input fabric_fpga_rdata_axi_s1_i86; - input fabric_fpga_rdata_axi_s1_i87; - input fabric_fpga_rdata_axi_s1_i88; - input fabric_fpga_rdata_axi_s1_i89; - input fabric_fpga_rdata_axi_s1_i9; - input fabric_fpga_rdata_axi_s1_i90; - input fabric_fpga_rdata_axi_s1_i91; - input fabric_fpga_rdata_axi_s1_i92; - input fabric_fpga_rdata_axi_s1_i93; - input fabric_fpga_rdata_axi_s1_i94; - input fabric_fpga_rdata_axi_s1_i95; - input fabric_fpga_rdata_axi_s1_i96; - input fabric_fpga_rdata_axi_s1_i97; - input fabric_fpga_rdata_axi_s1_i98; - input fabric_fpga_rdata_axi_s1_i99; - input fabric_fpga_rdata_axi_s2_i1; - input fabric_fpga_rdata_axi_s2_i10; - input fabric_fpga_rdata_axi_s2_i100; - input fabric_fpga_rdata_axi_s2_i101; - input fabric_fpga_rdata_axi_s2_i102; - input fabric_fpga_rdata_axi_s2_i103; - input fabric_fpga_rdata_axi_s2_i104; - input fabric_fpga_rdata_axi_s2_i105; - input fabric_fpga_rdata_axi_s2_i106; - input fabric_fpga_rdata_axi_s2_i107; - input fabric_fpga_rdata_axi_s2_i108; - input fabric_fpga_rdata_axi_s2_i109; - input fabric_fpga_rdata_axi_s2_i11; - input fabric_fpga_rdata_axi_s2_i110; - input fabric_fpga_rdata_axi_s2_i111; - input fabric_fpga_rdata_axi_s2_i112; - input fabric_fpga_rdata_axi_s2_i113; - input fabric_fpga_rdata_axi_s2_i114; - input fabric_fpga_rdata_axi_s2_i115; - input fabric_fpga_rdata_axi_s2_i116; - input fabric_fpga_rdata_axi_s2_i117; - input fabric_fpga_rdata_axi_s2_i118; - input fabric_fpga_rdata_axi_s2_i119; - input fabric_fpga_rdata_axi_s2_i12; - input fabric_fpga_rdata_axi_s2_i120; - input fabric_fpga_rdata_axi_s2_i121; - input fabric_fpga_rdata_axi_s2_i122; - input fabric_fpga_rdata_axi_s2_i123; - input fabric_fpga_rdata_axi_s2_i124; - input fabric_fpga_rdata_axi_s2_i125; - input fabric_fpga_rdata_axi_s2_i126; - input fabric_fpga_rdata_axi_s2_i127; - input fabric_fpga_rdata_axi_s2_i128; - input fabric_fpga_rdata_axi_s2_i13; - input fabric_fpga_rdata_axi_s2_i14; - input fabric_fpga_rdata_axi_s2_i15; - input fabric_fpga_rdata_axi_s2_i16; - input fabric_fpga_rdata_axi_s2_i17; - input fabric_fpga_rdata_axi_s2_i18; - input fabric_fpga_rdata_axi_s2_i19; - input fabric_fpga_rdata_axi_s2_i2; - input fabric_fpga_rdata_axi_s2_i20; - input fabric_fpga_rdata_axi_s2_i21; - input fabric_fpga_rdata_axi_s2_i22; - input fabric_fpga_rdata_axi_s2_i23; - input fabric_fpga_rdata_axi_s2_i24; - input fabric_fpga_rdata_axi_s2_i25; - input fabric_fpga_rdata_axi_s2_i26; - input fabric_fpga_rdata_axi_s2_i27; - input fabric_fpga_rdata_axi_s2_i28; - input fabric_fpga_rdata_axi_s2_i29; - input fabric_fpga_rdata_axi_s2_i3; - input fabric_fpga_rdata_axi_s2_i30; - input fabric_fpga_rdata_axi_s2_i31; - input fabric_fpga_rdata_axi_s2_i32; - input fabric_fpga_rdata_axi_s2_i33; - input fabric_fpga_rdata_axi_s2_i34; - input fabric_fpga_rdata_axi_s2_i35; - input fabric_fpga_rdata_axi_s2_i36; - input fabric_fpga_rdata_axi_s2_i37; - input fabric_fpga_rdata_axi_s2_i38; - input fabric_fpga_rdata_axi_s2_i39; - input fabric_fpga_rdata_axi_s2_i4; - input fabric_fpga_rdata_axi_s2_i40; - input fabric_fpga_rdata_axi_s2_i41; - input fabric_fpga_rdata_axi_s2_i42; - input fabric_fpga_rdata_axi_s2_i43; - input fabric_fpga_rdata_axi_s2_i44; - input fabric_fpga_rdata_axi_s2_i45; - input fabric_fpga_rdata_axi_s2_i46; - input fabric_fpga_rdata_axi_s2_i47; - input fabric_fpga_rdata_axi_s2_i48; - input fabric_fpga_rdata_axi_s2_i49; - input fabric_fpga_rdata_axi_s2_i5; - input fabric_fpga_rdata_axi_s2_i50; - input fabric_fpga_rdata_axi_s2_i51; - input fabric_fpga_rdata_axi_s2_i52; - input fabric_fpga_rdata_axi_s2_i53; - input fabric_fpga_rdata_axi_s2_i54; - input fabric_fpga_rdata_axi_s2_i55; - input fabric_fpga_rdata_axi_s2_i56; - input fabric_fpga_rdata_axi_s2_i57; - input fabric_fpga_rdata_axi_s2_i58; - input fabric_fpga_rdata_axi_s2_i59; - input fabric_fpga_rdata_axi_s2_i6; - input fabric_fpga_rdata_axi_s2_i60; - input fabric_fpga_rdata_axi_s2_i61; - input fabric_fpga_rdata_axi_s2_i62; - input fabric_fpga_rdata_axi_s2_i63; - input fabric_fpga_rdata_axi_s2_i64; - input fabric_fpga_rdata_axi_s2_i65; - input fabric_fpga_rdata_axi_s2_i66; - input fabric_fpga_rdata_axi_s2_i67; - input fabric_fpga_rdata_axi_s2_i68; - input fabric_fpga_rdata_axi_s2_i69; - input fabric_fpga_rdata_axi_s2_i7; - input fabric_fpga_rdata_axi_s2_i70; - input fabric_fpga_rdata_axi_s2_i71; - input fabric_fpga_rdata_axi_s2_i72; - input fabric_fpga_rdata_axi_s2_i73; - input fabric_fpga_rdata_axi_s2_i74; - input fabric_fpga_rdata_axi_s2_i75; - input fabric_fpga_rdata_axi_s2_i76; - input fabric_fpga_rdata_axi_s2_i77; - input fabric_fpga_rdata_axi_s2_i78; - input fabric_fpga_rdata_axi_s2_i79; - input fabric_fpga_rdata_axi_s2_i8; - input fabric_fpga_rdata_axi_s2_i80; - input fabric_fpga_rdata_axi_s2_i81; - input fabric_fpga_rdata_axi_s2_i82; - input fabric_fpga_rdata_axi_s2_i83; - input fabric_fpga_rdata_axi_s2_i84; - input fabric_fpga_rdata_axi_s2_i85; - input fabric_fpga_rdata_axi_s2_i86; - input fabric_fpga_rdata_axi_s2_i87; - input fabric_fpga_rdata_axi_s2_i88; - input fabric_fpga_rdata_axi_s2_i89; - input fabric_fpga_rdata_axi_s2_i9; - input fabric_fpga_rdata_axi_s2_i90; - input fabric_fpga_rdata_axi_s2_i91; - input fabric_fpga_rdata_axi_s2_i92; - input fabric_fpga_rdata_axi_s2_i93; - input fabric_fpga_rdata_axi_s2_i94; - input fabric_fpga_rdata_axi_s2_i95; - input fabric_fpga_rdata_axi_s2_i96; - input fabric_fpga_rdata_axi_s2_i97; - input fabric_fpga_rdata_axi_s2_i98; - input fabric_fpga_rdata_axi_s2_i99; - output fabric_fpga_rid_axi_m1_o1; - output fabric_fpga_rid_axi_m1_o2; - output fabric_fpga_rid_axi_m1_o3; - output fabric_fpga_rid_axi_m1_o4; - output fabric_fpga_rid_axi_m1_o5; - output fabric_fpga_rid_axi_m2_o1; - output fabric_fpga_rid_axi_m2_o2; - output fabric_fpga_rid_axi_m2_o3; - output fabric_fpga_rid_axi_m2_o4; - output fabric_fpga_rid_axi_m2_o5; - input fabric_fpga_rid_axi_s1_i1; - input fabric_fpga_rid_axi_s1_i10; - input fabric_fpga_rid_axi_s1_i11; - input fabric_fpga_rid_axi_s1_i12; - input fabric_fpga_rid_axi_s1_i2; - input fabric_fpga_rid_axi_s1_i3; - input fabric_fpga_rid_axi_s1_i4; - input fabric_fpga_rid_axi_s1_i5; - input fabric_fpga_rid_axi_s1_i6; - input fabric_fpga_rid_axi_s1_i7; - input fabric_fpga_rid_axi_s1_i8; - input fabric_fpga_rid_axi_s1_i9; - input fabric_fpga_rid_axi_s2_i1; - input fabric_fpga_rid_axi_s2_i10; - input fabric_fpga_rid_axi_s2_i11; - input fabric_fpga_rid_axi_s2_i12; - input fabric_fpga_rid_axi_s2_i2; - input fabric_fpga_rid_axi_s2_i3; - input fabric_fpga_rid_axi_s2_i4; - input fabric_fpga_rid_axi_s2_i5; - input fabric_fpga_rid_axi_s2_i6; - input fabric_fpga_rid_axi_s2_i7; - input fabric_fpga_rid_axi_s2_i8; - input fabric_fpga_rid_axi_s2_i9; - output fabric_fpga_rlast_axi_m1_o; - output fabric_fpga_rlast_axi_m2_o; - input fabric_fpga_rlast_axi_s1_i; - input fabric_fpga_rlast_axi_s2_i; - input fabric_fpga_rready_axi_m1_i; - input fabric_fpga_rready_axi_m2_i; - output fabric_fpga_rready_axi_s1_o; - output fabric_fpga_rready_axi_s2_o; - output fabric_fpga_rresp_axi_m1_o1; - output fabric_fpga_rresp_axi_m1_o2; - output fabric_fpga_rresp_axi_m2_o1; - output fabric_fpga_rresp_axi_m2_o2; - input fabric_fpga_rresp_axi_s1_i1; - input fabric_fpga_rresp_axi_s1_i2; - input fabric_fpga_rresp_axi_s2_i1; - input fabric_fpga_rresp_axi_s2_i2; - output fabric_fpga_rvalid_axi_m1_o; - output fabric_fpga_rvalid_axi_m2_o; - input fabric_fpga_rvalid_axi_s1_i; - input fabric_fpga_rvalid_axi_s2_i; - input fabric_fpga_sysrstn_i; - output fabric_fpga_trigger_in_o1; - output fabric_fpga_trigger_in_o2; - output fabric_fpga_trigger_in_o3; - output fabric_fpga_trigger_in_o4; - output fabric_fpga_trigger_in_o5; - output fabric_fpga_trigger_in_o6; - output fabric_fpga_trigger_in_o7; - output fabric_fpga_trigger_in_o8; - input fabric_fpga_trigger_out_i1; - input fabric_fpga_trigger_out_i2; - input fabric_fpga_trigger_out_i3; - input fabric_fpga_trigger_out_i4; - input fabric_fpga_trigger_out_i5; - input fabric_fpga_trigger_out_i6; - input fabric_fpga_trigger_out_i7; - input fabric_fpga_trigger_out_i8; - input fabric_fpga_wdata_axi_m1_i1; - input fabric_fpga_wdata_axi_m1_i10; - input fabric_fpga_wdata_axi_m1_i100; - input fabric_fpga_wdata_axi_m1_i101; - input fabric_fpga_wdata_axi_m1_i102; - input fabric_fpga_wdata_axi_m1_i103; - input fabric_fpga_wdata_axi_m1_i104; - input fabric_fpga_wdata_axi_m1_i105; - input fabric_fpga_wdata_axi_m1_i106; - input fabric_fpga_wdata_axi_m1_i107; - input fabric_fpga_wdata_axi_m1_i108; - input fabric_fpga_wdata_axi_m1_i109; - input fabric_fpga_wdata_axi_m1_i11; - input fabric_fpga_wdata_axi_m1_i110; - input fabric_fpga_wdata_axi_m1_i111; - input fabric_fpga_wdata_axi_m1_i112; - input fabric_fpga_wdata_axi_m1_i113; - input fabric_fpga_wdata_axi_m1_i114; - input fabric_fpga_wdata_axi_m1_i115; - input fabric_fpga_wdata_axi_m1_i116; - input fabric_fpga_wdata_axi_m1_i117; - input fabric_fpga_wdata_axi_m1_i118; - input fabric_fpga_wdata_axi_m1_i119; - input fabric_fpga_wdata_axi_m1_i12; - input fabric_fpga_wdata_axi_m1_i120; - input fabric_fpga_wdata_axi_m1_i121; - input fabric_fpga_wdata_axi_m1_i122; - input fabric_fpga_wdata_axi_m1_i123; - input fabric_fpga_wdata_axi_m1_i124; - input fabric_fpga_wdata_axi_m1_i125; - input fabric_fpga_wdata_axi_m1_i126; - input fabric_fpga_wdata_axi_m1_i127; - input fabric_fpga_wdata_axi_m1_i128; - input fabric_fpga_wdata_axi_m1_i13; - input fabric_fpga_wdata_axi_m1_i14; - input fabric_fpga_wdata_axi_m1_i15; - input fabric_fpga_wdata_axi_m1_i16; - input fabric_fpga_wdata_axi_m1_i17; - input fabric_fpga_wdata_axi_m1_i18; - input fabric_fpga_wdata_axi_m1_i19; - input fabric_fpga_wdata_axi_m1_i2; - input fabric_fpga_wdata_axi_m1_i20; - input fabric_fpga_wdata_axi_m1_i21; - input fabric_fpga_wdata_axi_m1_i22; - input fabric_fpga_wdata_axi_m1_i23; - input fabric_fpga_wdata_axi_m1_i24; - input fabric_fpga_wdata_axi_m1_i25; - input fabric_fpga_wdata_axi_m1_i26; - input fabric_fpga_wdata_axi_m1_i27; - input fabric_fpga_wdata_axi_m1_i28; - input fabric_fpga_wdata_axi_m1_i29; - input fabric_fpga_wdata_axi_m1_i3; - input fabric_fpga_wdata_axi_m1_i30; - input fabric_fpga_wdata_axi_m1_i31; - input fabric_fpga_wdata_axi_m1_i32; - input fabric_fpga_wdata_axi_m1_i33; - input fabric_fpga_wdata_axi_m1_i34; - input fabric_fpga_wdata_axi_m1_i35; - input fabric_fpga_wdata_axi_m1_i36; - input fabric_fpga_wdata_axi_m1_i37; - input fabric_fpga_wdata_axi_m1_i38; - input fabric_fpga_wdata_axi_m1_i39; - input fabric_fpga_wdata_axi_m1_i4; - input fabric_fpga_wdata_axi_m1_i40; - input fabric_fpga_wdata_axi_m1_i41; - input fabric_fpga_wdata_axi_m1_i42; - input fabric_fpga_wdata_axi_m1_i43; - input fabric_fpga_wdata_axi_m1_i44; - input fabric_fpga_wdata_axi_m1_i45; - input fabric_fpga_wdata_axi_m1_i46; - input fabric_fpga_wdata_axi_m1_i47; - input fabric_fpga_wdata_axi_m1_i48; - input fabric_fpga_wdata_axi_m1_i49; - input fabric_fpga_wdata_axi_m1_i5; - input fabric_fpga_wdata_axi_m1_i50; - input fabric_fpga_wdata_axi_m1_i51; - input fabric_fpga_wdata_axi_m1_i52; - input fabric_fpga_wdata_axi_m1_i53; - input fabric_fpga_wdata_axi_m1_i54; - input fabric_fpga_wdata_axi_m1_i55; - input fabric_fpga_wdata_axi_m1_i56; - input fabric_fpga_wdata_axi_m1_i57; - input fabric_fpga_wdata_axi_m1_i58; - input fabric_fpga_wdata_axi_m1_i59; - input fabric_fpga_wdata_axi_m1_i6; - input fabric_fpga_wdata_axi_m1_i60; - input fabric_fpga_wdata_axi_m1_i61; - input fabric_fpga_wdata_axi_m1_i62; - input fabric_fpga_wdata_axi_m1_i63; - input fabric_fpga_wdata_axi_m1_i64; - input fabric_fpga_wdata_axi_m1_i65; - input fabric_fpga_wdata_axi_m1_i66; - input fabric_fpga_wdata_axi_m1_i67; - input fabric_fpga_wdata_axi_m1_i68; - input fabric_fpga_wdata_axi_m1_i69; - input fabric_fpga_wdata_axi_m1_i7; - input fabric_fpga_wdata_axi_m1_i70; - input fabric_fpga_wdata_axi_m1_i71; - input fabric_fpga_wdata_axi_m1_i72; - input fabric_fpga_wdata_axi_m1_i73; - input fabric_fpga_wdata_axi_m1_i74; - input fabric_fpga_wdata_axi_m1_i75; - input fabric_fpga_wdata_axi_m1_i76; - input fabric_fpga_wdata_axi_m1_i77; - input fabric_fpga_wdata_axi_m1_i78; - input fabric_fpga_wdata_axi_m1_i79; - input fabric_fpga_wdata_axi_m1_i8; - input fabric_fpga_wdata_axi_m1_i80; - input fabric_fpga_wdata_axi_m1_i81; - input fabric_fpga_wdata_axi_m1_i82; - input fabric_fpga_wdata_axi_m1_i83; - input fabric_fpga_wdata_axi_m1_i84; - input fabric_fpga_wdata_axi_m1_i85; - input fabric_fpga_wdata_axi_m1_i86; - input fabric_fpga_wdata_axi_m1_i87; - input fabric_fpga_wdata_axi_m1_i88; - input fabric_fpga_wdata_axi_m1_i89; - input fabric_fpga_wdata_axi_m1_i9; - input fabric_fpga_wdata_axi_m1_i90; - input fabric_fpga_wdata_axi_m1_i91; - input fabric_fpga_wdata_axi_m1_i92; - input fabric_fpga_wdata_axi_m1_i93; - input fabric_fpga_wdata_axi_m1_i94; - input fabric_fpga_wdata_axi_m1_i95; - input fabric_fpga_wdata_axi_m1_i96; - input fabric_fpga_wdata_axi_m1_i97; - input fabric_fpga_wdata_axi_m1_i98; - input fabric_fpga_wdata_axi_m1_i99; - input fabric_fpga_wdata_axi_m2_i1; - input fabric_fpga_wdata_axi_m2_i10; - input fabric_fpga_wdata_axi_m2_i100; - input fabric_fpga_wdata_axi_m2_i101; - input fabric_fpga_wdata_axi_m2_i102; - input fabric_fpga_wdata_axi_m2_i103; - input fabric_fpga_wdata_axi_m2_i104; - input fabric_fpga_wdata_axi_m2_i105; - input fabric_fpga_wdata_axi_m2_i106; - input fabric_fpga_wdata_axi_m2_i107; - input fabric_fpga_wdata_axi_m2_i108; - input fabric_fpga_wdata_axi_m2_i109; - input fabric_fpga_wdata_axi_m2_i11; - input fabric_fpga_wdata_axi_m2_i110; - input fabric_fpga_wdata_axi_m2_i111; - input fabric_fpga_wdata_axi_m2_i112; - input fabric_fpga_wdata_axi_m2_i113; - input fabric_fpga_wdata_axi_m2_i114; - input fabric_fpga_wdata_axi_m2_i115; - input fabric_fpga_wdata_axi_m2_i116; - input fabric_fpga_wdata_axi_m2_i117; - input fabric_fpga_wdata_axi_m2_i118; - input fabric_fpga_wdata_axi_m2_i119; - input fabric_fpga_wdata_axi_m2_i12; - input fabric_fpga_wdata_axi_m2_i120; - input fabric_fpga_wdata_axi_m2_i121; - input fabric_fpga_wdata_axi_m2_i122; - input fabric_fpga_wdata_axi_m2_i123; - input fabric_fpga_wdata_axi_m2_i124; - input fabric_fpga_wdata_axi_m2_i125; - input fabric_fpga_wdata_axi_m2_i126; - input fabric_fpga_wdata_axi_m2_i127; - input fabric_fpga_wdata_axi_m2_i128; - input fabric_fpga_wdata_axi_m2_i13; - input fabric_fpga_wdata_axi_m2_i14; - input fabric_fpga_wdata_axi_m2_i15; - input fabric_fpga_wdata_axi_m2_i16; - input fabric_fpga_wdata_axi_m2_i17; - input fabric_fpga_wdata_axi_m2_i18; - input fabric_fpga_wdata_axi_m2_i19; - input fabric_fpga_wdata_axi_m2_i2; - input fabric_fpga_wdata_axi_m2_i20; - input fabric_fpga_wdata_axi_m2_i21; - input fabric_fpga_wdata_axi_m2_i22; - input fabric_fpga_wdata_axi_m2_i23; - input fabric_fpga_wdata_axi_m2_i24; - input fabric_fpga_wdata_axi_m2_i25; - input fabric_fpga_wdata_axi_m2_i26; - input fabric_fpga_wdata_axi_m2_i27; - input fabric_fpga_wdata_axi_m2_i28; - input fabric_fpga_wdata_axi_m2_i29; - input fabric_fpga_wdata_axi_m2_i3; - input fabric_fpga_wdata_axi_m2_i30; - input fabric_fpga_wdata_axi_m2_i31; - input fabric_fpga_wdata_axi_m2_i32; - input fabric_fpga_wdata_axi_m2_i33; - input fabric_fpga_wdata_axi_m2_i34; - input fabric_fpga_wdata_axi_m2_i35; - input fabric_fpga_wdata_axi_m2_i36; - input fabric_fpga_wdata_axi_m2_i37; - input fabric_fpga_wdata_axi_m2_i38; - input fabric_fpga_wdata_axi_m2_i39; - input fabric_fpga_wdata_axi_m2_i4; - input fabric_fpga_wdata_axi_m2_i40; - input fabric_fpga_wdata_axi_m2_i41; - input fabric_fpga_wdata_axi_m2_i42; - input fabric_fpga_wdata_axi_m2_i43; - input fabric_fpga_wdata_axi_m2_i44; - input fabric_fpga_wdata_axi_m2_i45; - input fabric_fpga_wdata_axi_m2_i46; - input fabric_fpga_wdata_axi_m2_i47; - input fabric_fpga_wdata_axi_m2_i48; - input fabric_fpga_wdata_axi_m2_i49; - input fabric_fpga_wdata_axi_m2_i5; - input fabric_fpga_wdata_axi_m2_i50; - input fabric_fpga_wdata_axi_m2_i51; - input fabric_fpga_wdata_axi_m2_i52; - input fabric_fpga_wdata_axi_m2_i53; - input fabric_fpga_wdata_axi_m2_i54; - input fabric_fpga_wdata_axi_m2_i55; - input fabric_fpga_wdata_axi_m2_i56; - input fabric_fpga_wdata_axi_m2_i57; - input fabric_fpga_wdata_axi_m2_i58; - input fabric_fpga_wdata_axi_m2_i59; - input fabric_fpga_wdata_axi_m2_i6; - input fabric_fpga_wdata_axi_m2_i60; - input fabric_fpga_wdata_axi_m2_i61; - input fabric_fpga_wdata_axi_m2_i62; - input fabric_fpga_wdata_axi_m2_i63; - input fabric_fpga_wdata_axi_m2_i64; - input fabric_fpga_wdata_axi_m2_i65; - input fabric_fpga_wdata_axi_m2_i66; - input fabric_fpga_wdata_axi_m2_i67; - input fabric_fpga_wdata_axi_m2_i68; - input fabric_fpga_wdata_axi_m2_i69; - input fabric_fpga_wdata_axi_m2_i7; - input fabric_fpga_wdata_axi_m2_i70; - input fabric_fpga_wdata_axi_m2_i71; - input fabric_fpga_wdata_axi_m2_i72; - input fabric_fpga_wdata_axi_m2_i73; - input fabric_fpga_wdata_axi_m2_i74; - input fabric_fpga_wdata_axi_m2_i75; - input fabric_fpga_wdata_axi_m2_i76; - input fabric_fpga_wdata_axi_m2_i77; - input fabric_fpga_wdata_axi_m2_i78; - input fabric_fpga_wdata_axi_m2_i79; - input fabric_fpga_wdata_axi_m2_i8; - input fabric_fpga_wdata_axi_m2_i80; - input fabric_fpga_wdata_axi_m2_i81; - input fabric_fpga_wdata_axi_m2_i82; - input fabric_fpga_wdata_axi_m2_i83; - input fabric_fpga_wdata_axi_m2_i84; - input fabric_fpga_wdata_axi_m2_i85; - input fabric_fpga_wdata_axi_m2_i86; - input fabric_fpga_wdata_axi_m2_i87; - input fabric_fpga_wdata_axi_m2_i88; - input fabric_fpga_wdata_axi_m2_i89; - input fabric_fpga_wdata_axi_m2_i9; - input fabric_fpga_wdata_axi_m2_i90; - input fabric_fpga_wdata_axi_m2_i91; - input fabric_fpga_wdata_axi_m2_i92; - input fabric_fpga_wdata_axi_m2_i93; - input fabric_fpga_wdata_axi_m2_i94; - input fabric_fpga_wdata_axi_m2_i95; - input fabric_fpga_wdata_axi_m2_i96; - input fabric_fpga_wdata_axi_m2_i97; - input fabric_fpga_wdata_axi_m2_i98; - input fabric_fpga_wdata_axi_m2_i99; - output fabric_fpga_wdata_axi_s1_o1; - output fabric_fpga_wdata_axi_s1_o10; - output fabric_fpga_wdata_axi_s1_o100; - output fabric_fpga_wdata_axi_s1_o101; - output fabric_fpga_wdata_axi_s1_o102; - output fabric_fpga_wdata_axi_s1_o103; - output fabric_fpga_wdata_axi_s1_o104; - output fabric_fpga_wdata_axi_s1_o105; - output fabric_fpga_wdata_axi_s1_o106; - output fabric_fpga_wdata_axi_s1_o107; - output fabric_fpga_wdata_axi_s1_o108; - output fabric_fpga_wdata_axi_s1_o109; - output fabric_fpga_wdata_axi_s1_o11; - output fabric_fpga_wdata_axi_s1_o110; - output fabric_fpga_wdata_axi_s1_o111; - output fabric_fpga_wdata_axi_s1_o112; - output fabric_fpga_wdata_axi_s1_o113; - output fabric_fpga_wdata_axi_s1_o114; - output fabric_fpga_wdata_axi_s1_o115; - output fabric_fpga_wdata_axi_s1_o116; - output fabric_fpga_wdata_axi_s1_o117; - output fabric_fpga_wdata_axi_s1_o118; - output fabric_fpga_wdata_axi_s1_o119; - output fabric_fpga_wdata_axi_s1_o12; - output fabric_fpga_wdata_axi_s1_o120; - output fabric_fpga_wdata_axi_s1_o121; - output fabric_fpga_wdata_axi_s1_o122; - output fabric_fpga_wdata_axi_s1_o123; - output fabric_fpga_wdata_axi_s1_o124; - output fabric_fpga_wdata_axi_s1_o125; - output fabric_fpga_wdata_axi_s1_o126; - output fabric_fpga_wdata_axi_s1_o127; - output fabric_fpga_wdata_axi_s1_o128; - output fabric_fpga_wdata_axi_s1_o13; - output fabric_fpga_wdata_axi_s1_o14; - output fabric_fpga_wdata_axi_s1_o15; - output fabric_fpga_wdata_axi_s1_o16; - output fabric_fpga_wdata_axi_s1_o17; - output fabric_fpga_wdata_axi_s1_o18; - output fabric_fpga_wdata_axi_s1_o19; - output fabric_fpga_wdata_axi_s1_o2; - output fabric_fpga_wdata_axi_s1_o20; - output fabric_fpga_wdata_axi_s1_o21; - output fabric_fpga_wdata_axi_s1_o22; - output fabric_fpga_wdata_axi_s1_o23; - output fabric_fpga_wdata_axi_s1_o24; - output fabric_fpga_wdata_axi_s1_o25; - output fabric_fpga_wdata_axi_s1_o26; - output fabric_fpga_wdata_axi_s1_o27; - output fabric_fpga_wdata_axi_s1_o28; - output fabric_fpga_wdata_axi_s1_o29; - output fabric_fpga_wdata_axi_s1_o3; - output fabric_fpga_wdata_axi_s1_o30; - output fabric_fpga_wdata_axi_s1_o31; - output fabric_fpga_wdata_axi_s1_o32; - output fabric_fpga_wdata_axi_s1_o33; - output fabric_fpga_wdata_axi_s1_o34; - output fabric_fpga_wdata_axi_s1_o35; - output fabric_fpga_wdata_axi_s1_o36; - output fabric_fpga_wdata_axi_s1_o37; - output fabric_fpga_wdata_axi_s1_o38; - output fabric_fpga_wdata_axi_s1_o39; - output fabric_fpga_wdata_axi_s1_o4; - output fabric_fpga_wdata_axi_s1_o40; - output fabric_fpga_wdata_axi_s1_o41; - output fabric_fpga_wdata_axi_s1_o42; - output fabric_fpga_wdata_axi_s1_o43; - output fabric_fpga_wdata_axi_s1_o44; - output fabric_fpga_wdata_axi_s1_o45; - output fabric_fpga_wdata_axi_s1_o46; - output fabric_fpga_wdata_axi_s1_o47; - output fabric_fpga_wdata_axi_s1_o48; - output fabric_fpga_wdata_axi_s1_o49; - output fabric_fpga_wdata_axi_s1_o5; - output fabric_fpga_wdata_axi_s1_o50; - output fabric_fpga_wdata_axi_s1_o51; - output fabric_fpga_wdata_axi_s1_o52; - output fabric_fpga_wdata_axi_s1_o53; - output fabric_fpga_wdata_axi_s1_o54; - output fabric_fpga_wdata_axi_s1_o55; - output fabric_fpga_wdata_axi_s1_o56; - output fabric_fpga_wdata_axi_s1_o57; - output fabric_fpga_wdata_axi_s1_o58; - output fabric_fpga_wdata_axi_s1_o59; - output fabric_fpga_wdata_axi_s1_o6; - output fabric_fpga_wdata_axi_s1_o60; - output fabric_fpga_wdata_axi_s1_o61; - output fabric_fpga_wdata_axi_s1_o62; - output fabric_fpga_wdata_axi_s1_o63; - output fabric_fpga_wdata_axi_s1_o64; - output fabric_fpga_wdata_axi_s1_o65; - output fabric_fpga_wdata_axi_s1_o66; - output fabric_fpga_wdata_axi_s1_o67; - output fabric_fpga_wdata_axi_s1_o68; - output fabric_fpga_wdata_axi_s1_o69; - output fabric_fpga_wdata_axi_s1_o7; - output fabric_fpga_wdata_axi_s1_o70; - output fabric_fpga_wdata_axi_s1_o71; - output fabric_fpga_wdata_axi_s1_o72; - output fabric_fpga_wdata_axi_s1_o73; - output fabric_fpga_wdata_axi_s1_o74; - output fabric_fpga_wdata_axi_s1_o75; - output fabric_fpga_wdata_axi_s1_o76; - output fabric_fpga_wdata_axi_s1_o77; - output fabric_fpga_wdata_axi_s1_o78; - output fabric_fpga_wdata_axi_s1_o79; - output fabric_fpga_wdata_axi_s1_o8; - output fabric_fpga_wdata_axi_s1_o80; - output fabric_fpga_wdata_axi_s1_o81; - output fabric_fpga_wdata_axi_s1_o82; - output fabric_fpga_wdata_axi_s1_o83; - output fabric_fpga_wdata_axi_s1_o84; - output fabric_fpga_wdata_axi_s1_o85; - output fabric_fpga_wdata_axi_s1_o86; - output fabric_fpga_wdata_axi_s1_o87; - output fabric_fpga_wdata_axi_s1_o88; - output fabric_fpga_wdata_axi_s1_o89; - output fabric_fpga_wdata_axi_s1_o9; - output fabric_fpga_wdata_axi_s1_o90; - output fabric_fpga_wdata_axi_s1_o91; - output fabric_fpga_wdata_axi_s1_o92; - output fabric_fpga_wdata_axi_s1_o93; - output fabric_fpga_wdata_axi_s1_o94; - output fabric_fpga_wdata_axi_s1_o95; - output fabric_fpga_wdata_axi_s1_o96; - output fabric_fpga_wdata_axi_s1_o97; - output fabric_fpga_wdata_axi_s1_o98; - output fabric_fpga_wdata_axi_s1_o99; - output fabric_fpga_wdata_axi_s2_o1; - output fabric_fpga_wdata_axi_s2_o10; - output fabric_fpga_wdata_axi_s2_o100; - output fabric_fpga_wdata_axi_s2_o101; - output fabric_fpga_wdata_axi_s2_o102; - output fabric_fpga_wdata_axi_s2_o103; - output fabric_fpga_wdata_axi_s2_o104; - output fabric_fpga_wdata_axi_s2_o105; - output fabric_fpga_wdata_axi_s2_o106; - output fabric_fpga_wdata_axi_s2_o107; - output fabric_fpga_wdata_axi_s2_o108; - output fabric_fpga_wdata_axi_s2_o109; - output fabric_fpga_wdata_axi_s2_o11; - output fabric_fpga_wdata_axi_s2_o110; - output fabric_fpga_wdata_axi_s2_o111; - output fabric_fpga_wdata_axi_s2_o112; - output fabric_fpga_wdata_axi_s2_o113; - output fabric_fpga_wdata_axi_s2_o114; - output fabric_fpga_wdata_axi_s2_o115; - output fabric_fpga_wdata_axi_s2_o116; - output fabric_fpga_wdata_axi_s2_o117; - output fabric_fpga_wdata_axi_s2_o118; - output fabric_fpga_wdata_axi_s2_o119; - output fabric_fpga_wdata_axi_s2_o12; - output fabric_fpga_wdata_axi_s2_o120; - output fabric_fpga_wdata_axi_s2_o121; - output fabric_fpga_wdata_axi_s2_o122; - output fabric_fpga_wdata_axi_s2_o123; - output fabric_fpga_wdata_axi_s2_o124; - output fabric_fpga_wdata_axi_s2_o125; - output fabric_fpga_wdata_axi_s2_o126; - output fabric_fpga_wdata_axi_s2_o127; - output fabric_fpga_wdata_axi_s2_o128; - output fabric_fpga_wdata_axi_s2_o13; - output fabric_fpga_wdata_axi_s2_o14; - output fabric_fpga_wdata_axi_s2_o15; - output fabric_fpga_wdata_axi_s2_o16; - output fabric_fpga_wdata_axi_s2_o17; - output fabric_fpga_wdata_axi_s2_o18; - output fabric_fpga_wdata_axi_s2_o19; - output fabric_fpga_wdata_axi_s2_o2; - output fabric_fpga_wdata_axi_s2_o20; - output fabric_fpga_wdata_axi_s2_o21; - output fabric_fpga_wdata_axi_s2_o22; - output fabric_fpga_wdata_axi_s2_o23; - output fabric_fpga_wdata_axi_s2_o24; - output fabric_fpga_wdata_axi_s2_o25; - output fabric_fpga_wdata_axi_s2_o26; - output fabric_fpga_wdata_axi_s2_o27; - output fabric_fpga_wdata_axi_s2_o28; - output fabric_fpga_wdata_axi_s2_o29; - output fabric_fpga_wdata_axi_s2_o3; - output fabric_fpga_wdata_axi_s2_o30; - output fabric_fpga_wdata_axi_s2_o31; - output fabric_fpga_wdata_axi_s2_o32; - output fabric_fpga_wdata_axi_s2_o33; - output fabric_fpga_wdata_axi_s2_o34; - output fabric_fpga_wdata_axi_s2_o35; - output fabric_fpga_wdata_axi_s2_o36; - output fabric_fpga_wdata_axi_s2_o37; - output fabric_fpga_wdata_axi_s2_o38; - output fabric_fpga_wdata_axi_s2_o39; - output fabric_fpga_wdata_axi_s2_o4; - output fabric_fpga_wdata_axi_s2_o40; - output fabric_fpga_wdata_axi_s2_o41; - output fabric_fpga_wdata_axi_s2_o42; - output fabric_fpga_wdata_axi_s2_o43; - output fabric_fpga_wdata_axi_s2_o44; - output fabric_fpga_wdata_axi_s2_o45; - output fabric_fpga_wdata_axi_s2_o46; - output fabric_fpga_wdata_axi_s2_o47; - output fabric_fpga_wdata_axi_s2_o48; - output fabric_fpga_wdata_axi_s2_o49; - output fabric_fpga_wdata_axi_s2_o5; - output fabric_fpga_wdata_axi_s2_o50; - output fabric_fpga_wdata_axi_s2_o51; - output fabric_fpga_wdata_axi_s2_o52; - output fabric_fpga_wdata_axi_s2_o53; - output fabric_fpga_wdata_axi_s2_o54; - output fabric_fpga_wdata_axi_s2_o55; - output fabric_fpga_wdata_axi_s2_o56; - output fabric_fpga_wdata_axi_s2_o57; - output fabric_fpga_wdata_axi_s2_o58; - output fabric_fpga_wdata_axi_s2_o59; - output fabric_fpga_wdata_axi_s2_o6; - output fabric_fpga_wdata_axi_s2_o60; - output fabric_fpga_wdata_axi_s2_o61; - output fabric_fpga_wdata_axi_s2_o62; - output fabric_fpga_wdata_axi_s2_o63; - output fabric_fpga_wdata_axi_s2_o64; - output fabric_fpga_wdata_axi_s2_o65; - output fabric_fpga_wdata_axi_s2_o66; - output fabric_fpga_wdata_axi_s2_o67; - output fabric_fpga_wdata_axi_s2_o68; - output fabric_fpga_wdata_axi_s2_o69; - output fabric_fpga_wdata_axi_s2_o7; - output fabric_fpga_wdata_axi_s2_o70; - output fabric_fpga_wdata_axi_s2_o71; - output fabric_fpga_wdata_axi_s2_o72; - output fabric_fpga_wdata_axi_s2_o73; - output fabric_fpga_wdata_axi_s2_o74; - output fabric_fpga_wdata_axi_s2_o75; - output fabric_fpga_wdata_axi_s2_o76; - output fabric_fpga_wdata_axi_s2_o77; - output fabric_fpga_wdata_axi_s2_o78; - output fabric_fpga_wdata_axi_s2_o79; - output fabric_fpga_wdata_axi_s2_o8; - output fabric_fpga_wdata_axi_s2_o80; - output fabric_fpga_wdata_axi_s2_o81; - output fabric_fpga_wdata_axi_s2_o82; - output fabric_fpga_wdata_axi_s2_o83; - output fabric_fpga_wdata_axi_s2_o84; - output fabric_fpga_wdata_axi_s2_o85; - output fabric_fpga_wdata_axi_s2_o86; - output fabric_fpga_wdata_axi_s2_o87; - output fabric_fpga_wdata_axi_s2_o88; - output fabric_fpga_wdata_axi_s2_o89; - output fabric_fpga_wdata_axi_s2_o9; - output fabric_fpga_wdata_axi_s2_o90; - output fabric_fpga_wdata_axi_s2_o91; - output fabric_fpga_wdata_axi_s2_o92; - output fabric_fpga_wdata_axi_s2_o93; - output fabric_fpga_wdata_axi_s2_o94; - output fabric_fpga_wdata_axi_s2_o95; - output fabric_fpga_wdata_axi_s2_o96; - output fabric_fpga_wdata_axi_s2_o97; - output fabric_fpga_wdata_axi_s2_o98; - output fabric_fpga_wdata_axi_s2_o99; - input fabric_fpga_wlast_axi_m1_i; - input fabric_fpga_wlast_axi_m2_i; - output fabric_fpga_wlast_axi_s1_o; - output fabric_fpga_wlast_axi_s2_o; - output fabric_fpga_wready_axi_m1_o; - output fabric_fpga_wready_axi_m2_o; - input fabric_fpga_wready_axi_s1_i; - input fabric_fpga_wready_axi_s2_i; - input fabric_fpga_wstrb_axi_m1_i1; - input fabric_fpga_wstrb_axi_m1_i10; - input fabric_fpga_wstrb_axi_m1_i11; - input fabric_fpga_wstrb_axi_m1_i12; - input fabric_fpga_wstrb_axi_m1_i13; - input fabric_fpga_wstrb_axi_m1_i14; - input fabric_fpga_wstrb_axi_m1_i15; - input fabric_fpga_wstrb_axi_m1_i16; - input fabric_fpga_wstrb_axi_m1_i2; - input fabric_fpga_wstrb_axi_m1_i3; - input fabric_fpga_wstrb_axi_m1_i4; - input fabric_fpga_wstrb_axi_m1_i5; - input fabric_fpga_wstrb_axi_m1_i6; - input fabric_fpga_wstrb_axi_m1_i7; - input fabric_fpga_wstrb_axi_m1_i8; - input fabric_fpga_wstrb_axi_m1_i9; - input fabric_fpga_wstrb_axi_m2_i1; - input fabric_fpga_wstrb_axi_m2_i10; - input fabric_fpga_wstrb_axi_m2_i11; - input fabric_fpga_wstrb_axi_m2_i12; - input fabric_fpga_wstrb_axi_m2_i13; - input fabric_fpga_wstrb_axi_m2_i14; - input fabric_fpga_wstrb_axi_m2_i15; - input fabric_fpga_wstrb_axi_m2_i16; - input fabric_fpga_wstrb_axi_m2_i2; - input fabric_fpga_wstrb_axi_m2_i3; - input fabric_fpga_wstrb_axi_m2_i4; - input fabric_fpga_wstrb_axi_m2_i5; - input fabric_fpga_wstrb_axi_m2_i6; - input fabric_fpga_wstrb_axi_m2_i7; - input fabric_fpga_wstrb_axi_m2_i8; - input fabric_fpga_wstrb_axi_m2_i9; - output fabric_fpga_wstrb_axi_s1_o1; - output fabric_fpga_wstrb_axi_s1_o10; - output fabric_fpga_wstrb_axi_s1_o11; - output fabric_fpga_wstrb_axi_s1_o12; - output fabric_fpga_wstrb_axi_s1_o13; - output fabric_fpga_wstrb_axi_s1_o14; - output fabric_fpga_wstrb_axi_s1_o15; - output fabric_fpga_wstrb_axi_s1_o16; - output fabric_fpga_wstrb_axi_s1_o2; - output fabric_fpga_wstrb_axi_s1_o3; - output fabric_fpga_wstrb_axi_s1_o4; - output fabric_fpga_wstrb_axi_s1_o5; - output fabric_fpga_wstrb_axi_s1_o6; - output fabric_fpga_wstrb_axi_s1_o7; - output fabric_fpga_wstrb_axi_s1_o8; - output fabric_fpga_wstrb_axi_s1_o9; - output fabric_fpga_wstrb_axi_s2_o1; - output fabric_fpga_wstrb_axi_s2_o10; - output fabric_fpga_wstrb_axi_s2_o11; - output fabric_fpga_wstrb_axi_s2_o12; - output fabric_fpga_wstrb_axi_s2_o13; - output fabric_fpga_wstrb_axi_s2_o14; - output fabric_fpga_wstrb_axi_s2_o15; - output fabric_fpga_wstrb_axi_s2_o16; - output fabric_fpga_wstrb_axi_s2_o2; - output fabric_fpga_wstrb_axi_s2_o3; - output fabric_fpga_wstrb_axi_s2_o4; - output fabric_fpga_wstrb_axi_s2_o5; - output fabric_fpga_wstrb_axi_s2_o6; - output fabric_fpga_wstrb_axi_s2_o7; - output fabric_fpga_wstrb_axi_s2_o8; - output fabric_fpga_wstrb_axi_s2_o9; - input fabric_fpga_wvalid_axi_m1_i; - input fabric_fpga_wvalid_axi_m2_i; - output fabric_fpga_wvalid_axi_s1_o; - output fabric_fpga_wvalid_axi_s2_o; - output fabric_llpp0_araddr_s_o1; - output fabric_llpp0_araddr_s_o10; - output fabric_llpp0_araddr_s_o11; - output fabric_llpp0_araddr_s_o12; - output fabric_llpp0_araddr_s_o13; - output fabric_llpp0_araddr_s_o14; - output fabric_llpp0_araddr_s_o15; - output fabric_llpp0_araddr_s_o16; - output fabric_llpp0_araddr_s_o17; - output fabric_llpp0_araddr_s_o18; - output fabric_llpp0_araddr_s_o19; - output fabric_llpp0_araddr_s_o2; - output fabric_llpp0_araddr_s_o20; - output fabric_llpp0_araddr_s_o21; - output fabric_llpp0_araddr_s_o22; - output fabric_llpp0_araddr_s_o23; - output fabric_llpp0_araddr_s_o24; - output fabric_llpp0_araddr_s_o25; - output fabric_llpp0_araddr_s_o26; - output fabric_llpp0_araddr_s_o27; - output fabric_llpp0_araddr_s_o28; - output fabric_llpp0_araddr_s_o29; - output fabric_llpp0_araddr_s_o3; - output fabric_llpp0_araddr_s_o30; - output fabric_llpp0_araddr_s_o31; - output fabric_llpp0_araddr_s_o32; - output fabric_llpp0_araddr_s_o4; - output fabric_llpp0_araddr_s_o5; - output fabric_llpp0_araddr_s_o6; - output fabric_llpp0_araddr_s_o7; - output fabric_llpp0_araddr_s_o8; - output fabric_llpp0_araddr_s_o9; - output fabric_llpp0_arburst_s_o1; - output fabric_llpp0_arburst_s_o2; - output fabric_llpp0_arcache_s_o1; - output fabric_llpp0_arcache_s_o2; - output fabric_llpp0_arcache_s_o3; - output fabric_llpp0_arcache_s_o4; - output fabric_llpp0_arid_s_o1; - output fabric_llpp0_arid_s_o10; - output fabric_llpp0_arid_s_o11; - output fabric_llpp0_arid_s_o12; - output fabric_llpp0_arid_s_o2; - output fabric_llpp0_arid_s_o3; - output fabric_llpp0_arid_s_o4; - output fabric_llpp0_arid_s_o5; - output fabric_llpp0_arid_s_o6; - output fabric_llpp0_arid_s_o7; - output fabric_llpp0_arid_s_o8; - output fabric_llpp0_arid_s_o9; - output fabric_llpp0_arlen_s_o1; - output fabric_llpp0_arlen_s_o2; - output fabric_llpp0_arlen_s_o3; - output fabric_llpp0_arlen_s_o4; - output fabric_llpp0_arlen_s_o5; - output fabric_llpp0_arlen_s_o6; - output fabric_llpp0_arlen_s_o7; - output fabric_llpp0_arlen_s_o8; - output fabric_llpp0_arlock_s_o; - output fabric_llpp0_arprot_s_o1; - output fabric_llpp0_arprot_s_o2; - output fabric_llpp0_arprot_s_o3; - output fabric_llpp0_arqos_s_o1; - output fabric_llpp0_arqos_s_o2; - output fabric_llpp0_arqos_s_o3; - output fabric_llpp0_arqos_s_o4; - input fabric_llpp0_arready_s_i; - output fabric_llpp0_arsize_s_o1; - output fabric_llpp0_arsize_s_o2; - output fabric_llpp0_arsize_s_o3; - output fabric_llpp0_arvalid_s_o; - output fabric_llpp0_awaddr_s_o1; - output fabric_llpp0_awaddr_s_o10; - output fabric_llpp0_awaddr_s_o11; - output fabric_llpp0_awaddr_s_o12; - output fabric_llpp0_awaddr_s_o13; - output fabric_llpp0_awaddr_s_o14; - output fabric_llpp0_awaddr_s_o15; - output fabric_llpp0_awaddr_s_o16; - output fabric_llpp0_awaddr_s_o17; - output fabric_llpp0_awaddr_s_o18; - output fabric_llpp0_awaddr_s_o19; - output fabric_llpp0_awaddr_s_o2; - output fabric_llpp0_awaddr_s_o20; - output fabric_llpp0_awaddr_s_o21; - output fabric_llpp0_awaddr_s_o22; - output fabric_llpp0_awaddr_s_o23; - output fabric_llpp0_awaddr_s_o24; - output fabric_llpp0_awaddr_s_o25; - output fabric_llpp0_awaddr_s_o26; - output fabric_llpp0_awaddr_s_o27; - output fabric_llpp0_awaddr_s_o28; - output fabric_llpp0_awaddr_s_o29; - output fabric_llpp0_awaddr_s_o3; - output fabric_llpp0_awaddr_s_o30; - output fabric_llpp0_awaddr_s_o31; - output fabric_llpp0_awaddr_s_o32; - output fabric_llpp0_awaddr_s_o4; - output fabric_llpp0_awaddr_s_o5; - output fabric_llpp0_awaddr_s_o6; - output fabric_llpp0_awaddr_s_o7; - output fabric_llpp0_awaddr_s_o8; - output fabric_llpp0_awaddr_s_o9; - output fabric_llpp0_awburst_s_o1; - output fabric_llpp0_awburst_s_o2; - output fabric_llpp0_awcache_s_o1; - output fabric_llpp0_awcache_s_o2; - output fabric_llpp0_awcache_s_o3; - output fabric_llpp0_awcache_s_o4; - output fabric_llpp0_awid_s_o1; - output fabric_llpp0_awid_s_o10; - output fabric_llpp0_awid_s_o11; - output fabric_llpp0_awid_s_o12; - output fabric_llpp0_awid_s_o2; - output fabric_llpp0_awid_s_o3; - output fabric_llpp0_awid_s_o4; - output fabric_llpp0_awid_s_o5; - output fabric_llpp0_awid_s_o6; - output fabric_llpp0_awid_s_o7; - output fabric_llpp0_awid_s_o8; - output fabric_llpp0_awid_s_o9; - output fabric_llpp0_awlen_s_o1; - output fabric_llpp0_awlen_s_o2; - output fabric_llpp0_awlen_s_o3; - output fabric_llpp0_awlen_s_o4; - output fabric_llpp0_awlen_s_o5; - output fabric_llpp0_awlen_s_o6; - output fabric_llpp0_awlen_s_o7; - output fabric_llpp0_awlen_s_o8; - output fabric_llpp0_awlock_s_o; - output fabric_llpp0_awprot_s_o1; - output fabric_llpp0_awprot_s_o2; - output fabric_llpp0_awprot_s_o3; - output fabric_llpp0_awqos_s_o1; - output fabric_llpp0_awqos_s_o2; - output fabric_llpp0_awqos_s_o3; - output fabric_llpp0_awqos_s_o4; - input fabric_llpp0_awready_s_i; - output fabric_llpp0_awsize_s_o1; - output fabric_llpp0_awsize_s_o2; - output fabric_llpp0_awsize_s_o3; - output fabric_llpp0_awvalid_s_o; - input fabric_llpp0_bid_s_i1; - input fabric_llpp0_bid_s_i10; - input fabric_llpp0_bid_s_i11; - input fabric_llpp0_bid_s_i12; - input fabric_llpp0_bid_s_i2; - input fabric_llpp0_bid_s_i3; - input fabric_llpp0_bid_s_i4; - input fabric_llpp0_bid_s_i5; - input fabric_llpp0_bid_s_i6; - input fabric_llpp0_bid_s_i7; - input fabric_llpp0_bid_s_i8; - input fabric_llpp0_bid_s_i9; - output fabric_llpp0_bready_s_o; - input fabric_llpp0_bresp_s_i1; - input fabric_llpp0_bresp_s_i2; - input fabric_llpp0_bvalid_s_i; - input fabric_llpp0_rdata_s_i1; - input fabric_llpp0_rdata_s_i10; - input fabric_llpp0_rdata_s_i11; - input fabric_llpp0_rdata_s_i12; - input fabric_llpp0_rdata_s_i13; - input fabric_llpp0_rdata_s_i14; - input fabric_llpp0_rdata_s_i15; - input fabric_llpp0_rdata_s_i16; - input fabric_llpp0_rdata_s_i17; - input fabric_llpp0_rdata_s_i18; - input fabric_llpp0_rdata_s_i19; - input fabric_llpp0_rdata_s_i2; - input fabric_llpp0_rdata_s_i20; - input fabric_llpp0_rdata_s_i21; - input fabric_llpp0_rdata_s_i22; - input fabric_llpp0_rdata_s_i23; - input fabric_llpp0_rdata_s_i24; - input fabric_llpp0_rdata_s_i25; - input fabric_llpp0_rdata_s_i26; - input fabric_llpp0_rdata_s_i27; - input fabric_llpp0_rdata_s_i28; - input fabric_llpp0_rdata_s_i29; - input fabric_llpp0_rdata_s_i3; - input fabric_llpp0_rdata_s_i30; - input fabric_llpp0_rdata_s_i31; - input fabric_llpp0_rdata_s_i32; - input fabric_llpp0_rdata_s_i4; - input fabric_llpp0_rdata_s_i5; - input fabric_llpp0_rdata_s_i6; - input fabric_llpp0_rdata_s_i7; - input fabric_llpp0_rdata_s_i8; - input fabric_llpp0_rdata_s_i9; - input fabric_llpp0_rid_s_i1; - input fabric_llpp0_rid_s_i10; - input fabric_llpp0_rid_s_i11; - input fabric_llpp0_rid_s_i12; - input fabric_llpp0_rid_s_i2; - input fabric_llpp0_rid_s_i3; - input fabric_llpp0_rid_s_i4; - input fabric_llpp0_rid_s_i5; - input fabric_llpp0_rid_s_i6; - input fabric_llpp0_rid_s_i7; - input fabric_llpp0_rid_s_i8; - input fabric_llpp0_rid_s_i9; - input fabric_llpp0_rlast_s_i; - output fabric_llpp0_rready_s_o; - input fabric_llpp0_rresp_s_i1; - input fabric_llpp0_rresp_s_i2; - input fabric_llpp0_rvalid_s_i; - output fabric_llpp0_wdata_s_o1; - output fabric_llpp0_wdata_s_o10; - output fabric_llpp0_wdata_s_o11; - output fabric_llpp0_wdata_s_o12; - output fabric_llpp0_wdata_s_o13; - output fabric_llpp0_wdata_s_o14; - output fabric_llpp0_wdata_s_o15; - output fabric_llpp0_wdata_s_o16; - output fabric_llpp0_wdata_s_o17; - output fabric_llpp0_wdata_s_o18; - output fabric_llpp0_wdata_s_o19; - output fabric_llpp0_wdata_s_o2; - output fabric_llpp0_wdata_s_o20; - output fabric_llpp0_wdata_s_o21; - output fabric_llpp0_wdata_s_o22; - output fabric_llpp0_wdata_s_o23; - output fabric_llpp0_wdata_s_o24; - output fabric_llpp0_wdata_s_o25; - output fabric_llpp0_wdata_s_o26; - output fabric_llpp0_wdata_s_o27; - output fabric_llpp0_wdata_s_o28; - output fabric_llpp0_wdata_s_o29; - output fabric_llpp0_wdata_s_o3; - output fabric_llpp0_wdata_s_o30; - output fabric_llpp0_wdata_s_o31; - output fabric_llpp0_wdata_s_o32; - output fabric_llpp0_wdata_s_o4; - output fabric_llpp0_wdata_s_o5; - output fabric_llpp0_wdata_s_o6; - output fabric_llpp0_wdata_s_o7; - output fabric_llpp0_wdata_s_o8; - output fabric_llpp0_wdata_s_o9; - output fabric_llpp0_wlast_s_o; - input fabric_llpp0_wready_s_i; - output fabric_llpp0_wstrb_s_o1; - output fabric_llpp0_wstrb_s_o2; - output fabric_llpp0_wstrb_s_o3; - output fabric_llpp0_wstrb_s_o4; - output fabric_llpp0_wvalid_s_o; - output fabric_llpp1_araddr_s_o1; - output fabric_llpp1_araddr_s_o10; - output fabric_llpp1_araddr_s_o11; - output fabric_llpp1_araddr_s_o12; - output fabric_llpp1_araddr_s_o13; - output fabric_llpp1_araddr_s_o14; - output fabric_llpp1_araddr_s_o15; - output fabric_llpp1_araddr_s_o16; - output fabric_llpp1_araddr_s_o17; - output fabric_llpp1_araddr_s_o18; - output fabric_llpp1_araddr_s_o19; - output fabric_llpp1_araddr_s_o2; - output fabric_llpp1_araddr_s_o20; - output fabric_llpp1_araddr_s_o21; - output fabric_llpp1_araddr_s_o22; - output fabric_llpp1_araddr_s_o23; - output fabric_llpp1_araddr_s_o24; - output fabric_llpp1_araddr_s_o25; - output fabric_llpp1_araddr_s_o26; - output fabric_llpp1_araddr_s_o27; - output fabric_llpp1_araddr_s_o28; - output fabric_llpp1_araddr_s_o29; - output fabric_llpp1_araddr_s_o3; - output fabric_llpp1_araddr_s_o30; - output fabric_llpp1_araddr_s_o31; - output fabric_llpp1_araddr_s_o32; - output fabric_llpp1_araddr_s_o4; - output fabric_llpp1_araddr_s_o5; - output fabric_llpp1_araddr_s_o6; - output fabric_llpp1_araddr_s_o7; - output fabric_llpp1_araddr_s_o8; - output fabric_llpp1_araddr_s_o9; - output fabric_llpp1_arburst_s_o1; - output fabric_llpp1_arburst_s_o2; - output fabric_llpp1_arcache_s_o1; - output fabric_llpp1_arcache_s_o2; - output fabric_llpp1_arcache_s_o3; - output fabric_llpp1_arcache_s_o4; - output fabric_llpp1_arid_s_o1; - output fabric_llpp1_arid_s_o10; - output fabric_llpp1_arid_s_o11; - output fabric_llpp1_arid_s_o12; - output fabric_llpp1_arid_s_o2; - output fabric_llpp1_arid_s_o3; - output fabric_llpp1_arid_s_o4; - output fabric_llpp1_arid_s_o5; - output fabric_llpp1_arid_s_o6; - output fabric_llpp1_arid_s_o7; - output fabric_llpp1_arid_s_o8; - output fabric_llpp1_arid_s_o9; - output fabric_llpp1_arlen_s_o1; - output fabric_llpp1_arlen_s_o2; - output fabric_llpp1_arlen_s_o3; - output fabric_llpp1_arlen_s_o4; - output fabric_llpp1_arlen_s_o5; - output fabric_llpp1_arlen_s_o6; - output fabric_llpp1_arlen_s_o7; - output fabric_llpp1_arlen_s_o8; - output fabric_llpp1_arlock_s_o; - output fabric_llpp1_arprot_s_o1; - output fabric_llpp1_arprot_s_o2; - output fabric_llpp1_arprot_s_o3; - output fabric_llpp1_arqos_s1_o1; - output fabric_llpp1_arqos_s1_o2; - output fabric_llpp1_arqos_s1_o3; - output fabric_llpp1_arqos_s1_o4; - input fabric_llpp1_arready_s_i; - output fabric_llpp1_arsize_s_o1; - output fabric_llpp1_arsize_s_o2; - output fabric_llpp1_arsize_s_o3; - output fabric_llpp1_arvalid_s_o; - output fabric_llpp1_awaddr_s_o1; - output fabric_llpp1_awaddr_s_o10; - output fabric_llpp1_awaddr_s_o11; - output fabric_llpp1_awaddr_s_o12; - output fabric_llpp1_awaddr_s_o13; - output fabric_llpp1_awaddr_s_o14; - output fabric_llpp1_awaddr_s_o15; - output fabric_llpp1_awaddr_s_o16; - output fabric_llpp1_awaddr_s_o17; - output fabric_llpp1_awaddr_s_o18; - output fabric_llpp1_awaddr_s_o19; - output fabric_llpp1_awaddr_s_o2; - output fabric_llpp1_awaddr_s_o20; - output fabric_llpp1_awaddr_s_o21; - output fabric_llpp1_awaddr_s_o22; - output fabric_llpp1_awaddr_s_o23; - output fabric_llpp1_awaddr_s_o24; - output fabric_llpp1_awaddr_s_o25; - output fabric_llpp1_awaddr_s_o26; - output fabric_llpp1_awaddr_s_o27; - output fabric_llpp1_awaddr_s_o28; - output fabric_llpp1_awaddr_s_o29; - output fabric_llpp1_awaddr_s_o3; - output fabric_llpp1_awaddr_s_o30; - output fabric_llpp1_awaddr_s_o31; - output fabric_llpp1_awaddr_s_o32; - output fabric_llpp1_awaddr_s_o4; - output fabric_llpp1_awaddr_s_o5; - output fabric_llpp1_awaddr_s_o6; - output fabric_llpp1_awaddr_s_o7; - output fabric_llpp1_awaddr_s_o8; - output fabric_llpp1_awaddr_s_o9; - output fabric_llpp1_awburst_s_o1; - output fabric_llpp1_awburst_s_o2; - output fabric_llpp1_awcache_s_o1; - output fabric_llpp1_awcache_s_o2; - output fabric_llpp1_awcache_s_o3; - output fabric_llpp1_awcache_s_o4; - output fabric_llpp1_awid_s_o1; - output fabric_llpp1_awid_s_o10; - output fabric_llpp1_awid_s_o11; - output fabric_llpp1_awid_s_o12; - output fabric_llpp1_awid_s_o2; - output fabric_llpp1_awid_s_o3; - output fabric_llpp1_awid_s_o4; - output fabric_llpp1_awid_s_o5; - output fabric_llpp1_awid_s_o6; - output fabric_llpp1_awid_s_o7; - output fabric_llpp1_awid_s_o8; - output fabric_llpp1_awid_s_o9; - output fabric_llpp1_awlen_s_o1; - output fabric_llpp1_awlen_s_o2; - output fabric_llpp1_awlen_s_o3; - output fabric_llpp1_awlen_s_o4; - output fabric_llpp1_awlen_s_o5; - output fabric_llpp1_awlen_s_o6; - output fabric_llpp1_awlen_s_o7; - output fabric_llpp1_awlen_s_o8; - output fabric_llpp1_awlock_s_o; - output fabric_llpp1_awprot_s_o1; - output fabric_llpp1_awprot_s_o2; - output fabric_llpp1_awprot_s_o3; - output fabric_llpp1_awqos_s_o1; - output fabric_llpp1_awqos_s_o2; - output fabric_llpp1_awqos_s_o3; - output fabric_llpp1_awqos_s_o4; - input fabric_llpp1_awready_s_i; - output fabric_llpp1_awsize_s_o1; - output fabric_llpp1_awsize_s_o2; - output fabric_llpp1_awsize_s_o3; - output fabric_llpp1_awvalid_s_o; - input fabric_llpp1_bid_s_i1; - input fabric_llpp1_bid_s_i10; - input fabric_llpp1_bid_s_i11; - input fabric_llpp1_bid_s_i12; - input fabric_llpp1_bid_s_i2; - input fabric_llpp1_bid_s_i3; - input fabric_llpp1_bid_s_i4; - input fabric_llpp1_bid_s_i5; - input fabric_llpp1_bid_s_i6; - input fabric_llpp1_bid_s_i7; - input fabric_llpp1_bid_s_i8; - input fabric_llpp1_bid_s_i9; - output fabric_llpp1_bready_s_o; - input fabric_llpp1_bresp_s_i1; - input fabric_llpp1_bresp_s_i2; - input fabric_llpp1_bvalid_s_i; - input fabric_llpp1_rdata_s_i1; - input fabric_llpp1_rdata_s_i10; - input fabric_llpp1_rdata_s_i11; - input fabric_llpp1_rdata_s_i12; - input fabric_llpp1_rdata_s_i13; - input fabric_llpp1_rdata_s_i14; - input fabric_llpp1_rdata_s_i15; - input fabric_llpp1_rdata_s_i16; - input fabric_llpp1_rdata_s_i17; - input fabric_llpp1_rdata_s_i18; - input fabric_llpp1_rdata_s_i19; - input fabric_llpp1_rdata_s_i2; - input fabric_llpp1_rdata_s_i20; - input fabric_llpp1_rdata_s_i21; - input fabric_llpp1_rdata_s_i22; - input fabric_llpp1_rdata_s_i23; - input fabric_llpp1_rdata_s_i24; - input fabric_llpp1_rdata_s_i25; - input fabric_llpp1_rdata_s_i26; - input fabric_llpp1_rdata_s_i27; - input fabric_llpp1_rdata_s_i28; - input fabric_llpp1_rdata_s_i29; - input fabric_llpp1_rdata_s_i3; - input fabric_llpp1_rdata_s_i30; - input fabric_llpp1_rdata_s_i31; - input fabric_llpp1_rdata_s_i32; - input fabric_llpp1_rdata_s_i4; - input fabric_llpp1_rdata_s_i5; - input fabric_llpp1_rdata_s_i6; - input fabric_llpp1_rdata_s_i7; - input fabric_llpp1_rdata_s_i8; - input fabric_llpp1_rdata_s_i9; - input fabric_llpp1_rid_s_i1; - input fabric_llpp1_rid_s_i10; - input fabric_llpp1_rid_s_i11; - input fabric_llpp1_rid_s_i12; - input fabric_llpp1_rid_s_i2; - input fabric_llpp1_rid_s_i3; - input fabric_llpp1_rid_s_i4; - input fabric_llpp1_rid_s_i5; - input fabric_llpp1_rid_s_i6; - input fabric_llpp1_rid_s_i7; - input fabric_llpp1_rid_s_i8; - input fabric_llpp1_rid_s_i9; - input fabric_llpp1_rlast_s_i; - output fabric_llpp1_rready_s_o; - input fabric_llpp1_rresp_s_i1; - input fabric_llpp1_rresp_s_i2; - input fabric_llpp1_rvalid_s_i; - output fabric_llpp1_wdata_s_o1; - output fabric_llpp1_wdata_s_o10; - output fabric_llpp1_wdata_s_o11; - output fabric_llpp1_wdata_s_o12; - output fabric_llpp1_wdata_s_o13; - output fabric_llpp1_wdata_s_o14; - output fabric_llpp1_wdata_s_o15; - output fabric_llpp1_wdata_s_o16; - output fabric_llpp1_wdata_s_o17; - output fabric_llpp1_wdata_s_o18; - output fabric_llpp1_wdata_s_o19; - output fabric_llpp1_wdata_s_o2; - output fabric_llpp1_wdata_s_o20; - output fabric_llpp1_wdata_s_o21; - output fabric_llpp1_wdata_s_o22; - output fabric_llpp1_wdata_s_o23; - output fabric_llpp1_wdata_s_o24; - output fabric_llpp1_wdata_s_o25; - output fabric_llpp1_wdata_s_o26; - output fabric_llpp1_wdata_s_o27; - output fabric_llpp1_wdata_s_o28; - output fabric_llpp1_wdata_s_o29; - output fabric_llpp1_wdata_s_o3; - output fabric_llpp1_wdata_s_o30; - output fabric_llpp1_wdata_s_o31; - output fabric_llpp1_wdata_s_o32; - output fabric_llpp1_wdata_s_o4; - output fabric_llpp1_wdata_s_o5; - output fabric_llpp1_wdata_s_o6; - output fabric_llpp1_wdata_s_o7; - output fabric_llpp1_wdata_s_o8; - output fabric_llpp1_wdata_s_o9; - output fabric_llpp1_wlast_s_o; - input fabric_llpp1_wready_s_i; - output fabric_llpp1_wstrb_s_o1; - output fabric_llpp1_wstrb_s_o2; - output fabric_llpp1_wstrb_s_o3; - output fabric_llpp1_wstrb_s_o4; - output fabric_llpp1_wvalid_s_o; - output fabric_llpp2_araddr_s_o1; - output fabric_llpp2_araddr_s_o10; - output fabric_llpp2_araddr_s_o11; - output fabric_llpp2_araddr_s_o12; - output fabric_llpp2_araddr_s_o13; - output fabric_llpp2_araddr_s_o14; - output fabric_llpp2_araddr_s_o15; - output fabric_llpp2_araddr_s_o16; - output fabric_llpp2_araddr_s_o17; - output fabric_llpp2_araddr_s_o18; - output fabric_llpp2_araddr_s_o19; - output fabric_llpp2_araddr_s_o2; - output fabric_llpp2_araddr_s_o20; - output fabric_llpp2_araddr_s_o21; - output fabric_llpp2_araddr_s_o22; - output fabric_llpp2_araddr_s_o23; - output fabric_llpp2_araddr_s_o24; - output fabric_llpp2_araddr_s_o25; - output fabric_llpp2_araddr_s_o26; - output fabric_llpp2_araddr_s_o27; - output fabric_llpp2_araddr_s_o28; - output fabric_llpp2_araddr_s_o29; - output fabric_llpp2_araddr_s_o3; - output fabric_llpp2_araddr_s_o30; - output fabric_llpp2_araddr_s_o31; - output fabric_llpp2_araddr_s_o32; - output fabric_llpp2_araddr_s_o4; - output fabric_llpp2_araddr_s_o5; - output fabric_llpp2_araddr_s_o6; - output fabric_llpp2_araddr_s_o7; - output fabric_llpp2_araddr_s_o8; - output fabric_llpp2_araddr_s_o9; - output fabric_llpp2_arburst_s_o1; - output fabric_llpp2_arburst_s_o2; - output fabric_llpp2_arcache_s_o1; - output fabric_llpp2_arcache_s_o2; - output fabric_llpp2_arcache_s_o3; - output fabric_llpp2_arcache_s_o4; - output fabric_llpp2_arid_s_o1; - output fabric_llpp2_arid_s_o10; - output fabric_llpp2_arid_s_o11; - output fabric_llpp2_arid_s_o12; - output fabric_llpp2_arid_s_o2; - output fabric_llpp2_arid_s_o3; - output fabric_llpp2_arid_s_o4; - output fabric_llpp2_arid_s_o5; - output fabric_llpp2_arid_s_o6; - output fabric_llpp2_arid_s_o7; - output fabric_llpp2_arid_s_o8; - output fabric_llpp2_arid_s_o9; - output fabric_llpp2_arlen_s_o1; - output fabric_llpp2_arlen_s_o2; - output fabric_llpp2_arlen_s_o3; - output fabric_llpp2_arlen_s_o4; - output fabric_llpp2_arlen_s_o5; - output fabric_llpp2_arlen_s_o6; - output fabric_llpp2_arlen_s_o7; - output fabric_llpp2_arlen_s_o8; - output fabric_llpp2_arlock_s_o; - output fabric_llpp2_arprot_s_o1; - output fabric_llpp2_arprot_s_o2; - output fabric_llpp2_arprot_s_o3; - output fabric_llpp2_arqos_s_o1; - output fabric_llpp2_arqos_s_o2; - output fabric_llpp2_arqos_s_o3; - output fabric_llpp2_arqos_s_o4; - input fabric_llpp2_arready_s_i; - output fabric_llpp2_arsize_s_o1; - output fabric_llpp2_arsize_s_o2; - output fabric_llpp2_arsize_s_o3; - output fabric_llpp2_arvalid_s_o; - output fabric_llpp2_awaddr_s_o1; - output fabric_llpp2_awaddr_s_o10; - output fabric_llpp2_awaddr_s_o11; - output fabric_llpp2_awaddr_s_o12; - output fabric_llpp2_awaddr_s_o13; - output fabric_llpp2_awaddr_s_o14; - output fabric_llpp2_awaddr_s_o15; - output fabric_llpp2_awaddr_s_o16; - output fabric_llpp2_awaddr_s_o17; - output fabric_llpp2_awaddr_s_o18; - output fabric_llpp2_awaddr_s_o19; - output fabric_llpp2_awaddr_s_o2; - output fabric_llpp2_awaddr_s_o20; - output fabric_llpp2_awaddr_s_o21; - output fabric_llpp2_awaddr_s_o22; - output fabric_llpp2_awaddr_s_o23; - output fabric_llpp2_awaddr_s_o24; - output fabric_llpp2_awaddr_s_o25; - output fabric_llpp2_awaddr_s_o26; - output fabric_llpp2_awaddr_s_o27; - output fabric_llpp2_awaddr_s_o28; - output fabric_llpp2_awaddr_s_o29; - output fabric_llpp2_awaddr_s_o3; - output fabric_llpp2_awaddr_s_o30; - output fabric_llpp2_awaddr_s_o31; - output fabric_llpp2_awaddr_s_o32; - output fabric_llpp2_awaddr_s_o4; - output fabric_llpp2_awaddr_s_o5; - output fabric_llpp2_awaddr_s_o6; - output fabric_llpp2_awaddr_s_o7; - output fabric_llpp2_awaddr_s_o8; - output fabric_llpp2_awaddr_s_o9; - output fabric_llpp2_awburst_s_o1; - output fabric_llpp2_awburst_s_o2; - output fabric_llpp2_awcache_s_o1; - output fabric_llpp2_awcache_s_o2; - output fabric_llpp2_awcache_s_o3; - output fabric_llpp2_awcache_s_o4; - output fabric_llpp2_awid_s_o1; - output fabric_llpp2_awid_s_o10; - output fabric_llpp2_awid_s_o11; - output fabric_llpp2_awid_s_o12; - output fabric_llpp2_awid_s_o2; - output fabric_llpp2_awid_s_o3; - output fabric_llpp2_awid_s_o4; - output fabric_llpp2_awid_s_o5; - output fabric_llpp2_awid_s_o6; - output fabric_llpp2_awid_s_o7; - output fabric_llpp2_awid_s_o8; - output fabric_llpp2_awid_s_o9; - output fabric_llpp2_awlen_s_o1; - output fabric_llpp2_awlen_s_o2; - output fabric_llpp2_awlen_s_o3; - output fabric_llpp2_awlen_s_o4; - output fabric_llpp2_awlen_s_o5; - output fabric_llpp2_awlen_s_o6; - output fabric_llpp2_awlen_s_o7; - output fabric_llpp2_awlen_s_o8; - output fabric_llpp2_awlock_s_o; - output fabric_llpp2_awprot_s_o1; - output fabric_llpp2_awprot_s_o2; - output fabric_llpp2_awprot_s_o3; - output fabric_llpp2_awqos_s_o1; - output fabric_llpp2_awqos_s_o2; - output fabric_llpp2_awqos_s_o3; - output fabric_llpp2_awqos_s_o4; - input fabric_llpp2_awready_s_i; - output fabric_llpp2_awsize_s_o1; - output fabric_llpp2_awsize_s_o2; - output fabric_llpp2_awsize_s_o3; - output fabric_llpp2_awvalid_s_o; - input fabric_llpp2_bid_s_i1; - input fabric_llpp2_bid_s_i10; - input fabric_llpp2_bid_s_i11; - input fabric_llpp2_bid_s_i12; - input fabric_llpp2_bid_s_i2; - input fabric_llpp2_bid_s_i3; - input fabric_llpp2_bid_s_i4; - input fabric_llpp2_bid_s_i5; - input fabric_llpp2_bid_s_i6; - input fabric_llpp2_bid_s_i7; - input fabric_llpp2_bid_s_i8; - input fabric_llpp2_bid_s_i9; - output fabric_llpp2_bready_s_o; - input fabric_llpp2_bresp_s_i1; - input fabric_llpp2_bresp_s_i2; - input fabric_llpp2_bvalid_s_i; - input fabric_llpp2_rdata_s_i1; - input fabric_llpp2_rdata_s_i10; - input fabric_llpp2_rdata_s_i11; - input fabric_llpp2_rdata_s_i12; - input fabric_llpp2_rdata_s_i13; - input fabric_llpp2_rdata_s_i14; - input fabric_llpp2_rdata_s_i15; - input fabric_llpp2_rdata_s_i16; - input fabric_llpp2_rdata_s_i17; - input fabric_llpp2_rdata_s_i18; - input fabric_llpp2_rdata_s_i19; - input fabric_llpp2_rdata_s_i2; - input fabric_llpp2_rdata_s_i20; - input fabric_llpp2_rdata_s_i21; - input fabric_llpp2_rdata_s_i22; - input fabric_llpp2_rdata_s_i23; - input fabric_llpp2_rdata_s_i24; - input fabric_llpp2_rdata_s_i25; - input fabric_llpp2_rdata_s_i26; - input fabric_llpp2_rdata_s_i27; - input fabric_llpp2_rdata_s_i28; - input fabric_llpp2_rdata_s_i29; - input fabric_llpp2_rdata_s_i3; - input fabric_llpp2_rdata_s_i30; - input fabric_llpp2_rdata_s_i31; - input fabric_llpp2_rdata_s_i32; - input fabric_llpp2_rdata_s_i4; - input fabric_llpp2_rdata_s_i5; - input fabric_llpp2_rdata_s_i6; - input fabric_llpp2_rdata_s_i7; - input fabric_llpp2_rdata_s_i8; - input fabric_llpp2_rdata_s_i9; - input fabric_llpp2_rid_s_i1; - input fabric_llpp2_rid_s_i10; - input fabric_llpp2_rid_s_i11; - input fabric_llpp2_rid_s_i12; - input fabric_llpp2_rid_s_i2; - input fabric_llpp2_rid_s_i3; - input fabric_llpp2_rid_s_i4; - input fabric_llpp2_rid_s_i5; - input fabric_llpp2_rid_s_i6; - input fabric_llpp2_rid_s_i7; - input fabric_llpp2_rid_s_i8; - input fabric_llpp2_rid_s_i9; - input fabric_llpp2_rlast_s_i; - output fabric_llpp2_rready_s_o; - input fabric_llpp2_rresp_s_i1; - input fabric_llpp2_rresp_s_i2; - input fabric_llpp2_rvalid_s_i; - output fabric_llpp2_wdata_s_o1; - output fabric_llpp2_wdata_s_o10; - output fabric_llpp2_wdata_s_o11; - output fabric_llpp2_wdata_s_o12; - output fabric_llpp2_wdata_s_o13; - output fabric_llpp2_wdata_s_o14; - output fabric_llpp2_wdata_s_o15; - output fabric_llpp2_wdata_s_o16; - output fabric_llpp2_wdata_s_o17; - output fabric_llpp2_wdata_s_o18; - output fabric_llpp2_wdata_s_o19; - output fabric_llpp2_wdata_s_o2; - output fabric_llpp2_wdata_s_o20; - output fabric_llpp2_wdata_s_o21; - output fabric_llpp2_wdata_s_o22; - output fabric_llpp2_wdata_s_o23; - output fabric_llpp2_wdata_s_o24; - output fabric_llpp2_wdata_s_o25; - output fabric_llpp2_wdata_s_o26; - output fabric_llpp2_wdata_s_o27; - output fabric_llpp2_wdata_s_o28; - output fabric_llpp2_wdata_s_o29; - output fabric_llpp2_wdata_s_o3; - output fabric_llpp2_wdata_s_o30; - output fabric_llpp2_wdata_s_o31; - output fabric_llpp2_wdata_s_o32; - output fabric_llpp2_wdata_s_o4; - output fabric_llpp2_wdata_s_o5; - output fabric_llpp2_wdata_s_o6; - output fabric_llpp2_wdata_s_o7; - output fabric_llpp2_wdata_s_o8; - output fabric_llpp2_wdata_s_o9; - output fabric_llpp2_wlast_s_o; - input fabric_llpp2_wready_s_i; - output fabric_llpp2_wstrb_s_o1; - output fabric_llpp2_wstrb_s_o2; - output fabric_llpp2_wstrb_s_o3; - output fabric_llpp2_wstrb_s_o4; - output fabric_llpp2_wvalid_s_o; - output fabric_llpp3_araddr_s_o1; - output fabric_llpp3_araddr_s_o10; - output fabric_llpp3_araddr_s_o11; - output fabric_llpp3_araddr_s_o12; - output fabric_llpp3_araddr_s_o13; - output fabric_llpp3_araddr_s_o14; - output fabric_llpp3_araddr_s_o15; - output fabric_llpp3_araddr_s_o16; - output fabric_llpp3_araddr_s_o17; - output fabric_llpp3_araddr_s_o18; - output fabric_llpp3_araddr_s_o19; - output fabric_llpp3_araddr_s_o2; - output fabric_llpp3_araddr_s_o20; - output fabric_llpp3_araddr_s_o21; - output fabric_llpp3_araddr_s_o22; - output fabric_llpp3_araddr_s_o23; - output fabric_llpp3_araddr_s_o24; - output fabric_llpp3_araddr_s_o25; - output fabric_llpp3_araddr_s_o26; - output fabric_llpp3_araddr_s_o27; - output fabric_llpp3_araddr_s_o28; - output fabric_llpp3_araddr_s_o29; - output fabric_llpp3_araddr_s_o3; - output fabric_llpp3_araddr_s_o30; - output fabric_llpp3_araddr_s_o31; - output fabric_llpp3_araddr_s_o32; - output fabric_llpp3_araddr_s_o4; - output fabric_llpp3_araddr_s_o5; - output fabric_llpp3_araddr_s_o6; - output fabric_llpp3_araddr_s_o7; - output fabric_llpp3_araddr_s_o8; - output fabric_llpp3_araddr_s_o9; - output fabric_llpp3_arburst_s_o1; - output fabric_llpp3_arburst_s_o2; - output fabric_llpp3_arcache_s_o1; - output fabric_llpp3_arcache_s_o2; - output fabric_llpp3_arcache_s_o3; - output fabric_llpp3_arcache_s_o4; - output fabric_llpp3_arid_s_o1; - output fabric_llpp3_arid_s_o10; - output fabric_llpp3_arid_s_o11; - output fabric_llpp3_arid_s_o12; - output fabric_llpp3_arid_s_o2; - output fabric_llpp3_arid_s_o3; - output fabric_llpp3_arid_s_o4; - output fabric_llpp3_arid_s_o5; - output fabric_llpp3_arid_s_o6; - output fabric_llpp3_arid_s_o7; - output fabric_llpp3_arid_s_o8; - output fabric_llpp3_arid_s_o9; - output fabric_llpp3_arlen_s_o1; - output fabric_llpp3_arlen_s_o2; - output fabric_llpp3_arlen_s_o3; - output fabric_llpp3_arlen_s_o4; - output fabric_llpp3_arlen_s_o5; - output fabric_llpp3_arlen_s_o6; - output fabric_llpp3_arlen_s_o7; - output fabric_llpp3_arlen_s_o8; - output fabric_llpp3_arlock_s_o; - output fabric_llpp3_arprot_s_o1; - output fabric_llpp3_arprot_s_o2; - output fabric_llpp3_arprot_s_o3; - output fabric_llpp3_arqos_s_o1; - output fabric_llpp3_arqos_s_o2; - output fabric_llpp3_arqos_s_o3; - output fabric_llpp3_arqos_s_o4; - input fabric_llpp3_arready_s_i; - output fabric_llpp3_arsize_s_o1; - output fabric_llpp3_arsize_s_o2; - output fabric_llpp3_arsize_s_o3; - output fabric_llpp3_arvalid_s_o; - output fabric_llpp3_awaddr_s_o1; - output fabric_llpp3_awaddr_s_o10; - output fabric_llpp3_awaddr_s_o11; - output fabric_llpp3_awaddr_s_o12; - output fabric_llpp3_awaddr_s_o13; - output fabric_llpp3_awaddr_s_o14; - output fabric_llpp3_awaddr_s_o15; - output fabric_llpp3_awaddr_s_o16; - output fabric_llpp3_awaddr_s_o17; - output fabric_llpp3_awaddr_s_o18; - output fabric_llpp3_awaddr_s_o19; - output fabric_llpp3_awaddr_s_o2; - output fabric_llpp3_awaddr_s_o20; - output fabric_llpp3_awaddr_s_o21; - output fabric_llpp3_awaddr_s_o22; - output fabric_llpp3_awaddr_s_o23; - output fabric_llpp3_awaddr_s_o24; - output fabric_llpp3_awaddr_s_o25; - output fabric_llpp3_awaddr_s_o26; - output fabric_llpp3_awaddr_s_o27; - output fabric_llpp3_awaddr_s_o28; - output fabric_llpp3_awaddr_s_o29; - output fabric_llpp3_awaddr_s_o3; - output fabric_llpp3_awaddr_s_o30; - output fabric_llpp3_awaddr_s_o31; - output fabric_llpp3_awaddr_s_o32; - output fabric_llpp3_awaddr_s_o4; - output fabric_llpp3_awaddr_s_o5; - output fabric_llpp3_awaddr_s_o6; - output fabric_llpp3_awaddr_s_o7; - output fabric_llpp3_awaddr_s_o8; - output fabric_llpp3_awaddr_s_o9; - output fabric_llpp3_awburst_s_o1; - output fabric_llpp3_awburst_s_o2; - output fabric_llpp3_awcache_s_o1; - output fabric_llpp3_awcache_s_o2; - output fabric_llpp3_awcache_s_o3; - output fabric_llpp3_awcache_s_o4; - output fabric_llpp3_awid_s_o1; - output fabric_llpp3_awid_s_o10; - output fabric_llpp3_awid_s_o11; - output fabric_llpp3_awid_s_o12; - output fabric_llpp3_awid_s_o2; - output fabric_llpp3_awid_s_o3; - output fabric_llpp3_awid_s_o4; - output fabric_llpp3_awid_s_o5; - output fabric_llpp3_awid_s_o6; - output fabric_llpp3_awid_s_o7; - output fabric_llpp3_awid_s_o8; - output fabric_llpp3_awid_s_o9; - output fabric_llpp3_awlen_s_o1; - output fabric_llpp3_awlen_s_o2; - output fabric_llpp3_awlen_s_o3; - output fabric_llpp3_awlen_s_o4; - output fabric_llpp3_awlen_s_o5; - output fabric_llpp3_awlen_s_o6; - output fabric_llpp3_awlen_s_o7; - output fabric_llpp3_awlen_s_o8; - output fabric_llpp3_awlock_s_o; - output fabric_llpp3_awprot_s_o1; - output fabric_llpp3_awprot_s_o2; - output fabric_llpp3_awprot_s_o3; - output fabric_llpp3_awqos_s_o1; - output fabric_llpp3_awqos_s_o2; - output fabric_llpp3_awqos_s_o3; - output fabric_llpp3_awqos_s_o4; - input fabric_llpp3_awready_s_i; - output fabric_llpp3_awsize_s_o1; - output fabric_llpp3_awsize_s_o2; - output fabric_llpp3_awsize_s_o3; - output fabric_llpp3_awvalid_s_o; - input fabric_llpp3_bid_s_i1; - input fabric_llpp3_bid_s_i10; - input fabric_llpp3_bid_s_i11; - input fabric_llpp3_bid_s_i12; - input fabric_llpp3_bid_s_i2; - input fabric_llpp3_bid_s_i3; - input fabric_llpp3_bid_s_i4; - input fabric_llpp3_bid_s_i5; - input fabric_llpp3_bid_s_i6; - input fabric_llpp3_bid_s_i7; - input fabric_llpp3_bid_s_i8; - input fabric_llpp3_bid_s_i9; - output fabric_llpp3_bready_s_o; - input fabric_llpp3_bresp_s_i1; - input fabric_llpp3_bresp_s_i2; - input fabric_llpp3_bvalid_s_i; - input fabric_llpp3_rdata_s_i1; - input fabric_llpp3_rdata_s_i10; - input fabric_llpp3_rdata_s_i11; - input fabric_llpp3_rdata_s_i12; - input fabric_llpp3_rdata_s_i13; - input fabric_llpp3_rdata_s_i14; - input fabric_llpp3_rdata_s_i15; - input fabric_llpp3_rdata_s_i16; - input fabric_llpp3_rdata_s_i17; - input fabric_llpp3_rdata_s_i18; - input fabric_llpp3_rdata_s_i19; - input fabric_llpp3_rdata_s_i2; - input fabric_llpp3_rdata_s_i20; - input fabric_llpp3_rdata_s_i21; - input fabric_llpp3_rdata_s_i22; - input fabric_llpp3_rdata_s_i23; - input fabric_llpp3_rdata_s_i24; - input fabric_llpp3_rdata_s_i25; - input fabric_llpp3_rdata_s_i26; - input fabric_llpp3_rdata_s_i27; - input fabric_llpp3_rdata_s_i28; - input fabric_llpp3_rdata_s_i29; - input fabric_llpp3_rdata_s_i3; - input fabric_llpp3_rdata_s_i30; - input fabric_llpp3_rdata_s_i31; - input fabric_llpp3_rdata_s_i32; - input fabric_llpp3_rdata_s_i4; - input fabric_llpp3_rdata_s_i5; - input fabric_llpp3_rdata_s_i6; - input fabric_llpp3_rdata_s_i7; - input fabric_llpp3_rdata_s_i8; - input fabric_llpp3_rdata_s_i9; - input fabric_llpp3_rid_s_i1; - input fabric_llpp3_rid_s_i10; - input fabric_llpp3_rid_s_i11; - input fabric_llpp3_rid_s_i12; - input fabric_llpp3_rid_s_i2; - input fabric_llpp3_rid_s_i3; - input fabric_llpp3_rid_s_i4; - input fabric_llpp3_rid_s_i5; - input fabric_llpp3_rid_s_i6; - input fabric_llpp3_rid_s_i7; - input fabric_llpp3_rid_s_i8; - input fabric_llpp3_rid_s_i9; - input fabric_llpp3_rlast_s_i; - output fabric_llpp3_rready_s_o; - input fabric_llpp3_rresp_s_i1; - input fabric_llpp3_rresp_s_i2; - input fabric_llpp3_rvalid_s_i; - output fabric_llpp3_wdata_s_o1; - output fabric_llpp3_wdata_s_o10; - output fabric_llpp3_wdata_s_o11; - output fabric_llpp3_wdata_s_o12; - output fabric_llpp3_wdata_s_o13; - output fabric_llpp3_wdata_s_o14; - output fabric_llpp3_wdata_s_o15; - output fabric_llpp3_wdata_s_o16; - output fabric_llpp3_wdata_s_o17; - output fabric_llpp3_wdata_s_o18; - output fabric_llpp3_wdata_s_o19; - output fabric_llpp3_wdata_s_o2; - output fabric_llpp3_wdata_s_o20; - output fabric_llpp3_wdata_s_o21; - output fabric_llpp3_wdata_s_o22; - output fabric_llpp3_wdata_s_o23; - output fabric_llpp3_wdata_s_o24; - output fabric_llpp3_wdata_s_o25; - output fabric_llpp3_wdata_s_o26; - output fabric_llpp3_wdata_s_o27; - output fabric_llpp3_wdata_s_o28; - output fabric_llpp3_wdata_s_o29; - output fabric_llpp3_wdata_s_o3; - output fabric_llpp3_wdata_s_o30; - output fabric_llpp3_wdata_s_o31; - output fabric_llpp3_wdata_s_o32; - output fabric_llpp3_wdata_s_o4; - output fabric_llpp3_wdata_s_o5; - output fabric_llpp3_wdata_s_o6; - output fabric_llpp3_wdata_s_o7; - output fabric_llpp3_wdata_s_o8; - output fabric_llpp3_wdata_s_o9; - output fabric_llpp3_wlast_s_o; - input fabric_llpp3_wready_s_i; - output fabric_llpp3_wstrb_s_o1; - output fabric_llpp3_wstrb_s_o2; - output fabric_llpp3_wstrb_s_o3; - output fabric_llpp3_wstrb_s_o4; - output fabric_llpp3_wvalid_s_o; - input fabric_lowskew_i1; - input fabric_lowskew_i10; - input fabric_lowskew_i2; - input fabric_lowskew_i3; - input fabric_lowskew_i4; - input fabric_lowskew_i5; - input fabric_lowskew_i6; - input fabric_lowskew_i7; - input fabric_lowskew_i8; - input fabric_lowskew_i9; - output fabric_lowskew_o1; - output fabric_lowskew_o2; - input fabric_qos_pclk_i; - input fabric_qos_ppaddr_i1; - input fabric_qos_ppaddr_i10; - input fabric_qos_ppaddr_i11; - input fabric_qos_ppaddr_i12; - input fabric_qos_ppaddr_i13; - input fabric_qos_ppaddr_i14; - input fabric_qos_ppaddr_i15; - input fabric_qos_ppaddr_i16; - input fabric_qos_ppaddr_i17; - input fabric_qos_ppaddr_i18; - input fabric_qos_ppaddr_i19; - input fabric_qos_ppaddr_i2; - input fabric_qos_ppaddr_i20; - input fabric_qos_ppaddr_i21; - input fabric_qos_ppaddr_i22; - input fabric_qos_ppaddr_i23; - input fabric_qos_ppaddr_i24; - input fabric_qos_ppaddr_i25; - input fabric_qos_ppaddr_i26; - input fabric_qos_ppaddr_i27; - input fabric_qos_ppaddr_i28; - input fabric_qos_ppaddr_i29; - input fabric_qos_ppaddr_i3; - input fabric_qos_ppaddr_i30; - input fabric_qos_ppaddr_i31; - input fabric_qos_ppaddr_i32; - input fabric_qos_ppaddr_i4; - input fabric_qos_ppaddr_i5; - input fabric_qos_ppaddr_i6; - input fabric_qos_ppaddr_i7; - input fabric_qos_ppaddr_i8; - input fabric_qos_ppaddr_i9; - input fabric_qos_ppenable_i; - output fabric_qos_pprdata_o1; - output fabric_qos_pprdata_o10; - output fabric_qos_pprdata_o11; - output fabric_qos_pprdata_o12; - output fabric_qos_pprdata_o13; - output fabric_qos_pprdata_o14; - output fabric_qos_pprdata_o15; - output fabric_qos_pprdata_o16; - output fabric_qos_pprdata_o17; - output fabric_qos_pprdata_o18; - output fabric_qos_pprdata_o19; - output fabric_qos_pprdata_o2; - output fabric_qos_pprdata_o20; - output fabric_qos_pprdata_o21; - output fabric_qos_pprdata_o22; - output fabric_qos_pprdata_o23; - output fabric_qos_pprdata_o24; - output fabric_qos_pprdata_o25; - output fabric_qos_pprdata_o26; - output fabric_qos_pprdata_o27; - output fabric_qos_pprdata_o28; - output fabric_qos_pprdata_o29; - output fabric_qos_pprdata_o3; - output fabric_qos_pprdata_o30; - output fabric_qos_pprdata_o31; - output fabric_qos_pprdata_o32; - output fabric_qos_pprdata_o4; - output fabric_qos_pprdata_o5; - output fabric_qos_pprdata_o6; - output fabric_qos_pprdata_o7; - output fabric_qos_pprdata_o8; - output fabric_qos_pprdata_o9; - output fabric_qos_ppready_o; - output fabric_qos_ppslverr_o; - input fabric_qos_ppwdata_i1; - input fabric_qos_ppwdata_i10; - input fabric_qos_ppwdata_i11; - input fabric_qos_ppwdata_i12; - input fabric_qos_ppwdata_i13; - input fabric_qos_ppwdata_i14; - input fabric_qos_ppwdata_i15; - input fabric_qos_ppwdata_i16; - input fabric_qos_ppwdata_i17; - input fabric_qos_ppwdata_i18; - input fabric_qos_ppwdata_i19; - input fabric_qos_ppwdata_i2; - input fabric_qos_ppwdata_i20; - input fabric_qos_ppwdata_i21; - input fabric_qos_ppwdata_i22; - input fabric_qos_ppwdata_i23; - input fabric_qos_ppwdata_i24; - input fabric_qos_ppwdata_i25; - input fabric_qos_ppwdata_i26; - input fabric_qos_ppwdata_i27; - input fabric_qos_ppwdata_i28; - input fabric_qos_ppwdata_i29; - input fabric_qos_ppwdata_i3; - input fabric_qos_ppwdata_i30; - input fabric_qos_ppwdata_i31; - input fabric_qos_ppwdata_i32; - input fabric_qos_ppwdata_i4; - input fabric_qos_ppwdata_i5; - input fabric_qos_ppwdata_i6; - input fabric_qos_ppwdata_i7; - input fabric_qos_ppwdata_i8; - input fabric_qos_ppwdata_i9; - input fabric_qos_ppwrite_i; - input fabric_qos_presetn_i; - input fabric_qos_psel_i; - output fabric_soc_mon_sensor_alarm_o; - input fabric_sysc_hold_on_debug_i; - output fabric_tnd_fpga_apb_master_paddr_o1; - output fabric_tnd_fpga_apb_master_paddr_o10; - output fabric_tnd_fpga_apb_master_paddr_o11; - output fabric_tnd_fpga_apb_master_paddr_o12; - output fabric_tnd_fpga_apb_master_paddr_o13; - output fabric_tnd_fpga_apb_master_paddr_o14; - output fabric_tnd_fpga_apb_master_paddr_o15; - output fabric_tnd_fpga_apb_master_paddr_o16; - output fabric_tnd_fpga_apb_master_paddr_o17; - output fabric_tnd_fpga_apb_master_paddr_o18; - output fabric_tnd_fpga_apb_master_paddr_o19; - output fabric_tnd_fpga_apb_master_paddr_o2; - output fabric_tnd_fpga_apb_master_paddr_o20; - output fabric_tnd_fpga_apb_master_paddr_o21; - output fabric_tnd_fpga_apb_master_paddr_o22; - output fabric_tnd_fpga_apb_master_paddr_o23; - output fabric_tnd_fpga_apb_master_paddr_o24; - output fabric_tnd_fpga_apb_master_paddr_o25; - output fabric_tnd_fpga_apb_master_paddr_o26; - output fabric_tnd_fpga_apb_master_paddr_o27; - output fabric_tnd_fpga_apb_master_paddr_o28; - output fabric_tnd_fpga_apb_master_paddr_o29; - output fabric_tnd_fpga_apb_master_paddr_o3; - output fabric_tnd_fpga_apb_master_paddr_o30; - output fabric_tnd_fpga_apb_master_paddr_o31; - output fabric_tnd_fpga_apb_master_paddr_o32; - output fabric_tnd_fpga_apb_master_paddr_o4; - output fabric_tnd_fpga_apb_master_paddr_o5; - output fabric_tnd_fpga_apb_master_paddr_o6; - output fabric_tnd_fpga_apb_master_paddr_o7; - output fabric_tnd_fpga_apb_master_paddr_o8; - output fabric_tnd_fpga_apb_master_paddr_o9; - output fabric_tnd_fpga_apb_master_penable_o; - input fabric_tnd_fpga_apb_master_prdata_i1; - input fabric_tnd_fpga_apb_master_prdata_i10; - input fabric_tnd_fpga_apb_master_prdata_i11; - input fabric_tnd_fpga_apb_master_prdata_i12; - input fabric_tnd_fpga_apb_master_prdata_i13; - input fabric_tnd_fpga_apb_master_prdata_i14; - input fabric_tnd_fpga_apb_master_prdata_i15; - input fabric_tnd_fpga_apb_master_prdata_i16; - input fabric_tnd_fpga_apb_master_prdata_i17; - input fabric_tnd_fpga_apb_master_prdata_i18; - input fabric_tnd_fpga_apb_master_prdata_i19; - input fabric_tnd_fpga_apb_master_prdata_i2; - input fabric_tnd_fpga_apb_master_prdata_i20; - input fabric_tnd_fpga_apb_master_prdata_i21; - input fabric_tnd_fpga_apb_master_prdata_i22; - input fabric_tnd_fpga_apb_master_prdata_i23; - input fabric_tnd_fpga_apb_master_prdata_i24; - input fabric_tnd_fpga_apb_master_prdata_i25; - input fabric_tnd_fpga_apb_master_prdata_i26; - input fabric_tnd_fpga_apb_master_prdata_i27; - input fabric_tnd_fpga_apb_master_prdata_i28; - input fabric_tnd_fpga_apb_master_prdata_i29; - input fabric_tnd_fpga_apb_master_prdata_i3; - input fabric_tnd_fpga_apb_master_prdata_i30; - input fabric_tnd_fpga_apb_master_prdata_i31; - input fabric_tnd_fpga_apb_master_prdata_i32; - input fabric_tnd_fpga_apb_master_prdata_i4; - input fabric_tnd_fpga_apb_master_prdata_i5; - input fabric_tnd_fpga_apb_master_prdata_i6; - input fabric_tnd_fpga_apb_master_prdata_i7; - input fabric_tnd_fpga_apb_master_prdata_i8; - input fabric_tnd_fpga_apb_master_prdata_i9; - input fabric_tnd_fpga_apb_master_pready_i; - output fabric_tnd_fpga_apb_master_psel_o; - input fabric_tnd_fpga_apb_master_pslverr_i; - output fabric_tnd_fpga_apb_master_pwdata_o1; - output fabric_tnd_fpga_apb_master_pwdata_o10; - output fabric_tnd_fpga_apb_master_pwdata_o11; - output fabric_tnd_fpga_apb_master_pwdata_o12; - output fabric_tnd_fpga_apb_master_pwdata_o13; - output fabric_tnd_fpga_apb_master_pwdata_o14; - output fabric_tnd_fpga_apb_master_pwdata_o15; - output fabric_tnd_fpga_apb_master_pwdata_o16; - output fabric_tnd_fpga_apb_master_pwdata_o17; - output fabric_tnd_fpga_apb_master_pwdata_o18; - output fabric_tnd_fpga_apb_master_pwdata_o19; - output fabric_tnd_fpga_apb_master_pwdata_o2; - output fabric_tnd_fpga_apb_master_pwdata_o20; - output fabric_tnd_fpga_apb_master_pwdata_o21; - output fabric_tnd_fpga_apb_master_pwdata_o22; - output fabric_tnd_fpga_apb_master_pwdata_o23; - output fabric_tnd_fpga_apb_master_pwdata_o24; - output fabric_tnd_fpga_apb_master_pwdata_o25; - output fabric_tnd_fpga_apb_master_pwdata_o26; - output fabric_tnd_fpga_apb_master_pwdata_o27; - output fabric_tnd_fpga_apb_master_pwdata_o28; - output fabric_tnd_fpga_apb_master_pwdata_o29; - output fabric_tnd_fpga_apb_master_pwdata_o3; - output fabric_tnd_fpga_apb_master_pwdata_o30; - output fabric_tnd_fpga_apb_master_pwdata_o31; - output fabric_tnd_fpga_apb_master_pwdata_o32; - output fabric_tnd_fpga_apb_master_pwdata_o4; - output fabric_tnd_fpga_apb_master_pwdata_o5; - output fabric_tnd_fpga_apb_master_pwdata_o6; - output fabric_tnd_fpga_apb_master_pwdata_o7; - output fabric_tnd_fpga_apb_master_pwdata_o8; - output fabric_tnd_fpga_apb_master_pwdata_o9; - output fabric_tnd_fpga_apb_master_pwrite_o; - input fabric_tnd_fpga_atb_master_afready_i; - output fabric_tnd_fpga_atb_master_afvalid_o; - input fabric_tnd_fpga_atb_master_atbytes_i1; - input fabric_tnd_fpga_atb_master_atbytes_i2; - input fabric_tnd_fpga_atb_master_atbytes_i3; - input fabric_tnd_fpga_atb_master_atbytes_i4; - input fabric_tnd_fpga_atb_master_atdata_i1; - input fabric_tnd_fpga_atb_master_atdata_i10; - input fabric_tnd_fpga_atb_master_atdata_i100; - input fabric_tnd_fpga_atb_master_atdata_i101; - input fabric_tnd_fpga_atb_master_atdata_i102; - input fabric_tnd_fpga_atb_master_atdata_i103; - input fabric_tnd_fpga_atb_master_atdata_i104; - input fabric_tnd_fpga_atb_master_atdata_i105; - input fabric_tnd_fpga_atb_master_atdata_i106; - input fabric_tnd_fpga_atb_master_atdata_i107; - input fabric_tnd_fpga_atb_master_atdata_i108; - input fabric_tnd_fpga_atb_master_atdata_i109; - input fabric_tnd_fpga_atb_master_atdata_i11; - input fabric_tnd_fpga_atb_master_atdata_i110; - input fabric_tnd_fpga_atb_master_atdata_i111; - input fabric_tnd_fpga_atb_master_atdata_i112; - input fabric_tnd_fpga_atb_master_atdata_i113; - input fabric_tnd_fpga_atb_master_atdata_i114; - input fabric_tnd_fpga_atb_master_atdata_i115; - input fabric_tnd_fpga_atb_master_atdata_i116; - input fabric_tnd_fpga_atb_master_atdata_i117; - input fabric_tnd_fpga_atb_master_atdata_i118; - input fabric_tnd_fpga_atb_master_atdata_i119; - input fabric_tnd_fpga_atb_master_atdata_i12; - input fabric_tnd_fpga_atb_master_atdata_i120; - input fabric_tnd_fpga_atb_master_atdata_i121; - input fabric_tnd_fpga_atb_master_atdata_i122; - input fabric_tnd_fpga_atb_master_atdata_i123; - input fabric_tnd_fpga_atb_master_atdata_i124; - input fabric_tnd_fpga_atb_master_atdata_i125; - input fabric_tnd_fpga_atb_master_atdata_i126; - input fabric_tnd_fpga_atb_master_atdata_i127; - input fabric_tnd_fpga_atb_master_atdata_i128; - input fabric_tnd_fpga_atb_master_atdata_i13; - input fabric_tnd_fpga_atb_master_atdata_i14; - input fabric_tnd_fpga_atb_master_atdata_i15; - input fabric_tnd_fpga_atb_master_atdata_i16; - input fabric_tnd_fpga_atb_master_atdata_i17; - input fabric_tnd_fpga_atb_master_atdata_i18; - input fabric_tnd_fpga_atb_master_atdata_i19; - input fabric_tnd_fpga_atb_master_atdata_i2; - input fabric_tnd_fpga_atb_master_atdata_i20; - input fabric_tnd_fpga_atb_master_atdata_i21; - input fabric_tnd_fpga_atb_master_atdata_i22; - input fabric_tnd_fpga_atb_master_atdata_i23; - input fabric_tnd_fpga_atb_master_atdata_i24; - input fabric_tnd_fpga_atb_master_atdata_i25; - input fabric_tnd_fpga_atb_master_atdata_i26; - input fabric_tnd_fpga_atb_master_atdata_i27; - input fabric_tnd_fpga_atb_master_atdata_i28; - input fabric_tnd_fpga_atb_master_atdata_i29; - input fabric_tnd_fpga_atb_master_atdata_i3; - input fabric_tnd_fpga_atb_master_atdata_i30; - input fabric_tnd_fpga_atb_master_atdata_i31; - input fabric_tnd_fpga_atb_master_atdata_i32; - input fabric_tnd_fpga_atb_master_atdata_i33; - input fabric_tnd_fpga_atb_master_atdata_i34; - input fabric_tnd_fpga_atb_master_atdata_i35; - input fabric_tnd_fpga_atb_master_atdata_i36; - input fabric_tnd_fpga_atb_master_atdata_i37; - input fabric_tnd_fpga_atb_master_atdata_i38; - input fabric_tnd_fpga_atb_master_atdata_i39; - input fabric_tnd_fpga_atb_master_atdata_i4; - input fabric_tnd_fpga_atb_master_atdata_i40; - input fabric_tnd_fpga_atb_master_atdata_i41; - input fabric_tnd_fpga_atb_master_atdata_i42; - input fabric_tnd_fpga_atb_master_atdata_i43; - input fabric_tnd_fpga_atb_master_atdata_i44; - input fabric_tnd_fpga_atb_master_atdata_i45; - input fabric_tnd_fpga_atb_master_atdata_i46; - input fabric_tnd_fpga_atb_master_atdata_i47; - input fabric_tnd_fpga_atb_master_atdata_i48; - input fabric_tnd_fpga_atb_master_atdata_i49; - input fabric_tnd_fpga_atb_master_atdata_i5; - input fabric_tnd_fpga_atb_master_atdata_i50; - input fabric_tnd_fpga_atb_master_atdata_i51; - input fabric_tnd_fpga_atb_master_atdata_i52; - input fabric_tnd_fpga_atb_master_atdata_i53; - input fabric_tnd_fpga_atb_master_atdata_i54; - input fabric_tnd_fpga_atb_master_atdata_i55; - input fabric_tnd_fpga_atb_master_atdata_i56; - input fabric_tnd_fpga_atb_master_atdata_i57; - input fabric_tnd_fpga_atb_master_atdata_i58; - input fabric_tnd_fpga_atb_master_atdata_i59; - input fabric_tnd_fpga_atb_master_atdata_i6; - input fabric_tnd_fpga_atb_master_atdata_i60; - input fabric_tnd_fpga_atb_master_atdata_i61; - input fabric_tnd_fpga_atb_master_atdata_i62; - input fabric_tnd_fpga_atb_master_atdata_i63; - input fabric_tnd_fpga_atb_master_atdata_i64; - input fabric_tnd_fpga_atb_master_atdata_i65; - input fabric_tnd_fpga_atb_master_atdata_i66; - input fabric_tnd_fpga_atb_master_atdata_i67; - input fabric_tnd_fpga_atb_master_atdata_i68; - input fabric_tnd_fpga_atb_master_atdata_i69; - input fabric_tnd_fpga_atb_master_atdata_i7; - input fabric_tnd_fpga_atb_master_atdata_i70; - input fabric_tnd_fpga_atb_master_atdata_i71; - input fabric_tnd_fpga_atb_master_atdata_i72; - input fabric_tnd_fpga_atb_master_atdata_i73; - input fabric_tnd_fpga_atb_master_atdata_i74; - input fabric_tnd_fpga_atb_master_atdata_i75; - input fabric_tnd_fpga_atb_master_atdata_i76; - input fabric_tnd_fpga_atb_master_atdata_i77; - input fabric_tnd_fpga_atb_master_atdata_i78; - input fabric_tnd_fpga_atb_master_atdata_i79; - input fabric_tnd_fpga_atb_master_atdata_i8; - input fabric_tnd_fpga_atb_master_atdata_i80; - input fabric_tnd_fpga_atb_master_atdata_i81; - input fabric_tnd_fpga_atb_master_atdata_i82; - input fabric_tnd_fpga_atb_master_atdata_i83; - input fabric_tnd_fpga_atb_master_atdata_i84; - input fabric_tnd_fpga_atb_master_atdata_i85; - input fabric_tnd_fpga_atb_master_atdata_i86; - input fabric_tnd_fpga_atb_master_atdata_i87; - input fabric_tnd_fpga_atb_master_atdata_i88; - input fabric_tnd_fpga_atb_master_atdata_i89; - input fabric_tnd_fpga_atb_master_atdata_i9; - input fabric_tnd_fpga_atb_master_atdata_i90; - input fabric_tnd_fpga_atb_master_atdata_i91; - input fabric_tnd_fpga_atb_master_atdata_i92; - input fabric_tnd_fpga_atb_master_atdata_i93; - input fabric_tnd_fpga_atb_master_atdata_i94; - input fabric_tnd_fpga_atb_master_atdata_i95; - input fabric_tnd_fpga_atb_master_atdata_i96; - input fabric_tnd_fpga_atb_master_atdata_i97; - input fabric_tnd_fpga_atb_master_atdata_i98; - input fabric_tnd_fpga_atb_master_atdata_i99; - input fabric_tnd_fpga_atb_master_atid_i1; - input fabric_tnd_fpga_atb_master_atid_i2; - input fabric_tnd_fpga_atb_master_atid_i3; - input fabric_tnd_fpga_atb_master_atid_i4; - input fabric_tnd_fpga_atb_master_atid_i5; - input fabric_tnd_fpga_atb_master_atid_i6; - input fabric_tnd_fpga_atb_master_atid_i7; - output fabric_tnd_fpga_atb_master_atready_o; - input fabric_tnd_fpga_atb_master_atvalid_i; - output fabric_tnd_fpga_atb_master_syncreq_o; - output fabric_tnd_hssl_apb_master_paddr_o1; - output fabric_tnd_hssl_apb_master_paddr_o10; - output fabric_tnd_hssl_apb_master_paddr_o11; - output fabric_tnd_hssl_apb_master_paddr_o12; - output fabric_tnd_hssl_apb_master_paddr_o13; - output fabric_tnd_hssl_apb_master_paddr_o14; - output fabric_tnd_hssl_apb_master_paddr_o15; - output fabric_tnd_hssl_apb_master_paddr_o16; - output fabric_tnd_hssl_apb_master_paddr_o17; - output fabric_tnd_hssl_apb_master_paddr_o18; - output fabric_tnd_hssl_apb_master_paddr_o19; - output fabric_tnd_hssl_apb_master_paddr_o2; - output fabric_tnd_hssl_apb_master_paddr_o20; - output fabric_tnd_hssl_apb_master_paddr_o21; - output fabric_tnd_hssl_apb_master_paddr_o22; - output fabric_tnd_hssl_apb_master_paddr_o23; - output fabric_tnd_hssl_apb_master_paddr_o24; - output fabric_tnd_hssl_apb_master_paddr_o25; - output fabric_tnd_hssl_apb_master_paddr_o26; - output fabric_tnd_hssl_apb_master_paddr_o27; - output fabric_tnd_hssl_apb_master_paddr_o28; - output fabric_tnd_hssl_apb_master_paddr_o29; - output fabric_tnd_hssl_apb_master_paddr_o3; - output fabric_tnd_hssl_apb_master_paddr_o30; - output fabric_tnd_hssl_apb_master_paddr_o31; - output fabric_tnd_hssl_apb_master_paddr_o32; - output fabric_tnd_hssl_apb_master_paddr_o4; - output fabric_tnd_hssl_apb_master_paddr_o5; - output fabric_tnd_hssl_apb_master_paddr_o6; - output fabric_tnd_hssl_apb_master_paddr_o7; - output fabric_tnd_hssl_apb_master_paddr_o8; - output fabric_tnd_hssl_apb_master_paddr_o9; - output fabric_tnd_hssl_apb_master_penable_o; - input fabric_tnd_hssl_apb_master_prdata_i1; - input fabric_tnd_hssl_apb_master_prdata_i10; - input fabric_tnd_hssl_apb_master_prdata_i11; - input fabric_tnd_hssl_apb_master_prdata_i12; - input fabric_tnd_hssl_apb_master_prdata_i13; - input fabric_tnd_hssl_apb_master_prdata_i14; - input fabric_tnd_hssl_apb_master_prdata_i15; - input fabric_tnd_hssl_apb_master_prdata_i16; - input fabric_tnd_hssl_apb_master_prdata_i17; - input fabric_tnd_hssl_apb_master_prdata_i18; - input fabric_tnd_hssl_apb_master_prdata_i19; - input fabric_tnd_hssl_apb_master_prdata_i2; - input fabric_tnd_hssl_apb_master_prdata_i20; - input fabric_tnd_hssl_apb_master_prdata_i21; - input fabric_tnd_hssl_apb_master_prdata_i22; - input fabric_tnd_hssl_apb_master_prdata_i23; - input fabric_tnd_hssl_apb_master_prdata_i24; - input fabric_tnd_hssl_apb_master_prdata_i25; - input fabric_tnd_hssl_apb_master_prdata_i26; - input fabric_tnd_hssl_apb_master_prdata_i27; - input fabric_tnd_hssl_apb_master_prdata_i28; - input fabric_tnd_hssl_apb_master_prdata_i29; - input fabric_tnd_hssl_apb_master_prdata_i3; - input fabric_tnd_hssl_apb_master_prdata_i30; - input fabric_tnd_hssl_apb_master_prdata_i31; - input fabric_tnd_hssl_apb_master_prdata_i32; - input fabric_tnd_hssl_apb_master_prdata_i4; - input fabric_tnd_hssl_apb_master_prdata_i5; - input fabric_tnd_hssl_apb_master_prdata_i6; - input fabric_tnd_hssl_apb_master_prdata_i7; - input fabric_tnd_hssl_apb_master_prdata_i8; - input fabric_tnd_hssl_apb_master_prdata_i9; - input fabric_tnd_hssl_apb_master_pready_i; - output fabric_tnd_hssl_apb_master_psel_o; - input fabric_tnd_hssl_apb_master_pslverr_i; - output fabric_tnd_hssl_apb_master_pwdata_o1; - output fabric_tnd_hssl_apb_master_pwdata_o10; - output fabric_tnd_hssl_apb_master_pwdata_o11; - output fabric_tnd_hssl_apb_master_pwdata_o12; - output fabric_tnd_hssl_apb_master_pwdata_o13; - output fabric_tnd_hssl_apb_master_pwdata_o14; - output fabric_tnd_hssl_apb_master_pwdata_o15; - output fabric_tnd_hssl_apb_master_pwdata_o16; - output fabric_tnd_hssl_apb_master_pwdata_o17; - output fabric_tnd_hssl_apb_master_pwdata_o18; - output fabric_tnd_hssl_apb_master_pwdata_o19; - output fabric_tnd_hssl_apb_master_pwdata_o2; - output fabric_tnd_hssl_apb_master_pwdata_o20; - output fabric_tnd_hssl_apb_master_pwdata_o21; - output fabric_tnd_hssl_apb_master_pwdata_o22; - output fabric_tnd_hssl_apb_master_pwdata_o23; - output fabric_tnd_hssl_apb_master_pwdata_o24; - output fabric_tnd_hssl_apb_master_pwdata_o25; - output fabric_tnd_hssl_apb_master_pwdata_o26; - output fabric_tnd_hssl_apb_master_pwdata_o27; - output fabric_tnd_hssl_apb_master_pwdata_o28; - output fabric_tnd_hssl_apb_master_pwdata_o29; - output fabric_tnd_hssl_apb_master_pwdata_o3; - output fabric_tnd_hssl_apb_master_pwdata_o30; - output fabric_tnd_hssl_apb_master_pwdata_o31; - output fabric_tnd_hssl_apb_master_pwdata_o32; - output fabric_tnd_hssl_apb_master_pwdata_o4; - output fabric_tnd_hssl_apb_master_pwdata_o5; - output fabric_tnd_hssl_apb_master_pwdata_o6; - output fabric_tnd_hssl_apb_master_pwdata_o7; - output fabric_tnd_hssl_apb_master_pwdata_o8; - output fabric_tnd_hssl_apb_master_pwdata_o9; - output fabric_tnd_hssl_apb_master_pwrite_o; - output fabric_tnd_hssl_atb_master_afready_o; - input fabric_tnd_hssl_atb_master_afvalid_i; - output fabric_tnd_hssl_atb_master_atbytes_o1; - output fabric_tnd_hssl_atb_master_atbytes_o2; - output fabric_tnd_hssl_atb_master_atbytes_o3; - output fabric_tnd_hssl_atb_master_atbytes_o4; - output fabric_tnd_hssl_atb_master_atdata_o1; - output fabric_tnd_hssl_atb_master_atdata_o10; - output fabric_tnd_hssl_atb_master_atdata_o100; - output fabric_tnd_hssl_atb_master_atdata_o101; - output fabric_tnd_hssl_atb_master_atdata_o102; - output fabric_tnd_hssl_atb_master_atdata_o103; - output fabric_tnd_hssl_atb_master_atdata_o104; - output fabric_tnd_hssl_atb_master_atdata_o105; - output fabric_tnd_hssl_atb_master_atdata_o106; - output fabric_tnd_hssl_atb_master_atdata_o107; - output fabric_tnd_hssl_atb_master_atdata_o108; - output fabric_tnd_hssl_atb_master_atdata_o109; - output fabric_tnd_hssl_atb_master_atdata_o11; - output fabric_tnd_hssl_atb_master_atdata_o110; - output fabric_tnd_hssl_atb_master_atdata_o111; - output fabric_tnd_hssl_atb_master_atdata_o112; - output fabric_tnd_hssl_atb_master_atdata_o113; - output fabric_tnd_hssl_atb_master_atdata_o114; - output fabric_tnd_hssl_atb_master_atdata_o115; - output fabric_tnd_hssl_atb_master_atdata_o116; - output fabric_tnd_hssl_atb_master_atdata_o117; - output fabric_tnd_hssl_atb_master_atdata_o118; - output fabric_tnd_hssl_atb_master_atdata_o119; - output fabric_tnd_hssl_atb_master_atdata_o12; - output fabric_tnd_hssl_atb_master_atdata_o120; - output fabric_tnd_hssl_atb_master_atdata_o121; - output fabric_tnd_hssl_atb_master_atdata_o122; - output fabric_tnd_hssl_atb_master_atdata_o123; - output fabric_tnd_hssl_atb_master_atdata_o124; - output fabric_tnd_hssl_atb_master_atdata_o125; - output fabric_tnd_hssl_atb_master_atdata_o126; - output fabric_tnd_hssl_atb_master_atdata_o127; - output fabric_tnd_hssl_atb_master_atdata_o128; - output fabric_tnd_hssl_atb_master_atdata_o13; - output fabric_tnd_hssl_atb_master_atdata_o14; - output fabric_tnd_hssl_atb_master_atdata_o15; - output fabric_tnd_hssl_atb_master_atdata_o16; - output fabric_tnd_hssl_atb_master_atdata_o17; - output fabric_tnd_hssl_atb_master_atdata_o18; - output fabric_tnd_hssl_atb_master_atdata_o19; - output fabric_tnd_hssl_atb_master_atdata_o2; - output fabric_tnd_hssl_atb_master_atdata_o20; - output fabric_tnd_hssl_atb_master_atdata_o21; - output fabric_tnd_hssl_atb_master_atdata_o22; - output fabric_tnd_hssl_atb_master_atdata_o23; - output fabric_tnd_hssl_atb_master_atdata_o24; - output fabric_tnd_hssl_atb_master_atdata_o25; - output fabric_tnd_hssl_atb_master_atdata_o26; - output fabric_tnd_hssl_atb_master_atdata_o27; - output fabric_tnd_hssl_atb_master_atdata_o28; - output fabric_tnd_hssl_atb_master_atdata_o29; - output fabric_tnd_hssl_atb_master_atdata_o3; - output fabric_tnd_hssl_atb_master_atdata_o30; - output fabric_tnd_hssl_atb_master_atdata_o31; - output fabric_tnd_hssl_atb_master_atdata_o32; - output fabric_tnd_hssl_atb_master_atdata_o33; - output fabric_tnd_hssl_atb_master_atdata_o34; - output fabric_tnd_hssl_atb_master_atdata_o35; - output fabric_tnd_hssl_atb_master_atdata_o36; - output fabric_tnd_hssl_atb_master_atdata_o37; - output fabric_tnd_hssl_atb_master_atdata_o38; - output fabric_tnd_hssl_atb_master_atdata_o39; - output fabric_tnd_hssl_atb_master_atdata_o4; - output fabric_tnd_hssl_atb_master_atdata_o40; - output fabric_tnd_hssl_atb_master_atdata_o41; - output fabric_tnd_hssl_atb_master_atdata_o42; - output fabric_tnd_hssl_atb_master_atdata_o43; - output fabric_tnd_hssl_atb_master_atdata_o44; - output fabric_tnd_hssl_atb_master_atdata_o45; - output fabric_tnd_hssl_atb_master_atdata_o46; - output fabric_tnd_hssl_atb_master_atdata_o47; - output fabric_tnd_hssl_atb_master_atdata_o48; - output fabric_tnd_hssl_atb_master_atdata_o49; - output fabric_tnd_hssl_atb_master_atdata_o5; - output fabric_tnd_hssl_atb_master_atdata_o50; - output fabric_tnd_hssl_atb_master_atdata_o51; - output fabric_tnd_hssl_atb_master_atdata_o52; - output fabric_tnd_hssl_atb_master_atdata_o53; - output fabric_tnd_hssl_atb_master_atdata_o54; - output fabric_tnd_hssl_atb_master_atdata_o55; - output fabric_tnd_hssl_atb_master_atdata_o56; - output fabric_tnd_hssl_atb_master_atdata_o57; - output fabric_tnd_hssl_atb_master_atdata_o58; - output fabric_tnd_hssl_atb_master_atdata_o59; - output fabric_tnd_hssl_atb_master_atdata_o6; - output fabric_tnd_hssl_atb_master_atdata_o60; - output fabric_tnd_hssl_atb_master_atdata_o61; - output fabric_tnd_hssl_atb_master_atdata_o62; - output fabric_tnd_hssl_atb_master_atdata_o63; - output fabric_tnd_hssl_atb_master_atdata_o64; - output fabric_tnd_hssl_atb_master_atdata_o65; - output fabric_tnd_hssl_atb_master_atdata_o66; - output fabric_tnd_hssl_atb_master_atdata_o67; - output fabric_tnd_hssl_atb_master_atdata_o68; - output fabric_tnd_hssl_atb_master_atdata_o69; - output fabric_tnd_hssl_atb_master_atdata_o7; - output fabric_tnd_hssl_atb_master_atdata_o70; - output fabric_tnd_hssl_atb_master_atdata_o71; - output fabric_tnd_hssl_atb_master_atdata_o72; - output fabric_tnd_hssl_atb_master_atdata_o73; - output fabric_tnd_hssl_atb_master_atdata_o74; - output fabric_tnd_hssl_atb_master_atdata_o75; - output fabric_tnd_hssl_atb_master_atdata_o76; - output fabric_tnd_hssl_atb_master_atdata_o77; - output fabric_tnd_hssl_atb_master_atdata_o78; - output fabric_tnd_hssl_atb_master_atdata_o79; - output fabric_tnd_hssl_atb_master_atdata_o8; - output fabric_tnd_hssl_atb_master_atdata_o80; - output fabric_tnd_hssl_atb_master_atdata_o81; - output fabric_tnd_hssl_atb_master_atdata_o82; - output fabric_tnd_hssl_atb_master_atdata_o83; - output fabric_tnd_hssl_atb_master_atdata_o84; - output fabric_tnd_hssl_atb_master_atdata_o85; - output fabric_tnd_hssl_atb_master_atdata_o86; - output fabric_tnd_hssl_atb_master_atdata_o87; - output fabric_tnd_hssl_atb_master_atdata_o88; - output fabric_tnd_hssl_atb_master_atdata_o89; - output fabric_tnd_hssl_atb_master_atdata_o9; - output fabric_tnd_hssl_atb_master_atdata_o90; - output fabric_tnd_hssl_atb_master_atdata_o91; - output fabric_tnd_hssl_atb_master_atdata_o92; - output fabric_tnd_hssl_atb_master_atdata_o93; - output fabric_tnd_hssl_atb_master_atdata_o94; - output fabric_tnd_hssl_atb_master_atdata_o95; - output fabric_tnd_hssl_atb_master_atdata_o96; - output fabric_tnd_hssl_atb_master_atdata_o97; - output fabric_tnd_hssl_atb_master_atdata_o98; - output fabric_tnd_hssl_atb_master_atdata_o99; - output fabric_tnd_hssl_atb_master_atid_o1; - output fabric_tnd_hssl_atb_master_atid_o2; - output fabric_tnd_hssl_atb_master_atid_o3; - output fabric_tnd_hssl_atb_master_atid_o4; - output fabric_tnd_hssl_atb_master_atid_o5; - output fabric_tnd_hssl_atb_master_atid_o6; - output fabric_tnd_hssl_atb_master_atid_o7; - input fabric_tnd_hssl_atb_master_atready_i; - output fabric_tnd_hssl_atb_master_atvalid_o; - input fabric_tnd_hssl_atb_master_syncreq_i; - output fabric_tnd_hssl_flushin_o; - output fabric_tnd_hssl_trigin_o; - output fabric_tnd_trace_clk_traceoutportintf_o; - output fabric_tnd_trace_ctl_traceoutportintf_o; - output fabric_tnd_trace_data_traceoutportintf_o1; - output fabric_tnd_trace_data_traceoutportintf_o10; - output fabric_tnd_trace_data_traceoutportintf_o11; - output fabric_tnd_trace_data_traceoutportintf_o12; - output fabric_tnd_trace_data_traceoutportintf_o13; - output fabric_tnd_trace_data_traceoutportintf_o14; - output fabric_tnd_trace_data_traceoutportintf_o15; - output fabric_tnd_trace_data_traceoutportintf_o16; - output fabric_tnd_trace_data_traceoutportintf_o17; - output fabric_tnd_trace_data_traceoutportintf_o18; - output fabric_tnd_trace_data_traceoutportintf_o19; - output fabric_tnd_trace_data_traceoutportintf_o2; - output fabric_tnd_trace_data_traceoutportintf_o20; - output fabric_tnd_trace_data_traceoutportintf_o21; - output fabric_tnd_trace_data_traceoutportintf_o22; - output fabric_tnd_trace_data_traceoutportintf_o23; - output fabric_tnd_trace_data_traceoutportintf_o24; - output fabric_tnd_trace_data_traceoutportintf_o25; - output fabric_tnd_trace_data_traceoutportintf_o26; - output fabric_tnd_trace_data_traceoutportintf_o27; - output fabric_tnd_trace_data_traceoutportintf_o28; - output fabric_tnd_trace_data_traceoutportintf_o29; - output fabric_tnd_trace_data_traceoutportintf_o3; - output fabric_tnd_trace_data_traceoutportintf_o30; - output fabric_tnd_trace_data_traceoutportintf_o31; - output fabric_tnd_trace_data_traceoutportintf_o32; - output fabric_tnd_trace_data_traceoutportintf_o4; - output fabric_tnd_trace_data_traceoutportintf_o5; - output fabric_tnd_trace_data_traceoutportintf_o6; - output fabric_tnd_trace_data_traceoutportintf_o7; - output fabric_tnd_trace_data_traceoutportintf_o8; - output fabric_tnd_trace_data_traceoutportintf_o9; - output fabric_tst_pll_lock_o1; - output fabric_tst_pll_lock_o2; - output fabric_tst_pll_lock_o3; - output fabric_tst_pll_lock_o4; - output fabric_tst_pll_lock_o5; - output fabric_tst_pll_lock_o6; - output fabric_tst_pll_lock_o7; - output fabric_tsvalue_tsgen_fpga_o1; - output fabric_tsvalue_tsgen_fpga_o10; - output fabric_tsvalue_tsgen_fpga_o11; - output fabric_tsvalue_tsgen_fpga_o12; - output fabric_tsvalue_tsgen_fpga_o13; - output fabric_tsvalue_tsgen_fpga_o14; - output fabric_tsvalue_tsgen_fpga_o15; - output fabric_tsvalue_tsgen_fpga_o16; - output fabric_tsvalue_tsgen_fpga_o17; - output fabric_tsvalue_tsgen_fpga_o18; - output fabric_tsvalue_tsgen_fpga_o19; - output fabric_tsvalue_tsgen_fpga_o2; - output fabric_tsvalue_tsgen_fpga_o20; - output fabric_tsvalue_tsgen_fpga_o21; - output fabric_tsvalue_tsgen_fpga_o22; - output fabric_tsvalue_tsgen_fpga_o23; - output fabric_tsvalue_tsgen_fpga_o24; - output fabric_tsvalue_tsgen_fpga_o25; - output fabric_tsvalue_tsgen_fpga_o26; - output fabric_tsvalue_tsgen_fpga_o27; - output fabric_tsvalue_tsgen_fpga_o28; - output fabric_tsvalue_tsgen_fpga_o29; - output fabric_tsvalue_tsgen_fpga_o3; - output fabric_tsvalue_tsgen_fpga_o30; - output fabric_tsvalue_tsgen_fpga_o31; - output fabric_tsvalue_tsgen_fpga_o32; - output fabric_tsvalue_tsgen_fpga_o33; - output fabric_tsvalue_tsgen_fpga_o34; - output fabric_tsvalue_tsgen_fpga_o35; - output fabric_tsvalue_tsgen_fpga_o36; - output fabric_tsvalue_tsgen_fpga_o37; - output fabric_tsvalue_tsgen_fpga_o38; - output fabric_tsvalue_tsgen_fpga_o39; - output fabric_tsvalue_tsgen_fpga_o4; - output fabric_tsvalue_tsgen_fpga_o40; - output fabric_tsvalue_tsgen_fpga_o41; - output fabric_tsvalue_tsgen_fpga_o42; - output fabric_tsvalue_tsgen_fpga_o43; - output fabric_tsvalue_tsgen_fpga_o44; - output fabric_tsvalue_tsgen_fpga_o45; - output fabric_tsvalue_tsgen_fpga_o46; - output fabric_tsvalue_tsgen_fpga_o47; - output fabric_tsvalue_tsgen_fpga_o48; - output fabric_tsvalue_tsgen_fpga_o49; - output fabric_tsvalue_tsgen_fpga_o5; - output fabric_tsvalue_tsgen_fpga_o50; - output fabric_tsvalue_tsgen_fpga_o51; - output fabric_tsvalue_tsgen_fpga_o52; - output fabric_tsvalue_tsgen_fpga_o53; - output fabric_tsvalue_tsgen_fpga_o54; - output fabric_tsvalue_tsgen_fpga_o55; - output fabric_tsvalue_tsgen_fpga_o56; - output fabric_tsvalue_tsgen_fpga_o57; - output fabric_tsvalue_tsgen_fpga_o58; - output fabric_tsvalue_tsgen_fpga_o59; - output fabric_tsvalue_tsgen_fpga_o6; - output fabric_tsvalue_tsgen_fpga_o60; - output fabric_tsvalue_tsgen_fpga_o61; - output fabric_tsvalue_tsgen_fpga_o62; - output fabric_tsvalue_tsgen_fpga_o63; - output fabric_tsvalue_tsgen_fpga_o64; - output fabric_tsvalue_tsgen_fpga_o7; - output fabric_tsvalue_tsgen_fpga_o8; - output fabric_tsvalue_tsgen_fpga_o9; - output fabric_watchdog0_signal_0_o; - output fabric_watchdog0_signal_1_o; - output fabric_watchdog1_signal_0_o; - output fabric_watchdog1_signal_1_o; - output fabric_watchdog2_signal_0_o; - output fabric_watchdog2_signal_1_o; - output fabric_watchdog3_signal_0_o; - output fabric_watchdog3_signal_1_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SOC_INTERFACE_V1_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o -, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i -, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o -, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o -, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i -, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o -, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_pclk_i, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o -, fabric_tnd_fpga_atb_master_atready_o, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o -, fabric_watchdog1_signal_1_o, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i -, fabric_erom_fpga_cpu3_niden_i, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o, fabric_fpga_arqos_axi_s1_o -, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o, fabric_fpga_arcache_axi_s2_o -, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i, fabric_fpga_rid_axi_s2_i -, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i, fabric_fpga_awlen_axi_m1_i -, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i, fabric_fpga_arprot_axi_m2_i -, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o, fabric_fpga_ddr0_araddr_i -, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i, fabric_llpp0_araddr_s_o -, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i, fabric_llpp0_rid_s_i -, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arqos_s1_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i -, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o -, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o -, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i -, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o); - input [2:0] fabric_enable_TMR_i; - input fabric_erom_fpga_cpu0_dbgen_i; - input fabric_erom_fpga_cpu0_hiden_i; - input fabric_erom_fpga_cpu0_hniden_i; - input fabric_erom_fpga_cpu0_niden_i; - input fabric_erom_fpga_cpu1_dbgen_i; - input fabric_erom_fpga_cpu1_hiden_i; - input fabric_erom_fpga_cpu1_hniden_i; - input fabric_erom_fpga_cpu1_niden_i; - input fabric_erom_fpga_cpu2_dbgen_i; - input fabric_erom_fpga_cpu2_hiden_i; - input fabric_erom_fpga_cpu2_hniden_i; - input fabric_erom_fpga_cpu2_niden_i; - input fabric_erom_fpga_cpu3_dbgen_i; - input fabric_erom_fpga_cpu3_hiden_i; - input fabric_erom_fpga_cpu3_hniden_i; - input fabric_erom_fpga_cpu3_niden_i; - input fabric_erom_fpga_cs_dbgen_i; - input fabric_erom_fpga_cs_deviceen_i; - input fabric_erom_fpga_cs_niden_i; - input fabric_erom_fpga_cs_rst_n_i; - input fabric_erom_fpga_debug_en_i; - input [39:0] fabric_fpga_araddr_axi_m1_i; - input [39:0] fabric_fpga_araddr_axi_m2_i; - output [39:0] fabric_fpga_araddr_axi_s1_o; - output [39:0] fabric_fpga_araddr_axi_s2_o; - input [1:0] fabric_fpga_arburst_axi_m1_i; - input [1:0] fabric_fpga_arburst_axi_m2_i; - output [1:0] fabric_fpga_arburst_axi_s1_o; - output [1:0] fabric_fpga_arburst_axi_s2_o; - input [3:0] fabric_fpga_arcache_axi_m1_i; - input [3:0] fabric_fpga_arcache_axi_m2_i; - output [3:0] fabric_fpga_arcache_axi_s1_o; - output [3:0] fabric_fpga_arcache_axi_s2_o; - input [4:0] fabric_fpga_arid_axi_m1_i; - input [4:0] fabric_fpga_arid_axi_m2_i; - output [11:0] fabric_fpga_arid_axi_s1_o; - output [11:0] fabric_fpga_arid_axi_s2_o; - input [7:0] fabric_fpga_arlen_axi_m1_i; - input [7:0] fabric_fpga_arlen_axi_m2_i; - output [7:0] fabric_fpga_arlen_axi_s1_o; - output [7:0] fabric_fpga_arlen_axi_s2_o; - input fabric_fpga_arlock_axi_m1_i; - input fabric_fpga_arlock_axi_m2_i; - output fabric_fpga_arlock_axi_s1_o; - output fabric_fpga_arlock_axi_s2_o; - input [2:0] fabric_fpga_arprot_axi_m1_i; - input [2:0] fabric_fpga_arprot_axi_m2_i; - output [2:0] fabric_fpga_arprot_axi_s1_o; - output [2:0] fabric_fpga_arprot_axi_s2_o; - input [3:0] fabric_fpga_arqos_axi_m1_i; - input [3:0] fabric_fpga_arqos_axi_m2_i; - output [3:0] fabric_fpga_arqos_axi_s1_o; - output [3:0] fabric_fpga_arqos_axi_s2_o; - output fabric_fpga_arready_axi_m1_o; - output fabric_fpga_arready_axi_m2_o; - input fabric_fpga_arready_axi_s1_i; - input fabric_fpga_arready_axi_s2_i; - output [3:0] fabric_fpga_arregion_axi_s1_o; - output [3:0] fabric_fpga_arregion_axi_s2_o; - input [2:0] fabric_fpga_arsize_axi_m1_i; - input [2:0] fabric_fpga_arsize_axi_m2_i; - output [2:0] fabric_fpga_arsize_axi_s1_o; - output [2:0] fabric_fpga_arsize_axi_s2_o; - input fabric_fpga_arvalid_axi_m1_i; - input fabric_fpga_arvalid_axi_m2_i; - output fabric_fpga_arvalid_axi_s1_o; - output fabric_fpga_arvalid_axi_s2_o; - input [39:0] fabric_fpga_awaddr_axi_m1_i; - input [39:0] fabric_fpga_awaddr_axi_m2_i; - output [39:0] fabric_fpga_awaddr_axi_s1_o; - output [39:0] fabric_fpga_awaddr_axi_s2_o; - input [1:0] fabric_fpga_awburst_axi_m1_i; - input [1:0] fabric_fpga_awburst_axi_m2_i; - output [1:0] fabric_fpga_awburst_axi_s1_o; - output [1:0] fabric_fpga_awburst_axi_s2_o; - input [3:0] fabric_fpga_awcache_axi_m1_i; - input [3:0] fabric_fpga_awcache_axi_m2_i; - output [3:0] fabric_fpga_awcache_axi_s1_o; - output [3:0] fabric_fpga_awcache_axi_s2_o; - input [4:0] fabric_fpga_awid_axi_m1_i; - input [4:0] fabric_fpga_awid_axi_m2_i; - output [11:0] fabric_fpga_awid_axi_s1_o; - output [11:0] fabric_fpga_awid_axi_s2_o; - input [7:0] fabric_fpga_awlen_axi_m1_i; - input [7:0] fabric_fpga_awlen_axi_m2_i; - output [7:0] fabric_fpga_awlen_axi_s1_o; - output [7:0] fabric_fpga_awlen_axi_s2_o; - input fabric_fpga_awlock_axi_m1_i; - input fabric_fpga_awlock_axi_m2_i; - output fabric_fpga_awlock_axi_s1_o; - output fabric_fpga_awlock_axi_s2_o; - input [2:0] fabric_fpga_awprot_axi_m1_i; - input [2:0] fabric_fpga_awprot_axi_m2_i; - output [2:0] fabric_fpga_awprot_axi_s1_o; - output [2:0] fabric_fpga_awprot_axi_s2_o; - input [3:0] fabric_fpga_awqos_axi_m1_i; - input [3:0] fabric_fpga_awqos_axi_m2_i; - output [3:0] fabric_fpga_awqos_axi_s1_o; - output [3:0] fabric_fpga_awqos_axi_s2_o; - output fabric_fpga_awready_axi_m1_o; - output fabric_fpga_awready_axi_m2_o; - input fabric_fpga_awready_axi_s1_i; - input fabric_fpga_awready_axi_s2_i; - output [3:0] fabric_fpga_awregion_axi_s1_o; - output [3:0] fabric_fpga_awregion_axi_s2_o; - input [2:0] fabric_fpga_awsize_axi_m1_i; - input [2:0] fabric_fpga_awsize_axi_m2_i; - output [2:0] fabric_fpga_awsize_axi_s1_o; - output [2:0] fabric_fpga_awsize_axi_s2_o; - input fabric_fpga_awvalid_axi_m1_i; - input fabric_fpga_awvalid_axi_m2_i; - output fabric_fpga_awvalid_axi_s1_o; - output fabric_fpga_awvalid_axi_s2_o; - output [4:0] fabric_fpga_bid_axi_m1_o; - output [4:0] fabric_fpga_bid_axi_m2_o; - input [11:0] fabric_fpga_bid_axi_s1_i; - input [11:0] fabric_fpga_bid_axi_s2_i; - input fabric_fpga_bready_axi_m1_i; - input fabric_fpga_bready_axi_m2_i; - output fabric_fpga_bready_axi_s1_o; - output fabric_fpga_bready_axi_s2_o; - output [1:0] fabric_fpga_bresp_axi_m1_o; - output [1:0] fabric_fpga_bresp_axi_m2_o; - input [1:0] fabric_fpga_bresp_axi_s1_i; - input [1:0] fabric_fpga_bresp_axi_s2_i; - output fabric_fpga_bvalid_axi_m1_o; - output fabric_fpga_bvalid_axi_m2_o; - input fabric_fpga_bvalid_axi_s1_i; - input fabric_fpga_bvalid_axi_s2_i; - input [39:0] fabric_fpga_ddr0_araddr_i; - input [1:0] fabric_fpga_ddr0_arburst_i; - input [3:0] fabric_fpga_ddr0_arcache_i; - input [4:0] fabric_fpga_ddr0_arid_i; - input [7:0] fabric_fpga_ddr0_arlen_i; - input fabric_fpga_ddr0_arlock_i; - input [2:0] fabric_fpga_ddr0_arprot_i; - input [3:0] fabric_fpga_ddr0_arqos_i; - output fabric_fpga_ddr0_arready_o; - input [2:0] fabric_fpga_ddr0_arsize_i; - input fabric_fpga_ddr0_arvalid_i; - input [39:0] fabric_fpga_ddr0_awaddr_i; - input [1:0] fabric_fpga_ddr0_awburst_i; - input [3:0] fabric_fpga_ddr0_awcache_i; - input [4:0] fabric_fpga_ddr0_awid_i; - input [7:0] fabric_fpga_ddr0_awlen_i; - input fabric_fpga_ddr0_awlock_i; - input [2:0] fabric_fpga_ddr0_awprot_i; - input [3:0] fabric_fpga_ddr0_awqos_i; - output fabric_fpga_ddr0_awready_o; - input [2:0] fabric_fpga_ddr0_awsize_i; - input fabric_fpga_ddr0_awvalid_i; - output [4:0] fabric_fpga_ddr0_bid_o; - input fabric_fpga_ddr0_bready_i; - output [1:0] fabric_fpga_ddr0_bresp_o; - output fabric_fpga_ddr0_bvalid_o; - output [127:0] fabric_fpga_ddr0_rdata_o; - output [4:0] fabric_fpga_ddr0_rid_o; - output fabric_fpga_ddr0_rlast_o; - input fabric_fpga_ddr0_rready_i; - output [1:0] fabric_fpga_ddr0_rresp_o; - output fabric_fpga_ddr0_rvalid_o; - input [127:0] fabric_fpga_ddr0_wdata_i; - input fabric_fpga_ddr0_wlast_i; - output fabric_fpga_ddr0_wready_o; - input [15:0] fabric_fpga_ddr0_wstrb_i; - input fabric_fpga_ddr0_wvalid_i; - output [5:0] fabric_fpga_dma_ack_m1_o; - output [5:0] fabric_fpga_dma_ack_m2_o; - output [5:0] fabric_fpga_dma_finish_m1_o; - output [5:0] fabric_fpga_dma_finish_m2_o; - input [5:0] fabric_fpga_dma_last_m1_i; - input [5:0] fabric_fpga_dma_last_m2_i; - input [5:0] fabric_fpga_dma_req_m1_i; - input [5:0] fabric_fpga_dma_req_m2_i; - input [5:0] fabric_fpga_dma_single_m1_i; - input [5:0] fabric_fpga_dma_single_m2_i; - input [59:0] fabric_fpga_events60_i; - input [119:0] fabric_fpga_interrupt_in_i; - input [9:0] fabric_fpga_nic_rstn_i; - output [31:0] fabric_fpga_paddr_apb_o; - output fabric_fpga_penable_apb_o; - input fabric_fpga_pmrstn_i; - input [31:0] fabric_fpga_prdata_apb_i; - input fabric_fpga_pready_apb_i; - output fabric_fpga_psel_apb_o; - input fabric_fpga_pslverr_apb_i; - output [31:0] fabric_fpga_pwdata_apb_o; - output fabric_fpga_pwrite_apb_o; - output [127:0] fabric_fpga_rdata_axi_m1_o; - output [127:0] fabric_fpga_rdata_axi_m2_o; - input [127:0] fabric_fpga_rdata_axi_s1_i; - input [127:0] fabric_fpga_rdata_axi_s2_i; - output [4:0] fabric_fpga_rid_axi_m1_o; - output [4:0] fabric_fpga_rid_axi_m2_o; - input [11:0] fabric_fpga_rid_axi_s1_i; - input [11:0] fabric_fpga_rid_axi_s2_i; - output fabric_fpga_rlast_axi_m1_o; - output fabric_fpga_rlast_axi_m2_o; - input fabric_fpga_rlast_axi_s1_i; - input fabric_fpga_rlast_axi_s2_i; - input fabric_fpga_rready_axi_m1_i; - input fabric_fpga_rready_axi_m2_i; - output fabric_fpga_rready_axi_s1_o; - output fabric_fpga_rready_axi_s2_o; - output [1:0] fabric_fpga_rresp_axi_m1_o; - output [1:0] fabric_fpga_rresp_axi_m2_o; - input [1:0] fabric_fpga_rresp_axi_s1_i; - input [1:0] fabric_fpga_rresp_axi_s2_i; - output fabric_fpga_rvalid_axi_m1_o; - output fabric_fpga_rvalid_axi_m2_o; - input fabric_fpga_rvalid_axi_s1_i; - input fabric_fpga_rvalid_axi_s2_i; - input fabric_fpga_sysrstn_i; - output [7:0] fabric_fpga_trigger_in_o; - input [7:0] fabric_fpga_trigger_out_i; - input [127:0] fabric_fpga_wdata_axi_m1_i; - input [127:0] fabric_fpga_wdata_axi_m2_i; - output [127:0] fabric_fpga_wdata_axi_s1_o; - output [127:0] fabric_fpga_wdata_axi_s2_o; - input fabric_fpga_wlast_axi_m1_i; - input fabric_fpga_wlast_axi_m2_i; - output fabric_fpga_wlast_axi_s1_o; - output fabric_fpga_wlast_axi_s2_o; - output fabric_fpga_wready_axi_m1_o; - output fabric_fpga_wready_axi_m2_o; - input fabric_fpga_wready_axi_s1_i; - input fabric_fpga_wready_axi_s2_i; - input [15:0] fabric_fpga_wstrb_axi_m1_i; - input [15:0] fabric_fpga_wstrb_axi_m2_i; - output [15:0] fabric_fpga_wstrb_axi_s1_o; - output [15:0] fabric_fpga_wstrb_axi_s2_o; - input fabric_fpga_wvalid_axi_m1_i; - input fabric_fpga_wvalid_axi_m2_i; - output fabric_fpga_wvalid_axi_s1_o; - output fabric_fpga_wvalid_axi_s2_o; - output [31:0] fabric_llpp0_araddr_s_o; - output [1:0] fabric_llpp0_arburst_s_o; - output [3:0] fabric_llpp0_arcache_s_o; - output [11:0] fabric_llpp0_arid_s_o; - output [7:0] fabric_llpp0_arlen_s_o; - output fabric_llpp0_arlock_s_o; - output [2:0] fabric_llpp0_arprot_s_o; - output [3:0] fabric_llpp0_arqos_s_o; - input fabric_llpp0_arready_s_i; - output [2:0] fabric_llpp0_arsize_s_o; - output fabric_llpp0_arvalid_s_o; - output [31:0] fabric_llpp0_awaddr_s_o; - output [1:0] fabric_llpp0_awburst_s_o; - output [3:0] fabric_llpp0_awcache_s_o; - output [11:0] fabric_llpp0_awid_s_o; - output [7:0] fabric_llpp0_awlen_s_o; - output fabric_llpp0_awlock_s_o; - output [2:0] fabric_llpp0_awprot_s_o; - output [3:0] fabric_llpp0_awqos_s_o; - input fabric_llpp0_awready_s_i; - output [2:0] fabric_llpp0_awsize_s_o; - output fabric_llpp0_awvalid_s_o; - input [11:0] fabric_llpp0_bid_s_i; - output fabric_llpp0_bready_s_o; - input [1:0] fabric_llpp0_bresp_s_i; - input fabric_llpp0_bvalid_s_i; - input [31:0] fabric_llpp0_rdata_s_i; - input [11:0] fabric_llpp0_rid_s_i; - input fabric_llpp0_rlast_s_i; - output fabric_llpp0_rready_s_o; - input [1:0] fabric_llpp0_rresp_s_i; - input fabric_llpp0_rvalid_s_i; - output [31:0] fabric_llpp0_wdata_s_o; - output fabric_llpp0_wlast_s_o; - input fabric_llpp0_wready_s_i; - output [3:0] fabric_llpp0_wstrb_s_o; - output fabric_llpp0_wvalid_s_o; - output [31:0] fabric_llpp1_araddr_s_o; - output [1:0] fabric_llpp1_arburst_s_o; - output [3:0] fabric_llpp1_arcache_s_o; - output [11:0] fabric_llpp1_arid_s_o; - output [7:0] fabric_llpp1_arlen_s_o; - output fabric_llpp1_arlock_s_o; - output [2:0] fabric_llpp1_arprot_s_o; - output [3:0] fabric_llpp1_arqos_s1_o; - input fabric_llpp1_arready_s_i; - output [2:0] fabric_llpp1_arsize_s_o; - output fabric_llpp1_arvalid_s_o; - output [31:0] fabric_llpp1_awaddr_s_o; - output [1:0] fabric_llpp1_awburst_s_o; - output [3:0] fabric_llpp1_awcache_s_o; - output [11:0] fabric_llpp1_awid_s_o; - output [7:0] fabric_llpp1_awlen_s_o; - output fabric_llpp1_awlock_s_o; - output [2:0] fabric_llpp1_awprot_s_o; - output [3:0] fabric_llpp1_awqos_s_o; - input fabric_llpp1_awready_s_i; - output [2:0] fabric_llpp1_awsize_s_o; - output fabric_llpp1_awvalid_s_o; - input [11:0] fabric_llpp1_bid_s_i; - output fabric_llpp1_bready_s_o; - input [1:0] fabric_llpp1_bresp_s_i; - input fabric_llpp1_bvalid_s_i; - input [31:0] fabric_llpp1_rdata_s_i; - input [11:0] fabric_llpp1_rid_s_i; - input fabric_llpp1_rlast_s_i; - output fabric_llpp1_rready_s_o; - input [1:0] fabric_llpp1_rresp_s_i; - input fabric_llpp1_rvalid_s_i; - output [31:0] fabric_llpp1_wdata_s_o; - output fabric_llpp1_wlast_s_o; - input fabric_llpp1_wready_s_i; - output [3:0] fabric_llpp1_wstrb_s_o; - output fabric_llpp1_wvalid_s_o; - output [31:0] fabric_llpp2_araddr_s_o; - output [1:0] fabric_llpp2_arburst_s_o; - output [3:0] fabric_llpp2_arcache_s_o; - output [11:0] fabric_llpp2_arid_s_o; - output [7:0] fabric_llpp2_arlen_s_o; - output fabric_llpp2_arlock_s_o; - output [2:0] fabric_llpp2_arprot_s_o; - output [3:0] fabric_llpp2_arqos_s_o; - input fabric_llpp2_arready_s_i; - output [2:0] fabric_llpp2_arsize_s_o; - output fabric_llpp2_arvalid_s_o; - output [31:0] fabric_llpp2_awaddr_s_o; - output [1:0] fabric_llpp2_awburst_s_o; - output [3:0] fabric_llpp2_awcache_s_o; - output [11:0] fabric_llpp2_awid_s_o; - output [7:0] fabric_llpp2_awlen_s_o; - output fabric_llpp2_awlock_s_o; - output [2:0] fabric_llpp2_awprot_s_o; - output [3:0] fabric_llpp2_awqos_s_o; - input fabric_llpp2_awready_s_i; - output [2:0] fabric_llpp2_awsize_s_o; - output fabric_llpp2_awvalid_s_o; - input [11:0] fabric_llpp2_bid_s_i; - output fabric_llpp2_bready_s_o; - input [1:0] fabric_llpp2_bresp_s_i; - input fabric_llpp2_bvalid_s_i; - input [31:0] fabric_llpp2_rdata_s_i; - input [11:0] fabric_llpp2_rid_s_i; - input fabric_llpp2_rlast_s_i; - output fabric_llpp2_rready_s_o; - input [1:0] fabric_llpp2_rresp_s_i; - input fabric_llpp2_rvalid_s_i; - output [31:0] fabric_llpp2_wdata_s_o; - output fabric_llpp2_wlast_s_o; - input fabric_llpp2_wready_s_i; - output [3:0] fabric_llpp2_wstrb_s_o; - output fabric_llpp2_wvalid_s_o; - output [31:0] fabric_llpp3_araddr_s_o; - output [1:0] fabric_llpp3_arburst_s_o; - output [3:0] fabric_llpp3_arcache_s_o; - output [11:0] fabric_llpp3_arid_s_o; - output [7:0] fabric_llpp3_arlen_s_o; - output fabric_llpp3_arlock_s_o; - output [2:0] fabric_llpp3_arprot_s_o; - output [3:0] fabric_llpp3_arqos_s_o; - input fabric_llpp3_arready_s_i; - output [2:0] fabric_llpp3_arsize_s_o; - output fabric_llpp3_arvalid_s_o; - output [31:0] fabric_llpp3_awaddr_s_o; - output [1:0] fabric_llpp3_awburst_s_o; - output [3:0] fabric_llpp3_awcache_s_o; - output [11:0] fabric_llpp3_awid_s_o; - output [7:0] fabric_llpp3_awlen_s_o; - output fabric_llpp3_awlock_s_o; - output [2:0] fabric_llpp3_awprot_s_o; - output [3:0] fabric_llpp3_awqos_s_o; - input fabric_llpp3_awready_s_i; - output [2:0] fabric_llpp3_awsize_s_o; - output fabric_llpp3_awvalid_s_o; - input [11:0] fabric_llpp3_bid_s_i; - output fabric_llpp3_bready_s_o; - input [1:0] fabric_llpp3_bresp_s_i; - input fabric_llpp3_bvalid_s_i; - input [31:0] fabric_llpp3_rdata_s_i; - input [11:0] fabric_llpp3_rid_s_i; - input fabric_llpp3_rlast_s_i; - output fabric_llpp3_rready_s_o; - input [1:0] fabric_llpp3_rresp_s_i; - input fabric_llpp3_rvalid_s_i; - output [31:0] fabric_llpp3_wdata_s_o; - output fabric_llpp3_wlast_s_o; - input fabric_llpp3_wready_s_i; - output [3:0] fabric_llpp3_wstrb_s_o; - output fabric_llpp3_wvalid_s_o; - input [9:0] fabric_lowskew_i; - output [1:0] fabric_lowskew_o; - input fabric_qos_pclk_i; - input [31:0] fabric_qos_ppaddr_i; - input fabric_qos_ppenable_i; - output [31:0] fabric_qos_pprdata_o; - output fabric_qos_ppready_o; - output fabric_qos_ppslverr_o; - input [31:0] fabric_qos_ppwdata_i; - input fabric_qos_ppwrite_i; - input fabric_qos_presetn_i; - input fabric_qos_psel_i; - output fabric_soc_mon_sensor_alarm_o; - input fabric_sysc_hold_on_debug_i; - output [31:0] fabric_tnd_fpga_apb_master_paddr_o; - output fabric_tnd_fpga_apb_master_penable_o; - input [31:0] fabric_tnd_fpga_apb_master_prdata_i; - input fabric_tnd_fpga_apb_master_pready_i; - output fabric_tnd_fpga_apb_master_psel_o; - input fabric_tnd_fpga_apb_master_pslverr_i; - output [31:0] fabric_tnd_fpga_apb_master_pwdata_o; - output fabric_tnd_fpga_apb_master_pwrite_o; - input fabric_tnd_fpga_atb_master_afready_i; - output fabric_tnd_fpga_atb_master_afvalid_o; - input [3:0] fabric_tnd_fpga_atb_master_atbytes_i; - input [127:0] fabric_tnd_fpga_atb_master_atdata_i; - input [6:0] fabric_tnd_fpga_atb_master_atid_i; - output fabric_tnd_fpga_atb_master_atready_o; - input fabric_tnd_fpga_atb_master_atvalid_i; - output fabric_tnd_fpga_atb_master_syncreq_o; - output [31:0] fabric_tnd_hssl_apb_master_paddr_o; - output fabric_tnd_hssl_apb_master_penable_o; - input [31:0] fabric_tnd_hssl_apb_master_prdata_i; - input fabric_tnd_hssl_apb_master_pready_i; - output fabric_tnd_hssl_apb_master_psel_o; - input fabric_tnd_hssl_apb_master_pslverr_i; - output [31:0] fabric_tnd_hssl_apb_master_pwdata_o; - output fabric_tnd_hssl_apb_master_pwrite_o; - output fabric_tnd_hssl_atb_master_afready_o; - input fabric_tnd_hssl_atb_master_afvalid_i; - output [3:0] fabric_tnd_hssl_atb_master_atbytes_o; - output [127:0] fabric_tnd_hssl_atb_master_atdata_o; - output [6:0] fabric_tnd_hssl_atb_master_atid_o; - input fabric_tnd_hssl_atb_master_atready_i; - output fabric_tnd_hssl_atb_master_atvalid_o; - input fabric_tnd_hssl_atb_master_syncreq_i; - output fabric_tnd_hssl_flushin_o; - output fabric_tnd_hssl_trigin_o; - output fabric_tnd_trace_clk_traceoutportintf_o; - output fabric_tnd_trace_ctl_traceoutportintf_o; - output [31:0] fabric_tnd_trace_data_traceoutportintf_o; - output [6:0] fabric_tst_pll_lock_o; - output [63:0] fabric_tsvalue_tsgen_fpga_o; - output fabric_watchdog0_signal_0_o; - output fabric_watchdog0_signal_1_o; - output fabric_watchdog1_signal_0_o; - output fabric_watchdog1_signal_1_o; - output fabric_watchdog2_signal_0_o; - output fabric_watchdog2_signal_1_o; - output fabric_watchdog3_signal_0_o; - output fabric_watchdog3_signal_1_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - -(* blackbox *) -module NX_SOC_INTERFACE_WRAP(fabric_fpga_pmrstn_i, fabric_fpga_sysrstn_i, fabric_sysc_hold_on_debug_i, fabric_fpga_arlock_axi_s1_o, fabric_fpga_arvalid_axi_s1_o, fabric_fpga_awlock_axi_s1_o, fabric_fpga_bready_axi_s1_o, fabric_fpga_rready_axi_s1_o, fabric_fpga_wlast_axi_s1_o, fabric_fpga_wvalid_axi_s1_o, fabric_fpga_awvalid_axi_s1_o, fabric_fpga_arready_axi_s1_i, fabric_fpga_awready_axi_s1_i, fabric_fpga_bvalid_axi_s1_i, fabric_fpga_rlast_axi_s1_i, fabric_fpga_rvalid_axi_s1_i, fabric_fpga_wready_axi_s1_i, fabric_fpga_arlock_axi_s2_o, fabric_fpga_arvalid_axi_s2_o, fabric_fpga_awlock_axi_s2_o, fabric_fpga_bready_axi_s2_o -, fabric_fpga_rready_axi_s2_o, fabric_fpga_wlast_axi_s2_o, fabric_fpga_wvalid_axi_s2_o, fabric_fpga_awvalid_axi_s2_o, fabric_fpga_arready_axi_s2_i, fabric_fpga_awready_axi_s2_i, fabric_fpga_bvalid_axi_s2_i, fabric_fpga_rlast_axi_s2_i, fabric_fpga_rvalid_axi_s2_i, fabric_fpga_wready_axi_s2_i, fabric_fpga_arready_axi_m1_o, fabric_fpga_awready_axi_m1_o, fabric_fpga_bvalid_axi_m1_o, fabric_fpga_rlast_axi_m1_o, fabric_fpga_rvalid_axi_m1_o, fabric_fpga_wready_axi_m1_o, fabric_fpga_arlock_axi_m1_i, fabric_fpga_arvalid_axi_m1_i, fabric_fpga_awlock_axi_m1_i, fabric_fpga_awvalid_axi_m1_i, fabric_fpga_bready_axi_m1_i -, fabric_fpga_rready_axi_m1_i, fabric_fpga_wlast_axi_m1_i, fabric_fpga_wvalid_axi_m1_i, fabric_fpga_arready_axi_m2_o, fabric_fpga_awready_axi_m2_o, fabric_fpga_bvalid_axi_m2_o, fabric_fpga_rlast_axi_m2_o, fabric_fpga_rvalid_axi_m2_o, fabric_fpga_wready_axi_m2_o, fabric_fpga_arlock_axi_m2_i, fabric_fpga_arvalid_axi_m2_i, fabric_fpga_awlock_axi_m2_i, fabric_fpga_awvalid_axi_m2_i, fabric_fpga_bready_axi_m2_i, fabric_fpga_rready_axi_m2_i, fabric_fpga_wlast_axi_m2_i, fabric_fpga_wvalid_axi_m2_i, fabric_fpga_ddr0_arready_o, fabric_fpga_ddr0_awready_o, fabric_fpga_ddr0_bvalid_o, fabric_fpga_ddr0_rlast_o -, fabric_fpga_ddr0_rvalid_o, fabric_fpga_ddr0_wready_o, fabric_fpga_ddr0_arlock_i, fabric_fpga_ddr0_arvalid_i, fabric_fpga_ddr0_awlock_i, fabric_fpga_ddr0_awvalid_i, fabric_fpga_ddr0_bready_i, fabric_fpga_ddr0_rready_i, fabric_fpga_ddr0_wlast_i, fabric_fpga_ddr0_wvalid_i, fabric_fpga_penable_apb_o, fabric_fpga_psel_apb_o, fabric_fpga_pwrite_apb_o, fabric_fpga_pready_apb_i, fabric_fpga_pslverr_apb_i, fabric_llpp0_arlock_s_o, fabric_llpp0_arvalid_s_o, fabric_llpp0_awlock_s_o, fabric_llpp0_awvalid_s_o, fabric_llpp0_bready_s_o, fabric_llpp0_rready_s_o -, fabric_llpp0_wlast_s_o, fabric_llpp0_wvalid_s_o, fabric_llpp0_arready_s_i, fabric_llpp0_awready_s_i, fabric_llpp0_bvalid_s_i, fabric_llpp0_rlast_s_i, fabric_llpp0_rvalid_s_i, fabric_llpp0_wready_s_i, fabric_llpp1_arlock_s_o, fabric_llpp1_arvalid_s_o, fabric_llpp1_awlock_s_o, fabric_llpp1_awvalid_s_o, fabric_llpp1_bready_s_o, fabric_llpp1_rready_s_o, fabric_llpp1_wlast_s_o, fabric_llpp1_wvalid_s_o, fabric_llpp1_arready_s_i, fabric_llpp1_awready_s_i, fabric_llpp1_bvalid_s_i, fabric_llpp1_rlast_s_i, fabric_llpp1_rvalid_s_i -, fabric_llpp1_wready_s_i, fabric_llpp2_arlock_s_o, fabric_llpp2_arvalid_s_o, fabric_llpp2_awlock_s_o, fabric_llpp2_awvalid_s_o, fabric_llpp2_bready_s_o, fabric_llpp2_rready_s_o, fabric_llpp2_wlast_s_o, fabric_llpp2_wvalid_s_o, fabric_llpp2_arready_s_i, fabric_llpp2_awready_s_i, fabric_llpp2_bvalid_s_i, fabric_llpp2_rlast_s_i, fabric_llpp2_rvalid_s_i, fabric_llpp2_wready_s_i, fabric_llpp3_arlock_s_o, fabric_llpp3_arvalid_s_o, fabric_llpp3_awlock_s_o, fabric_llpp3_awvalid_s_o, fabric_llpp3_bready_s_o, fabric_llpp3_rready_s_o -, fabric_llpp3_wlast_s_o, fabric_llpp3_wvalid_s_o, fabric_llpp3_arready_s_i, fabric_llpp3_awready_s_i, fabric_llpp3_bvalid_s_i, fabric_llpp3_rlast_s_i, fabric_llpp3_rvalid_s_i, fabric_llpp3_wready_s_i, fabric_qos_ppready_o, fabric_qos_ppslverr_o, fabric_qos_ppenable_i, fabric_qos_ppwrite_i, fabric_qos_presetn_i, fabric_qos_psel_i, fabric_tnd_hssl_flushin_o, fabric_tnd_hssl_trigin_o, fabric_tnd_fpga_apb_master_penable_o, fabric_tnd_fpga_apb_master_psel_o, fabric_tnd_fpga_apb_master_pwrite_o, fabric_tnd_fpga_atb_master_afvalid_o, fabric_tnd_fpga_atb_master_atready_o -, fabric_tnd_fpga_atb_master_syncreq_o, fabric_tnd_hssl_apb_master_penable_o, fabric_tnd_hssl_apb_master_psel_o, fabric_tnd_hssl_apb_master_pwrite_o, fabric_tnd_hssl_atb_master_afready_o, fabric_tnd_hssl_atb_master_atvalid_o, fabric_tnd_trace_clk_traceoutportintf_o, fabric_tnd_trace_ctl_traceoutportintf_o, fabric_tnd_fpga_apb_master_pready_i, fabric_tnd_fpga_apb_master_pslverr_i, fabric_tnd_fpga_atb_master_afready_i, fabric_tnd_fpga_atb_master_atvalid_i, fabric_tnd_hssl_apb_master_pready_i, fabric_tnd_hssl_apb_master_pslverr_i, fabric_tnd_hssl_atb_master_afvalid_i, fabric_tnd_hssl_atb_master_atready_i, fabric_tnd_hssl_atb_master_syncreq_i, fabric_watchdog0_signal_0_o, fabric_watchdog0_signal_1_o, fabric_watchdog1_signal_0_o, fabric_watchdog1_signal_1_o -, fabric_watchdog2_signal_0_o, fabric_watchdog2_signal_1_o, fabric_watchdog3_signal_0_o, fabric_watchdog3_signal_1_o, fabric_soc_mon_sensor_alarm_o, fabric_erom_fpga_cpu0_dbgen_i, fabric_erom_fpga_cpu0_hiden_i, fabric_erom_fpga_cpu0_hniden_i, fabric_erom_fpga_cpu0_niden_i, fabric_erom_fpga_cpu1_dbgen_i, fabric_erom_fpga_cpu1_hiden_i, fabric_erom_fpga_cpu1_hniden_i, fabric_erom_fpga_cpu1_niden_i, fabric_erom_fpga_cpu2_dbgen_i, fabric_erom_fpga_cpu2_hiden_i, fabric_erom_fpga_cpu2_hniden_i, fabric_erom_fpga_cpu2_niden_i, fabric_erom_fpga_cpu3_dbgen_i, fabric_erom_fpga_cpu3_hiden_i, fabric_erom_fpga_cpu3_hniden_i, fabric_erom_fpga_cpu3_niden_i -, fabric_erom_fpga_cs_dbgen_i, fabric_erom_fpga_cs_niden_i, fabric_erom_fpga_cs_deviceen_i, fabric_erom_fpga_cs_rst_n_i, fabric_erom_fpga_debug_en_i, fabric_flash_irq_toggle_o, fabric_flash_irq_o, fabric_enable_TMR_i, fabric_lowskew_i, fabric_lowskew_o, fabric_fpga_nic_rstn_i, fabric_fpga_trigger_in_o, fabric_fpga_trigger_out_i, fabric_fpga_interrupt_in_i, fabric_fpga_events60_i, fabric_fpga_araddr_axi_s1_o, fabric_fpga_arburst_axi_s1_o, fabric_fpga_arcache_axi_s1_o, fabric_fpga_arid_axi_s1_o, fabric_fpga_arlen_axi_s1_o, fabric_fpga_arprot_axi_s1_o -, fabric_fpga_arqos_axi_s1_o, fabric_fpga_arregion_axi_s1_o, fabric_fpga_arsize_axi_s1_o, fabric_fpga_awaddr_axi_s1_o, fabric_fpga_awburst_axi_s1_o, fabric_fpga_awcache_axi_s1_o, fabric_fpga_awid_axi_s1_o, fabric_fpga_awlen_axi_s1_o, fabric_fpga_awprot_axi_s1_o, fabric_fpga_awqos_axi_s1_o, fabric_fpga_awregion_axi_s1_o, fabric_fpga_awsize_axi_s1_o, fabric_fpga_wdata_axi_s1_o, fabric_fpga_wstrb_axi_s1_o, fabric_fpga_bid_axi_s1_i, fabric_fpga_bresp_axi_s1_i, fabric_fpga_rdata_axi_s1_i, fabric_fpga_rid_axi_s1_i, fabric_fpga_rresp_axi_s1_i, fabric_fpga_araddr_axi_s2_o, fabric_fpga_arburst_axi_s2_o -, fabric_fpga_arcache_axi_s2_o, fabric_fpga_arid_axi_s2_o, fabric_fpga_arlen_axi_s2_o, fabric_fpga_arprot_axi_s2_o, fabric_fpga_arqos_axi_s2_o, fabric_fpga_arregion_axi_s2_o, fabric_fpga_arsize_axi_s2_o, fabric_fpga_awaddr_axi_s2_o, fabric_fpga_awburst_axi_s2_o, fabric_fpga_awcache_axi_s2_o, fabric_fpga_awid_axi_s2_o, fabric_fpga_awlen_axi_s2_o, fabric_fpga_awprot_axi_s2_o, fabric_fpga_awqos_axi_s2_o, fabric_fpga_awregion_axi_s2_o, fabric_fpga_awsize_axi_s2_o, fabric_fpga_wdata_axi_s2_o, fabric_fpga_wstrb_axi_s2_o, fabric_fpga_bid_axi_s2_i, fabric_fpga_bresp_axi_s2_i, fabric_fpga_rdata_axi_s2_i -, fabric_fpga_rid_axi_s2_i, fabric_fpga_rresp_axi_s2_i, fabric_fpga_bid_axi_m1_o, fabric_fpga_bresp_axi_m1_o, fabric_fpga_dma_ack_m1_o, fabric_fpga_dma_finish_m1_o, fabric_fpga_rdata_axi_m1_o, fabric_fpga_rid_axi_m1_o, fabric_fpga_rresp_axi_m1_o, fabric_fpga_araddr_axi_m1_i, fabric_fpga_arburst_axi_m1_i, fabric_fpga_arcache_axi_m1_i, fabric_fpga_arid_axi_m1_i, fabric_fpga_arlen_axi_m1_i, fabric_fpga_arprot_axi_m1_i, fabric_fpga_arqos_axi_m1_i, fabric_fpga_arsize_axi_m1_i, fabric_fpga_awaddr_axi_m1_i, fabric_fpga_awburst_axi_m1_i, fabric_fpga_awcache_axi_m1_i, fabric_fpga_awid_axi_m1_i -, fabric_fpga_awlen_axi_m1_i, fabric_fpga_awprot_axi_m1_i, fabric_fpga_awqos_axi_m1_i, fabric_fpga_awsize_axi_m1_i, fabric_fpga_dma_last_m1_i, fabric_fpga_dma_req_m1_i, fabric_fpga_dma_single_m1_i, fabric_fpga_wdata_axi_m1_i, fabric_fpga_wstrb_axi_m1_i, fabric_fpga_bid_axi_m2_o, fabric_fpga_bresp_axi_m2_o, fabric_fpga_dma_ack_m2_o, fabric_fpga_dma_finish_m2_o, fabric_fpga_rdata_axi_m2_o, fabric_fpga_rid_axi_m2_o, fabric_fpga_rresp_axi_m2_o, fabric_fpga_araddr_axi_m2_i, fabric_fpga_arburst_axi_m2_i, fabric_fpga_arcache_axi_m2_i, fabric_fpga_arid_axi_m2_i, fabric_fpga_arlen_axi_m2_i -, fabric_fpga_arprot_axi_m2_i, fabric_fpga_arqos_axi_m2_i, fabric_fpga_arsize_axi_m2_i, fabric_fpga_awaddr_axi_m2_i, fabric_fpga_awburst_axi_m2_i, fabric_fpga_awcache_axi_m2_i, fabric_fpga_awid_axi_m2_i, fabric_fpga_awlen_axi_m2_i, fabric_fpga_awprot_axi_m2_i, fabric_fpga_awqos_axi_m2_i, fabric_fpga_awsize_axi_m2_i, fabric_fpga_dma_last_m2_i, fabric_fpga_dma_req_m2_i, fabric_fpga_dma_single_m2_i, fabric_fpga_wdata_axi_m2_i, fabric_fpga_wstrb_axi_m2_i, fabric_fpga_ddr0_bid_o, fabric_fpga_ddr0_bresp_o, fabric_fpga_ddr0_rdata_o, fabric_fpga_ddr0_rid_o, fabric_fpga_ddr0_rresp_o -, fabric_fpga_ddr0_araddr_i, fabric_fpga_ddr0_arburst_i, fabric_fpga_ddr0_arcache_i, fabric_fpga_ddr0_arid_i, fabric_fpga_ddr0_arlen_i, fabric_fpga_ddr0_arprot_i, fabric_fpga_ddr0_arqos_i, fabric_fpga_ddr0_arsize_i, fabric_fpga_ddr0_awaddr_i, fabric_fpga_ddr0_awburst_i, fabric_fpga_ddr0_awcache_i, fabric_fpga_ddr0_awid_i, fabric_fpga_ddr0_awlen_i, fabric_fpga_ddr0_awprot_i, fabric_fpga_ddr0_awqos_i, fabric_fpga_ddr0_awsize_i, fabric_fpga_ddr0_wdata_i, fabric_fpga_ddr0_wstrb_i, fabric_fpga_paddr_apb_o, fabric_fpga_pwdata_apb_o, fabric_fpga_prdata_apb_i -, fabric_llpp0_araddr_s_o, fabric_llpp0_arburst_s_o, fabric_llpp0_arcache_s_o, fabric_llpp0_arid_s_o, fabric_llpp0_arlen_s_o, fabric_llpp0_arprot_s_o, fabric_llpp0_arqos_s_o, fabric_llpp0_arsize_s_o, fabric_llpp0_awaddr_s_o, fabric_llpp0_awburst_s_o, fabric_llpp0_awcache_s_o, fabric_llpp0_awid_s_o, fabric_llpp0_awlen_s_o, fabric_llpp0_awprot_s_o, fabric_llpp0_awqos_s_o, fabric_llpp0_awsize_s_o, fabric_llpp0_wdata_s_o, fabric_llpp0_wstrb_s_o, fabric_llpp0_bid_s_i, fabric_llpp0_bresp_s_i, fabric_llpp0_rdata_s_i -, fabric_llpp0_rid_s_i, fabric_llpp0_rresp_s_i, fabric_llpp1_araddr_s_o, fabric_llpp1_arburst_s_o, fabric_llpp1_arcache_s_o, fabric_llpp1_arid_s_o, fabric_llpp1_arlen_s_o, fabric_llpp1_arprot_s_o, fabric_llpp1_arsize_s_o, fabric_llpp1_awaddr_s_o, fabric_llpp1_awburst_s_o, fabric_llpp1_awcache_s_o, fabric_llpp1_awid_s_o, fabric_llpp1_awlen_s_o, fabric_llpp1_awprot_s_o, fabric_llpp1_awqos_s_o, fabric_llpp1_awsize_s_o, fabric_llpp1_wdata_s_o, fabric_llpp1_wstrb_s_o, fabric_llpp1_bid_s_i, fabric_llpp1_bresp_s_i -, fabric_llpp1_rdata_s_i, fabric_llpp1_rid_s_i, fabric_llpp1_rresp_s_i, fabric_llpp2_araddr_s_o, fabric_llpp2_arburst_s_o, fabric_llpp2_arcache_s_o, fabric_llpp2_arid_s_o, fabric_llpp2_arlen_s_o, fabric_llpp2_arprot_s_o, fabric_llpp2_arqos_s_o, fabric_llpp2_arsize_s_o, fabric_llpp2_awaddr_s_o, fabric_llpp2_awburst_s_o, fabric_llpp2_awcache_s_o, fabric_llpp2_awid_s_o, fabric_llpp2_awlen_s_o, fabric_llpp2_awprot_s_o, fabric_llpp2_awqos_s_o, fabric_llpp2_awsize_s_o, fabric_llpp2_wdata_s_o, fabric_llpp2_wstrb_s_o -, fabric_llpp2_bid_s_i, fabric_llpp2_bresp_s_i, fabric_llpp2_rdata_s_i, fabric_llpp2_rid_s_i, fabric_llpp2_rresp_s_i, fabric_llpp3_araddr_s_o, fabric_llpp3_arburst_s_o, fabric_llpp3_arcache_s_o, fabric_llpp3_arid_s_o, fabric_llpp3_arlen_s_o, fabric_llpp3_arprot_s_o, fabric_llpp3_arqos_s_o, fabric_llpp3_arsize_s_o, fabric_llpp3_awaddr_s_o, fabric_llpp3_awburst_s_o, fabric_llpp3_awcache_s_o, fabric_llpp3_awid_s_o, fabric_llpp3_awlen_s_o, fabric_llpp3_awprot_s_o, fabric_llpp3_awqos_s_o, fabric_llpp3_awsize_s_o -, fabric_llpp3_wdata_s_o, fabric_llpp3_wstrb_s_o, fabric_llpp3_bid_s_i, fabric_llpp3_bresp_s_i, fabric_llpp3_rdata_s_i, fabric_llpp3_rid_s_i, fabric_llpp3_rresp_s_i, fabric_qos_pprdata_o, fabric_qos_ppaddr_i, fabric_qos_ppwdata_i, fabric_tnd_fpga_apb_master_paddr_o, fabric_tnd_fpga_apb_master_pwdata_o, fabric_tnd_hssl_apb_master_paddr_o, fabric_tnd_hssl_apb_master_pwdata_o, fabric_tnd_hssl_atb_master_atbytes_o, fabric_tnd_hssl_atb_master_atdata_o, fabric_tnd_hssl_atb_master_atid_o, fabric_tnd_trace_data_traceoutportintf_o, fabric_tsvalue_tsgen_fpga_o, fabric_tnd_fpga_apb_master_prdata_i, fabric_tnd_fpga_atb_master_atbytes_i -, fabric_tnd_fpga_atb_master_atdata_i, fabric_tnd_fpga_atb_master_atid_i, fabric_tnd_hssl_apb_master_prdata_i, fabric_tst_pll_lock_o, fabric_llpp1_arqos_s_o, fabric_spw_interrupts_toggle_o, fabric_spw_interrupts_o, fabric_fpga_dma_hs_rstn_i); - input [2:0] fabric_enable_TMR_i; - input fabric_erom_fpga_cpu0_dbgen_i; - input fabric_erom_fpga_cpu0_hiden_i; - input fabric_erom_fpga_cpu0_hniden_i; - input fabric_erom_fpga_cpu0_niden_i; - input fabric_erom_fpga_cpu1_dbgen_i; - input fabric_erom_fpga_cpu1_hiden_i; - input fabric_erom_fpga_cpu1_hniden_i; - input fabric_erom_fpga_cpu1_niden_i; - input fabric_erom_fpga_cpu2_dbgen_i; - input fabric_erom_fpga_cpu2_hiden_i; - input fabric_erom_fpga_cpu2_hniden_i; - input fabric_erom_fpga_cpu2_niden_i; - input fabric_erom_fpga_cpu3_dbgen_i; - input fabric_erom_fpga_cpu3_hiden_i; - input fabric_erom_fpga_cpu3_hniden_i; - input fabric_erom_fpga_cpu3_niden_i; - input fabric_erom_fpga_cs_dbgen_i; - input fabric_erom_fpga_cs_deviceen_i; - input fabric_erom_fpga_cs_niden_i; - input fabric_erom_fpga_cs_rst_n_i; - input fabric_erom_fpga_debug_en_i; - output fabric_flash_irq_o; - output fabric_flash_irq_toggle_o; - input [39:0] fabric_fpga_araddr_axi_m1_i; - input [39:0] fabric_fpga_araddr_axi_m2_i; - output [39:0] fabric_fpga_araddr_axi_s1_o; - output [39:0] fabric_fpga_araddr_axi_s2_o; - input [1:0] fabric_fpga_arburst_axi_m1_i; - input [1:0] fabric_fpga_arburst_axi_m2_i; - output [1:0] fabric_fpga_arburst_axi_s1_o; - output [1:0] fabric_fpga_arburst_axi_s2_o; - input [3:0] fabric_fpga_arcache_axi_m1_i; - input [3:0] fabric_fpga_arcache_axi_m2_i; - output [3:0] fabric_fpga_arcache_axi_s1_o; - output [3:0] fabric_fpga_arcache_axi_s2_o; - input [4:0] fabric_fpga_arid_axi_m1_i; - input [4:0] fabric_fpga_arid_axi_m2_i; - output [11:0] fabric_fpga_arid_axi_s1_o; - output [11:0] fabric_fpga_arid_axi_s2_o; - input [7:0] fabric_fpga_arlen_axi_m1_i; - input [7:0] fabric_fpga_arlen_axi_m2_i; - output [7:0] fabric_fpga_arlen_axi_s1_o; - output [7:0] fabric_fpga_arlen_axi_s2_o; - input fabric_fpga_arlock_axi_m1_i; - input fabric_fpga_arlock_axi_m2_i; - output fabric_fpga_arlock_axi_s1_o; - output fabric_fpga_arlock_axi_s2_o; - input [2:0] fabric_fpga_arprot_axi_m1_i; - input [2:0] fabric_fpga_arprot_axi_m2_i; - output [2:0] fabric_fpga_arprot_axi_s1_o; - output [2:0] fabric_fpga_arprot_axi_s2_o; - input [3:0] fabric_fpga_arqos_axi_m1_i; - input [3:0] fabric_fpga_arqos_axi_m2_i; - output [3:0] fabric_fpga_arqos_axi_s1_o; - output [3:0] fabric_fpga_arqos_axi_s2_o; - output fabric_fpga_arready_axi_m1_o; - output fabric_fpga_arready_axi_m2_o; - input fabric_fpga_arready_axi_s1_i; - input fabric_fpga_arready_axi_s2_i; - output [3:0] fabric_fpga_arregion_axi_s1_o; - output [3:0] fabric_fpga_arregion_axi_s2_o; - input [2:0] fabric_fpga_arsize_axi_m1_i; - input [2:0] fabric_fpga_arsize_axi_m2_i; - output [2:0] fabric_fpga_arsize_axi_s1_o; - output [2:0] fabric_fpga_arsize_axi_s2_o; - input fabric_fpga_arvalid_axi_m1_i; - input fabric_fpga_arvalid_axi_m2_i; - output fabric_fpga_arvalid_axi_s1_o; - output fabric_fpga_arvalid_axi_s2_o; - input [39:0] fabric_fpga_awaddr_axi_m1_i; - input [39:0] fabric_fpga_awaddr_axi_m2_i; - output [39:0] fabric_fpga_awaddr_axi_s1_o; - output [39:0] fabric_fpga_awaddr_axi_s2_o; - input [1:0] fabric_fpga_awburst_axi_m1_i; - input [1:0] fabric_fpga_awburst_axi_m2_i; - output [1:0] fabric_fpga_awburst_axi_s1_o; - output [1:0] fabric_fpga_awburst_axi_s2_o; - input [3:0] fabric_fpga_awcache_axi_m1_i; - input [3:0] fabric_fpga_awcache_axi_m2_i; - output [3:0] fabric_fpga_awcache_axi_s1_o; - output [3:0] fabric_fpga_awcache_axi_s2_o; - input [4:0] fabric_fpga_awid_axi_m1_i; - input [4:0] fabric_fpga_awid_axi_m2_i; - output [11:0] fabric_fpga_awid_axi_s1_o; - output [11:0] fabric_fpga_awid_axi_s2_o; - input [7:0] fabric_fpga_awlen_axi_m1_i; - input [7:0] fabric_fpga_awlen_axi_m2_i; - output [7:0] fabric_fpga_awlen_axi_s1_o; - output [7:0] fabric_fpga_awlen_axi_s2_o; - input fabric_fpga_awlock_axi_m1_i; - input fabric_fpga_awlock_axi_m2_i; - output fabric_fpga_awlock_axi_s1_o; - output fabric_fpga_awlock_axi_s2_o; - input [2:0] fabric_fpga_awprot_axi_m1_i; - input [2:0] fabric_fpga_awprot_axi_m2_i; - output [2:0] fabric_fpga_awprot_axi_s1_o; - output [2:0] fabric_fpga_awprot_axi_s2_o; - input [3:0] fabric_fpga_awqos_axi_m1_i; - input [3:0] fabric_fpga_awqos_axi_m2_i; - output [3:0] fabric_fpga_awqos_axi_s1_o; - output [3:0] fabric_fpga_awqos_axi_s2_o; - output fabric_fpga_awready_axi_m1_o; - output fabric_fpga_awready_axi_m2_o; - input fabric_fpga_awready_axi_s1_i; - input fabric_fpga_awready_axi_s2_i; - output [3:0] fabric_fpga_awregion_axi_s1_o; - output [3:0] fabric_fpga_awregion_axi_s2_o; - input [2:0] fabric_fpga_awsize_axi_m1_i; - input [2:0] fabric_fpga_awsize_axi_m2_i; - output [2:0] fabric_fpga_awsize_axi_s1_o; - output [2:0] fabric_fpga_awsize_axi_s2_o; - input fabric_fpga_awvalid_axi_m1_i; - input fabric_fpga_awvalid_axi_m2_i; - output fabric_fpga_awvalid_axi_s1_o; - output fabric_fpga_awvalid_axi_s2_o; - output [4:0] fabric_fpga_bid_axi_m1_o; - output [4:0] fabric_fpga_bid_axi_m2_o; - input [11:0] fabric_fpga_bid_axi_s1_i; - input [11:0] fabric_fpga_bid_axi_s2_i; - input fabric_fpga_bready_axi_m1_i; - input fabric_fpga_bready_axi_m2_i; - output fabric_fpga_bready_axi_s1_o; - output fabric_fpga_bready_axi_s2_o; - output [1:0] fabric_fpga_bresp_axi_m1_o; - output [1:0] fabric_fpga_bresp_axi_m2_o; - input [1:0] fabric_fpga_bresp_axi_s1_i; - input [1:0] fabric_fpga_bresp_axi_s2_i; - output fabric_fpga_bvalid_axi_m1_o; - output fabric_fpga_bvalid_axi_m2_o; - input fabric_fpga_bvalid_axi_s1_i; - input fabric_fpga_bvalid_axi_s2_i; - input [39:0] fabric_fpga_ddr0_araddr_i; - input [1:0] fabric_fpga_ddr0_arburst_i; - input [3:0] fabric_fpga_ddr0_arcache_i; - input [4:0] fabric_fpga_ddr0_arid_i; - input [7:0] fabric_fpga_ddr0_arlen_i; - input fabric_fpga_ddr0_arlock_i; - input [2:0] fabric_fpga_ddr0_arprot_i; - input [3:0] fabric_fpga_ddr0_arqos_i; - output fabric_fpga_ddr0_arready_o; - input [2:0] fabric_fpga_ddr0_arsize_i; - input fabric_fpga_ddr0_arvalid_i; - input [39:0] fabric_fpga_ddr0_awaddr_i; - input [1:0] fabric_fpga_ddr0_awburst_i; - input [3:0] fabric_fpga_ddr0_awcache_i; - input [4:0] fabric_fpga_ddr0_awid_i; - input [7:0] fabric_fpga_ddr0_awlen_i; - input fabric_fpga_ddr0_awlock_i; - input [2:0] fabric_fpga_ddr0_awprot_i; - input [3:0] fabric_fpga_ddr0_awqos_i; - output fabric_fpga_ddr0_awready_o; - input [2:0] fabric_fpga_ddr0_awsize_i; - input fabric_fpga_ddr0_awvalid_i; - output [4:0] fabric_fpga_ddr0_bid_o; - input fabric_fpga_ddr0_bready_i; - output [1:0] fabric_fpga_ddr0_bresp_o; - output fabric_fpga_ddr0_bvalid_o; - output [127:0] fabric_fpga_ddr0_rdata_o; - output [4:0] fabric_fpga_ddr0_rid_o; - output fabric_fpga_ddr0_rlast_o; - input fabric_fpga_ddr0_rready_i; - output [1:0] fabric_fpga_ddr0_rresp_o; - output fabric_fpga_ddr0_rvalid_o; - input [127:0] fabric_fpga_ddr0_wdata_i; - input fabric_fpga_ddr0_wlast_i; - output fabric_fpga_ddr0_wready_o; - input [15:0] fabric_fpga_ddr0_wstrb_i; - input fabric_fpga_ddr0_wvalid_i; - output [5:0] fabric_fpga_dma_ack_m1_o; - output [5:0] fabric_fpga_dma_ack_m2_o; - output [5:0] fabric_fpga_dma_finish_m1_o; - output [5:0] fabric_fpga_dma_finish_m2_o; - input [5:0] fabric_fpga_dma_hs_rstn_i; - input [5:0] fabric_fpga_dma_last_m1_i; - input [5:0] fabric_fpga_dma_last_m2_i; - input [5:0] fabric_fpga_dma_req_m1_i; - input [5:0] fabric_fpga_dma_req_m2_i; - input [5:0] fabric_fpga_dma_single_m1_i; - input [5:0] fabric_fpga_dma_single_m2_i; - input [59:0] fabric_fpga_events60_i; - input [119:0] fabric_fpga_interrupt_in_i; - input [9:0] fabric_fpga_nic_rstn_i; - output [31:0] fabric_fpga_paddr_apb_o; - output fabric_fpga_penable_apb_o; - input fabric_fpga_pmrstn_i; - input [31:0] fabric_fpga_prdata_apb_i; - input fabric_fpga_pready_apb_i; - output fabric_fpga_psel_apb_o; - input fabric_fpga_pslverr_apb_i; - output [31:0] fabric_fpga_pwdata_apb_o; - output fabric_fpga_pwrite_apb_o; - output [127:0] fabric_fpga_rdata_axi_m1_o; - output [127:0] fabric_fpga_rdata_axi_m2_o; - input [127:0] fabric_fpga_rdata_axi_s1_i; - input [127:0] fabric_fpga_rdata_axi_s2_i; - output [4:0] fabric_fpga_rid_axi_m1_o; - output [4:0] fabric_fpga_rid_axi_m2_o; - input [11:0] fabric_fpga_rid_axi_s1_i; - input [11:0] fabric_fpga_rid_axi_s2_i; - output fabric_fpga_rlast_axi_m1_o; - output fabric_fpga_rlast_axi_m2_o; - input fabric_fpga_rlast_axi_s1_i; - input fabric_fpga_rlast_axi_s2_i; - input fabric_fpga_rready_axi_m1_i; - input fabric_fpga_rready_axi_m2_i; - output fabric_fpga_rready_axi_s1_o; - output fabric_fpga_rready_axi_s2_o; - output [1:0] fabric_fpga_rresp_axi_m1_o; - output [1:0] fabric_fpga_rresp_axi_m2_o; - input [1:0] fabric_fpga_rresp_axi_s1_i; - input [1:0] fabric_fpga_rresp_axi_s2_i; - output fabric_fpga_rvalid_axi_m1_o; - output fabric_fpga_rvalid_axi_m2_o; - input fabric_fpga_rvalid_axi_s1_i; - input fabric_fpga_rvalid_axi_s2_i; - input fabric_fpga_sysrstn_i; - output [7:0] fabric_fpga_trigger_in_o; - input [7:0] fabric_fpga_trigger_out_i; - input [127:0] fabric_fpga_wdata_axi_m1_i; - input [127:0] fabric_fpga_wdata_axi_m2_i; - output [127:0] fabric_fpga_wdata_axi_s1_o; - output [127:0] fabric_fpga_wdata_axi_s2_o; - input fabric_fpga_wlast_axi_m1_i; - input fabric_fpga_wlast_axi_m2_i; - output fabric_fpga_wlast_axi_s1_o; - output fabric_fpga_wlast_axi_s2_o; - output fabric_fpga_wready_axi_m1_o; - output fabric_fpga_wready_axi_m2_o; - input fabric_fpga_wready_axi_s1_i; - input fabric_fpga_wready_axi_s2_i; - input [15:0] fabric_fpga_wstrb_axi_m1_i; - input [15:0] fabric_fpga_wstrb_axi_m2_i; - output [15:0] fabric_fpga_wstrb_axi_s1_o; - output [15:0] fabric_fpga_wstrb_axi_s2_o; - input fabric_fpga_wvalid_axi_m1_i; - input fabric_fpga_wvalid_axi_m2_i; - output fabric_fpga_wvalid_axi_s1_o; - output fabric_fpga_wvalid_axi_s2_o; - output [31:0] fabric_llpp0_araddr_s_o; - output [1:0] fabric_llpp0_arburst_s_o; - output [3:0] fabric_llpp0_arcache_s_o; - output [11:0] fabric_llpp0_arid_s_o; - output [7:0] fabric_llpp0_arlen_s_o; - output fabric_llpp0_arlock_s_o; - output [2:0] fabric_llpp0_arprot_s_o; - output [3:0] fabric_llpp0_arqos_s_o; - input fabric_llpp0_arready_s_i; - output [2:0] fabric_llpp0_arsize_s_o; - output fabric_llpp0_arvalid_s_o; - output [31:0] fabric_llpp0_awaddr_s_o; - output [1:0] fabric_llpp0_awburst_s_o; - output [3:0] fabric_llpp0_awcache_s_o; - output [11:0] fabric_llpp0_awid_s_o; - output [7:0] fabric_llpp0_awlen_s_o; - output fabric_llpp0_awlock_s_o; - output [2:0] fabric_llpp0_awprot_s_o; - output [3:0] fabric_llpp0_awqos_s_o; - input fabric_llpp0_awready_s_i; - output [2:0] fabric_llpp0_awsize_s_o; - output fabric_llpp0_awvalid_s_o; - input [11:0] fabric_llpp0_bid_s_i; - output fabric_llpp0_bready_s_o; - input [1:0] fabric_llpp0_bresp_s_i; - input fabric_llpp0_bvalid_s_i; - input [31:0] fabric_llpp0_rdata_s_i; - input [11:0] fabric_llpp0_rid_s_i; - input fabric_llpp0_rlast_s_i; - output fabric_llpp0_rready_s_o; - input [1:0] fabric_llpp0_rresp_s_i; - input fabric_llpp0_rvalid_s_i; - output [31:0] fabric_llpp0_wdata_s_o; - output fabric_llpp0_wlast_s_o; - input fabric_llpp0_wready_s_i; - output [3:0] fabric_llpp0_wstrb_s_o; - output fabric_llpp0_wvalid_s_o; - output [31:0] fabric_llpp1_araddr_s_o; - output [1:0] fabric_llpp1_arburst_s_o; - output [3:0] fabric_llpp1_arcache_s_o; - output [11:0] fabric_llpp1_arid_s_o; - output [7:0] fabric_llpp1_arlen_s_o; - output fabric_llpp1_arlock_s_o; - output [2:0] fabric_llpp1_arprot_s_o; - output [3:0] fabric_llpp1_arqos_s_o; - input fabric_llpp1_arready_s_i; - output [2:0] fabric_llpp1_arsize_s_o; - output fabric_llpp1_arvalid_s_o; - output [31:0] fabric_llpp1_awaddr_s_o; - output [1:0] fabric_llpp1_awburst_s_o; - output [3:0] fabric_llpp1_awcache_s_o; - output [11:0] fabric_llpp1_awid_s_o; - output [7:0] fabric_llpp1_awlen_s_o; - output fabric_llpp1_awlock_s_o; - output [2:0] fabric_llpp1_awprot_s_o; - output [3:0] fabric_llpp1_awqos_s_o; - input fabric_llpp1_awready_s_i; - output [2:0] fabric_llpp1_awsize_s_o; - output fabric_llpp1_awvalid_s_o; - input [11:0] fabric_llpp1_bid_s_i; - output fabric_llpp1_bready_s_o; - input [1:0] fabric_llpp1_bresp_s_i; - input fabric_llpp1_bvalid_s_i; - input [31:0] fabric_llpp1_rdata_s_i; - input [11:0] fabric_llpp1_rid_s_i; - input fabric_llpp1_rlast_s_i; - output fabric_llpp1_rready_s_o; - input [1:0] fabric_llpp1_rresp_s_i; - input fabric_llpp1_rvalid_s_i; - output [31:0] fabric_llpp1_wdata_s_o; - output fabric_llpp1_wlast_s_o; - input fabric_llpp1_wready_s_i; - output [3:0] fabric_llpp1_wstrb_s_o; - output fabric_llpp1_wvalid_s_o; - output [31:0] fabric_llpp2_araddr_s_o; - output [1:0] fabric_llpp2_arburst_s_o; - output [3:0] fabric_llpp2_arcache_s_o; - output [11:0] fabric_llpp2_arid_s_o; - output [7:0] fabric_llpp2_arlen_s_o; - output fabric_llpp2_arlock_s_o; - output [2:0] fabric_llpp2_arprot_s_o; - output [3:0] fabric_llpp2_arqos_s_o; - input fabric_llpp2_arready_s_i; - output [2:0] fabric_llpp2_arsize_s_o; - output fabric_llpp2_arvalid_s_o; - output [31:0] fabric_llpp2_awaddr_s_o; - output [1:0] fabric_llpp2_awburst_s_o; - output [3:0] fabric_llpp2_awcache_s_o; - output [11:0] fabric_llpp2_awid_s_o; - output [7:0] fabric_llpp2_awlen_s_o; - output fabric_llpp2_awlock_s_o; - output [2:0] fabric_llpp2_awprot_s_o; - output [3:0] fabric_llpp2_awqos_s_o; - input fabric_llpp2_awready_s_i; - output [2:0] fabric_llpp2_awsize_s_o; - output fabric_llpp2_awvalid_s_o; - input [11:0] fabric_llpp2_bid_s_i; - output fabric_llpp2_bready_s_o; - input [1:0] fabric_llpp2_bresp_s_i; - input fabric_llpp2_bvalid_s_i; - input [31:0] fabric_llpp2_rdata_s_i; - input [11:0] fabric_llpp2_rid_s_i; - input fabric_llpp2_rlast_s_i; - output fabric_llpp2_rready_s_o; - input [1:0] fabric_llpp2_rresp_s_i; - input fabric_llpp2_rvalid_s_i; - output [31:0] fabric_llpp2_wdata_s_o; - output fabric_llpp2_wlast_s_o; - input fabric_llpp2_wready_s_i; - output [3:0] fabric_llpp2_wstrb_s_o; - output fabric_llpp2_wvalid_s_o; - output [31:0] fabric_llpp3_araddr_s_o; - output [1:0] fabric_llpp3_arburst_s_o; - output [3:0] fabric_llpp3_arcache_s_o; - output [11:0] fabric_llpp3_arid_s_o; - output [7:0] fabric_llpp3_arlen_s_o; - output fabric_llpp3_arlock_s_o; - output [2:0] fabric_llpp3_arprot_s_o; - output [3:0] fabric_llpp3_arqos_s_o; - input fabric_llpp3_arready_s_i; - output [2:0] fabric_llpp3_arsize_s_o; - output fabric_llpp3_arvalid_s_o; - output [31:0] fabric_llpp3_awaddr_s_o; - output [1:0] fabric_llpp3_awburst_s_o; - output [3:0] fabric_llpp3_awcache_s_o; - output [11:0] fabric_llpp3_awid_s_o; - output [7:0] fabric_llpp3_awlen_s_o; - output fabric_llpp3_awlock_s_o; - output [2:0] fabric_llpp3_awprot_s_o; - output [3:0] fabric_llpp3_awqos_s_o; - input fabric_llpp3_awready_s_i; - output [2:0] fabric_llpp3_awsize_s_o; - output fabric_llpp3_awvalid_s_o; - input [11:0] fabric_llpp3_bid_s_i; - output fabric_llpp3_bready_s_o; - input [1:0] fabric_llpp3_bresp_s_i; - input fabric_llpp3_bvalid_s_i; - input [31:0] fabric_llpp3_rdata_s_i; - input [11:0] fabric_llpp3_rid_s_i; - input fabric_llpp3_rlast_s_i; - output fabric_llpp3_rready_s_o; - input [1:0] fabric_llpp3_rresp_s_i; - input fabric_llpp3_rvalid_s_i; - output [31:0] fabric_llpp3_wdata_s_o; - output fabric_llpp3_wlast_s_o; - input fabric_llpp3_wready_s_i; - output [3:0] fabric_llpp3_wstrb_s_o; - output fabric_llpp3_wvalid_s_o; - input [18:2] fabric_lowskew_i; - output [1:0] fabric_lowskew_o; - input [31:0] fabric_qos_ppaddr_i; - input fabric_qos_ppenable_i; - output [31:0] fabric_qos_pprdata_o; - output fabric_qos_ppready_o; - output fabric_qos_ppslverr_o; - input [31:0] fabric_qos_ppwdata_i; - input fabric_qos_ppwrite_i; - input fabric_qos_presetn_i; - input fabric_qos_psel_i; - output fabric_soc_mon_sensor_alarm_o; - output [2:0] fabric_spw_interrupts_o; - output [2:0] fabric_spw_interrupts_toggle_o; - input fabric_sysc_hold_on_debug_i; - output [31:0] fabric_tnd_fpga_apb_master_paddr_o; - output fabric_tnd_fpga_apb_master_penable_o; - input [31:0] fabric_tnd_fpga_apb_master_prdata_i; - input fabric_tnd_fpga_apb_master_pready_i; - output fabric_tnd_fpga_apb_master_psel_o; - input fabric_tnd_fpga_apb_master_pslverr_i; - output [31:0] fabric_tnd_fpga_apb_master_pwdata_o; - output fabric_tnd_fpga_apb_master_pwrite_o; - input fabric_tnd_fpga_atb_master_afready_i; - output fabric_tnd_fpga_atb_master_afvalid_o; - input [3:0] fabric_tnd_fpga_atb_master_atbytes_i; - input [127:0] fabric_tnd_fpga_atb_master_atdata_i; - input [6:0] fabric_tnd_fpga_atb_master_atid_i; - output fabric_tnd_fpga_atb_master_atready_o; - input fabric_tnd_fpga_atb_master_atvalid_i; - output fabric_tnd_fpga_atb_master_syncreq_o; - output [31:0] fabric_tnd_hssl_apb_master_paddr_o; - output fabric_tnd_hssl_apb_master_penable_o; - input [31:0] fabric_tnd_hssl_apb_master_prdata_i; - input fabric_tnd_hssl_apb_master_pready_i; - output fabric_tnd_hssl_apb_master_psel_o; - input fabric_tnd_hssl_apb_master_pslverr_i; - output [31:0] fabric_tnd_hssl_apb_master_pwdata_o; - output fabric_tnd_hssl_apb_master_pwrite_o; - output fabric_tnd_hssl_atb_master_afready_o; - input fabric_tnd_hssl_atb_master_afvalid_i; - output [3:0] fabric_tnd_hssl_atb_master_atbytes_o; - output [127:0] fabric_tnd_hssl_atb_master_atdata_o; - output [6:0] fabric_tnd_hssl_atb_master_atid_o; - input fabric_tnd_hssl_atb_master_atready_i; - output fabric_tnd_hssl_atb_master_atvalid_o; - input fabric_tnd_hssl_atb_master_syncreq_i; - output fabric_tnd_hssl_flushin_o; - output fabric_tnd_hssl_trigin_o; - output fabric_tnd_trace_clk_traceoutportintf_o; - output fabric_tnd_trace_ctl_traceoutportintf_o; - output [31:0] fabric_tnd_trace_data_traceoutportintf_o; - output [6:0] fabric_tst_pll_lock_o; - output [63:0] fabric_tsvalue_tsgen_fpga_o; - output fabric_watchdog0_signal_0_o; - output fabric_watchdog0_signal_1_o; - output fabric_watchdog1_signal_0_o; - output fabric_watchdog1_signal_1_o; - output fabric_watchdog2_signal_0_o; - output fabric_watchdog2_signal_1_o; - output fabric_watchdog3_signal_0_o; - output fabric_watchdog3_signal_1_o; - parameter ahb_config = 0; - parameter bsm_config = 0; -endmodule - (* blackbox *) module NX_WFG(SI, ZI, RDY, SO, ZO); input RDY; From 827ea115037a975d9e7c8c3d2afa2878b814b3c9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Mar 2024 13:03:20 +0100 Subject: [PATCH 019/342] start splitting blackboxes and add wrapper techmap --- techlibs/nanoxplore/Makefile.inc | 6 +++++ techlibs/nanoxplore/cells_bb.v | 26 ------------------- techlibs/nanoxplore/cells_bb_l.v | 0 techlibs/nanoxplore/cells_bb_m.v | 0 techlibs/nanoxplore/cells_bb_u.v | 10 ++++++++ techlibs/nanoxplore/cells_wrap_l.v | 0 techlibs/nanoxplore/cells_wrap_m.v | 0 techlibs/nanoxplore/cells_wrap_u.v | 34 +++++++++++++++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 17 ++++++++++++- 9 files changed, 66 insertions(+), 27 deletions(-) create mode 100644 techlibs/nanoxplore/cells_bb_l.v create mode 100644 techlibs/nanoxplore/cells_bb_m.v create mode 100644 techlibs/nanoxplore/cells_bb_u.v create mode 100644 techlibs/nanoxplore/cells_wrap_l.v create mode 100644 techlibs/nanoxplore/cells_wrap_m.v create mode 100644 techlibs/nanoxplore/cells_wrap_u.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 030cabd64..37755106b 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -4,7 +4,13 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 01fc0e3f3..0ff721121 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -419,21 +419,6 @@ module NX_CKS(CKI, CMD, CKO); parameter ck_edge = 1'b0; endmodule -(* blackbox *) -module NX_CKS_U(CKI, CMD, CKO); - input CKI; - output CKO; - input CMD; -endmodule - -(* blackbox *) -module NX_CMUX_U(CKI0, CKI1, SEL, CKO); - input CKI0; - input CKI1; - output CKO; - input SEL; -endmodule - (* blackbox *) module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 @@ -2839,17 +2824,6 @@ module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11 parameter wck_edge = 1'b0; endmodule -(* blackbox *) -module NX_GCK_U(SI1, SI2, CMD, SO); - input CMD; - input SI1; - input SI2; - output SO; - parameter inv_in = 1'b0; - parameter inv_out = 1'b0; - parameter std_mode = "BYPASS"; -endmodule - (* blackbox *) module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v new file mode 100644 index 000000000..41f8736fc --- /dev/null +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -0,0 +1,10 @@ +(* blackbox *) +module NX_GCK_U(SI1, SI2, CMD, SO); + input CMD; + input SI1; + input SI2; + output SO; + parameter inv_in = 1'b0; + parameter inv_out = 1'b0; + parameter std_mode = "BYPASS"; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v new file mode 100644 index 000000000..e8f793612 --- /dev/null +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -0,0 +1,34 @@ +module NX_CKS_U(CKI, CMD, CKO); + input CKI; + output CKO; + input CMD; + +NX_GCK_U #( + .inv_in(1'b0), + .inv_out(1'b0), + .std_mode("CKS") +) _TECHMAP_REPLACE_ ( + .CMD(CMD), + .SI1(CKI), + .SI2(1'b0), + .SO(CKO) +); +endmodule + +module NX_CMUX_U(CKI0, CKI1, SEL, CKO); + input CKI0; + input CKI1; + output CKO; + input SEL; + +NX_GCK_U #( + .inv_in(1'b0), + .inv_out(1'b0), + .std_mode("MUX") +) _TECHMAP_REPLACE_ ( + .CMD(SEL), + .SI1(CKI0), + .SI2(CKI1), + .SO(CKO) +); +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 75168adcc..2a8f48729 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -93,6 +93,7 @@ struct SynthNanoXplorePass : public ScriptPass string top_opt, json_file, family; bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad; + std::string postfix; void clear_flags() override { @@ -106,6 +107,7 @@ struct SynthNanoXplorePass : public ScriptPass nobram = false; nodsp = false; iopad = false; + postfix = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -175,8 +177,20 @@ struct SynthNanoXplorePass : public ScriptPass if (family.empty()) { //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; + postfix = "_u"; } + if (family == "ultra") { + postfix = "_u"; + } else if (family == "u300") { + postfix = "_u"; + } else if (family == "medium") { + postfix = "_m"; + } else if (family == "large") { + postfix = "_l"; + } else + log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); + if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -192,7 +206,8 @@ struct SynthNanoXplorePass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v"); + run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); + run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } From 815622f6853a911ce81390773a1ef2ab55117196 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Mar 2024 13:58:15 +0100 Subject: [PATCH 020/342] CDC_L wrappers --- techlibs/nanoxplore/cells_bb.v | 170 --------------- techlibs/nanoxplore/cells_bb_l.v | 86 ++++++++ techlibs/nanoxplore/cells_bb_m.v | 8 + techlibs/nanoxplore/cells_wrap_l.v | 335 +++++++++++++++++++++++++++++ 4 files changed, 429 insertions(+), 170 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 0ff721121..2a3d8b62f 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -70,168 +70,6 @@ module NX_BFR(I, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1 -, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4 -, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6); - input AI1; - input AI2; - input AI3; - input AI4; - input AI5; - input AI6; - output AO1; - output AO2; - output AO3; - output AO4; - output AO5; - output AO6; - input BI1; - input BI2; - input BI3; - input BI4; - input BI5; - input BI6; - output BO1; - output BO2; - output BO3; - output BO4; - output BO5; - output BO6; - input CI1; - input CI2; - input CI3; - input CI4; - input CI5; - input CI6; - input CK1; - input CK2; - output CO1; - output CO2; - output CO3; - output CO4; - output CO5; - output CO6; - input DI1; - input DI2; - input DI3; - input DI4; - input DI5; - input DI6; - output DO1; - output DO2; - output DO3; - output DO4; - output DO5; - output DO6; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter cck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter dck_sel = 1'b0; - parameter gt0_bypass_reg1 = 1'b0; - parameter gt0_bypass_reg2 = 1'b0; - parameter gt1_bypass_reg1 = 1'b0; - parameter gt1_bypass_reg2 = 1'b0; - parameter link_BA = 1'b0; - parameter link_CB = 1'b0; - parameter link_DC = 1'b0; - parameter mode = 0; - parameter use_adest_arst = 2'b00; - parameter use_asrc_arst = 2'b00; - parameter use_bdest_arst = 2'b00; - parameter use_bsrc_arst = 2'b00; - parameter use_cdest_arst = 2'b00; - parameter use_csrc_arst = 2'b00; - parameter use_ddest_arst = 2'b00; - parameter use_dsrc_arst = 2'b00; -endmodule - -(* blackbox *) -module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI); - input ADRSTI; - input [5:0] AI; - output [5:0] AO; - input BDRSTI; - input [5:0] BI; - output [5:0] BO; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter gt0_bypass_reg1 = 1'b0; - parameter gt0_bypass_reg2 = 1'b0; - parameter gt1_bypass_reg1 = 1'b0; - parameter gt1_bypass_reg2 = 1'b0; - parameter use_adest_arst = 2'b00; - parameter use_bdest_arst = 2'b00; -endmodule - -(* blackbox *) -module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); - input ADRSTI; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - input BDRSTI; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter gt0_bypass_reg1 = 1'b0; - parameter gt0_bypass_reg2 = 1'b0; - parameter gt1_bypass_reg1 = 1'b0; - parameter gt1_bypass_reg2 = 1'b0; - parameter use_adest_arst = 2'b00; - parameter use_asrc_arst = 2'b00; - parameter use_bdest_arst = 2'b00; - parameter use_bsrc_arst = 2'b00; -endmodule - -(* blackbox *) -module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI); - input [5:0] AI; - output [5:0] AO; - input [5:0] BI; - output [5:0] BO; - input CK1; - input CK2; -endmodule - -(* blackbox *) -module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); - input ADRSTI; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - input BDRSTI; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter gt0_bypass_reg1 = 1'b0; - parameter gt0_bypass_reg2 = 1'b0; - parameter gt1_bypass_reg1 = 1'b0; - parameter gt1_bypass_reg2 = 1'b0; - parameter use_adest_arst = 2'b00; - parameter use_asrc_arst = 2'b00; - parameter use_bdest_arst = 2'b00; - parameter use_bsrc_arst = 2'b00; -endmodule - (* blackbox *) module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO , BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4 @@ -411,14 +249,6 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); output [5:0] BO; endmodule -(* blackbox *) -module NX_CKS(CKI, CMD, CKO); - input CKI; - output CKO; - input CMD; - parameter ck_edge = 1'b0; -endmodule - (* blackbox *) module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index e69de29bb..e5a88023f 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -0,0 +1,86 @@ +(* blackbox *) +module NX_CKS(CKI, CMD, CKO); + input CKI; + output CKO; + input CMD; + parameter ck_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1 +, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4 +, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6); + input AI1; + input AI2; + input AI3; + input AI4; + input AI5; + input AI6; + output AO1; + output AO2; + output AO3; + output AO4; + output AO5; + output AO6; + input BI1; + input BI2; + input BI3; + input BI4; + input BI5; + input BI6; + output BO1; + output BO2; + output BO3; + output BO4; + output BO5; + output BO6; + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CI6; + input CK1; + input CK2; + output CO1; + output CO2; + output CO3; + output CO4; + output CO5; + output CO6; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter mode = 0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; + parameter use_cdest_arst = 2'b00; + parameter use_csrc_arst = 2'b00; + parameter use_ddest_arst = 2'b00; + parameter use_dsrc_arst = 2'b00; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index e69de29bb..85b288ea0 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -0,0 +1,8 @@ +(* blackbox *) +module NX_CKS(CKI, CMD, CKO); + input CKI; + output CKO; + input CMD; + parameter ck_edge = 1'b0; +endmodule + diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index e69de29bb..d0f5502f8 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -0,0 +1,335 @@ +module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + + NX_CDC_L #( + .mode(0), // -- 0: 2DFF + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(2'b00), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(2'b00), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(2'b00), + .use_cdest_arst(2'b00), + .use_dsrc_arst(2'b00), + .use_ddest_arst(2'b00), + .gt0_bypass_reg1(gt0_bypass_reg1), + .gt0_bypass_reg2(gt0_bypass_reg2), + .gt1_bypass_reg1(gt1_bypass_reg2), + .gt1_bypass_reg2(gt1_bypass_reg2), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0) + ); +endmodule + +module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; + + NX_CDC_L #( + .mode(1), // -- 1: 3DFF + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(use_asrc_arst), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(use_bsrc_arst), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(2'b00), + .use_cdest_arst(2'b00), + .use_dsrc_arst(2'b00), + .use_ddest_arst(2'b00), + .gt0_bypass_reg1(gt0_bypass_reg1), + .gt0_bypass_reg2(gt0_bypass_reg2), + .gt1_bypass_reg1(gt1_bypass_reg2), + .gt1_bypass_reg2(gt1_bypass_reg2), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0) + ); +endmodule + +module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI); + input ADRSTI; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + input BDRSTI; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter gt0_bypass_reg1 = 1'b0; + parameter gt0_bypass_reg2 = 1'b0; + parameter gt1_bypass_reg1 = 1'b0; + parameter gt1_bypass_reg2 = 1'b0; + parameter use_adest_arst = 2'b00; + parameter use_asrc_arst = 2'b00; + parameter use_bdest_arst = 2'b00; + parameter use_bsrc_arst = 2'b00; + + NX_CDC_L #( + .mode(2), // -- 2: B2G_3DFF_G2B + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(use_asrc_arst), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(use_bsrc_arst), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(2'b00), + .use_cdest_arst(2'b00), + .use_dsrc_arst(2'b00), + .use_ddest_arst(2'b00), + .gt0_bypass_reg1(gt0_bypass_reg1), + .gt0_bypass_reg2(gt0_bypass_reg2), + .gt1_bypass_reg1(gt1_bypass_reg2), + .gt1_bypass_reg2(gt1_bypass_reg2), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0) + ); +endmodule + +module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; + + NX_CDC_L #( + .mode(3), // -- 3: bin2gray + .ck0_edge(1'b0), + .ck1_edge(1'b0), + .ack_sel(1'b0), + .bck_sel(1'b0), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(2'b00), + .use_adest_arst(2'b00), + .use_bsrc_arst(2'b00), + .use_bdest_arst(2'b00), + .use_csrc_arst(2'b00), + .use_cdest_arst(2'b00), + .use_dsrc_arst(2'b00), + .use_ddest_arst(2'b00), + .gt0_bypass_reg1(1'b0), + .gt0_bypass_reg2(1'b0), + .gt1_bypass_reg1(1'b0), + .gt1_bypass_reg2(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0) + ); +endmodule From 60611b936b5e67ad68ee07fb822f71112f85b3a0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Mar 2024 14:15:30 +0100 Subject: [PATCH 021/342] CDC_U --- techlibs/nanoxplore/cells_bb.v | 179 ------------ techlibs/nanoxplore/cells_bb_u.v | 91 ++++++ techlibs/nanoxplore/cells_wrap_u.v | 434 +++++++++++++++++++++++++++++ 3 files changed, 525 insertions(+), 179 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 2a3d8b62f..5a2ec90f4 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -70,185 +70,6 @@ module NX_BFR(I, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO -, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4 -, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3 -, DO4, DO5, DO6); - input ADRSTI; - output ADRSTO; - input AI1; - input AI2; - input AI3; - input AI4; - input AI5; - input AI6; - output AO1; - output AO2; - output AO3; - output AO4; - output AO5; - output AO6; - input ASRSTI; - output ASRSTO; - input BDRSTI; - output BDRSTO; - input BI1; - input BI2; - input BI3; - input BI4; - input BI5; - input BI6; - output BO1; - output BO2; - output BO3; - output BO4; - output BO5; - output BO6; - input BSRSTI; - output BSRSTO; - input CDRSTI; - output CDRSTO; - input CI1; - input CI2; - input CI3; - input CI4; - input CI5; - input CI6; - input CK1; - input CK2; - output CO1; - output CO2; - output CO3; - output CO4; - output CO5; - output CO6; - input CSRSTI; - output CSRSTO; - input DDRSTI; - output DDRSTO; - input DI1; - input DI2; - input DI3; - input DI4; - input DI5; - input DI6; - output DO1; - output DO2; - output DO3; - output DO4; - output DO5; - output DO6; - input DSRSTI; - output DSRSTO; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter cck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter dck_sel = 1'b0; - parameter link_BA = 1'b0; - parameter link_CB = 1'b0; - parameter link_DC = 1'b0; - parameter mode = 0; - parameter use_adest_arst = 1'b0; - parameter use_asrc_arst = 1'b0; - parameter use_bdest_arst = 1'b0; - parameter use_bsrc_arst = 1'b0; - parameter use_cdest_arst = 1'b0; - parameter use_csrc_arst = 1'b0; - parameter use_ddest_arst = 1'b0; - parameter use_dsrc_arst = 1'b0; -endmodule - -(* blackbox *) -module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI); - input ADRSTI; - output ADRSTO; - input [5:0] AI; - output [5:0] AO; - input BDRSTI; - output BDRSTO; - input [5:0] BI; - output [5:0] BO; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter use_adest_arst = 1'b0; - parameter use_bdest_arst = 1'b0; -endmodule - -(* blackbox *) -module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); - input ADRSTI; - output ADRSTO; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - output ASRSTO; - input BDRSTI; - output BDRSTO; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - output BSRSTO; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter use_adest_arst = 1'b0; - parameter use_asrc_arst = 1'b0; - parameter use_bdest_arst = 1'b0; - parameter use_bsrc_arst = 1'b0; -endmodule - -(* blackbox *) -module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI); - input [5:0] AI; - output [5:0] AO; - input [5:0] BI; - output [5:0] BO; -endmodule - -(* blackbox *) -module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); - input ADRSTI; - output ADRSTO; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - output ASRSTO; - input BDRSTI; - output BDRSTO; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - output BSRSTO; - input CK1; - input CK2; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter use_adest_arst = 1'b0; - parameter use_asrc_arst = 1'b0; - parameter use_bdest_arst = 1'b0; - parameter use_bsrc_arst = 1'b0; -endmodule - -(* blackbox *) -module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); - input [5:0] AI; - output [5:0] AO; - input [5:0] BI; - output [5:0] BO; -endmodule - (* blackbox *) module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 , DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 41f8736fc..fca409a5b 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -8,3 +8,94 @@ module NX_GCK_U(SI1, SI2, CMD, SO); parameter inv_out = 1'b0; parameter std_mode = "BYPASS"; endmodule + +(* blackbox *) +module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO +, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4 +, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3 +, DO4, DO5, DO6); + input ADRSTI; + output ADRSTO; + input AI1; + input AI2; + input AI3; + input AI4; + input AI5; + input AI6; + output AO1; + output AO2; + output AO3; + output AO4; + output AO5; + output AO6; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input BI1; + input BI2; + input BI3; + input BI4; + input BI5; + input BI6; + output BO1; + output BO2; + output BO3; + output BO4; + output BO5; + output BO6; + input BSRSTI; + output BSRSTO; + input CDRSTI; + output CDRSTO; + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CI6; + input CK1; + input CK2; + output CO1; + output CO2; + output CO3; + output CO4; + output CO5; + output CO6; + input CSRSTI; + output CSRSTO; + input DDRSTI; + output DDRSTO; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + input DSRSTI; + output DSRSTO; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter mode = 0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + parameter use_cdest_arst = 1'b0; + parameter use_csrc_arst = 1'b0; + parameter use_ddest_arst = 1'b0; + parameter use_dsrc_arst = 1'b0; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index e8f793612..ec5369906 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -32,3 +32,437 @@ NX_GCK_U #( .SO(CKO) ); endmodule + +module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + + NX_CDC_U #( + .mode(0), // -- 0: 2DFF + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(1'b0), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(1'b0), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(1'b0), + .use_cdest_arst(1'b0), + .use_dsrc_arst(1'b0), + .use_ddest_arst(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .ASRSTI(1'b0), + .ADRSTI(ADRSTI), + .ADRSTO(ADRSTO), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(1'b0), + .BDRSTI(BDRSTI), + .BDRSTO(BDRSTO), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(1'b0), + .CDRSTI(1'b0), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DSRSTI(1'b0), + .DDRSTI(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0), + ); +endmodule + +module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + + NX_CDC_U #( + .mode(1), // -- 1: 3DFF + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(use_asrc_arst), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(use_bsrc_arst), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(1'b0), + .use_cdest_arst(1'b0), + .use_dsrc_arst(1'b0), + .use_ddest_arst(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .ASRSTI(ASRSTI), + .ADRSTI(ADRSTI), + .ASRSTO(ASRSTO), + .ADRSTO(ADRSTO), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(BSRSTI), + .BDRSTI(BDRSTI), + .BSRSTO(BSRSTO), + .BDRSTO(BDRSTO), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(1'b0), + .CDRSTI(1'b0), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DSRSTI(1'b0), + .DDRSTI(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0), + ); +endmodule + +module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CK1; + input CK2; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + + NX_CDC_U #( + .mode(2), // -- 2: bin2gray + 3DFF + gray2bin + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(use_asrc_arst), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(use_bsrc_arst), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(1'b0), + .use_cdest_arst(1'b0), + .use_dsrc_arst(1'b0), + .use_ddest_arst(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .ASRSTI(ASRSTI), + .ADRSTI(ADRSTI), + .ASRSTO(ASRSTO), + .ADRSTO(ADRSTO), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(BSRSTI), + .BDRSTI(BDRSTI), + .BSRSTO(BSRSTO), + .BDRSTO(BDRSTO), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(1'b0), + .CDRSTI(1'b0), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DSRSTI(1'b0), + .DDRSTI(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0), + ); +endmodule + +module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; + + NX_CDC_U #( + .mode(3), // -- 3: bin2gray + .ck0_edge(1'b0), + .ck1_edge(1'b0), + .ack_sel(1'b0), + .bck_sel(1'b0), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(1'b0), + .use_adest_arst(1'b0), + .use_bsrc_arst(1'b0), + .use_bdest_arst(1'b0), + .use_csrc_arst(1'b0), + .use_cdest_arst(1'b0), + .use_dsrc_arst(1'b0), + .use_ddest_arst(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(1'b0), + .CK2(1'b0), + .ASRSTI(1'b0), + .ADRSTI(1'b0), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(1'b0), + .BDRSTI(1'b0), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(1'b0), + .CDRSTI(1'b0), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DSRSTI(1'b0), + .DDRSTI(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0), + ); +endmodule + +module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); + input [5:0] AI; + output [5:0] AO; + input [5:0] BI; + output [5:0] BO; + + NX_CDC_U #( + .mode(4), // -- 4: gray2bin + .ck0_edge(1'b0), + .ck1_edge(1'b0), + .ack_sel(1'b0), + .bck_sel(1'b0), + .cck_sel(1'b0), + .dck_sel(1'b0), + .use_asrc_arst(1'b0), + .use_adest_arst(1'b0), + .use_bsrc_arst(1'b0), + .use_bdest_arst(1'b0), + .use_csrc_arst(1'b0), + .use_cdest_arst(1'b0), + .use_dsrc_arst(1'b0), + .use_ddest_arst(1'b0), + .link_BA(1'b0), + .link_CB(1'b0), + .link_DC(1'b0), + ) _TECHMAP_REPLACE_ ( + .CK1(1'b0), + .CK2(1'b0), + .ASRSTI(1'b0), + .ADRSTI(1'b0), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(1'b0), + .BDRSTI(1'b0), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(1'b0), + .CDRSTI(1'b0), + .CI1(1'b0), + .CI2(1'b0), + .CI3(1'b0), + .CI4(1'b0), + .CI5(1'b0), + .CI6(1'b0), + .DSRSTI(1'b0), + .DDRSTI(1'b0), + .DI1(1'b0), + .DI2(1'b0), + .DI3(1'b0), + .DI4(1'b0), + .DI5(1'b0), + .DI6(1'b0), + ); +endmodule + From ce635abc210e9cbbd0396a7fca7ce0d06f7ecbf5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Mar 2024 15:26:18 +0100 Subject: [PATCH 022/342] NX_DSP/SPLIT --- techlibs/nanoxplore/cells_bb.v | 1214 ---------------------------- techlibs/nanoxplore/cells_bb_l.v | 385 +++++++++ techlibs/nanoxplore/cells_bb_m.v | 372 +++++++++ techlibs/nanoxplore/cells_bb_u.v | 386 +++++++++ techlibs/nanoxplore/cells_wrap_m.v | 448 ++++++++++ 5 files changed, 1591 insertions(+), 1214 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 5a2ec90f4..7aa8dcfb7 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -853,763 +853,6 @@ module NX_DFR(I, CK, L, R, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 -, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 -, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 -, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 -, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9 -, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12 -, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15 -, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11 -, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32 -, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53 -, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18 -, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39 -, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4 -, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3 -, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24 -, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45 -, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56); - input A1; - input A10; - input A11; - input A12; - input A13; - input A14; - input A15; - input A16; - input A17; - input A18; - input A19; - input A2; - input A20; - input A21; - input A22; - input A23; - input A24; - input A3; - input A4; - input A5; - input A6; - input A7; - input A8; - input A9; - input B1; - input B10; - input B11; - input B12; - input B13; - input B14; - input B15; - input B16; - input B17; - input B18; - input B2; - input B3; - input B4; - input B5; - input B6; - input B7; - input B8; - input B9; - input C1; - input C10; - input C11; - input C12; - input C13; - input C14; - input C15; - input C16; - input C17; - input C18; - input C19; - input C2; - input C20; - input C21; - input C22; - input C23; - input C24; - input C25; - input C26; - input C27; - input C28; - input C29; - input C3; - input C30; - input C31; - input C32; - input C33; - input C34; - input C35; - input C36; - input C4; - input C5; - input C6; - input C7; - input C8; - input C9; - input CAI1; - input CAI10; - input CAI11; - input CAI12; - input CAI13; - input CAI14; - input CAI15; - input CAI16; - input CAI17; - input CAI18; - input CAI2; - input CAI3; - input CAI4; - input CAI5; - input CAI6; - input CAI7; - input CAI8; - input CAI9; - output CAO1; - output CAO10; - output CAO11; - output CAO12; - output CAO13; - output CAO14; - output CAO15; - output CAO16; - output CAO17; - output CAO18; - output CAO2; - output CAO3; - output CAO4; - output CAO5; - output CAO6; - output CAO7; - output CAO8; - output CAO9; - input CBI1; - input CBI10; - input CBI11; - input CBI12; - input CBI13; - input CBI14; - input CBI15; - input CBI16; - input CBI17; - input CBI18; - input CBI2; - input CBI3; - input CBI4; - input CBI5; - input CBI6; - input CBI7; - input CBI8; - input CBI9; - output CBO1; - output CBO10; - output CBO11; - output CBO12; - output CBO13; - output CBO14; - output CBO15; - output CBO16; - output CBO17; - output CBO18; - output CBO2; - output CBO3; - output CBO4; - output CBO5; - output CBO6; - output CBO7; - output CBO8; - output CBO9; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO37; - output CO49; - input CZI1; - input CZI10; - input CZI11; - input CZI12; - input CZI13; - input CZI14; - input CZI15; - input CZI16; - input CZI17; - input CZI18; - input CZI19; - input CZI2; - input CZI20; - input CZI21; - input CZI22; - input CZI23; - input CZI24; - input CZI25; - input CZI26; - input CZI27; - input CZI28; - input CZI29; - input CZI3; - input CZI30; - input CZI31; - input CZI32; - input CZI33; - input CZI34; - input CZI35; - input CZI36; - input CZI37; - input CZI38; - input CZI39; - input CZI4; - input CZI40; - input CZI41; - input CZI42; - input CZI43; - input CZI44; - input CZI45; - input CZI46; - input CZI47; - input CZI48; - input CZI49; - input CZI5; - input CZI50; - input CZI51; - input CZI52; - input CZI53; - input CZI54; - input CZI55; - input CZI56; - input CZI6; - input CZI7; - input CZI8; - input CZI9; - output CZO1; - output CZO10; - output CZO11; - output CZO12; - output CZO13; - output CZO14; - output CZO15; - output CZO16; - output CZO17; - output CZO18; - output CZO19; - output CZO2; - output CZO20; - output CZO21; - output CZO22; - output CZO23; - output CZO24; - output CZO25; - output CZO26; - output CZO27; - output CZO28; - output CZO29; - output CZO3; - output CZO30; - output CZO31; - output CZO32; - output CZO33; - output CZO34; - output CZO35; - output CZO36; - output CZO37; - output CZO38; - output CZO39; - output CZO4; - output CZO40; - output CZO41; - output CZO42; - output CZO43; - output CZO44; - output CZO45; - output CZO46; - output CZO47; - output CZO48; - output CZO49; - output CZO5; - output CZO50; - output CZO51; - output CZO52; - output CZO53; - output CZO54; - output CZO55; - output CZO56; - output CZO6; - output CZO7; - output CZO8; - output CZO9; - input D1; - input D10; - input D11; - input D12; - input D13; - input D14; - input D15; - input D16; - input D17; - input D18; - input D2; - input D3; - input D4; - input D5; - input D6; - input D7; - input D8; - input D9; - output OVF; - input R; - input RZ; - input WE; - output Z1; - output Z10; - output Z11; - output Z12; - output Z13; - output Z14; - output Z15; - output Z16; - output Z17; - output Z18; - output Z19; - output Z2; - output Z20; - output Z21; - output Z22; - output Z23; - output Z24; - output Z25; - output Z26; - output Z27; - output Z28; - output Z29; - output Z3; - output Z30; - output Z31; - output Z32; - output Z33; - output Z34; - output Z35; - output Z36; - output Z37; - output Z38; - output Z39; - output Z4; - output Z40; - output Z41; - output Z42; - output Z43; - output Z44; - output Z45; - output Z46; - output Z47; - output Z48; - output Z49; - output Z5; - output Z50; - output Z51; - output Z52; - output Z53; - output Z54; - output Z55; - output Z56; - output Z6; - output Z7; - output Z8; - output Z9; - parameter raw_config0 = 20'b00000000000000000000; - parameter raw_config1 = 19'b0000000000000000000; - parameter raw_config2 = 13'b0000000000000; - parameter raw_config3 = 7'b0000000; - parameter std_mode = ""; -endmodule - -(* blackbox *) -module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 -, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 -, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 -, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 -, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 -, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 -, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 -, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37 -, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 -, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 -, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 -, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 -, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 -, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 -, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12 -, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33 -, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54 -, Z55, Z56); - input A1; - input A10; - input A11; - input A12; - input A13; - input A14; - input A15; - input A16; - input A17; - input A18; - input A19; - input A2; - input A20; - input A21; - input A22; - input A23; - input A24; - input A3; - input A4; - input A5; - input A6; - input A7; - input A8; - input A9; - input B1; - input B10; - input B11; - input B12; - input B13; - input B14; - input B15; - input B16; - input B17; - input B18; - input B2; - input B3; - input B4; - input B5; - input B6; - input B7; - input B8; - input B9; - input C1; - input C10; - input C11; - input C12; - input C13; - input C14; - input C15; - input C16; - input C17; - input C18; - input C19; - input C2; - input C20; - input C21; - input C22; - input C23; - input C24; - input C25; - input C26; - input C27; - input C28; - input C29; - input C3; - input C30; - input C31; - input C32; - input C33; - input C34; - input C35; - input C36; - input C4; - input C5; - input C6; - input C7; - input C8; - input C9; - input CAI1; - input CAI10; - input CAI11; - input CAI12; - input CAI13; - input CAI14; - input CAI15; - input CAI16; - input CAI17; - input CAI18; - input CAI19; - input CAI2; - input CAI20; - input CAI21; - input CAI22; - input CAI23; - input CAI24; - input CAI3; - input CAI4; - input CAI5; - input CAI6; - input CAI7; - input CAI8; - input CAI9; - output CAO1; - output CAO10; - output CAO11; - output CAO12; - output CAO13; - output CAO14; - output CAO15; - output CAO16; - output CAO17; - output CAO18; - output CAO19; - output CAO2; - output CAO20; - output CAO21; - output CAO22; - output CAO23; - output CAO24; - output CAO3; - output CAO4; - output CAO5; - output CAO6; - output CAO7; - output CAO8; - output CAO9; - input CBI1; - input CBI10; - input CBI11; - input CBI12; - input CBI13; - input CBI14; - input CBI15; - input CBI16; - input CBI17; - input CBI18; - input CBI2; - input CBI3; - input CBI4; - input CBI5; - input CBI6; - input CBI7; - input CBI8; - input CBI9; - output CBO1; - output CBO10; - output CBO11; - output CBO12; - output CBO13; - output CBO14; - output CBO15; - output CBO16; - output CBO17; - output CBO18; - output CBO2; - output CBO3; - output CBO4; - output CBO5; - output CBO6; - output CBO7; - output CBO8; - output CBO9; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO37; - output CO57; - input CZI1; - input CZI10; - input CZI11; - input CZI12; - input CZI13; - input CZI14; - input CZI15; - input CZI16; - input CZI17; - input CZI18; - input CZI19; - input CZI2; - input CZI20; - input CZI21; - input CZI22; - input CZI23; - input CZI24; - input CZI25; - input CZI26; - input CZI27; - input CZI28; - input CZI29; - input CZI3; - input CZI30; - input CZI31; - input CZI32; - input CZI33; - input CZI34; - input CZI35; - input CZI36; - input CZI37; - input CZI38; - input CZI39; - input CZI4; - input CZI40; - input CZI41; - input CZI42; - input CZI43; - input CZI44; - input CZI45; - input CZI46; - input CZI47; - input CZI48; - input CZI49; - input CZI5; - input CZI50; - input CZI51; - input CZI52; - input CZI53; - input CZI54; - input CZI55; - input CZI56; - input CZI6; - input CZI7; - input CZI8; - input CZI9; - output CZO1; - output CZO10; - output CZO11; - output CZO12; - output CZO13; - output CZO14; - output CZO15; - output CZO16; - output CZO17; - output CZO18; - output CZO19; - output CZO2; - output CZO20; - output CZO21; - output CZO22; - output CZO23; - output CZO24; - output CZO25; - output CZO26; - output CZO27; - output CZO28; - output CZO29; - output CZO3; - output CZO30; - output CZO31; - output CZO32; - output CZO33; - output CZO34; - output CZO35; - output CZO36; - output CZO37; - output CZO38; - output CZO39; - output CZO4; - output CZO40; - output CZO41; - output CZO42; - output CZO43; - output CZO44; - output CZO45; - output CZO46; - output CZO47; - output CZO48; - output CZO49; - output CZO5; - output CZO50; - output CZO51; - output CZO52; - output CZO53; - output CZO54; - output CZO55; - output CZO56; - output CZO6; - output CZO7; - output CZO8; - output CZO9; - input D1; - input D10; - input D11; - input D12; - input D13; - input D14; - input D15; - input D16; - input D17; - input D18; - input D2; - input D3; - input D4; - input D5; - input D6; - input D7; - input D8; - input D9; - output OVF; - input R; - input RZ; - input WE; - output Z1; - output Z10; - output Z11; - output Z12; - output Z13; - output Z14; - output Z15; - output Z16; - output Z17; - output Z18; - output Z19; - output Z2; - output Z20; - output Z21; - output Z22; - output Z23; - output Z24; - output Z25; - output Z26; - output Z27; - output Z28; - output Z29; - output Z3; - output Z30; - output Z31; - output Z32; - output Z33; - output Z34; - output Z35; - output Z36; - output Z37; - output Z38; - output Z39; - output Z4; - output Z40; - output Z41; - output Z42; - output Z43; - output Z44; - output Z45; - output Z46; - output Z47; - output Z48; - output Z49; - output Z5; - output Z50; - output Z51; - output Z52; - output Z53; - output Z54; - output Z55; - output Z56; - output Z6; - output Z7; - output Z8; - output Z9; - parameter raw_config0 = 20'b00000000000000000000; - parameter raw_config1 = 19'b0000000000000000000; - parameter raw_config2 = 13'b0000000000000; - parameter raw_config3 = 7'b0000000; - parameter std_mode = ""; -endmodule - (* blackbox *) module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO); @@ -1713,463 +956,6 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, parameter std_mode = ""; endmodule -(* blackbox *) -module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [17:0] CAI; - output [17:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO36; - output CO48; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - output [55:0] Z; - parameter ALU_DYNAMIC_OP = 1'b0; - parameter ALU_MUX = 1'b0; - parameter ALU_OP = 6'b000000; - parameter CO_SEL = 1'b0; - parameter ENABLE_PR_ALU_RST = 1'b0; - parameter ENABLE_PR_A_RST = 1'b0; - parameter ENABLE_PR_B_RST = 1'b0; - parameter ENABLE_PR_CI_RST = 1'b0; - parameter ENABLE_PR_CO_RST = 1'b0; - parameter ENABLE_PR_C_RST = 1'b0; - parameter ENABLE_PR_D_RST = 1'b0; - parameter ENABLE_PR_MULT_RST = 1'b0; - parameter ENABLE_PR_OV_RST = 1'b0; - parameter ENABLE_PR_P_RST = 1'b0; - parameter ENABLE_PR_X_RST = 1'b0; - parameter ENABLE_PR_Y_RST = 1'b0; - parameter ENABLE_PR_Z_RST = 1'b0; - parameter ENABLE_SATURATION = 1'b0; - parameter MUX_A = 1'b0; - parameter MUX_B = 1'b0; - parameter MUX_CI = 1'b0; - parameter MUX_P = 1'b0; - parameter MUX_X = 2'b00; - parameter MUX_Y = 1'b0; - parameter MUX_Z = 1'b0; - parameter PRE_ADDER_OP = 1'b0; - parameter PR_ALU_MUX = 1'b0; - parameter PR_A_CASCADE_MUX = 2'b00; - parameter PR_A_MUX = 2'b00; - parameter PR_B_CASCADE_MUX = 2'b00; - parameter PR_B_MUX = 2'b00; - parameter PR_CI_MUX = 1'b0; - parameter PR_CO_MUX = 1'b0; - parameter PR_C_MUX = 1'b0; - parameter PR_D_MUX = 1'b0; - parameter PR_MULT_MUX = 1'b0; - parameter PR_OV_MUX = 1'b0; - parameter PR_P_MUX = 1'b0; - parameter PR_X_MUX = 1'b0; - parameter PR_Y_MUX = 1'b0; - parameter PR_Z_MUX = 1'b0; - parameter SATURATION_RANK = 6'b000000; - parameter SIGNED_MODE = 1'b0; - parameter Z_FEEDBACK_SHL12 = 1'b0; -endmodule - -(* blackbox *) -module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 -, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 -, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 -, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 -, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 -, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 -, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 -, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57 -, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 -, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 -, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 -, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 -, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 -, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 -, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11 -, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32 -, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53 -, Z54, Z55, Z56); - input A1; - input A10; - input A11; - input A12; - input A13; - input A14; - input A15; - input A16; - input A17; - input A18; - input A19; - input A2; - input A20; - input A21; - input A22; - input A23; - input A24; - input A3; - input A4; - input A5; - input A6; - input A7; - input A8; - input A9; - input B1; - input B10; - input B11; - input B12; - input B13; - input B14; - input B15; - input B16; - input B17; - input B18; - input B2; - input B3; - input B4; - input B5; - input B6; - input B7; - input B8; - input B9; - input C1; - input C10; - input C11; - input C12; - input C13; - input C14; - input C15; - input C16; - input C17; - input C18; - input C19; - input C2; - input C20; - input C21; - input C22; - input C23; - input C24; - input C25; - input C26; - input C27; - input C28; - input C29; - input C3; - input C30; - input C31; - input C32; - input C33; - input C34; - input C35; - input C36; - input C4; - input C5; - input C6; - input C7; - input C8; - input C9; - input CAI1; - input CAI10; - input CAI11; - input CAI12; - input CAI13; - input CAI14; - input CAI15; - input CAI16; - input CAI17; - input CAI18; - input CAI19; - input CAI2; - input CAI20; - input CAI21; - input CAI22; - input CAI23; - input CAI24; - input CAI3; - input CAI4; - input CAI5; - input CAI6; - input CAI7; - input CAI8; - input CAI9; - output CAO1; - output CAO10; - output CAO11; - output CAO12; - output CAO13; - output CAO14; - output CAO15; - output CAO16; - output CAO17; - output CAO18; - output CAO19; - output CAO2; - output CAO20; - output CAO21; - output CAO22; - output CAO23; - output CAO24; - output CAO3; - output CAO4; - output CAO5; - output CAO6; - output CAO7; - output CAO8; - output CAO9; - input CBI1; - input CBI10; - input CBI11; - input CBI12; - input CBI13; - input CBI14; - input CBI15; - input CBI16; - input CBI17; - input CBI18; - input CBI2; - input CBI3; - input CBI4; - input CBI5; - input CBI6; - input CBI7; - input CBI8; - input CBI9; - output CBO1; - output CBO10; - output CBO11; - output CBO12; - output CBO13; - output CBO14; - output CBO15; - output CBO16; - output CBO17; - output CBO18; - output CBO2; - output CBO3; - output CBO4; - output CBO5; - output CBO6; - output CBO7; - output CBO8; - output CBO9; - input CCI; - output CCO; - input CI; - input CK; - output CO43; - output CO57; - input CZI1; - input CZI10; - input CZI11; - input CZI12; - input CZI13; - input CZI14; - input CZI15; - input CZI16; - input CZI17; - input CZI18; - input CZI19; - input CZI2; - input CZI20; - input CZI21; - input CZI22; - input CZI23; - input CZI24; - input CZI25; - input CZI26; - input CZI27; - input CZI28; - input CZI29; - input CZI3; - input CZI30; - input CZI31; - input CZI32; - input CZI33; - input CZI34; - input CZI35; - input CZI36; - input CZI37; - input CZI38; - input CZI39; - input CZI4; - input CZI40; - input CZI41; - input CZI42; - input CZI43; - input CZI44; - input CZI45; - input CZI46; - input CZI47; - input CZI48; - input CZI49; - input CZI5; - input CZI50; - input CZI51; - input CZI52; - input CZI53; - input CZI54; - input CZI55; - input CZI56; - input CZI6; - input CZI7; - input CZI8; - input CZI9; - output CZO1; - output CZO10; - output CZO11; - output CZO12; - output CZO13; - output CZO14; - output CZO15; - output CZO16; - output CZO17; - output CZO18; - output CZO19; - output CZO2; - output CZO20; - output CZO21; - output CZO22; - output CZO23; - output CZO24; - output CZO25; - output CZO26; - output CZO27; - output CZO28; - output CZO29; - output CZO3; - output CZO30; - output CZO31; - output CZO32; - output CZO33; - output CZO34; - output CZO35; - output CZO36; - output CZO37; - output CZO38; - output CZO39; - output CZO4; - output CZO40; - output CZO41; - output CZO42; - output CZO43; - output CZO44; - output CZO45; - output CZO46; - output CZO47; - output CZO48; - output CZO49; - output CZO5; - output CZO50; - output CZO51; - output CZO52; - output CZO53; - output CZO54; - output CZO55; - output CZO56; - output CZO6; - output CZO7; - output CZO8; - output CZO9; - input D1; - input D10; - input D11; - input D12; - input D13; - input D14; - input D15; - input D16; - input D17; - input D18; - input D2; - input D3; - input D4; - input D5; - input D6; - input D7; - input D8; - input D9; - output OVF; - input R; - output RESERVED; - input RZ; - input WE; - input WEZ; - output Z1; - output Z10; - output Z11; - output Z12; - output Z13; - output Z14; - output Z15; - output Z16; - output Z17; - output Z18; - output Z19; - output Z2; - output Z20; - output Z21; - output Z22; - output Z23; - output Z24; - output Z25; - output Z26; - output Z27; - output Z28; - output Z29; - output Z3; - output Z30; - output Z31; - output Z32; - output Z33; - output Z34; - output Z35; - output Z36; - output Z37; - output Z38; - output Z39; - output Z4; - output Z40; - output Z41; - output Z42; - output Z43; - output Z44; - output Z45; - output Z46; - output Z47; - output Z48; - output Z49; - output Z5; - output Z50; - output Z51; - output Z52; - output Z53; - output Z54; - output Z55; - output Z56; - output Z6; - output Z7; - output Z8; - output Z9; - parameter raw_config0 = 27'b000000000000000000000000000; - parameter raw_config1 = 24'b000000000000000000000000; - parameter raw_config2 = 14'b00000000000000; - parameter raw_config3 = 3'b000; - parameter std_mode = ""; -endmodule - (* blackbox *) module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO); diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index e5a88023f..a3a11a06c 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -84,3 +84,388 @@ module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, parameter use_dsrc_arst = 2'b00; endmodule +(* blackbox *) +module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 +, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 +, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 +, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37 +, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 +, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 +, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 +, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 +, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 +, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 +, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12 +, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33 +, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54 +, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI19; + input CAI2; + input CAI20; + input CAI21; + input CAI22; + input CAI23; + input CAI24; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO19; + output CAO2; + output CAO20; + output CAO21; + output CAO22; + output CAO23; + output CAO24; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO57; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + input RZ; + input WE; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index 85b288ea0..e54c1fd8a 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -6,3 +6,375 @@ module NX_CKS(CKI, CMD, CKO); parameter ck_edge = 1'b0; endmodule +(* blackbox *) +module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9 +, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12 +, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15 +, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11 +, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32 +, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53 +, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18 +, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39 +, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4 +, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3 +, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24 +, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45 +, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI2; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO2; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO49; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + input RZ; + input WE; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index fca409a5b..657cd6667 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -99,3 +99,389 @@ module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI parameter use_ddest_arst = 1'b0; parameter use_dsrc_arst = 1'b0; endmodule + +(* blackbox *) +module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21 +, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 +, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21 +, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6 +, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3 +, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24 +, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3 +, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57 +, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20 +, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41 +, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6 +, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27 +, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48 +, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13 +, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11 +, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32 +, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53 +, Z54, Z55, Z56); + input A1; + input A10; + input A11; + input A12; + input A13; + input A14; + input A15; + input A16; + input A17; + input A18; + input A19; + input A2; + input A20; + input A21; + input A22; + input A23; + input A24; + input A3; + input A4; + input A5; + input A6; + input A7; + input A8; + input A9; + input B1; + input B10; + input B11; + input B12; + input B13; + input B14; + input B15; + input B16; + input B17; + input B18; + input B2; + input B3; + input B4; + input B5; + input B6; + input B7; + input B8; + input B9; + input C1; + input C10; + input C11; + input C12; + input C13; + input C14; + input C15; + input C16; + input C17; + input C18; + input C19; + input C2; + input C20; + input C21; + input C22; + input C23; + input C24; + input C25; + input C26; + input C27; + input C28; + input C29; + input C3; + input C30; + input C31; + input C32; + input C33; + input C34; + input C35; + input C36; + input C4; + input C5; + input C6; + input C7; + input C8; + input C9; + input CAI1; + input CAI10; + input CAI11; + input CAI12; + input CAI13; + input CAI14; + input CAI15; + input CAI16; + input CAI17; + input CAI18; + input CAI19; + input CAI2; + input CAI20; + input CAI21; + input CAI22; + input CAI23; + input CAI24; + input CAI3; + input CAI4; + input CAI5; + input CAI6; + input CAI7; + input CAI8; + input CAI9; + output CAO1; + output CAO10; + output CAO11; + output CAO12; + output CAO13; + output CAO14; + output CAO15; + output CAO16; + output CAO17; + output CAO18; + output CAO19; + output CAO2; + output CAO20; + output CAO21; + output CAO22; + output CAO23; + output CAO24; + output CAO3; + output CAO4; + output CAO5; + output CAO6; + output CAO7; + output CAO8; + output CAO9; + input CBI1; + input CBI10; + input CBI11; + input CBI12; + input CBI13; + input CBI14; + input CBI15; + input CBI16; + input CBI17; + input CBI18; + input CBI2; + input CBI3; + input CBI4; + input CBI5; + input CBI6; + input CBI7; + input CBI8; + input CBI9; + output CBO1; + output CBO10; + output CBO11; + output CBO12; + output CBO13; + output CBO14; + output CBO15; + output CBO16; + output CBO17; + output CBO18; + output CBO2; + output CBO3; + output CBO4; + output CBO5; + output CBO6; + output CBO7; + output CBO8; + output CBO9; + input CCI; + output CCO; + input CI; + input CK; + output CO43; + output CO57; + input CZI1; + input CZI10; + input CZI11; + input CZI12; + input CZI13; + input CZI14; + input CZI15; + input CZI16; + input CZI17; + input CZI18; + input CZI19; + input CZI2; + input CZI20; + input CZI21; + input CZI22; + input CZI23; + input CZI24; + input CZI25; + input CZI26; + input CZI27; + input CZI28; + input CZI29; + input CZI3; + input CZI30; + input CZI31; + input CZI32; + input CZI33; + input CZI34; + input CZI35; + input CZI36; + input CZI37; + input CZI38; + input CZI39; + input CZI4; + input CZI40; + input CZI41; + input CZI42; + input CZI43; + input CZI44; + input CZI45; + input CZI46; + input CZI47; + input CZI48; + input CZI49; + input CZI5; + input CZI50; + input CZI51; + input CZI52; + input CZI53; + input CZI54; + input CZI55; + input CZI56; + input CZI6; + input CZI7; + input CZI8; + input CZI9; + output CZO1; + output CZO10; + output CZO11; + output CZO12; + output CZO13; + output CZO14; + output CZO15; + output CZO16; + output CZO17; + output CZO18; + output CZO19; + output CZO2; + output CZO20; + output CZO21; + output CZO22; + output CZO23; + output CZO24; + output CZO25; + output CZO26; + output CZO27; + output CZO28; + output CZO29; + output CZO3; + output CZO30; + output CZO31; + output CZO32; + output CZO33; + output CZO34; + output CZO35; + output CZO36; + output CZO37; + output CZO38; + output CZO39; + output CZO4; + output CZO40; + output CZO41; + output CZO42; + output CZO43; + output CZO44; + output CZO45; + output CZO46; + output CZO47; + output CZO48; + output CZO49; + output CZO5; + output CZO50; + output CZO51; + output CZO52; + output CZO53; + output CZO54; + output CZO55; + output CZO56; + output CZO6; + output CZO7; + output CZO8; + output CZO9; + input D1; + input D10; + input D11; + input D12; + input D13; + input D14; + input D15; + input D16; + input D17; + input D18; + input D2; + input D3; + input D4; + input D5; + input D6; + input D7; + input D8; + input D9; + output OVF; + input R; + output RESERVED; + input RZ; + input WE; + input WEZ; + output Z1; + output Z10; + output Z11; + output Z12; + output Z13; + output Z14; + output Z15; + output Z16; + output Z17; + output Z18; + output Z19; + output Z2; + output Z20; + output Z21; + output Z22; + output Z23; + output Z24; + output Z25; + output Z26; + output Z27; + output Z28; + output Z29; + output Z3; + output Z30; + output Z31; + output Z32; + output Z33; + output Z34; + output Z35; + output Z36; + output Z37; + output Z38; + output Z39; + output Z4; + output Z40; + output Z41; + output Z42; + output Z43; + output Z44; + output Z45; + output Z46; + output Z47; + output Z48; + output Z49; + output Z5; + output Z50; + output Z51; + output Z52; + output Z53; + output Z54; + output Z55; + output Z56; + output Z6; + output Z7; + output Z8; + output Z9; + parameter raw_config0 = 27'b000000000000000000000000000; + parameter raw_config1 = 24'b000000000000000000000000; + parameter raw_config2 = 14'b00000000000000; + parameter raw_config3 = 3'b000; + parameter std_mode = ""; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v index e69de29bb..04c9cd667 100644 --- a/techlibs/nanoxplore/cells_wrap_m.v +++ b/techlibs/nanoxplore/cells_wrap_m.v @@ -0,0 +1,448 @@ +module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [17:0] CAI; + output [17:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO36; + output CO48; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 1'b0; + parameter ALU_MUX = 1'b0; + parameter ALU_OP = 6'b000000; + parameter CO_SEL = 1'b0; + parameter ENABLE_PR_ALU_RST = 1'b0; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 2'b00; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_ALU_MUX = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; + parameter Z_FEEDBACK_SHL12 = 1'b0; + +localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z, + MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE }; + +localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX, + PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX }; + +localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST, + ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST, + ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST }; + +localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP }; + + NX_DSP #( + .std_mode(""), + .raw_config0(RAW_CONFIG0_GEN), + .raw_config1(RAW_CONFIG1_GEN), + .raw_config2(RAW_CONFIG2_GEN), + .raw_config3(RAW_CONFIG3_GEN), + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO(CO), + .CO37(CO36), + .CO49(CO48), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule From 200e1a7bfea7bd950e372a4e2e8def4afe9be97f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 12 Mar 2024 15:11:11 +0100 Subject: [PATCH 023/342] more DSP wrappers --- techlibs/nanoxplore/cells_bb.v | 248 -------- techlibs/nanoxplore/cells_wrap_l.v | 874 ++++++++++++++++++++++++++++ techlibs/nanoxplore/cells_wrap_m.v | 399 +++++++++++++ techlibs/nanoxplore/cells_wrap_u.v | 883 +++++++++++++++++++++++++++++ 4 files changed, 2156 insertions(+), 248 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 7aa8dcfb7..f01d7571f 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -853,254 +853,6 @@ module NX_DFR(I, CK, L, R, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [23:0] CAI; - output [23:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO36; - output CO56; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - output [55:0] Z; - parameter ALU_DYNAMIC_OP = 1'b0; - parameter ALU_MUX = 1'b0; - parameter ALU_OP = 6'b000000; - parameter CO_SEL = 1'b0; - parameter ENABLE_PR_ALU_RST = 1'b0; - parameter ENABLE_PR_A_RST = 1'b0; - parameter ENABLE_PR_B_RST = 1'b0; - parameter ENABLE_PR_CI_RST = 1'b0; - parameter ENABLE_PR_CO_RST = 1'b0; - parameter ENABLE_PR_C_RST = 1'b0; - parameter ENABLE_PR_D_RST = 1'b0; - parameter ENABLE_PR_MULT_RST = 1'b0; - parameter ENABLE_PR_OV_RST = 1'b0; - parameter ENABLE_PR_P_RST = 1'b0; - parameter ENABLE_PR_X_RST = 1'b0; - parameter ENABLE_PR_Y_RST = 1'b0; - parameter ENABLE_PR_Z_RST = 1'b0; - parameter ENABLE_SATURATION = 1'b0; - parameter MUX_A = 1'b0; - parameter MUX_B = 1'b0; - parameter MUX_CI = 1'b0; - parameter MUX_P = 1'b0; - parameter MUX_X = 2'b00; - parameter MUX_Y = 1'b0; - parameter MUX_Z = 1'b0; - parameter PRE_ADDER_OP = 1'b0; - parameter PR_ALU_MUX = 1'b0; - parameter PR_A_CASCADE_MUX = 2'b00; - parameter PR_A_MUX = 2'b00; - parameter PR_B_CASCADE_MUX = 2'b00; - parameter PR_B_MUX = 2'b00; - parameter PR_CI_MUX = 1'b0; - parameter PR_CO_MUX = 1'b0; - parameter PR_C_MUX = 1'b0; - parameter PR_D_MUX = 1'b0; - parameter PR_MULT_MUX = 1'b0; - parameter PR_OV_MUX = 1'b0; - parameter PR_P_MUX = 1'b0; - parameter PR_X_MUX = 1'b0; - parameter PR_Y_MUX = 1'b0; - parameter PR_Z_MUX = 1'b0; - parameter SATURATION_RANK = 6'b000000; - parameter SIGNED_MODE = 1'b0; - parameter Z_FEEDBACK_SHL12 = 1'b0; -endmodule - -(* blackbox *) -module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [23:0] CAI; - output [23:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO37; - output CO57; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - output [55:0] Z; - parameter raw_config0 = 20'b00000000000000000000; - parameter raw_config1 = 19'b0000000000000000000; - parameter raw_config2 = 13'b0000000000000; - parameter raw_config3 = 7'b0000000; - parameter std_mode = ""; -endmodule - -(* blackbox *) -module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [23:0] CAI; - output [23:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO42; - output CO56; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - input WEZ; - output [55:0] Z; - parameter ALU_DYNAMIC_OP = 2'b00; - parameter ALU_OP = 3'b000; - parameter ENABLE_PR_A_RST = 1'b0; - parameter ENABLE_PR_B_RST = 1'b0; - parameter ENABLE_PR_CCO_RST = 1'b0; - parameter ENABLE_PR_CI_RST = 1'b0; - parameter ENABLE_PR_CO_RST = 1'b0; - parameter ENABLE_PR_CZ_RST = 1'b0; - parameter ENABLE_PR_C_RST = 1'b0; - parameter ENABLE_PR_D_RST = 1'b0; - parameter ENABLE_PR_MULT_RST = 1'b0; - parameter ENABLE_PR_OV_RST = 1'b0; - parameter ENABLE_PR_P_RST = 1'b0; - parameter ENABLE_PR_X_RST = 1'b0; - parameter ENABLE_PR_Y_RST = 1'b0; - parameter ENABLE_PR_Z_RST = 1'b0; - parameter ENABLE_SATURATION = 1'b0; - parameter INV_RST = 1'b0; - parameter INV_RSTZ = 1'b0; - parameter INV_WE = 1'b0; - parameter INV_WEZ = 1'b0; - parameter MUX_A = 1'b0; - parameter MUX_B = 1'b0; - parameter MUX_CCI = 1'b0; - parameter MUX_CCO = 1'b0; - parameter MUX_CI = 1'b0; - parameter MUX_CZ = 1'b0; - parameter MUX_P = 1'b0; - parameter MUX_X = 3'b000; - parameter MUX_Y = 1'b0; - parameter MUX_Z = 1'b0; - parameter PRE_ADDER_OP = 1'b0; - parameter PR_A_CASCADE_MUX = 2'b00; - parameter PR_A_MUX = 2'b00; - parameter PR_B_CASCADE_MUX = 2'b00; - parameter PR_B_MUX = 2'b00; - parameter PR_CCO_MUX = 1'b0; - parameter PR_CI_MUX = 1'b0; - parameter PR_CO_MUX = 1'b0; - parameter PR_CZ_MUX = 1'b0; - parameter PR_C_MUX = 1'b0; - parameter PR_D_MUX = 1'b0; - parameter PR_MULT_MUX = 1'b0; - parameter PR_OV_MUX = 1'b0; - parameter PR_P_MUX = 1'b0; - parameter PR_RSTZ_MUX = 1'b0; - parameter PR_RST_MUX = 1'b0; - parameter PR_WEZ_MUX = 1'b0; - parameter PR_WE_MUX = 1'b0; - parameter PR_X_MUX = 1'b0; - parameter PR_Y_MUX = 1'b0; - parameter PR_Z_MUX = 1'b0; - parameter SATURATION_RANK = 6'b000000; - parameter SIGNED_MODE = 1'b0; -endmodule - -(* blackbox *) -module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [23:0] CAI; - output [23:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO43; - output CO57; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - input WEZ; - output [55:0] Z; - parameter raw_config0 = 27'b000000000000000000000000000; - parameter raw_config1 = 24'b000000000000000000000000; - parameter raw_config2 = 14'b00000000000000; - parameter raw_config3 = 3'b000; - parameter std_mode = ""; -endmodule - -(* blackbox *) -module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO -, CZO); - input [23:0] A; - input [17:0] B; - input [35:0] C; - input [17:0] CAI; - output [17:0] CAO; - input [17:0] CBI; - output [17:0] CBO; - input CCI; - output CCO; - input CI; - input CK; - output CO; - output CO37; - output CO49; - input [55:0] CZI; - output [55:0] CZO; - input [17:0] D; - output OVF; - input R; - input RZ; - input WE; - output [55:0] Z; - parameter raw_config0 = 20'b00000000000000000000; - parameter raw_config1 = 19'b0000000000000000000; - parameter raw_config2 = 13'b0000000000000; - parameter raw_config3 = 7'b0000000; - parameter std_mode = ""; -endmodule - (* blackbox *) module NX_ECC(CKD, CHK, COR, ERR); input CHK; diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index d0f5502f8..dc2e2a81c 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -333,3 +333,877 @@ module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI); .DI6(1'b0) ); endmodule + +module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO36; + output CO56; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 1'b0; + parameter ALU_MUX = 1'b0; + parameter ALU_OP = 6'b000000; + parameter CO_SEL = 1'b0; + parameter ENABLE_PR_ALU_RST = 1'b0; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 2'b00; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_ALU_MUX = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; + parameter Z_FEEDBACK_SHL12 = 1'b0; + +localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z, + MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE }; + +localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX, + PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX }; + +localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST, + ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST, + ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST }; + +localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP }; + + NX_DSP_L #( + .std_mode(""), + .raw_config0(RAW_CONFIG0_GEN), + .raw_config1(RAW_CONFIG1_GEN), + .raw_config2(RAW_CONFIG2_GEN), + .raw_config3(RAW_CONFIG3_GEN), + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + .CAI19(CAI[18]), + .CAI20(CAI[19]), + .CAI21(CAI[20]), + .CAI22(CAI[21]), + .CAI23(CAI[22]), + .CAI24(CAI[23]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + .CAO19(CAO[18]), + .CAO20(CAO[19]), + .CAO21(CAO[20]), + .CAO22(CAO[21]), + .CAO23(CAO[22]), + .CAO24(CAO[23]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO(CO), + .CO37(CO36), + .CO57(CO56), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule + +module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO57; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; + + NX_DSP_L #( + .std_mode(std_mode), + .raw_config0(raw_config0), + .raw_config1(raw_config1), + .raw_config2(raw_config2), + .raw_config3(raw_config3), + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + .CAI19(CAI[18]), + .CAI20(CAI[19]), + .CAI21(CAI[20]), + .CAI22(CAI[21]), + .CAI23(CAI[22]), + .CAI24(CAI[23]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + .CAO19(CAO[18]), + .CAO20(CAO[19]), + .CAO21(CAO[20]), + .CAO22(CAO[21]), + .CAO23(CAO[22]), + .CAO24(CAO[23]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO(CO), + .CO37(CO36), + .CO57(CO56), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule + diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v index 04c9cd667..f66bc636e 100644 --- a/techlibs/nanoxplore/cells_wrap_m.v +++ b/techlibs/nanoxplore/cells_wrap_m.v @@ -446,3 +446,402 @@ localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP }; .Z56(Z[55]) ); endmodule + +module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [17:0] CAI; + output [17:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO; + output CO37; + output CO49; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + output [55:0] Z; + parameter raw_config0 = 20'b00000000000000000000; + parameter raw_config1 = 19'b0000000000000000000; + parameter raw_config2 = 13'b0000000000000; + parameter raw_config3 = 7'b0000000; + parameter std_mode = ""; + + NX_DSP #( + .std_mode(std_mode), + .raw_config0(raw_config0), + .raw_config1(raw_config1), + .raw_config2(raw_config2), + .raw_config3(raw_config3), + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO(CO), + .CO37(CO36), + .CO49(CO48), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index ec5369906..7f7fda789 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -466,3 +466,886 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); ); endmodule +module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO42; + output CO56; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + input WEZ; + output [55:0] Z; + parameter ALU_DYNAMIC_OP = 2'b00; + parameter ALU_OP = 3'b000; + parameter ENABLE_PR_A_RST = 1'b0; + parameter ENABLE_PR_B_RST = 1'b0; + parameter ENABLE_PR_CCO_RST = 1'b0; + parameter ENABLE_PR_CI_RST = 1'b0; + parameter ENABLE_PR_CO_RST = 1'b0; + parameter ENABLE_PR_CZ_RST = 1'b0; + parameter ENABLE_PR_C_RST = 1'b0; + parameter ENABLE_PR_D_RST = 1'b0; + parameter ENABLE_PR_MULT_RST = 1'b0; + parameter ENABLE_PR_OV_RST = 1'b0; + parameter ENABLE_PR_P_RST = 1'b0; + parameter ENABLE_PR_X_RST = 1'b0; + parameter ENABLE_PR_Y_RST = 1'b0; + parameter ENABLE_PR_Z_RST = 1'b0; + parameter ENABLE_SATURATION = 1'b0; + parameter INV_RST = 1'b0; + parameter INV_RSTZ = 1'b0; + parameter INV_WE = 1'b0; + parameter INV_WEZ = 1'b0; + parameter MUX_A = 1'b0; + parameter MUX_B = 1'b0; + parameter MUX_CCI = 1'b0; + parameter MUX_CCO = 1'b0; + parameter MUX_CI = 1'b0; + parameter MUX_CZ = 1'b0; + parameter MUX_P = 1'b0; + parameter MUX_X = 3'b000; + parameter MUX_Y = 1'b0; + parameter MUX_Z = 1'b0; + parameter PRE_ADDER_OP = 1'b0; + parameter PR_A_CASCADE_MUX = 2'b00; + parameter PR_A_MUX = 2'b00; + parameter PR_B_CASCADE_MUX = 2'b00; + parameter PR_B_MUX = 2'b00; + parameter PR_CCO_MUX = 1'b0; + parameter PR_CI_MUX = 1'b0; + parameter PR_CO_MUX = 1'b0; + parameter PR_CZ_MUX = 1'b0; + parameter PR_C_MUX = 1'b0; + parameter PR_D_MUX = 1'b0; + parameter PR_MULT_MUX = 1'b0; + parameter PR_OV_MUX = 1'b0; + parameter PR_P_MUX = 1'b0; + parameter PR_RSTZ_MUX = 1'b0; + parameter PR_RST_MUX = 1'b0; + parameter PR_WEZ_MUX = 1'b0; + parameter PR_WE_MUX = 1'b0; + parameter PR_X_MUX = 1'b0; + parameter PR_Y_MUX = 1'b0; + parameter PR_Z_MUX = 1'b0; + parameter SATURATION_RANK = 6'b000000; + parameter SIGNED_MODE = 1'b0; + + localparam RAW_CONFIG0_GEN = { INV_WE, INV_WEZ, INV_RST, INV_RSTZ, MUX_CCO, ALU_DYNAMIC_OP, SATURATION_RANK, + ENABLE_SATURATION, MUX_Z, MUX_CCI, MUX_CI, MUX_Y, MUX_CZ, MUX_X, MUX_P, + MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE }; + + localparam RAW_CONFIG1_GEN = { PR_WE_MUX, PR_WEZ_MUX, PR_RST_MUX, PR_RSTZ_MUX, PR_OV_MUX, PR_CO_MUX, PR_CCO_MUX, + PR_Z_MUX, PR_CZ_MUX, PR_Y_MUX, PR_X_MUX, PR_CI_MUX, PR_MULT_MUX, PR_P_MUX, PR_D_MUX, + PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX }; + + localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_CCO_RST, ENABLE_PR_Z_RST, ENABLE_PR_CZ_RST, + ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST, + ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST }; + + localparam RAW_CONFIG3_GEN = { ALU_OP }; + + NX_DSP_U #( + .std_mode(""), + .raw_config0(RAW_CONFIG0_GEN), + .raw_config1(RAW_CONFIG1_GEN), + .raw_config2(RAW_CONFIG2_GEN), + .raw_config3(RAW_CONFIG3_GEN) + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + .CAI19(CAI[18]), + .CAI20(CAI[19]), + .CAI21(CAI[20]), + .CAI22(CAI[21]), + .CAI23(CAI[22]), + .CAI24(CAI[23]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + .CAO19(CAO[18]), + .CAO20(CAO[19]), + .CAO21(CAO[20]), + .CAO22(CAO[21]), + .CAO23(CAO[22]), + .CAO24(CAO[23]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO43(CO42), + .CO57(CO56), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + .WEZ(WEZ), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule + +module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO +, CZO); + input [23:0] A; + input [17:0] B; + input [35:0] C; + input [23:0] CAI; + output [23:0] CAO; + input [17:0] CBI; + output [17:0] CBO; + input CCI; + output CCO; + input CI; + input CK; + output CO43; + output CO57; + input [55:0] CZI; + output [55:0] CZO; + input [17:0] D; + output OVF; + input R; + input RZ; + input WE; + input WEZ; + output [55:0] Z; + parameter raw_config0 = 27'b000000000000000000000000000; + parameter raw_config1 = 24'b000000000000000000000000; + parameter raw_config2 = 14'b00000000000000; + parameter raw_config3 = 3'b000; + parameter std_mode = ""; + + NX_DSP_U #( + .std_mode(std_mode), + .raw_config0(raw_config0), + .raw_config1(raw_config1), + .raw_config2(raw_config2), + .raw_config3(raw_config3) + ) _TECHMAP_REPLACE_ ( + .A1(A[0]), + .A2(A[1]), + .A3(A[2]), + .A4(A[3]), + .A5(A[4]), + .A6(A[5]), + .A7(A[6]), + .A8(A[7]), + .A9(A[8]), + .A10(A[9]), + .A11(A[10]), + .A12(A[11]), + .A13(A[12]), + .A14(A[13]), + .A15(A[14]), + .A16(A[15]), + .A17(A[16]), + .A18(A[17]), + .A19(A[18]), + .A20(A[19]), + .A21(A[20]), + .A22(A[21]), + .A23(A[22]), + .A24(A[23]), + + .B1(B[0]), + .B2(B[1]), + .B3(B[2]), + .B4(B[3]), + .B5(B[4]), + .B6(B[5]), + .B7(B[6]), + .B8(B[7]), + .B9(B[8]), + .B10(B[9]), + .B11(B[10]), + .B12(B[11]), + .B13(B[12]), + .B14(B[13]), + .B15(B[14]), + .B16(B[15]), + .B17(B[16]), + .B18(B[17]), + + .C1(C[0]), + .C2(C[1]), + .C3(C[2]), + .C4(C[3]), + .C5(C[4]), + .C6(C[5]), + .C7(C[6]), + .C8(C[7]), + .C9(C[8]), + .C10(C[9]), + .C11(C[10]), + .C12(C[11]), + .C13(C[12]), + .C14(C[13]), + .C15(C[14]), + .C16(C[15]), + .C17(C[16]), + .C18(C[17]), + .C19(C[18]), + .C20(C[19]), + .C21(C[20]), + .C22(C[21]), + .C23(C[22]), + .C24(C[23]), + .C25(C[24]), + .C26(C[25]), + .C27(C[26]), + .C28(C[27]), + .C29(C[28]), + .C30(C[29]), + .C31(C[30]), + .C32(C[31]), + .C33(C[32]), + .C34(C[33]), + .C35(C[34]), + .C36(C[35]), + + .CAI1(CAI[0]), + .CAI2(CAI[1]), + .CAI3(CAI[2]), + .CAI4(CAI[3]), + .CAI5(CAI[4]), + .CAI6(CAI[5]), + .CAI7(CAI[6]), + .CAI8(CAI[7]), + .CAI9(CAI[8]), + .CAI10(CAI[9]), + .CAI11(CAI[10]), + .CAI12(CAI[11]), + .CAI13(CAI[12]), + .CAI14(CAI[13]), + .CAI15(CAI[14]), + .CAI16(CAI[15]), + .CAI17(CAI[16]), + .CAI18(CAI[17]), + .CAI19(CAI[18]), + .CAI20(CAI[19]), + .CAI21(CAI[20]), + .CAI22(CAI[21]), + .CAI23(CAI[22]), + .CAI24(CAI[23]), + + .CAO1(CAO[0]), + .CAO2(CAO[1]), + .CAO3(CAO[2]), + .CAO4(CAO[3]), + .CAO5(CAO[4]), + .CAO6(CAO[5]), + .CAO7(CAO[6]), + .CAO8(CAO[7]), + .CAO9(CAO[8]), + .CAO10(CAO[9]), + .CAO11(CAO[10]), + .CAO12(CAO[11]), + .CAO13(CAO[12]), + .CAO14(CAO[13]), + .CAO15(CAO[14]), + .CAO16(CAO[15]), + .CAO17(CAO[16]), + .CAO18(CAO[17]), + .CAO19(CAO[18]), + .CAO20(CAO[19]), + .CAO21(CAO[20]), + .CAO22(CAO[21]), + .CAO23(CAO[22]), + .CAO24(CAO[23]), + + .CBI1(CBI[0]), + .CBI2(CBI[1]), + .CBI3(CBI[2]), + .CBI4(CBI[3]), + .CBI5(CBI[4]), + .CBI6(CBI[5]), + .CBI7(CBI[6]), + .CBI8(CBI[7]), + .CBI9(CBI[8]), + .CBI10(CBI[9]), + .CBI11(CBI[10]), + .CBI12(CBI[11]), + .CBI13(CBI[12]), + .CBI14(CBI[13]), + .CBI15(CBI[14]), + .CBI16(CBI[15]), + .CBI17(CBI[16]), + .CBI18(CBI[17]), + + .CBO1(CBO[0]), + .CBO2(CBO[1]), + .CBO3(CBO[2]), + .CBO4(CBO[3]), + .CBO5(CBO[4]), + .CBO6(CBO[5]), + .CBO7(CBO[6]), + .CBO8(CBO[7]), + .CBO9(CBO[8]), + .CBO10(CBO[9]), + .CBO11(CBO[10]), + .CBO12(CBO[11]), + .CBO13(CBO[12]), + .CBO14(CBO[13]), + .CBO15(CBO[14]), + .CBO16(CBO[15]), + .CBO17(CBO[16]), + .CBO18(CBO[17]), + + .CCI(CCI), + .CCO(CCO), + .CI(CI), + .CK(CK), + .CO43(CO42), + .CO57(CO56), + + .CZI1(CZI[0]), + .CZI2(CZI[1]), + .CZI3(CZI[2]), + .CZI4(CZI[3]), + .CZI5(CZI[4]), + .CZI6(CZI[5]), + .CZI7(CZI[6]), + .CZI8(CZI[7]), + .CZI9(CZI[8]), + .CZI10(CZI[9]), + .CZI11(CZI[10]), + .CZI12(CZI[11]), + .CZI13(CZI[12]), + .CZI14(CZI[13]), + .CZI15(CZI[14]), + .CZI16(CZI[15]), + .CZI17(CZI[16]), + .CZI18(CZI[17]), + .CZI19(CZI[18]), + .CZI20(CZI[19]), + .CZI21(CZI[20]), + .CZI22(CZI[21]), + .CZI23(CZI[22]), + .CZI24(CZI[23]), + .CZI25(CZI[24]), + .CZI26(CZI[25]), + .CZI27(CZI[26]), + .CZI28(CZI[27]), + .CZI29(CZI[28]), + .CZI30(CZI[29]), + .CZI31(CZI[30]), + .CZI32(CZI[31]), + .CZI33(CZI[32]), + .CZI34(CZI[33]), + .CZI35(CZI[34]), + .CZI36(CZI[35]), + .CZI37(CZI[36]), + .CZI38(CZI[37]), + .CZI39(CZI[38]), + .CZI40(CZI[39]), + .CZI41(CZI[40]), + .CZI42(CZI[41]), + .CZI43(CZI[42]), + .CZI44(CZI[43]), + .CZI45(CZI[44]), + .CZI46(CZI[45]), + .CZI47(CZI[46]), + .CZI48(CZI[47]), + .CZI49(CZI[48]), + .CZI50(CZI[49]), + .CZI51(CZI[50]), + .CZI52(CZI[51]), + .CZI53(CZI[52]), + .CZI54(CZI[53]), + .CZI55(CZI[54]), + .CZI56(CZI[55]), + + .CZO1(CZO[0]), + .CZO2(CZO[1]), + .CZO3(CZO[2]), + .CZO4(CZO[3]), + .CZO5(CZO[4]), + .CZO6(CZO[5]), + .CZO7(CZO[6]), + .CZO8(CZO[7]), + .CZO9(CZO[8]), + .CZO10(CZO[9]), + .CZO11(CZO[10]), + .CZO12(CZO[11]), + .CZO13(CZO[12]), + .CZO14(CZO[13]), + .CZO15(CZO[14]), + .CZO16(CZO[15]), + .CZO17(CZO[16]), + .CZO18(CZO[17]), + .CZO19(CZO[18]), + .CZO20(CZO[19]), + .CZO21(CZO[20]), + .CZO22(CZO[21]), + .CZO23(CZO[22]), + .CZO24(CZO[23]), + .CZO25(CZO[24]), + .CZO26(CZO[25]), + .CZO27(CZO[26]), + .CZO28(CZO[27]), + .CZO29(CZO[28]), + .CZO30(CZO[29]), + .CZO31(CZO[30]), + .CZO32(CZO[31]), + .CZO33(CZO[32]), + .CZO34(CZO[33]), + .CZO35(CZO[34]), + .CZO36(CZO[35]), + .CZO37(CZO[36]), + .CZO38(CZO[37]), + .CZO39(CZO[38]), + .CZO40(CZO[39]), + .CZO41(CZO[40]), + .CZO42(CZO[41]), + .CZO43(CZO[42]), + .CZO44(CZO[43]), + .CZO45(CZO[44]), + .CZO46(CZO[45]), + .CZO47(CZO[46]), + .CZO48(CZO[47]), + .CZO49(CZO[48]), + .CZO50(CZO[49]), + .CZO51(CZO[50]), + .CZO52(CZO[51]), + .CZO53(CZO[52]), + .CZO54(CZO[53]), + .CZO55(CZO[54]), + .CZO56(CZO[55]), + + .D1(D[0]), + .D2(D[1]), + .D3(D[2]), + .D4(D[3]), + .D5(D[4]), + .D6(D[5]), + .D7(D[6]), + .D8(D[7]), + .D9(D[8]), + .D10(D[9]), + .D11(D[10]), + .D12(D[11]), + .D13(D[12]), + .D14(D[13]), + .D15(D[14]), + .D16(D[15]), + .D17(D[16]), + .D18(D[17]), + + .OVF(OVF), + .R(R), + .RZ(RZ), + .WE(WE), + .WEZ(WEZ), + + .Z1(Z[0]), + .Z2(Z[1]), + .Z3(Z[2]), + .Z4(Z[3]), + .Z5(Z[4]), + .Z6(Z[5]), + .Z7(Z[6]), + .Z8(Z[7]), + .Z9(Z[8]), + .Z10(Z[9]), + .Z11(Z[10]), + .Z12(Z[11]), + .Z13(Z[12]), + .Z14(Z[13]), + .Z15(Z[14]), + .Z16(Z[15]), + .Z17(Z[16]), + .Z18(Z[17]), + .Z19(Z[18]), + .Z20(Z[19]), + .Z21(Z[20]), + .Z22(Z[21]), + .Z23(Z[22]), + .Z24(Z[23]), + .Z25(Z[24]), + .Z26(Z[25]), + .Z27(Z[26]), + .Z28(Z[27]), + .Z29(Z[28]), + .Z30(Z[29]), + .Z31(Z[30]), + .Z32(Z[31]), + .Z33(Z[32]), + .Z34(Z[33]), + .Z35(Z[34]), + .Z36(Z[35]), + .Z37(Z[36]), + .Z38(Z[37]), + .Z39(Z[38]), + .Z40(Z[39]), + .Z41(Z[40]), + .Z42(Z[41]), + .Z43(Z[42]), + .Z44(Z[43]), + .Z45(Z[44]), + .Z46(Z[45]), + .Z47(Z[46]), + .Z48(Z[47]), + .Z49(Z[48]), + .Z50(Z[49]), + .Z51(Z[50]), + .Z52(Z[51]), + .Z53(Z[52]), + .Z54(Z[53]), + .Z55(Z[54]), + .Z56(Z[55]) + ); +endmodule \ No newline at end of file From 0ecc2e597fe149a94fdf56949ad1c2721e16fc79 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 12 Mar 2024 15:23:42 +0100 Subject: [PATCH 024/342] PLLs --- techlibs/nanoxplore/cells_bb.v | 168 ----------------------------- techlibs/nanoxplore/cells_bb_l.v | 32 ++++++ techlibs/nanoxplore/cells_bb_m.v | 23 ++++ techlibs/nanoxplore/cells_bb_u.v | 64 +++++++++++ techlibs/nanoxplore/cells_wrap_u.v | 112 ++++++++++++++++++- 5 files changed, 230 insertions(+), 169 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index f01d7571f..7b49616ce 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -5846,174 +5846,6 @@ endmodule // parameter lut_table = 16'b0000000000000000; //endmodule -(* blackbox *) -module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY); - output D1; - output D2; - output D3; - input FBK; - output OSC; - output RDY; - input REF; - output VCO; - parameter clk_outdiv1 = 0; - parameter clk_outdiv2 = 0; - parameter clk_outdiv3 = 0; - parameter ext_fbk_on = 1'b0; - parameter fbk_delay = 0; - parameter fbk_delay_on = 1'b0; - parameter fbk_div_on = 1'b0; - parameter fbk_intdiv = 2; - parameter location = ""; - parameter ref_div_on = 1'b0; - parameter vco_range = 0; -endmodule - -(* blackbox *) -module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED); - output CAL_LOCKED; - output DIVO1; - output DIVO2; - output DIVP1; - output DIVP2; - output DIVP3; - input FBK; - output LDFO; - output OSC; - output PLL_LOCKED; - input R; - input REF; - output REFO; - output VCO; - parameter cfg_use_pll = 1'b1; - parameter clk_outdivo1 = 0; - parameter clk_outdivp1 = 0; - parameter clk_outdivp2 = 0; - parameter clk_outdivp3o2 = 0; - parameter ext_fbk_on = 1'b0; - parameter fbk_delay = 0; - parameter fbk_delay_on = 1'b0; - parameter fbk_intdiv = 2; - parameter location = ""; - parameter pll_cpump = 3'b010; - parameter ref_intdiv = 0; - parameter ref_osc_on = 1'b0; - parameter wfg_sync_cal_lock = 1'b0; - parameter wfg_sync_pll_lock = 1'b0; -endmodule - -(* blackbox *) -module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV -, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5); - input ARST_CAL; - output CAL1; - output CAL2; - output CAL3; - output CAL4; - output CAL5; - output CAL_LOCKED; - input CLK_CAL; - output CLK_CAL_DIV; - output CLK_DIV1; - output CLK_DIV2; - output CLK_DIV3; - output CLK_DIV4; - output CLK_DIVD1; - output CLK_DIVD2; - output CLK_DIVD3; - output CLK_DIVD4; - output CLK_DIVD5; - input EXT_CAL1; - input EXT_CAL2; - input EXT_CAL3; - input EXT_CAL4; - input EXT_CAL5; - input EXT_CAL_LOCKED; - input FBK; - output LDFO; - output OSC; - output PLL_LOCKED; - output PLL_LOCKEDA; - input R; - input REF; - output REFO; - output VCO; - parameter cal_delay = 6'b011011; - parameter cal_div = 4'b0111; - parameter clk_cal_sel = 2'b01; - parameter clk_outdiv1 = 3'b000; - parameter clk_outdiv2 = 3'b000; - parameter clk_outdiv3 = 3'b000; - parameter clk_outdiv4 = 3'b000; - parameter clk_outdivd1 = 4'b0000; - parameter clk_outdivd2 = 4'b0000; - parameter clk_outdivd3 = 4'b0000; - parameter clk_outdivd4 = 4'b0000; - parameter clk_outdivd5 = 4'b0000; - parameter ext_fbk_on = 1'b0; - parameter fbk_delay = 6'b000000; - parameter fbk_delay_on = 1'b0; - parameter fbk_intdiv = 7'b0000000; - parameter location = ""; - parameter pll_cpump = 4'b0000; - parameter pll_lock = 4'b0000; - parameter pll_lpf_cap = 4'b0000; - parameter pll_lpf_res = 4'b0000; - parameter pll_odf = 2'b00; - parameter ref_intdiv = 5'b00000; - parameter ref_osc_on = 1'b0; - parameter use_cal = 1'b0; - parameter use_pll = 1'b1; -endmodule - -(* blackbox *) -module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV); - input ARST_CAL; - output [4:0] CAL; - output CAL_LOCKED; - input CLK_CAL; - output CLK_CAL_DIV; - output [3:0] CLK_DIV; - output [4:0] CLK_DIVD; - input [4:0] EXT_CAL; - input EXT_CAL_LOCKED; - input FBK; - output LDFO; - output OSC; - output PLL_LOCKED; - output PLL_LOCKEDA; - input R; - input REF; - output REFO; - output VCO; - parameter cal_delay = 6'b011011; - parameter cal_div = 4'b0111; - parameter clk_cal_sel = 2'b01; - parameter clk_outdiv1 = 3'b000; - parameter clk_outdiv2 = 3'b000; - parameter clk_outdiv3 = 3'b000; - parameter clk_outdiv4 = 3'b000; - parameter clk_outdivd1 = 4'b0000; - parameter clk_outdivd2 = 4'b0000; - parameter clk_outdivd3 = 4'b0000; - parameter clk_outdivd4 = 4'b0000; - parameter clk_outdivd5 = 4'b0000; - parameter ext_fbk_on = 1'b0; - parameter fbk_delay = 6'b000000; - parameter fbk_delay_on = 1'b0; - parameter fbk_intdiv = 7'b0000000; - parameter location = ""; - parameter pll_cpump = 4'b0000; - parameter pll_lock = 4'b0000; - parameter pll_lpf_cap = 4'b0000; - parameter pll_lpf_res = 4'b0000; - parameter pll_odf = 2'b00; - parameter ref_intdiv = 5'b00000; - parameter ref_osc_on = 1'b0; - parameter use_cal = 1'b0; - parameter use_pll = 1'b1; -endmodule - (* blackbox *) module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2 , MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3 diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index a3a11a06c..991600e65 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -469,3 +469,35 @@ module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 parameter std_mode = ""; endmodule +(* blackbox *) +module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED); + output CAL_LOCKED; + output DIVO1; + output DIVO2; + output DIVP1; + output DIVP2; + output DIVP3; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + input R; + input REF; + output REFO; + output VCO; + parameter cfg_use_pll = 1'b1; + parameter clk_outdivo1 = 0; + parameter clk_outdivp1 = 0; + parameter clk_outdivp2 = 0; + parameter clk_outdivp3o2 = 0; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 0; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 2; + parameter location = ""; + parameter pll_cpump = 3'b010; + parameter ref_intdiv = 0; + parameter ref_osc_on = 1'b0; + parameter wfg_sync_cal_lock = 1'b0; + parameter wfg_sync_pll_lock = 1'b0; +endmodule diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index e54c1fd8a..0be57e720 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -378,3 +378,26 @@ module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, parameter std_mode = ""; endmodule +(* blackbox *) +module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY); + output D1; + output D2; + output D3; + input FBK; + output OSC; + output RDY; + input REF; + output VCO; + parameter clk_outdiv1 = 0; + parameter clk_outdiv2 = 0; + parameter clk_outdiv3 = 0; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 0; + parameter fbk_delay_on = 1'b0; + parameter fbk_div_on = 1'b0; + parameter fbk_intdiv = 2; + parameter location = ""; + parameter ref_div_on = 1'b0; + parameter vco_range = 0; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 657cd6667..988ddb4c5 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -485,3 +485,67 @@ module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 parameter raw_config3 = 3'b000; parameter std_mode = ""; endmodule + +(* blackbox *) +module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV +, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5); + input ARST_CAL; + output CAL1; + output CAL2; + output CAL3; + output CAL4; + output CAL5; + output CAL_LOCKED; + input CLK_CAL; + output CLK_CAL_DIV; + output CLK_DIV1; + output CLK_DIV2; + output CLK_DIV3; + output CLK_DIV4; + output CLK_DIVD1; + output CLK_DIVD2; + output CLK_DIVD3; + output CLK_DIVD4; + output CLK_DIVD5; + input EXT_CAL1; + input EXT_CAL2; + input EXT_CAL3; + input EXT_CAL4; + input EXT_CAL5; + input EXT_CAL_LOCKED; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + output PLL_LOCKEDA; + input R; + input REF; + output REFO; + output VCO; + parameter cal_delay = 6'b011011; + parameter cal_div = 4'b0111; + parameter clk_cal_sel = 2'b01; + parameter clk_outdiv1 = 3'b000; + parameter clk_outdiv2 = 3'b000; + parameter clk_outdiv3 = 3'b000; + parameter clk_outdiv4 = 3'b000; + parameter clk_outdivd1 = 4'b0000; + parameter clk_outdivd2 = 4'b0000; + parameter clk_outdivd3 = 4'b0000; + parameter clk_outdivd4 = 4'b0000; + parameter clk_outdivd5 = 4'b0000; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 6'b000000; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 7'b0000000; + parameter location = ""; + parameter pll_cpump = 4'b0000; + parameter pll_lock = 4'b0000; + parameter pll_lpf_cap = 4'b0000; + parameter pll_lpf_res = 4'b0000; + parameter pll_odf = 2'b00; + parameter ref_intdiv = 5'b00000; + parameter ref_osc_on = 1'b0; + parameter use_cal = 1'b0; + parameter use_pll = 1'b1; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index 7f7fda789..be5561c3e 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -1348,4 +1348,114 @@ module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, .Z55(Z[54]), .Z56(Z[55]) ); -endmodule \ No newline at end of file +endmodule + +module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV); + input ARST_CAL; + output [4:0] CAL; + output CAL_LOCKED; + input CLK_CAL; + output CLK_CAL_DIV; + output [3:0] CLK_DIV; + output [4:0] CLK_DIVD; + input [4:0] EXT_CAL; + input EXT_CAL_LOCKED; + input FBK; + output LDFO; + output OSC; + output PLL_LOCKED; + output PLL_LOCKEDA; + input R; + input REF; + output REFO; + output VCO; + parameter cal_delay = 6'b011011; + parameter cal_div = 4'b0111; + parameter clk_cal_sel = 2'b01; + parameter clk_outdiv1 = 3'b000; + parameter clk_outdiv2 = 3'b000; + parameter clk_outdiv3 = 3'b000; + parameter clk_outdiv4 = 3'b000; + parameter clk_outdivd1 = 4'b0000; + parameter clk_outdivd2 = 4'b0000; + parameter clk_outdivd3 = 4'b0000; + parameter clk_outdivd4 = 4'b0000; + parameter clk_outdivd5 = 4'b0000; + parameter ext_fbk_on = 1'b0; + parameter fbk_delay = 6'b000000; + parameter fbk_delay_on = 1'b0; + parameter fbk_intdiv = 7'b0000000; + parameter location = ""; + parameter pll_cpump = 4'b0000; + parameter pll_lock = 4'b0000; + parameter pll_lpf_cap = 4'b0000; + parameter pll_lpf_res = 4'b0000; + parameter pll_odf = 2'b00; + parameter ref_intdiv = 5'b00000; + parameter ref_osc_on = 1'b0; + parameter use_cal = 1'b0; + parameter use_pll = 1'b1; + + NX_PLL_U #( + .cal_delay(cal_delay), + .cal_div(cal_div), + .clk_cal_sel(clk_cal_sel), + .clk_outdiv1(clk_outdiv1), + .clk_outdiv2(clk_outdiv2), + .clk_outdiv3(clk_outdiv3), + .clk_outdiv4(clk_outdiv4), + .clk_outdivd1(clk_outdivd1), + .clk_outdivd2(clk_outdivd2), + .clk_outdivd3(clk_outdivd3), + .clk_outdivd4(clk_outdivd4), + .clk_outdivd5(clk_outdivd5), + .ext_fbk_on(ext_fbk_on), + .fbk_delay(fbk_delay), + .fbk_delay_on(fbk_delay_on), + .fbk_intdiv(fbk_intdiv), + .location(location), + .pll_cpump(pll_cpump), + .pll_lock(pll_lock), + .pll_lpf_cap(pll_lpf_cap), + .pll_lpf_res(pll_lpf_res), + .pll_odf(pll_odf), + .ref_intdiv(ref_intdiv), + .ref_osc_on(ref_osc_on), + .use_cal(use_cal), + .use_pll(use_pll) + ) _TECHMAP_REPLACE_ ( + .ARST_CAL(ARST_CAL), + .CAL1(CAL[0]), + .CAL2(CAL[1]), + .CAL3(CAL[2]), + .CAL4(CAL[3]), + .CAL5(CAL[4]), + .CAL_LOCKED(CAL_LOCKED), + .CLK_CAL(CLK_CAL), + .CLK_CAL_DIV(CLK_CAL_DIV), + .CLK_DIV1(CLK_DIV[0]), + .CLK_DIV2(CLK_DIV[1]), + .CLK_DIV3(CLK_DIV[2]), + .CLK_DIV4(CLK_DIV[3]), + .CLK_DIVD1(CLK_DIVD[0]), + .CLK_DIVD2(CLK_DIVD[1]), + .CLK_DIVD3(CLK_DIVD[2]), + .CLK_DIVD4(CLK_DIVD[3]), + .CLK_DIVD5(CLK_DIVD[4]), + .EXT_CAL1(EXT_CAL[0]), + .EXT_CAL2(EXT_CAL[1]), + .EXT_CAL3(EXT_CAL[2]), + .EXT_CAL4(EXT_CAL[3]), + .EXT_CAL5(EXT_CAL[4]), + .EXT_CAL_LOCKED(EXT_CAL_LOCKED), + .FBK(FBK), + .LDFO(LDFO), + .OSC(OSC), + .PLL_LOCKED(PLL_LOCKED), + .PLL_LOCKEDA(PLL_LOCKEDA), + .R(R), + .REF(REF), + .REFO(REFO), + .VCO(VCO) + ); +endmodule From 3ed5ea24b2144ec076350e2ae84abb1846d92e12 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 12 Mar 2024 16:45:46 +0100 Subject: [PATCH 025/342] sortout more blackboxes --- techlibs/nanoxplore/cells_bb.v | 4065 ------------------------------ techlibs/nanoxplore/cells_bb_l.v | 1441 +++++++++++ techlibs/nanoxplore/cells_bb_m.v | 828 ++++++ techlibs/nanoxplore/cells_bb_u.v | 1800 +++++++++++++ 4 files changed, 4069 insertions(+), 4065 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 7b49616ce..6b46317af 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -70,702 +70,6 @@ module NX_BFR(I, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 -, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 -, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45 -, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2 -, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7 -, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4 -, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK); - input ALIGN_E_I; - output ALIGN_O; - input ALIGN_S_I; - input BUF_FE_I; - input BUF_R_I; - output BUSY_O; - input CDR_R_I; - output CH_A_O1; - output CH_A_O2; - output CH_A_O3; - output CH_A_O4; - output CH_A_O5; - output CH_A_O6; - output CH_A_O7; - output CH_A_O8; - output CH_COM_O1; - output CH_COM_O2; - output CH_COM_O3; - output CH_COM_O4; - output CH_COM_O5; - output CH_COM_O6; - output CH_COM_O7; - output CH_COM_O8; - output CH_F_O1; - output CH_F_O2; - output CH_F_O3; - output CH_F_O4; - output CH_F_O5; - output CH_F_O6; - output CH_F_O7; - output CH_F_O8; - output CH_K_O1; - output CH_K_O2; - output CH_K_O3; - output CH_K_O4; - output CH_K_O5; - output CH_K_O6; - output CH_K_O7; - output CH_K_O8; - input CKG_RN_I; - output DATA_O1; - output DATA_O10; - output DATA_O11; - output DATA_O12; - output DATA_O13; - output DATA_O14; - output DATA_O15; - output DATA_O16; - output DATA_O17; - output DATA_O18; - output DATA_O19; - output DATA_O2; - output DATA_O20; - output DATA_O21; - output DATA_O22; - output DATA_O23; - output DATA_O24; - output DATA_O25; - output DATA_O26; - output DATA_O27; - output DATA_O28; - output DATA_O29; - output DATA_O3; - output DATA_O30; - output DATA_O31; - output DATA_O32; - output DATA_O33; - output DATA_O34; - output DATA_O35; - output DATA_O36; - output DATA_O37; - output DATA_O38; - output DATA_O39; - output DATA_O4; - output DATA_O40; - output DATA_O41; - output DATA_O42; - output DATA_O43; - output DATA_O44; - output DATA_O45; - output DATA_O46; - output DATA_O47; - output DATA_O48; - output DATA_O49; - output DATA_O5; - output DATA_O50; - output DATA_O51; - output DATA_O52; - output DATA_O53; - output DATA_O54; - output DATA_O55; - output DATA_O56; - output DATA_O57; - output DATA_O58; - output DATA_O59; - output DATA_O6; - output DATA_O60; - output DATA_O61; - output DATA_O62; - output DATA_O63; - output DATA_O64; - output DATA_O7; - output DATA_O8; - output DATA_O9; - input DEC_E_I; - input DSCR_E_I; - output D_ERR_O1; - output D_ERR_O2; - output D_ERR_O3; - output D_ERR_O4; - output D_ERR_O5; - output D_ERR_O6; - output D_ERR_O7; - output D_ERR_O8; - inout [9:0] LINK; - output LOCK_O; - output LOS_O; - output NIT_O1; - output NIT_O2; - output NIT_O3; - output NIT_O4; - output NIT_O5; - output NIT_O6; - output NIT_O7; - output NIT_O8; - input OVS_BS_I1; - input OVS_BS_I2; - input PLL_RN_I; - input REP_E_I; - input RST_N_I; - input RX_I; - input TST_I1; - input TST_I2; - input TST_I3; - input TST_I4; - output TST_O1; - output TST_O2; - output TST_O3; - output TST_O4; - output TST_O5; - output TST_O6; - output TST_O7; - output TST_O8; - parameter location = ""; - parameter pcs_8b_dscr_sel = 1'b0; - parameter pcs_align_bypass = 1'b0; - parameter pcs_buffers_bypass = 1'b0; - parameter pcs_buffers_use_cdc = 1'b0; - parameter pcs_bypass_pma_cdc = 1'b0; - parameter pcs_bypass_usr_cdc = 1'b0; - parameter pcs_comma_mask = 10'b0000000000; - parameter pcs_debug_en = 1'b0; - parameter pcs_dec_bypass = 1'b0; - parameter pcs_dscr_bypass = 1'b0; - parameter pcs_el_buff_diff_bef_comp = 3'b000; - parameter pcs_el_buff_max_comp = 3'b000; - parameter pcs_el_buff_only_one_skp = 1'b0; - parameter pcs_el_buff_skp_char_0 = 9'b000000000; - parameter pcs_el_buff_skp_char_1 = 9'b000000000; - parameter pcs_el_buff_skp_char_2 = 9'b000000000; - parameter pcs_el_buff_skp_char_3 = 9'b000000000; - parameter pcs_el_buff_skp_header_0 = 9'b000000000; - parameter pcs_el_buff_skp_header_1 = 9'b000000000; - parameter pcs_el_buff_skp_header_2 = 9'b000000000; - parameter pcs_el_buff_skp_header_3 = 9'b000000000; - parameter pcs_el_buff_skp_header_size = 2'b00; - parameter pcs_el_buff_skp_seq_size = 2'b00; - parameter pcs_el_buff_underflow_handle = 1'b0; - parameter pcs_fsm_sel = 2'b00; - parameter pcs_fsm_watchdog_en = 1'b0; - parameter pcs_loopback = 1'b0; - parameter pcs_m_comma_en = 1'b0; - parameter pcs_m_comma_val = 10'b0000000000; - parameter pcs_nb_comma_bef_realign = 2'b00; - parameter pcs_p_comma_en = 1'b0; - parameter pcs_p_comma_val = 10'b0000000000; - parameter pcs_polarity = 1'b0; - parameter pcs_protocol_size = 1'b0; - parameter pcs_replace_bypass = 1'b0; - parameter pcs_sync_supported = 1'b0; - parameter pma_cdr_cp = 4'b0000; - parameter pma_clk_pos = 1'b0; - parameter pma_ctrl_term = 6'b000000; - parameter pma_loopback = 1'b0; - parameter pma_pll_cpump_n = 3'b000; - parameter pma_pll_divf = 2'b00; - parameter pma_pll_divf_en_n = 1'b0; - parameter pma_pll_divm = 2'b00; - parameter pma_pll_divm_en_n = 1'b0; - parameter pma_pll_divn = 1'b0; - parameter pma_pll_divn_en_n = 1'b0; - parameter test = 2'b00; -endmodule - -(* blackbox *) -module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6 -, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27 -, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48 -, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5 -, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2 -, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7 -, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK); - input ALIGN_E_I; - output ALIGN_O; - input ALIGN_S_I; - input BUF_R_I; - output BUSY_O; - output CH_A_O1; - output CH_A_O2; - output CH_A_O3; - output CH_A_O4; - output CH_A_O5; - output CH_A_O6; - output CH_A_O7; - output CH_A_O8; - output CH_COM_O1; - output CH_COM_O2; - output CH_COM_O3; - output CH_COM_O4; - output CH_COM_O5; - output CH_COM_O6; - output CH_COM_O7; - output CH_COM_O8; - output CH_F_O1; - output CH_F_O2; - output CH_F_O3; - output CH_F_O4; - output CH_F_O5; - output CH_F_O6; - output CH_F_O7; - output CH_F_O8; - output CH_K_O1; - output CH_K_O2; - output CH_K_O3; - output CH_K_O4; - output CH_K_O5; - output CH_K_O6; - output CH_K_O7; - output CH_K_O8; - output DATA_O1; - output DATA_O10; - output DATA_O11; - output DATA_O12; - output DATA_O13; - output DATA_O14; - output DATA_O15; - output DATA_O16; - output DATA_O17; - output DATA_O18; - output DATA_O19; - output DATA_O2; - output DATA_O20; - output DATA_O21; - output DATA_O22; - output DATA_O23; - output DATA_O24; - output DATA_O25; - output DATA_O26; - output DATA_O27; - output DATA_O28; - output DATA_O29; - output DATA_O3; - output DATA_O30; - output DATA_O31; - output DATA_O32; - output DATA_O33; - output DATA_O34; - output DATA_O35; - output DATA_O36; - output DATA_O37; - output DATA_O38; - output DATA_O39; - output DATA_O4; - output DATA_O40; - output DATA_O41; - output DATA_O42; - output DATA_O43; - output DATA_O44; - output DATA_O45; - output DATA_O46; - output DATA_O47; - output DATA_O48; - output DATA_O49; - output DATA_O5; - output DATA_O50; - output DATA_O51; - output DATA_O52; - output DATA_O53; - output DATA_O54; - output DATA_O55; - output DATA_O56; - output DATA_O57; - output DATA_O58; - output DATA_O59; - output DATA_O6; - output DATA_O60; - output DATA_O61; - output DATA_O62; - output DATA_O63; - output DATA_O64; - output DATA_O7; - output DATA_O8; - output DATA_O9; - input DBG_S_I1; - input DBG_S_I2; - input DBG_S_I3; - input DEC_E_I; - input DSCR_E_I; - output D_ERR_O1; - output D_ERR_O2; - output D_ERR_O3; - output D_ERR_O4; - output D_ERR_O5; - output D_ERR_O6; - output D_ERR_O7; - output D_ERR_O8; - inout [9:0] LINK; - output LL_FLOCK_O; - output LL_SLOCK_O; - output LOS_O; - input MEYE_RST_I; - output NIT_O1; - output NIT_O2; - output NIT_O3; - output NIT_O4; - output NIT_O5; - output NIT_O6; - output NIT_O7; - output NIT_O8; - input OVS_BS_I1; - input OVS_BS_I2; - output PLL_LOCKT_O; - output PLL_LOCK_O; - input PMA_RSTN_I; - input PWDN_N_I; - input REP_E_I; - input RST_N_I; - output TST_O1; - output TST_O2; - output TST_O3; - output TST_O4; - output TST_O5; - output TST_O6; - output TST_O7; - output TST_O8; - output VREALIGN_O; - parameter gearbox_en = 1'b0; - parameter gearbox_mode = 1'b0; - parameter location = ""; - parameter pcs_8b_dscr_sel = 1'b0; - parameter pcs_align_bypass = 1'b0; - parameter pcs_buffers_bypass = 1'b0; - parameter pcs_buffers_use_cdc = 1'b0; - parameter pcs_bypass_pma_cdc = 1'b0; - parameter pcs_bypass_usr_cdc = 1'b0; - parameter pcs_comma_mask = 10'b0000000000; - parameter pcs_debug_en = 1'b0; - parameter pcs_dec_bypass = 1'b0; - parameter pcs_dscr_bypass = 1'b0; - parameter pcs_el_buff_diff_bef_comp = 4'b0000; - parameter pcs_el_buff_max_comp = 4'b0000; - parameter pcs_el_buff_only_one_skp = 1'b0; - parameter pcs_el_buff_skp_char_0 = 9'b000000000; - parameter pcs_el_buff_skp_char_1 = 9'b000000000; - parameter pcs_el_buff_skp_char_2 = 9'b000000000; - parameter pcs_el_buff_skp_char_3 = 9'b000000000; - parameter pcs_el_buff_skp_header_0 = 9'b000000000; - parameter pcs_el_buff_skp_header_1 = 9'b000000000; - parameter pcs_el_buff_skp_header_2 = 9'b000000000; - parameter pcs_el_buff_skp_header_3 = 9'b000000000; - parameter pcs_el_buff_skp_header_size = 2'b00; - parameter pcs_el_buff_skp_seq_size = 2'b00; - parameter pcs_fsm_sel = 2'b00; - parameter pcs_fsm_watchdog_en = 1'b0; - parameter pcs_loopback = 1'b0; - parameter pcs_m_comma_en = 1'b0; - parameter pcs_m_comma_val = 10'b0000000000; - parameter pcs_nb_comma_bef_realign = 2'b00; - parameter pcs_p_comma_en = 1'b0; - parameter pcs_p_comma_val = 10'b0000000000; - parameter pcs_polarity = 1'b0; - parameter pcs_protocol_size = 1'b0; - parameter pcs_replace_bypass = 1'b0; - parameter pcs_sync_supported = 1'b0; - parameter pma_cdr_cp = 4'b0000; - parameter pma_clk_pos = 1'b0; - parameter pma_coarse_ppm = 3'b000; - parameter pma_ctrl_term = 6'b000000; - parameter pma_dco_divl = 2'b00; - parameter pma_dco_divm = 1'b0; - parameter pma_dco_divn = 2'b00; - parameter pma_dco_reg_res = 2'b00; - parameter pma_dco_vref_sel = 1'b0; - parameter pma_fine_ppm = 3'b000; - parameter pma_loopback = 1'b0; - parameter pma_m_eye_ppm = 3'b000; - parameter pma_peak_detect_cmd = 2'b00; - parameter pma_peak_detect_on = 1'b0; - parameter pma_pll_cpump_n = 3'b000; - parameter pma_pll_divf = 2'b00; - parameter pma_pll_divf_en_n = 1'b0; - parameter pma_pll_divm = 2'b00; - parameter pma_pll_divm_en_n = 1'b0; - parameter pma_pll_divn = 1'b0; - parameter pma_pll_divn_en_n = 1'b0; -endmodule - -(* blackbox *) -module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 -, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I -, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17 -, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38 -, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59 -, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK); - output BUSY_O; - input CH_K_I1; - input CH_K_I2; - input CH_K_I3; - input CH_K_I4; - input CH_K_I5; - input CH_K_I6; - input CH_K_I7; - input CH_K_I8; - input CLK_E_I; - input DATA_I1; - input DATA_I10; - input DATA_I11; - input DATA_I12; - input DATA_I13; - input DATA_I14; - input DATA_I15; - input DATA_I16; - input DATA_I17; - input DATA_I18; - input DATA_I19; - input DATA_I2; - input DATA_I20; - input DATA_I21; - input DATA_I22; - input DATA_I23; - input DATA_I24; - input DATA_I25; - input DATA_I26; - input DATA_I27; - input DATA_I28; - input DATA_I29; - input DATA_I3; - input DATA_I30; - input DATA_I31; - input DATA_I32; - input DATA_I33; - input DATA_I34; - input DATA_I35; - input DATA_I36; - input DATA_I37; - input DATA_I38; - input DATA_I39; - input DATA_I4; - input DATA_I40; - input DATA_I41; - input DATA_I42; - input DATA_I43; - input DATA_I44; - input DATA_I45; - input DATA_I46; - input DATA_I47; - input DATA_I48; - input DATA_I49; - input DATA_I5; - input DATA_I50; - input DATA_I51; - input DATA_I52; - input DATA_I53; - input DATA_I54; - input DATA_I55; - input DATA_I56; - input DATA_I57; - input DATA_I58; - input DATA_I59; - input DATA_I6; - input DATA_I60; - input DATA_I61; - input DATA_I62; - input DATA_I63; - input DATA_I64; - input DATA_I7; - input DATA_I8; - input DATA_I9; - input ENC_E_I1; - input ENC_E_I2; - input ENC_E_I3; - input ENC_E_I4; - input ENC_E_I5; - input ENC_E_I6; - input ENC_E_I7; - input ENC_E_I8; - input EOF_I1; - input EOF_I2; - input EOF_I3; - input EOF_I4; - input EOF_I5; - input EOF_I6; - input EOF_I7; - input EOF_I8; - input EOMF_I1; - input EOMF_I2; - input EOMF_I3; - input EOMF_I4; - input EOMF_I5; - input EOMF_I6; - input EOMF_I7; - input EOMF_I8; - inout [19:0] LINK; - input REP_E_I; - input RST_N_I; - input SCR_E_I1; - input SCR_E_I2; - input SCR_E_I3; - input SCR_E_I4; - input SCR_E_I5; - input SCR_E_I6; - input SCR_E_I7; - input SCR_E_I8; - input TST_I1; - input TST_I2; - input TST_I3; - input TST_I4; - output TST_O1; - output TST_O2; - output TST_O3; - output TST_O4; - output TX_O; - parameter location = ""; - parameter pcs_8b_scr_sel = 1'b0; - parameter pcs_bypass_pma_cdc = 1'b0; - parameter pcs_bypass_usr_cdc = 1'b0; - parameter pcs_enc_bypass = 1'b0; - parameter pcs_esistream_fsm_en = 1'b0; - parameter pcs_loopback = 1'b0; - parameter pcs_polarity = 1'b0; - parameter pcs_protocol_size = 1'b0; - parameter pcs_replace_bypass = 1'b0; - parameter pcs_scr_bypass = 1'b0; - parameter pcs_scr_init = 17'b00000000000000000; - parameter pcs_sync_supported = 1'b0; - parameter pma_clk_pos = 1'b0; - parameter pma_loopback = 1'b0; - parameter test = 2'b00; -endmodule - -(* blackbox *) -module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 -, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I -, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21 -, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42 -, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63 -, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK); - output BUSY_O; - input CH_K_I1; - input CH_K_I2; - input CH_K_I3; - input CH_K_I4; - input CH_K_I5; - input CH_K_I6; - input CH_K_I7; - input CH_K_I8; - input CLK_E_I; - output CLK_O; - input DATA_I1; - input DATA_I10; - input DATA_I11; - input DATA_I12; - input DATA_I13; - input DATA_I14; - input DATA_I15; - input DATA_I16; - input DATA_I17; - input DATA_I18; - input DATA_I19; - input DATA_I2; - input DATA_I20; - input DATA_I21; - input DATA_I22; - input DATA_I23; - input DATA_I24; - input DATA_I25; - input DATA_I26; - input DATA_I27; - input DATA_I28; - input DATA_I29; - input DATA_I3; - input DATA_I30; - input DATA_I31; - input DATA_I32; - input DATA_I33; - input DATA_I34; - input DATA_I35; - input DATA_I36; - input DATA_I37; - input DATA_I38; - input DATA_I39; - input DATA_I4; - input DATA_I40; - input DATA_I41; - input DATA_I42; - input DATA_I43; - input DATA_I44; - input DATA_I45; - input DATA_I46; - input DATA_I47; - input DATA_I48; - input DATA_I49; - input DATA_I5; - input DATA_I50; - input DATA_I51; - input DATA_I52; - input DATA_I53; - input DATA_I54; - input DATA_I55; - input DATA_I56; - input DATA_I57; - input DATA_I58; - input DATA_I59; - input DATA_I6; - input DATA_I60; - input DATA_I61; - input DATA_I62; - input DATA_I63; - input DATA_I64; - input DATA_I7; - input DATA_I8; - input DATA_I9; - input ENC_E_I1; - input ENC_E_I2; - input ENC_E_I3; - input ENC_E_I4; - input ENC_E_I5; - input ENC_E_I6; - input ENC_E_I7; - input ENC_E_I8; - input EOF_I1; - input EOF_I2; - input EOF_I3; - input EOF_I4; - input EOF_I5; - input EOF_I6; - input EOF_I7; - input EOF_I8; - input EOMF_I1; - input EOMF_I2; - input EOMF_I3; - input EOMF_I4; - input EOMF_I5; - input EOMF_I6; - input EOMF_I7; - input EOMF_I8; - output INV_K_O; - inout [19:0] LINK; - input PWDN_N_I; - input REP_E_I; - input RST_N_I; - input SCR_E_I1; - input SCR_E_I2; - input SCR_E_I3; - input SCR_E_I4; - input SCR_E_I5; - input SCR_E_I6; - input SCR_E_I7; - input SCR_E_I8; - parameter gearbox_en = 1'b0; - parameter gearbox_mode = 1'b0; - parameter location = ""; - parameter pcs_8b_scr_sel = 1'b0; - parameter pcs_bypass_pma_cdc = 1'b0; - parameter pcs_bypass_usr_cdc = 1'b0; - parameter pcs_enc_bypass = 1'b0; - parameter pcs_esistream_fsm_en = 1'b0; - parameter pcs_loopback = 1'b0; - parameter pcs_polarity = 1'b0; - parameter pcs_protocol_size = 1'b0; - parameter pcs_replace_bypass = 1'b0; - parameter pcs_scr_bypass = 1'b0; - parameter pcs_scr_init = 17'b00000000000000000; - parameter pcs_sync_supported = 1'b0; - parameter pma_clk_pos = 1'b0; - parameter pma_loopback = 1'b0; -endmodule - //(* blackbox *) //module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4); // input A1; @@ -2000,817 +1304,6 @@ module NX_IOB_O(I, C, T, IO); parameter weakTermination = ""; endmodule -(* blackbox *) -module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 -, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4 -, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3 -, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3 -, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR -, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL -, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI -, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO -, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3 -, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2 -, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1 -, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO -, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI -, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO -, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR -, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL -, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1 -, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5 -, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4 -, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3 -, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2 -, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1 -, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR -, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL -, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI -, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO -, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER -, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL -, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5 -, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO -, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI -, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO -, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR -, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL -, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1 -, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5 -); - output C1RED; - input C1RNE; - input C1RS; - input C1RW1; - input C1RW2; - input C1RW3; - input C1TS; - input C1TW; - output C2RED; - input C2RNE; - input C2RS; - input C2RW1; - input C2RW2; - input C2RW3; - input C2TS; - input C2TW; - input CAD1; - input CAD2; - input CAD3; - input CAD4; - input CAD5; - input CAD6; - output CAL; - input CAN1; - input CAN2; - input CAN3; - input CAN4; - input CAP1; - input CAP2; - input CAP3; - input CAP4; - input CAT1; - input CAT2; - input CAT3; - input CAT4; - input CCK; - output CKO1; - output CKO2; - input CTCK; - input DC; - input DCK; - input DIG; - input DIS; - input DOG; - input DOS; - input DPAG; - input DPAS; - input DQSG; - input DQSS; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRA5; - input DRI1; - input DRI2; - input DRI3; - input DRI4; - input DRI5; - input DRI6; - input DRL; - output DRO1; - output DRO2; - output DRO3; - output DRO4; - output DRO5; - output DRO6; - input DS1; - input DS2; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - output FLD; - output FLG; - input FZ; - input P10CI1; - input P10CL; - output P10CO; - input P10CR; - input P10CTI; - output P10CTO; - input P10EI1; - input P10EI2; - input P10EI3; - input P10EI4; - input P10EI5; - input P10EL; - output P10EO; - input P10ER; - input P10RI; - input P10RL; - output P10RO1; - output P10RO2; - output P10RO3; - output P10RO4; - output P10RO5; - input P10RR; - input P11CI1; - input P11CL; - output P11CO; - input P11CR; - input P11CTI; - output P11CTO; - input P11EI1; - input P11EI2; - input P11EI3; - input P11EI4; - input P11EI5; - input P11EL; - output P11EO; - input P11ER; - input P11RI; - input P11RL; - output P11RO1; - output P11RO2; - output P11RO3; - output P11RO4; - output P11RO5; - input P11RR; - input P12CI1; - input P12CL; - output P12CO; - input P12CR; - input P12CTI; - output P12CTO; - input P12EI1; - input P12EI2; - input P12EI3; - input P12EI4; - input P12EI5; - input P12EL; - output P12EO; - input P12ER; - input P12RI; - input P12RL; - output P12RO1; - output P12RO2; - output P12RO3; - output P12RO4; - output P12RO5; - input P12RR; - input P13CI1; - input P13CL; - output P13CO; - input P13CR; - input P13CTI; - output P13CTO; - input P13EI1; - input P13EI2; - input P13EI3; - input P13EI4; - input P13EI5; - input P13EL; - output P13EO; - input P13ER; - input P13RI; - input P13RL; - output P13RO1; - output P13RO2; - output P13RO3; - output P13RO4; - output P13RO5; - input P13RR; - input P14CI1; - input P14CL; - output P14CO; - input P14CR; - input P14CTI; - output P14CTO; - input P14EI1; - input P14EI2; - input P14EI3; - input P14EI4; - input P14EI5; - input P14EL; - output P14EO; - input P14ER; - input P14RI; - input P14RL; - output P14RO1; - output P14RO2; - output P14RO3; - output P14RO4; - output P14RO5; - input P14RR; - input P15CI1; - input P15CL; - output P15CO; - input P15CR; - input P15CTI; - output P15CTO; - input P15EI1; - input P15EI2; - input P15EI3; - input P15EI4; - input P15EI5; - input P15EL; - output P15EO; - input P15ER; - input P15RI; - input P15RL; - output P15RO1; - output P15RO2; - output P15RO3; - output P15RO4; - output P15RO5; - input P15RR; - input P16CI1; - input P16CL; - output P16CO; - input P16CR; - input P16CTI; - output P16CTO; - input P16EI1; - input P16EI2; - input P16EI3; - input P16EI4; - input P16EI5; - input P16EL; - output P16EO; - input P16ER; - input P16RI; - input P16RL; - output P16RO1; - output P16RO2; - output P16RO3; - output P16RO4; - output P16RO5; - input P16RR; - input P17CI1; - input P17CL; - output P17CO; - input P17CR; - input P17CTI; - output P17CTO; - input P17EI1; - input P17EI2; - input P17EI3; - input P17EI4; - input P17EI5; - input P17EL; - output P17EO; - input P17ER; - input P17RI; - input P17RL; - output P17RO1; - output P17RO2; - output P17RO3; - output P17RO4; - output P17RO5; - input P17RR; - input P18CI1; - input P18CL; - output P18CO; - input P18CR; - input P18CTI; - output P18CTO; - input P18EI1; - input P18EI2; - input P18EI3; - input P18EI4; - input P18EI5; - input P18EL; - output P18EO; - input P18ER; - input P18RI; - input P18RL; - output P18RO1; - output P18RO2; - output P18RO3; - output P18RO4; - output P18RO5; - input P18RR; - input P19CI1; - input P19CL; - output P19CO; - input P19CR; - input P19CTI; - output P19CTO; - input P19EI1; - input P19EI2; - input P19EI3; - input P19EI4; - input P19EI5; - input P19EL; - output P19EO; - input P19ER; - input P19RI; - input P19RL; - output P19RO1; - output P19RO2; - output P19RO3; - output P19RO4; - output P19RO5; - input P19RR; - input P1CI1; - input P1CL; - output P1CO; - input P1CR; - input P1CTI; - output P1CTO; - input P1EI1; - input P1EI2; - input P1EI3; - input P1EI4; - input P1EI5; - input P1EL; - output P1EO; - input P1ER; - input P1RI; - input P1RL; - output P1RO1; - output P1RO2; - output P1RO3; - output P1RO4; - output P1RO5; - input P1RR; - input P20CI1; - input P20CL; - output P20CO; - input P20CR; - input P20CTI; - output P20CTO; - input P20EI1; - input P20EI2; - input P20EI3; - input P20EI4; - input P20EI5; - input P20EL; - output P20EO; - input P20ER; - input P20RI; - input P20RL; - output P20RO1; - output P20RO2; - output P20RO3; - output P20RO4; - output P20RO5; - input P20RR; - input P21CI1; - input P21CL; - output P21CO; - input P21CR; - input P21CTI; - output P21CTO; - input P21EI1; - input P21EI2; - input P21EI3; - input P21EI4; - input P21EI5; - input P21EL; - output P21EO; - input P21ER; - input P21RI; - input P21RL; - output P21RO1; - output P21RO2; - output P21RO3; - output P21RO4; - output P21RO5; - input P21RR; - input P22CI1; - input P22CL; - output P22CO; - input P22CR; - input P22CTI; - output P22CTO; - input P22EI1; - input P22EI2; - input P22EI3; - input P22EI4; - input P22EI5; - input P22EL; - output P22EO; - input P22ER; - input P22RI; - input P22RL; - output P22RO1; - output P22RO2; - output P22RO3; - output P22RO4; - output P22RO5; - input P22RR; - input P23CI1; - input P23CL; - output P23CO; - input P23CR; - input P23CTI; - output P23CTO; - input P23EI1; - input P23EI2; - input P23EI3; - input P23EI4; - input P23EI5; - input P23EL; - output P23EO; - input P23ER; - input P23RI; - input P23RL; - output P23RO1; - output P23RO2; - output P23RO3; - output P23RO4; - output P23RO5; - input P23RR; - input P24CI1; - input P24CL; - output P24CO; - input P24CR; - input P24CTI; - output P24CTO; - input P24EI1; - input P24EI2; - input P24EI3; - input P24EI4; - input P24EI5; - input P24EL; - output P24EO; - input P24ER; - input P24RI; - input P24RL; - output P24RO1; - output P24RO2; - output P24RO3; - output P24RO4; - output P24RO5; - input P24RR; - input P25CI1; - input P25CI2; - input P25CI3; - input P25CI4; - input P25CI5; - input P25CL; - output P25CO; - input P25CR; - input P25CTI; - output P25CTO; - input P25EI1; - input P25EI2; - input P25EI3; - input P25EI4; - input P25EI5; - input P25EL; - output P25EO; - input P25ER; - input P25RI; - input P25RL; - output P25RO1; - output P25RO2; - output P25RO3; - output P25RO4; - output P25RO5; - input P25RR; - input P26CI1; - input P26CL; - output P26CO; - input P26CR; - input P26CTI; - output P26CTO; - input P26EI1; - input P26EI2; - input P26EI3; - input P26EI4; - input P26EI5; - input P26EL; - output P26EO; - input P26ER; - input P26RI; - input P26RL; - output P26RO1; - output P26RO2; - output P26RO3; - output P26RO4; - output P26RO5; - input P26RR; - input P27CI1; - input P27CL; - output P27CO; - input P27CR; - input P27CTI; - output P27CTO; - input P27EI1; - input P27EI2; - input P27EI3; - input P27EI4; - input P27EI5; - input P27EL; - output P27EO; - input P27ER; - input P27RI; - input P27RL; - output P27RO1; - output P27RO2; - output P27RO3; - output P27RO4; - output P27RO5; - input P27RR; - input P28CI1; - input P28CL; - output P28CO; - input P28CR; - input P28CTI; - output P28CTO; - input P28EI1; - input P28EI2; - input P28EI3; - input P28EI4; - input P28EI5; - input P28EL; - output P28EO; - input P28ER; - input P28RI; - input P28RL; - output P28RO1; - output P28RO2; - output P28RO3; - output P28RO4; - output P28RO5; - input P28RR; - input P29CI1; - input P29CL; - output P29CO; - input P29CR; - input P29CTI; - output P29CTO; - input P29EI1; - input P29EI2; - input P29EI3; - input P29EI4; - input P29EI5; - input P29EL; - output P29EO; - input P29ER; - input P29RI; - input P29RL; - output P29RO1; - output P29RO2; - output P29RO3; - output P29RO4; - output P29RO5; - input P29RR; - input P2CI1; - input P2CL; - output P2CO; - input P2CR; - input P2CTI; - output P2CTO; - input P2EI1; - input P2EI2; - input P2EI3; - input P2EI4; - input P2EI5; - input P2EL; - output P2EO; - input P2ER; - input P2RI; - input P2RL; - output P2RO1; - output P2RO2; - output P2RO3; - output P2RO4; - output P2RO5; - input P2RR; - input P30CI1; - input P30CL; - output P30CO; - input P30CR; - input P30CTI; - output P30CTO; - input P30EI1; - input P30EI2; - input P30EI3; - input P30EI4; - input P30EI5; - input P30EL; - output P30EO; - input P30ER; - input P30RI; - input P30RL; - output P30RO1; - output P30RO2; - output P30RO3; - output P30RO4; - output P30RO5; - input P30RR; - input P3CI1; - input P3CL; - output P3CO; - input P3CR; - input P3CTI; - output P3CTO; - input P3EI1; - input P3EI2; - input P3EI3; - input P3EI4; - input P3EI5; - input P3EL; - output P3EO; - input P3ER; - input P3RI; - input P3RL; - output P3RO1; - output P3RO2; - output P3RO3; - output P3RO4; - output P3RO5; - input P3RR; - input P4CI1; - input P4CL; - output P4CO; - input P4CR; - input P4CTI; - output P4CTO; - input P4EI1; - input P4EI2; - input P4EI3; - input P4EI4; - input P4EI5; - input P4EL; - output P4EO; - input P4ER; - input P4RI; - input P4RL; - output P4RO1; - output P4RO2; - output P4RO3; - output P4RO4; - output P4RO5; - input P4RR; - input P5CI1; - input P5CI2; - input P5CI3; - input P5CI4; - input P5CI5; - input P5CL; - output P5CO; - input P5CR; - input P5CTI; - output P5CTO; - input P5EI1; - input P5EI2; - input P5EI3; - input P5EI4; - input P5EI5; - input P5EL; - output P5EO; - input P5ER; - input P5RI; - input P5RL; - output P5RO1; - output P5RO2; - output P5RO3; - output P5RO4; - output P5RO5; - input P5RR; - input P6CI1; - input P6CL; - output P6CO; - input P6CR; - input P6CTI; - output P6CTO; - input P6EI1; - input P6EI2; - input P6EI3; - input P6EI4; - input P6EI5; - input P6EL; - output P6EO; - input P6ER; - input P6RI; - input P6RL; - output P6RO1; - output P6RO2; - output P6RO3; - output P6RO4; - output P6RO5; - input P6RR; - input P7CI1; - input P7CL; - output P7CO; - input P7CR; - input P7CTI; - output P7CTO; - input P7EI1; - input P7EI2; - input P7EI3; - input P7EI4; - input P7EI5; - input P7EL; - output P7EO; - input P7ER; - input P7RI; - input P7RL; - output P7RO1; - output P7RO2; - output P7RO3; - output P7RO4; - output P7RO5; - input P7RR; - input P8CI1; - input P8CL; - output P8CO; - input P8CR; - input P8CTI; - output P8CTO; - input P8EI1; - input P8EI2; - input P8EI3; - input P8EI4; - input P8EI5; - input P8EL; - output P8EO; - input P8ER; - input P8RI; - input P8RL; - output P8RO1; - output P8RO2; - output P8RO3; - output P8RO4; - output P8RO5; - input P8RR; - input P9CI1; - input P9CL; - output P9CO; - input P9CR; - input P9CTI; - output P9CTO; - input P9EI1; - input P9EI2; - input P9EI3; - input P9EI4; - input P9EI5; - input P9EL; - output P9EO; - input P9ER; - input P9RI; - input P9RL; - output P9RO1; - output P9RO2; - output P9RO3; - output P9RO4; - output P9RO5; - input P9RR; - input RRCK1; - input RRCK2; - input RTCK1; - input RTCK2; - input SPI1; - input SPI2; - input SPI3; - input WRCK1; - input WRCK2; - input WTCK1; - input WTCK2; - parameter div_rx1 = 4'b0000; - parameter div_rx2 = 4'b0000; - parameter div_tx1 = 4'b0000; - parameter div_tx2 = 4'b0000; - parameter mode_io_cal = 1'b0; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter pads_dict = ""; - parameter pads_path = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_clkr_rx1 = 1'b0; - parameter sel_clkr_rx2 = 1'b0; - parameter sel_clkw_rx1 = 2'b00; - parameter sel_clkw_rx2 = 2'b00; -endmodule - (* blackbox *) module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA); input [1:0] DS; @@ -3673,908 +2166,6 @@ module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, parameter tpath_mode = 1'b0; endmodule -(* blackbox *) -module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 -, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 -, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 -, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 -, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1 -, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR -, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL -, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI -, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4 -, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3 -, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2 -, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1 -, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO -, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI -, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO -, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR -, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL -, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1 -, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5 -, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4 -, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3 -, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2 -, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1 -, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR -, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL -, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI -, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO -, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER -, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL -, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5 -, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4 -, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3 -, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2 -, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR -, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL -, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1 -, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5 -, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4 -, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3 -, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2 -, P34RO3, P34RO4, P34RO5); - output C1RED; - input C1RNE; - input C1RS; - input C1RW1; - input C1RW2; - input C1RW3; - input C1TS; - input C1TW; - output C2RED; - input C2RNE; - input C2RS; - input C2RW1; - input C2RW2; - input C2RW3; - input C2TS; - input C2TW; - input CAD1; - input CAD2; - input CAD3; - input CAD4; - input CAD5; - input CAD6; - output CAL; - input CAN1; - input CAN2; - input CAN3; - input CAN4; - input CAP1; - input CAP2; - input CAP3; - input CAP4; - input CAT1; - input CAT2; - input CAT3; - input CAT4; - input CCK; - output CKO1; - output CKO2; - input CTCK; - input DC; - input DCK; - input DIG; - input DIS; - input DOG; - input DOS; - input DPAG; - input DPAS; - input DQSG; - input DQSS; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRA5; - input DRA6; - input DRI1; - input DRI2; - input DRI3; - input DRI4; - input DRI5; - input DRI6; - input DRL; - output DRO1; - output DRO2; - output DRO3; - output DRO4; - output DRO5; - output DRO6; - input DS1; - input DS2; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - output FLD; - output FLG; - input FZ; - input P10CI1; - input P10CL; - output P10CO; - input P10CR; - input P10CTI; - output P10CTO; - input P10EI1; - input P10EI2; - input P10EI3; - input P10EI4; - input P10EI5; - input P10EL; - output P10EO; - input P10ER; - input P10RI; - input P10RL; - output P10RO1; - output P10RO2; - output P10RO3; - output P10RO4; - output P10RO5; - input P10RR; - input P11CI1; - input P11CL; - output P11CO; - input P11CR; - input P11CTI; - output P11CTO; - input P11EI1; - input P11EI2; - input P11EI3; - input P11EI4; - input P11EI5; - input P11EL; - output P11EO; - input P11ER; - input P11RI; - input P11RL; - output P11RO1; - output P11RO2; - output P11RO3; - output P11RO4; - output P11RO5; - input P11RR; - input P12CI1; - input P12CL; - output P12CO; - input P12CR; - input P12CTI; - output P12CTO; - input P12EI1; - input P12EI2; - input P12EI3; - input P12EI4; - input P12EI5; - input P12EL; - output P12EO; - input P12ER; - input P12RI; - input P12RL; - output P12RO1; - output P12RO2; - output P12RO3; - output P12RO4; - output P12RO5; - input P12RR; - input P13CI1; - input P13CL; - output P13CO; - input P13CR; - input P13CTI; - output P13CTO; - input P13EI1; - input P13EI2; - input P13EI3; - input P13EI4; - input P13EI5; - input P13EL; - output P13EO; - input P13ER; - input P13RI; - input P13RL; - output P13RO1; - output P13RO2; - output P13RO3; - output P13RO4; - output P13RO5; - input P13RR; - input P14CI1; - input P14CL; - output P14CO; - input P14CR; - input P14CTI; - output P14CTO; - input P14EI1; - input P14EI2; - input P14EI3; - input P14EI4; - input P14EI5; - input P14EL; - output P14EO; - input P14ER; - input P14RI; - input P14RL; - output P14RO1; - output P14RO2; - output P14RO3; - output P14RO4; - output P14RO5; - input P14RR; - input P15CI1; - input P15CL; - output P15CO; - input P15CR; - input P15CTI; - output P15CTO; - input P15EI1; - input P15EI2; - input P15EI3; - input P15EI4; - input P15EI5; - input P15EL; - output P15EO; - input P15ER; - input P15RI; - input P15RL; - output P15RO1; - output P15RO2; - output P15RO3; - output P15RO4; - output P15RO5; - input P15RR; - input P16CI1; - input P16CL; - output P16CO; - input P16CR; - input P16CTI; - output P16CTO; - input P16EI1; - input P16EI2; - input P16EI3; - input P16EI4; - input P16EI5; - input P16EL; - output P16EO; - input P16ER; - input P16RI; - input P16RL; - output P16RO1; - output P16RO2; - output P16RO3; - output P16RO4; - output P16RO5; - input P16RR; - input P17CI1; - input P17CL; - output P17CO; - input P17CR; - input P17CTI; - output P17CTO; - input P17EI1; - input P17EI2; - input P17EI3; - input P17EI4; - input P17EI5; - input P17EL; - output P17EO; - input P17ER; - input P17RI; - input P17RL; - output P17RO1; - output P17RO2; - output P17RO3; - output P17RO4; - output P17RO5; - input P17RR; - input P18CI1; - input P18CL; - output P18CO; - input P18CR; - input P18CTI; - output P18CTO; - input P18EI1; - input P18EI2; - input P18EI3; - input P18EI4; - input P18EI5; - input P18EL; - output P18EO; - input P18ER; - input P18RI; - input P18RL; - output P18RO1; - output P18RO2; - output P18RO3; - output P18RO4; - output P18RO5; - input P18RR; - input P19CI1; - input P19CL; - output P19CO; - input P19CR; - input P19CTI; - output P19CTO; - input P19EI1; - input P19EI2; - input P19EI3; - input P19EI4; - input P19EI5; - input P19EL; - output P19EO; - input P19ER; - input P19RI; - input P19RL; - output P19RO1; - output P19RO2; - output P19RO3; - output P19RO4; - output P19RO5; - input P19RR; - input P1CI1; - input P1CL; - output P1CO; - input P1CR; - input P1CTI; - output P1CTO; - input P1EI1; - input P1EI2; - input P1EI3; - input P1EI4; - input P1EI5; - input P1EL; - output P1EO; - input P1ER; - input P1RI; - input P1RL; - output P1RO1; - output P1RO2; - output P1RO3; - output P1RO4; - output P1RO5; - input P1RR; - input P20CI1; - input P20CL; - output P20CO; - input P20CR; - input P20CTI; - output P20CTO; - input P20EI1; - input P20EI2; - input P20EI3; - input P20EI4; - input P20EI5; - input P20EL; - output P20EO; - input P20ER; - input P20RI; - input P20RL; - output P20RO1; - output P20RO2; - output P20RO3; - output P20RO4; - output P20RO5; - input P20RR; - input P21CI1; - input P21CL; - output P21CO; - input P21CR; - input P21CTI; - output P21CTO; - input P21EI1; - input P21EI2; - input P21EI3; - input P21EI4; - input P21EI5; - input P21EL; - output P21EO; - input P21ER; - input P21RI; - input P21RL; - output P21RO1; - output P21RO2; - output P21RO3; - output P21RO4; - output P21RO5; - input P21RR; - input P22CI1; - input P22CL; - output P22CO; - input P22CR; - input P22CTI; - output P22CTO; - input P22EI1; - input P22EI2; - input P22EI3; - input P22EI4; - input P22EI5; - input P22EL; - output P22EO; - input P22ER; - input P22RI; - input P22RL; - output P22RO1; - output P22RO2; - output P22RO3; - output P22RO4; - output P22RO5; - input P22RR; - input P23CI1; - input P23CL; - output P23CO; - input P23CR; - input P23CTI; - output P23CTO; - input P23EI1; - input P23EI2; - input P23EI3; - input P23EI4; - input P23EI5; - input P23EL; - output P23EO; - input P23ER; - input P23RI; - input P23RL; - output P23RO1; - output P23RO2; - output P23RO3; - output P23RO4; - output P23RO5; - input P23RR; - input P24CI1; - input P24CL; - output P24CO; - input P24CR; - input P24CTI; - output P24CTO; - input P24EI1; - input P24EI2; - input P24EI3; - input P24EI4; - input P24EI5; - input P24EL; - output P24EO; - input P24ER; - input P24RI; - input P24RL; - output P24RO1; - output P24RO2; - output P24RO3; - output P24RO4; - output P24RO5; - input P24RR; - input P25CI1; - input P25CL; - output P25CO; - input P25CR; - input P25CTI; - output P25CTO; - input P25EI1; - input P25EI2; - input P25EI3; - input P25EI4; - input P25EI5; - input P25EL; - output P25EO; - input P25ER; - input P25RI; - input P25RL; - output P25RO1; - output P25RO2; - output P25RO3; - output P25RO4; - output P25RO5; - input P25RR; - input P26CI1; - input P26CL; - output P26CO; - input P26CR; - input P26CTI; - output P26CTO; - input P26EI1; - input P26EI2; - input P26EI3; - input P26EI4; - input P26EI5; - input P26EL; - output P26EO; - input P26ER; - input P26RI; - input P26RL; - output P26RO1; - output P26RO2; - output P26RO3; - output P26RO4; - output P26RO5; - input P26RR; - input P27CI1; - input P27CL; - output P27CO; - input P27CR; - input P27CTI; - output P27CTO; - input P27EI1; - input P27EI2; - input P27EI3; - input P27EI4; - input P27EI5; - input P27EL; - output P27EO; - input P27ER; - input P27RI; - input P27RL; - output P27RO1; - output P27RO2; - output P27RO3; - output P27RO4; - output P27RO5; - input P27RR; - input P28CI1; - input P28CL; - output P28CO; - input P28CR; - input P28CTI; - output P28CTO; - input P28EI1; - input P28EI2; - input P28EI3; - input P28EI4; - input P28EI5; - input P28EL; - output P28EO; - input P28ER; - input P28RI; - input P28RL; - output P28RO1; - output P28RO2; - output P28RO3; - output P28RO4; - output P28RO5; - input P28RR; - input P29CI1; - input P29CI2; - input P29CI3; - input P29CI4; - input P29CI5; - input P29CL; - output P29CO; - input P29CR; - input P29CTI; - output P29CTO; - input P29EI1; - input P29EI2; - input P29EI3; - input P29EI4; - input P29EI5; - input P29EL; - output P29EO; - input P29ER; - input P29RI; - input P29RL; - output P29RO1; - output P29RO2; - output P29RO3; - output P29RO4; - output P29RO5; - input P29RR; - input P2CI1; - input P2CL; - output P2CO; - input P2CR; - input P2CTI; - output P2CTO; - input P2EI1; - input P2EI2; - input P2EI3; - input P2EI4; - input P2EI5; - input P2EL; - output P2EO; - input P2ER; - input P2RI; - input P2RL; - output P2RO1; - output P2RO2; - output P2RO3; - output P2RO4; - output P2RO5; - input P2RR; - input P30CI1; - input P30CL; - output P30CO; - input P30CR; - input P30CTI; - output P30CTO; - input P30EI1; - input P30EI2; - input P30EI3; - input P30EI4; - input P30EI5; - input P30EL; - output P30EO; - input P30ER; - input P30RI; - input P30RL; - output P30RO1; - output P30RO2; - output P30RO3; - output P30RO4; - output P30RO5; - input P30RR; - input P31CI1; - input P31CL; - output P31CO; - input P31CR; - input P31CTI; - output P31CTO; - input P31EI1; - input P31EI2; - input P31EI3; - input P31EI4; - input P31EI5; - input P31EL; - output P31EO; - input P31ER; - input P31RI; - input P31RL; - output P31RO1; - output P31RO2; - output P31RO3; - output P31RO4; - output P31RO5; - input P31RR; - input P32CI1; - input P32CL; - output P32CO; - input P32CR; - input P32CTI; - output P32CTO; - input P32EI1; - input P32EI2; - input P32EI3; - input P32EI4; - input P32EI5; - input P32EL; - output P32EO; - input P32ER; - input P32RI; - input P32RL; - output P32RO1; - output P32RO2; - output P32RO3; - output P32RO4; - output P32RO5; - input P32RR; - input P33CI1; - input P33CL; - output P33CO; - input P33CR; - input P33CTI; - output P33CTO; - input P33EI1; - input P33EI2; - input P33EI3; - input P33EI4; - input P33EI5; - input P33EL; - output P33EO; - input P33ER; - input P33RI; - input P33RL; - output P33RO1; - output P33RO2; - output P33RO3; - output P33RO4; - output P33RO5; - input P33RR; - input P34CI1; - input P34CL; - output P34CO; - input P34CR; - input P34CTI; - output P34CTO; - input P34EI1; - input P34EI2; - input P34EI3; - input P34EI4; - input P34EI5; - input P34EL; - output P34EO; - input P34ER; - input P34RI; - input P34RL; - output P34RO1; - output P34RO2; - output P34RO3; - output P34RO4; - output P34RO5; - input P34RR; - input P3CI1; - input P3CL; - output P3CO; - input P3CR; - input P3CTI; - output P3CTO; - input P3EI1; - input P3EI2; - input P3EI3; - input P3EI4; - input P3EI5; - input P3EL; - output P3EO; - input P3ER; - input P3RI; - input P3RL; - output P3RO1; - output P3RO2; - output P3RO3; - output P3RO4; - output P3RO5; - input P3RR; - input P4CI1; - input P4CL; - output P4CO; - input P4CR; - input P4CTI; - output P4CTO; - input P4EI1; - input P4EI2; - input P4EI3; - input P4EI4; - input P4EI5; - input P4EL; - output P4EO; - input P4ER; - input P4RI; - input P4RL; - output P4RO1; - output P4RO2; - output P4RO3; - output P4RO4; - output P4RO5; - input P4RR; - input P5CI1; - input P5CI2; - input P5CI3; - input P5CI4; - input P5CI5; - input P5CL; - output P5CO; - input P5CR; - input P5CTI; - output P5CTO; - input P5EI1; - input P5EI2; - input P5EI3; - input P5EI4; - input P5EI5; - input P5EL; - output P5EO; - input P5ER; - input P5RI; - input P5RL; - output P5RO1; - output P5RO2; - output P5RO3; - output P5RO4; - output P5RO5; - input P5RR; - input P6CI1; - input P6CL; - output P6CO; - input P6CR; - input P6CTI; - output P6CTO; - input P6EI1; - input P6EI2; - input P6EI3; - input P6EI4; - input P6EI5; - input P6EL; - output P6EO; - input P6ER; - input P6RI; - input P6RL; - output P6RO1; - output P6RO2; - output P6RO3; - output P6RO4; - output P6RO5; - input P6RR; - input P7CI1; - input P7CL; - output P7CO; - input P7CR; - input P7CTI; - output P7CTO; - input P7EI1; - input P7EI2; - input P7EI3; - input P7EI4; - input P7EI5; - input P7EL; - output P7EO; - input P7ER; - input P7RI; - input P7RL; - output P7RO1; - output P7RO2; - output P7RO3; - output P7RO4; - output P7RO5; - input P7RR; - input P8CI1; - input P8CL; - output P8CO; - input P8CR; - input P8CTI; - output P8CTO; - input P8EI1; - input P8EI2; - input P8EI3; - input P8EI4; - input P8EI5; - input P8EL; - output P8EO; - input P8ER; - input P8RI; - input P8RL; - output P8RO1; - output P8RO2; - output P8RO3; - output P8RO4; - output P8RO5; - input P8RR; - input P9CI1; - input P9CL; - output P9CO; - input P9CR; - input P9CTI; - output P9CTO; - input P9EI1; - input P9EI2; - input P9EI3; - input P9EI4; - input P9EI5; - input P9EL; - output P9EO; - input P9ER; - input P9RI; - input P9RL; - output P9RO1; - output P9RO2; - output P9RO3; - output P9RO4; - output P9RO5; - input P9RR; - input RRCK1; - input RRCK2; - input RTCK1; - input RTCK2; - input WRCK1; - input WRCK2; - input WTCK1; - input WTCK2; - parameter div_rx1 = 4'b0000; - parameter div_rx2 = 4'b0000; - parameter div_tx1 = 4'b0000; - parameter div_tx2 = 4'b0000; - parameter mode_io_cal = 1'b0; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter pads_dict = ""; - parameter pads_path = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_clkr_rx1 = 1'b0; - parameter sel_clkr_rx2 = 1'b0; - parameter sel_clkw_rx1 = 2'b00; - parameter sel_clkw_rx2 = 2'b00; -endmodule - (* blackbox *) module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); input CTCK; @@ -4653,1189 +2244,6 @@ module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG parameter location = ""; endmodule -(* blackbox *) -module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 -, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 -, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN -, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN -, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 -, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 -, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 -, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL -, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6 -, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI -, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6 -, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL -, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6 -, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI -, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6 -, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL -, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6 -, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI -, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6 -, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL -, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6 -, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI -, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6 -, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL -, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6 -, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI -, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6 -, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL -, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6 -, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI -, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6 -, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL -, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6 -, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI -, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6 -, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL -, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6 -, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI -, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6 -, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL -, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6 -, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI -, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6 -, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL -, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6 -, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI -, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6 -, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL -, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6 -, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI -, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6 -, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL -, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8); - output AL1D; - output AL1T; - output AL2D; - output AL2T; - output AL3D; - output AL3T; - input ALCK1; - input ALCK2; - input ALCK3; - input CA1D1; - input CA1D2; - input CA1D3; - input CA1D4; - input CA1D5; - input CA1D6; - input CA1N1; - input CA1N2; - input CA1N3; - input CA1N4; - input CA1P1; - input CA1P2; - input CA1P3; - input CA1P4; - input CA1T1; - input CA1T2; - input CA1T3; - input CA1T4; - input CA2D1; - input CA2D2; - input CA2D3; - input CA2D4; - input CA2D5; - input CA2D6; - input CA2N1; - input CA2N2; - input CA2N3; - input CA2N4; - input CA2P1; - input CA2P2; - input CA2P3; - input CA2P4; - input CA2T1; - input CA2T2; - input CA2T3; - input CA2T4; - input CCK; - output CKO1; - output CKO2; - output DCL; - input DCRN; - input DQ1CI1; - input DQ1CI2; - input DQ1CI3; - input DQ1CI4; - input DQ1CI5; - input DQ1CI6; - input DQ1CI7; - input DQ1CI8; - input DQ2CI1; - input DQ2CI2; - input DQ2CI3; - input DQ2CI4; - input DQ2CI5; - input DQ2CI6; - input DQ2CI7; - input DQ2CI8; - input DQ3CI1; - input DQ3CI2; - input DQ3CI3; - input DQ3CI4; - input DQ3CI5; - input DQ3CI6; - input DQ3CI7; - input DQ3CI8; - input DQS1CI1; - input DQS1CI2; - input DQS1CI3; - input DQS1CI4; - input DQS1CI5; - input DQS1CI6; - input DQS1CI7; - input DQS1CI8; - input DQS2CI1; - input DQS2CI2; - input DQS2CI3; - input DQS2CI4; - input DQS2CI5; - input DQS2CI6; - input DQS2CI7; - input DQS2CI8; - input DQS3CI1; - input DQS3CI2; - input DQS3CI3; - input DQS3CI4; - input DQS3CI5; - input DQS3CI6; - input DQS3CI7; - input DQS3CI8; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRCCSN; - input DRDPA1CSN; - input DRDPA2CSN; - input DRDPA3CSN; - input DRE; - input DRI1; - input DRI1CSN; - input DRI2; - input DRI2CSN; - input DRI3; - input DRI3CSN; - input DRI4; - input DRI5; - input DRI6; - output DRO1; - input DRO1CSN; - output DRO2; - input DRO2CSN; - output DRO3; - input DRO3CSN; - output DRO4; - output DRO5; - output DRO6; - input DRWDS; - input DRWEN; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - input FCK1; - input FCK2; - input FDCK; - output FLD; - output FLG; - input FZ; - input LD1RN; - input LD2RN; - input LD3RN; - input LDSCK1; - input LDSCK2; - input LDSCK3; - input LE; - input P10CI1; - input P10CL; - output P10CO; - input P10CR; - input P10CTI; - output P10CTO; - input P10EI1; - input P10EI2; - input P10EI3; - input P10EI4; - input P10EI5; - input P10EI6; - input P10EI7; - input P10EI8; - input P10EL; - output P10EO; - input P10ER; - input P10RI; - input P10RL; - output P10RO1; - output P10RO2; - output P10RO3; - output P10RO4; - output P10RO5; - output P10RO6; - output P10RO7; - output P10RO8; - input P10RR; - input P11CI1; - input P11CL; - output P11CO; - input P11CR; - input P11CTI; - output P11CTO; - input P11EI1; - input P11EI2; - input P11EI3; - input P11EI4; - input P11EI5; - input P11EI6; - input P11EI7; - input P11EI8; - input P11EL; - output P11EO; - input P11ER; - input P11RI; - input P11RL; - output P11RO1; - output P11RO2; - output P11RO3; - output P11RO4; - output P11RO5; - output P11RO6; - output P11RO7; - output P11RO8; - input P11RR; - input P12CI1; - input P12CL; - output P12CO; - input P12CR; - input P12CTI; - output P12CTO; - input P12EI1; - input P12EI2; - input P12EI3; - input P12EI4; - input P12EI5; - input P12EI6; - input P12EI7; - input P12EI8; - input P12EL; - output P12EO; - input P12ER; - input P12RI; - input P12RL; - output P12RO1; - output P12RO2; - output P12RO3; - output P12RO4; - output P12RO5; - output P12RO6; - output P12RO7; - output P12RO8; - input P12RR; - input P13CI1; - input P13CL; - output P13CO; - input P13CR; - input P13CTI; - output P13CTO; - input P13EI1; - input P13EI2; - input P13EI3; - input P13EI4; - input P13EI5; - input P13EI6; - input P13EI7; - input P13EI8; - input P13EL; - output P13EO; - input P13ER; - input P13RI; - input P13RL; - output P13RO1; - output P13RO2; - output P13RO3; - output P13RO4; - output P13RO5; - output P13RO6; - output P13RO7; - output P13RO8; - input P13RR; - input P14CI1; - input P14CL; - output P14CO; - input P14CR; - input P14CTI; - output P14CTO; - input P14EI1; - input P14EI2; - input P14EI3; - input P14EI4; - input P14EI5; - input P14EI6; - input P14EI7; - input P14EI8; - input P14EL; - output P14EO; - input P14ER; - input P14RI; - input P14RL; - output P14RO1; - output P14RO2; - output P14RO3; - output P14RO4; - output P14RO5; - output P14RO6; - output P14RO7; - output P14RO8; - input P14RR; - input P15CI1; - input P15CL; - output P15CO; - input P15CR; - input P15CTI; - output P15CTO; - input P15EI1; - input P15EI2; - input P15EI3; - input P15EI4; - input P15EI5; - input P15EI6; - input P15EI7; - input P15EI8; - input P15EL; - output P15EO; - input P15ER; - input P15RI; - input P15RL; - output P15RO1; - output P15RO2; - output P15RO3; - output P15RO4; - output P15RO5; - output P15RO6; - output P15RO7; - output P15RO8; - input P15RR; - input P16CI1; - input P16CL; - output P16CO; - input P16CR; - input P16CTI; - output P16CTO; - input P16EI1; - input P16EI2; - input P16EI3; - input P16EI4; - input P16EI5; - input P16EI6; - input P16EI7; - input P16EI8; - input P16EL; - output P16EO; - input P16ER; - input P16RI; - input P16RL; - output P16RO1; - output P16RO2; - output P16RO3; - output P16RO4; - output P16RO5; - output P16RO6; - output P16RO7; - output P16RO8; - input P16RR; - input P17CI1; - input P17CL; - output P17CO; - input P17CR; - input P17CTI; - output P17CTO; - input P17EI1; - input P17EI2; - input P17EI3; - input P17EI4; - input P17EI5; - input P17EI6; - input P17EI7; - input P17EI8; - input P17EL; - output P17EO; - input P17ER; - input P17RI; - input P17RL; - output P17RO1; - output P17RO2; - output P17RO3; - output P17RO4; - output P17RO5; - output P17RO6; - output P17RO7; - output P17RO8; - input P17RR; - input P18CI1; - input P18CL; - output P18CO; - input P18CR; - input P18CTI; - output P18CTO; - input P18EI1; - input P18EI2; - input P18EI3; - input P18EI4; - input P18EI5; - input P18EI6; - input P18EI7; - input P18EI8; - input P18EL; - output P18EO; - input P18ER; - input P18RI; - input P18RL; - output P18RO1; - output P18RO2; - output P18RO3; - output P18RO4; - output P18RO5; - output P18RO6; - output P18RO7; - output P18RO8; - input P18RR; - input P19CI1; - input P19CL; - output P19CO; - input P19CR; - input P19CTI; - output P19CTO; - input P19EI1; - input P19EI2; - input P19EI3; - input P19EI4; - input P19EI5; - input P19EI6; - input P19EI7; - input P19EI8; - input P19EL; - output P19EO; - input P19ER; - input P19RI; - input P19RL; - output P19RO1; - output P19RO2; - output P19RO3; - output P19RO4; - output P19RO5; - output P19RO6; - output P19RO7; - output P19RO8; - input P19RR; - input P1CI1; - input P1CL; - output P1CO; - input P1CR; - input P1CTI; - output P1CTO; - input P1EI1; - input P1EI2; - input P1EI3; - input P1EI4; - input P1EI5; - input P1EI6; - input P1EI7; - input P1EI8; - input P1EL; - output P1EO; - input P1ER; - input P1RI; - input P1RL; - output P1RO1; - output P1RO2; - output P1RO3; - output P1RO4; - output P1RO5; - output P1RO6; - output P1RO7; - output P1RO8; - input P1RR; - input P20CI1; - input P20CL; - output P20CO; - input P20CR; - input P20CTI; - output P20CTO; - input P20EI1; - input P20EI2; - input P20EI3; - input P20EI4; - input P20EI5; - input P20EI6; - input P20EI7; - input P20EI8; - input P20EL; - output P20EO; - input P20ER; - input P20RI; - input P20RL; - output P20RO1; - output P20RO2; - output P20RO3; - output P20RO4; - output P20RO5; - output P20RO6; - output P20RO7; - output P20RO8; - input P20RR; - input P21CI1; - input P21CL; - output P21CO; - input P21CR; - input P21CTI; - output P21CTO; - input P21EI1; - input P21EI2; - input P21EI3; - input P21EI4; - input P21EI5; - input P21EI6; - input P21EI7; - input P21EI8; - input P21EL; - output P21EO; - input P21ER; - input P21RI; - input P21RL; - output P21RO1; - output P21RO2; - output P21RO3; - output P21RO4; - output P21RO5; - output P21RO6; - output P21RO7; - output P21RO8; - input P21RR; - input P22CI1; - input P22CL; - output P22CO; - input P22CR; - input P22CTI; - output P22CTO; - input P22EI1; - input P22EI2; - input P22EI3; - input P22EI4; - input P22EI5; - input P22EI6; - input P22EI7; - input P22EI8; - input P22EL; - output P22EO; - input P22ER; - input P22RI; - input P22RL; - output P22RO1; - output P22RO2; - output P22RO3; - output P22RO4; - output P22RO5; - output P22RO6; - output P22RO7; - output P22RO8; - input P22RR; - input P23CI1; - input P23CL; - output P23CO; - input P23CR; - input P23CTI; - output P23CTO; - input P23EI1; - input P23EI2; - input P23EI3; - input P23EI4; - input P23EI5; - input P23EI6; - input P23EI7; - input P23EI8; - input P23EL; - output P23EO; - input P23ER; - input P23RI; - input P23RL; - output P23RO1; - output P23RO2; - output P23RO3; - output P23RO4; - output P23RO5; - output P23RO6; - output P23RO7; - output P23RO8; - input P23RR; - input P24CI1; - input P24CL; - output P24CO; - input P24CR; - input P24CTI; - output P24CTO; - input P24EI1; - input P24EI2; - input P24EI3; - input P24EI4; - input P24EI5; - input P24EI6; - input P24EI7; - input P24EI8; - input P24EL; - output P24EO; - input P24ER; - input P24RI; - input P24RL; - output P24RO1; - output P24RO2; - output P24RO3; - output P24RO4; - output P24RO5; - output P24RO6; - output P24RO7; - output P24RO8; - input P24RR; - input P25CI1; - input P25CL; - output P25CO; - input P25CR; - input P25CTI; - output P25CTO; - input P25EI1; - input P25EI2; - input P25EI3; - input P25EI4; - input P25EI5; - input P25EI6; - input P25EI7; - input P25EI8; - input P25EL; - output P25EO; - input P25ER; - input P25RI; - input P25RL; - output P25RO1; - output P25RO2; - output P25RO3; - output P25RO4; - output P25RO5; - output P25RO6; - output P25RO7; - output P25RO8; - input P25RR; - input P26CI1; - input P26CL; - output P26CO; - input P26CR; - input P26CTI; - output P26CTO; - input P26EI1; - input P26EI2; - input P26EI3; - input P26EI4; - input P26EI5; - input P26EI6; - input P26EI7; - input P26EI8; - input P26EL; - output P26EO; - input P26ER; - input P26RI; - input P26RL; - output P26RO1; - output P26RO2; - output P26RO3; - output P26RO4; - output P26RO5; - output P26RO6; - output P26RO7; - output P26RO8; - input P26RR; - input P27CI1; - input P27CL; - output P27CO; - input P27CR; - input P27CTI; - output P27CTO; - input P27EI1; - input P27EI2; - input P27EI3; - input P27EI4; - input P27EI5; - input P27EI6; - input P27EI7; - input P27EI8; - input P27EL; - output P27EO; - input P27ER; - input P27RI; - input P27RL; - output P27RO1; - output P27RO2; - output P27RO3; - output P27RO4; - output P27RO5; - output P27RO6; - output P27RO7; - output P27RO8; - input P27RR; - input P28CI1; - input P28CL; - output P28CO; - input P28CR; - input P28CTI; - output P28CTO; - input P28EI1; - input P28EI2; - input P28EI3; - input P28EI4; - input P28EI5; - input P28EI6; - input P28EI7; - input P28EI8; - input P28EL; - output P28EO; - input P28ER; - input P28RI; - input P28RL; - output P28RO1; - output P28RO2; - output P28RO3; - output P28RO4; - output P28RO5; - output P28RO6; - output P28RO7; - output P28RO8; - input P28RR; - input P29CI1; - input P29CL; - output P29CO; - input P29CR; - input P29CTI; - output P29CTO; - input P29EI1; - input P29EI2; - input P29EI3; - input P29EI4; - input P29EI5; - input P29EI6; - input P29EI7; - input P29EI8; - input P29EL; - output P29EO; - input P29ER; - input P29RI; - input P29RL; - output P29RO1; - output P29RO2; - output P29RO3; - output P29RO4; - output P29RO5; - output P29RO6; - output P29RO7; - output P29RO8; - input P29RR; - input P2CI1; - input P2CL; - output P2CO; - input P2CR; - input P2CTI; - output P2CTO; - input P2EI1; - input P2EI2; - input P2EI3; - input P2EI4; - input P2EI5; - input P2EI6; - input P2EI7; - input P2EI8; - input P2EL; - output P2EO; - input P2ER; - input P2RI; - input P2RL; - output P2RO1; - output P2RO2; - output P2RO3; - output P2RO4; - output P2RO5; - output P2RO6; - output P2RO7; - output P2RO8; - input P2RR; - input P30CI1; - input P30CL; - output P30CO; - input P30CR; - input P30CTI; - output P30CTO; - input P30EI1; - input P30EI2; - input P30EI3; - input P30EI4; - input P30EI5; - input P30EI6; - input P30EI7; - input P30EI8; - input P30EL; - output P30EO; - input P30ER; - input P30RI; - input P30RL; - output P30RO1; - output P30RO2; - output P30RO3; - output P30RO4; - output P30RO5; - output P30RO6; - output P30RO7; - output P30RO8; - input P30RR; - input P31CI1; - input P31CL; - output P31CO; - input P31CR; - input P31CTI; - output P31CTO; - input P31EI1; - input P31EI2; - input P31EI3; - input P31EI4; - input P31EI5; - input P31EI6; - input P31EI7; - input P31EI8; - input P31EL; - output P31EO; - input P31ER; - input P31RI; - input P31RL; - output P31RO1; - output P31RO2; - output P31RO3; - output P31RO4; - output P31RO5; - output P31RO6; - output P31RO7; - output P31RO8; - input P31RR; - input P32CI1; - input P32CL; - output P32CO; - input P32CR; - input P32CTI; - output P32CTO; - input P32EI1; - input P32EI2; - input P32EI3; - input P32EI4; - input P32EI5; - input P32EI6; - input P32EI7; - input P32EI8; - input P32EL; - output P32EO; - input P32ER; - input P32RI; - input P32RL; - output P32RO1; - output P32RO2; - output P32RO3; - output P32RO4; - output P32RO5; - output P32RO6; - output P32RO7; - output P32RO8; - input P32RR; - input P33CI1; - input P33CL; - output P33CO; - input P33CR; - input P33CTI; - output P33CTO; - input P33EI1; - input P33EI2; - input P33EI3; - input P33EI4; - input P33EI5; - input P33EI6; - input P33EI7; - input P33EI8; - input P33EL; - output P33EO; - input P33ER; - input P33RI; - input P33RL; - output P33RO1; - output P33RO2; - output P33RO3; - output P33RO4; - output P33RO5; - output P33RO6; - output P33RO7; - output P33RO8; - input P33RR; - input P34CI1; - input P34CL; - output P34CO; - input P34CR; - input P34CTI; - output P34CTO; - input P34EI1; - input P34EI2; - input P34EI3; - input P34EI4; - input P34EI5; - input P34EI6; - input P34EI7; - input P34EI8; - input P34EL; - output P34EO; - input P34ER; - input P34RI; - input P34RL; - output P34RO1; - output P34RO2; - output P34RO3; - output P34RO4; - output P34RO5; - output P34RO6; - output P34RO7; - output P34RO8; - input P34RR; - input P3CI1; - input P3CL; - output P3CO; - input P3CR; - input P3CTI; - output P3CTO; - input P3EI1; - input P3EI2; - input P3EI3; - input P3EI4; - input P3EI5; - input P3EI6; - input P3EI7; - input P3EI8; - input P3EL; - output P3EO; - input P3ER; - input P3RI; - input P3RL; - output P3RO1; - output P3RO2; - output P3RO3; - output P3RO4; - output P3RO5; - output P3RO6; - output P3RO7; - output P3RO8; - input P3RR; - input P4CI1; - input P4CL; - output P4CO; - input P4CR; - input P4CTI; - output P4CTO; - input P4EI1; - input P4EI2; - input P4EI3; - input P4EI4; - input P4EI5; - input P4EI6; - input P4EI7; - input P4EI8; - input P4EL; - output P4EO; - input P4ER; - input P4RI; - input P4RL; - output P4RO1; - output P4RO2; - output P4RO3; - output P4RO4; - output P4RO5; - output P4RO6; - output P4RO7; - output P4RO8; - input P4RR; - input P5CI1; - input P5CL; - output P5CO; - input P5CR; - input P5CTI; - output P5CTO; - input P5EI1; - input P5EI2; - input P5EI3; - input P5EI4; - input P5EI5; - input P5EI6; - input P5EI7; - input P5EI8; - input P5EL; - output P5EO; - input P5ER; - input P5RI; - input P5RL; - output P5RO1; - output P5RO2; - output P5RO3; - output P5RO4; - output P5RO5; - output P5RO6; - output P5RO7; - output P5RO8; - input P5RR; - input P6CI1; - input P6CL; - output P6CO; - input P6CR; - input P6CTI; - output P6CTO; - input P6EI1; - input P6EI2; - input P6EI3; - input P6EI4; - input P6EI5; - input P6EI6; - input P6EI7; - input P6EI8; - input P6EL; - output P6EO; - input P6ER; - input P6RI; - input P6RL; - output P6RO1; - output P6RO2; - output P6RO3; - output P6RO4; - output P6RO5; - output P6RO6; - output P6RO7; - output P6RO8; - input P6RR; - input P7CI1; - input P7CL; - output P7CO; - input P7CR; - input P7CTI; - output P7CTO; - input P7EI1; - input P7EI2; - input P7EI3; - input P7EI4; - input P7EI5; - input P7EI6; - input P7EI7; - input P7EI8; - input P7EL; - output P7EO; - input P7ER; - input P7RI; - input P7RL; - output P7RO1; - output P7RO2; - output P7RO3; - output P7RO4; - output P7RO5; - output P7RO6; - output P7RO7; - output P7RO8; - input P7RR; - input P8CI1; - input P8CL; - output P8CO; - input P8CR; - input P8CTI; - output P8CTO; - input P8EI1; - input P8EI2; - input P8EI3; - input P8EI4; - input P8EI5; - input P8EI6; - input P8EI7; - input P8EI8; - input P8EL; - output P8EO; - input P8ER; - input P8RI; - input P8RL; - output P8RO1; - output P8RO2; - output P8RO3; - output P8RO4; - output P8RO5; - output P8RO6; - output P8RO7; - output P8RO8; - input P8RR; - input P9CI1; - input P9CL; - output P9CO; - input P9CR; - input P9CTI; - output P9CTO; - input P9EI1; - input P9EI2; - input P9EI3; - input P9EI4; - input P9EI5; - input P9EI6; - input P9EI7; - input P9EI8; - input P9EL; - output P9EO; - input P9ER; - input P9RI; - input P9RL; - output P9RO1; - output P9RO2; - output P9RO3; - output P9RO4; - output P9RO5; - output P9RO6; - output P9RO7; - output P9RO8; - input P9RR; - input SE; - input SWRX1CK; - input SWRX2CK; - parameter cal_delay1 = ""; - parameter cal_delay2 = ""; - parameter div1 = 3'b000; - parameter div2 = 3'b000; - parameter div3 = 3'b000; - parameter div_swrx1 = 3'b000; - parameter div_swrx2 = 3'b000; - parameter inv_ld_sck1 = 1'b0; - parameter inv_ld_sck2 = 1'b0; - parameter inv_ld_sck3 = 1'b0; - parameter link_ld_12 = 1'b0; - parameter link_ld_23 = 1'b0; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter mode_side3 = 0; - parameter pads_dict = ""; - parameter pads_path = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_dc_clk = 2'b00; - parameter sel_ld_fck1 = 2'b00; - parameter sel_ld_fck2 = 2'b00; - parameter sel_ld_fck3 = 2'b00; - parameter sel_sw_fck1 = 2'b00; - parameter sel_sw_fck2 = 2'b00; - parameter use_dc = 1'b0; -endmodule - //(* blackbox *) //module NX_LUT(I1, I2, I3, I4, O); // input I1; @@ -5846,377 +2254,6 @@ endmodule // parameter lut_table = 16'b0000000000000000; //endmodule -(* blackbox *) -module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2 -, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3 -, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2 -, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2 -, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7 -, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2 -, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0); - input CAL_1P_I1; - input CAL_1P_I2; - input CAL_1P_I3; - input CAL_1P_I4; - input CAL_1P_I5; - input CAL_1P_I6; - input CAL_1P_I7; - input CAL_1P_I8; - input CAL_2N_I1; - input CAL_2N_I2; - input CAL_2N_I3; - input CAL_2N_I4; - input CAL_2N_I5; - input CAL_2N_I6; - input CAL_2N_I7; - input CAL_2N_I8; - input CAL_3N_I1; - input CAL_3N_I2; - input CAL_3N_I3; - input CAL_3N_I4; - input CAL_3N_I5; - input CAL_3N_I6; - input CAL_3N_I7; - input CAL_3N_I8; - input CAL_4P_I1; - input CAL_4P_I2; - input CAL_4P_I3; - input CAL_4P_I4; - input CAL_4P_I5; - input CAL_4P_I6; - input CAL_4P_I7; - input CAL_4P_I8; - input CAL_E_I; - output CAL_O; - input CAL_SEL_I1; - input CAL_SEL_I2; - input CAL_SEL_I3; - input CAL_SEL_I4; - input CLK_EXT_I; - output CLK_O; - input CLK_REF_I; - input CLK_USER_I; - input CT_CAP_I1; - input CT_CAP_I2; - input CT_CAP_I3; - input CT_CAP_I4; - input CT_RESN_I1; - input CT_RESN_I2; - input CT_RESN_I3; - input CT_RESN_I4; - input CT_RESP_I1; - input CT_RESP_I2; - input CT_RESP_I3; - input CT_RESP_I4; - inout [9:0] LINK_RX0; - inout [9:0] LINK_RX1; - inout [9:0] LINK_RX2; - inout [9:0] LINK_RX3; - inout [9:0] LINK_RX4; - inout [9:0] LINK_RX5; - inout [19:0] LINK_TX0; - inout [19:0] LINK_TX1; - inout [19:0] LINK_TX2; - inout [19:0] LINK_TX3; - inout [19:0] LINK_TX4; - inout [19:0] LINK_TX5; - input LOCK_E_I; - output LOCK_O; - input MAIN_EN_I1; - input MAIN_EN_I2; - input MAIN_EN_I3; - input MAIN_EN_I4; - input MAIN_EN_I5; - input MAIN_EN_I6; - input MAIN_SG_I; - input MARG_ISV_I1; - input MARG_ISV_I2; - input MARG_ISV_I3; - input MARG_ISV_I4; - input MARG_ISV_I5; - input MARG_IS_I1; - input MARG_IS_I2; - input MARG_IS_I3; - input MARG_IS_I4; - input MARG_SV_I1; - input MARG_SV_I2; - input MARG_SV_I3; - input MARG_SV_I4; - input MARG_SV_I5; - input MARG_S_I1; - input MARG_S_I2; - input MARG_S_I3; - input MARG_S_I4; - input M_EYE_I; - input OVS_E_I; - input PLL_RN_I; - input POST_EN_I1; - input POST_EN_I2; - input POST_EN_I3; - input POST_EN_I4; - input POST_EN_I5; - input POST_ISV_I1; - input POST_ISV_I2; - input POST_ISV_I3; - input POST_ISV_I4; - input POST_IS_I1; - input POST_IS_I2; - input POST_IS_I3; - input POST_IS_I4; - input POST_SG_I; - input PRE_EN_I; - input PRE_IS_I1; - input PRE_IS_I2; - input PRE_IS_I3; - input PRE_IS_I4; - input PRE_SG_I; - input RST_N_I; - input RX_SEL_I1; - input RX_SEL_I2; - input RX_SEL_I3; - input RX_SEL_I4; - input RX_SEL_I5; - input RX_SEL_I6; - input TST_I1; - input TST_I2; - input TST_I3; - input TST_I4; - input TST_I5; - input TST_I6; - input TST_I7; - input TST_I8; - output TST_O1; - output TST_O2; - output TST_O3; - output TST_O4; - output TST_O5; - output TST_O6; - output TST_O7; - output TST_O8; - input TX_SEL_I1; - input TX_SEL_I2; - input TX_SEL_I3; - input TX_SEL_I4; - input TX_SEL_I5; - input TX_SEL_I6; - parameter location = ""; - parameter main_clk_to_fabric_div_en = 1'b0; - parameter main_clk_to_fabric_div_mode = 1'b0; - parameter main_clk_to_fabric_sel = 1'b0; - parameter main_test = 8'b00000000; - parameter main_use_only_usr_clock = 1'b0; - parameter main_use_pcs_clk_2 = 1'b0; - parameter pcs_ovs_mode = 1'b0; - parameter pcs_pll_lock_count = 3'b000; - parameter pcs_word_len = 2'b00; - parameter pll_pma_cpump_n = 3'b000; - parameter pll_pma_divf = 2'b00; - parameter pll_pma_divf_en_n = 1'b0; - parameter pll_pma_divm = 2'b00; - parameter pll_pma_divm_en_n = 1'b0; - parameter pll_pma_divn = 1'b0; - parameter pll_pma_divn_en_n = 1'b0; - parameter pll_pma_int_data_len = 1'b0; - parameter pll_pma_lvds_mux = 1'b0; - parameter pll_pma_mux_ckref = 1'b0; - parameter rx_pma_half_step = 1'b0; -endmodule - -(* blackbox *) -module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6 -, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8 -, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14 -, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3 -, LINK_TX0); - output CAL_OUT_O; - output CLK_O; - input CLK_REF_I; - input CLK_RX_I; - output CLK_RX_O; - input CLK_TX_I; - input DBG_A_I; - output DBG_R_O; - input DBG_S_I1; - input DBG_S_I2; - input DC_ADD_I1; - input DC_ADD_I2; - input DC_ADD_I3; - input DC_ADD_I4; - input DC_CCSN_I; - input DC_E_I; - input DC_LCSN_I1; - input DC_LCSN_I2; - input DC_LCSN_I3; - input DC_LCSN_I4; - input DC_WDATAS_I; - input DC_WDATA_I1; - input DC_WDATA_I10; - input DC_WDATA_I11; - input DC_WDATA_I12; - input DC_WDATA_I2; - input DC_WDATA_I3; - input DC_WDATA_I4; - input DC_WDATA_I5; - input DC_WDATA_I6; - input DC_WDATA_I7; - input DC_WDATA_I8; - input DC_WDATA_I9; - input DC_WE_N_I; - output FB_LOCK_O; - inout [9:0] LINK_RX0; - inout [9:0] LINK_RX1; - inout [9:0] LINK_RX2; - inout [9:0] LINK_RX3; - inout [19:0] LINK_TX0; - inout [19:0] LINK_TX1; - inout [19:0] LINK_TX2; - inout [19:0] LINK_TX3; - output LL_O1; - output LL_O10; - output LL_O11; - output LL_O12; - output LL_O13; - output LL_O14; - output LL_O15; - output LL_O16; - output LL_O17; - output LL_O18; - output LL_O19; - output LL_O2; - output LL_O20; - output LL_O3; - output LL_O4; - output LL_O5; - output LL_O6; - output LL_O7; - output LL_O8; - output LL_O9; - output LOCKA_O; - output LOCK_O; - input PLL_RN_I; - input PWDN_N_I; - input RST_N_I; - input SCAN_I1; - input SCAN_I2; - input SCAN_I3; - input SCAN_I4; - input SCAN_I5; - input SCAN_I6; - input SCAN_I7; - input SCAN_I8; - output SCAN_O1; - output SCAN_O2; - output SCAN_O3; - output SCAN_O4; - output SCAN_O5; - output SCAN_O6; - output SCAN_O7; - output SCAN_O8; - input SE_I; - parameter dyn_all_rx_pma_m_eye = 1'b0; - parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0; - parameter dyn_all_rx_pma_m_eye_dn = 1'b0; - parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0; - parameter dyn_all_rx_pma_m_eye_step = 4'b0000; - parameter dyn_all_rx_pma_m_eye_up = 1'b0; - parameter dyn_all_rx_pma_threshold_1 = 5'b00000; - parameter dyn_all_rx_pma_threshold_2 = 5'b00000; - parameter dyn_all_rx_pma_trim_locked = 3'b000; - parameter dyn_all_rx_pma_trim_mode = 2'b00; - parameter dyn_all_rx_pma_trim_unlocked = 3'b000; - parameter dyn_rx0_pma_ctle_cap_p = 4'b0000; - parameter dyn_rx0_pma_ctle_res_p = 4'b0000; - parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000; - parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000; - parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000; - parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000; - parameter dyn_rx0_pma_termination_cmd = 6'b000000; - parameter dyn_rx1_pma_ctle_cap_p = 4'b0000; - parameter dyn_rx1_pma_ctle_res_p = 4'b0000; - parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000; - parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000; - parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000; - parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000; - parameter dyn_rx1_pma_termination_cmd = 6'b000000; - parameter dyn_rx2_pma_ctle_cap_p = 4'b0000; - parameter dyn_rx2_pma_ctle_res_p = 4'b0000; - parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000; - parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000; - parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000; - parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000; - parameter dyn_rx2_pma_termination_cmd = 6'b000000; - parameter dyn_rx3_pma_ctle_cap_p = 4'b0000; - parameter dyn_rx3_pma_ctle_res_p = 4'b0000; - parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000; - parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000; - parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000; - parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000; - parameter dyn_rx3_pma_termination_cmd = 6'b000000; - parameter dyn_tx0_pma_main_en = 6'b000000; - parameter dyn_tx0_pma_main_sign = 1'b0; - parameter dyn_tx0_pma_margin_input = 9'b000000000; - parameter dyn_tx0_pma_margin_sel = 9'b000000000; - parameter dyn_tx0_pma_post_en = 5'b00000; - parameter dyn_tx0_pma_post_sel = 8'b00000000; - parameter dyn_tx0_pma_post_sign = 1'b0; - parameter dyn_tx0_pma_pre_en = 1'b0; - parameter dyn_tx0_pma_pre_sel = 4'b0000; - parameter dyn_tx0_pma_pre_sign = 1'b0; - parameter dyn_tx1_pma_main_en = 6'b000000; - parameter dyn_tx1_pma_main_sign = 1'b0; - parameter dyn_tx1_pma_margin_input = 9'b000000000; - parameter dyn_tx1_pma_margin_sel = 9'b000000000; - parameter dyn_tx1_pma_post_en = 5'b00000; - parameter dyn_tx1_pma_post_sel = 8'b00000000; - parameter dyn_tx1_pma_post_sign = 1'b0; - parameter dyn_tx1_pma_pre_en = 1'b0; - parameter dyn_tx1_pma_pre_sel = 4'b0000; - parameter dyn_tx1_pma_pre_sign = 1'b0; - parameter dyn_tx2_pma_main_en = 6'b000000; - parameter dyn_tx2_pma_main_sign = 1'b0; - parameter dyn_tx2_pma_margin_input = 9'b000000000; - parameter dyn_tx2_pma_margin_sel = 9'b000000000; - parameter dyn_tx2_pma_post_en = 5'b00000; - parameter dyn_tx2_pma_post_sel = 8'b00000000; - parameter dyn_tx2_pma_post_sign = 1'b0; - parameter dyn_tx2_pma_pre_en = 1'b0; - parameter dyn_tx2_pma_pre_sel = 4'b0000; - parameter dyn_tx2_pma_pre_sign = 1'b0; - parameter dyn_tx3_pma_main_en = 6'b000000; - parameter dyn_tx3_pma_main_sign = 1'b0; - parameter dyn_tx3_pma_margin_input = 9'b000000000; - parameter dyn_tx3_pma_margin_sel = 9'b000000000; - parameter dyn_tx3_pma_post_en = 5'b00000; - parameter dyn_tx3_pma_post_sel = 8'b00000000; - parameter dyn_tx3_pma_post_sign = 1'b0; - parameter dyn_tx3_pma_pre_en = 1'b0; - parameter dyn_tx3_pma_pre_sel = 4'b0000; - parameter dyn_tx3_pma_pre_sign = 1'b0; - parameter location = ""; - parameter main_clk_to_fabric_div_en = 1'b0; - parameter main_clk_to_fabric_div_mode = 1'b0; - parameter main_clk_to_fabric_sel = 1'b0; - parameter main_rclk_to_fabric_sel = 2'b00; - parameter main_use_only_usr_clock = 1'b0; - parameter pcs_ovs_en = 1'b0; - parameter pcs_ovs_mode = 1'b0; - parameter pcs_pll_lock_ppm = 3'b000; - parameter pcs_word_len = 2'b00; - parameter pll_pma_ckref_ext = 1'b0; - parameter pll_pma_cpump = 4'b0000; - parameter pll_pma_divl = 2'b00; - parameter pll_pma_divm = 1'b0; - parameter pll_pma_divn = 2'b00; - parameter pll_pma_gbx_en = 1'b0; - parameter pll_pma_int_data_len = 1'b0; - parameter pll_pma_lvds_en = 1'b0; - parameter pll_pma_lvds_mux = 1'b0; - parameter pll_pma_mux_ckref = 1'b0; - parameter rx_usrclk_use_pcs_clk_2 = 1'b0; - parameter test_mode = 2'b00; - parameter tx_usrclk_use_pcs_clk_2 = 1'b0; -endmodule - (* blackbox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 @@ -7701,108 +3738,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD parameter weakTermination = ""; endmodule -(* blackbox *) -module NX_WFG(SI, ZI, RDY, SO, ZO); - input RDY; - input SI; - output SO; - input ZI; - output ZO; - parameter delay = 0; - parameter delay_on = 1'b0; - parameter location = ""; - parameter mode = 1'b0; - parameter pattern = 16'b0000000000000000; - parameter pattern_end = 1; - parameter wfg_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_WFG_L(R, SI, ZI, RDY, SO, ZO); - input R; - input RDY; - input SI; - output SO; - input ZI; - output ZO; - parameter delay = 0; - parameter delay_on = 1'b0; - parameter location = ""; - parameter mode = 1'b0; - parameter pattern = 16'b0000000000000000; - parameter pattern_end = 1; - parameter wfg_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_WFG_U(R, SI, ZI, SO, ZO); - input R; - input SI; - output SO; - input ZI; - output ZO; - parameter delay = 0; - parameter delay_on = 1'b0; - parameter div_phase = 1'b0; - parameter div_ratio = 0; - parameter location = ""; - parameter mode = 0; - parameter pattern = 16'b0000000000000000; - parameter pattern_end = 0; - parameter reset_on_cal_lock_n = 1'b0; - parameter reset_on_pll_lock_n = 1'b0; - parameter reset_on_pll_locka_n = 1'b0; - parameter wfg_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO -, AO, BO, AI, DI, DO); - input ADRSTI; - output ADRSTO; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - output ASRSTO; - input BDRSTI; - output BDRSTO; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - output BSRSTO; - input CDRSTI; - output CDRSTO; - input [5:0] CI; - input CK1; - input CK2; - output [5:0] CO; - input CSRSTI; - output CSRSTO; - input DDRSTI; - output DDRSTO; - input [5:0] DI; - output [5:0] DO; - input DSRSTI; - output DSRSTO; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter cck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter dck_sel = 1'b0; - parameter link_BA = 1'b0; - parameter link_CB = 1'b0; - parameter link_DC = 1'b0; - parameter use_adest_arst = 1'b0; - parameter use_asrc_arst = 1'b0; - parameter use_bdest_arst = 1'b0; - parameter use_bsrc_arst = 1'b0; - parameter use_cdest_arst = 1'b0; - parameter use_csrc_arst = 1'b0; - parameter use_ddest_arst = 1'b0; - parameter use_dsrc_arst = 1'b0; -endmodule - (* blackbox *) module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO); input [35:0] I; diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index 991600e65..cae2a0f29 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -501,3 +501,1444 @@ module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, parameter wfg_sync_cal_lock = 1'b0; parameter wfg_sync_pll_lock = 1'b0; endmodule + +(* blackbox *) +module NX_WFG_L(R, SI, ZI, RDY, SO, ZO); + input R; + input RDY; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter location = ""; + parameter mode = 1'b0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 1; + parameter wfg_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3 +, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24 +, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45 +, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2 +, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7 +, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4 +, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK); + input ALIGN_E_I; + output ALIGN_O; + input ALIGN_S_I; + input BUF_FE_I; + input BUF_R_I; + output BUSY_O; + input CDR_R_I; + output CH_A_O1; + output CH_A_O2; + output CH_A_O3; + output CH_A_O4; + output CH_A_O5; + output CH_A_O6; + output CH_A_O7; + output CH_A_O8; + output CH_COM_O1; + output CH_COM_O2; + output CH_COM_O3; + output CH_COM_O4; + output CH_COM_O5; + output CH_COM_O6; + output CH_COM_O7; + output CH_COM_O8; + output CH_F_O1; + output CH_F_O2; + output CH_F_O3; + output CH_F_O4; + output CH_F_O5; + output CH_F_O6; + output CH_F_O7; + output CH_F_O8; + output CH_K_O1; + output CH_K_O2; + output CH_K_O3; + output CH_K_O4; + output CH_K_O5; + output CH_K_O6; + output CH_K_O7; + output CH_K_O8; + input CKG_RN_I; + output DATA_O1; + output DATA_O10; + output DATA_O11; + output DATA_O12; + output DATA_O13; + output DATA_O14; + output DATA_O15; + output DATA_O16; + output DATA_O17; + output DATA_O18; + output DATA_O19; + output DATA_O2; + output DATA_O20; + output DATA_O21; + output DATA_O22; + output DATA_O23; + output DATA_O24; + output DATA_O25; + output DATA_O26; + output DATA_O27; + output DATA_O28; + output DATA_O29; + output DATA_O3; + output DATA_O30; + output DATA_O31; + output DATA_O32; + output DATA_O33; + output DATA_O34; + output DATA_O35; + output DATA_O36; + output DATA_O37; + output DATA_O38; + output DATA_O39; + output DATA_O4; + output DATA_O40; + output DATA_O41; + output DATA_O42; + output DATA_O43; + output DATA_O44; + output DATA_O45; + output DATA_O46; + output DATA_O47; + output DATA_O48; + output DATA_O49; + output DATA_O5; + output DATA_O50; + output DATA_O51; + output DATA_O52; + output DATA_O53; + output DATA_O54; + output DATA_O55; + output DATA_O56; + output DATA_O57; + output DATA_O58; + output DATA_O59; + output DATA_O6; + output DATA_O60; + output DATA_O61; + output DATA_O62; + output DATA_O63; + output DATA_O64; + output DATA_O7; + output DATA_O8; + output DATA_O9; + input DEC_E_I; + input DSCR_E_I; + output D_ERR_O1; + output D_ERR_O2; + output D_ERR_O3; + output D_ERR_O4; + output D_ERR_O5; + output D_ERR_O6; + output D_ERR_O7; + output D_ERR_O8; + inout [9:0] LINK; + output LOCK_O; + output LOS_O; + output NIT_O1; + output NIT_O2; + output NIT_O3; + output NIT_O4; + output NIT_O5; + output NIT_O6; + output NIT_O7; + output NIT_O8; + input OVS_BS_I1; + input OVS_BS_I2; + input PLL_RN_I; + input REP_E_I; + input RST_N_I; + input RX_I; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + parameter location = ""; + parameter pcs_8b_dscr_sel = 1'b0; + parameter pcs_align_bypass = 1'b0; + parameter pcs_buffers_bypass = 1'b0; + parameter pcs_buffers_use_cdc = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_comma_mask = 10'b0000000000; + parameter pcs_debug_en = 1'b0; + parameter pcs_dec_bypass = 1'b0; + parameter pcs_dscr_bypass = 1'b0; + parameter pcs_el_buff_diff_bef_comp = 3'b000; + parameter pcs_el_buff_max_comp = 3'b000; + parameter pcs_el_buff_only_one_skp = 1'b0; + parameter pcs_el_buff_skp_char_0 = 9'b000000000; + parameter pcs_el_buff_skp_char_1 = 9'b000000000; + parameter pcs_el_buff_skp_char_2 = 9'b000000000; + parameter pcs_el_buff_skp_char_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_0 = 9'b000000000; + parameter pcs_el_buff_skp_header_1 = 9'b000000000; + parameter pcs_el_buff_skp_header_2 = 9'b000000000; + parameter pcs_el_buff_skp_header_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_size = 2'b00; + parameter pcs_el_buff_skp_seq_size = 2'b00; + parameter pcs_el_buff_underflow_handle = 1'b0; + parameter pcs_fsm_sel = 2'b00; + parameter pcs_fsm_watchdog_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_m_comma_en = 1'b0; + parameter pcs_m_comma_val = 10'b0000000000; + parameter pcs_nb_comma_bef_realign = 2'b00; + parameter pcs_p_comma_en = 1'b0; + parameter pcs_p_comma_val = 10'b0000000000; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_sync_supported = 1'b0; + parameter pma_cdr_cp = 4'b0000; + parameter pma_clk_pos = 1'b0; + parameter pma_ctrl_term = 6'b000000; + parameter pma_loopback = 1'b0; + parameter pma_pll_cpump_n = 3'b000; + parameter pma_pll_divf = 2'b00; + parameter pma_pll_divf_en_n = 1'b0; + parameter pma_pll_divm = 2'b00; + parameter pma_pll_divm_en_n = 1'b0; + parameter pma_pll_divn = 1'b0; + parameter pma_pll_divn_en_n = 1'b0; + parameter test = 2'b00; +endmodule + +(* blackbox *) +module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 +, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I +, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17 +, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38 +, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59 +, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK); + output BUSY_O; + input CH_K_I1; + input CH_K_I2; + input CH_K_I3; + input CH_K_I4; + input CH_K_I5; + input CH_K_I6; + input CH_K_I7; + input CH_K_I8; + input CLK_E_I; + input DATA_I1; + input DATA_I10; + input DATA_I11; + input DATA_I12; + input DATA_I13; + input DATA_I14; + input DATA_I15; + input DATA_I16; + input DATA_I17; + input DATA_I18; + input DATA_I19; + input DATA_I2; + input DATA_I20; + input DATA_I21; + input DATA_I22; + input DATA_I23; + input DATA_I24; + input DATA_I25; + input DATA_I26; + input DATA_I27; + input DATA_I28; + input DATA_I29; + input DATA_I3; + input DATA_I30; + input DATA_I31; + input DATA_I32; + input DATA_I33; + input DATA_I34; + input DATA_I35; + input DATA_I36; + input DATA_I37; + input DATA_I38; + input DATA_I39; + input DATA_I4; + input DATA_I40; + input DATA_I41; + input DATA_I42; + input DATA_I43; + input DATA_I44; + input DATA_I45; + input DATA_I46; + input DATA_I47; + input DATA_I48; + input DATA_I49; + input DATA_I5; + input DATA_I50; + input DATA_I51; + input DATA_I52; + input DATA_I53; + input DATA_I54; + input DATA_I55; + input DATA_I56; + input DATA_I57; + input DATA_I58; + input DATA_I59; + input DATA_I6; + input DATA_I60; + input DATA_I61; + input DATA_I62; + input DATA_I63; + input DATA_I64; + input DATA_I7; + input DATA_I8; + input DATA_I9; + input ENC_E_I1; + input ENC_E_I2; + input ENC_E_I3; + input ENC_E_I4; + input ENC_E_I5; + input ENC_E_I6; + input ENC_E_I7; + input ENC_E_I8; + input EOF_I1; + input EOF_I2; + input EOF_I3; + input EOF_I4; + input EOF_I5; + input EOF_I6; + input EOF_I7; + input EOF_I8; + input EOMF_I1; + input EOMF_I2; + input EOMF_I3; + input EOMF_I4; + input EOMF_I5; + input EOMF_I6; + input EOMF_I7; + input EOMF_I8; + inout [19:0] LINK; + input REP_E_I; + input RST_N_I; + input SCR_E_I1; + input SCR_E_I2; + input SCR_E_I3; + input SCR_E_I4; + input SCR_E_I5; + input SCR_E_I6; + input SCR_E_I7; + input SCR_E_I8; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TX_O; + parameter location = ""; + parameter pcs_8b_scr_sel = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_enc_bypass = 1'b0; + parameter pcs_esistream_fsm_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_scr_bypass = 1'b0; + parameter pcs_scr_init = 17'b00000000000000000; + parameter pcs_sync_supported = 1'b0; + parameter pma_clk_pos = 1'b0; + parameter pma_loopback = 1'b0; + parameter test = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 +, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1 +, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR +, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL +, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI +, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4 +, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3 +, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2 +, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1 +, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO +, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI +, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO +, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR +, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL +, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1 +, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5 +, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4 +, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3 +, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2 +, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1 +, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR +, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL +, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI +, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO +, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER +, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL +, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5 +, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4 +, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3 +, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2 +, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR +, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL +, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1 +, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5 +, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4 +, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3 +, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2 +, P34RO3, P34RO4, P34RO5); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + input P24RR; + input P25CI1; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + input P28RR; + input P29CI1; + input P29CI2; + input P29CI3; + input P29CI4; + input P29CI5; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + input P30RR; + input P31CI1; + input P31CL; + output P31CO; + input P31CR; + input P31CTI; + output P31CTO; + input P31EI1; + input P31EI2; + input P31EI3; + input P31EI4; + input P31EI5; + input P31EL; + output P31EO; + input P31ER; + input P31RI; + input P31RL; + output P31RO1; + output P31RO2; + output P31RO3; + output P31RO4; + output P31RO5; + input P31RR; + input P32CI1; + input P32CL; + output P32CO; + input P32CR; + input P32CTI; + output P32CTO; + input P32EI1; + input P32EI2; + input P32EI3; + input P32EI4; + input P32EI5; + input P32EL; + output P32EO; + input P32ER; + input P32RI; + input P32RL; + output P32RO1; + output P32RO2; + output P32RO3; + output P32RO4; + output P32RO5; + input P32RR; + input P33CI1; + input P33CL; + output P33CO; + input P33CR; + input P33CTI; + output P33CTO; + input P33EI1; + input P33EI2; + input P33EI3; + input P33EI4; + input P33EI5; + input P33EL; + output P33EO; + input P33ER; + input P33RI; + input P33RL; + output P33RO1; + output P33RO2; + output P33RO3; + output P33RO4; + output P33RO5; + input P33RR; + input P34CI1; + input P34CL; + output P34CO; + input P34CR; + input P34CTI; + output P34CTO; + input P34EI1; + input P34EI2; + input P34EI3; + input P34EI4; + input P34EI5; + input P34EL; + output P34EO; + input P34ER; + input P34RI; + input P34RL; + output P34RO1; + output P34RO2; + output P34RO3; + output P34RO4; + output P34RO5; + input P34RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + input P4RR; + input P5CI1; + input P5CI2; + input P5CI3; + input P5CI4; + input P5CI5; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + input P9RR; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter mode_io_cal = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2 +, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3 +, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2 +, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2 +, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7 +, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2 +, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0); + input CAL_1P_I1; + input CAL_1P_I2; + input CAL_1P_I3; + input CAL_1P_I4; + input CAL_1P_I5; + input CAL_1P_I6; + input CAL_1P_I7; + input CAL_1P_I8; + input CAL_2N_I1; + input CAL_2N_I2; + input CAL_2N_I3; + input CAL_2N_I4; + input CAL_2N_I5; + input CAL_2N_I6; + input CAL_2N_I7; + input CAL_2N_I8; + input CAL_3N_I1; + input CAL_3N_I2; + input CAL_3N_I3; + input CAL_3N_I4; + input CAL_3N_I5; + input CAL_3N_I6; + input CAL_3N_I7; + input CAL_3N_I8; + input CAL_4P_I1; + input CAL_4P_I2; + input CAL_4P_I3; + input CAL_4P_I4; + input CAL_4P_I5; + input CAL_4P_I6; + input CAL_4P_I7; + input CAL_4P_I8; + input CAL_E_I; + output CAL_O; + input CAL_SEL_I1; + input CAL_SEL_I2; + input CAL_SEL_I3; + input CAL_SEL_I4; + input CLK_EXT_I; + output CLK_O; + input CLK_REF_I; + input CLK_USER_I; + input CT_CAP_I1; + input CT_CAP_I2; + input CT_CAP_I3; + input CT_CAP_I4; + input CT_RESN_I1; + input CT_RESN_I2; + input CT_RESN_I3; + input CT_RESN_I4; + input CT_RESP_I1; + input CT_RESP_I2; + input CT_RESP_I3; + input CT_RESP_I4; + inout [9:0] LINK_RX0; + inout [9:0] LINK_RX1; + inout [9:0] LINK_RX2; + inout [9:0] LINK_RX3; + inout [9:0] LINK_RX4; + inout [9:0] LINK_RX5; + inout [19:0] LINK_TX0; + inout [19:0] LINK_TX1; + inout [19:0] LINK_TX2; + inout [19:0] LINK_TX3; + inout [19:0] LINK_TX4; + inout [19:0] LINK_TX5; + input LOCK_E_I; + output LOCK_O; + input MAIN_EN_I1; + input MAIN_EN_I2; + input MAIN_EN_I3; + input MAIN_EN_I4; + input MAIN_EN_I5; + input MAIN_EN_I6; + input MAIN_SG_I; + input MARG_ISV_I1; + input MARG_ISV_I2; + input MARG_ISV_I3; + input MARG_ISV_I4; + input MARG_ISV_I5; + input MARG_IS_I1; + input MARG_IS_I2; + input MARG_IS_I3; + input MARG_IS_I4; + input MARG_SV_I1; + input MARG_SV_I2; + input MARG_SV_I3; + input MARG_SV_I4; + input MARG_SV_I5; + input MARG_S_I1; + input MARG_S_I2; + input MARG_S_I3; + input MARG_S_I4; + input M_EYE_I; + input OVS_E_I; + input PLL_RN_I; + input POST_EN_I1; + input POST_EN_I2; + input POST_EN_I3; + input POST_EN_I4; + input POST_EN_I5; + input POST_ISV_I1; + input POST_ISV_I2; + input POST_ISV_I3; + input POST_ISV_I4; + input POST_IS_I1; + input POST_IS_I2; + input POST_IS_I3; + input POST_IS_I4; + input POST_SG_I; + input PRE_EN_I; + input PRE_IS_I1; + input PRE_IS_I2; + input PRE_IS_I3; + input PRE_IS_I4; + input PRE_SG_I; + input RST_N_I; + input RX_SEL_I1; + input RX_SEL_I2; + input RX_SEL_I3; + input RX_SEL_I4; + input RX_SEL_I5; + input RX_SEL_I6; + input TST_I1; + input TST_I2; + input TST_I3; + input TST_I4; + input TST_I5; + input TST_I6; + input TST_I7; + input TST_I8; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + input TX_SEL_I1; + input TX_SEL_I2; + input TX_SEL_I3; + input TX_SEL_I4; + input TX_SEL_I5; + input TX_SEL_I6; + parameter location = ""; + parameter main_clk_to_fabric_div_en = 1'b0; + parameter main_clk_to_fabric_div_mode = 1'b0; + parameter main_clk_to_fabric_sel = 1'b0; + parameter main_test = 8'b00000000; + parameter main_use_only_usr_clock = 1'b0; + parameter main_use_pcs_clk_2 = 1'b0; + parameter pcs_ovs_mode = 1'b0; + parameter pcs_pll_lock_count = 3'b000; + parameter pcs_word_len = 2'b00; + parameter pll_pma_cpump_n = 3'b000; + parameter pll_pma_divf = 2'b00; + parameter pll_pma_divf_en_n = 1'b0; + parameter pll_pma_divm = 2'b00; + parameter pll_pma_divm_en_n = 1'b0; + parameter pll_pma_divn = 1'b0; + parameter pll_pma_divn_en_n = 1'b0; + parameter pll_pma_int_data_len = 1'b0; + parameter pll_pma_lvds_mux = 1'b0; + parameter pll_pma_mux_ckref = 1'b0; + parameter rx_pma_half_step = 1'b0; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index 0be57e720..620e9107d 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -401,3 +401,831 @@ module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY); parameter vco_range = 0; endmodule +(* blackbox *) +module NX_WFG(SI, ZI, RDY, SO, ZO); + input RDY; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter location = ""; + parameter mode = 1'b0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 1; + parameter wfg_edge = 1'b0; +endmodule + + +(* blackbox *) +module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1 +, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4 +, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3 +, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3 +, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR +, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL +, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI +, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO +, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3 +, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2 +, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1 +, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO +, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI +, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO +, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR +, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL +, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1 +, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5 +, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4 +, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3 +, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2 +, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1 +, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR +, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL +, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI +, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO +, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER +, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL +, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5 +, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO +, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI +, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO +, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR +, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL +, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1 +, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5 +); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + output FLD; + output FLG; + input FZ; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + input P24RR; + input P25CI1; + input P25CI2; + input P25CI3; + input P25CI4; + input P25CI5; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + input P28RR; + input P29CI1; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + input P30RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + input P4RR; + input P5CI1; + input P5CI2; + input P5CI3; + input P5CI4; + input P5CI5; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + input P9RR; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter mode_io_cal = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 988ddb4c5..2bcaa5326 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -549,3 +549,1803 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, parameter use_cal = 1'b0; parameter use_pll = 1'b1; endmodule + +(* blackbox *) +module NX_WFG_U(R, SI, ZI, SO, ZO); + input R; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter div_phase = 1'b0; + parameter div_ratio = 0; + parameter location = ""; + parameter mode = 0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 0; + parameter reset_on_cal_lock_n = 1'b0; + parameter reset_on_pll_lock_n = 1'b0; + parameter reset_on_pll_locka_n = 1'b0; + parameter wfg_edge = 1'b0; +endmodule + +(* blackbox *) +module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO +, AO, BO, AI, DI, DO); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CDRSTI; + output CDRSTO; + input [5:0] CI; + input CK1; + input CK2; + output [5:0] CO; + input CSRSTI; + output CSRSTO; + input DDRSTI; + output DDRSTO; + input [5:0] DI; + output [5:0] DO; + input DSRSTI; + output DSRSTO; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + parameter use_cdest_arst = 1'b0; + parameter use_csrc_arst = 1'b0; + parameter use_ddest_arst = 1'b0; + parameter use_dsrc_arst = 1'b0; +endmodule + +(* blackbox *) +module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6 +, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27 +, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48 +, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5 +, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2 +, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7 +, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK); + input ALIGN_E_I; + output ALIGN_O; + input ALIGN_S_I; + input BUF_R_I; + output BUSY_O; + output CH_A_O1; + output CH_A_O2; + output CH_A_O3; + output CH_A_O4; + output CH_A_O5; + output CH_A_O6; + output CH_A_O7; + output CH_A_O8; + output CH_COM_O1; + output CH_COM_O2; + output CH_COM_O3; + output CH_COM_O4; + output CH_COM_O5; + output CH_COM_O6; + output CH_COM_O7; + output CH_COM_O8; + output CH_F_O1; + output CH_F_O2; + output CH_F_O3; + output CH_F_O4; + output CH_F_O5; + output CH_F_O6; + output CH_F_O7; + output CH_F_O8; + output CH_K_O1; + output CH_K_O2; + output CH_K_O3; + output CH_K_O4; + output CH_K_O5; + output CH_K_O6; + output CH_K_O7; + output CH_K_O8; + output DATA_O1; + output DATA_O10; + output DATA_O11; + output DATA_O12; + output DATA_O13; + output DATA_O14; + output DATA_O15; + output DATA_O16; + output DATA_O17; + output DATA_O18; + output DATA_O19; + output DATA_O2; + output DATA_O20; + output DATA_O21; + output DATA_O22; + output DATA_O23; + output DATA_O24; + output DATA_O25; + output DATA_O26; + output DATA_O27; + output DATA_O28; + output DATA_O29; + output DATA_O3; + output DATA_O30; + output DATA_O31; + output DATA_O32; + output DATA_O33; + output DATA_O34; + output DATA_O35; + output DATA_O36; + output DATA_O37; + output DATA_O38; + output DATA_O39; + output DATA_O4; + output DATA_O40; + output DATA_O41; + output DATA_O42; + output DATA_O43; + output DATA_O44; + output DATA_O45; + output DATA_O46; + output DATA_O47; + output DATA_O48; + output DATA_O49; + output DATA_O5; + output DATA_O50; + output DATA_O51; + output DATA_O52; + output DATA_O53; + output DATA_O54; + output DATA_O55; + output DATA_O56; + output DATA_O57; + output DATA_O58; + output DATA_O59; + output DATA_O6; + output DATA_O60; + output DATA_O61; + output DATA_O62; + output DATA_O63; + output DATA_O64; + output DATA_O7; + output DATA_O8; + output DATA_O9; + input DBG_S_I1; + input DBG_S_I2; + input DBG_S_I3; + input DEC_E_I; + input DSCR_E_I; + output D_ERR_O1; + output D_ERR_O2; + output D_ERR_O3; + output D_ERR_O4; + output D_ERR_O5; + output D_ERR_O6; + output D_ERR_O7; + output D_ERR_O8; + inout [9:0] LINK; + output LL_FLOCK_O; + output LL_SLOCK_O; + output LOS_O; + input MEYE_RST_I; + output NIT_O1; + output NIT_O2; + output NIT_O3; + output NIT_O4; + output NIT_O5; + output NIT_O6; + output NIT_O7; + output NIT_O8; + input OVS_BS_I1; + input OVS_BS_I2; + output PLL_LOCKT_O; + output PLL_LOCK_O; + input PMA_RSTN_I; + input PWDN_N_I; + input REP_E_I; + input RST_N_I; + output TST_O1; + output TST_O2; + output TST_O3; + output TST_O4; + output TST_O5; + output TST_O6; + output TST_O7; + output TST_O8; + output VREALIGN_O; + parameter gearbox_en = 1'b0; + parameter gearbox_mode = 1'b0; + parameter location = ""; + parameter pcs_8b_dscr_sel = 1'b0; + parameter pcs_align_bypass = 1'b0; + parameter pcs_buffers_bypass = 1'b0; + parameter pcs_buffers_use_cdc = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_comma_mask = 10'b0000000000; + parameter pcs_debug_en = 1'b0; + parameter pcs_dec_bypass = 1'b0; + parameter pcs_dscr_bypass = 1'b0; + parameter pcs_el_buff_diff_bef_comp = 4'b0000; + parameter pcs_el_buff_max_comp = 4'b0000; + parameter pcs_el_buff_only_one_skp = 1'b0; + parameter pcs_el_buff_skp_char_0 = 9'b000000000; + parameter pcs_el_buff_skp_char_1 = 9'b000000000; + parameter pcs_el_buff_skp_char_2 = 9'b000000000; + parameter pcs_el_buff_skp_char_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_0 = 9'b000000000; + parameter pcs_el_buff_skp_header_1 = 9'b000000000; + parameter pcs_el_buff_skp_header_2 = 9'b000000000; + parameter pcs_el_buff_skp_header_3 = 9'b000000000; + parameter pcs_el_buff_skp_header_size = 2'b00; + parameter pcs_el_buff_skp_seq_size = 2'b00; + parameter pcs_fsm_sel = 2'b00; + parameter pcs_fsm_watchdog_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_m_comma_en = 1'b0; + parameter pcs_m_comma_val = 10'b0000000000; + parameter pcs_nb_comma_bef_realign = 2'b00; + parameter pcs_p_comma_en = 1'b0; + parameter pcs_p_comma_val = 10'b0000000000; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_sync_supported = 1'b0; + parameter pma_cdr_cp = 4'b0000; + parameter pma_clk_pos = 1'b0; + parameter pma_coarse_ppm = 3'b000; + parameter pma_ctrl_term = 6'b000000; + parameter pma_dco_divl = 2'b00; + parameter pma_dco_divm = 1'b0; + parameter pma_dco_divn = 2'b00; + parameter pma_dco_reg_res = 2'b00; + parameter pma_dco_vref_sel = 1'b0; + parameter pma_fine_ppm = 3'b000; + parameter pma_loopback = 1'b0; + parameter pma_m_eye_ppm = 3'b000; + parameter pma_peak_detect_cmd = 2'b00; + parameter pma_peak_detect_on = 1'b0; + parameter pma_pll_cpump_n = 3'b000; + parameter pma_pll_divf = 2'b00; + parameter pma_pll_divf_en_n = 1'b0; + parameter pma_pll_divm = 2'b00; + parameter pma_pll_divm_en_n = 1'b0; + parameter pma_pll_divn = 1'b0; + parameter pma_pll_divn_en_n = 1'b0; +endmodule + + +(* blackbox *) +module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5 +, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I +, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21 +, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42 +, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63 +, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK); + output BUSY_O; + input CH_K_I1; + input CH_K_I2; + input CH_K_I3; + input CH_K_I4; + input CH_K_I5; + input CH_K_I6; + input CH_K_I7; + input CH_K_I8; + input CLK_E_I; + output CLK_O; + input DATA_I1; + input DATA_I10; + input DATA_I11; + input DATA_I12; + input DATA_I13; + input DATA_I14; + input DATA_I15; + input DATA_I16; + input DATA_I17; + input DATA_I18; + input DATA_I19; + input DATA_I2; + input DATA_I20; + input DATA_I21; + input DATA_I22; + input DATA_I23; + input DATA_I24; + input DATA_I25; + input DATA_I26; + input DATA_I27; + input DATA_I28; + input DATA_I29; + input DATA_I3; + input DATA_I30; + input DATA_I31; + input DATA_I32; + input DATA_I33; + input DATA_I34; + input DATA_I35; + input DATA_I36; + input DATA_I37; + input DATA_I38; + input DATA_I39; + input DATA_I4; + input DATA_I40; + input DATA_I41; + input DATA_I42; + input DATA_I43; + input DATA_I44; + input DATA_I45; + input DATA_I46; + input DATA_I47; + input DATA_I48; + input DATA_I49; + input DATA_I5; + input DATA_I50; + input DATA_I51; + input DATA_I52; + input DATA_I53; + input DATA_I54; + input DATA_I55; + input DATA_I56; + input DATA_I57; + input DATA_I58; + input DATA_I59; + input DATA_I6; + input DATA_I60; + input DATA_I61; + input DATA_I62; + input DATA_I63; + input DATA_I64; + input DATA_I7; + input DATA_I8; + input DATA_I9; + input ENC_E_I1; + input ENC_E_I2; + input ENC_E_I3; + input ENC_E_I4; + input ENC_E_I5; + input ENC_E_I6; + input ENC_E_I7; + input ENC_E_I8; + input EOF_I1; + input EOF_I2; + input EOF_I3; + input EOF_I4; + input EOF_I5; + input EOF_I6; + input EOF_I7; + input EOF_I8; + input EOMF_I1; + input EOMF_I2; + input EOMF_I3; + input EOMF_I4; + input EOMF_I5; + input EOMF_I6; + input EOMF_I7; + input EOMF_I8; + output INV_K_O; + inout [19:0] LINK; + input PWDN_N_I; + input REP_E_I; + input RST_N_I; + input SCR_E_I1; + input SCR_E_I2; + input SCR_E_I3; + input SCR_E_I4; + input SCR_E_I5; + input SCR_E_I6; + input SCR_E_I7; + input SCR_E_I8; + parameter gearbox_en = 1'b0; + parameter gearbox_mode = 1'b0; + parameter location = ""; + parameter pcs_8b_scr_sel = 1'b0; + parameter pcs_bypass_pma_cdc = 1'b0; + parameter pcs_bypass_usr_cdc = 1'b0; + parameter pcs_enc_bypass = 1'b0; + parameter pcs_esistream_fsm_en = 1'b0; + parameter pcs_loopback = 1'b0; + parameter pcs_polarity = 1'b0; + parameter pcs_protocol_size = 1'b0; + parameter pcs_replace_bypass = 1'b0; + parameter pcs_scr_bypass = 1'b0; + parameter pcs_scr_init = 17'b00000000000000000; + parameter pcs_sync_supported = 1'b0; + parameter pma_clk_pos = 1'b0; + parameter pma_loopback = 1'b0; +endmodule + +(* blackbox *) +module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 +, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 +, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN +, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN +, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 +, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 +, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL +, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6 +, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI +, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6 +, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL +, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6 +, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI +, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6 +, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL +, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6 +, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI +, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6 +, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL +, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6 +, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI +, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6 +, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL +, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6 +, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI +, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6 +, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL +, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6 +, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI +, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6 +, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL +, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6 +, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI +, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6 +, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL +, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6 +, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI +, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6 +, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL +, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6 +, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI +, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6 +, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL +, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6 +, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI +, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6 +, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL +, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6 +, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI +, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6 +, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL +, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8); + output AL1D; + output AL1T; + output AL2D; + output AL2T; + output AL3D; + output AL3T; + input ALCK1; + input ALCK2; + input ALCK3; + input CA1D1; + input CA1D2; + input CA1D3; + input CA1D4; + input CA1D5; + input CA1D6; + input CA1N1; + input CA1N2; + input CA1N3; + input CA1N4; + input CA1P1; + input CA1P2; + input CA1P3; + input CA1P4; + input CA1T1; + input CA1T2; + input CA1T3; + input CA1T4; + input CA2D1; + input CA2D2; + input CA2D3; + input CA2D4; + input CA2D5; + input CA2D6; + input CA2N1; + input CA2N2; + input CA2N3; + input CA2N4; + input CA2P1; + input CA2P2; + input CA2P3; + input CA2P4; + input CA2T1; + input CA2T2; + input CA2T3; + input CA2T4; + input CCK; + output CKO1; + output CKO2; + output DCL; + input DCRN; + input DQ1CI1; + input DQ1CI2; + input DQ1CI3; + input DQ1CI4; + input DQ1CI5; + input DQ1CI6; + input DQ1CI7; + input DQ1CI8; + input DQ2CI1; + input DQ2CI2; + input DQ2CI3; + input DQ2CI4; + input DQ2CI5; + input DQ2CI6; + input DQ2CI7; + input DQ2CI8; + input DQ3CI1; + input DQ3CI2; + input DQ3CI3; + input DQ3CI4; + input DQ3CI5; + input DQ3CI6; + input DQ3CI7; + input DQ3CI8; + input DQS1CI1; + input DQS1CI2; + input DQS1CI3; + input DQS1CI4; + input DQS1CI5; + input DQS1CI6; + input DQS1CI7; + input DQS1CI8; + input DQS2CI1; + input DQS2CI2; + input DQS2CI3; + input DQS2CI4; + input DQS2CI5; + input DQS2CI6; + input DQS2CI7; + input DQS2CI8; + input DQS3CI1; + input DQS3CI2; + input DQS3CI3; + input DQS3CI4; + input DQS3CI5; + input DQS3CI6; + input DQS3CI7; + input DQS3CI8; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRCCSN; + input DRDPA1CSN; + input DRDPA2CSN; + input DRDPA3CSN; + input DRE; + input DRI1; + input DRI1CSN; + input DRI2; + input DRI2CSN; + input DRI3; + input DRI3CSN; + input DRI4; + input DRI5; + input DRI6; + output DRO1; + input DRO1CSN; + output DRO2; + input DRO2CSN; + output DRO3; + input DRO3CSN; + output DRO4; + output DRO5; + output DRO6; + input DRWDS; + input DRWEN; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + input FCK1; + input FCK2; + input FDCK; + output FLD; + output FLG; + input FZ; + input LD1RN; + input LD2RN; + input LD3RN; + input LDSCK1; + input LDSCK2; + input LDSCK3; + input LE; + input P10CI1; + input P10CL; + output P10CO; + input P10CR; + input P10CTI; + output P10CTO; + input P10EI1; + input P10EI2; + input P10EI3; + input P10EI4; + input P10EI5; + input P10EI6; + input P10EI7; + input P10EI8; + input P10EL; + output P10EO; + input P10ER; + input P10RI; + input P10RL; + output P10RO1; + output P10RO2; + output P10RO3; + output P10RO4; + output P10RO5; + output P10RO6; + output P10RO7; + output P10RO8; + input P10RR; + input P11CI1; + input P11CL; + output P11CO; + input P11CR; + input P11CTI; + output P11CTO; + input P11EI1; + input P11EI2; + input P11EI3; + input P11EI4; + input P11EI5; + input P11EI6; + input P11EI7; + input P11EI8; + input P11EL; + output P11EO; + input P11ER; + input P11RI; + input P11RL; + output P11RO1; + output P11RO2; + output P11RO3; + output P11RO4; + output P11RO5; + output P11RO6; + output P11RO7; + output P11RO8; + input P11RR; + input P12CI1; + input P12CL; + output P12CO; + input P12CR; + input P12CTI; + output P12CTO; + input P12EI1; + input P12EI2; + input P12EI3; + input P12EI4; + input P12EI5; + input P12EI6; + input P12EI7; + input P12EI8; + input P12EL; + output P12EO; + input P12ER; + input P12RI; + input P12RL; + output P12RO1; + output P12RO2; + output P12RO3; + output P12RO4; + output P12RO5; + output P12RO6; + output P12RO7; + output P12RO8; + input P12RR; + input P13CI1; + input P13CL; + output P13CO; + input P13CR; + input P13CTI; + output P13CTO; + input P13EI1; + input P13EI2; + input P13EI3; + input P13EI4; + input P13EI5; + input P13EI6; + input P13EI7; + input P13EI8; + input P13EL; + output P13EO; + input P13ER; + input P13RI; + input P13RL; + output P13RO1; + output P13RO2; + output P13RO3; + output P13RO4; + output P13RO5; + output P13RO6; + output P13RO7; + output P13RO8; + input P13RR; + input P14CI1; + input P14CL; + output P14CO; + input P14CR; + input P14CTI; + output P14CTO; + input P14EI1; + input P14EI2; + input P14EI3; + input P14EI4; + input P14EI5; + input P14EI6; + input P14EI7; + input P14EI8; + input P14EL; + output P14EO; + input P14ER; + input P14RI; + input P14RL; + output P14RO1; + output P14RO2; + output P14RO3; + output P14RO4; + output P14RO5; + output P14RO6; + output P14RO7; + output P14RO8; + input P14RR; + input P15CI1; + input P15CL; + output P15CO; + input P15CR; + input P15CTI; + output P15CTO; + input P15EI1; + input P15EI2; + input P15EI3; + input P15EI4; + input P15EI5; + input P15EI6; + input P15EI7; + input P15EI8; + input P15EL; + output P15EO; + input P15ER; + input P15RI; + input P15RL; + output P15RO1; + output P15RO2; + output P15RO3; + output P15RO4; + output P15RO5; + output P15RO6; + output P15RO7; + output P15RO8; + input P15RR; + input P16CI1; + input P16CL; + output P16CO; + input P16CR; + input P16CTI; + output P16CTO; + input P16EI1; + input P16EI2; + input P16EI3; + input P16EI4; + input P16EI5; + input P16EI6; + input P16EI7; + input P16EI8; + input P16EL; + output P16EO; + input P16ER; + input P16RI; + input P16RL; + output P16RO1; + output P16RO2; + output P16RO3; + output P16RO4; + output P16RO5; + output P16RO6; + output P16RO7; + output P16RO8; + input P16RR; + input P17CI1; + input P17CL; + output P17CO; + input P17CR; + input P17CTI; + output P17CTO; + input P17EI1; + input P17EI2; + input P17EI3; + input P17EI4; + input P17EI5; + input P17EI6; + input P17EI7; + input P17EI8; + input P17EL; + output P17EO; + input P17ER; + input P17RI; + input P17RL; + output P17RO1; + output P17RO2; + output P17RO3; + output P17RO4; + output P17RO5; + output P17RO6; + output P17RO7; + output P17RO8; + input P17RR; + input P18CI1; + input P18CL; + output P18CO; + input P18CR; + input P18CTI; + output P18CTO; + input P18EI1; + input P18EI2; + input P18EI3; + input P18EI4; + input P18EI5; + input P18EI6; + input P18EI7; + input P18EI8; + input P18EL; + output P18EO; + input P18ER; + input P18RI; + input P18RL; + output P18RO1; + output P18RO2; + output P18RO3; + output P18RO4; + output P18RO5; + output P18RO6; + output P18RO7; + output P18RO8; + input P18RR; + input P19CI1; + input P19CL; + output P19CO; + input P19CR; + input P19CTI; + output P19CTO; + input P19EI1; + input P19EI2; + input P19EI3; + input P19EI4; + input P19EI5; + input P19EI6; + input P19EI7; + input P19EI8; + input P19EL; + output P19EO; + input P19ER; + input P19RI; + input P19RL; + output P19RO1; + output P19RO2; + output P19RO3; + output P19RO4; + output P19RO5; + output P19RO6; + output P19RO7; + output P19RO8; + input P19RR; + input P1CI1; + input P1CL; + output P1CO; + input P1CR; + input P1CTI; + output P1CTO; + input P1EI1; + input P1EI2; + input P1EI3; + input P1EI4; + input P1EI5; + input P1EI6; + input P1EI7; + input P1EI8; + input P1EL; + output P1EO; + input P1ER; + input P1RI; + input P1RL; + output P1RO1; + output P1RO2; + output P1RO3; + output P1RO4; + output P1RO5; + output P1RO6; + output P1RO7; + output P1RO8; + input P1RR; + input P20CI1; + input P20CL; + output P20CO; + input P20CR; + input P20CTI; + output P20CTO; + input P20EI1; + input P20EI2; + input P20EI3; + input P20EI4; + input P20EI5; + input P20EI6; + input P20EI7; + input P20EI8; + input P20EL; + output P20EO; + input P20ER; + input P20RI; + input P20RL; + output P20RO1; + output P20RO2; + output P20RO3; + output P20RO4; + output P20RO5; + output P20RO6; + output P20RO7; + output P20RO8; + input P20RR; + input P21CI1; + input P21CL; + output P21CO; + input P21CR; + input P21CTI; + output P21CTO; + input P21EI1; + input P21EI2; + input P21EI3; + input P21EI4; + input P21EI5; + input P21EI6; + input P21EI7; + input P21EI8; + input P21EL; + output P21EO; + input P21ER; + input P21RI; + input P21RL; + output P21RO1; + output P21RO2; + output P21RO3; + output P21RO4; + output P21RO5; + output P21RO6; + output P21RO7; + output P21RO8; + input P21RR; + input P22CI1; + input P22CL; + output P22CO; + input P22CR; + input P22CTI; + output P22CTO; + input P22EI1; + input P22EI2; + input P22EI3; + input P22EI4; + input P22EI5; + input P22EI6; + input P22EI7; + input P22EI8; + input P22EL; + output P22EO; + input P22ER; + input P22RI; + input P22RL; + output P22RO1; + output P22RO2; + output P22RO3; + output P22RO4; + output P22RO5; + output P22RO6; + output P22RO7; + output P22RO8; + input P22RR; + input P23CI1; + input P23CL; + output P23CO; + input P23CR; + input P23CTI; + output P23CTO; + input P23EI1; + input P23EI2; + input P23EI3; + input P23EI4; + input P23EI5; + input P23EI6; + input P23EI7; + input P23EI8; + input P23EL; + output P23EO; + input P23ER; + input P23RI; + input P23RL; + output P23RO1; + output P23RO2; + output P23RO3; + output P23RO4; + output P23RO5; + output P23RO6; + output P23RO7; + output P23RO8; + input P23RR; + input P24CI1; + input P24CL; + output P24CO; + input P24CR; + input P24CTI; + output P24CTO; + input P24EI1; + input P24EI2; + input P24EI3; + input P24EI4; + input P24EI5; + input P24EI6; + input P24EI7; + input P24EI8; + input P24EL; + output P24EO; + input P24ER; + input P24RI; + input P24RL; + output P24RO1; + output P24RO2; + output P24RO3; + output P24RO4; + output P24RO5; + output P24RO6; + output P24RO7; + output P24RO8; + input P24RR; + input P25CI1; + input P25CL; + output P25CO; + input P25CR; + input P25CTI; + output P25CTO; + input P25EI1; + input P25EI2; + input P25EI3; + input P25EI4; + input P25EI5; + input P25EI6; + input P25EI7; + input P25EI8; + input P25EL; + output P25EO; + input P25ER; + input P25RI; + input P25RL; + output P25RO1; + output P25RO2; + output P25RO3; + output P25RO4; + output P25RO5; + output P25RO6; + output P25RO7; + output P25RO8; + input P25RR; + input P26CI1; + input P26CL; + output P26CO; + input P26CR; + input P26CTI; + output P26CTO; + input P26EI1; + input P26EI2; + input P26EI3; + input P26EI4; + input P26EI5; + input P26EI6; + input P26EI7; + input P26EI8; + input P26EL; + output P26EO; + input P26ER; + input P26RI; + input P26RL; + output P26RO1; + output P26RO2; + output P26RO3; + output P26RO4; + output P26RO5; + output P26RO6; + output P26RO7; + output P26RO8; + input P26RR; + input P27CI1; + input P27CL; + output P27CO; + input P27CR; + input P27CTI; + output P27CTO; + input P27EI1; + input P27EI2; + input P27EI3; + input P27EI4; + input P27EI5; + input P27EI6; + input P27EI7; + input P27EI8; + input P27EL; + output P27EO; + input P27ER; + input P27RI; + input P27RL; + output P27RO1; + output P27RO2; + output P27RO3; + output P27RO4; + output P27RO5; + output P27RO6; + output P27RO7; + output P27RO8; + input P27RR; + input P28CI1; + input P28CL; + output P28CO; + input P28CR; + input P28CTI; + output P28CTO; + input P28EI1; + input P28EI2; + input P28EI3; + input P28EI4; + input P28EI5; + input P28EI6; + input P28EI7; + input P28EI8; + input P28EL; + output P28EO; + input P28ER; + input P28RI; + input P28RL; + output P28RO1; + output P28RO2; + output P28RO3; + output P28RO4; + output P28RO5; + output P28RO6; + output P28RO7; + output P28RO8; + input P28RR; + input P29CI1; + input P29CL; + output P29CO; + input P29CR; + input P29CTI; + output P29CTO; + input P29EI1; + input P29EI2; + input P29EI3; + input P29EI4; + input P29EI5; + input P29EI6; + input P29EI7; + input P29EI8; + input P29EL; + output P29EO; + input P29ER; + input P29RI; + input P29RL; + output P29RO1; + output P29RO2; + output P29RO3; + output P29RO4; + output P29RO5; + output P29RO6; + output P29RO7; + output P29RO8; + input P29RR; + input P2CI1; + input P2CL; + output P2CO; + input P2CR; + input P2CTI; + output P2CTO; + input P2EI1; + input P2EI2; + input P2EI3; + input P2EI4; + input P2EI5; + input P2EI6; + input P2EI7; + input P2EI8; + input P2EL; + output P2EO; + input P2ER; + input P2RI; + input P2RL; + output P2RO1; + output P2RO2; + output P2RO3; + output P2RO4; + output P2RO5; + output P2RO6; + output P2RO7; + output P2RO8; + input P2RR; + input P30CI1; + input P30CL; + output P30CO; + input P30CR; + input P30CTI; + output P30CTO; + input P30EI1; + input P30EI2; + input P30EI3; + input P30EI4; + input P30EI5; + input P30EI6; + input P30EI7; + input P30EI8; + input P30EL; + output P30EO; + input P30ER; + input P30RI; + input P30RL; + output P30RO1; + output P30RO2; + output P30RO3; + output P30RO4; + output P30RO5; + output P30RO6; + output P30RO7; + output P30RO8; + input P30RR; + input P31CI1; + input P31CL; + output P31CO; + input P31CR; + input P31CTI; + output P31CTO; + input P31EI1; + input P31EI2; + input P31EI3; + input P31EI4; + input P31EI5; + input P31EI6; + input P31EI7; + input P31EI8; + input P31EL; + output P31EO; + input P31ER; + input P31RI; + input P31RL; + output P31RO1; + output P31RO2; + output P31RO3; + output P31RO4; + output P31RO5; + output P31RO6; + output P31RO7; + output P31RO8; + input P31RR; + input P32CI1; + input P32CL; + output P32CO; + input P32CR; + input P32CTI; + output P32CTO; + input P32EI1; + input P32EI2; + input P32EI3; + input P32EI4; + input P32EI5; + input P32EI6; + input P32EI7; + input P32EI8; + input P32EL; + output P32EO; + input P32ER; + input P32RI; + input P32RL; + output P32RO1; + output P32RO2; + output P32RO3; + output P32RO4; + output P32RO5; + output P32RO6; + output P32RO7; + output P32RO8; + input P32RR; + input P33CI1; + input P33CL; + output P33CO; + input P33CR; + input P33CTI; + output P33CTO; + input P33EI1; + input P33EI2; + input P33EI3; + input P33EI4; + input P33EI5; + input P33EI6; + input P33EI7; + input P33EI8; + input P33EL; + output P33EO; + input P33ER; + input P33RI; + input P33RL; + output P33RO1; + output P33RO2; + output P33RO3; + output P33RO4; + output P33RO5; + output P33RO6; + output P33RO7; + output P33RO8; + input P33RR; + input P34CI1; + input P34CL; + output P34CO; + input P34CR; + input P34CTI; + output P34CTO; + input P34EI1; + input P34EI2; + input P34EI3; + input P34EI4; + input P34EI5; + input P34EI6; + input P34EI7; + input P34EI8; + input P34EL; + output P34EO; + input P34ER; + input P34RI; + input P34RL; + output P34RO1; + output P34RO2; + output P34RO3; + output P34RO4; + output P34RO5; + output P34RO6; + output P34RO7; + output P34RO8; + input P34RR; + input P3CI1; + input P3CL; + output P3CO; + input P3CR; + input P3CTI; + output P3CTO; + input P3EI1; + input P3EI2; + input P3EI3; + input P3EI4; + input P3EI5; + input P3EI6; + input P3EI7; + input P3EI8; + input P3EL; + output P3EO; + input P3ER; + input P3RI; + input P3RL; + output P3RO1; + output P3RO2; + output P3RO3; + output P3RO4; + output P3RO5; + output P3RO6; + output P3RO7; + output P3RO8; + input P3RR; + input P4CI1; + input P4CL; + output P4CO; + input P4CR; + input P4CTI; + output P4CTO; + input P4EI1; + input P4EI2; + input P4EI3; + input P4EI4; + input P4EI5; + input P4EI6; + input P4EI7; + input P4EI8; + input P4EL; + output P4EO; + input P4ER; + input P4RI; + input P4RL; + output P4RO1; + output P4RO2; + output P4RO3; + output P4RO4; + output P4RO5; + output P4RO6; + output P4RO7; + output P4RO8; + input P4RR; + input P5CI1; + input P5CL; + output P5CO; + input P5CR; + input P5CTI; + output P5CTO; + input P5EI1; + input P5EI2; + input P5EI3; + input P5EI4; + input P5EI5; + input P5EI6; + input P5EI7; + input P5EI8; + input P5EL; + output P5EO; + input P5ER; + input P5RI; + input P5RL; + output P5RO1; + output P5RO2; + output P5RO3; + output P5RO4; + output P5RO5; + output P5RO6; + output P5RO7; + output P5RO8; + input P5RR; + input P6CI1; + input P6CL; + output P6CO; + input P6CR; + input P6CTI; + output P6CTO; + input P6EI1; + input P6EI2; + input P6EI3; + input P6EI4; + input P6EI5; + input P6EI6; + input P6EI7; + input P6EI8; + input P6EL; + output P6EO; + input P6ER; + input P6RI; + input P6RL; + output P6RO1; + output P6RO2; + output P6RO3; + output P6RO4; + output P6RO5; + output P6RO6; + output P6RO7; + output P6RO8; + input P6RR; + input P7CI1; + input P7CL; + output P7CO; + input P7CR; + input P7CTI; + output P7CTO; + input P7EI1; + input P7EI2; + input P7EI3; + input P7EI4; + input P7EI5; + input P7EI6; + input P7EI7; + input P7EI8; + input P7EL; + output P7EO; + input P7ER; + input P7RI; + input P7RL; + output P7RO1; + output P7RO2; + output P7RO3; + output P7RO4; + output P7RO5; + output P7RO6; + output P7RO7; + output P7RO8; + input P7RR; + input P8CI1; + input P8CL; + output P8CO; + input P8CR; + input P8CTI; + output P8CTO; + input P8EI1; + input P8EI2; + input P8EI3; + input P8EI4; + input P8EI5; + input P8EI6; + input P8EI7; + input P8EI8; + input P8EL; + output P8EO; + input P8ER; + input P8RI; + input P8RL; + output P8RO1; + output P8RO2; + output P8RO3; + output P8RO4; + output P8RO5; + output P8RO6; + output P8RO7; + output P8RO8; + input P8RR; + input P9CI1; + input P9CL; + output P9CO; + input P9CR; + input P9CTI; + output P9CTO; + input P9EI1; + input P9EI2; + input P9EI3; + input P9EI4; + input P9EI5; + input P9EI6; + input P9EI7; + input P9EI8; + input P9EL; + output P9EO; + input P9ER; + input P9RI; + input P9RL; + output P9RO1; + output P9RO2; + output P9RO3; + output P9RO4; + output P9RO5; + output P9RO6; + output P9RO7; + output P9RO8; + input P9RR; + input SE; + input SWRX1CK; + input SWRX2CK; + parameter cal_delay1 = ""; + parameter cal_delay2 = ""; + parameter div1 = 3'b000; + parameter div2 = 3'b000; + parameter div3 = 3'b000; + parameter div_swrx1 = 3'b000; + parameter div_swrx2 = 3'b000; + parameter inv_ld_sck1 = 1'b0; + parameter inv_ld_sck2 = 1'b0; + parameter inv_ld_sck3 = 1'b0; + parameter link_ld_12 = 1'b0; + parameter link_ld_23 = 1'b0; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_side3 = 0; + parameter pads_dict = ""; + parameter pads_path = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_dc_clk = 2'b00; + parameter sel_ld_fck1 = 2'b00; + parameter sel_ld_fck2 = 2'b00; + parameter sel_ld_fck3 = 2'b00; + parameter sel_sw_fck1 = 2'b00; + parameter sel_sw_fck2 = 2'b00; + parameter use_dc = 1'b0; +endmodule + +(* blackbox *) +module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6 +, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8 +, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14 +, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3 +, LINK_TX0); + output CAL_OUT_O; + output CLK_O; + input CLK_REF_I; + input CLK_RX_I; + output CLK_RX_O; + input CLK_TX_I; + input DBG_A_I; + output DBG_R_O; + input DBG_S_I1; + input DBG_S_I2; + input DC_ADD_I1; + input DC_ADD_I2; + input DC_ADD_I3; + input DC_ADD_I4; + input DC_CCSN_I; + input DC_E_I; + input DC_LCSN_I1; + input DC_LCSN_I2; + input DC_LCSN_I3; + input DC_LCSN_I4; + input DC_WDATAS_I; + input DC_WDATA_I1; + input DC_WDATA_I10; + input DC_WDATA_I11; + input DC_WDATA_I12; + input DC_WDATA_I2; + input DC_WDATA_I3; + input DC_WDATA_I4; + input DC_WDATA_I5; + input DC_WDATA_I6; + input DC_WDATA_I7; + input DC_WDATA_I8; + input DC_WDATA_I9; + input DC_WE_N_I; + output FB_LOCK_O; + inout [9:0] LINK_RX0; + inout [9:0] LINK_RX1; + inout [9:0] LINK_RX2; + inout [9:0] LINK_RX3; + inout [19:0] LINK_TX0; + inout [19:0] LINK_TX1; + inout [19:0] LINK_TX2; + inout [19:0] LINK_TX3; + output LL_O1; + output LL_O10; + output LL_O11; + output LL_O12; + output LL_O13; + output LL_O14; + output LL_O15; + output LL_O16; + output LL_O17; + output LL_O18; + output LL_O19; + output LL_O2; + output LL_O20; + output LL_O3; + output LL_O4; + output LL_O5; + output LL_O6; + output LL_O7; + output LL_O8; + output LL_O9; + output LOCKA_O; + output LOCK_O; + input PLL_RN_I; + input PWDN_N_I; + input RST_N_I; + input SCAN_I1; + input SCAN_I2; + input SCAN_I3; + input SCAN_I4; + input SCAN_I5; + input SCAN_I6; + input SCAN_I7; + input SCAN_I8; + output SCAN_O1; + output SCAN_O2; + output SCAN_O3; + output SCAN_O4; + output SCAN_O5; + output SCAN_O6; + output SCAN_O7; + output SCAN_O8; + input SE_I; + parameter dyn_all_rx_pma_m_eye = 1'b0; + parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0; + parameter dyn_all_rx_pma_m_eye_dn = 1'b0; + parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0; + parameter dyn_all_rx_pma_m_eye_step = 4'b0000; + parameter dyn_all_rx_pma_m_eye_up = 1'b0; + parameter dyn_all_rx_pma_threshold_1 = 5'b00000; + parameter dyn_all_rx_pma_threshold_2 = 5'b00000; + parameter dyn_all_rx_pma_trim_locked = 3'b000; + parameter dyn_all_rx_pma_trim_mode = 2'b00; + parameter dyn_all_rx_pma_trim_unlocked = 3'b000; + parameter dyn_rx0_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx0_pma_ctle_res_p = 4'b0000; + parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx0_pma_termination_cmd = 6'b000000; + parameter dyn_rx1_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx1_pma_ctle_res_p = 4'b0000; + parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx1_pma_termination_cmd = 6'b000000; + parameter dyn_rx2_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx2_pma_ctle_res_p = 4'b0000; + parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx2_pma_termination_cmd = 6'b000000; + parameter dyn_rx3_pma_ctle_cap_p = 4'b0000; + parameter dyn_rx3_pma_ctle_res_p = 4'b0000; + parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000; + parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000; + parameter dyn_rx3_pma_termination_cmd = 6'b000000; + parameter dyn_tx0_pma_main_en = 6'b000000; + parameter dyn_tx0_pma_main_sign = 1'b0; + parameter dyn_tx0_pma_margin_input = 9'b000000000; + parameter dyn_tx0_pma_margin_sel = 9'b000000000; + parameter dyn_tx0_pma_post_en = 5'b00000; + parameter dyn_tx0_pma_post_sel = 8'b00000000; + parameter dyn_tx0_pma_post_sign = 1'b0; + parameter dyn_tx0_pma_pre_en = 1'b0; + parameter dyn_tx0_pma_pre_sel = 4'b0000; + parameter dyn_tx0_pma_pre_sign = 1'b0; + parameter dyn_tx1_pma_main_en = 6'b000000; + parameter dyn_tx1_pma_main_sign = 1'b0; + parameter dyn_tx1_pma_margin_input = 9'b000000000; + parameter dyn_tx1_pma_margin_sel = 9'b000000000; + parameter dyn_tx1_pma_post_en = 5'b00000; + parameter dyn_tx1_pma_post_sel = 8'b00000000; + parameter dyn_tx1_pma_post_sign = 1'b0; + parameter dyn_tx1_pma_pre_en = 1'b0; + parameter dyn_tx1_pma_pre_sel = 4'b0000; + parameter dyn_tx1_pma_pre_sign = 1'b0; + parameter dyn_tx2_pma_main_en = 6'b000000; + parameter dyn_tx2_pma_main_sign = 1'b0; + parameter dyn_tx2_pma_margin_input = 9'b000000000; + parameter dyn_tx2_pma_margin_sel = 9'b000000000; + parameter dyn_tx2_pma_post_en = 5'b00000; + parameter dyn_tx2_pma_post_sel = 8'b00000000; + parameter dyn_tx2_pma_post_sign = 1'b0; + parameter dyn_tx2_pma_pre_en = 1'b0; + parameter dyn_tx2_pma_pre_sel = 4'b0000; + parameter dyn_tx2_pma_pre_sign = 1'b0; + parameter dyn_tx3_pma_main_en = 6'b000000; + parameter dyn_tx3_pma_main_sign = 1'b0; + parameter dyn_tx3_pma_margin_input = 9'b000000000; + parameter dyn_tx3_pma_margin_sel = 9'b000000000; + parameter dyn_tx3_pma_post_en = 5'b00000; + parameter dyn_tx3_pma_post_sel = 8'b00000000; + parameter dyn_tx3_pma_post_sign = 1'b0; + parameter dyn_tx3_pma_pre_en = 1'b0; + parameter dyn_tx3_pma_pre_sel = 4'b0000; + parameter dyn_tx3_pma_pre_sign = 1'b0; + parameter location = ""; + parameter main_clk_to_fabric_div_en = 1'b0; + parameter main_clk_to_fabric_div_mode = 1'b0; + parameter main_clk_to_fabric_sel = 1'b0; + parameter main_rclk_to_fabric_sel = 2'b00; + parameter main_use_only_usr_clock = 1'b0; + parameter pcs_ovs_en = 1'b0; + parameter pcs_ovs_mode = 1'b0; + parameter pcs_pll_lock_ppm = 3'b000; + parameter pcs_word_len = 2'b00; + parameter pll_pma_ckref_ext = 1'b0; + parameter pll_pma_cpump = 4'b0000; + parameter pll_pma_divl = 2'b00; + parameter pll_pma_divm = 1'b0; + parameter pll_pma_divn = 2'b00; + parameter pll_pma_gbx_en = 1'b0; + parameter pll_pma_int_data_len = 1'b0; + parameter pll_pma_lvds_en = 1'b0; + parameter pll_pma_lvds_mux = 1'b0; + parameter pll_pma_mux_ckref = 1'b0; + parameter rx_usrclk_use_pcs_clk_2 = 1'b0; + parameter test_mode = 2'b00; + parameter tx_usrclk_use_pcs_clk_2 = 1'b0; +endmodule + From 012f0e2952bec71cdf1182ac3393b3ac030ed23b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 09:26:19 +0100 Subject: [PATCH 026/342] memory blocks --- techlibs/nanoxplore/cells_bb.v | 384 ---------------- techlibs/nanoxplore/cells_bb_l.v | 59 +++ techlibs/nanoxplore/cells_bb_m.v | 59 +++ techlibs/nanoxplore/cells_bb_u.v | 102 +++++ techlibs/nanoxplore/cells_wrap_l.v | 193 +++++++++ techlibs/nanoxplore/cells_wrap_m.v | 191 ++++++++ techlibs/nanoxplore/cells_wrap_u.v | 674 +++++++++++++++++++++++++++++ 7 files changed, 1278 insertions(+), 384 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 6b46317af..a9d18edee 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -3324,349 +3324,6 @@ module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO); parameter outputContext = ""; endmodule -(* blackbox *) -module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 -, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 -, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); - output COR; - output ERR; - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I2; - input I3; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O2; - output O3; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RA1; - input RA2; - input RA3; - input RA4; - input RA5; - input RA6; - input RCK; - input RE; - input WA1; - input WA2; - input WA3; - input WA4; - input WA5; - input WA6; - input WCK; - input WE; - parameter addr_mask = 5'b00000; - parameter mem_ctxt = ""; - parameter rck_edge = 1'b0; - parameter wck_edge = 1'b0; - parameter we_mask = 1'b0; - parameter wea_mask = 1'b0; -endmodule - -(* blackbox *) -module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA); - input [17:0] I; - output [17:0] O; - input [4:0] RA; - input [4:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA); - input [17:0] I; - output [17:0] O; - input [4:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 -, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 -, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); - output COR; - output ERR; - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I2; - input I3; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O2; - output O3; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RA1; - input RA2; - input RA3; - input RA4; - input RA5; - input RA6; - input RCK; - input RE; - input WA1; - input WA2; - input WA3; - input WA4; - input WA5; - input WA6; - input WCK; - input WE; - parameter mem_ctxt = ""; - parameter mode = 0; - parameter rck_edge = 1'b0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); - output COR; - output ERR; - input [15:0] I; - output [15:0] O; - input [5:0] RA; - input RCK; - input RE; - input [5:0] WA; - input WCK; - input WE; - parameter mem_ctxt = ""; - parameter mode = 0; - parameter rck_edge = 1'b0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 -, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 -, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); - output COR; - output ERR; - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I2; - input I3; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O2; - output O3; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RA1; - input RA2; - input RA3; - input RA4; - input RA5; - input RA6; - input RCK; - input RE; - input WA1; - input WA2; - input WA3; - input WA4; - input WA5; - input WA6; - input WCK; - input WE; - parameter mem_ctxt = ""; - parameter rck_edge = 1'b0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 -, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 -, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 -, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1 -, WA2, WA3, WA4, WA5, WA6, WE, WEA); - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I17; - input I18; - input I19; - input I2; - input I20; - input I21; - input I22; - input I23; - input I24; - input I25; - input I26; - input I27; - input I28; - input I29; - input I3; - input I30; - input I31; - input I32; - input I33; - input I34; - input I35; - input I36; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O17; - output O18; - output O19; - output O2; - output O20; - output O21; - output O22; - output O23; - output O24; - output O25; - output O26; - output O27; - output O28; - output O29; - output O3; - output O30; - output O31; - output O32; - output O33; - output O34; - output O35; - output O36; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RA1; - input RA10; - input RA2; - input RA3; - input RA4; - input RA5; - input RA6; - input RA7; - input RA8; - input RA9; - input WA1; - input WA2; - input WA3; - input WA4; - input WA5; - input WA6; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter mode = 0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); - output COR; - output ERR; - input [15:0] I; - output [15:0] O; - input [5:0] RA; - input RCK; - input RE; - input [5:0] WA; - input WCK; - input WE; - parameter mem_ctxt = ""; - parameter rck_edge = 1'b0; - parameter wck_edge = 1'b0; -endmodule - (* blackbox *) module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); input DCK; @@ -3784,47 +3441,6 @@ module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, parameter wck_edge = 1'b0; endmodule -(* blackbox *) -module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); - output [17:0] AO; - input [4:0] ARA; - output [17:0] BO; - input [4:0] BRA; - input [17:0] I; - input [4:0] WA; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter wck_edge = 1'b0; -endmodule - -//(* blackbox *) -//module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); -// input [35:0] I; -// output [35:0] O; -// input [4:0] RA; -// input [4:0] WA; -// input WCK; -// input WE; -// input WEA; -// parameter mem_ctxt = ""; -// parameter wck_edge = 1'b0; -//endmodule -// -//(* blackbox *) -//module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); -// input [17:0] I; -// output [17:0] O; -// input [5:0] RA; -// input [5:0] WA; -// input WCK; -// input WE; -// input WEA; -// parameter mem_ctxt = ""; -// parameter wck_edge = 1'b0; -//endmodule - (* blackbox *) module SMACC24x18_1DSP(clk, rst, A, B, Z); input [23:0] A; diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index cae2a0f29..3ed9c1a89 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -1942,3 +1942,62 @@ module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, parameter rx_pma_half_step = 1'b0; endmodule +(* blackbox *) +module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index 620e9107d..b3e94ac15 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -1229,3 +1229,62 @@ module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, parameter sel_clkw_rx2 = 2'b00; endmodule +(* blackbox *) +module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 2bcaa5326..f828ebb3a 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -2349,3 +2349,105 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D parameter tx_usrclk_use_pcs_clk_2 = 1'b0; endmodule +(* blackbox *) +module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 +, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 +, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 +, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1 +, WA2, WA3, WA4, WA5, WA6, WE, WEA); + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I17; + input I18; + input I19; + input I2; + input I20; + input I21; + input I22; + input I23; + input I24; + input I25; + input I26; + input I27; + input I28; + input I29; + input I3; + input I30; + input I31; + input I32; + input I33; + input I34; + input I35; + input I36; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O17; + output O18; + output O19; + output O2; + output O20; + output O21; + output O22; + output O23; + output O24; + output O25; + output O26; + output O27; + output O28; + output O29; + output O3; + output O30; + output O31; + output O32; + output O33; + output O34; + output O35; + output O36; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA10; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RA7; + input RA8; + input RA9; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter wck_edge = 1'b0; +endmodule + diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index dc2e2a81c..57ad7e947 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -1207,3 +1207,196 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, ); endmodule +module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); + output COR; + output ERR; + input [15:0] I; + output [15:0] O; + input [5:0] RA; + input RCK; + input RE; + input [5:0] WA; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + + NX_RFB_L #( + .mode(mode), + .rck_edge(rck_edge), + .wck_edge(wck_edge), + .mem_ctxt(mem_ctxt) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .COR(COR), + .ERR(ERR), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .RA1(RA[0]), + .RA2(RA[1]), + .RA3(RA[2]), + .RA4(RA[3]), + .RA5(RA[4]), + .RA6(RA[5]), + .RE(RE), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(WA[5]), + .WE(WE) + ); +endmodule + +module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter addr_mask = 5'b00000; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + parameter we_mask = 1'b0; + parameter wea_mask = 1'b0; + + NX_RFB_L #( + .mode(0), + .mem_ctxt(mem_ctxt), + .rck_edge(rck_edge), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .I1(I1), + .I2(I2), + .I3(I3), + .I4(I4), + .I5(I5), + .I6(I6), + .I7(I7), + .I8(I8), + .I9(I9), + .I10(I10), + .I11(I11), + .I12(I12), + .I13(I13), + .I14(I14), + .I15(I15), + .I16(I16), + .COR(COR), + .ERR(ERR), + .O1(O1), + .O2(O2), + .O3(O3), + .O4(O4), + .O5(O5), + .O6(O6), + .O7(O7), + .O8(O8), + .O9(O9), + .O10(O10), + .O11(O11), + .O12(O12), + .O13(O13), + .O14(O14), + .O15(O15), + .O16(O16), + .RA1(RA1), + .RA2(RA2), + .RA3(RA3), + .RA4(RA4), + .RA5(RA5), + .RA6(RA6), + .RE(RE), + .WA1(WA1), + .WA2(WA2), + .WA3(WA3), + .WA4(WA4), + .WA5(WA5), + .WA6(WA6), + .WE(WE) + ); +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v index f66bc636e..190196e2f 100644 --- a/techlibs/nanoxplore/cells_wrap_m.v +++ b/techlibs/nanoxplore/cells_wrap_m.v @@ -845,3 +845,194 @@ module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, .Z56(Z[55]) ); endmodule + +module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA); + output COR; + output ERR; + input [15:0] I; + output [15:0] O; + input [5:0] RA; + input RCK; + input RE; + input [5:0] WA; + input WCK; + input WE; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + + NX_RFB_M #( + .mem_ctxt(mem_ctxt), + .rck_edge(rck_edge), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .COR(COR), + .ERR(ERR), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .RA1(RA[0]), + .RA2(RA[1]), + .RA3(RA[2]), + .RA4(RA[3]), + .RA5(RA[4]), + .RA6(RA[5]), + .RE(RE), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(WA[5]), + .WE(WE) + ); +endmodule + +module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter addr_mask = 5'b00000; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + parameter we_mask = 1'b0; + parameter wea_mask = 1'b0; + + NX_RFB_M #( + .mem_ctxt(mem_ctxt), + .rck_edge(rck_edge), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .I1(I1), + .I2(I2), + .I3(I3), + .I4(I4), + .I5(I5), + .I6(I6), + .I7(I7), + .I8(I8), + .I9(I9), + .I10(I10), + .I11(I11), + .I12(I12), + .I13(I13), + .I14(I14), + .I15(I15), + .I16(I16), + .COR(COR), + .ERR(ERR), + .O1(O1), + .O2(O2), + .O3(O3), + .O4(O4), + .O5(O5), + .O6(O6), + .O7(O7), + .O8(O8), + .O9(O9), + .O10(O10), + .O11(O11), + .O12(O12), + .O13(O13), + .O14(O14), + .O15(O15), + .O16(O16), + .RA1(RA1), + .RA2(RA2), + .RA3(RA3), + .RA4(RA4), + .RA5(RA5), + .RA6(RA6), + .RE(RE), + .WA1(WA1), + .WA2(WA2), + .WA3(WA3), + .WA4(WA4), + .WA5(WA5), + .WA6(WA6), + .WE(WE) + ); +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index be5561c3e..eda3565b3 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -1459,3 +1459,677 @@ module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, .VCO(VCO) ); endmodule + +module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA); + input [17:0] I; + output [17:0] O; + input [4:0] RA; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; + + NX_RFB_U #( + .mode(0), + .mem_ctxt(mem_ctxt), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .RA1(RA[0]), + .RA2(RA[1]), + .RA3(RA[2]), + .RA4(RA[3]), + .RA5(RA[4]), + .RA6(1'b0), + .RA7(1'b0), + .RA8(1'b0), + .RA9(1'b0), + .RA10(1'b0), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(1'b0), + .WE(WE), + .WEA(WEA) + ); + +endmodule + +module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA); + input [17:0] I; + output [17:0] O; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; + + NX_RFB_U #( + .mode(1), + .mem_ctxt(mem_ctxt), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .RA1(1'b0), + .RA2(1'b0), + .RA3(1'b0), + .RA4(1'b0), + .RA5(1'b0), + .RA6(1'b0), + .RA7(1'b0), + .RA8(1'b0), + .RA9(1'b0), + .RA10(1'b0), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(1'b0), + .WE(WE), + .WEA(WEA) + ); +endmodule + +module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); + input [17:0] I; + output [17:0] O; + input [5:0] RA; + input [5:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; + + NX_RFB_U #( + .mode(2), + .mem_ctxt(mem_ctxt), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .RA1(RA[0]), + .RA2(RA[1]), + .RA3(RA[2]), + .RA4(RA[3]), + .RA5(RA[4]), + .RA6(RA[5]), + .RA7(1'b0), + .RA8(1'b0), + .RA9(1'b0), + .RA10(1'b0), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(WA[5]), + .WE(WE), + .WEA(WEA) + ); +endmodule + +module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); + input [35:0] I; + output [35:0] O; + input [4:0] RA; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; + + NX_RFB_U #( + .mode(3), + .mem_ctxt(mem_ctxt), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(I[18]), + .I20(I[19]), + .I21(I[20]), + .I22(I[21]), + .I23(I[22]), + .I24(I[23]), + .I25(I[24]), + .I26(I[25]), + .I27(I[26]), + .I28(I[27]), + .I29(I[28]), + .I30(I[29]), + .I31(I[30]), + .I32(I[31]), + .I33(I[32]), + .I34(I[33]), + .I35(I[34]), + .I36(I[35]), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .O19(O[18]), + .O20(O[19]), + .O21(O[20]), + .O22(O[21]), + .O23(O[22]), + .O24(O[23]), + .O25(O[24]), + .O26(O[25]), + .O27(O[26]), + .O28(O[27]), + .O29(O[28]), + .O30(O[29]), + .O31(O[30]), + .O32(O[31]), + .O33(O[32]), + .O34(O[33]), + .O35(O[34]), + .O36(O[35]), + .RA1(RA[0]), + .RA2(RA[1]), + .RA3(RA[2]), + .RA4(RA[3]), + .RA5(RA[4]), + .RA6(1'b0), + .RA7(1'b0), + .RA8(1'b0), + .RA9(1'b0), + .RA10(1'b0), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(1'b0), + .WE(WE), + .WEA(WEA) + ); +endmodule + +module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); + output [17:0] AO; + input [4:0] ARA; + output [17:0] BO; + input [4:0] BRA; + input [17:0] I; + input [4:0] WA; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter wck_edge = 1'b0; + + NX_RFB_U #( + .mode(32'd4), + .mem_ctxt(mem_ctxt), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(AO[0]), + .O2(AO[1]), + .O3(AO[2]), + .O4(AO[3]), + .O5(AO[4]), + .O6(AO[5]), + .O7(AO[6]), + .O8(AO[7]), + .O9(AO[8]), + .O10(AO[9]), + .O11(AO[10]), + .O12(AO[11]), + .O13(AO[12]), + .O14(AO[13]), + .O15(AO[14]), + .O16(AO[15]), + .O17(AO[16]), + .O18(AO[17]), + .O19(BO[0]), + .O20(BO[1]), + .O21(BO[2]), + .O22(BO[3]), + .O23(BO[4]), + .O24(BO[5]), + .O25(BO[6]), + .O26(BO[7]), + .O27(BO[8]), + .O28(BO[9]), + .O29(BO[10]), + .O30(BO[11]), + .O31(BO[12]), + .O32(BO[13]), + .O33(BO[14]), + .O34(BO[15]), + .O35(BO[16]), + .O36(BO[17]), + .RA1(ARA[0]), + .RA2(ARA[1]), + .RA3(ARA[2]), + .RA4(ARA[3]), + .RA5(ARA[4]), + .RA6(BRA[0]), + .RA7(BRA[1]), + .RA8(BRA[2]), + .RA9(BRA[3]), + .RA10(BRA[4]), + .WA1(WA[0]), + .WA2(WA[1]), + .WA3(WA[2]), + .WA4(WA[3]), + .WA5(WA[4]), + .WA6(1'b0), + .WE(WE), + .WEA(WEA) + ); +endmodule + +module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1 +, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6 +, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE); + output COR; + output ERR; + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I2; + input I3; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O2; + output O3; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RCK; + input RE; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + parameter addr_mask = 5'b00000; + parameter mem_ctxt = ""; + parameter rck_edge = 1'b0; + parameter wck_edge = 1'b0; + parameter we_mask = 1'b0; + parameter wea_mask = 1'b0; + + wire [15:0] D; + wire [15:0] Q; + + NX_RFB_U #( + .mem_ctxt(mem_ctxt), + .mode(2), + .wck_edge(wck_edge) + ) _TECHMAP_REPLACE_ ( + .WCK(WCK), + .I1(I1), + .I2(I2), + .I3(I3), + .I4(I4), + .I5(I5), + .I6(I6), + .I7(I7), + .I8(I8), + .I9(I9), + .I10(I10), + .I11(I11), + .I12(I12), + .I13(I13), + .I14(I14), + .I15(I15), + .I16(I16), + .I17(1'b0), + .I18(1'b0), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(D[0]), + .O2(D[1]), + .O3(D[2]), + .O4(D[3]), + .O5(D[4]), + .O6(D[5]), + .O7(D[6]), + .O8(D[7]), + .O9(D[8]), + .O10(D[9]), + .O11(D[10]), + .O12(D[11]), + .O13(D[12]), + .O14(D[13]), + .O15(D[14]), + .O16(D[15]), + .RA1(RA1), + .RA2(RA2), + .RA3(RA3), + .RA4(RA4), + .RA5(RA5), + .RA6(RA6), + .RA7(1'b0), + .RA8(1'b0), + .RA9(1'b0), + .RA10(1'b0), + .WA1(WA1), + .WA2(WA2), + .WA3(WA3), + .WA4(WA4), + .WA5(WA5), + .WA6(WA6), + .WE(WE), + .WEA(1'b0) + ); + + genvar i; + generate for (i = 0; i < 16; i = i + 1) begin:q_reg + NX_DFF #( + .dff_edge(rck_edge), + .dff_init(1'b0), + .dff_load(1'b1) + ) out_reg_i ( + .CK(RCK), + .I(D[i]), + .L(RE), + .R(1'b0), + .O(Q[i]) + ); + end endgenerate; + assign O1=Q[0]; + assign O2=Q[1]; + assign O3=Q[2]; + assign O4=Q[3]; + assign O5=Q[4]; + assign O6=Q[5]; + assign O7=Q[6]; + assign O8=Q[7]; + assign O9=Q[8]; + assign O10=Q[9]; + assign O11=Q[10]; + assign O12=Q[11]; + assign O13=Q[12]; + assign O14=Q[13]; + assign O15=Q[14]; + assign O16=Q[15]; + + assign COR=1'b0; + assign ERR=1'b0; +endmodule From 8f42d6dacea3ea3fab5862ecb6ac77f33b28a90e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 09:48:16 +0100 Subject: [PATCH 027/342] fifo --- techlibs/nanoxplore/cells_bb.v | 198 --------------- techlibs/nanoxplore/cells_bb_u.v | 127 ++++++++++ techlibs/nanoxplore/cells_wrap_u.v | 386 +++++++++++++++++++++++++++++ 3 files changed, 513 insertions(+), 198 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index a9d18edee..e5207ad34 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -165,158 +165,6 @@ module NX_ECC(CKD, CHK, COR, ERR); output ERR; endmodule -(* blackbox *) -module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO); - input [17:0] I; - output [17:0] O; - input [5:0] RAI; - output [5:0] RAO; - input RCK; - output REQ; - input RRSTI; - output RRSTO; - input [5:0] WAI; - output [5:0] WAO; - input WCK; - input WE; - input WEA; - output WEQ; - input WRSTI; - output WRSTO; - parameter rck_edge = 1'b0; - parameter read_addr_inv = 6'b000000; - parameter use_read_arst = 1'b0; - parameter use_write_arst = 1'b0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17 -, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2 -, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23 -, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7 -, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2 -, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2); - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I17; - input I18; - input I19; - input I2; - input I20; - input I21; - input I22; - input I23; - input I24; - input I25; - input I26; - input I27; - input I28; - input I29; - input I3; - input I30; - input I31; - input I32; - input I33; - input I34; - input I35; - input I36; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O17; - output O18; - output O19; - output O2; - output O20; - output O21; - output O22; - output O23; - output O24; - output O25; - output O26; - output O27; - output O28; - output O29; - output O3; - output O30; - output O31; - output O32; - output O33; - output O34; - output O35; - output O36; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RAI1; - input RAI2; - input RAI3; - input RAI4; - input RAI5; - input RAI6; - input RAI7; - output RAO1; - output RAO2; - output RAO3; - output RAO4; - output RAO5; - output RAO6; - output RAO7; - input RCK; - output REQ1; - output REQ2; - input RRSTI; - output RRSTO; - input WAI1; - input WAI2; - input WAI3; - input WAI4; - input WAI5; - input WAI6; - input WAI7; - output WAO1; - output WAO2; - output WAO3; - output WAO4; - output WAO5; - output WAO6; - output WAO7; - input WCK; - input WE; - input WEA; - output WEQ1; - output WEQ2; - input WRSTI; - output WRSTO; - parameter mode = 0; - parameter rck_edge = 1'b0; - parameter read_addr_inv = 7'b0000000; - parameter use_read_arst = 1'b0; - parameter use_write_arst = 1'b0; - parameter wck_edge = 1'b0; -endmodule - (* blackbox *) module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o @@ -3395,52 +3243,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD parameter weakTermination = ""; endmodule -(* blackbox *) -module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO); - input [35:0] I; - output [35:0] O; - input [5:0] RAI; - output [5:0] RAO; - input RCK; - output REQ; - input RRSTI; - input [5:0] WAI; - output [5:0] WAO; - input WCK; - input WE; - input WEA; - output WEQ; - input WRSTI; - parameter rck_edge = 1'b0; - parameter read_addr_inv = 7'b0000000; - parameter use_read_arst = 1'b0; - parameter use_write_arst = 1'b0; - parameter wck_edge = 1'b0; -endmodule - -(* blackbox *) -module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO); - input [17:0] I; - output [17:0] O; - input [6:0] RAI; - output [6:0] RAO; - input RCK; - output [1:0] REQ; - input RRSTI; - input [6:0] WAI; - output [6:0] WAO; - input WCK; - input WE; - input WEA; - output [1:0] WEQ; - input WRSTI; - parameter rck_edge = 1'b0; - parameter read_addr_inv = 7'b0000000; - parameter use_read_arst = 1'b0; - parameter use_write_arst = 1'b0; - parameter wck_edge = 1'b0; -endmodule - (* blackbox *) module SMACC24x18_1DSP(clk, rst, A, B, Z); input [23:0] A; diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index f828ebb3a..598eb8d2c 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -2451,3 +2451,130 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 parameter wck_edge = 1'b0; endmodule + +(* blackbox *) +module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17 +, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2 +, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23 +, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7 +, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2 +, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2); + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I17; + input I18; + input I19; + input I2; + input I20; + input I21; + input I22; + input I23; + input I24; + input I25; + input I26; + input I27; + input I28; + input I29; + input I3; + input I30; + input I31; + input I32; + input I33; + input I34; + input I35; + input I36; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O17; + output O18; + output O19; + output O2; + output O20; + output O21; + output O22; + output O23; + output O24; + output O25; + output O26; + output O27; + output O28; + output O29; + output O3; + output O30; + output O31; + output O32; + output O33; + output O34; + output O35; + output O36; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RAI1; + input RAI2; + input RAI3; + input RAI4; + input RAI5; + input RAI6; + input RAI7; + output RAO1; + output RAO2; + output RAO3; + output RAO4; + output RAO5; + output RAO6; + output RAO7; + input RCK; + output REQ1; + output REQ2; + input RRSTI; + output RRSTO; + input WAI1; + input WAI2; + input WAI3; + input WAI4; + input WAI5; + input WAI6; + input WAI7; + output WAO1; + output WAO2; + output WAO3; + output WAO4; + output WAO5; + output WAO6; + output WAO7; + input WCK; + input WE; + input WEA; + output WEQ1; + output WEQ2; + input WRSTI; + output WRSTO; + parameter mode = 0; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index eda3565b3..3c9eba1aa 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -2133,3 +2133,389 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, assign COR=1'b0; assign ERR=1'b0; endmodule + +module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO); + input [17:0] I; + output [17:0] O; + input [5:0] RAI; + output [5:0] RAO; + input RCK; + output REQ; + input RRSTI; + output RRSTO; + input [5:0] WAI; + output [5:0] WAO; + input WCK; + input WE; + input WEA; + output WEQ; + input WRSTI; + output WRSTO; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 6'b000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; + + NX_FIFO_U #( + .mode(0), + .wck_edge(wck_edge), + .rck_edge(rck_edge), + .read_addr_inv(read_addr_inv), + .use_write_arst(use_write_arst), + .use_read_arst(use_read_arst) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .WE(WE), + .WEA(WEA), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .WRSTI(WRSTI), + .WAI1(WAI[0]), + .WAI2(WAI[1]), + .WAI3(WAI[2]), + .WAI4(WAI[3]), + .WAI5(WAI[4]), + .WAI6(WAI[5]), + .WAI7(1'b0), + .WRSTO(WRSTO), + .WAO1(WAO[0]), + .WAO2(WAO[1]), + .WAO3(WAO[2]), + .WAO4(WAO[3]), + .WAO5(WAO[4]), + .WAO6(WAO[5]), + .WEQ1(WEQ), + .RRSTI(RRSTI), + .RAI1(RAI[0]), + .RAI2(RAI[1]), + .RAI3(RAI[2]), + .RAI4(RAI[3]), + .RAI5(RAI[4]), + .RAI6(RAI[5]), + .RAI7(1'b0), + .RRSTO(RRSTO), + .RAO1(RAO[0]), + .RAO2(RAO[1]), + .RAO3(RAO[2]), + .RAO4(RAO[3]), + .RAO5(RAO[4]), + .RAO6(RAO[5]), + .REQ1(REQ) + ); +endmodule + +module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO); + input [17:0] I; + output [17:0] O; + input [6:0] RAI; + output [6:0] RAO; + input RCK; + output [1:0] REQ; + input RRSTI; + input [6:0] WAI; + output [6:0] WAO; + input WCK; + input WE; + input WEA; + output [1:0] WEQ; + input WRSTI; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; + + NX_FIFO_U #( + .mode(1), + .wck_edge(wck_edge), + .rck_edge(rck_edge), + .read_addr_inv(read_addr_inv), + .use_write_arst(use_write_arst), + .use_read_arst(use_read_arst) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .WE(WE), + .WEA(WEA), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(1'b0), + .I20(1'b0), + .I21(1'b0), + .I22(1'b0), + .I23(1'b0), + .I24(1'b0), + .I25(1'b0), + .I26(1'b0), + .I27(1'b0), + .I28(1'b0), + .I29(1'b0), + .I30(1'b0), + .I31(1'b0), + .I32(1'b0), + .I33(1'b0), + .I34(1'b0), + .I35(1'b0), + .I36(1'b0), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .WRSTI(WRSTI), + .WAI1(WAI[0]), + .WAI2(WAI[1]), + .WAI3(WAI[2]), + .WAI4(WAI[3]), + .WAI5(WAI[4]), + .WAI6(WAI[5]), + .WAI7(WAI[6]), + .WAO1(WAO[0]), + .WAO2(WAO[1]), + .WAO3(WAO[2]), + .WAO4(WAO[3]), + .WAO5(WAO[4]), + .WAO6(WAO[5]), + .WAO7(WAO[6]), + .WEQ1(WEQ[0]), + .WEQ2(WEQ[1]), + .RRSTI(RRSTI), + .RAI1(RAI[0]), + .RAI2(RAI[1]), + .RAI3(RAI[2]), + .RAI4(RAI[3]), + .RAI5(RAI[4]), + .RAI6(RAI[5]), + .RAI7(RAI[6]), + .RAO1(RAO[0]), + .RAO2(RAO[1]), + .RAO3(RAO[2]), + .RAO4(RAO[3]), + .RAO5(RAO[4]), + .RAO6(RAO[5]), + .RAO7(RAO[6]), + .REQ1(REQ[0]), + .REQ2(REQ[1]) + ); +endmodule + +module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO); + input [35:0] I; + output [35:0] O; + input [5:0] RAI; + output [5:0] RAO; + input RCK; + output REQ; + input RRSTI; + input [5:0] WAI; + output [5:0] WAO; + input WCK; + input WE; + input WEA; + output WEQ; + input WRSTI; + parameter rck_edge = 1'b0; + parameter read_addr_inv = 7'b0000000; + parameter use_read_arst = 1'b0; + parameter use_write_arst = 1'b0; + parameter wck_edge = 1'b0; + + NX_FIFO_U #( + .mode(2), + .wck_edge(wck_edge), + .rck_edge(rck_edge), + .read_addr_inv(read_addr_inv), + .use_write_arst(use_write_arst), + .use_read_arst(use_read_arst) + ) _TECHMAP_REPLACE_ ( + .RCK(RCK), + .WCK(WCK), + .WE(WE), + .WEA(WEA), + .I1(I[0]), + .I2(I[1]), + .I3(I[2]), + .I4(I[3]), + .I5(I[4]), + .I6(I[5]), + .I7(I[6]), + .I8(I[7]), + .I9(I[8]), + .I10(I[9]), + .I11(I[10]), + .I12(I[11]), + .I13(I[12]), + .I14(I[13]), + .I15(I[14]), + .I16(I[15]), + .I17(I[16]), + .I18(I[17]), + .I19(I[18]), + .I20(I[19]), + .I21(I[20]), + .I22(I[21]), + .I23(I[22]), + .I24(I[23]), + .I25(I[24]), + .I26(I[25]), + .I27(I[26]), + .I28(I[27]), + .I29(I[28]), + .I30(I[29]), + .I31(I[30]), + .I32(I[31]), + .I33(I[32]), + .I34(I[33]), + .I35(I[34]), + .I36(I[35]), + .O1(O[0]), + .O2(O[1]), + .O3(O[2]), + .O4(O[3]), + .O5(O[4]), + .O6(O[5]), + .O7(O[6]), + .O8(O[7]), + .O9(O[8]), + .O10(O[9]), + .O11(O[10]), + .O12(O[11]), + .O13(O[12]), + .O14(O[13]), + .O15(O[14]), + .O16(O[15]), + .O17(O[16]), + .O18(O[17]), + .O19(O[18]), + .O20(O[19]), + .O21(O[20]), + .O22(O[21]), + .O23(O[22]), + .O24(O[23]), + .O25(O[24]), + .O26(O[25]), + .O27(O[26]), + .O28(O[27]), + .O29(O[28]), + .O30(O[29]), + .O31(O[30]), + .O32(O[31]), + .O33(O[32]), + .O34(O[33]), + .O35(O[34]), + .O36(O[35]), + .WRSTI(WRSTI), + .WAI1(WAI[0]), + .WAI2(WAI[1]), + .WAI3(WAI[2]), + .WAI4(WAI[3]), + .WAI5(WAI[4]), + .WAI6(WAI[5]), + .WAI7(1'b0), + .WAO1(WAO[0]), + .WAO2(WAO[1]), + .WAO3(WAO[2]), + .WAO4(WAO[3]), + .WAO5(WAO[4]), + .WAO6(WAO[5]), + .WEQ1(WEQ), + .RRSTI(RRSTI), + .RAI1(RAI[0]), + .RAI2(RAI[1]), + .RAI3(RAI[2]), + .RAI4(RAI[3]), + .RAI5(RAI[4]), + .RAI6(RAI[5]), + .RAI7(1'b0), + .RAO1(RAO[0]), + .RAO2(RAO[1]), + .RAO3(RAO[2]), + .RAO4(RAO[3]), + .RAO5(RAO[4]), + .RAO6(RAO[5]), + .REQ1(REQ) + ); +endmodule \ No newline at end of file From f836de6bccd250ff0183dec521523c1a0c9bc4a2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 10:07:54 +0100 Subject: [PATCH 028/342] mark DSPs as TODOs for now --- techlibs/nanoxplore/cells_bb.v | 195 ----------------------------- techlibs/nanoxplore/cells_wrap_l.v | 13 +- techlibs/nanoxplore/cells_wrap_u.v | 187 ++++++++++++++++++++++++++- 3 files changed, 198 insertions(+), 197 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index e5207ad34..2b79cc472 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -1,50 +1,3 @@ -(* blackbox *) -module ACC84_2DSP(clk, rst, X, Z); - input [83:0] X; - output [84:0] Z; - input clk; - input rst; - parameter g_pipe = 2; -endmodule - -(* blackbox *) -module ACC92_2DSP(clk, rst, X, Z); - input [55:0] X; - output [91:0] Z; - input clk; - input rst; - parameter g_pipe = 2; -endmodule - -(* blackbox *) -module ACC98_2DSP(clk, rst, X, Z); - input [55:0] X; - output [97:0] Z; - input clk; - input rst; - parameter g_pipe = 2; -endmodule - -(* blackbox *) -module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z); - input [41:0] X; - input [41:0] Y; - output [84:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module ADD84_2DSP(clk, rst, X, Y, Z); - input [83:0] X; - input [83:0] Y; - output [84:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - (* blackbox *) module NX_BD(I, O); input I; @@ -3242,151 +3195,3 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD parameter turbo = ""; parameter weakTermination = ""; endmodule - -(* blackbox *) -module SMACC24x18_1DSP(clk, rst, A, B, Z); - input [23:0] A; - input [17:0] B; - output [55:0] Z; - input clk; - input rst; - parameter g_pipe = 1; -endmodule - -(* blackbox *) -module SMACC24x32_2DSP(clk, rst, A, B, Z); - input [23:0] A; - input [31:0] B; - output [55:0] Z; - input clk; - input rst; - parameter g_pipe = 1; -endmodule - -(* blackbox *) -module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z); - input [23:0] A; - input [31:0] B; - output [55:0] Z; - input clk; - input rst; - input we; - parameter STAGE_1 = "false"; - parameter STAGE_2 = "false"; - parameter STAGE_3 = "false"; - parameter STAGE_4 = "false"; -endmodule - -(* blackbox *) -module SMUL24x32_2DSP(clk, rst, A, B, Z); - input [23:0] A; - input [31:0] B; - output [54:0] Z; - input clk; - input rst; - parameter g_pipe = 1; -endmodule - -(* blackbox *) -module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z); - input [23:0] A; - input [31:0] B; - output [97:0] Z; - input clk; - input rst; - input we; - parameter STAGE_1 = "false"; - parameter STAGE_2 = "false"; - parameter STAGE_3 = "false"; -endmodule - -(* blackbox *) -module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z); - input [23:0] A; - input [31:0] B; - output [91:0] Z; - input clk; - input rst; - input we; -endmodule - -(* blackbox *) -module SMUL47x35_4DSP(clk, rst, A, B, Z); - input [46:0] A; - input [34:0] B; - output [80:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMADD24_2DSP(clk, rst, A, B, C, Z); - input [23:0] A; - input [31:0] B; - input [55:0] C; - output [55:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z); - input [23:0] A; - input [15:0] B; - output [55:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL24x32_2DSP(clk, rst, A, B, Z); - input [23:0] A; - input [31:0] B; - output [55:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z); - input [23:0] A; - input [17:0] B; - output [59:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL24x36_2DSP(clk, rst, A, B, Z); - input [23:0] A; - input [35:0] B; - output [59:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z); - input [23:0] A; - input [17:0] B; - output [83:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule - -(* blackbox *) -module UMUL48x36_4DSP(clk, rst, A, B, Z); - input [47:0] A; - input [35:0] B; - output [83:0] Z; - input clk; - input rst; - parameter piped = "true"; -endmodule diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index 57ad7e947..24430052f 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -1399,4 +1399,15 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .WA6(WA6), .WE(WE) ); -endmodule \ No newline at end of file +endmodule + +// TODO +module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [91:0] Z; + input clk; + input rst; + input we; +endmodule + diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index 3c9eba1aa..b07c9e46b 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -2518,4 +2518,189 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, .RAO6(RAO[5]), .REQ1(REQ) ); -endmodule \ No newline at end of file +endmodule + +//TODO +module ACC84_2DSP(clk, rst, X, Z); + input [83:0] X; + output [84:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +//TODO +module ACC92_2DSP(clk, rst, X, Z); + input [55:0] X; + output [91:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +//TODO +module ACC98_2DSP(clk, rst, X, Z); + input [55:0] X; + output [97:0] Z; + input clk; + input rst; + parameter g_pipe = 2; +endmodule + +//TODO +module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z); + input [41:0] X; + input [41:0] Y; + output [84:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module ADD84_2DSP(clk, rst, X, Y, Z); + input [83:0] X; + input [83:0] Y; + output [84:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module SMACC24x18_1DSP(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [55:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +//TODO +module SMACC24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +//TODO +module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + input we; + parameter STAGE_1 = "false"; + parameter STAGE_2 = "false"; + parameter STAGE_3 = "false"; + parameter STAGE_4 = "false"; +endmodule + +//TODO +module SMUL24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [54:0] Z; + input clk; + input rst; + parameter g_pipe = 1; +endmodule + +//TODO +module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z); + input [23:0] A; + input [31:0] B; + output [97:0] Z; + input clk; + input rst; + input we; + parameter STAGE_1 = "false"; + parameter STAGE_2 = "false"; + parameter STAGE_3 = "false"; +endmodule + +//TODO +module SMUL47x35_4DSP(clk, rst, A, B, Z); + input [46:0] A; + input [34:0] B; + output [80:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMADD24_2DSP(clk, rst, A, B, C, Z); + input [23:0] A; + input [31:0] B; + input [55:0] C; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [15:0] B; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL24x32_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [31:0] B; + output [55:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [59:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL24x36_2DSP(clk, rst, A, B, Z); + input [23:0] A; + input [35:0] B; + output [59:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z); + input [23:0] A; + input [17:0] B; + output [83:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule + +//TODO +module UMUL48x36_4DSP(clk, rst, A, B, Z); + input [47:0] A; + input [35:0] B; + output [83:0] Z; + input clk; + input rst; + parameter piped = "true"; +endmodule From ef15325dce40a79d7317bb6b299306e724a74ef2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 10:08:18 +0100 Subject: [PATCH 029/342] removed virtual primitive --- techlibs/nanoxplore/cells_bb.v | 837 --------------------------------- 1 file changed, 837 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 2b79cc472..b040ece78 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -2288,843 +2288,6 @@ module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS parameter std_mode = ""; endmodule -(* blackbox *) -module NX_RB(CK1, CK2, CK3, CK4, EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EI9, EI10, EI11, EI12, EI13, EI14, EI15, EI16, EI17 -, EI18, EI19, EI20, EI21, EI22, EI23, EI24, EI25, EI26, EI27, EI28, EI29, EI30, EI31, EI32, EI33, EI34, EI35, EI36, EI37, EI38 -, EI39, EI40, EI41, EI42, EI43, EI44, EI45, EI46, EI47, EI48, EI49, EI50, EI51, EI52, EI53, EI54, EI55, EI56, EI57, EI58, EI59 -, EI60, EI61, EI62, EI63, EI64, EI65, EI66, EI67, EI68, EI69, EI70, EI71, EI72, EI73, EI74, EI75, EI76, EI77, EI78, EI79, EI80 -, EI81, EI82, EI83, EI84, EI85, EI86, EI87, EI88, EI89, EI90, EI91, EI92, EI93, EI94, EI95, EI96, EI97, EI98, EI99, EI100, EI101 -, EI102, EI103, EI104, EI105, EI106, EI107, EI108, EI109, EI110, EI111, EI112, EI113, EI114, EI115, EI116, EI117, EI118, EI119, EI120, EI121, EI122 -, EI123, EI124, EI125, EI126, EI127, EI128, EI129, EI130, EI131, EI132, EI133, EI134, EI135, EI136, EI137, EI138, EI139, EI140, EI141, EI142, EI143 -, EI144, EI145, EI146, EI147, EI148, EI149, EI150, EI151, EI152, EI153, EI154, EI155, EI156, EI157, EI158, EI159, EI160, EI161, EI162, EI163, EI164 -, EI165, EI166, EI167, EI168, EI169, EI170, EI171, EI172, EI173, EI174, EI175, EI176, EI177, EI178, EI179, EI180, EI181, EI182, EI183, EI184, EI185 -, EI186, EI187, EI188, EI189, EI190, EI191, EI192, EI_CK, EO_CK, EO1, EO2, EO3, EO4, EO5, EO6, EO7, EO8, EO9, EO10, EO11, EO12 -, EO13, EO14, EO15, EO16, EO17, EO18, EO19, EO20, EO21, EO22, EO23, EO24, EO25, EO26, EO27, EO28, EO29, EO30, EO31, EO32, EO33 -, EO34, EO35, EO36, EO37, EO38, EO39, EO40, EO41, EO42, EO43, EO44, EO45, EO46, EO47, EO48, EO49, EO50, EO51, EO52, EO53, EO54 -, EO55, EO56, EO57, EO58, EO59, EO60, EO61, EO62, EO63, EO64, EO65, EO66, EO67, EO68, EO69, EO70, EO71, EO72, EO73, EO74, EO75 -, EO76, EO77, EO78, EO79, EO80, EO81, EO82, EO83, EO84, EO85, EO86, EO87, EO88, EO89, EO90, EO91, EO92, EO93, EO94, EO95, EO96 -, EO97, EO98, EO99, EO100, EO101, EO102, EO103, EO104, EO105, EO106, EO107, EO108, EO109, EO110, EO111, EO112, EO113, EO114, EO115, EO116, EO117 -, EO118, EO119, EO120, EO121, EO122, EO123, EO124, EO125, EO126, EO127, EO128, EO129, EO130, EO131, EO132, EO133, EO134, EO135, EO136, EO137, EO138 -, EO139, EO140, EO141, EO142, EO143, EO144, EO145, EO146, EO147, EO148, EO149, EO150, EO151, EO152, EO153, EO154, EO155, EO156, EO157, EO158, EO159 -, EO160, EO161, EO162, EO163, EO164, EO165, EO166, EO167, EO168, EO169, EO170, EO171, EO172, EO173, EO174, EO175, EO176, EO177, EO178, EO179, EO180 -, EO181, EO182, EO183, EO184, EO185, EO186, EO187, EO188, EO189, EO190, EO191, EO192, FI1, FI2, FI3, FI4, FI5, FI6, FI7, FI8, FI9 -, FI10, FI11, FI12, FI13, FI14, FI15, FI16, FI17, FI18, FI19, FI20, FI21, FI22, FI23, FI24, FI25, FI26, FI27, FI28, FI29, FI30 -, FI31, FI32, FI33, FI34, FI35, FI36, FI37, FI38, FI39, FI40, FI41, FI42, FI43, FI44, FI45, FI46, FI47, FI48, FI49, FI50, FI51 -, FI52, FI53, FI54, FI55, FI56, FI57, FI58, FI59, FI60, FI61, FI62, FI63, FI64, FI65, FI66, FI67, FI68, FI69, FI70, FI71, FI72 -, FI73, FI74, FI75, FI76, FI77, FI78, FI79, FI80, FI81, FI82, FI83, FI84, FI85, FI86, FI87, FI88, FI89, FI90, FI91, FI92, FI93 -, FI94, FI95, FI96, FI97, FI98, FI99, FI100, FI101, FI102, FI103, FI104, FI105, FI106, FI107, FI108, FI109, FI110, FI111, FI112, FI113, FI114 -, FI115, FI116, FI117, FI118, FI119, FI120, FI121, FI122, FI123, FI124, FI125, FI126, FI127, FI128, FI129, FI130, FI131, FI132, FI133, FI134, FI135 -, FI136, FI137, FI138, FI139, FI140, FI141, FI142, FI143, FI144, FI145, FI146, FI147, FI148, FI149, FI150, FI151, FI152, FI153, FI154, FI155, FI156 -, FI157, FI158, FI159, FI160, FI161, FI162, FI163, FI164, FI165, FI166, FI167, FI168, FI169, FI170, FI171, FI172, FI173, FI174, FI175, FI176, FI177 -, FI178, FI179, FI180, FI181, FI182, FI183, FI184, FI185, FI186, FI187, FI188, FI189, FI190, FI191, FI192, FO1, FO2, FO3, FO4, FO5, FO6 -, FO7, FO8, FO9, FO10, FO11, FO12, FO13, FO14, FO15, FO16, FO17, FO18, FO19, FO20, FO21, FO22, FO23, FO24, FO25, FO26, FO27 -, FO28, FO29, FO30, FO31, FO32, FO33, FO34, FO35, FO36, FO37, FO38, FO39, FO40, FO41, FO42, FO43, FO44, FO45, FO46, FO47, FO48 -, FO49, FO50, FO51, FO52, FO53, FO54, FO55, FO56, FO57, FO58, FO59, FO60, FO61, FO62, FO63, FO64, FO65, FO66, FO67, FO68, FO69 -, FO70, FO71, FO72, FO73, FO74, FO75, FO76, FO77, FO78, FO79, FO80, FO81, FO82, FO83, FO84, FO85, FO86, FO87, FO88, FO89, FO90 -, FO91, FO92, FO93, FO94, FO95, FO96, FO97, FO98, FO99, FO100, FO101, FO102, FO103, FO104, FO105, FO106, FO107, FO108, FO109, FO110, FO111 -, FO112, FO113, FO114, FO115, FO116, FO117, FO118, FO119, FO120, FO121, FO122, FO123, FO124, FO125, FO126, FO127, FO128, FO129, FO130, FO131, FO132 -, FO133, FO134, FO135, FO136, FO137, FO138, FO139, FO140, FO141, FO142, FO143, FO144, FO145, FO146, FO147, FO148, FO149, FO150, FO151, FO152, FO153 -, FO154, FO155, FO156, FO157, FO158, FO159, FO160, FO161, FO162, FO163, FO164, FO165, FO166, FO167, FO168, FO169, FO170, FO171, FO172, FO173, FO174 -, FO175, FO176, FO177, FO178, FO179, FO180, FO181, FO182, FO183, FO184, FO185, FO186, FO187, FO188, FO189, FO190, FO191, FO192); - input CK1; - input CK2; - input CK3; - input CK4; - input EI1; - input EI10; - input EI100; - input EI101; - input EI102; - input EI103; - input EI104; - input EI105; - input EI106; - input EI107; - input EI108; - input EI109; - input EI11; - input EI110; - input EI111; - input EI112; - input EI113; - input EI114; - input EI115; - input EI116; - input EI117; - input EI118; - input EI119; - input EI12; - input EI120; - input EI121; - input EI122; - input EI123; - input EI124; - input EI125; - input EI126; - input EI127; - input EI128; - input EI129; - input EI13; - input EI130; - input EI131; - input EI132; - input EI133; - input EI134; - input EI135; - input EI136; - input EI137; - input EI138; - input EI139; - input EI14; - input EI140; - input EI141; - input EI142; - input EI143; - input EI144; - input EI145; - input EI146; - input EI147; - input EI148; - input EI149; - input EI15; - input EI150; - input EI151; - input EI152; - input EI153; - input EI154; - input EI155; - input EI156; - input EI157; - input EI158; - input EI159; - input EI16; - input EI160; - input EI161; - input EI162; - input EI163; - input EI164; - input EI165; - input EI166; - input EI167; - input EI168; - input EI169; - input EI17; - input EI170; - input EI171; - input EI172; - input EI173; - input EI174; - input EI175; - input EI176; - input EI177; - input EI178; - input EI179; - input EI18; - input EI180; - input EI181; - input EI182; - input EI183; - input EI184; - input EI185; - input EI186; - input EI187; - input EI188; - input EI189; - input EI19; - input EI190; - input EI191; - input EI192; - input EI2; - input EI20; - input EI21; - input EI22; - input EI23; - input EI24; - input EI25; - input EI26; - input EI27; - input EI28; - input EI29; - input EI3; - input EI30; - input EI31; - input EI32; - input EI33; - input EI34; - input EI35; - input EI36; - input EI37; - input EI38; - input EI39; - input EI4; - input EI40; - input EI41; - input EI42; - input EI43; - input EI44; - input EI45; - input EI46; - input EI47; - input EI48; - input EI49; - input EI5; - input EI50; - input EI51; - input EI52; - input EI53; - input EI54; - input EI55; - input EI56; - input EI57; - input EI58; - input EI59; - input EI6; - input EI60; - input EI61; - input EI62; - input EI63; - input EI64; - input EI65; - input EI66; - input EI67; - input EI68; - input EI69; - input EI7; - input EI70; - input EI71; - input EI72; - input EI73; - input EI74; - input EI75; - input EI76; - input EI77; - input EI78; - input EI79; - input EI8; - input EI80; - input EI81; - input EI82; - input EI83; - input EI84; - input EI85; - input EI86; - input EI87; - input EI88; - input EI89; - input EI9; - input EI90; - input EI91; - input EI92; - input EI93; - input EI94; - input EI95; - input EI96; - input EI97; - input EI98; - input EI99; - output EI_CK; - output EO1; - output EO10; - output EO100; - output EO101; - output EO102; - output EO103; - output EO104; - output EO105; - output EO106; - output EO107; - output EO108; - output EO109; - output EO11; - output EO110; - output EO111; - output EO112; - output EO113; - output EO114; - output EO115; - output EO116; - output EO117; - output EO118; - output EO119; - output EO12; - output EO120; - output EO121; - output EO122; - output EO123; - output EO124; - output EO125; - output EO126; - output EO127; - output EO128; - output EO129; - output EO13; - output EO130; - output EO131; - output EO132; - output EO133; - output EO134; - output EO135; - output EO136; - output EO137; - output EO138; - output EO139; - output EO14; - output EO140; - output EO141; - output EO142; - output EO143; - output EO144; - output EO145; - output EO146; - output EO147; - output EO148; - output EO149; - output EO15; - output EO150; - output EO151; - output EO152; - output EO153; - output EO154; - output EO155; - output EO156; - output EO157; - output EO158; - output EO159; - output EO16; - output EO160; - output EO161; - output EO162; - output EO163; - output EO164; - output EO165; - output EO166; - output EO167; - output EO168; - output EO169; - output EO17; - output EO170; - output EO171; - output EO172; - output EO173; - output EO174; - output EO175; - output EO176; - output EO177; - output EO178; - output EO179; - output EO18; - output EO180; - output EO181; - output EO182; - output EO183; - output EO184; - output EO185; - output EO186; - output EO187; - output EO188; - output EO189; - output EO19; - output EO190; - output EO191; - output EO192; - output EO2; - output EO20; - output EO21; - output EO22; - output EO23; - output EO24; - output EO25; - output EO26; - output EO27; - output EO28; - output EO29; - output EO3; - output EO30; - output EO31; - output EO32; - output EO33; - output EO34; - output EO35; - output EO36; - output EO37; - output EO38; - output EO39; - output EO4; - output EO40; - output EO41; - output EO42; - output EO43; - output EO44; - output EO45; - output EO46; - output EO47; - output EO48; - output EO49; - output EO5; - output EO50; - output EO51; - output EO52; - output EO53; - output EO54; - output EO55; - output EO56; - output EO57; - output EO58; - output EO59; - output EO6; - output EO60; - output EO61; - output EO62; - output EO63; - output EO64; - output EO65; - output EO66; - output EO67; - output EO68; - output EO69; - output EO7; - output EO70; - output EO71; - output EO72; - output EO73; - output EO74; - output EO75; - output EO76; - output EO77; - output EO78; - output EO79; - output EO8; - output EO80; - output EO81; - output EO82; - output EO83; - output EO84; - output EO85; - output EO86; - output EO87; - output EO88; - output EO89; - output EO9; - output EO90; - output EO91; - output EO92; - output EO93; - output EO94; - output EO95; - output EO96; - output EO97; - output EO98; - output EO99; - output EO_CK; - input FI1; - input FI10; - input FI100; - input FI101; - input FI102; - input FI103; - input FI104; - input FI105; - input FI106; - input FI107; - input FI108; - input FI109; - input FI11; - input FI110; - input FI111; - input FI112; - input FI113; - input FI114; - input FI115; - input FI116; - input FI117; - input FI118; - input FI119; - input FI12; - input FI120; - input FI121; - input FI122; - input FI123; - input FI124; - input FI125; - input FI126; - input FI127; - input FI128; - input FI129; - input FI13; - input FI130; - input FI131; - input FI132; - input FI133; - input FI134; - input FI135; - input FI136; - input FI137; - input FI138; - input FI139; - input FI14; - input FI140; - input FI141; - input FI142; - input FI143; - input FI144; - input FI145; - input FI146; - input FI147; - input FI148; - input FI149; - input FI15; - input FI150; - input FI151; - input FI152; - input FI153; - input FI154; - input FI155; - input FI156; - input FI157; - input FI158; - input FI159; - input FI16; - input FI160; - input FI161; - input FI162; - input FI163; - input FI164; - input FI165; - input FI166; - input FI167; - input FI168; - input FI169; - input FI17; - input FI170; - input FI171; - input FI172; - input FI173; - input FI174; - input FI175; - input FI176; - input FI177; - input FI178; - input FI179; - input FI18; - input FI180; - input FI181; - input FI182; - input FI183; - input FI184; - input FI185; - input FI186; - input FI187; - input FI188; - input FI189; - input FI19; - input FI190; - input FI191; - input FI192; - input FI2; - input FI20; - input FI21; - input FI22; - input FI23; - input FI24; - input FI25; - input FI26; - input FI27; - input FI28; - input FI29; - input FI3; - input FI30; - input FI31; - input FI32; - input FI33; - input FI34; - input FI35; - input FI36; - input FI37; - input FI38; - input FI39; - input FI4; - input FI40; - input FI41; - input FI42; - input FI43; - input FI44; - input FI45; - input FI46; - input FI47; - input FI48; - input FI49; - input FI5; - input FI50; - input FI51; - input FI52; - input FI53; - input FI54; - input FI55; - input FI56; - input FI57; - input FI58; - input FI59; - input FI6; - input FI60; - input FI61; - input FI62; - input FI63; - input FI64; - input FI65; - input FI66; - input FI67; - input FI68; - input FI69; - input FI7; - input FI70; - input FI71; - input FI72; - input FI73; - input FI74; - input FI75; - input FI76; - input FI77; - input FI78; - input FI79; - input FI8; - input FI80; - input FI81; - input FI82; - input FI83; - input FI84; - input FI85; - input FI86; - input FI87; - input FI88; - input FI89; - input FI9; - input FI90; - input FI91; - input FI92; - input FI93; - input FI94; - input FI95; - input FI96; - input FI97; - input FI98; - input FI99; - output FO1; - output FO10; - output FO100; - output FO101; - output FO102; - output FO103; - output FO104; - output FO105; - output FO106; - output FO107; - output FO108; - output FO109; - output FO11; - output FO110; - output FO111; - output FO112; - output FO113; - output FO114; - output FO115; - output FO116; - output FO117; - output FO118; - output FO119; - output FO12; - output FO120; - output FO121; - output FO122; - output FO123; - output FO124; - output FO125; - output FO126; - output FO127; - output FO128; - output FO129; - output FO13; - output FO130; - output FO131; - output FO132; - output FO133; - output FO134; - output FO135; - output FO136; - output FO137; - output FO138; - output FO139; - output FO14; - output FO140; - output FO141; - output FO142; - output FO143; - output FO144; - output FO145; - output FO146; - output FO147; - output FO148; - output FO149; - output FO15; - output FO150; - output FO151; - output FO152; - output FO153; - output FO154; - output FO155; - output FO156; - output FO157; - output FO158; - output FO159; - output FO16; - output FO160; - output FO161; - output FO162; - output FO163; - output FO164; - output FO165; - output FO166; - output FO167; - output FO168; - output FO169; - output FO17; - output FO170; - output FO171; - output FO172; - output FO173; - output FO174; - output FO175; - output FO176; - output FO177; - output FO178; - output FO179; - output FO18; - output FO180; - output FO181; - output FO182; - output FO183; - output FO184; - output FO185; - output FO186; - output FO187; - output FO188; - output FO189; - output FO19; - output FO190; - output FO191; - output FO192; - output FO2; - output FO20; - output FO21; - output FO22; - output FO23; - output FO24; - output FO25; - output FO26; - output FO27; - output FO28; - output FO29; - output FO3; - output FO30; - output FO31; - output FO32; - output FO33; - output FO34; - output FO35; - output FO36; - output FO37; - output FO38; - output FO39; - output FO4; - output FO40; - output FO41; - output FO42; - output FO43; - output FO44; - output FO45; - output FO46; - output FO47; - output FO48; - output FO49; - output FO5; - output FO50; - output FO51; - output FO52; - output FO53; - output FO54; - output FO55; - output FO56; - output FO57; - output FO58; - output FO59; - output FO6; - output FO60; - output FO61; - output FO62; - output FO63; - output FO64; - output FO65; - output FO66; - output FO67; - output FO68; - output FO69; - output FO7; - output FO70; - output FO71; - output FO72; - output FO73; - output FO74; - output FO75; - output FO76; - output FO77; - output FO78; - output FO79; - output FO8; - output FO80; - output FO81; - output FO82; - output FO83; - output FO84; - output FO85; - output FO86; - output FO87; - output FO88; - output FO89; - output FO9; - output FO90; - output FO91; - output FO92; - output FO93; - output FO94; - output FO95; - output FO96; - output FO97; - output FO98; - output FO99; - parameter inputBypass = 24'b000000000000000000000000; - parameter inputClk = 2'b00; - parameter inputContext = ""; - parameter outputBypass = 24'b000000000000000000000000; - parameter outputClk = 2'b00; - parameter outputContext = ""; -endmodule - -(* blackbox *) -module NX_RB_WRAP(EI_CK, EO_CK, CK, EO, EI, FI, FO); - input [3:0] CK; - input [191:0] EI; - output EI_CK; - output [191:0] EO; - output EO_CK; - input [191:0] FI; - output [191:0] FO; - parameter inputBypass = 24'b000000000000000000000000; - parameter inputClk = 2'b00; - parameter inputContext = ""; - parameter outputBypass = 24'b000000000000000000000000; - parameter outputClk = 2'b00; - parameter outputContext = ""; -endmodule - (* blackbox *) module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); input DCK; From 71f0984dc9874d7d0b298e58fcc92d3932f226d0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 10:16:09 +0100 Subject: [PATCH 030/342] fixes --- techlibs/nanoxplore/cells_wrap_l.v | 4 ++-- techlibs/nanoxplore/cells_wrap_m.v | 4 ++-- techlibs/nanoxplore/cells_wrap_u.v | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index 24430052f..d86b4518b 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -1007,8 +1007,8 @@ module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, .CI(CI), .CK(CK), .CO(CO), - .CO37(CO36), - .CO57(CO56), + .CO37(CO37), + .CO57(CO57), .CZI1(CZI[0]), .CZI2(CZI[1]), diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v index 190196e2f..0bf3a9050 100644 --- a/techlibs/nanoxplore/cells_wrap_m.v +++ b/techlibs/nanoxplore/cells_wrap_m.v @@ -646,8 +646,8 @@ module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, .CI(CI), .CK(CK), .CO(CO), - .CO37(CO36), - .CO49(CO48), + .CO37(CO37), + .CO49(CO49), .CZI1(CZI[0]), .CZI2(CZI[1]), diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index b07c9e46b..f5623dfeb 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -1149,8 +1149,8 @@ module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, .CCO(CCO), .CI(CI), .CK(CK), - .CO43(CO42), - .CO57(CO56), + .CO43(CO43), + .CO57(CO57), .CZI1(CZI[0]), .CZI2(CZI[1]), From b202126c76ca921dee6768f7bf9f80efe38acb41 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 10:57:58 +0100 Subject: [PATCH 031/342] IOM --- techlibs/nanoxplore/cells_bb.v | 1831 ---------------------------- techlibs/nanoxplore/cells_bb_l.v | 153 +++ techlibs/nanoxplore/cells_bb_m.v | 237 ++++ techlibs/nanoxplore/cells_bb_u.v | 361 ++++++ techlibs/nanoxplore/cells_wrap_l.v | 302 ++++- techlibs/nanoxplore/cells_wrap_m.v | 465 ++++++- techlibs/nanoxplore/cells_wrap_u.v | 602 +++++++++ 7 files changed, 2118 insertions(+), 1833 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index b040ece78..ba7318c73 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -118,908 +118,6 @@ module NX_ECC(CKD, CHK, COR, ERR); output ERR; endmodule -(* blackbox *) -module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o -, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o -, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o -, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o -, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o -, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o -, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i -, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i -, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o -, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o -, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o -, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o -, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i); - input hssl_clk_ref_i; - input hssl_clk_user_i; - output hssl_clock_o; - input pma_clk_ext_i; - input pma_rx0_i; - input pma_rx1_i; - input pma_rx2_i; - input pma_rx3_i; - input pma_rx4_i; - input pma_rx5_i; - output pma_tx0_o; - output pma_tx1_o; - output pma_tx2_o; - output pma_tx3_o; - output pma_tx4_o; - output pma_tx5_o; - input usr_calibrate_pma_en_i; - output usr_calibrate_pma_out_o; - input [7:0] usr_calibrate_pma_res_n2_i; - input [7:0] usr_calibrate_pma_res_n3_i; - input [7:0] usr_calibrate_pma_res_p1_i; - input [7:0] usr_calibrate_pma_res_p4_i; - input [3:0] usr_calibrate_pma_sel_i; - input [5:0] usr_com_ctrl_rx_sel_i; - input [5:0] usr_com_ctrl_tx_sel_i; - input [3:0] usr_com_rx_pma_ctle_cap_i; - input [3:0] usr_com_rx_pma_ctle_resn_i; - input [3:0] usr_com_rx_pma_ctle_resp_i; - input usr_com_rx_pma_m_eye_i; - input [5:0] usr_com_tx_pma_main_en_i; - input usr_com_tx_pma_main_sign_i; - input [3:0] usr_com_tx_pma_margin_input_sel_i; - input [4:0] usr_com_tx_pma_margin_input_sel_var_i; - input [3:0] usr_com_tx_pma_margin_sel_i; - input [4:0] usr_com_tx_pma_margin_sel_var_i; - input [4:0] usr_com_tx_pma_post_en_i; - input [3:0] usr_com_tx_pma_post_input_sel_i; - input [3:0] usr_com_tx_pma_post_input_sel_var_i; - input usr_com_tx_pma_post_sign_i; - input usr_com_tx_pma_pre_en_i; - input [3:0] usr_com_tx_pma_pre_input_sel_i; - input usr_com_tx_pma_pre_sign_i; - input usr_main_rst_n_i; - input [7:0] usr_main_test_i; - output [7:0] usr_main_test_o; - input usr_pcs_ctrl_ovs_en_i; - input usr_pcs_ctrl_pll_lock_en_i; - output usr_pll_lock_o; - input usr_pll_pma_rst_n_i; - output usr_rx0_busy_o; - input usr_rx0_ctrl_align_en_i; - input usr_rx0_ctrl_align_sync_i; - output [7:0] usr_rx0_ctrl_char_is_a_o; - output usr_rx0_ctrl_char_is_aligned_o; - output [7:0] usr_rx0_ctrl_char_is_comma_o; - output [7:0] usr_rx0_ctrl_char_is_f_o; - output [7:0] usr_rx0_ctrl_char_is_k_o; - input usr_rx0_ctrl_dec_en_i; - output [7:0] usr_rx0_ctrl_disp_err_o; - input usr_rx0_ctrl_dscr_en_i; - input usr_rx0_ctrl_el_buff_fifo_en_i; - input usr_rx0_ctrl_el_buff_rst_i; - output [7:0] usr_rx0_ctrl_not_in_table_o; - input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; - input usr_rx0_ctrl_replace_en_i; - output [63:0] usr_rx0_data_o; - output usr_rx0_pll_lock_o; - input usr_rx0_pma_cdr_rst_i; - input usr_rx0_pma_ckgen_rst_n_i; - output usr_rx0_pma_loss_of_signal_o; - input usr_rx0_pma_pll_rst_n_i; - input usr_rx0_rst_n_i; - input [3:0] usr_rx0_test_i; - output [7:0] usr_rx0_test_o; - output usr_rx1_busy_o; - input usr_rx1_ctrl_align_en_i; - input usr_rx1_ctrl_align_sync_i; - output [7:0] usr_rx1_ctrl_char_is_a_o; - output usr_rx1_ctrl_char_is_aligned_o; - output [7:0] usr_rx1_ctrl_char_is_comma_o; - output [7:0] usr_rx1_ctrl_char_is_f_o; - output [7:0] usr_rx1_ctrl_char_is_k_o; - input usr_rx1_ctrl_dec_en_i; - output [7:0] usr_rx1_ctrl_disp_err_o; - input usr_rx1_ctrl_dscr_en_i; - input usr_rx1_ctrl_el_buff_fifo_en_i; - input usr_rx1_ctrl_el_buff_rst_i; - output [7:0] usr_rx1_ctrl_not_in_table_o; - input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; - input usr_rx1_ctrl_replace_en_i; - output [63:0] usr_rx1_data_o; - output usr_rx1_pll_lock_o; - input usr_rx1_pma_cdr_rst_i; - input usr_rx1_pma_ckgen_rst_n_i; - output usr_rx1_pma_loss_of_signal_o; - input usr_rx1_pma_pll_rst_n_i; - input usr_rx1_rst_n_i; - input [3:0] usr_rx1_test_i; - output [7:0] usr_rx1_test_o; - output usr_rx2_busy_o; - input usr_rx2_ctrl_align_en_i; - input usr_rx2_ctrl_align_sync_i; - output [7:0] usr_rx2_ctrl_char_is_a_o; - output usr_rx2_ctrl_char_is_aligned_o; - output [7:0] usr_rx2_ctrl_char_is_comma_o; - output [7:0] usr_rx2_ctrl_char_is_f_o; - output [7:0] usr_rx2_ctrl_char_is_k_o; - input usr_rx2_ctrl_dec_en_i; - output [7:0] usr_rx2_ctrl_disp_err_o; - input usr_rx2_ctrl_dscr_en_i; - input usr_rx2_ctrl_el_buff_fifo_en_i; - input usr_rx2_ctrl_el_buff_rst_i; - output [7:0] usr_rx2_ctrl_not_in_table_o; - input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; - input usr_rx2_ctrl_replace_en_i; - output [63:0] usr_rx2_data_o; - output usr_rx2_pll_lock_o; - input usr_rx2_pma_cdr_rst_i; - input usr_rx2_pma_ckgen_rst_n_i; - output usr_rx2_pma_loss_of_signal_o; - input usr_rx2_pma_pll_rst_n_i; - input usr_rx2_rst_n_i; - input [3:0] usr_rx2_test_i; - output [7:0] usr_rx2_test_o; - output usr_rx3_busy_o; - input usr_rx3_ctrl_align_en_i; - input usr_rx3_ctrl_align_sync_i; - output [7:0] usr_rx3_ctrl_char_is_a_o; - output usr_rx3_ctrl_char_is_aligned_o; - output [7:0] usr_rx3_ctrl_char_is_comma_o; - output [7:0] usr_rx3_ctrl_char_is_f_o; - output [7:0] usr_rx3_ctrl_char_is_k_o; - input usr_rx3_ctrl_dec_en_i; - output [7:0] usr_rx3_ctrl_disp_err_o; - input usr_rx3_ctrl_dscr_en_i; - input usr_rx3_ctrl_el_buff_fifo_en_i; - input usr_rx3_ctrl_el_buff_rst_i; - output [7:0] usr_rx3_ctrl_not_in_table_o; - input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; - input usr_rx3_ctrl_replace_en_i; - output [63:0] usr_rx3_data_o; - output usr_rx3_pll_lock_o; - input usr_rx3_pma_cdr_rst_i; - input usr_rx3_pma_ckgen_rst_n_i; - output usr_rx3_pma_loss_of_signal_o; - input usr_rx3_pma_pll_rst_n_i; - input usr_rx3_rst_n_i; - input [3:0] usr_rx3_test_i; - output [7:0] usr_rx3_test_o; - output usr_rx4_busy_o; - input usr_rx4_ctrl_align_en_i; - input usr_rx4_ctrl_align_sync_i; - output [7:0] usr_rx4_ctrl_char_is_a_o; - output usr_rx4_ctrl_char_is_aligned_o; - output [7:0] usr_rx4_ctrl_char_is_comma_o; - output [7:0] usr_rx4_ctrl_char_is_f_o; - output [7:0] usr_rx4_ctrl_char_is_k_o; - input usr_rx4_ctrl_dec_en_i; - output [7:0] usr_rx4_ctrl_disp_err_o; - input usr_rx4_ctrl_dscr_en_i; - input usr_rx4_ctrl_el_buff_fifo_en_i; - input usr_rx4_ctrl_el_buff_rst_i; - output [7:0] usr_rx4_ctrl_not_in_table_o; - input [1:0] usr_rx4_ctrl_ovs_bit_sel_i; - input usr_rx4_ctrl_replace_en_i; - output [63:0] usr_rx4_data_o; - output usr_rx4_pll_lock_o; - input usr_rx4_pma_cdr_rst_i; - input usr_rx4_pma_ckgen_rst_n_i; - output usr_rx4_pma_loss_of_signal_o; - input usr_rx4_pma_pll_rst_n_i; - input usr_rx4_rst_n_i; - input [3:0] usr_rx4_test_i; - output [7:0] usr_rx4_test_o; - output usr_rx5_busy_o; - input usr_rx5_ctrl_align_en_i; - input usr_rx5_ctrl_align_sync_i; - output [7:0] usr_rx5_ctrl_char_is_a_o; - output usr_rx5_ctrl_char_is_aligned_o; - output [7:0] usr_rx5_ctrl_char_is_comma_o; - output [7:0] usr_rx5_ctrl_char_is_f_o; - output [7:0] usr_rx5_ctrl_char_is_k_o; - input usr_rx5_ctrl_dec_en_i; - output [7:0] usr_rx5_ctrl_disp_err_o; - input usr_rx5_ctrl_dscr_en_i; - input usr_rx5_ctrl_el_buff_fifo_en_i; - input usr_rx5_ctrl_el_buff_rst_i; - output [7:0] usr_rx5_ctrl_not_in_table_o; - input [1:0] usr_rx5_ctrl_ovs_bit_sel_i; - input usr_rx5_ctrl_replace_en_i; - output [63:0] usr_rx5_data_o; - output usr_rx5_pll_lock_o; - input usr_rx5_pma_cdr_rst_i; - input usr_rx5_pma_ckgen_rst_n_i; - output usr_rx5_pma_loss_of_signal_o; - input usr_rx5_pma_pll_rst_n_i; - input usr_rx5_rst_n_i; - input [3:0] usr_rx5_test_i; - output [7:0] usr_rx5_test_o; - output usr_tx0_busy_o; - input [7:0] usr_tx0_ctrl_char_is_k_i; - input [7:0] usr_tx0_ctrl_enc_en_i; - input [7:0] usr_tx0_ctrl_end_of_frame_i; - input [7:0] usr_tx0_ctrl_end_of_multiframe_i; - input usr_tx0_ctrl_replace_en_i; - input [7:0] usr_tx0_ctrl_scr_en_i; - input [63:0] usr_tx0_data_i; - input usr_tx0_pma_clk_en_i; - input usr_tx0_rst_n_i; - input [3:0] usr_tx0_test_i; - output [3:0] usr_tx0_test_o; - output usr_tx1_busy_o; - input [7:0] usr_tx1_ctrl_char_is_k_i; - input [7:0] usr_tx1_ctrl_enc_en_i; - input [7:0] usr_tx1_ctrl_end_of_frame_i; - input [7:0] usr_tx1_ctrl_end_of_multiframe_i; - input usr_tx1_ctrl_replace_en_i; - input [7:0] usr_tx1_ctrl_scr_en_i; - input [63:0] usr_tx1_data_i; - input usr_tx1_pma_clk_en_i; - input usr_tx1_rst_n_i; - input [3:0] usr_tx1_test_i; - output [3:0] usr_tx1_test_o; - output usr_tx2_busy_o; - input [7:0] usr_tx2_ctrl_char_is_k_i; - input [7:0] usr_tx2_ctrl_enc_en_i; - input [7:0] usr_tx2_ctrl_end_of_frame_i; - input [7:0] usr_tx2_ctrl_end_of_multiframe_i; - input usr_tx2_ctrl_replace_en_i; - input [7:0] usr_tx2_ctrl_scr_en_i; - input [63:0] usr_tx2_data_i; - input usr_tx2_pma_clk_en_i; - input usr_tx2_rst_n_i; - input [3:0] usr_tx2_test_i; - output [3:0] usr_tx2_test_o; - output usr_tx3_busy_o; - input [7:0] usr_tx3_ctrl_char_is_k_i; - input [7:0] usr_tx3_ctrl_enc_en_i; - input [7:0] usr_tx3_ctrl_end_of_frame_i; - input [7:0] usr_tx3_ctrl_end_of_multiframe_i; - input usr_tx3_ctrl_replace_en_i; - input [7:0] usr_tx3_ctrl_scr_en_i; - input [63:0] usr_tx3_data_i; - input usr_tx3_pma_clk_en_i; - input usr_tx3_rst_n_i; - input [3:0] usr_tx3_test_i; - output [3:0] usr_tx3_test_o; - output usr_tx4_busy_o; - input [7:0] usr_tx4_ctrl_char_is_k_i; - input [7:0] usr_tx4_ctrl_enc_en_i; - input [7:0] usr_tx4_ctrl_end_of_frame_i; - input [7:0] usr_tx4_ctrl_end_of_multiframe_i; - input usr_tx4_ctrl_replace_en_i; - input [7:0] usr_tx4_ctrl_scr_en_i; - input [63:0] usr_tx4_data_i; - input usr_tx4_pma_clk_en_i; - input usr_tx4_rst_n_i; - input [3:0] usr_tx4_test_i; - output [3:0] usr_tx4_test_o; - output usr_tx5_busy_o; - input [7:0] usr_tx5_ctrl_char_is_k_i; - input [7:0] usr_tx5_ctrl_enc_en_i; - input [7:0] usr_tx5_ctrl_end_of_frame_i; - input [7:0] usr_tx5_ctrl_end_of_multiframe_i; - input usr_tx5_ctrl_replace_en_i; - input [7:0] usr_tx5_ctrl_scr_en_i; - input [63:0] usr_tx5_data_i; - input usr_tx5_pma_clk_en_i; - input usr_tx5_rst_n_i; - input [3:0] usr_tx5_test_i; - output [3:0] usr_tx5_test_o; - parameter cfg_main_i = 34'b0000000000000000000000000000000000; - parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter cfg_tx0_i = 0; - parameter cfg_tx1_i = 0; - parameter cfg_tx2_i = 0; - parameter cfg_tx3_i = 0; - parameter cfg_tx4_i = 0; - parameter cfg_tx5_i = 0; - parameter location = ""; -endmodule - -(* blackbox *) -module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i -, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o -, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o -, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i -, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i -, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o -, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o -, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i -, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i -, usr_dyn_cfg_lane_cs_n_i); - input hssl_clk_ref_i; - input hssl_clk_user_rx_i; - input hssl_clk_user_tx_i; - output hssl_clock_o; - output hssl_rclock_o; - input scan_en_i; - input [7:0] scan_in_i; - output [7:0] scan_out_o; - output usr_calibrate_pma_out_o; - input [3:0] usr_dyn_cfg_addr_i; - input usr_dyn_cfg_calibration_cs_n_i; - input usr_dyn_cfg_en_i; - input [3:0] usr_dyn_cfg_lane_cs_n_i; - input [11:0] usr_dyn_cfg_wdata_i; - input usr_dyn_cfg_wdata_sel_i; - input usr_dyn_cfg_we_n_i; - input usr_main_async_debug_ack_i; - input [1:0] usr_main_async_debug_lane_sel_i; - output usr_main_async_debug_req_o; - input usr_main_rst_n_i; - output [19:0] usr_main_rx_pma_ll_out_o; - output usr_pll_ckfb_lock_o; - output usr_pll_lock_o; - output usr_pll_pma_lock_analog_o; - input usr_pll_pma_pwr_down_n_i; - input usr_pll_pma_rst_n_i; - output usr_rx0_busy_o; - input usr_rx0_ctrl_align_en_i; - input usr_rx0_ctrl_align_sync_i; - output [7:0] usr_rx0_ctrl_char_is_a_o; - output usr_rx0_ctrl_char_is_aligned_o; - output [7:0] usr_rx0_ctrl_char_is_comma_o; - output [7:0] usr_rx0_ctrl_char_is_f_o; - output [7:0] usr_rx0_ctrl_char_is_k_o; - input [2:0] usr_rx0_ctrl_debug_sel_i; - input usr_rx0_ctrl_dec_en_i; - output [7:0] usr_rx0_ctrl_disp_err_o; - input usr_rx0_ctrl_dscr_en_i; - input usr_rx0_ctrl_el_buff_rst_i; - output [7:0] usr_rx0_ctrl_not_in_table_o; - input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; - input usr_rx0_ctrl_replace_en_i; - output usr_rx0_ctrl_valid_realign_o; - output [63:0] usr_rx0_data_o; - output usr_rx0_pma_ll_fast_locked_o; - output usr_rx0_pma_ll_slow_locked_o; - output usr_rx0_pma_loss_of_signal_o; - input usr_rx0_pma_m_eye_rst_i; - output usr_rx0_pma_pll_lock_o; - output usr_rx0_pma_pll_lock_track_o; - input usr_rx0_pma_pwr_down_n_i; - input usr_rx0_pma_rst_n_i; - input usr_rx0_rst_n_i; - output [7:0] usr_rx0_test_o; - output usr_rx1_busy_o; - input usr_rx1_ctrl_align_en_i; - input usr_rx1_ctrl_align_sync_i; - output [7:0] usr_rx1_ctrl_char_is_a_o; - output usr_rx1_ctrl_char_is_aligned_o; - output [7:0] usr_rx1_ctrl_char_is_comma_o; - output [7:0] usr_rx1_ctrl_char_is_f_o; - output [7:0] usr_rx1_ctrl_char_is_k_o; - input [2:0] usr_rx1_ctrl_debug_sel_i; - input usr_rx1_ctrl_dec_en_i; - output [7:0] usr_rx1_ctrl_disp_err_o; - input usr_rx1_ctrl_dscr_en_i; - input usr_rx1_ctrl_el_buff_rst_i; - output [7:0] usr_rx1_ctrl_not_in_table_o; - input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; - input usr_rx1_ctrl_replace_en_i; - output usr_rx1_ctrl_valid_realign_o; - output [63:0] usr_rx1_data_o; - output usr_rx1_pma_ll_fast_locked_o; - output usr_rx1_pma_ll_slow_locked_o; - output usr_rx1_pma_loss_of_signal_o; - input usr_rx1_pma_m_eye_rst_i; - output usr_rx1_pma_pll_lock_o; - output usr_rx1_pma_pll_lock_track_o; - input usr_rx1_pma_pwr_down_n_i; - input usr_rx1_pma_rst_n_i; - input usr_rx1_rst_n_i; - output [7:0] usr_rx1_test_o; - output usr_rx2_busy_o; - input usr_rx2_ctrl_align_en_i; - input usr_rx2_ctrl_align_sync_i; - output [7:0] usr_rx2_ctrl_char_is_a_o; - output usr_rx2_ctrl_char_is_aligned_o; - output [7:0] usr_rx2_ctrl_char_is_comma_o; - output [7:0] usr_rx2_ctrl_char_is_f_o; - output [7:0] usr_rx2_ctrl_char_is_k_o; - input [2:0] usr_rx2_ctrl_debug_sel_i; - input usr_rx2_ctrl_dec_en_i; - output [7:0] usr_rx2_ctrl_disp_err_o; - input usr_rx2_ctrl_dscr_en_i; - input usr_rx2_ctrl_el_buff_rst_i; - output [7:0] usr_rx2_ctrl_not_in_table_o; - input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; - input usr_rx2_ctrl_replace_en_i; - output usr_rx2_ctrl_valid_realign_o; - output [63:0] usr_rx2_data_o; - output usr_rx2_pma_ll_fast_locked_o; - output usr_rx2_pma_ll_slow_locked_o; - output usr_rx2_pma_loss_of_signal_o; - input usr_rx2_pma_m_eye_rst_i; - output usr_rx2_pma_pll_lock_o; - output usr_rx2_pma_pll_lock_track_o; - input usr_rx2_pma_pwr_down_n_i; - input usr_rx2_pma_rst_n_i; - input usr_rx2_rst_n_i; - output [7:0] usr_rx2_test_o; - output usr_rx3_busy_o; - input usr_rx3_ctrl_align_en_i; - input usr_rx3_ctrl_align_sync_i; - output [7:0] usr_rx3_ctrl_char_is_a_o; - output usr_rx3_ctrl_char_is_aligned_o; - output [7:0] usr_rx3_ctrl_char_is_comma_o; - output [7:0] usr_rx3_ctrl_char_is_f_o; - output [7:0] usr_rx3_ctrl_char_is_k_o; - input [2:0] usr_rx3_ctrl_debug_sel_i; - input usr_rx3_ctrl_dec_en_i; - output [7:0] usr_rx3_ctrl_disp_err_o; - input usr_rx3_ctrl_dscr_en_i; - input usr_rx3_ctrl_el_buff_rst_i; - output [7:0] usr_rx3_ctrl_not_in_table_o; - input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; - input usr_rx3_ctrl_replace_en_i; - output usr_rx3_ctrl_valid_realign_o; - output [63:0] usr_rx3_data_o; - output usr_rx3_pma_ll_fast_locked_o; - output usr_rx3_pma_ll_slow_locked_o; - output usr_rx3_pma_loss_of_signal_o; - input usr_rx3_pma_m_eye_rst_i; - output usr_rx3_pma_pll_lock_o; - output usr_rx3_pma_pll_lock_track_o; - input usr_rx3_pma_pwr_down_n_i; - input usr_rx3_pma_rst_n_i; - input usr_rx3_rst_n_i; - output [7:0] usr_rx3_test_o; - output usr_tx0_busy_o; - input [7:0] usr_tx0_ctrl_char_is_k_i; - input usr_tx0_ctrl_driver_pwrdwn_n_i; - input [7:0] usr_tx0_ctrl_enc_en_i; - input [7:0] usr_tx0_ctrl_end_of_frame_i; - input [7:0] usr_tx0_ctrl_end_of_multiframe_i; - output usr_tx0_ctrl_invalid_k_o; - input usr_tx0_ctrl_replace_en_i; - input [7:0] usr_tx0_ctrl_scr_en_i; - input [63:0] usr_tx0_data_i; - input usr_tx0_pma_clk_en_i; - output usr_tx0_pma_tx_clk_o; - input usr_tx0_rst_n_i; - output usr_tx1_busy_o; - input [7:0] usr_tx1_ctrl_char_is_k_i; - input usr_tx1_ctrl_driver_pwrdwn_n_i; - input [7:0] usr_tx1_ctrl_enc_en_i; - input [7:0] usr_tx1_ctrl_end_of_frame_i; - input [7:0] usr_tx1_ctrl_end_of_multiframe_i; - output usr_tx1_ctrl_invalid_k_o; - input usr_tx1_ctrl_replace_en_i; - input [7:0] usr_tx1_ctrl_scr_en_i; - input [63:0] usr_tx1_data_i; - input usr_tx1_pma_clk_en_i; - output usr_tx1_pma_tx_clk_o; - input usr_tx1_rst_n_i; - output usr_tx2_busy_o; - input [7:0] usr_tx2_ctrl_char_is_k_i; - input usr_tx2_ctrl_driver_pwrdwn_n_i; - input [7:0] usr_tx2_ctrl_enc_en_i; - input [7:0] usr_tx2_ctrl_end_of_frame_i; - input [7:0] usr_tx2_ctrl_end_of_multiframe_i; - output usr_tx2_ctrl_invalid_k_o; - input usr_tx2_ctrl_replace_en_i; - input [7:0] usr_tx2_ctrl_scr_en_i; - input [63:0] usr_tx2_data_i; - input usr_tx2_pma_clk_en_i; - output usr_tx2_pma_tx_clk_o; - input usr_tx2_rst_n_i; - output usr_tx3_busy_o; - input [7:0] usr_tx3_ctrl_char_is_k_i; - input usr_tx3_ctrl_driver_pwrdwn_n_i; - input [7:0] usr_tx3_ctrl_enc_en_i; - input [7:0] usr_tx3_ctrl_end_of_frame_i; - input [7:0] usr_tx3_ctrl_end_of_multiframe_i; - output usr_tx3_ctrl_invalid_k_o; - input usr_tx3_ctrl_replace_en_i; - input [7:0] usr_tx3_ctrl_scr_en_i; - input [63:0] usr_tx3_data_i; - input usr_tx3_pma_clk_en_i; - output usr_tx3_pma_tx_clk_o; - input usr_tx3_rst_n_i; - parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0; - parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0; - parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0; - parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0; - parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000; - parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0; - parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000; - parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000; - parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000; - parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00; - parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000; - parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000; - parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000; - parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000; - parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000; - parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000; - parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000; - parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000; - parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000; - parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000; - parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000; - parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000; - parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000; - parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000; - parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000; - parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000; - parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000; - parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000; - parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000; - parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000; - parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000; - parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000; - parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000; - parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000; - parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000; - parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000; - parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000; - parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000; - parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000; - parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000; - parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0; - parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000; - parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000; - parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000; - parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000; - parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0; - parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0; - parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000; - parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0; - parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000; - parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0; - parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000; - parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000; - parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000; - parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000; - parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0; - parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0; - parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000; - parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0; - parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000; - parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0; - parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000; - parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000; - parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000; - parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000; - parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0; - parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0; - parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000; - parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0; - parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000; - parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0; - parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000; - parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000; - parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000; - parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000; - parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0; - parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0; - parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000; - parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0; - parameter cfg_main_clk_to_fabric_div_en_i = 1'b0; - parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0; - parameter cfg_main_clk_to_fabric_sel_i = 1'b0; - parameter cfg_main_rclk_to_fabric_sel_i = 2'b00; - parameter cfg_main_use_only_usr_clock_i = 1'b0; - parameter cfg_pcs_ovs_en_i = 1'b0; - parameter cfg_pcs_ovs_mode_i = 1'b0; - parameter cfg_pcs_pll_lock_ppm_i = 3'b000; - parameter cfg_pcs_word_len_i = 2'b00; - parameter cfg_pll_pma_ckref_ext_i = 1'b0; - parameter cfg_pll_pma_cpump_i = 4'b0000; - parameter cfg_pll_pma_divl_i = 2'b00; - parameter cfg_pll_pma_divm_i = 1'b0; - parameter cfg_pll_pma_divn_i = 2'b00; - parameter cfg_pll_pma_gbx_en_i = 1'b0; - parameter cfg_pll_pma_int_data_len_i = 1'b0; - parameter cfg_pll_pma_lvds_en_i = 1'b0; - parameter cfg_pll_pma_lvds_mux_i = 1'b0; - parameter cfg_pll_pma_mux_ckref_i = 1'b0; - parameter cfg_rx0_gearbox_en_i = 1'b0; - parameter cfg_rx0_gearbox_mode_i = 1'b0; - parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0; - parameter cfg_rx0_pcs_align_bypass_i = 1'b0; - parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0; - parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0; - parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000; - parameter cfg_rx0_pcs_debug_en_i = 1'b0; - parameter cfg_rx0_pcs_dec_bypass_i = 1'b0; - parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0; - parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000; - parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000; - parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0; - parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000; - parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00; - parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00; - parameter cfg_rx0_pcs_fsm_sel_i = 2'b00; - parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0; - parameter cfg_rx0_pcs_loopback_i = 1'b0; - parameter cfg_rx0_pcs_m_comma_en_i = 1'b0; - parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000; - parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00; - parameter cfg_rx0_pcs_p_comma_en_i = 1'b0; - parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000; - parameter cfg_rx0_pcs_polarity_i = 1'b0; - parameter cfg_rx0_pcs_protocol_size_i = 1'b0; - parameter cfg_rx0_pcs_replace_bypass_i = 1'b0; - parameter cfg_rx0_pcs_sync_supported_i = 1'b0; - parameter cfg_rx0_pma_cdr_cp_i = 4'b0000; - parameter cfg_rx0_pma_clk_pos_i = 1'b0; - parameter cfg_rx0_pma_coarse_ppm_i = 3'b000; - parameter cfg_rx0_pma_ctrl_term_i = 6'b000000; - parameter cfg_rx0_pma_dco_divl_i = 2'b00; - parameter cfg_rx0_pma_dco_divm_i = 1'b0; - parameter cfg_rx0_pma_dco_divn_i = 2'b00; - parameter cfg_rx0_pma_dco_reg_res_i = 2'b00; - parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0; - parameter cfg_rx0_pma_fine_ppm_i = 3'b000; - parameter cfg_rx0_pma_loopback_i = 1'b0; - parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000; - parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00; - parameter cfg_rx0_pma_peak_detect_on_i = 1'b0; - parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000; - parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0; - parameter cfg_rx0_pma_pll_divf_i = 2'b00; - parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0; - parameter cfg_rx0_pma_pll_divm_i = 2'b00; - parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0; - parameter cfg_rx0_pma_pll_divn_i = 1'b0; - parameter cfg_rx1_gearbox_en_i = 1'b0; - parameter cfg_rx1_gearbox_mode_i = 1'b0; - parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0; - parameter cfg_rx1_pcs_align_bypass_i = 1'b0; - parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0; - parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0; - parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000; - parameter cfg_rx1_pcs_debug_en_i = 1'b0; - parameter cfg_rx1_pcs_dec_bypass_i = 1'b0; - parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0; - parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000; - parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000; - parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0; - parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000; - parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00; - parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00; - parameter cfg_rx1_pcs_fsm_sel_i = 2'b00; - parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0; - parameter cfg_rx1_pcs_loopback_i = 1'b0; - parameter cfg_rx1_pcs_m_comma_en_i = 1'b0; - parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000; - parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00; - parameter cfg_rx1_pcs_p_comma_en_i = 1'b0; - parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000; - parameter cfg_rx1_pcs_polarity_i = 1'b0; - parameter cfg_rx1_pcs_protocol_size_i = 1'b0; - parameter cfg_rx1_pcs_replace_bypass_i = 1'b0; - parameter cfg_rx1_pcs_sync_supported_i = 1'b0; - parameter cfg_rx1_pma_cdr_cp_i = 4'b0000; - parameter cfg_rx1_pma_clk_pos_i = 1'b0; - parameter cfg_rx1_pma_coarse_ppm_i = 3'b000; - parameter cfg_rx1_pma_ctrl_term_i = 6'b000000; - parameter cfg_rx1_pma_dco_divl_i = 2'b00; - parameter cfg_rx1_pma_dco_divm_i = 1'b0; - parameter cfg_rx1_pma_dco_divn_i = 2'b00; - parameter cfg_rx1_pma_dco_reg_res_i = 2'b00; - parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0; - parameter cfg_rx1_pma_fine_ppm_i = 3'b000; - parameter cfg_rx1_pma_loopback_i = 1'b0; - parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000; - parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00; - parameter cfg_rx1_pma_peak_detect_on_i = 1'b0; - parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000; - parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0; - parameter cfg_rx1_pma_pll_divf_i = 2'b00; - parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0; - parameter cfg_rx1_pma_pll_divm_i = 2'b00; - parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0; - parameter cfg_rx1_pma_pll_divn_i = 1'b0; - parameter cfg_rx2_gearbox_en_i = 1'b0; - parameter cfg_rx2_gearbox_mode_i = 1'b0; - parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0; - parameter cfg_rx2_pcs_align_bypass_i = 1'b0; - parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0; - parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0; - parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000; - parameter cfg_rx2_pcs_debug_en_i = 1'b0; - parameter cfg_rx2_pcs_dec_bypass_i = 1'b0; - parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0; - parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000; - parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000; - parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0; - parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000; - parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00; - parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00; - parameter cfg_rx2_pcs_fsm_sel_i = 2'b00; - parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0; - parameter cfg_rx2_pcs_loopback_i = 1'b0; - parameter cfg_rx2_pcs_m_comma_en_i = 1'b0; - parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000; - parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00; - parameter cfg_rx2_pcs_p_comma_en_i = 1'b0; - parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000; - parameter cfg_rx2_pcs_polarity_i = 1'b0; - parameter cfg_rx2_pcs_protocol_size_i = 1'b0; - parameter cfg_rx2_pcs_replace_bypass_i = 1'b0; - parameter cfg_rx2_pcs_sync_supported_i = 1'b0; - parameter cfg_rx2_pma_cdr_cp_i = 4'b0000; - parameter cfg_rx2_pma_clk_pos_i = 1'b0; - parameter cfg_rx2_pma_coarse_ppm_i = 3'b000; - parameter cfg_rx2_pma_ctrl_term_i = 6'b000000; - parameter cfg_rx2_pma_dco_divl_i = 2'b00; - parameter cfg_rx2_pma_dco_divm_i = 1'b0; - parameter cfg_rx2_pma_dco_divn_i = 2'b00; - parameter cfg_rx2_pma_dco_reg_res_i = 2'b00; - parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0; - parameter cfg_rx2_pma_fine_ppm_i = 3'b000; - parameter cfg_rx2_pma_loopback_i = 1'b0; - parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000; - parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00; - parameter cfg_rx2_pma_peak_detect_on_i = 1'b0; - parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000; - parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0; - parameter cfg_rx2_pma_pll_divf_i = 2'b00; - parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0; - parameter cfg_rx2_pma_pll_divm_i = 2'b00; - parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0; - parameter cfg_rx2_pma_pll_divn_i = 1'b0; - parameter cfg_rx3_gearbox_en_i = 1'b0; - parameter cfg_rx3_gearbox_mode_i = 1'b0; - parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0; - parameter cfg_rx3_pcs_align_bypass_i = 1'b0; - parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0; - parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0; - parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000; - parameter cfg_rx3_pcs_debug_en_i = 1'b0; - parameter cfg_rx3_pcs_dec_bypass_i = 1'b0; - parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0; - parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000; - parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000; - parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0; - parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000; - parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00; - parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00; - parameter cfg_rx3_pcs_fsm_sel_i = 2'b00; - parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0; - parameter cfg_rx3_pcs_loopback_i = 1'b0; - parameter cfg_rx3_pcs_m_comma_en_i = 1'b0; - parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000; - parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00; - parameter cfg_rx3_pcs_p_comma_en_i = 1'b0; - parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000; - parameter cfg_rx3_pcs_polarity_i = 1'b0; - parameter cfg_rx3_pcs_protocol_size_i = 1'b0; - parameter cfg_rx3_pcs_replace_bypass_i = 1'b0; - parameter cfg_rx3_pcs_sync_supported_i = 1'b0; - parameter cfg_rx3_pma_cdr_cp_i = 4'b0000; - parameter cfg_rx3_pma_clk_pos_i = 1'b0; - parameter cfg_rx3_pma_coarse_ppm_i = 3'b000; - parameter cfg_rx3_pma_ctrl_term_i = 6'b000000; - parameter cfg_rx3_pma_dco_divl_i = 2'b00; - parameter cfg_rx3_pma_dco_divm_i = 1'b0; - parameter cfg_rx3_pma_dco_divn_i = 2'b00; - parameter cfg_rx3_pma_dco_reg_res_i = 2'b00; - parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0; - parameter cfg_rx3_pma_fine_ppm_i = 3'b000; - parameter cfg_rx3_pma_loopback_i = 1'b0; - parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000; - parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00; - parameter cfg_rx3_pma_peak_detect_on_i = 1'b0; - parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000; - parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0; - parameter cfg_rx3_pma_pll_divf_i = 2'b00; - parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0; - parameter cfg_rx3_pma_pll_divm_i = 2'b00; - parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0; - parameter cfg_rx3_pma_pll_divn_i = 1'b0; - parameter cfg_test_mode_i = 2'b00; - parameter cfg_tx0_gearbox_en_i = 1'b0; - parameter cfg_tx0_gearbox_mode_i = 1'b0; - parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0; - parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_tx0_pcs_enc_bypass_i = 1'b0; - parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0; - parameter cfg_tx0_pcs_loopback_i = 1'b0; - parameter cfg_tx0_pcs_polarity_i = 1'b0; - parameter cfg_tx0_pcs_protocol_size_i = 1'b0; - parameter cfg_tx0_pcs_replace_bypass_i = 1'b0; - parameter cfg_tx0_pcs_scr_bypass_i = 1'b0; - parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000; - parameter cfg_tx0_pcs_sync_supported_i = 1'b0; - parameter cfg_tx0_pma_clk_pos_i = 1'b0; - parameter cfg_tx0_pma_loopback_i = 1'b0; - parameter cfg_tx1_gearbox_en_i = 1'b0; - parameter cfg_tx1_gearbox_mode_i = 1'b0; - parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0; - parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_tx1_pcs_enc_bypass_i = 1'b0; - parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0; - parameter cfg_tx1_pcs_loopback_i = 1'b0; - parameter cfg_tx1_pcs_polarity_i = 1'b0; - parameter cfg_tx1_pcs_protocol_size_i = 1'b0; - parameter cfg_tx1_pcs_replace_bypass_i = 1'b0; - parameter cfg_tx1_pcs_scr_bypass_i = 1'b0; - parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000; - parameter cfg_tx1_pcs_sync_supported_i = 1'b0; - parameter cfg_tx1_pma_clk_pos_i = 1'b0; - parameter cfg_tx1_pma_loopback_i = 1'b0; - parameter cfg_tx2_gearbox_en_i = 1'b0; - parameter cfg_tx2_gearbox_mode_i = 1'b0; - parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0; - parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_tx2_pcs_enc_bypass_i = 1'b0; - parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0; - parameter cfg_tx2_pcs_loopback_i = 1'b0; - parameter cfg_tx2_pcs_polarity_i = 1'b0; - parameter cfg_tx2_pcs_protocol_size_i = 1'b0; - parameter cfg_tx2_pcs_replace_bypass_i = 1'b0; - parameter cfg_tx2_pcs_scr_bypass_i = 1'b0; - parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000; - parameter cfg_tx2_pcs_sync_supported_i = 1'b0; - parameter cfg_tx2_pma_clk_pos_i = 1'b0; - parameter cfg_tx2_pma_loopback_i = 1'b0; - parameter cfg_tx3_gearbox_en_i = 1'b0; - parameter cfg_tx3_gearbox_mode_i = 1'b0; - parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0; - parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0; - parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0; - parameter cfg_tx3_pcs_enc_bypass_i = 1'b0; - parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0; - parameter cfg_tx3_pcs_loopback_i = 1'b0; - parameter cfg_tx3_pcs_polarity_i = 1'b0; - parameter cfg_tx3_pcs_protocol_size_i = 1'b0; - parameter cfg_tx3_pcs_replace_bypass_i = 1'b0; - parameter cfg_tx3_pcs_scr_bypass_i = 1'b0; - parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000; - parameter cfg_tx3_pcs_sync_supported_i = 1'b0; - parameter cfg_tx3_pma_clk_pos_i = 1'b0; - parameter cfg_tx3_pma_loopback_i = 1'b0; - parameter location = ""; - parameter rx_usrclk_use_pcs_clk_2 = 1'b0; - parameter tx_usrclk_use_pcs_clk_2 = 1'b0; -endmodule - (* blackbox *) module NX_IOB(I, C, T, O, IO); input C; @@ -1116,935 +214,6 @@ module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA); output [3:0] PA; endmodule -(* blackbox *) -module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 -, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 -, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 -, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 -, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 -, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); - output C1RED; - input C1RNE; - input C1RS; - input C1RW1; - input C1RW2; - input C1RW3; - input C1TS; - input C1TW; - output C2RED; - input C2RNE; - input C2RS; - input C2RW1; - input C2RW2; - input C2RW3; - input C2TS; - input C2TW; - input CAD1; - input CAD2; - input CAD3; - input CAD4; - input CAD5; - input CAD6; - output CAL; - input CAN1; - input CAN2; - input CAN3; - input CAN4; - input CAP1; - input CAP2; - input CAP3; - input CAP4; - input CAT1; - input CAT2; - input CAT3; - input CAT4; - input CCK; - output CKO1; - output CKO2; - input CTCK; - input DC; - input DCK; - input DIG; - input DIS; - input DOG; - input DOS; - input DPAG; - input DPAS; - input DQSG; - input DQSS; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRA5; - input DRA6; - input DRI1; - input DRI2; - input DRI3; - input DRI4; - input DRI5; - input DRI6; - input DRL; - output DRO1; - output DRO2; - output DRO3; - output DRO4; - output DRO5; - output DRO6; - input DS1; - input DS2; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - output FLD; - output FLG; - input FZ; - inout [41:0] LINK1; - inout [41:0] LINK10; - inout [41:0] LINK11; - inout [41:0] LINK12; - inout [41:0] LINK13; - inout [41:0] LINK14; - inout [41:0] LINK15; - inout [41:0] LINK16; - inout [41:0] LINK17; - inout [41:0] LINK18; - inout [41:0] LINK19; - inout [41:0] LINK2; - inout [41:0] LINK20; - inout [41:0] LINK21; - inout [41:0] LINK22; - inout [41:0] LINK23; - inout [41:0] LINK24; - inout [41:0] LINK25; - inout [41:0] LINK26; - inout [41:0] LINK27; - inout [41:0] LINK28; - inout [41:0] LINK29; - inout [41:0] LINK3; - inout [41:0] LINK30; - inout [41:0] LINK31; - inout [41:0] LINK32; - inout [41:0] LINK33; - inout [41:0] LINK34; - inout [41:0] LINK4; - inout [41:0] LINK5; - inout [41:0] LINK6; - inout [41:0] LINK7; - inout [41:0] LINK8; - inout [41:0] LINK9; - input RRCK1; - input RRCK2; - input RTCK1; - input RTCK2; - input SPI1; - input SPI2; - input SPI3; - input WRCK1; - input WRCK2; - input WTCK1; - input WTCK2; - parameter div_rx1 = 4'b0000; - parameter div_rx2 = 4'b0000; - parameter div_tx1 = 4'b0000; - parameter div_tx2 = 4'b0000; - parameter inv_di_fclk1 = 1'b0; - parameter inv_di_fclk2 = 1'b0; - parameter latency1 = 1'b0; - parameter latency2 = 1'b0; - parameter location = ""; - parameter mode_cpath = ""; - parameter mode_epath = ""; - parameter mode_io_cal = 1'b0; - parameter mode_rpath = ""; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter mode_tpath = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_clkr_rx1 = 1'b0; - parameter sel_clkr_rx2 = 1'b0; - parameter sel_clkw_rx1 = 2'b00; - parameter sel_clkw_rx2 = 2'b00; -endmodule - -(* blackbox *) -module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 -, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 -, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 -, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 -, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19 -, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); - output C1RED; - input C1RNE; - input C1RS; - input C1RW1; - input C1RW2; - input C1RW3; - input C1TS; - input C1TW; - output C2RED; - input C2RNE; - input C2RS; - input C2RW1; - input C2RW2; - input C2RW3; - input C2TS; - input C2TW; - input CAD1; - input CAD2; - input CAD3; - input CAD4; - input CAD5; - input CAD6; - output CAL; - input CAN1; - input CAN2; - input CAN3; - input CAN4; - input CAP1; - input CAP2; - input CAP3; - input CAP4; - input CAT1; - input CAT2; - input CAT3; - input CAT4; - input CCK; - output CKO1; - output CKO2; - input CTCK; - input DC; - input DCK; - input DIG; - input DIS; - input DOG; - input DOS; - input DPAG; - input DPAS; - input DQSG; - input DQSS; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRA5; - input DRA6; - input DRI1; - input DRI2; - input DRI3; - input DRI4; - input DRI5; - input DRI6; - input DRL; - output DRO1; - output DRO2; - output DRO3; - output DRO4; - output DRO5; - output DRO6; - input DS1; - input DS2; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - output FLD; - output FLG; - input FZ; - inout [41:0] LINK1; - inout [41:0] LINK10; - inout [41:0] LINK11; - inout [41:0] LINK12; - inout [41:0] LINK13; - inout [41:0] LINK14; - inout [41:0] LINK15; - inout [41:0] LINK16; - inout [41:0] LINK17; - inout [41:0] LINK18; - inout [41:0] LINK19; - inout [41:0] LINK2; - inout [41:0] LINK20; - inout [41:0] LINK21; - inout [41:0] LINK22; - inout [41:0] LINK23; - inout [41:0] LINK24; - inout [41:0] LINK25; - inout [41:0] LINK26; - inout [41:0] LINK27; - inout [41:0] LINK28; - inout [41:0] LINK29; - inout [41:0] LINK3; - inout [41:0] LINK30; - inout [41:0] LINK31; - inout [41:0] LINK32; - inout [41:0] LINK33; - inout [41:0] LINK34; - inout [41:0] LINK4; - inout [41:0] LINK5; - inout [41:0] LINK6; - inout [41:0] LINK7; - inout [41:0] LINK8; - inout [41:0] LINK9; - input RRCK1; - input RRCK2; - input RTCK1; - input RTCK2; - input WRCK1; - input WRCK2; - input WTCK1; - input WTCK2; - parameter div_rx1 = 4'b0000; - parameter div_rx2 = 4'b0000; - parameter div_tx1 = 4'b0000; - parameter div_tx2 = 4'b0000; - parameter inv_di_fclk1 = 1'b0; - parameter inv_di_fclk2 = 1'b0; - parameter latency1 = 1'b0; - parameter latency2 = 1'b0; - parameter location = ""; - parameter mode_cpath = ""; - parameter mode_epath = ""; - parameter mode_io_cal = 1'b0; - parameter mode_rpath = ""; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter mode_tpath = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_clkr_rx1 = 1'b0; - parameter sel_clkr_rx2 = 1'b0; - parameter sel_clkw_rx1 = 2'b00; - parameter sel_clkw_rx2 = 2'b00; -endmodule - -(* blackbox *) -module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 -, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 -, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 -, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 -, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 -, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); - output C1RED; - input C1RNE; - input C1RS; - input C1RW1; - input C1RW2; - input C1RW3; - input C1TS; - input C1TW; - output C2RED; - input C2RNE; - input C2RS; - input C2RW1; - input C2RW2; - input C2RW3; - input C2TS; - input C2TW; - input CAD1; - input CAD2; - input CAD3; - input CAD4; - input CAD5; - input CAD6; - output CAL; - input CAN1; - input CAN2; - input CAN3; - input CAN4; - input CAP1; - input CAP2; - input CAP3; - input CAP4; - input CAT1; - input CAT2; - input CAT3; - input CAT4; - input CCK; - output CKO1; - output CKO2; - input CTCK; - input DC; - input DCK; - input DIG; - input DIS; - input DOG; - input DOS; - input DPAG; - input DPAS; - input DQSG; - input DQSS; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRA5; - input DRA6; - input DRI1; - input DRI2; - input DRI3; - input DRI4; - input DRI5; - input DRI6; - input DRL; - output DRO1; - output DRO2; - output DRO3; - output DRO4; - output DRO5; - output DRO6; - input DS1; - input DS2; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - output FLD; - output FLG; - input FZ; - inout [41:0] LINK1; - inout [41:0] LINK10; - inout [41:0] LINK11; - inout [41:0] LINK12; - inout [41:0] LINK13; - inout [41:0] LINK14; - inout [41:0] LINK15; - inout [41:0] LINK16; - inout [41:0] LINK17; - inout [41:0] LINK18; - inout [41:0] LINK19; - inout [41:0] LINK2; - inout [41:0] LINK20; - inout [41:0] LINK21; - inout [41:0] LINK22; - inout [41:0] LINK23; - inout [41:0] LINK24; - inout [41:0] LINK25; - inout [41:0] LINK26; - inout [41:0] LINK27; - inout [41:0] LINK28; - inout [41:0] LINK29; - inout [41:0] LINK3; - inout [41:0] LINK30; - inout [41:0] LINK31; - inout [41:0] LINK32; - inout [41:0] LINK33; - inout [41:0] LINK34; - inout [41:0] LINK4; - inout [41:0] LINK5; - inout [41:0] LINK6; - inout [41:0] LINK7; - inout [41:0] LINK8; - inout [41:0] LINK9; - input RRCK1; - input RRCK2; - input RTCK1; - input RTCK2; - input SPI1; - input SPI2; - input SPI3; - input WRCK1; - input WRCK2; - input WTCK1; - input WTCK2; - parameter div_rx1 = 4'b0000; - parameter div_rx2 = 4'b0000; - parameter div_tx1 = 4'b0000; - parameter div_tx2 = 4'b0000; - parameter inv_di_fclk1 = 1'b0; - parameter inv_di_fclk2 = 1'b0; - parameter latency1 = 1'b0; - parameter latency2 = 1'b0; - parameter location = ""; - parameter mode_cpath = ""; - parameter mode_epath = ""; - parameter mode_io_cal = 1'b0; - parameter mode_rpath = ""; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter mode_tpath = ""; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_clkr_rx1 = 1'b0; - parameter sel_clkr_rx2 = 1'b0; - parameter sel_clkw_rx1 = 2'b00; - parameter sel_clkw_rx2 = 2'b00; -endmodule - -(* blackbox *) -module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 -, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 -, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN -, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN -, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 -, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 -, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 -, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20 -, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); - output AL1D; - output AL1T; - output AL2D; - output AL2T; - output AL3D; - output AL3T; - input ALCK1; - input ALCK2; - input ALCK3; - input CA1D1; - input CA1D2; - input CA1D3; - input CA1D4; - input CA1D5; - input CA1D6; - input CA1N1; - input CA1N2; - input CA1N3; - input CA1N4; - input CA1P1; - input CA1P2; - input CA1P3; - input CA1P4; - input CA1T1; - input CA1T2; - input CA1T3; - input CA1T4; - input CA2D1; - input CA2D2; - input CA2D3; - input CA2D4; - input CA2D5; - input CA2D6; - input CA2N1; - input CA2N2; - input CA2N3; - input CA2N4; - input CA2P1; - input CA2P2; - input CA2P3; - input CA2P4; - input CA2T1; - input CA2T2; - input CA2T3; - input CA2T4; - input CCK; - output CKO1; - output CKO2; - output DCL; - input DCRN; - input DQ1CI1; - input DQ1CI2; - input DQ1CI3; - input DQ1CI4; - input DQ1CI5; - input DQ1CI6; - input DQ1CI7; - input DQ1CI8; - input DQ2CI1; - input DQ2CI2; - input DQ2CI3; - input DQ2CI4; - input DQ2CI5; - input DQ2CI6; - input DQ2CI7; - input DQ2CI8; - input DQ3CI1; - input DQ3CI2; - input DQ3CI3; - input DQ3CI4; - input DQ3CI5; - input DQ3CI6; - input DQ3CI7; - input DQ3CI8; - input DQS1CI1; - input DQS1CI2; - input DQS1CI3; - input DQS1CI4; - input DQS1CI5; - input DQS1CI6; - input DQS1CI7; - input DQS1CI8; - input DQS2CI1; - input DQS2CI2; - input DQS2CI3; - input DQS2CI4; - input DQS2CI5; - input DQS2CI6; - input DQS2CI7; - input DQS2CI8; - input DQS3CI1; - input DQS3CI2; - input DQS3CI3; - input DQS3CI4; - input DQS3CI5; - input DQS3CI6; - input DQS3CI7; - input DQS3CI8; - input DRA1; - input DRA2; - input DRA3; - input DRA4; - input DRCCSN; - input DRDPA1CSN; - input DRDPA2CSN; - input DRDPA3CSN; - input DRE; - input DRI1; - input DRI1CSN; - input DRI2; - input DRI2CSN; - input DRI3; - input DRI3CSN; - input DRI4; - input DRI5; - input DRI6; - output DRO1; - input DRO1CSN; - output DRO2; - input DRO2CSN; - output DRO3; - input DRO3CSN; - output DRO4; - output DRO5; - output DRO6; - input DRWDS; - input DRWEN; - input FA1; - input FA2; - input FA3; - input FA4; - input FA5; - input FA6; - input FCK1; - input FCK2; - input FDCK; - output FLD; - output FLG; - input FZ; - input LD1RN; - input LD2RN; - input LD3RN; - input LDSCK1; - input LDSCK2; - input LDSCK3; - input LE; - inout [41:0] LINK1; - inout [41:0] LINK10; - inout [41:0] LINK11; - inout [41:0] LINK12; - inout [41:0] LINK13; - inout [41:0] LINK14; - inout [41:0] LINK15; - inout [41:0] LINK16; - inout [41:0] LINK17; - inout [41:0] LINK18; - inout [41:0] LINK19; - inout [41:0] LINK2; - inout [41:0] LINK20; - inout [41:0] LINK21; - inout [41:0] LINK22; - inout [41:0] LINK23; - inout [41:0] LINK24; - inout [41:0] LINK25; - inout [41:0] LINK26; - inout [41:0] LINK27; - inout [41:0] LINK28; - inout [41:0] LINK29; - inout [41:0] LINK3; - inout [41:0] LINK30; - inout [41:0] LINK31; - inout [41:0] LINK32; - inout [41:0] LINK33; - inout [41:0] LINK34; - inout [41:0] LINK4; - inout [41:0] LINK5; - inout [41:0] LINK6; - inout [41:0] LINK7; - inout [41:0] LINK8; - inout [41:0] LINK9; - input SE; - input SWRX1CK; - input SWRX2CK; - parameter cal_delay1 = ""; - parameter cal_delay2 = ""; - parameter div1 = 3'b000; - parameter div2 = 3'b000; - parameter div3 = 3'b000; - parameter div_swrx1 = 3'b000; - parameter div_swrx2 = 3'b000; - parameter inv_ld_sck1 = 1'b0; - parameter inv_ld_sck2 = 1'b0; - parameter inv_ld_sck3 = 1'b0; - parameter link_ld_12 = 1'b0; - parameter link_ld_23 = 1'b0; - parameter location = ""; - parameter mode_side1 = 0; - parameter mode_side2 = 0; - parameter mode_side3 = 0; - parameter sel_clk_out1 = 1'b0; - parameter sel_clk_out2 = 1'b0; - parameter sel_dc_clk = 2'b00; - parameter sel_ld_fck1 = 2'b00; - parameter sel_ld_fck2 = 2'b00; - parameter sel_ld_fck3 = 2'b00; - parameter sel_sw_fck1 = 2'b00; - parameter sel_sw_fck2 = 2'b00; - parameter use_dc = 1'b0; -endmodule - -(* blackbox *) -module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 -, RO2, RO3, RO4, RO5, CTO, LINK); - input CI1; - input CI2; - input CI3; - input CI4; - input CI5; - input CL; - output CO; - input CR; - input CTI; - output CTO; - input EI1; - input EI2; - input EI3; - input EI4; - input EI5; - input EL; - output EO; - input ER; - inout [41:0] LINK; - input RI; - input RL; - output RO1; - output RO2; - output RO3; - output RO4; - output RO5; - input RR; - parameter chained = 1'b0; - parameter cpath_edge = 1'b0; - parameter cpath_init = 1'b0; - parameter cpath_inv = 1'b0; - parameter cpath_load = 1'b0; - parameter cpath_mode = 4'b0000; - parameter cpath_sync = 1'b0; - parameter epath_dynamic = 1'b0; - parameter epath_edge = 1'b0; - parameter epath_init = 1'b0; - parameter epath_load = 1'b0; - parameter epath_mode = 4'b0000; - parameter epath_sync = 1'b0; - parameter location = ""; - parameter rpath_dynamic = 1'b0; - parameter rpath_edge = 1'b0; - parameter rpath_init = 1'b0; - parameter rpath_load = 1'b0; - parameter rpath_mode = 4'b0000; - parameter rpath_sync = 1'b0; - parameter symbol = ""; - parameter tpath_mode = 2'b00; - parameter variant = ""; -endmodule - -(* blackbox *) -module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 -, RO2, RO3, RO4, RO5, CTO, LINK); - input CI1; - input CI2; - input CI3; - input CI4; - input CI5; - input CL; - output CO; - input CR; - input CTI; - output CTO; - input EI1; - input EI2; - input EI3; - input EI4; - input EI5; - input EL; - output EO; - input ER; - inout [41:0] LINK; - input RI; - input RL; - output RO1; - output RO2; - output RO3; - output RO4; - output RO5; - input RR; - parameter chained = 1'b0; - parameter cpath_edge = 1'b0; - parameter cpath_init = 1'b0; - parameter cpath_inv = 1'b0; - parameter cpath_load = 1'b0; - parameter cpath_mode = 4'b0000; - parameter cpath_sync = 1'b0; - parameter epath_dynamic = 1'b0; - parameter epath_edge = 1'b0; - parameter epath_init = 1'b0; - parameter epath_load = 1'b0; - parameter epath_mode = 4'b0000; - parameter epath_sync = 1'b0; - parameter location = ""; - parameter rpath_dynamic = 1'b0; - parameter rpath_edge = 1'b0; - parameter rpath_init = 1'b0; - parameter rpath_load = 1'b0; - parameter rpath_mode = 4'b0000; - parameter rpath_sync = 1'b0; - parameter symbol = ""; - parameter tpath_mode = 2'b00; - parameter variant = ""; -endmodule - -(* blackbox *) -module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1 -, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK); - input CI1; - input CL; - output CO; - input CR; - input CTI; - output CTO; - input EI1; - input EI2; - input EI3; - input EI4; - input EI5; - input EI6; - input EI7; - input EI8; - input EL; - output EO; - input ER; - inout [41:0] LINK; - input RI; - input RL; - output RO1; - output RO2; - output RO3; - output RO4; - output RO5; - output RO6; - output RO7; - output RO8; - input RR; - parameter chained = 1'b0; - parameter cpath_edge = 1'b0; - parameter cpath_init = 1'b0; - parameter cpath_inv = 1'b0; - parameter cpath_load = 1'b0; - parameter cpath_mode = 4'b0000; - parameter cpath_sync = 1'b0; - parameter cpath_type = 1'b0; - parameter epath_dynamic = 1'b0; - parameter epath_edge = 1'b0; - parameter epath_init = 1'b0; - parameter epath_load = 1'b0; - parameter epath_mode = 4'b0000; - parameter epath_sync = 1'b0; - parameter epath_type = 1'b0; - parameter location = ""; - parameter rpath_dynamic = 1'b0; - parameter rpath_edge = 1'b0; - parameter rpath_init = 1'b0; - parameter rpath_load = 1'b0; - parameter rpath_mode = 4'b0000; - parameter rpath_sync = 1'b0; - parameter rpath_type = 1'b0; - parameter symbol = ""; - parameter tpath_mode = 1'b0; -endmodule - -(* blackbox *) -module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); - input CTCK; - input DCK; - output [5:0] DID; - input DIG; - input [5:0] DRA; - input [5:0] DRI; - input DRL; - output [5:0] DRO; - input [1:0] DS; - output FLD; - output FLG; - input FZ; - inout [41:0] LINKN; - inout [41:0] LINKP; - input RRCK; - input RRST; - input RTCK; - input TRST; - input WRCK; - input WTCK; - parameter data_size = 5; - parameter location = ""; -endmodule - -(* blackbox *) -module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); - input CTCK; - input DCK; - output [5:0] DID; - input DIG; - input [5:0] DRA; - input [5:0] DRI; - input DRL; - output [5:0] DRO; - input [1:0] DS; - output FLD; - output FLG; - input FZ; - inout [41:0] LINKN; - inout [41:0] LINKP; - input RRCK; - input RRST; - input RTCK; - input TRST; - input WRCK; - input WTCK; - parameter data_size = 5; - parameter location = ""; -endmodule - -(* blackbox *) -module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON); - output ALD; - output ALT; - output [5:0] DID; - input [3:0] DRA; - input [2:0] DRDN; - input DRE; - input [5:0] DRI; - input [2:0] DRIN; - output [5:0] DRO; - input [2:0] DRON; - input DRWDS; - input DRWEN; - input [5:0] FA; - input FCK; - output FLD; - output FLG; - input FZ; - input LDRN; - inout [41:0] LINK; - input SCK; - parameter data_size = 5; - parameter location = ""; -endmodule - //(* blackbox *) //module NX_LUT(I1, I2, I3, I4, O); // input I1; diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v index 3ed9c1a89..376e524ce 100644 --- a/techlibs/nanoxplore/cells_bb_l.v +++ b/techlibs/nanoxplore/cells_bb_l.v @@ -2001,3 +2001,156 @@ module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13 parameter rck_edge = 1'b0; parameter wck_edge = 1'b0; endmodule + +(* blackbox *) +module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19 +, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v index b3e94ac15..d0497c490 100644 --- a/techlibs/nanoxplore/cells_bb_m.v +++ b/techlibs/nanoxplore/cells_bb_m.v @@ -1288,3 +1288,240 @@ module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13 parameter wck_edge = 1'b0; endmodule + +(* blackbox *) +module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 +, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 +, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 +, RO2, RO3, RO4, RO5, CTO, LINK); + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 2'b00; + parameter variant = ""; +endmodule + +(* blackbox *) +module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); + input CTCK; + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + output FLD; + output FLG; + input FZ; + inout [41:0] LINKN; + inout [41:0] LINKP; + input RRCK; + input RRST; + input RTCK; + input TRST; + input WRCK; + input WTCK; + parameter data_size = 5; + parameter location = ""; +endmodule + diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 598eb8d2c..5c1e8bcb0 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -2578,3 +2578,364 @@ module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11 parameter use_write_arst = 1'b0; parameter wck_edge = 1'b0; endmodule + + +(* blackbox *) +module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1 +, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6 +, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN +, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN +, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1 +, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6 +, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4 +, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20 +, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output AL1D; + output AL1T; + output AL2D; + output AL2T; + output AL3D; + output AL3T; + input ALCK1; + input ALCK2; + input ALCK3; + input CA1D1; + input CA1D2; + input CA1D3; + input CA1D4; + input CA1D5; + input CA1D6; + input CA1N1; + input CA1N2; + input CA1N3; + input CA1N4; + input CA1P1; + input CA1P2; + input CA1P3; + input CA1P4; + input CA1T1; + input CA1T2; + input CA1T3; + input CA1T4; + input CA2D1; + input CA2D2; + input CA2D3; + input CA2D4; + input CA2D5; + input CA2D6; + input CA2N1; + input CA2N2; + input CA2N3; + input CA2N4; + input CA2P1; + input CA2P2; + input CA2P3; + input CA2P4; + input CA2T1; + input CA2T2; + input CA2T3; + input CA2T4; + input CCK; + output CKO1; + output CKO2; + output DCL; + input DCRN; + input DQ1CI1; + input DQ1CI2; + input DQ1CI3; + input DQ1CI4; + input DQ1CI5; + input DQ1CI6; + input DQ1CI7; + input DQ1CI8; + input DQ2CI1; + input DQ2CI2; + input DQ2CI3; + input DQ2CI4; + input DQ2CI5; + input DQ2CI6; + input DQ2CI7; + input DQ2CI8; + input DQ3CI1; + input DQ3CI2; + input DQ3CI3; + input DQ3CI4; + input DQ3CI5; + input DQ3CI6; + input DQ3CI7; + input DQ3CI8; + input DQS1CI1; + input DQS1CI2; + input DQS1CI3; + input DQS1CI4; + input DQS1CI5; + input DQS1CI6; + input DQS1CI7; + input DQS1CI8; + input DQS2CI1; + input DQS2CI2; + input DQS2CI3; + input DQS2CI4; + input DQS2CI5; + input DQS2CI6; + input DQS2CI7; + input DQS2CI8; + input DQS3CI1; + input DQS3CI2; + input DQS3CI3; + input DQS3CI4; + input DQS3CI5; + input DQS3CI6; + input DQS3CI7; + input DQS3CI8; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRCCSN; + input DRDPA1CSN; + input DRDPA2CSN; + input DRDPA3CSN; + input DRE; + input DRI1; + input DRI1CSN; + input DRI2; + input DRI2CSN; + input DRI3; + input DRI3CSN; + input DRI4; + input DRI5; + input DRI6; + output DRO1; + input DRO1CSN; + output DRO2; + input DRO2CSN; + output DRO3; + input DRO3CSN; + output DRO4; + output DRO5; + output DRO6; + input DRWDS; + input DRWEN; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + input FCK1; + input FCK2; + input FDCK; + output FLD; + output FLG; + input FZ; + input LD1RN; + input LD2RN; + input LD3RN; + input LDSCK1; + input LDSCK2; + input LDSCK3; + input LE; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input SE; + input SWRX1CK; + input SWRX2CK; + parameter cal_delay1 = ""; + parameter cal_delay2 = ""; + parameter div1 = 3'b000; + parameter div2 = 3'b000; + parameter div3 = 3'b000; + parameter div_swrx1 = 3'b000; + parameter div_swrx2 = 3'b000; + parameter inv_ld_sck1 = 1'b0; + parameter inv_ld_sck2 = 1'b0; + parameter inv_ld_sck3 = 1'b0; + parameter link_ld_12 = 1'b0; + parameter link_ld_23 = 1'b0; + parameter location = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_side3 = 0; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_dc_clk = 2'b00; + parameter sel_ld_fck1 = 2'b00; + parameter sel_ld_fck2 = 2'b00; + parameter sel_ld_fck3 = 2'b00; + parameter sel_sw_fck1 = 2'b00; + parameter sel_sw_fck2 = 2'b00; + parameter use_dc = 1'b0; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 +, RO2, RO3, RO4, RO5, CTO, LINK); + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 2'b00; + parameter variant = ""; +endmodule + +(* blackbox *) +module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1 +, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK); + input CI1; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EI6; + input EI7; + input EI8; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + output RO6; + output RO7; + output RO8; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter cpath_type = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter epath_type = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter rpath_type = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 1'b0; +endmodule + +(* blackbox *) +module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON); + output ALD; + output ALT; + output [5:0] DID; + input [3:0] DRA; + input [2:0] DRDN; + input DRE; + input [5:0] DRI; + input [2:0] DRIN; + output [5:0] DRO; + input [2:0] DRON; + input DRWDS; + input DRWEN; + input [5:0] FA; + input FCK; + output FLD; + output FLG; + input FZ; + input LDRN; + inout [41:0] LINK; + input SCK; + parameter data_size = 5; + parameter location = ""; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v index d86b4518b..5bfdd4d13 100644 --- a/techlibs/nanoxplore/cells_wrap_l.v +++ b/techlibs/nanoxplore/cells_wrap_l.v @@ -1401,7 +1401,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, ); endmodule -// TODO +//TODO module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z); input [23:0] A; input [31:0] B; @@ -1411,3 +1411,303 @@ module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z); input we; endmodule +//TODO +module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o +, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o +, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o +, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o +, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o +, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o +, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i +, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i +, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o +, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o +, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o +, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o +, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i); + input hssl_clk_ref_i; + input hssl_clk_user_i; + output hssl_clock_o; + input pma_clk_ext_i; + input pma_rx0_i; + input pma_rx1_i; + input pma_rx2_i; + input pma_rx3_i; + input pma_rx4_i; + input pma_rx5_i; + output pma_tx0_o; + output pma_tx1_o; + output pma_tx2_o; + output pma_tx3_o; + output pma_tx4_o; + output pma_tx5_o; + input usr_calibrate_pma_en_i; + output usr_calibrate_pma_out_o; + input [7:0] usr_calibrate_pma_res_n2_i; + input [7:0] usr_calibrate_pma_res_n3_i; + input [7:0] usr_calibrate_pma_res_p1_i; + input [7:0] usr_calibrate_pma_res_p4_i; + input [3:0] usr_calibrate_pma_sel_i; + input [5:0] usr_com_ctrl_rx_sel_i; + input [5:0] usr_com_ctrl_tx_sel_i; + input [3:0] usr_com_rx_pma_ctle_cap_i; + input [3:0] usr_com_rx_pma_ctle_resn_i; + input [3:0] usr_com_rx_pma_ctle_resp_i; + input usr_com_rx_pma_m_eye_i; + input [5:0] usr_com_tx_pma_main_en_i; + input usr_com_tx_pma_main_sign_i; + input [3:0] usr_com_tx_pma_margin_input_sel_i; + input [4:0] usr_com_tx_pma_margin_input_sel_var_i; + input [3:0] usr_com_tx_pma_margin_sel_i; + input [4:0] usr_com_tx_pma_margin_sel_var_i; + input [4:0] usr_com_tx_pma_post_en_i; + input [3:0] usr_com_tx_pma_post_input_sel_i; + input [3:0] usr_com_tx_pma_post_input_sel_var_i; + input usr_com_tx_pma_post_sign_i; + input usr_com_tx_pma_pre_en_i; + input [3:0] usr_com_tx_pma_pre_input_sel_i; + input usr_com_tx_pma_pre_sign_i; + input usr_main_rst_n_i; + input [7:0] usr_main_test_i; + output [7:0] usr_main_test_o; + input usr_pcs_ctrl_ovs_en_i; + input usr_pcs_ctrl_pll_lock_en_i; + output usr_pll_lock_o; + input usr_pll_pma_rst_n_i; + output usr_rx0_busy_o; + input usr_rx0_ctrl_align_en_i; + input usr_rx0_ctrl_align_sync_i; + output [7:0] usr_rx0_ctrl_char_is_a_o; + output usr_rx0_ctrl_char_is_aligned_o; + output [7:0] usr_rx0_ctrl_char_is_comma_o; + output [7:0] usr_rx0_ctrl_char_is_f_o; + output [7:0] usr_rx0_ctrl_char_is_k_o; + input usr_rx0_ctrl_dec_en_i; + output [7:0] usr_rx0_ctrl_disp_err_o; + input usr_rx0_ctrl_dscr_en_i; + input usr_rx0_ctrl_el_buff_fifo_en_i; + input usr_rx0_ctrl_el_buff_rst_i; + output [7:0] usr_rx0_ctrl_not_in_table_o; + input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; + input usr_rx0_ctrl_replace_en_i; + output [63:0] usr_rx0_data_o; + output usr_rx0_pll_lock_o; + input usr_rx0_pma_cdr_rst_i; + input usr_rx0_pma_ckgen_rst_n_i; + output usr_rx0_pma_loss_of_signal_o; + input usr_rx0_pma_pll_rst_n_i; + input usr_rx0_rst_n_i; + input [3:0] usr_rx0_test_i; + output [7:0] usr_rx0_test_o; + output usr_rx1_busy_o; + input usr_rx1_ctrl_align_en_i; + input usr_rx1_ctrl_align_sync_i; + output [7:0] usr_rx1_ctrl_char_is_a_o; + output usr_rx1_ctrl_char_is_aligned_o; + output [7:0] usr_rx1_ctrl_char_is_comma_o; + output [7:0] usr_rx1_ctrl_char_is_f_o; + output [7:0] usr_rx1_ctrl_char_is_k_o; + input usr_rx1_ctrl_dec_en_i; + output [7:0] usr_rx1_ctrl_disp_err_o; + input usr_rx1_ctrl_dscr_en_i; + input usr_rx1_ctrl_el_buff_fifo_en_i; + input usr_rx1_ctrl_el_buff_rst_i; + output [7:0] usr_rx1_ctrl_not_in_table_o; + input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; + input usr_rx1_ctrl_replace_en_i; + output [63:0] usr_rx1_data_o; + output usr_rx1_pll_lock_o; + input usr_rx1_pma_cdr_rst_i; + input usr_rx1_pma_ckgen_rst_n_i; + output usr_rx1_pma_loss_of_signal_o; + input usr_rx1_pma_pll_rst_n_i; + input usr_rx1_rst_n_i; + input [3:0] usr_rx1_test_i; + output [7:0] usr_rx1_test_o; + output usr_rx2_busy_o; + input usr_rx2_ctrl_align_en_i; + input usr_rx2_ctrl_align_sync_i; + output [7:0] usr_rx2_ctrl_char_is_a_o; + output usr_rx2_ctrl_char_is_aligned_o; + output [7:0] usr_rx2_ctrl_char_is_comma_o; + output [7:0] usr_rx2_ctrl_char_is_f_o; + output [7:0] usr_rx2_ctrl_char_is_k_o; + input usr_rx2_ctrl_dec_en_i; + output [7:0] usr_rx2_ctrl_disp_err_o; + input usr_rx2_ctrl_dscr_en_i; + input usr_rx2_ctrl_el_buff_fifo_en_i; + input usr_rx2_ctrl_el_buff_rst_i; + output [7:0] usr_rx2_ctrl_not_in_table_o; + input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; + input usr_rx2_ctrl_replace_en_i; + output [63:0] usr_rx2_data_o; + output usr_rx2_pll_lock_o; + input usr_rx2_pma_cdr_rst_i; + input usr_rx2_pma_ckgen_rst_n_i; + output usr_rx2_pma_loss_of_signal_o; + input usr_rx2_pma_pll_rst_n_i; + input usr_rx2_rst_n_i; + input [3:0] usr_rx2_test_i; + output [7:0] usr_rx2_test_o; + output usr_rx3_busy_o; + input usr_rx3_ctrl_align_en_i; + input usr_rx3_ctrl_align_sync_i; + output [7:0] usr_rx3_ctrl_char_is_a_o; + output usr_rx3_ctrl_char_is_aligned_o; + output [7:0] usr_rx3_ctrl_char_is_comma_o; + output [7:0] usr_rx3_ctrl_char_is_f_o; + output [7:0] usr_rx3_ctrl_char_is_k_o; + input usr_rx3_ctrl_dec_en_i; + output [7:0] usr_rx3_ctrl_disp_err_o; + input usr_rx3_ctrl_dscr_en_i; + input usr_rx3_ctrl_el_buff_fifo_en_i; + input usr_rx3_ctrl_el_buff_rst_i; + output [7:0] usr_rx3_ctrl_not_in_table_o; + input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; + input usr_rx3_ctrl_replace_en_i; + output [63:0] usr_rx3_data_o; + output usr_rx3_pll_lock_o; + input usr_rx3_pma_cdr_rst_i; + input usr_rx3_pma_ckgen_rst_n_i; + output usr_rx3_pma_loss_of_signal_o; + input usr_rx3_pma_pll_rst_n_i; + input usr_rx3_rst_n_i; + input [3:0] usr_rx3_test_i; + output [7:0] usr_rx3_test_o; + output usr_rx4_busy_o; + input usr_rx4_ctrl_align_en_i; + input usr_rx4_ctrl_align_sync_i; + output [7:0] usr_rx4_ctrl_char_is_a_o; + output usr_rx4_ctrl_char_is_aligned_o; + output [7:0] usr_rx4_ctrl_char_is_comma_o; + output [7:0] usr_rx4_ctrl_char_is_f_o; + output [7:0] usr_rx4_ctrl_char_is_k_o; + input usr_rx4_ctrl_dec_en_i; + output [7:0] usr_rx4_ctrl_disp_err_o; + input usr_rx4_ctrl_dscr_en_i; + input usr_rx4_ctrl_el_buff_fifo_en_i; + input usr_rx4_ctrl_el_buff_rst_i; + output [7:0] usr_rx4_ctrl_not_in_table_o; + input [1:0] usr_rx4_ctrl_ovs_bit_sel_i; + input usr_rx4_ctrl_replace_en_i; + output [63:0] usr_rx4_data_o; + output usr_rx4_pll_lock_o; + input usr_rx4_pma_cdr_rst_i; + input usr_rx4_pma_ckgen_rst_n_i; + output usr_rx4_pma_loss_of_signal_o; + input usr_rx4_pma_pll_rst_n_i; + input usr_rx4_rst_n_i; + input [3:0] usr_rx4_test_i; + output [7:0] usr_rx4_test_o; + output usr_rx5_busy_o; + input usr_rx5_ctrl_align_en_i; + input usr_rx5_ctrl_align_sync_i; + output [7:0] usr_rx5_ctrl_char_is_a_o; + output usr_rx5_ctrl_char_is_aligned_o; + output [7:0] usr_rx5_ctrl_char_is_comma_o; + output [7:0] usr_rx5_ctrl_char_is_f_o; + output [7:0] usr_rx5_ctrl_char_is_k_o; + input usr_rx5_ctrl_dec_en_i; + output [7:0] usr_rx5_ctrl_disp_err_o; + input usr_rx5_ctrl_dscr_en_i; + input usr_rx5_ctrl_el_buff_fifo_en_i; + input usr_rx5_ctrl_el_buff_rst_i; + output [7:0] usr_rx5_ctrl_not_in_table_o; + input [1:0] usr_rx5_ctrl_ovs_bit_sel_i; + input usr_rx5_ctrl_replace_en_i; + output [63:0] usr_rx5_data_o; + output usr_rx5_pll_lock_o; + input usr_rx5_pma_cdr_rst_i; + input usr_rx5_pma_ckgen_rst_n_i; + output usr_rx5_pma_loss_of_signal_o; + input usr_rx5_pma_pll_rst_n_i; + input usr_rx5_rst_n_i; + input [3:0] usr_rx5_test_i; + output [7:0] usr_rx5_test_o; + output usr_tx0_busy_o; + input [7:0] usr_tx0_ctrl_char_is_k_i; + input [7:0] usr_tx0_ctrl_enc_en_i; + input [7:0] usr_tx0_ctrl_end_of_frame_i; + input [7:0] usr_tx0_ctrl_end_of_multiframe_i; + input usr_tx0_ctrl_replace_en_i; + input [7:0] usr_tx0_ctrl_scr_en_i; + input [63:0] usr_tx0_data_i; + input usr_tx0_pma_clk_en_i; + input usr_tx0_rst_n_i; + input [3:0] usr_tx0_test_i; + output [3:0] usr_tx0_test_o; + output usr_tx1_busy_o; + input [7:0] usr_tx1_ctrl_char_is_k_i; + input [7:0] usr_tx1_ctrl_enc_en_i; + input [7:0] usr_tx1_ctrl_end_of_frame_i; + input [7:0] usr_tx1_ctrl_end_of_multiframe_i; + input usr_tx1_ctrl_replace_en_i; + input [7:0] usr_tx1_ctrl_scr_en_i; + input [63:0] usr_tx1_data_i; + input usr_tx1_pma_clk_en_i; + input usr_tx1_rst_n_i; + input [3:0] usr_tx1_test_i; + output [3:0] usr_tx1_test_o; + output usr_tx2_busy_o; + input [7:0] usr_tx2_ctrl_char_is_k_i; + input [7:0] usr_tx2_ctrl_enc_en_i; + input [7:0] usr_tx2_ctrl_end_of_frame_i; + input [7:0] usr_tx2_ctrl_end_of_multiframe_i; + input usr_tx2_ctrl_replace_en_i; + input [7:0] usr_tx2_ctrl_scr_en_i; + input [63:0] usr_tx2_data_i; + input usr_tx2_pma_clk_en_i; + input usr_tx2_rst_n_i; + input [3:0] usr_tx2_test_i; + output [3:0] usr_tx2_test_o; + output usr_tx3_busy_o; + input [7:0] usr_tx3_ctrl_char_is_k_i; + input [7:0] usr_tx3_ctrl_enc_en_i; + input [7:0] usr_tx3_ctrl_end_of_frame_i; + input [7:0] usr_tx3_ctrl_end_of_multiframe_i; + input usr_tx3_ctrl_replace_en_i; + input [7:0] usr_tx3_ctrl_scr_en_i; + input [63:0] usr_tx3_data_i; + input usr_tx3_pma_clk_en_i; + input usr_tx3_rst_n_i; + input [3:0] usr_tx3_test_i; + output [3:0] usr_tx3_test_o; + output usr_tx4_busy_o; + input [7:0] usr_tx4_ctrl_char_is_k_i; + input [7:0] usr_tx4_ctrl_enc_en_i; + input [7:0] usr_tx4_ctrl_end_of_frame_i; + input [7:0] usr_tx4_ctrl_end_of_multiframe_i; + input usr_tx4_ctrl_replace_en_i; + input [7:0] usr_tx4_ctrl_scr_en_i; + input [63:0] usr_tx4_data_i; + input usr_tx4_pma_clk_en_i; + input usr_tx4_rst_n_i; + input [3:0] usr_tx4_test_i; + output [3:0] usr_tx4_test_o; + output usr_tx5_busy_o; + input [7:0] usr_tx5_ctrl_char_is_k_i; + input [7:0] usr_tx5_ctrl_enc_en_i; + input [7:0] usr_tx5_ctrl_end_of_frame_i; + input [7:0] usr_tx5_ctrl_end_of_multiframe_i; + input usr_tx5_ctrl_replace_en_i; + input [7:0] usr_tx5_ctrl_scr_en_i; + input [63:0] usr_tx5_data_i; + input usr_tx5_pma_clk_en_i; + input usr_tx5_rst_n_i; + input [3:0] usr_tx5_test_i; + output [3:0] usr_tx5_test_o; + parameter cfg_main_i = 34'b0000000000000000000000000000000000; + parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter cfg_tx0_i = 0; + parameter cfg_tx1_i = 0; + parameter cfg_tx2_i = 0; + parameter cfg_tx3_i = 0; + parameter cfg_tx4_i = 0; + parameter cfg_tx5_i = 0; + parameter location = ""; +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v index 0bf3a9050..ff4c011c7 100644 --- a/techlibs/nanoxplore/cells_wrap_m.v +++ b/techlibs/nanoxplore/cells_wrap_m.v @@ -1035,4 +1035,467 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .WA6(WA6), .WE(WE) ); -endmodule \ No newline at end of file +endmodule + +module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3 +, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3 +, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1 +, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1 +, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16 +, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1); + output C1RED; + input C1RNE; + input C1RS; + input C1RW1; + input C1RW2; + input C1RW3; + input C1TS; + input C1TW; + output C2RED; + input C2RNE; + input C2RS; + input C2RW1; + input C2RW2; + input C2RW3; + input C2TS; + input C2TW; + input CAD1; + input CAD2; + input CAD3; + input CAD4; + input CAD5; + input CAD6; + output CAL; + input CAN1; + input CAN2; + input CAN3; + input CAN4; + input CAP1; + input CAP2; + input CAP3; + input CAP4; + input CAT1; + input CAT2; + input CAT3; + input CAT4; + input CCK; + output CKO1; + output CKO2; + input CTCK; + input DC; + input DCK; + input DIG; + input DIS; + input DOG; + input DOS; + input DPAG; + input DPAS; + input DQSG; + input DQSS; + input DRA1; + input DRA2; + input DRA3; + input DRA4; + input DRA5; + input DRA6; + input DRI1; + input DRI2; + input DRI3; + input DRI4; + input DRI5; + input DRI6; + input DRL; + output DRO1; + output DRO2; + output DRO3; + output DRO4; + output DRO5; + output DRO6; + input DS1; + input DS2; + input FA1; + input FA2; + input FA3; + input FA4; + input FA5; + input FA6; + output FLD; + output FLG; + input FZ; + inout [41:0] LINK1; + inout [41:0] LINK10; + inout [41:0] LINK11; + inout [41:0] LINK12; + inout [41:0] LINK13; + inout [41:0] LINK14; + inout [41:0] LINK15; + inout [41:0] LINK16; + inout [41:0] LINK17; + inout [41:0] LINK18; + inout [41:0] LINK19; + inout [41:0] LINK2; + inout [41:0] LINK20; + inout [41:0] LINK21; + inout [41:0] LINK22; + inout [41:0] LINK23; + inout [41:0] LINK24; + inout [41:0] LINK25; + inout [41:0] LINK26; + inout [41:0] LINK27; + inout [41:0] LINK28; + inout [41:0] LINK29; + inout [41:0] LINK3; + inout [41:0] LINK30; + inout [41:0] LINK31; + inout [41:0] LINK32; + inout [41:0] LINK33; + inout [41:0] LINK34; + inout [41:0] LINK4; + inout [41:0] LINK5; + inout [41:0] LINK6; + inout [41:0] LINK7; + inout [41:0] LINK8; + inout [41:0] LINK9; + input RRCK1; + input RRCK2; + input RTCK1; + input RTCK2; + input SPI1; + input SPI2; + input SPI3; + input WRCK1; + input WRCK2; + input WTCK1; + input WTCK2; + parameter div_rx1 = 4'b0000; + parameter div_rx2 = 4'b0000; + parameter div_tx1 = 4'b0000; + parameter div_tx2 = 4'b0000; + parameter inv_di_fclk1 = 1'b0; + parameter inv_di_fclk2 = 1'b0; + parameter latency1 = 1'b0; + parameter latency2 = 1'b0; + parameter location = ""; + parameter mode_cpath = ""; + parameter mode_epath = ""; + parameter mode_io_cal = 1'b0; + parameter mode_rpath = ""; + parameter mode_side1 = 0; + parameter mode_side2 = 0; + parameter mode_tpath = ""; + parameter sel_clk_out1 = 1'b0; + parameter sel_clk_out2 = 1'b0; + parameter sel_clkr_rx1 = 1'b0; + parameter sel_clkr_rx2 = 1'b0; + parameter sel_clkw_rx1 = 2'b00; + parameter sel_clkw_rx2 = 2'b00; + + NX_IOM_CONTROL_M #( + .div_rx1(div_rx1), + .div_rx2(div_rx2), + .div_tx1(div_tx1), + .div_tx2(div_tx2), + .inv_di_fclk1(inv_di_fclk1), + .inv_di_fclk2(inv_di_fclk2), + .latency1(latency1), + .latency2(latency2), + .location(location), + .mode_cpath(mode_cpath), + .mode_epath(mode_epath), + .mode_io_cal(mode_io_cal), + .mode_rpath(mode_rpath), + .mode_side1(mode_side1), + .mode_side2(mode_side2), + .mode_tpath(mode_tpath), + .sel_clk_out1(sel_clk_out1), + .sel_clk_out2(sel_clk_out2), + .sel_clkr_rx1(sel_clkr_rx1), + .sel_clkr_rx2(sel_clkr_rx2), + .sel_clkw_rx1(sel_clkw_rx1), + .sel_clkw_rx2(sel_clkw_rx2) + ) _TECHMAP_REPLACE_ ( + .C1RED(C1RED), + .C1RNE(C1RNE), + .C1RS(C1RS), + .C1RW1(C1RW1), + .C1RW2(C1RW2), + .C1RW3(C1RW3), + .C1TS(C1TS), + .C1TW(C1TW), + .C2RED(C2RED), + .C2RNE(C2RNE), + .C2RS(C2RS), + .C2RW1(C2RW1), + .C2RW2(C2RW2), + .C2RW3(C2RW3), + .C2TS(C2TS), + .C2TW(C2TW), + .CAD1(CAD1), + .CAD2(CAD2), + .CAD3(CAD3), + .CAD4(CAD4), + .CAD5(CAD5), + .CAD6(CAD6), + .CAL(CAL), + .CAN1(CAN1), + .CAN2(CAN2), + .CAN3(CAN3), + .CAN4(CAN4), + .CAP1(CAP1), + .CAP2(CAP2), + .CAP3(CAP3), + .CAP4(CAP4), + .CAT1(CAT1), + .CAT2(CAT2), + .CAT3(CAT3), + .CAT4(CAT4), + .CCK(CCK), + .CKO1(CKO1), + .CKO2(CKO2), + .CTCK(CTCK), + .DC(DC), + .DCK(DCK), + .DIG(DIG), + .DIS(DIS), + .DOG(DOG), + .DOS(DOS), + .DPAG(DPAG), + .DPAS(DPAS), + .DQSG(DQSG), + .DQSS(DQSS), + .DRA1(DRA1), + .DRA2(DRA2), + .DRA3(DRA3), + .DRA4(DRA4), + .DRA5(DRA5), + .DRA6(DRA6), + .DRI1(DRI1), + .DRI2(DRI2), + .DRI3(DRI3), + .DRI4(DRI4), + .DRI5(DRI5), + .DRI6(DRI6), + .DRL(DRL), + .DRO1(DRO1), + .DRO2(DRO2), + .DRO3(DRO3), + .DRO4(DRO4), + .DRO5(DRO5), + .DRO6(DRO6), + .DS1(DS1), + .DS2(DS2), + .FA1(FA1), + .FA2(FA2), + .FA3(FA3), + .FA4(FA4), + .FA5(FA5), + .FA6(FA6), + .FLD(FLD), + .FLG(FLG), + .FZ(FZ), + .LINK1(LINK1), + .LINK10(LINK10), + .LINK11(LINK11), + .LINK12(LINK12), + .LINK13(LINK13), + .LINK14(LINK14), + .LINK15(LINK15), + .LINK16(LINK16), + .LINK17(LINK17), + .LINK18(LINK18), + .LINK19(LINK19), + .LINK2(LINK2), + .LINK20(LINK20), + .LINK21(LINK21), + .LINK22(LINK22), + .LINK23(LINK23), + .LINK24(LINK24), + .LINK25(LINK25), + .LINK26(LINK26), + .LINK27(LINK27), + .LINK28(LINK28), + .LINK29(LINK29), + .LINK3(LINK3), + .LINK30(LINK30), + .LINK31(LINK31), + .LINK32(LINK32), + .LINK33(LINK33), + .LINK34(LINK34), + .LINK4(LINK4), + .LINK5(LINK5), + .LINK6(LINK6), + .LINK7(LINK7), + .LINK8(LINK8), + .LINK9(LINK9), + .RRCK1(RRCK1), + .RRCK2(RRCK2), + .RTCK1(RTCK1), + .RTCK2(RTCK2), + .SPI1(SPI1), + .SPI2(SPI2), + .SPI3(SPI3), + .WRCK1(WRCK1), + .WRCK2(WRCK2), + .WTCK1(WTCK1), + .WTCK2(WTCK2) + ); +endmodule + +module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1 +, RO2, RO3, RO4, RO5, CTO, LINK); + input CI1; + input CI2; + input CI3; + input CI4; + input CI5; + input CL; + output CO; + input CR; + input CTI; + output CTO; + input EI1; + input EI2; + input EI3; + input EI4; + input EI5; + input EL; + output EO; + input ER; + inout [41:0] LINK; + input RI; + input RL; + output RO1; + output RO2; + output RO3; + output RO4; + output RO5; + input RR; + parameter chained = 1'b0; + parameter cpath_edge = 1'b0; + parameter cpath_init = 1'b0; + parameter cpath_inv = 1'b0; + parameter cpath_load = 1'b0; + parameter cpath_mode = 4'b0000; + parameter cpath_sync = 1'b0; + parameter epath_dynamic = 1'b0; + parameter epath_edge = 1'b0; + parameter epath_init = 1'b0; + parameter epath_load = 1'b0; + parameter epath_mode = 4'b0000; + parameter epath_sync = 1'b0; + parameter location = ""; + parameter rpath_dynamic = 1'b0; + parameter rpath_edge = 1'b0; + parameter rpath_init = 1'b0; + parameter rpath_load = 1'b0; + parameter rpath_mode = 4'b0000; + parameter rpath_sync = 1'b0; + parameter symbol = ""; + parameter tpath_mode = 2'b00; + parameter variant = ""; + + NX_IOM_DRIVER_M #( + .chained(chained), + .cpath_edge(cpath_edge), + .cpath_init(cpath_init), + .cpath_inv(cpath_inv), + .cpath_load(cpath_load), + .cpath_mode(cpath_mode), + .cpath_sync(cpath_sync), + .epath_dynamic(epath_dynamic), + .epath_edge(epath_edge), + .epath_init(epath_init), + .epath_load(epath_load), + .epath_mode(epath_mode), + .epath_sync(epath_sync), + .location(location), + .rpath_dynamic(rpath_dynamic), + .rpath_edge(rpath_edge), + .rpath_init(rpath_init), + .rpath_load(rpath_load), + .rpath_mode(rpath_mode), + .rpath_sync(rpath_sync), + .symbol(symbol), + .tpath_mode(tpath_mode), + .variant(variant) + ) _TECHMAP_REPLACE_ ( + .CI1(CI1), + .CI2(CI2), + .CI3(CI3), + .CI4(CI4), + .CI5(CI5), + .CL(CL), + .CO(CO), + .CR(CR), + .CTI(CTI), + .CTO(CTO), + .EI1(EI1), + .EI2(EI2), + .EI3(EI3), + .EI4(EI4), + .EI5(EI5), + .EL(EL), + .EO(EO), + .ER(ER), + .LINK(LINK), + .RI(RI), + .RL(RL), + .RO1(RO1), + .RO2(RO2), + .RO3(RO3), + .RO4(RO4), + .RO5(RO5), + .RR(RR) + ); +endmodule + +module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP); + input CTCK; + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + output FLD; + output FLG; + input FZ; + inout [41:0] LINKN; + inout [41:0] LINKP; + input RRCK; + input RRST; + input RTCK; + input TRST; + input WRCK; + input WTCK; + parameter data_size = 5; + parameter location = ""; + + NX_IOM_SERDES_M #( + .data_size(data_size), + .location(location) + ) _TECHMAP_REPLACE_ ( + .CTCK(CTCK), + .DCK(DCK), + .DID(DID), + .DIG(DIG), + .DRA(DRA), + .DRI(DRI), + .DRL(DRL), + .DRO(DRO), + .DS(DS), + .FLD(FLD), + .FLG(FLG), + .FZ(FZ), + .LINKN(LINKN), + .LINKP(LINKP), + .RRCK(RRCK), + .RRST(RRST), + .RTCK(RTCK), + .TRST(TRST), + .WRCK(WRCK), + .WTCK(WTCK) + ); +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index f5623dfeb..b753c5466 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -2704,3 +2704,605 @@ module UMUL48x36_4DSP(clk, rst, A, B, Z); input rst; parameter piped = "true"; endmodule + +//TODO +module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i +, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o +, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o +, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i +, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i +, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o +, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o +, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i +, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i +, usr_dyn_cfg_lane_cs_n_i); + input hssl_clk_ref_i; + input hssl_clk_user_rx_i; + input hssl_clk_user_tx_i; + output hssl_clock_o; + output hssl_rclock_o; + input scan_en_i; + input [7:0] scan_in_i; + output [7:0] scan_out_o; + output usr_calibrate_pma_out_o; + input [3:0] usr_dyn_cfg_addr_i; + input usr_dyn_cfg_calibration_cs_n_i; + input usr_dyn_cfg_en_i; + input [3:0] usr_dyn_cfg_lane_cs_n_i; + input [11:0] usr_dyn_cfg_wdata_i; + input usr_dyn_cfg_wdata_sel_i; + input usr_dyn_cfg_we_n_i; + input usr_main_async_debug_ack_i; + input [1:0] usr_main_async_debug_lane_sel_i; + output usr_main_async_debug_req_o; + input usr_main_rst_n_i; + output [19:0] usr_main_rx_pma_ll_out_o; + output usr_pll_ckfb_lock_o; + output usr_pll_lock_o; + output usr_pll_pma_lock_analog_o; + input usr_pll_pma_pwr_down_n_i; + input usr_pll_pma_rst_n_i; + output usr_rx0_busy_o; + input usr_rx0_ctrl_align_en_i; + input usr_rx0_ctrl_align_sync_i; + output [7:0] usr_rx0_ctrl_char_is_a_o; + output usr_rx0_ctrl_char_is_aligned_o; + output [7:0] usr_rx0_ctrl_char_is_comma_o; + output [7:0] usr_rx0_ctrl_char_is_f_o; + output [7:0] usr_rx0_ctrl_char_is_k_o; + input [2:0] usr_rx0_ctrl_debug_sel_i; + input usr_rx0_ctrl_dec_en_i; + output [7:0] usr_rx0_ctrl_disp_err_o; + input usr_rx0_ctrl_dscr_en_i; + input usr_rx0_ctrl_el_buff_rst_i; + output [7:0] usr_rx0_ctrl_not_in_table_o; + input [1:0] usr_rx0_ctrl_ovs_bit_sel_i; + input usr_rx0_ctrl_replace_en_i; + output usr_rx0_ctrl_valid_realign_o; + output [63:0] usr_rx0_data_o; + output usr_rx0_pma_ll_fast_locked_o; + output usr_rx0_pma_ll_slow_locked_o; + output usr_rx0_pma_loss_of_signal_o; + input usr_rx0_pma_m_eye_rst_i; + output usr_rx0_pma_pll_lock_o; + output usr_rx0_pma_pll_lock_track_o; + input usr_rx0_pma_pwr_down_n_i; + input usr_rx0_pma_rst_n_i; + input usr_rx0_rst_n_i; + output [7:0] usr_rx0_test_o; + output usr_rx1_busy_o; + input usr_rx1_ctrl_align_en_i; + input usr_rx1_ctrl_align_sync_i; + output [7:0] usr_rx1_ctrl_char_is_a_o; + output usr_rx1_ctrl_char_is_aligned_o; + output [7:0] usr_rx1_ctrl_char_is_comma_o; + output [7:0] usr_rx1_ctrl_char_is_f_o; + output [7:0] usr_rx1_ctrl_char_is_k_o; + input [2:0] usr_rx1_ctrl_debug_sel_i; + input usr_rx1_ctrl_dec_en_i; + output [7:0] usr_rx1_ctrl_disp_err_o; + input usr_rx1_ctrl_dscr_en_i; + input usr_rx1_ctrl_el_buff_rst_i; + output [7:0] usr_rx1_ctrl_not_in_table_o; + input [1:0] usr_rx1_ctrl_ovs_bit_sel_i; + input usr_rx1_ctrl_replace_en_i; + output usr_rx1_ctrl_valid_realign_o; + output [63:0] usr_rx1_data_o; + output usr_rx1_pma_ll_fast_locked_o; + output usr_rx1_pma_ll_slow_locked_o; + output usr_rx1_pma_loss_of_signal_o; + input usr_rx1_pma_m_eye_rst_i; + output usr_rx1_pma_pll_lock_o; + output usr_rx1_pma_pll_lock_track_o; + input usr_rx1_pma_pwr_down_n_i; + input usr_rx1_pma_rst_n_i; + input usr_rx1_rst_n_i; + output [7:0] usr_rx1_test_o; + output usr_rx2_busy_o; + input usr_rx2_ctrl_align_en_i; + input usr_rx2_ctrl_align_sync_i; + output [7:0] usr_rx2_ctrl_char_is_a_o; + output usr_rx2_ctrl_char_is_aligned_o; + output [7:0] usr_rx2_ctrl_char_is_comma_o; + output [7:0] usr_rx2_ctrl_char_is_f_o; + output [7:0] usr_rx2_ctrl_char_is_k_o; + input [2:0] usr_rx2_ctrl_debug_sel_i; + input usr_rx2_ctrl_dec_en_i; + output [7:0] usr_rx2_ctrl_disp_err_o; + input usr_rx2_ctrl_dscr_en_i; + input usr_rx2_ctrl_el_buff_rst_i; + output [7:0] usr_rx2_ctrl_not_in_table_o; + input [1:0] usr_rx2_ctrl_ovs_bit_sel_i; + input usr_rx2_ctrl_replace_en_i; + output usr_rx2_ctrl_valid_realign_o; + output [63:0] usr_rx2_data_o; + output usr_rx2_pma_ll_fast_locked_o; + output usr_rx2_pma_ll_slow_locked_o; + output usr_rx2_pma_loss_of_signal_o; + input usr_rx2_pma_m_eye_rst_i; + output usr_rx2_pma_pll_lock_o; + output usr_rx2_pma_pll_lock_track_o; + input usr_rx2_pma_pwr_down_n_i; + input usr_rx2_pma_rst_n_i; + input usr_rx2_rst_n_i; + output [7:0] usr_rx2_test_o; + output usr_rx3_busy_o; + input usr_rx3_ctrl_align_en_i; + input usr_rx3_ctrl_align_sync_i; + output [7:0] usr_rx3_ctrl_char_is_a_o; + output usr_rx3_ctrl_char_is_aligned_o; + output [7:0] usr_rx3_ctrl_char_is_comma_o; + output [7:0] usr_rx3_ctrl_char_is_f_o; + output [7:0] usr_rx3_ctrl_char_is_k_o; + input [2:0] usr_rx3_ctrl_debug_sel_i; + input usr_rx3_ctrl_dec_en_i; + output [7:0] usr_rx3_ctrl_disp_err_o; + input usr_rx3_ctrl_dscr_en_i; + input usr_rx3_ctrl_el_buff_rst_i; + output [7:0] usr_rx3_ctrl_not_in_table_o; + input [1:0] usr_rx3_ctrl_ovs_bit_sel_i; + input usr_rx3_ctrl_replace_en_i; + output usr_rx3_ctrl_valid_realign_o; + output [63:0] usr_rx3_data_o; + output usr_rx3_pma_ll_fast_locked_o; + output usr_rx3_pma_ll_slow_locked_o; + output usr_rx3_pma_loss_of_signal_o; + input usr_rx3_pma_m_eye_rst_i; + output usr_rx3_pma_pll_lock_o; + output usr_rx3_pma_pll_lock_track_o; + input usr_rx3_pma_pwr_down_n_i; + input usr_rx3_pma_rst_n_i; + input usr_rx3_rst_n_i; + output [7:0] usr_rx3_test_o; + output usr_tx0_busy_o; + input [7:0] usr_tx0_ctrl_char_is_k_i; + input usr_tx0_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx0_ctrl_enc_en_i; + input [7:0] usr_tx0_ctrl_end_of_frame_i; + input [7:0] usr_tx0_ctrl_end_of_multiframe_i; + output usr_tx0_ctrl_invalid_k_o; + input usr_tx0_ctrl_replace_en_i; + input [7:0] usr_tx0_ctrl_scr_en_i; + input [63:0] usr_tx0_data_i; + input usr_tx0_pma_clk_en_i; + output usr_tx0_pma_tx_clk_o; + input usr_tx0_rst_n_i; + output usr_tx1_busy_o; + input [7:0] usr_tx1_ctrl_char_is_k_i; + input usr_tx1_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx1_ctrl_enc_en_i; + input [7:0] usr_tx1_ctrl_end_of_frame_i; + input [7:0] usr_tx1_ctrl_end_of_multiframe_i; + output usr_tx1_ctrl_invalid_k_o; + input usr_tx1_ctrl_replace_en_i; + input [7:0] usr_tx1_ctrl_scr_en_i; + input [63:0] usr_tx1_data_i; + input usr_tx1_pma_clk_en_i; + output usr_tx1_pma_tx_clk_o; + input usr_tx1_rst_n_i; + output usr_tx2_busy_o; + input [7:0] usr_tx2_ctrl_char_is_k_i; + input usr_tx2_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx2_ctrl_enc_en_i; + input [7:0] usr_tx2_ctrl_end_of_frame_i; + input [7:0] usr_tx2_ctrl_end_of_multiframe_i; + output usr_tx2_ctrl_invalid_k_o; + input usr_tx2_ctrl_replace_en_i; + input [7:0] usr_tx2_ctrl_scr_en_i; + input [63:0] usr_tx2_data_i; + input usr_tx2_pma_clk_en_i; + output usr_tx2_pma_tx_clk_o; + input usr_tx2_rst_n_i; + output usr_tx3_busy_o; + input [7:0] usr_tx3_ctrl_char_is_k_i; + input usr_tx3_ctrl_driver_pwrdwn_n_i; + input [7:0] usr_tx3_ctrl_enc_en_i; + input [7:0] usr_tx3_ctrl_end_of_frame_i; + input [7:0] usr_tx3_ctrl_end_of_multiframe_i; + output usr_tx3_ctrl_invalid_k_o; + input usr_tx3_ctrl_replace_en_i; + input [7:0] usr_tx3_ctrl_scr_en_i; + input [63:0] usr_tx3_data_i; + input usr_tx3_pma_clk_en_i; + output usr_tx3_pma_tx_clk_o; + input usr_tx3_rst_n_i; + parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0; + parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000; + parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0; + parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000; + parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000; + parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000; + parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00; + parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000; + parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000; + parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000; + parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000; + parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000; + parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000; + parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000; + parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000; + parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000; + parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0; + parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0; + parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000; + parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0; + parameter cfg_main_clk_to_fabric_div_en_i = 1'b0; + parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0; + parameter cfg_main_clk_to_fabric_sel_i = 1'b0; + parameter cfg_main_rclk_to_fabric_sel_i = 2'b00; + parameter cfg_main_use_only_usr_clock_i = 1'b0; + parameter cfg_pcs_ovs_en_i = 1'b0; + parameter cfg_pcs_ovs_mode_i = 1'b0; + parameter cfg_pcs_pll_lock_ppm_i = 3'b000; + parameter cfg_pcs_word_len_i = 2'b00; + parameter cfg_pll_pma_ckref_ext_i = 1'b0; + parameter cfg_pll_pma_cpump_i = 4'b0000; + parameter cfg_pll_pma_divl_i = 2'b00; + parameter cfg_pll_pma_divm_i = 1'b0; + parameter cfg_pll_pma_divn_i = 2'b00; + parameter cfg_pll_pma_gbx_en_i = 1'b0; + parameter cfg_pll_pma_int_data_len_i = 1'b0; + parameter cfg_pll_pma_lvds_en_i = 1'b0; + parameter cfg_pll_pma_lvds_mux_i = 1'b0; + parameter cfg_pll_pma_mux_ckref_i = 1'b0; + parameter cfg_rx0_gearbox_en_i = 1'b0; + parameter cfg_rx0_gearbox_mode_i = 1'b0; + parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx0_pcs_align_bypass_i = 1'b0; + parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx0_pcs_debug_en_i = 1'b0; + parameter cfg_rx0_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx0_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx0_pcs_loopback_i = 1'b0; + parameter cfg_rx0_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx0_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx0_pcs_polarity_i = 1'b0; + parameter cfg_rx0_pcs_protocol_size_i = 1'b0; + parameter cfg_rx0_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx0_pcs_sync_supported_i = 1'b0; + parameter cfg_rx0_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx0_pma_clk_pos_i = 1'b0; + parameter cfg_rx0_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx0_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx0_pma_dco_divl_i = 2'b00; + parameter cfg_rx0_pma_dco_divm_i = 1'b0; + parameter cfg_rx0_pma_dco_divn_i = 2'b00; + parameter cfg_rx0_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx0_pma_fine_ppm_i = 3'b000; + parameter cfg_rx0_pma_loopback_i = 1'b0; + parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx0_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divf_i = 2'b00; + parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divm_i = 2'b00; + parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx0_pma_pll_divn_i = 1'b0; + parameter cfg_rx1_gearbox_en_i = 1'b0; + parameter cfg_rx1_gearbox_mode_i = 1'b0; + parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx1_pcs_align_bypass_i = 1'b0; + parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx1_pcs_debug_en_i = 1'b0; + parameter cfg_rx1_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx1_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx1_pcs_loopback_i = 1'b0; + parameter cfg_rx1_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx1_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx1_pcs_polarity_i = 1'b0; + parameter cfg_rx1_pcs_protocol_size_i = 1'b0; + parameter cfg_rx1_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx1_pcs_sync_supported_i = 1'b0; + parameter cfg_rx1_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx1_pma_clk_pos_i = 1'b0; + parameter cfg_rx1_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx1_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx1_pma_dco_divl_i = 2'b00; + parameter cfg_rx1_pma_dco_divm_i = 1'b0; + parameter cfg_rx1_pma_dco_divn_i = 2'b00; + parameter cfg_rx1_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx1_pma_fine_ppm_i = 3'b000; + parameter cfg_rx1_pma_loopback_i = 1'b0; + parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx1_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divf_i = 2'b00; + parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divm_i = 2'b00; + parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx1_pma_pll_divn_i = 1'b0; + parameter cfg_rx2_gearbox_en_i = 1'b0; + parameter cfg_rx2_gearbox_mode_i = 1'b0; + parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx2_pcs_align_bypass_i = 1'b0; + parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx2_pcs_debug_en_i = 1'b0; + parameter cfg_rx2_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx2_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx2_pcs_loopback_i = 1'b0; + parameter cfg_rx2_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx2_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx2_pcs_polarity_i = 1'b0; + parameter cfg_rx2_pcs_protocol_size_i = 1'b0; + parameter cfg_rx2_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx2_pcs_sync_supported_i = 1'b0; + parameter cfg_rx2_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx2_pma_clk_pos_i = 1'b0; + parameter cfg_rx2_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx2_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx2_pma_dco_divl_i = 2'b00; + parameter cfg_rx2_pma_dco_divm_i = 1'b0; + parameter cfg_rx2_pma_dco_divn_i = 2'b00; + parameter cfg_rx2_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx2_pma_fine_ppm_i = 3'b000; + parameter cfg_rx2_pma_loopback_i = 1'b0; + parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx2_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divf_i = 2'b00; + parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divm_i = 2'b00; + parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx2_pma_pll_divn_i = 1'b0; + parameter cfg_rx3_gearbox_en_i = 1'b0; + parameter cfg_rx3_gearbox_mode_i = 1'b0; + parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0; + parameter cfg_rx3_pcs_align_bypass_i = 1'b0; + parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0; + parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0; + parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000; + parameter cfg_rx3_pcs_debug_en_i = 1'b0; + parameter cfg_rx3_pcs_dec_bypass_i = 1'b0; + parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0; + parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000; + parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000; + parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0; + parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000; + parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00; + parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00; + parameter cfg_rx3_pcs_fsm_sel_i = 2'b00; + parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0; + parameter cfg_rx3_pcs_loopback_i = 1'b0; + parameter cfg_rx3_pcs_m_comma_en_i = 1'b0; + parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000; + parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00; + parameter cfg_rx3_pcs_p_comma_en_i = 1'b0; + parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000; + parameter cfg_rx3_pcs_polarity_i = 1'b0; + parameter cfg_rx3_pcs_protocol_size_i = 1'b0; + parameter cfg_rx3_pcs_replace_bypass_i = 1'b0; + parameter cfg_rx3_pcs_sync_supported_i = 1'b0; + parameter cfg_rx3_pma_cdr_cp_i = 4'b0000; + parameter cfg_rx3_pma_clk_pos_i = 1'b0; + parameter cfg_rx3_pma_coarse_ppm_i = 3'b000; + parameter cfg_rx3_pma_ctrl_term_i = 6'b000000; + parameter cfg_rx3_pma_dco_divl_i = 2'b00; + parameter cfg_rx3_pma_dco_divm_i = 1'b0; + parameter cfg_rx3_pma_dco_divn_i = 2'b00; + parameter cfg_rx3_pma_dco_reg_res_i = 2'b00; + parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0; + parameter cfg_rx3_pma_fine_ppm_i = 3'b000; + parameter cfg_rx3_pma_loopback_i = 1'b0; + parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000; + parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00; + parameter cfg_rx3_pma_peak_detect_on_i = 1'b0; + parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000; + parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divf_i = 2'b00; + parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divm_i = 2'b00; + parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0; + parameter cfg_rx3_pma_pll_divn_i = 1'b0; + parameter cfg_test_mode_i = 2'b00; + parameter cfg_tx0_gearbox_en_i = 1'b0; + parameter cfg_tx0_gearbox_mode_i = 1'b0; + parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx0_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx0_pcs_loopback_i = 1'b0; + parameter cfg_tx0_pcs_polarity_i = 1'b0; + parameter cfg_tx0_pcs_protocol_size_i = 1'b0; + parameter cfg_tx0_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx0_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx0_pcs_sync_supported_i = 1'b0; + parameter cfg_tx0_pma_clk_pos_i = 1'b0; + parameter cfg_tx0_pma_loopback_i = 1'b0; + parameter cfg_tx1_gearbox_en_i = 1'b0; + parameter cfg_tx1_gearbox_mode_i = 1'b0; + parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx1_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx1_pcs_loopback_i = 1'b0; + parameter cfg_tx1_pcs_polarity_i = 1'b0; + parameter cfg_tx1_pcs_protocol_size_i = 1'b0; + parameter cfg_tx1_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx1_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx1_pcs_sync_supported_i = 1'b0; + parameter cfg_tx1_pma_clk_pos_i = 1'b0; + parameter cfg_tx1_pma_loopback_i = 1'b0; + parameter cfg_tx2_gearbox_en_i = 1'b0; + parameter cfg_tx2_gearbox_mode_i = 1'b0; + parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx2_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx2_pcs_loopback_i = 1'b0; + parameter cfg_tx2_pcs_polarity_i = 1'b0; + parameter cfg_tx2_pcs_protocol_size_i = 1'b0; + parameter cfg_tx2_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx2_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx2_pcs_sync_supported_i = 1'b0; + parameter cfg_tx2_pma_clk_pos_i = 1'b0; + parameter cfg_tx2_pma_loopback_i = 1'b0; + parameter cfg_tx3_gearbox_en_i = 1'b0; + parameter cfg_tx3_gearbox_mode_i = 1'b0; + parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0; + parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0; + parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0; + parameter cfg_tx3_pcs_enc_bypass_i = 1'b0; + parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0; + parameter cfg_tx3_pcs_loopback_i = 1'b0; + parameter cfg_tx3_pcs_polarity_i = 1'b0; + parameter cfg_tx3_pcs_protocol_size_i = 1'b0; + parameter cfg_tx3_pcs_replace_bypass_i = 1'b0; + parameter cfg_tx3_pcs_scr_bypass_i = 1'b0; + parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000; + parameter cfg_tx3_pcs_sync_supported_i = 1'b0; + parameter cfg_tx3_pma_clk_pos_i = 1'b0; + parameter cfg_tx3_pma_loopback_i = 1'b0; + parameter location = ""; + parameter rx_usrclk_use_pcs_clk_2 = 1'b0; + parameter tx_usrclk_use_pcs_clk_2 = 1'b0; +endmodule + From 8023f921e3e07c5d9d0ac502a486474cbd6c3c52 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 11:09:02 +0100 Subject: [PATCH 032/342] RAM --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/cells_bb.v | 61 ------- techlibs/nanoxplore/cells_wrap.v | 201 ++++++++++++++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 1 + 4 files changed, 203 insertions(+), 61 deletions(-) create mode 100644 techlibs/nanoxplore/cells_wrap.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 37755106b..ca37a2d5d 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -9,6 +9,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index ba7318c73..fc6165212 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -396,67 +396,6 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, parameter std_mode = ""; endmodule -(* blackbox *) -module NX_RAM_SLOWECC_1K_36_1r1w(ACK, BCK, ACOR, AERR, ACS, AWE, AR, BCS, BWE, BR, AO, AI, AA); - input [9:0] AA; - input ACK; - output ACOR; - input ACS; - output AERR; - input [35:0] AI; - output [35:0] AO; - input AR; - input AWE; - input BCK; - input BCS; - input BR; - input BWE; - parameter mem_ctxt = ""; -endmodule - -(* blackbox *) -module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA -, BA); - input [15:0] AA; - input ACK; - input ACKD; - input ACKR; - output ACOR; - input ACS; - output AERR; - input [23:0] AI; - output [23:0] AO; - input AR; - input AWE; - input [15:0] BA; - input BCK; - input BCKD; - input BCKR; - output BCOR; - input BCS; - output BERR; - input [23:0] BI; - output [23:0] BO; - input BR; - input BWE; - parameter mcka_edge = 1'b0; - parameter mckb_edge = 1'b0; - parameter mem_ctxt = ""; - parameter pcka_edge = 1'b0; - parameter pckb_edge = 1'b0; - parameter pipe_ia = 1'b0; - parameter pipe_ib = 1'b0; - parameter pipe_oa = 1'b0; - parameter pipe_ob = 1'b0; - parameter raw_config0 = 4'b0000; - parameter raw_config1 = 16'b0000000000000000; - parameter raw_l_enable = 1'b0; - parameter raw_l_extend = 4'b0000; - parameter raw_u_enable = 1'b0; - parameter raw_u_extend = 8'b00000000; - parameter std_mode = ""; -endmodule - (* blackbox *) module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); input DCK; diff --git a/techlibs/nanoxplore/cells_wrap.v b/techlibs/nanoxplore/cells_wrap.v new file mode 100644 index 000000000..aa328c4c6 --- /dev/null +++ b/techlibs/nanoxplore/cells_wrap.v @@ -0,0 +1,201 @@ +module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA +, BA); + input [15:0] AA; + input ACK; + input ACKD; + input ACKR; + output ACOR; + input ACS; + output AERR; + input [23:0] AI; + output [23:0] AO; + input AR; + input AWE; + input [15:0] BA; + input BCK; + input BCKD; + input BCKR; + output BCOR; + input BCS; + output BERR; + input [23:0] BI; + output [23:0] BO; + input BR; + input BWE; + parameter mcka_edge = 1'b0; + parameter mckb_edge = 1'b0; + parameter mem_ctxt = ""; + parameter pcka_edge = 1'b0; + parameter pckb_edge = 1'b0; + parameter pipe_ia = 1'b0; + parameter pipe_ib = 1'b0; + parameter pipe_oa = 1'b0; + parameter pipe_ob = 1'b0; + parameter raw_config0 = 4'b0000; + parameter raw_config1 = 16'b0000000000000000; + parameter std_mode = ""; + + NX_RAM #( + .mcka_edge(mcka_edge), + .mckb_edge(mckb_edge), + .mem_ctxt(mem_ctxt), + .pcka_edge(pcka_edge), + .pckb_edge(pckb_edge), + .pipe_ia(pipe_ia), + .pipe_ib(pipe_ib), + .pipe_oa(pipe_oa), + .pipe_ob(pipe_ob), + .raw_config0(raw_config0), + .raw_config1(raw_config1), + .std_mode(std_mode) + ) ram ( + .AA1(AA[0]), + .AA10(AA[9]), + .AA11(AA[10]), + .AA12(AA[11]), + .AA13(AA[12]), + .AA14(AA[13]), + .AA15(AA[14]), + .AA16(AA[15]), + .AA2(AA[1]), + .AA3(AA[2]), + .AA4(AA[3]), + .AA5(AA[4]), + .AA6(AA[5]), + .AA7(AA[6]), + .AA8(AA[7]), + .AA9(AA[8]), + .ACK(ACK), + .ACKC(ACK), + .ACKD(ACKD), + .ACKR(ACKR), + .ACOR(ACOR), + .ACS(ACS), + .AERR(AERR), + .AI1(AI[0]), + .AI10(AI[9]), + .AI11(AI[10]), + .AI12(AI[11]), + .AI13(AI[12]), + .AI14(AI[13]), + .AI15(AI[14]), + .AI16(AI[15]), + .AI17(AI[16]), + .AI18(AI[17]), + .AI19(AI[18]), + .AI2(AI[1]), + .AI20(AI[19]), + .AI21(AI[20]), + .AI22(AI[21]), + .AI23(AI[22]), + .AI24(AI[23]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AI7(AI[6]), + .AI8(AI[7]), + .AI9(AI[8]), + .AO1(AO[0]), + .AO10(AO[9]), + .AO11(AO[10]), + .AO12(AO[11]), + .AO13(AO[12]), + .AO14(AO[13]), + .AO15(AO[14]), + .AO16(AO[15]), + .AO17(AO[16]), + .AO18(AO[17]), + .AO19(AO[18]), + .AO2(AO[1]), + .AO20(AO[19]), + .AO21(AO[20]), + .AO22(AO[21]), + .AO23(AO[22]), + .AO24(AO[23]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .AO7(AO[6]), + .AO8(AO[7]), + .AO9(AO[8]), + .AR(AR), + .AWE(AWE), + .BA1(BA[0]), + .BA10(BA[9]), + .BA11(BA[10]), + .BA12(BA[11]), + .BA13(BA[12]), + .BA14(BA[13]), + .BA15(BA[14]), + .BA16(BA[15]), + .BA2(BA[1]), + .BA3(BA[2]), + .BA4(BA[3]), + .BA5(BA[4]), + .BA6(BA[5]), + .BA7(BA[6]), + .BA8(BA[7]), + .BA9(BA[8]), + .BCK(BCK), + .BCKC(BCK), + .BCKD(BCKD), + .BCKR(BCKR), + .BCOR(BCOR), + .BCS(BCS), + .BERR(BERR), + .BI1(BI[0]), + .BI10(BI[9]), + .BI11(BI[10]), + .BI12(BI[11]), + .BI13(BI[12]), + .BI14(BI[13]), + .BI15(BI[14]), + .BI16(BI[15]), + .BI17(BI[16]), + .BI18(BI[17]), + .BI19(BI[18]), + .BI2(BI[1]), + .BI20(BI[19]), + .BI21(BI[20]), + .BI22(BI[21]), + .BI23(BI[22]), + .BI24(BI[23]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BI7(BI[6]), + .BI8(BI[7]), + .BI9(BI[8]), + .BO1(BO[0]), + .BO10(BO[9]), + .BO11(BO[10]), + .BO12(BO[11]), + .BO13(BO[12]), + .BO14(BO[13]), + .BO15(BO[14]), + .BO16(BO[15]), + .BO17(BO[16]), + .BO18(BO[17]), + .BO19(BO[18]), + .BO2(BO[1]), + .BO20(BO[19]), + .BO21(BO[20]), + .BO22(BO[21]), + .BO23(BO[22]), + .BO24(BO[23]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .BO7(BO[6]), + .BO8(BO[7]), + .BO9(BO[8]), + .BR(BR), + .BWE(BWE) + ); + +endmodule + diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 2a8f48729..880e712c3 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -207,6 +207,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("begin")) { run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); + run("techmap -map +/nanoxplore/cells_wrap.v"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } From fa14c600ffcb9ab13bd5793e4755a4ec8dbe3088 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 11:23:33 +0100 Subject: [PATCH 033/342] commented remainder of primitives --- techlibs/nanoxplore/cells_bb.v | 168 +++++++++++++++++---------------- 1 file changed, 89 insertions(+), 79 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index fc6165212..1955f590b 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -1,27 +1,12 @@ -(* blackbox *) -module NX_BD(I, O); - input I; - output O; - parameter mode = "global_lowskew"; -endmodule - -(* blackbox *) -module NX_BFF(I, O); - input I; - output O; -endmodule - -(* blackbox *) -module NX_BFR(I, O); - input I; - output O; - parameter data_inv = 1'b0; - parameter iobname = ""; - parameter location = ""; - parameter mode = 0; - parameter path = 0; - parameter ring = 0; -endmodule +//(* blackbox *) +//module NX_LUT(I1, I2, I3, I4, O); +// input I1; +// input I2; +// input I3; +// input I4; +// output O; +// parameter lut_table = 16'b0000000000000000; +//endmodule //(* blackbox *) //module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4); @@ -42,37 +27,12 @@ endmodule // parameter add_carry = 0; //endmodule +// Bypass mode of NX_GCK_U (* blackbox *) -module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID); - input DCK; - output [5:0] DID; - input DIG; - input [5:0] DRA; - input [5:0] DRI; - input DRL; - output [5:0] DRO; - input [1:0] DS; - input FCK; - output FLD; - output FLG; - input FZ; - input IO; - output [4:0] O; - input R; - input SCK; - parameter data_size = 5; - parameter differential = ""; - parameter dpath_dynamic = 1'b0; - parameter drive = ""; - parameter inputDelayLine = ""; - parameter inputSignalSlope = ""; - parameter location = ""; - parameter locked = 1'b0; - parameter standard = ""; - parameter termination = ""; - parameter terminationReference = ""; - parameter turbo = ""; - parameter weakTermination = ""; +module NX_BD(I, O); + input I; + output O; + parameter mode = "global_lowskew"; endmodule //(* blackbox *) @@ -90,6 +50,14 @@ endmodule // parameter dff_type = 1'b0; //endmodule +// Special mode of NX_DFF +(* blackbox *) +module NX_BFF(I, O); + input I; + output O; +endmodule + + (* blackbox *) module NX_DFR(I, CK, L, R, O); input CK; @@ -110,12 +78,17 @@ module NX_DFR(I, CK, L, R, O); parameter ring = 0; endmodule +// Special mode of NX_DFR (* blackbox *) -module NX_ECC(CKD, CHK, COR, ERR); - input CHK; - input CKD; - output COR; - output ERR; +module NX_BFR(I, O); + input I; + output O; + parameter data_inv = 1'b0; + parameter iobname = ""; + parameter location = ""; + parameter mode = 0; + parameter path = 0; + parameter ring = 0; endmodule (* blackbox *) @@ -203,26 +176,6 @@ module NX_IOB_O(I, C, T, IO); parameter weakTermination = ""; endmodule -(* blackbox *) -module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA); - input [1:0] DS; - input GS; - output [2:0] GVDN; - output [2:0] GVIN; - output [2:0] GVON; - input [5:0] LA; - output [3:0] PA; -endmodule - -//(* blackbox *) -//module NX_LUT(I1, I2, I3, I4, O); -// input I1; -// input I2; -// input I3; -// input I4; -// output O; -// parameter lut_table = 16'b0000000000000000; -//endmodule (* blackbox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 @@ -396,6 +349,28 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, parameter std_mode = ""; endmodule +// NX_RAM related +(* blackbox *) +module NX_ECC(CKD, CHK, COR, ERR); + input CHK; + input CKD; + output COR; + output ERR; +endmodule + +//TODO +(* blackbox *) +module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA); + input [1:0] DS; + input GS; + output [2:0] GVDN; + output [2:0] GVIN; + output [2:0] GVON; + input [5:0] LA; + output [3:0] PA; +endmodule + +//TODO (* blackbox *) module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); input DCK; @@ -422,6 +397,41 @@ module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID); parameter standard = ""; endmodule +//TODO +(* blackbox *) +module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID); + input DCK; + output [5:0] DID; + input DIG; + input [5:0] DRA; + input [5:0] DRI; + input DRL; + output [5:0] DRO; + input [1:0] DS; + input FCK; + output FLD; + output FLG; + input FZ; + input IO; + output [4:0] O; + input R; + input SCK; + parameter data_size = 5; + parameter differential = ""; + parameter dpath_dynamic = 1'b0; + parameter drive = ""; + parameter inputDelayLine = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; +endmodule + +//TODO (* blackbox *) module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO , DID); From 370517b1e6c4872742a7c62564320ad556b356f8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 12:52:40 +0100 Subject: [PATCH 034/342] IO --- techlibs/nanoxplore/cells_bb.v | 86 ------------------------------ techlibs/nanoxplore/cells_sim.v | 94 +++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 86 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 1955f590b..42953b6b2 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -91,92 +91,6 @@ module NX_BFR(I, O); parameter ring = 0; endmodule -(* blackbox *) -module NX_IOB(I, C, T, O, IO); - input C; - input I; - inout IO; - output O; - input T; - parameter differential = ""; - parameter drive = ""; - parameter dynDrive = ""; - parameter dynInput = ""; - parameter dynTerm = ""; - parameter extra = 3; - parameter inputDelayLine = ""; - parameter inputDelayOn = ""; - parameter inputSignalSlope = ""; - parameter location = ""; - parameter locked = 1'b0; - parameter outputCapacity = ""; - parameter outputDelayLine = ""; - parameter outputDelayOn = ""; - parameter slewRate = ""; - parameter standard = ""; - parameter termination = ""; - parameter terminationReference = ""; - parameter turbo = ""; - parameter weakTermination = ""; -endmodule - -(* blackbox *) -module NX_IOB_I(C, T, IO, O); - input C; - input IO; - output O; - input T; - parameter differential = ""; - parameter drive = ""; - parameter dynDrive = ""; - parameter dynInput = ""; - parameter dynTerm = ""; - parameter extra = 1; - parameter inputDelayLine = ""; - parameter inputDelayOn = ""; - parameter inputSignalSlope = ""; - parameter location = ""; - parameter locked = 1'b0; - parameter outputCapacity = ""; - parameter outputDelayLine = ""; - parameter outputDelayOn = ""; - parameter slewRate = ""; - parameter standard = ""; - parameter termination = ""; - parameter terminationReference = ""; - parameter turbo = ""; - parameter weakTermination = ""; -endmodule - -(* blackbox *) -module NX_IOB_O(I, C, T, IO); - input C; - input I; - output IO; - input T; - parameter differential = ""; - parameter drive = ""; - parameter dynDrive = ""; - parameter dynInput = ""; - parameter dynTerm = ""; - parameter extra = 2; - parameter inputDelayLine = ""; - parameter inputDelayOn = ""; - parameter inputSignalSlope = ""; - parameter location = ""; - parameter locked = 1'b0; - parameter outputCapacity = ""; - parameter outputDelayLine = ""; - parameter outputDelayOn = ""; - parameter slewRate = ""; - parameter standard = ""; - parameter termination = ""; - parameter terminationReference = ""; - parameter turbo = ""; - parameter weakTermination = ""; -endmodule - - (* blackbox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 35b1574ba..88ec78b5c 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -91,3 +91,97 @@ always @(posedge clock) assign O = mem[RA]; endmodule + +module NX_IOB(I, C, T, O, IO); + input C; + input I; + (* iopad_external_pin *) + inout IO; + output O; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 3; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; + + assign O = IO; + assign IO = C ? I : 1'bz; +endmodule + +module NX_IOB_I(C, T, IO, O); + input C; + (* iopad_external_pin *) + input IO; + output O; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 1; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; + + assign O = IO; +endmodule + +module NX_IOB_O(I, C, T, IO); + input C; + input I; + (* iopad_external_pin *) + output IO; + input T; + parameter differential = ""; + parameter drive = ""; + parameter dynDrive = ""; + parameter dynInput = ""; + parameter dynTerm = ""; + parameter extra = 2; + parameter inputDelayLine = ""; + parameter inputDelayOn = ""; + parameter inputSignalSlope = ""; + parameter location = ""; + parameter locked = 1'b0; + parameter outputCapacity = ""; + parameter outputDelayLine = ""; + parameter outputDelayOn = ""; + parameter slewRate = ""; + parameter standard = ""; + parameter termination = ""; + parameter terminationReference = ""; + parameter turbo = ""; + parameter weakTermination = ""; + + assign IO = C ? I : 1'bz; +endmodule + + From a5bfb23b472966ccd55f526651c4c2b5a87db99d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 18:19:41 +0100 Subject: [PATCH 035/342] start cleaning rams --- techlibs/nanoxplore/Makefile.inc | 5 ++- techlibs/nanoxplore/brams.txt | 26 +++++++++++++ techlibs/nanoxplore/brams_map.v | 32 ++++++++++++++++ techlibs/nanoxplore/cells_map.v | 12 ------ techlibs/nanoxplore/rf_rams_map_u.v | 12 ++++++ .../nanoxplore/{drams.txt => rf_rams_u.txt} | 0 techlibs/nanoxplore/synth_nanoxplore.cc | 37 +++++++++++++------ tests/arch/nanoxplore/lutram.ys | 4 +- 8 files changed, 101 insertions(+), 27 deletions(-) create mode 100644 techlibs/nanoxplore/brams.txt create mode 100644 techlibs/nanoxplore/brams_map.v create mode 100644 techlibs/nanoxplore/rf_rams_map_u.v rename techlibs/nanoxplore/{drams.txt => rf_rams_u.txt} (100%) diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index ca37a2d5d..40e730cbe 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -3,6 +3,8 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v)) @@ -13,5 +15,6 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) -$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt new file mode 100644 index 000000000..bc3a1722e --- /dev/null +++ b/techlibs/nanoxplore/brams.txt @@ -0,0 +1,26 @@ +ram block $__NX_RAM_ { + abits 13; + widths 1 2 4 9 per_port; + cost 64; + init no_undef; + port srsw "A" "B" { + clock anyedge; + clken; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} \ No newline at end of file diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v new file mode 100644 index 000000000..04b6134c3 --- /dev/null +++ b/techlibs/nanoxplore/brams_map.v @@ -0,0 +1,32 @@ +module $__NX_RAM_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_A_WIDTH = 9; +parameter PORT_A_CLK_POL = 1; +parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input PORT_A_RD_SRST; +input PORT_A_RD_ARST; +input [12:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +parameter PORT_B_WIDTH = 9; +parameter PORT_B_CLK_POL = 1; +parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input PORT_B_RD_SRST; +input PORT_B_RD_ARST; +input [12:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 54f2414c8..75e7140aa 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -70,15 +70,3 @@ module \$_SDFF_NP1_ (input D, C, R, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule - -module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); - parameter INIT = 1152'bx; - parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); -endmodule - -module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); - parameter INIT = 1152'bx; - parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); -endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v new file mode 100644 index 000000000..397dd0fcd --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -0,0 +1,12 @@ + +module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule + +module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/rf_rams_u.txt similarity index 100% rename from techlibs/nanoxplore/drams.txt rename to techlibs/nanoxplore/rf_rams_u.txt diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 880e712c3..f6e507e62 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -73,11 +73,11 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); - log(" -nolutram\n"); - log(" do not use LUT RAM cells in output netlist\n"); + log(" -norfram\n"); + log(" do not use Register File RAM cells in output netlist\n"); log("\n"); log(" -nobram\n"); - log(" do not use block RAM cells in output netlist\n"); + log(" do not use block NX_RAM cells in output netlist\n"); log("\n"); log(" -nodsp\n"); log(" do not map multipliers to NX_DSP cells\n"); @@ -92,8 +92,8 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad; - std::string postfix; + bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad; + std::string postfix, rf_postfix; void clear_flags() override { @@ -103,11 +103,12 @@ struct SynthNanoXplorePass : public ScriptPass flatten = true; abc9 = false; nocy = false; - nolutram = false; + norfram = false; nobram = false; nodsp = false; iopad = false; postfix = ""; + rf_postfix = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -154,8 +155,8 @@ struct SynthNanoXplorePass : public ScriptPass nocy = true; continue; } - if (args[argidx] == "-nolutram") { - nolutram = true; + if (args[argidx] == "-norfram") { + norfram = true; continue; } if (args[argidx] == "-nobram") { @@ -177,17 +178,20 @@ struct SynthNanoXplorePass : public ScriptPass if (family.empty()) { //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; - postfix = "_u"; } if (family == "ultra") { postfix = "_u"; + rf_postfix = "_u"; } else if (family == "u300") { postfix = "_u"; + rf_postfix = "_u"; } else if (family == "medium") { postfix = "_m"; + rf_postfix = "_l"; } else if (family == "large") { postfix = "_l"; + rf_postfix = "_l"; } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); @@ -238,9 +242,18 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); } - if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_libmap -lib +/nanoxplore/drams.txt"); - run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_"); + if (check_label("map_ram")) + { + std::string args = ""; + if (nobram) + args += " -no-auto-block"; + if (norfram) + args += " -no-auto-distributed"; + if (help_mode) + args += " [-no-auto-block] [-no-auto-distributed]"; + run("memory_libmap -lib +/nanoxplore/rf_rams"+ rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); + run("techmap -map +/nanoxplore/rf_rams_map"+ rf_postfix+ ".v -map +/nanoxplore/brams_map.v"); + run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*"); } if (check_label("map_ffram")) diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 669cb0007..9809da928 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r synth_nanoxplore cd lutram_1w1r -select -assert-count 1 t:NX_XRFB_64x18 +select -assert-count 1 t:NX_RFB_U select -assert-count 8 t:NX_DFF -select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D +select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D From 474ed28aee995131f8ece02090c648d931054055 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 14 Mar 2024 08:40:14 +0100 Subject: [PATCH 036/342] added no-rw-check, and new rfb models --- techlibs/nanoxplore/Makefile.inc | 6 +++- techlibs/nanoxplore/rf_rams_l.txt | 15 ++++++++ techlibs/nanoxplore/rf_rams_m.txt | 15 ++++++++ techlibs/nanoxplore/rf_rams_map_l.v | 30 ++++++++++++++++ techlibs/nanoxplore/rf_rams_map_m.v | 30 ++++++++++++++++ techlibs/nanoxplore/rf_rams_map_u.v | 46 ++++++++++++++++++++++--- techlibs/nanoxplore/synth_nanoxplore.cc | 31 +++++++++++------ 7 files changed, 158 insertions(+), 15 deletions(-) create mode 100644 techlibs/nanoxplore/rf_rams_l.txt create mode 100644 techlibs/nanoxplore/rf_rams_m.txt create mode 100644 techlibs/nanoxplore/rf_rams_map_l.v create mode 100644 techlibs/nanoxplore/rf_rams_map_m.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 40e730cbe..cae2817b3 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -16,5 +16,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) -$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) diff --git a/techlibs/nanoxplore/rf_rams_l.txt b/techlibs/nanoxplore/rf_rams_l.txt new file mode 100644 index 000000000..112655184 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_l.txt @@ -0,0 +1,15 @@ +ram distributed $__NX_RFB_L_ { + abits 6; + width 16; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port sr "R" { + clock anyedge; + rden; + } +} diff --git a/techlibs/nanoxplore/rf_rams_m.txt b/techlibs/nanoxplore/rf_rams_m.txt new file mode 100644 index 000000000..d872405a3 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_m.txt @@ -0,0 +1,15 @@ +ram distributed $__NX_RFB_M_ { + abits 6; + width 16; + cost 10; + init no_undef; + prune_rom; + + port sw "W" { + clock anyedge; + } + port sr "R" { + clock anyedge; + rden; + } +} diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v new file mode 100644 index 000000000..e529ce1e1 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_l.v @@ -0,0 +1,30 @@ +module $__NX_RFB_L_ ( + input PORT_W_CLK, + input PORT_W_WR_EN, + input [5:0] PORT_W_ADDR, + input [15:0] PORT_W_WR_DATA, + input PORT_R_CLK, + input PORT_R_RD_EN, + input [5:0] PORT_R_ADDR, + output [15:0] PORT_R_RD_DATA, +); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + parameter PORT_R_CLK_POL = 1'b1; + + NX_RFB_L_WRAP #( + .mode(0), + .mem_ctxt(INIT), + .rck_edge(~PORT_R_CLK_POL), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .RCK(PORT_R_CLK), + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .RE(PORT_R_RD_EN), + .WE(PORT_W_WR_EN), + .O(PORT_R_RD_DATA) + ); +endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v new file mode 100644 index 000000000..a64dc3388 --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_m.v @@ -0,0 +1,30 @@ +module $__NX_RFB_M_ ( + input PORT_W_CLK, + input PORT_W_WR_EN, + input [5:0] PORT_W_ADDR, + input [15:0] PORT_W_WR_DATA, + input PORT_R_CLK, + input PORT_R_RD_EN, + input [5:0] PORT_R_ADDR, + output [15:0] PORT_R_RD_DATA, +); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + parameter PORT_R_CLK_POL = 1'b1; + + NX_RFB_M_WRAP #( + .mode(0), + .mem_ctxt(INIT), + .rck_edge(~PORT_R_CLK_POL), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .RCK(PORT_R_CLK), + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .RE(PORT_R_RD_EN), + .WE(PORT_W_WR_EN), + .O(PORT_R_RD_DATA) + ); +endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v index 397dd0fcd..94d5df097 100644 --- a/techlibs/nanoxplore/rf_rams_map_u.v +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -1,12 +1,50 @@ -module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); +module $__NX_XRFB_64x18_ ( + input PORT_W_CLK, + input [5:0] PORT_W_ADDR, + input [5:0] PORT_R_ADDR, + input [17:0] PORT_W_WR_DATA, + input PORT_W_WR_EN, + output [17:0] PORT_R_RD_DATA +); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); + + NX_XRFB_64x18 #( + .mem_ctxt(INIT), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WEA(1'b1), + .O(PORT_R_RD_DATA) + ); endmodule -module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); +module $__NX_XRFB_32x36_ ( + input PORT_W_CLK, + input [4:0] PORT_W_ADDR, + input [4:0] PORT_R_ADDR, + input [35:0] PORT_W_WR_DATA, + input PORT_W_WR_EN, + output [35:0] PORT_R_RD_DATA +); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); + + NX_XRFB_32x36 #( + .mem_ctxt(INIT), + .wck_edge(~PORT_W_CLK_POL) + ) _TECHMAP_REPLACE_ ( + .WCK(PORT_W_CLK), + .I(PORT_W_WR_DATA), + .RA(PORT_R_ADDR), + .WA(PORT_W_ADDR), + .WE(PORT_W_WR_EN), + .WEA(1'b1), + .O(PORT_R_RD_DATA) + ); endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index f6e507e62..23a2af278 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -85,6 +85,11 @@ struct SynthNanoXplorePass : public ScriptPass log(" -iopad\n"); log(" insert IO buffers\n"); log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -92,8 +97,8 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad; - std::string postfix, rf_postfix; + bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad, no_rw_check; + std::string postfix; void clear_flags() override { @@ -107,8 +112,8 @@ struct SynthNanoXplorePass : public ScriptPass nobram = false; nodsp = false; iopad = false; + no_rw_check = false; postfix = ""; - rf_postfix = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -171,6 +176,10 @@ struct SynthNanoXplorePass : public ScriptPass iopad = true; continue; } + if (args[argidx] == "-no-rw-check") { + no_rw_check = true; + continue; + } break; } extra_args(args, argidx, design); @@ -182,16 +191,12 @@ struct SynthNanoXplorePass : public ScriptPass if (family == "ultra") { postfix = "_u"; - rf_postfix = "_u"; } else if (family == "u300") { postfix = "_u"; - rf_postfix = "_u"; } else if (family == "medium") { postfix = "_m"; - rf_postfix = "_l"; } else if (family == "large") { postfix = "_l"; - rf_postfix = "_l"; } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); @@ -208,6 +213,12 @@ struct SynthNanoXplorePass : public ScriptPass void script() override { + std::string no_rw_check_opt = ""; + if (no_rw_check) + no_rw_check_opt = " -no-rw-check"; + if (help_mode) + no_rw_check_opt = " [-no-rw-check]"; + if (check_label("begin")) { run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); @@ -238,7 +249,7 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); run("alumacc"); run("opt"); - run("memory -nomap"); + run("memory -nomap" + no_rw_check_opt); run("opt_clean"); } @@ -251,8 +262,8 @@ struct SynthNanoXplorePass : public ScriptPass args += " -no-auto-distributed"; if (help_mode) args += " [-no-auto-block] [-no-auto-distributed]"; - run("memory_libmap -lib +/nanoxplore/rf_rams"+ rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); - run("techmap -map +/nanoxplore/rf_rams_map"+ rf_postfix+ ".v -map +/nanoxplore/brams_map.v"); + run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); + run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*"); } From da6a62f3a0f29898b105d675d5880a52d8ff0c12 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 Mar 2024 13:27:33 +0100 Subject: [PATCH 037/342] Initial carry chain handling pass --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/arith_map.v | 75 +++++------ techlibs/nanoxplore/cells_sim.v | 12 ++ techlibs/nanoxplore/nx_carry.cc | 158 ++++++++++++++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 4 +- 5 files changed, 213 insertions(+), 37 deletions(-) create mode 100644 techlibs/nanoxplore/nx_carry.cc diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index cae2817b3..f6606639e 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o +OBJS += techlibs/nanoxplore/nx_carry.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v index 69e83b68c..7b4534b83 100644 --- a/techlibs/nanoxplore/arith_map.v +++ b/techlibs/nanoxplore/arith_map.v @@ -1,4 +1,21 @@ -`default_nettype none +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Miodrag Milanovic + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ (* techmap_celltype = "$alu" *) module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO); @@ -26,46 +43,32 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO); \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - function integer round_up4; - input integer N; - begin - round_up4 = ((N + 3) / 4) * 4; - end - endfunction - - localparam Y_WIDTH4 = round_up4(Y_WIDTH); - (* force_downto *) - wire [Y_WIDTH4-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] AA = A_buf; (* force_downto *) - wire [Y_WIDTH4-1:0] BB = BI ? ~B_buf : B_buf; - (* force_downto *) - wire [Y_WIDTH4-1:0] BX = B_buf; - (* force_downto *) - wire [Y_WIDTH4:0] C = {CO, CI}; - (* force_downto *) - wire [Y_WIDTH4-1:0] FCO, Y1; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; genvar i; - generate for (i = 0; i < Y_WIDTH4; i = i + 4) begin:slice - NX_CY cy_i ( - .CI(C[i]), - .A1(AA[i]), .A2(AA[i+1]), .A3(AA[i+2]), .A4(AA[i+3]), - .B1(BB[i]), .B2(BB[i+1]), .B3(BB[i+2]), .B4(BB[i+3]), - .S1(Y1[i]), .S2(Y1[i+1]), .S3(Y1[i+2]), .S4(Y1[i+3]), - .CO(FCO[i]) - ); + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice + NX_CY_1BIT #(.first(i==0)) + alu_i ( + .CI(i==0 ? CI : CO[i-1]), + .A(AA[i]), + .B(BB[i]), + .S(Y[i]), + .CO(CO[i]) + ); - assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); - if (i+1 < Y_WIDTH) - assign CO[i+1] = (AA[i+1] && BB[i+1]) || (C[i+1] && (AA[i+1] || BB[i+1])); - if (i+2 < Y_WIDTH) - assign CO[i+2] = (AA[i+2] && BB[i+2]) || (C[i+2] && (AA[i+2] || BB[i+2])); - if (i+3 < Y_WIDTH) - assign CO[i+3] = FCO[i]; + end: slice + endgenerate - end endgenerate + NX_CY_1BIT alu_cout( + .CI(CO[Y_WIDTH-1]), + .A(1'b0), + .B(1'b0), + .S(CO[Y_WIDTH-1]) + ); - assign X = AA ^ BB; - assign Y = Y1[Y_WIDTH-1:0]; + /* End implementation */ + assign X = AA ^ BB; endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 88ec78b5c..9c3cace47 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -184,4 +184,16 @@ module NX_IOB_O(I, C, T, IO); assign IO = C ? I : 1'bz; endmodule +(* abc9_box, lib_whitebox *) +module NX_CY_1BIT(CI, A, B, S, CO); + (* abc9_carry *) + input CI; + input A; + input B; + output S; + (* abc9_carry *) + output CO; + parameter first = 1'b0; + assign {CO, S} = A + B + CI; +endmodule diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc new file mode 100644 index 000000000..f67cc7d5c --- /dev/null +++ b/techlibs/nanoxplore/nx_carry.cc @@ -0,0 +1,158 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Miodrag Milanovic + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +static SigBit get_bit_or_zero(const SigSpec &sig) +{ + if (GetSize(sig) == 0) + return State::S0; + return sig[0]; +} + +static void nx_carry_chain(Module *module) +{ + SigMap sigmap(module); + + dict carry_ci_propagate; + for (auto cell : module->cells()) + { + if (cell->type == ID(NX_CY_1BIT)) { + // Only first can have CI generated that is not constant + if (cell->getParam(ID(first)).as_int() == 0) continue; + if (!cell->getPort(ID(CI)).is_wire()) continue; + carry_ci_propagate[cell] = cell->getPort(ID(CI)).as_bit(); + } + } + + for (auto cy : carry_ci_propagate) + { + Cell *cell = cy.first; + cell->setParam(ID(first), Const(0, 1)); + + SigBit new_co = module->addWire(NEW_ID); + Cell *c = module->addCell(NEW_ID, ID(NX_CY_1BIT)); + c->setParam(ID(first), Const(1)); + c->setPort(ID(CI), State::S0); + c->setPort(ID(A), cy.second); + c->setPort(ID(B), State::S0); + c->setPort(ID(CO), new_co); + cell->setPort(ID(CI), new_co); + + log("Adding cell %s to propaget CI signal.\n", log_id(cell)); + } + carry_ci_propagate.clear(); + + dict carry; + for (auto cell : module->cells()) + { + if (cell->type == ID(NX_CY_1BIT)) { + if (cell->getParam(ID(first)).as_int() == 1) continue; + if (!cell->hasPort(ID(CI))) + log_error("Not able to find connected carry.\n"); + SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit()); + carry[ci] = cell; + } + } + + dict> carry_chains; + log("Detecting carry chains\n"); + for (auto cell : module->cells()) + { + if (cell->type == ID(NX_CY_1BIT)) { + if (cell->getParam(ID(first)).as_int() == 0) continue; + + vector chain; + SigBit co = sigmap(cell->getPort(ID(CO)).as_bit()); + Cell *current = cell; + chain.push_back(current); + while (co.is_wire()) + { + if (carry.count(co)==0) + break; + //log_error("Not able to find connected carry.\n"); + current = carry[co]; + chain.push_back(current); + if (!current->hasPort(ID(CO))) break; + co = sigmap(current->getPort(ID(CO)).as_bit()); + } + carry_chains[cell] = chain; + } + } + + log("Creating NX_CY cells.\n"); + for(auto& c : carry_chains) { + Cell *cell = nullptr; + int j = 0; + IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) }; + IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; + IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; + for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY)); + cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI))); + } + if (j==3) + cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO))); + + + cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A)))); + cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B)))); + + if (c.second.at(i)->hasPort(ID(S))) + cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S))); + + j = (j + 1) % 4; + module->remove(c.second.at(i)); + } + } +} + +struct NXCarryPass : public Pass { + NXCarryPass() : Pass("nx_carry", "NanoXplore: create carry cells") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" nx_carry [options] [selection]\n"); + log("\n"); + log("Fixes carry chain if needed, break it on 24 elements and group by 4 into NX_CY.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing NX_CARRY pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + nx_carry_chain(module); + } +} NXCarryPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 23a2af278..975f78cae 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -279,8 +279,10 @@ struct SynthNanoXplorePass : public ScriptPass { if (nocy) run("techmap"); - else + else { run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v"); + run("nx_carry"); + } if (help_mode || iopad) { run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')"); run("techmap -map +/nanoxplore/io_map.v"); From ab32dde81b050a7d83791112ac8de5eafc1082cb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 Mar 2024 15:22:53 +0100 Subject: [PATCH 038/342] optimized --- techlibs/nanoxplore/nx_carry.cc | 44 +++++++++++---------------------- 1 file changed, 14 insertions(+), 30 deletions(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index f67cc7d5c..d8a8b67bf 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -34,35 +34,6 @@ static void nx_carry_chain(Module *module) { SigMap sigmap(module); - dict carry_ci_propagate; - for (auto cell : module->cells()) - { - if (cell->type == ID(NX_CY_1BIT)) { - // Only first can have CI generated that is not constant - if (cell->getParam(ID(first)).as_int() == 0) continue; - if (!cell->getPort(ID(CI)).is_wire()) continue; - carry_ci_propagate[cell] = cell->getPort(ID(CI)).as_bit(); - } - } - - for (auto cy : carry_ci_propagate) - { - Cell *cell = cy.first; - cell->setParam(ID(first), Const(0, 1)); - - SigBit new_co = module->addWire(NEW_ID); - Cell *c = module->addCell(NEW_ID, ID(NX_CY_1BIT)); - c->setParam(ID(first), Const(1)); - c->setPort(ID(CI), State::S0); - c->setPort(ID(A), cy.second); - c->setPort(ID(B), State::S0); - c->setPort(ID(CO), new_co); - cell->setPort(ID(CI), new_co); - - log("Adding cell %s to propaget CI signal.\n", log_id(cell)); - } - carry_ci_propagate.clear(); - dict carry; for (auto cell : module->cells()) { @@ -83,9 +54,10 @@ static void nx_carry_chain(Module *module) if (cell->getParam(ID(first)).as_int() == 0) continue; vector chain; - SigBit co = sigmap(cell->getPort(ID(CO)).as_bit()); Cell *current = cell; chain.push_back(current); + + SigBit co = sigmap(cell->getPort(ID(CO)).as_bit()); while (co.is_wire()) { if (carry.count(co)==0) @@ -107,6 +79,18 @@ static void nx_carry_chain(Module *module) IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) }; IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; + if (c.second.at(0)->getPort(ID(CI)).is_wire()) { + SigBit new_co = module->addWire(NEW_ID); + cell = module->addCell(NEW_ID, ID(NX_CY)); + cell->setPort(ID(CI), State::S0); + cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); + cell->setPort(names_B[0], State::S0); + cell->setPort(ID(CO), new_co); + + c.second.at(0)->setPort(ID(CI), new_co); + j++; + } + for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY)); From b6f73837361196f2e510cceed51a56073469ba2f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 19 Mar 2024 17:47:40 +0100 Subject: [PATCH 039/342] break long chains --- techlibs/nanoxplore/nx_carry.cc | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index d8a8b67bf..2a495e41e 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -76,18 +76,15 @@ static void nx_carry_chain(Module *module) for(auto& c : carry_chains) { Cell *cell = nullptr; int j = 0; + int cnt = 0; IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) }; IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; if (c.second.at(0)->getPort(ID(CI)).is_wire()) { - SigBit new_co = module->addWire(NEW_ID); cell = module->addCell(NEW_ID, ID(NX_CY)); cell->setPort(ID(CI), State::S0); cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); cell->setPort(names_B[0], State::S0); - cell->setPort(ID(CO), new_co); - - c.second.at(0)->setPort(ID(CI), new_co); j++; } @@ -96,10 +93,24 @@ static void nx_carry_chain(Module *module) cell = module->addCell(NEW_ID, ID(NX_CY)); cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI))); } - if (j==3) - cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO))); - - + if (j==3) { + cell->set_string_attribute(ID(cnt), std::to_string(cnt)); + if (cnt % 24 == 23) { + SigBit new_co = module->addWire(NEW_ID); + cell->setPort(ID(A4), State::S0); + cell->setPort(ID(B4), State::S0); + cell->setPort(ID(S4), new_co); + cell = module->addCell(NEW_ID, ID(NX_CY)); + cell->setPort(ID(CI), State::S0); + cell->setPort(ID(A1), new_co); + cell->setPort(ID(B1), State::S0); + j = 1; + } else { + if (c.second.at(i)->hasPort(ID(CO))) + cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO))); + } + cnt++; + } cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A)))); cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B)))); From 31f943513bbee5905fc1241fe9edf1dbe24f3110 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 25 Mar 2024 09:23:31 +0100 Subject: [PATCH 040/342] set add_carry property and all inputs to 0 --- techlibs/nanoxplore/nx_carry.cc | 37 ++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 2a495e41e..a61921e05 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -83,6 +83,16 @@ static void nx_carry_chain(Module *module) if (c.second.at(0)->getPort(ID(CI)).is_wire()) { cell = module->addCell(NEW_ID, ID(NX_CY)); cell->setPort(ID(CI), State::S0); + // Set all inputs on 0 + cell->setPort(ID(A1), State::S0); + cell->setPort(ID(B1), State::S0); + cell->setPort(ID(A2), State::S0); + cell->setPort(ID(B2), State::S0); + cell->setPort(ID(A3), State::S0); + cell->setPort(ID(B3), State::S0); + cell->setPort(ID(A4), State::S0); + cell->setPort(ID(B4), State::S0); + cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); cell->setPort(names_B[0], State::S0); j++; @@ -91,7 +101,25 @@ static void nx_carry_chain(Module *module) for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY)); - cell->setPort(ID(CI), c.second.at(i)->getPort(ID(CI))); + SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit(); + cell->setPort(ID(CI), ci); + // Set all inputs on 0 + cell->setPort(ID(A1), State::S0); + cell->setPort(ID(B1), State::S0); + cell->setPort(ID(A2), State::S0); + cell->setPort(ID(B2), State::S0); + cell->setPort(ID(A3), State::S0); + cell->setPort(ID(B3), State::S0); + cell->setPort(ID(A4), State::S0); + cell->setPort(ID(B4), State::S0); + if (ci.is_wire()) { + cell->setParam(ID(add_carry), Const(2,2)); + } else { + if (ci == State::S0) + cell->setParam(ID(add_carry), Const(0,2)); + else + cell->setParam(ID(add_carry), Const(1,2)); + } } if (j==3) { cell->set_string_attribute(ID(cnt), std::to_string(cnt)); @@ -104,6 +132,13 @@ static void nx_carry_chain(Module *module) cell->setPort(ID(CI), State::S0); cell->setPort(ID(A1), new_co); cell->setPort(ID(B1), State::S0); + // Set all inputs on 0 + cell->setPort(ID(A2), State::S0); + cell->setPort(ID(B2), State::S0); + cell->setPort(ID(A3), State::S0); + cell->setPort(ID(B3), State::S0); + cell->setPort(ID(A4), State::S0); + cell->setPort(ID(B4), State::S0); j = 1; } else { if (c.second.at(i)->hasPort(ID(CO))) From cf21b48bfd60dccaeb6cf5efdace883ca80ac8e3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 7 Apr 2024 19:38:47 +0200 Subject: [PATCH 041/342] fix co on nx_cy --- techlibs/nanoxplore/arith_map.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v index 7b4534b83..39d03229d 100644 --- a/techlibs/nanoxplore/arith_map.v +++ b/techlibs/nanoxplore/arith_map.v @@ -35,6 +35,8 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO); input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; + (* force_downto *) + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; @@ -52,18 +54,18 @@ module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO); generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice NX_CY_1BIT #(.first(i==0)) alu_i ( - .CI(i==0 ? CI : CO[i-1]), + .CI(i==0 ? CI : COx[i-1]), .A(AA[i]), .B(BB[i]), .S(Y[i]), - .CO(CO[i]) + .CO(COx[i]) ); end: slice endgenerate NX_CY_1BIT alu_cout( - .CI(CO[Y_WIDTH-1]), + .CI(COx[Y_WIDTH-1]), .A(1'b0), .B(1'b0), .S(CO[Y_WIDTH-1]) From dac4f04460d6fdd7a1638aab637e41d72843a3ca Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 19 Apr 2024 18:09:47 +0200 Subject: [PATCH 042/342] add latch mapping, and remove aldff for now --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/cells_map.v | 14 +++++++------- techlibs/nanoxplore/latches_map.v | 11 +++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 3 ++- 4 files changed, 21 insertions(+), 8 deletions(-) create mode 100644 techlibs/nanoxplore/latches_map.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index f6606639e..180922a50 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -17,6 +17,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 75e7140aa..e851b86bf 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -43,13 +43,13 @@ module dff(input D, C, R, output Q); NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule -(* techmap_celltype = "$_ALDFF_[NP]P_" *) -module aldff(input D, C, L, AD, output Q); - parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_"; - localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N"; - wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q)); -endmodule +//(* techmap_celltype = "$_ALDFF_[NP]P_" *) +//module aldff(input D, C, L, AD, output Q); +// parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_"; +// localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N"; +// wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +// NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q)); +//endmodule module \$_SDFF_PP0_ (input D, C, R, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; diff --git a/techlibs/nanoxplore/latches_map.v b/techlibs/nanoxplore/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/techlibs/nanoxplore/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 975f78cae..edbd67f26 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -294,7 +294,8 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffs")) { - run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0"); + run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"); //-cell $_ALDFF_?P_ 0 + run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("clean -purge"); From 1591d258a9302e97cedcb9d31241025d02338e4e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Apr 2024 14:06:03 +0200 Subject: [PATCH 043/342] Made NX_CY model more robust --- techlibs/nanoxplore/cells_sim.v | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 9c3cace47..3af9dd539 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -40,7 +40,15 @@ endmodule module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); parameter add_carry = 0; -assign {CO, S4, S3, S2, S1} = {A4, A3, A2, A1} + {B4, B3, B2, B1} + CI; +wire CI_1; +wire CO1, CO2, CO3; + +assign CI_1 = (add_carry==2) ? CI : ((add_carry==1) ? 1'b1 : 1'b0); + +assign { CO1, S1 } = A1 + B1 + CI_1; +assign { CO2, S2 } = A2 + B2 + CO1; +assign { CO3, S3 } = A3 + B3 + CO2; +assign { CO, S4 } = A4 + B4 + CO3; endmodule From 4cb8e6262629d361f65e79fbeb2c4acde75366fb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Apr 2024 11:01:27 +0200 Subject: [PATCH 044/342] Properly map ff ram --- techlibs/nanoxplore/synth_nanoxplore.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index edbd67f26..de422ae9c 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -269,10 +269,9 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffram")) { - //run("opt -fast -mux_undef -undriven -fine"); + run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); - run("opt -full"); - //run("opt -undriven -fine -mux_undef"); + run("opt -undriven -fine -mux_undef"); } if (check_label("map_gates")) From 606439b44c417773453694e69a940410e0bebe1a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Apr 2024 11:28:03 +0200 Subject: [PATCH 045/342] do not leave NX_RAM empty to prevent removing it --- techlibs/nanoxplore/brams_map.v | 12 ++++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 1 + 2 files changed, 13 insertions(+) diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v index 04b6134c3..b025a6782 100644 --- a/techlibs/nanoxplore/brams_map.v +++ b/techlibs/nanoxplore/brams_map.v @@ -29,4 +29,16 @@ input [12:0] PORT_B_ADDR; input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; +NX_RAM_WRAP #( +) _TECHMAP_REPLACE_ ( + .ACK(PORT_A_CLK), + .AA(PORT_A_ADDR), + .AI(PORT_A_WR_DATA), + .AO(PORT_A_RD_DATA), + + .BCK(PORT_B_CLK), + .BA(PORT_B_ADDR), + .BI(PORT_B_WR_DATA), + .BO(PORT_B_RD_DATA) +); endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index de422ae9c..e34ae212e 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -264,6 +264,7 @@ struct SynthNanoXplorePass : public ScriptPass args += " [-no-auto-block] [-no-auto-distributed]"; run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v"); + run("techmap -map +/nanoxplore/cells_wrap.v t:NX_RAM*"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*"); } From 94675a5e0b7b00776244592f424d906a56430389 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Apr 2024 08:06:01 +0200 Subject: [PATCH 046/342] Fix dff simulation model --- techlibs/nanoxplore/cells_sim.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 3af9dd539..de3cffcc8 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -25,14 +25,14 @@ initial begin end wire clock = CK ^ dff_edge; -wire load = (dff_type == 2) ? (dff_load ? L : 1'bx) : dff_type; +wire load = dff_load ? L : 1'b1; wire async_reset = !dff_sync && dff_init && R; wire sync_reset = dff_sync && dff_init && R; always @(posedge clock, posedge async_reset) - if (async_reset) O <= load; - else if (sync_reset) O <= load; - else O <= I; + if (async_reset) O <= dff_type; + else if (sync_reset) O <= dff_type; + else if (load) O <= I; endmodule From 0c4bbf7e4b59c3688e9cf67bff52892bd2394a2c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Apr 2024 08:06:32 +0200 Subject: [PATCH 047/342] Fix existing DFF mapping and add new types --- techlibs/nanoxplore/cells_map.v | 61 +++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 21 deletions(-) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index e851b86bf..73680df59 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -35,38 +35,57 @@ module \$lut (A, Y); endmodule (* techmap_celltype = "$_DFF_[NP]P[01]_" *) -module dff(input D, C, R, output Q); - parameter _TECHMAP_CELLTYPE = "$_DFF_PP1_"; - localparam dff_edge = _TECHMAP_CELLTYPE[6*8 +: 8] == "N"; - localparam dff_type = _TECHMAP_CELLTYPE[8*8 +: 8] == "1"; +module \$_DFF_xxxx_ (input D, C, R, output Q); + parameter _TECHMAP_CELLTYPE_ = ""; + localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N"; + localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); endmodule -//(* techmap_celltype = "$_ALDFF_[NP]P_" *) -//module aldff(input D, C, L, AD, output Q); -// parameter _TECHMAP_CELLTYPE = "$_ALDFF_PP_"; -// localparam dff_edge = _TECHMAP_CELLTYPE[8*8 +: 8] == "N"; -// wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; -// NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(2)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(AD), .R(L), .O(Q)); -//endmodule - -module \$_SDFF_PP0_ (input D, C, R, output Q); +(* techmap_celltype = "$_SDFF_[NP]P[01]_" *) +module \$_SDFF_xxxx_ (input D, C, R, output Q); + parameter _TECHMAP_CELLTYPE_ = ""; + localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N"; + localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); endmodule -module \$_SDFF_PP1_ (input D, C, R, output Q); +(* techmap_celltype = "$_DFFE_[NP]P[01]P_" *) +module \$_DFFE_xxxx_ (input D, C, R, E, output Q); + parameter _TECHMAP_CELLTYPE_ = ""; + localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N"; + localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); endmodule -module \$_SDFF_NP0_ (input D, C, R, output Q); +(* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *) +module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); + parameter _TECHMAP_CELLTYPE_ = ""; + localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N"; + localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); endmodule -module \$_SDFF_NP1_ (input D, C, R, output Q); +module \$_DFF_P_ (input D, C, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); +endmodule + +module \$_DFF_N_ (input D, C, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); +endmodule + +module \$_DFFE_PP_ (input D, C, E, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); +endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; + NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); endmodule From 198fc963ca713b3798ce9fce1872b41df8448fe8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Apr 2024 08:18:04 +0200 Subject: [PATCH 048/342] Add new DFF types, and added "-nodffe" option --- techlibs/nanoxplore/synth_nanoxplore.cc | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index e34ae212e..1f6bc658c 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -73,6 +73,9 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with L in output netlist\n"); + log("\n"); log(" -norfram\n"); log(" do not use Register File RAM cells in output netlist\n"); log("\n"); @@ -97,7 +100,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad, no_rw_check; + bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, iopad, no_rw_check; std::string postfix; void clear_flags() override @@ -108,6 +111,7 @@ struct SynthNanoXplorePass : public ScriptPass flatten = true; abc9 = false; nocy = false; + nodffe = false; norfram = false; nobram = false; nodsp = false; @@ -160,6 +164,10 @@ struct SynthNanoXplorePass : public ScriptPass nocy = true; continue; } + if (args[argidx] == "-nodffe") { + nodffe = true; + continue; + } if (args[argidx] == "-norfram") { norfram = true; continue; @@ -294,7 +302,14 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffs")) { - run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0 -cell $_DLATCH_?_ x"); //-cell $_ALDFF_?P_ 0 + std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0"; + if (help_mode) { + dfflegalize_args += " [-cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0]"; + } else if (!nodffe) { + dfflegalize_args += " -cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0"; + } + dfflegalize_args += " -cell $_DLATCH_?_ x"; + run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); run("opt_expr -undriven -mux_undef"); From cb45f8b69df0699196f19f842252246aac05a318 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 30 Apr 2024 10:35:45 +0200 Subject: [PATCH 049/342] Fixed of mapping and initialization --- techlibs/nanoxplore/cells_map.v | 2 +- techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 73680df59..8e27b6992 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -85,7 +85,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q); NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); endmodule -module \$_DFFE_NN_ (input D, C, E, output Q); +module \$_DFFE_NP_ (input D, C, E, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 1f6bc658c..3b8351abc 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffs")) { - std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ 0 -cell $_SDFF_?P?_ 0"; + std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P0_ 0 -cell $_SDFF_?P0_ 0"; if (help_mode) { - dfflegalize_args += " [-cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0]"; + dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0]"; } else if (!nodffe) { - dfflegalize_args += " -cell $_DFFE_PP_ 0 -cell $_DFFE_NN_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFFE_?P?P_ 0"; + dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0"; } dfflegalize_args += " -cell $_DLATCH_?_ x"; run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); From dc16bdd85bb931a9111678fc5ce9225688cd3d90 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 30 Apr 2024 13:29:03 +0200 Subject: [PATCH 050/342] DFF reset and context must be in sync --- techlibs/nanoxplore/cells_map.v | 8 ++++---- techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 8e27b6992..8d6fb09fc 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -40,7 +40,7 @@ module \$_DFF_xxxx_ (input D, C, R, output Q); localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N"; localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); endmodule (* techmap_celltype = "$_SDFF_[NP]P[01]_" *) @@ -49,7 +49,7 @@ module \$_SDFF_xxxx_ (input D, C, R, output Q); localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N"; localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q)); endmodule (* techmap_celltype = "$_DFFE_[NP]P[01]P_" *) @@ -58,7 +58,7 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q); localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N"; localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); endmodule (* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *) @@ -67,7 +67,7 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N"; localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1"; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); + NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q)); endmodule module \$_DFF_P_ (input D, C, output Q); diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 3b8351abc..38f1d2f22 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffs")) { - std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P0_ 0 -cell $_SDFF_?P0_ 0"; + std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; if (help_mode) { - dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0]"; + dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]"; } else if (!nodffe) { - dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P0P_ 0 -cell $_SDFFE_?P0P_ 0"; + dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"; } dfflegalize_args += " -cell $_DLATCH_?_ x"; run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); From 9a9190b67d919598e31aad163040e6f429e1abd9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 30 Apr 2024 13:40:35 +0200 Subject: [PATCH 051/342] enable dff context initialization --- techlibs/nanoxplore/cells_map.v | 12 ++++++++---- techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++--- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 8d6fb09fc..39df93ee0 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -71,21 +71,25 @@ module \$_SDFFE_xxxx_ (input D, C, R, E, output Q); endmodule module \$_DFF_P_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); + NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); endmodule module \$_DFF_N_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); + NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); + NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); endmodule module \$_DFFE_NP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'b0; wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; - NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); + NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q)); endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 38f1d2f22..3842877e4 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -302,11 +302,11 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ffs")) { - std::string dfflegalize_args = " -cell $_DFF_?_ 0 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; + std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; if (help_mode) { - dfflegalize_args += " [-cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]"; + dfflegalize_args += " [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]"; } else if (!nodffe) { - dfflegalize_args += " -cell $_DFFE_?P_ 0 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"; + dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"; } dfflegalize_args += " -cell $_DLATCH_?_ x"; run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); From 645888cff5ca6b1a91afb968db1a2b3a5a90a0a5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 6 May 2024 15:00:06 +0200 Subject: [PATCH 052/342] cleanup --- techlibs/nanoxplore/nx_carry.cc | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index a61921e05..08701b44e 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -83,15 +83,6 @@ static void nx_carry_chain(Module *module) if (c.second.at(0)->getPort(ID(CI)).is_wire()) { cell = module->addCell(NEW_ID, ID(NX_CY)); cell->setPort(ID(CI), State::S0); - // Set all inputs on 0 - cell->setPort(ID(A1), State::S0); - cell->setPort(ID(B1), State::S0); - cell->setPort(ID(A2), State::S0); - cell->setPort(ID(B2), State::S0); - cell->setPort(ID(A3), State::S0); - cell->setPort(ID(B3), State::S0); - cell->setPort(ID(A4), State::S0); - cell->setPort(ID(B4), State::S0); cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); cell->setPort(names_B[0], State::S0); @@ -103,15 +94,6 @@ static void nx_carry_chain(Module *module) cell = module->addCell(NEW_ID, ID(NX_CY)); SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit(); cell->setPort(ID(CI), ci); - // Set all inputs on 0 - cell->setPort(ID(A1), State::S0); - cell->setPort(ID(B1), State::S0); - cell->setPort(ID(A2), State::S0); - cell->setPort(ID(B2), State::S0); - cell->setPort(ID(A3), State::S0); - cell->setPort(ID(B3), State::S0); - cell->setPort(ID(A4), State::S0); - cell->setPort(ID(B4), State::S0); if (ci.is_wire()) { cell->setParam(ID(add_carry), Const(2,2)); } else { @@ -132,13 +114,6 @@ static void nx_carry_chain(Module *module) cell->setPort(ID(CI), State::S0); cell->setPort(ID(A1), new_co); cell->setPort(ID(B1), State::S0); - // Set all inputs on 0 - cell->setPort(ID(A2), State::S0); - cell->setPort(ID(B2), State::S0); - cell->setPort(ID(A3), State::S0); - cell->setPort(ID(B3), State::S0); - cell->setPort(ID(A4), State::S0); - cell->setPort(ID(B4), State::S0); j = 1; } else { if (c.second.at(i)->hasPort(ID(CO))) From 34f08bc639b56bf0b75c618b52e4ba1820e29d70 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 6 May 2024 15:25:29 +0200 Subject: [PATCH 053/342] Enable nanoxplore tests --- Makefile | 1 + tests/arch/nanoxplore/adffs.ys | 3 ++- tests/arch/nanoxplore/dffs.ys | 3 +-- tests/arch/nanoxplore/fsm.ys | 2 +- tests/arch/nanoxplore/latches.ys | 10 ++++------ 5 files changed, 9 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index a2803ed59..14a37b995 100644 --- a/Makefile +++ b/Makefile @@ -877,6 +877,7 @@ endif +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT) +cd tests/arch/gowin && bash run-test.sh $(SEEDOPT) +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) + +cd tests/arch/nanoxplore && bash run-test.sh $(SEEDOPT) +cd tests/arch/nexus && bash run-test.sh $(SEEDOPT) +cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT) +cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT) diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys index 6a4f63ad7..9f4e1fac7 100644 --- a/tests/arch/nanoxplore/adffs.ys +++ b/tests/arch/nanoxplore/adffs.ys @@ -30,8 +30,9 @@ equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # e design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF +select -assert-count 1 t:NX_LUT -select -assert-none t:NX_DFF %% t:* %D +select -assert-none t:NX_DFF t:NX_LUT %% t:* %D design -load read diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys index ba7dff41c..898765408 100644 --- a/tests/arch/nanoxplore/dffs.ys +++ b/tests/arch/nanoxplore/dffs.ys @@ -17,6 +17,5 @@ equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # e design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF -select -assert-count 1 t:NX_LUT -select -assert-none t:NX_DFF t:NX_LUT %% t:* %D +select -assert-none t:NX_DFF %% t:* %D diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys index ee00be4e1..8582d111c 100644 --- a/tests/arch/nanoxplore/fsm.ys +++ b/tests/arch/nanoxplore/fsm.ys @@ -12,5 +12,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:NX_DFF -select -assert-count 13 t:NX_LUT +select -assert-count 14 t:NX_LUT select -assert-none t:NX_DFF t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys index 32609dbce..4625348f9 100644 --- a/tests/arch/nanoxplore/latches.ys +++ b/tests/arch/nanoxplore/latches.ys @@ -6,9 +6,9 @@ proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_nanoxplore cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:NX_DFF +select -assert-count 1 t:NX_LUT -select -assert-none t:NX_DFF %% t:* %D +select -assert-none t:NX_LUT %% t:* %D design -load read @@ -18,9 +18,8 @@ proc synth_nanoxplore cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT -select -assert-count 1 t:NX_DFF -select -assert-none t:NX_LUT t:NX_DFF %% t:* %D +select -assert-none t:NX_LUT %% t:* %D design -load read @@ -30,6 +29,5 @@ proc synth_nanoxplore cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:NX_LUT -select -assert-count 1 t:NX_DFF -select -assert-none t:NX_LUT t:NX_DFF %% t:* %D +select -assert-none t:NX_LUT %% t:* %D From 41ae513d6090539d0bff85c18c307adf2dda073d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 May 2024 09:06:10 +0200 Subject: [PATCH 054/342] support other I/O configurations --- techlibs/nanoxplore/io_map.v | 7 +++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 6 +++--- tests/arch/nanoxplore/tribuf.ys | 7 ++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/techlibs/nanoxplore/io_map.v b/techlibs/nanoxplore/io_map.v index 42fac4619..edbb0437b 100644 --- a/techlibs/nanoxplore/io_map.v +++ b/techlibs/nanoxplore/io_map.v @@ -6,3 +6,10 @@ module \$__BEYOND_OBUF (output PAD, input I); NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1)); endmodule +module \$__BEYOND_TOBUF (output PAD, input I, input C); + NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(C)); +endmodule + +module \$__BEYOND_IOBUF (output PAD, input I, output O, output C); + NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .O(O), .C(C)); +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 3842877e4..52d025603 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -292,10 +292,10 @@ struct SynthNanoXplorePass : public ScriptPass run("nx_carry"); } if (help_mode || iopad) { - run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -inpad $__BEYOND_IBUF O:PAD A:top", "(only if '-iopad')"); + run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')"); run("techmap -map +/nanoxplore/io_map.v"); - run("attrmvcp -attr LOC t:NX_IOB_O n:*"); - run("attrmvcp -attr LOC -driven t:NX_IOB_I n:*"); + run("attrmvcp -attr LOC t:NX_IOB_O t:NX_IOB n:*"); + run("attrmvcp -attr LOC -driven t:NX_IOB_I t:NX_IOB n:*"); } run("opt -fast"); } diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys index c72e2e1ad..e55764f01 100644 --- a/tests/arch/nanoxplore/tribuf.ys +++ b/tests/arch/nanoxplore/tribuf.ys @@ -4,9 +4,10 @@ proc tribuf flatten synth -equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore -iopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D +select -assert-count 1 t:NX_IOB +select -assert-count 2 t:NX_IOB_I +select -assert-none t:NX_IOB t:NX_IOB_I %% t:* %D From 04d36721213556403d6464e521e5fa382e63ee6d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 9 May 2024 14:01:53 +0200 Subject: [PATCH 055/342] No need for LOC --- techlibs/nanoxplore/synth_nanoxplore.cc | 2 -- 1 file changed, 2 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 52d025603..9dd8011cc 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -294,8 +294,6 @@ struct SynthNanoXplorePass : public ScriptPass if (help_mode || iopad) { run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')"); run("techmap -map +/nanoxplore/io_map.v"); - run("attrmvcp -attr LOC t:NX_IOB_O t:NX_IOB n:*"); - run("attrmvcp -attr LOC -driven t:NX_IOB_I t:NX_IOB n:*"); } run("opt -fast"); } From f9f68c3cd1504fc6b7959a4d976628ac68795b28 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 10 May 2024 11:15:56 +0200 Subject: [PATCH 056/342] Split sim models into multiple files and implement few --- techlibs/nanoxplore/Makefile.inc | 3 + techlibs/nanoxplore/cells_bb.v | 45 +++++++-------- techlibs/nanoxplore/cells_bb_u.v | 11 ---- techlibs/nanoxplore/cells_sim.v | 76 +++++++++---------------- techlibs/nanoxplore/cells_sim_l.v | 0 techlibs/nanoxplore/cells_sim_m.v | 0 techlibs/nanoxplore/cells_sim_u.v | 30 ++++++++++ techlibs/nanoxplore/synth_nanoxplore.cc | 2 +- 8 files changed, 84 insertions(+), 83 deletions(-) create mode 100644 techlibs/nanoxplore/cells_sim_l.v create mode 100644 techlibs/nanoxplore/cells_sim_m.v create mode 100644 techlibs/nanoxplore/cells_sim_u.v diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 180922a50..3370adef7 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -12,6 +12,9 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 42953b6b2..2f6ae1ec2 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -28,12 +28,12 @@ //endmodule // Bypass mode of NX_GCK_U -(* blackbox *) -module NX_BD(I, O); - input I; - output O; - parameter mode = "global_lowskew"; -endmodule +//(* blackbox *) +//module NX_BD(I, O); +// input I; +// output O; +// parameter mode = "global_lowskew"; +//endmodule //(* blackbox *) //module NX_DFF(I, CK, L, R, O); @@ -51,12 +51,11 @@ endmodule //endmodule // Special mode of NX_DFF -(* blackbox *) -module NX_BFF(I, O); - input I; - output O; -endmodule - +//(* blackbox *) +//module NX_BFF(I, O); +// input I; +// output O; +//endmodule (* blackbox *) module NX_DFR(I, CK, L, R, O); @@ -79,17 +78,17 @@ module NX_DFR(I, CK, L, R, O); endmodule // Special mode of NX_DFR -(* blackbox *) -module NX_BFR(I, O); - input I; - output O; - parameter data_inv = 1'b0; - parameter iobname = ""; - parameter location = ""; - parameter mode = 0; - parameter path = 0; - parameter ring = 0; -endmodule +//(* blackbox *) +//module NX_BFR(I, O); +// input I; +// output O; +// parameter data_inv = 1'b0; +// parameter iobname = ""; +// parameter location = ""; +// parameter mode = 0; +// parameter path = 0; +// parameter ring = 0; +//endmodule (* blackbox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 5c1e8bcb0..2cc16f410 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -1,14 +1,3 @@ -(* blackbox *) -module NX_GCK_U(SI1, SI2, CMD, SO); - input CMD; - input SI1; - input SI2; - output SO; - parameter inv_in = 1'b0; - parameter inv_out = 1'b0; - parameter std_mode = "BYPASS"; -endmodule - (* blackbox *) module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO , BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4 diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index de3cffcc8..392ee18e4 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -52,54 +52,6 @@ assign { CO, S4 } = A4 + B4 + CO3; endmodule -(* abc9_box, lib_whitebox *) -module NX_XRFB_64x18(input WCK, input [17:0] I, input [5:0] RA, WA, input WE, WEA, output [17:0] O); - -parameter wck_edge = 1'b0; -parameter mem_ctxt = 1152'b0; - -reg [17:0] mem [63:0]; - -integer i; -initial begin - for (i = 0; i < 64; i = i + 1) - mem[i] = mem_ctxt[18*i +: 18]; -end - -wire clock = WCK ^ wck_edge; - -always @(posedge clock) - if (WE && WEA) - mem[WA] <= I; - -assign O = mem[RA]; - -endmodule - -(* abc9_box, lib_whitebox *) -module NX_XRFB_32x36(input WCK, input [35:0] I, input [4:0] RA, WA, input WE, WEA, output [35:0] O); - -parameter wck_edge = 1'b0; -parameter mem_ctxt = 1152'b0; - -reg [35:0] mem [31:0]; - -integer i; -initial begin - for (i = 0; i < 32; i = i + 1) - mem[i] = mem_ctxt[36*i +: 36]; -end - -wire clock = WCK ^ wck_edge; - -always @(posedge clock) - if (WE && WEA) - mem[WA] <= I; - -assign O = mem[RA]; - -endmodule - module NX_IOB(I, C, T, O, IO); input C; input I; @@ -205,3 +157,31 @@ module NX_CY_1BIT(CI, A, B, S, CO); assign {CO, S} = A + B + CI; endmodule + +module NX_BD(I, O); + input I; + output O; + parameter mode = "global_lowskew"; + + assign O = I; +endmodule + +module NX_BFF(I, O); + input I; + output O; + + assign O = I; +endmodule + +module NX_BFR(I, O); + input I; + output O; + parameter data_inv = 1'b0; + parameter iobname = ""; + parameter location = ""; + parameter mode = 0; + parameter path = 0; + parameter ring = 0; + + assign O = data_inv ? ~I : I; +endmodule diff --git a/techlibs/nanoxplore/cells_sim_l.v b/techlibs/nanoxplore/cells_sim_l.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_sim_m.v b/techlibs/nanoxplore/cells_sim_m.v new file mode 100644 index 000000000..e69de29bb diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v new file mode 100644 index 000000000..794dd4e6a --- /dev/null +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -0,0 +1,30 @@ +module NX_GCK_U(SI1, SI2, CMD, SO); + input CMD; + input SI1; + input SI2; + output SO; + parameter inv_in = 1'b0; + parameter inv_out = 1'b0; + parameter std_mode = "BYPASS"; + + wire SI1_int = inv_in ? ~SI1 : SI1; + wire SI2_int = inv_in ? ~SI2 : SI2; + + wire SO_int; + generate if (std_mode == "BYPASS") begin + assign SO_int = SI1_int; + end + else if (std_mode == "MUX") begin + assign SO_int = CMD ? SI1_int : SI2_int; + end + else if (std_mode == "CKS") begin + assign SO_int = CMD ? SI1_int : 1'b0; + end + else if (std_mode == "CSC") begin + assign SO_int = CMD; + end + else + $error("Unrecognised std_mode"); + endgenerate + assign SO = inv_out ? ~SO_int : SO_int; +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 9dd8011cc..054ca5b0d 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -229,7 +229,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("begin")) { - run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); + run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v"); run("techmap -map +/nanoxplore/cells_wrap.v"); run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); From 11449ec493a1d1f84d38423bbb40a35bd9eb949c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 15 May 2024 15:55:26 +0200 Subject: [PATCH 057/342] Cleanup not connected ports --- techlibs/nanoxplore/cells_wrap_u.v | 334 ++++++++++++++--------------- 1 file changed, 167 insertions(+), 167 deletions(-) diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index b753c5466..74adfaa51 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -10,7 +10,7 @@ NX_GCK_U #( ) _TECHMAP_REPLACE_ ( .CMD(CMD), .SI1(CKI), - .SI2(1'b0), + .SI2(), .SO(CKO) ); endmodule @@ -1495,24 +1495,24 @@ module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA); .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(O[0]), .O2(O[1]), .O3(O[2]), @@ -1536,17 +1536,17 @@ module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA); .RA3(RA[2]), .RA4(RA[3]), .RA5(RA[4]), - .RA6(1'b0), - .RA7(1'b0), - .RA8(1'b0), - .RA9(1'b0), - .RA10(1'b0), + .RA6(), + .RA7(), + .RA8(), + .RA9(), + .RA10(), .WA1(WA[0]), .WA2(WA[1]), .WA3(WA[2]), .WA4(WA[3]), .WA5(WA[4]), - .WA6(1'b0), + .WA6(), .WE(WE), .WEA(WEA) ); @@ -1587,24 +1587,24 @@ module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA); .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(O[0]), .O2(O[1]), .O3(O[2]), @@ -1623,22 +1623,22 @@ module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA); .O16(O[15]), .O17(O[16]), .O18(O[17]), - .RA1(1'b0), - .RA2(1'b0), - .RA3(1'b0), - .RA4(1'b0), - .RA5(1'b0), - .RA6(1'b0), - .RA7(1'b0), - .RA8(1'b0), - .RA9(1'b0), - .RA10(1'b0), + .RA1(), + .RA2(), + .RA3(), + .RA4(), + .RA5(), + .RA6(), + .RA7(), + .RA8(), + .RA9(), + .RA10(), .WA1(WA[0]), .WA2(WA[1]), .WA3(WA[2]), .WA4(WA[3]), .WA5(WA[4]), - .WA6(1'b0), + .WA6(), .WE(WE), .WEA(WEA) ); @@ -1679,24 +1679,24 @@ module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(O[0]), .O2(O[1]), .O3(O[2]), @@ -1721,10 +1721,10 @@ module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA); .RA4(RA[3]), .RA5(RA[4]), .RA6(RA[5]), - .RA7(1'b0), - .RA8(1'b0), - .RA9(1'b0), - .RA10(1'b0), + .RA7(), + .RA8(), + .RA9(), + .RA10(), .WA1(WA[0]), .WA2(WA[1]), .WA3(WA[2]), @@ -1830,17 +1830,17 @@ module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA); .RA3(RA[2]), .RA4(RA[3]), .RA5(RA[4]), - .RA6(1'b0), - .RA7(1'b0), - .RA8(1'b0), - .RA9(1'b0), - .RA10(1'b0), + .RA6(), + .RA7(), + .RA8(), + .RA9(), + .RA10(), .WA1(WA[0]), .WA2(WA[1]), .WA3(WA[2]), .WA4(WA[3]), .WA5(WA[4]), - .WA6(1'b0), + .WA6(), .WE(WE), .WEA(WEA) ); @@ -1883,24 +1883,24 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(AO[0]), .O2(AO[1]), .O3(AO[2]), @@ -1952,7 +1952,7 @@ module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA); .WA3(WA[2]), .WA4(WA[3]), .WA5(WA[4]), - .WA6(1'b0), + .WA6(), .WE(WE), .WEA(WEA) ); @@ -2043,26 +2043,26 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .I14(I14), .I15(I15), .I16(I16), - .I17(1'b0), - .I18(1'b0), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I17(), + .I18(), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(D[0]), .O2(D[1]), .O3(D[2]), @@ -2085,10 +2085,10 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .RA4(RA4), .RA5(RA5), .RA6(RA6), - .RA7(1'b0), - .RA8(1'b0), - .RA9(1'b0), - .RA10(1'b0), + .RA7(), + .RA8(), + .RA9(), + .RA10(), .WA1(WA1), .WA2(WA2), .WA3(WA3), @@ -2096,7 +2096,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .WA5(WA5), .WA6(WA6), .WE(WE), - .WEA(1'b0) + .WEA() ); genvar i; @@ -2109,7 +2109,7 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, .CK(RCK), .I(D[i]), .L(RE), - .R(1'b0), + .R(), .O(Q[i]) ); end endgenerate; @@ -2187,24 +2187,24 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(O[0]), .O2(O[1]), .O3(O[2]), @@ -2230,7 +2230,7 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, .WAI4(WAI[3]), .WAI5(WAI[4]), .WAI6(WAI[5]), - .WAI7(1'b0), + .WAI7(), .WRSTO(WRSTO), .WAO1(WAO[0]), .WAO2(WAO[1]), @@ -2246,7 +2246,7 @@ module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, .RAI4(RAI[3]), .RAI5(RAI[4]), .RAI6(RAI[5]), - .RAI7(1'b0), + .RAI7(), .RRSTO(RRSTO), .RAO1(RAO[0]), .RAO2(RAO[1]), @@ -2309,24 +2309,24 @@ module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, .I16(I[15]), .I17(I[16]), .I18(I[17]), - .I19(1'b0), - .I20(1'b0), - .I21(1'b0), - .I22(1'b0), - .I23(1'b0), - .I24(1'b0), - .I25(1'b0), - .I26(1'b0), - .I27(1'b0), - .I28(1'b0), - .I29(1'b0), - .I30(1'b0), - .I31(1'b0), - .I32(1'b0), - .I33(1'b0), - .I34(1'b0), - .I35(1'b0), - .I36(1'b0), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), .O1(O[0]), .O2(O[1]), .O3(O[2]), @@ -2494,7 +2494,7 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, .WAI4(WAI[3]), .WAI5(WAI[4]), .WAI6(WAI[5]), - .WAI7(1'b0), + .WAI7(), .WAO1(WAO[0]), .WAO2(WAO[1]), .WAO3(WAO[2]), @@ -2509,7 +2509,7 @@ module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, .RAI4(RAI[3]), .RAI5(RAI[4]), .RAI6(RAI[5]), - .RAI7(1'b0), + .RAI7(), .RAO1(RAO[0]), .RAO2(RAO[1]), .RAO3(RAO[2]), From 7e4aef06e469de70baf73d8e62ade29ec4e6beb1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 16 May 2024 17:15:55 +0200 Subject: [PATCH 058/342] Add register file mapping --- techlibs/nanoxplore/rf_rams_map_u.v | 339 ++++++++++++++++++++++++++-- techlibs/nanoxplore/rf_rams_u.txt | 66 +++++- tests/arch/nanoxplore/lutram.ys | 64 +++++- 3 files changed, 429 insertions(+), 40 deletions(-) diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v index 94d5df097..b55d3e594 100644 --- a/techlibs/nanoxplore/rf_rams_map_u.v +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -1,50 +1,339 @@ -module $__NX_XRFB_64x18_ ( +module $__NX_RFB_U_DPREG_ ( input PORT_W_CLK, - input [5:0] PORT_W_ADDR, - input [5:0] PORT_R_ADDR, - input [17:0] PORT_W_WR_DATA, + input [6-1:0] PORT_W_ADDR, + input [6-1:0] PORT_R_ADDR, + input [36-1:0] PORT_W_WR_DATA, input PORT_W_WR_EN, - output [17:0] PORT_R_RD_DATA + output [36-1:0] PORT_R_RD_DATA ); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; - - NX_XRFB_64x18 #( + parameter OPTION_MODE = 0; + parameter WIDTH = 18; + parameter BITS_USED = 0; + + // mode 0 - DPREG + // mode 2 - NX_XRFB_64x18 + // mode 3 - NX_XRFB_32x36 + NX_RFB_U #( + .mode(OPTION_MODE), .mem_ctxt(INIT), - .wck_edge(~PORT_W_CLK_POL) + .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1) ) _TECHMAP_REPLACE_ ( .WCK(PORT_W_CLK), - .I(PORT_W_WR_DATA), - .RA(PORT_R_ADDR), - .WA(PORT_W_ADDR), + .I1(PORT_W_WR_DATA[0]), + .I2(PORT_W_WR_DATA[1]), + .I3(PORT_W_WR_DATA[2]), + .I4(PORT_W_WR_DATA[3]), + .I5(PORT_W_WR_DATA[4]), + .I6(PORT_W_WR_DATA[5]), + .I7(PORT_W_WR_DATA[6]), + .I8(PORT_W_WR_DATA[7]), + .I9(PORT_W_WR_DATA[8]), + .I10(PORT_W_WR_DATA[9]), + .I11(PORT_W_WR_DATA[10]), + .I12(PORT_W_WR_DATA[11]), + .I13(PORT_W_WR_DATA[12]), + .I14(PORT_W_WR_DATA[13]), + .I15(PORT_W_WR_DATA[14]), + .I16(PORT_W_WR_DATA[15]), + .I17(PORT_W_WR_DATA[16]), + .I18(PORT_W_WR_DATA[17]), + .I19(PORT_W_WR_DATA[18]), + .I20(PORT_W_WR_DATA[19]), + .I21(PORT_W_WR_DATA[20]), + .I22(PORT_W_WR_DATA[21]), + .I23(PORT_W_WR_DATA[22]), + .I24(PORT_W_WR_DATA[23]), + .I25(PORT_W_WR_DATA[24]), + .I26(PORT_W_WR_DATA[25]), + .I27(PORT_W_WR_DATA[26]), + .I28(PORT_W_WR_DATA[27]), + .I29(PORT_W_WR_DATA[28]), + .I30(PORT_W_WR_DATA[29]), + .I31(PORT_W_WR_DATA[30]), + .I32(PORT_W_WR_DATA[31]), + .I33(PORT_W_WR_DATA[32]), + .I34(PORT_W_WR_DATA[33]), + .I35(PORT_W_WR_DATA[34]), + .I36(PORT_W_WR_DATA[35]), + .O1(PORT_R_RD_DATA[0]), + .O2(PORT_R_RD_DATA[1]), + .O3(PORT_R_RD_DATA[2]), + .O4(PORT_R_RD_DATA[3]), + .O5(PORT_R_RD_DATA[4]), + .O6(PORT_R_RD_DATA[5]), + .O7(PORT_R_RD_DATA[6]), + .O8(PORT_R_RD_DATA[7]), + .O9(PORT_R_RD_DATA[8]), + .O10(PORT_R_RD_DATA[9]), + .O11(PORT_R_RD_DATA[10]), + .O12(PORT_R_RD_DATA[11]), + .O13(PORT_R_RD_DATA[12]), + .O14(PORT_R_RD_DATA[13]), + .O15(PORT_R_RD_DATA[14]), + .O16(PORT_R_RD_DATA[15]), + .O17(PORT_R_RD_DATA[16]), + .O18(PORT_R_RD_DATA[17]), + .O19(PORT_R_RD_DATA[18]), + .O20(PORT_R_RD_DATA[19]), + .O21(PORT_R_RD_DATA[20]), + .O22(PORT_R_RD_DATA[21]), + .O23(PORT_R_RD_DATA[22]), + .O24(PORT_R_RD_DATA[23]), + .O25(PORT_R_RD_DATA[24]), + .O26(PORT_R_RD_DATA[25]), + .O27(PORT_R_RD_DATA[26]), + .O28(PORT_R_RD_DATA[27]), + .O29(PORT_R_RD_DATA[28]), + .O30(PORT_R_RD_DATA[29]), + .O31(PORT_R_RD_DATA[30]), + .O32(PORT_R_RD_DATA[31]), + .O33(PORT_R_RD_DATA[32]), + .O34(PORT_R_RD_DATA[33]), + .O35(PORT_R_RD_DATA[34]), + .O36(PORT_R_RD_DATA[35]), + .RA1(PORT_R_ADDR[0]), + .RA2(PORT_R_ADDR[1]), + .RA3(PORT_R_ADDR[2]), + .RA4(PORT_R_ADDR[3]), + .RA5(PORT_R_ADDR[4]), + .RA6(PORT_R_ADDR[5]), + .RA7(), + .RA8(), + .RA9(), + .RA10(), + .WA1(PORT_W_ADDR[0]), + .WA2(PORT_W_ADDR[1]), + .WA3(PORT_W_ADDR[2]), + .WA4(PORT_W_ADDR[3]), + .WA5(PORT_W_ADDR[4]), + .WA6(PORT_W_ADDR[5]), .WE(PORT_W_WR_EN), - .WEA(1'b1), - .O(PORT_R_RD_DATA) + .WEA(1'b0) ); endmodule -module $__NX_XRFB_32x36_ ( +module $__NX_RFB_U_SPREG_ ( + input PORT_RW_CLK, + input [4:0] PORT_RW_ADDR, + input [17:0] PORT_RW_WR_DATA, + input PORT_RW_WR_EN, + output [17:0] PORT_RW_RD_DATA +); + parameter INIT = 1152'bx; + parameter PORT_RW_CLK_POL = 1'b1; + parameter BITS_USED = 0; + + NX_RFB_U #( + .mode(1), + .mem_ctxt(INIT), + .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1) + ) _TECHMAP_REPLACE_ ( + .WCK(PORT_RW_CLK), + .I1(PORT_RW_WR_DATA[0]), + .I2(PORT_RW_WR_DATA[1]), + .I3(PORT_RW_WR_DATA[2]), + .I4(PORT_RW_WR_DATA[3]), + .I5(PORT_RW_WR_DATA[4]), + .I6(PORT_RW_WR_DATA[5]), + .I7(PORT_RW_WR_DATA[6]), + .I8(PORT_RW_WR_DATA[7]), + .I9(PORT_RW_WR_DATA[8]), + .I10(PORT_RW_WR_DATA[9]), + .I11(PORT_RW_WR_DATA[10]), + .I12(PORT_RW_WR_DATA[11]), + .I13(PORT_RW_WR_DATA[12]), + .I14(PORT_RW_WR_DATA[13]), + .I15(PORT_RW_WR_DATA[14]), + .I16(PORT_RW_WR_DATA[15]), + .I17(PORT_RW_WR_DATA[16]), + .I18(PORT_RW_WR_DATA[17]), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), + .O1(PORT_RW_RD_DATA[0]), + .O2(PORT_RW_RD_DATA[1]), + .O3(PORT_RW_RD_DATA[2]), + .O4(PORT_RW_RD_DATA[3]), + .O5(PORT_RW_RD_DATA[4]), + .O6(PORT_RW_RD_DATA[5]), + .O7(PORT_RW_RD_DATA[6]), + .O8(PORT_RW_RD_DATA[7]), + .O9(PORT_RW_RD_DATA[8]), + .O10(PORT_RW_RD_DATA[9]), + .O11(PORT_RW_RD_DATA[10]), + .O12(PORT_RW_RD_DATA[11]), + .O13(PORT_RW_RD_DATA[12]), + .O14(PORT_RW_RD_DATA[13]), + .O15(PORT_RW_RD_DATA[14]), + .O16(PORT_RW_RD_DATA[15]), + .O17(PORT_RW_RD_DATA[16]), + .O18(PORT_RW_RD_DATA[17]), + .O19(), + .O20(), + .O21(), + .O22(), + .O23(), + .O24(), + .O25(), + .O26(), + .O27(), + .O28(), + .O29(), + .O30(), + .O31(), + .O32(), + .O33(), + .O34(), + .O35(), + .O36(), + .RA1(), + .RA2(), + .RA3(), + .RA4(), + .RA5(), + .RA6(), + .RA7(), + .RA8(), + .RA9(), + .RA10(), + .WA1(PORT_RW_ADDR[0]), + .WA2(PORT_RW_ADDR[1]), + .WA3(PORT_RW_ADDR[2]), + .WA4(PORT_RW_ADDR[3]), + .WA5(PORT_RW_ADDR[4]), + .WA6(), + .WE(PORT_RW_WR_EN), + .WEA(1'b0) + ); +endmodule + +module $__NX_XRFB_2R_1W_ ( input PORT_W_CLK, input [4:0] PORT_W_ADDR, - input [4:0] PORT_R_ADDR, - input [35:0] PORT_W_WR_DATA, + input [4:0] PORT_A_ADDR, + input [4:0] PORT_B_ADDR, + input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, - output [35:0] PORT_R_RD_DATA + output [17:0] PORT_A_RD_DATA, + output [17:0] PORT_B_RD_DATA ); parameter INIT = 1152'bx; parameter PORT_W_CLK_POL = 1'b1; + parameter BITS_USED = 0; - NX_XRFB_32x36 #( + NX_RFB_U #( + .mode(4), .mem_ctxt(INIT), - .wck_edge(~PORT_W_CLK_POL) + .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1) ) _TECHMAP_REPLACE_ ( .WCK(PORT_W_CLK), - .I(PORT_W_WR_DATA), - .RA(PORT_R_ADDR), - .WA(PORT_W_ADDR), + .I1(PORT_W_WR_DATA[0]), + .I2(PORT_W_WR_DATA[1]), + .I3(PORT_W_WR_DATA[2]), + .I4(PORT_W_WR_DATA[3]), + .I5(PORT_W_WR_DATA[4]), + .I6(PORT_W_WR_DATA[5]), + .I7(PORT_W_WR_DATA[6]), + .I8(PORT_W_WR_DATA[7]), + .I9(PORT_W_WR_DATA[8]), + .I10(PORT_W_WR_DATA[9]), + .I11(PORT_W_WR_DATA[10]), + .I12(PORT_W_WR_DATA[11]), + .I13(PORT_W_WR_DATA[12]), + .I14(PORT_W_WR_DATA[13]), + .I15(PORT_W_WR_DATA[14]), + .I16(PORT_W_WR_DATA[15]), + .I17(PORT_W_WR_DATA[16]), + .I18(PORT_W_WR_DATA[17]), + .I19(), + .I20(), + .I21(), + .I22(), + .I23(), + .I24(), + .I25(), + .I26(), + .I27(), + .I28(), + .I29(), + .I30(), + .I31(), + .I32(), + .I33(), + .I34(), + .I35(), + .I36(), + .O1(PORT_A_RD_DATA[0]), + .O2(PORT_A_RD_DATA[1]), + .O3(PORT_A_RD_DATA[2]), + .O4(PORT_A_RD_DATA[3]), + .O5(PORT_A_RD_DATA[4]), + .O6(PORT_A_RD_DATA[5]), + .O7(PORT_A_RD_DATA[6]), + .O8(PORT_A_RD_DATA[7]), + .O9(PORT_A_RD_DATA[8]), + .O10(PORT_A_RD_DATA[9]), + .O11(PORT_A_RD_DATA[10]), + .O12(PORT_A_RD_DATA[11]), + .O13(PORT_A_RD_DATA[12]), + .O14(PORT_A_RD_DATA[13]), + .O15(PORT_A_RD_DATA[14]), + .O16(PORT_A_RD_DATA[15]), + .O17(PORT_A_RD_DATA[16]), + .O18(PORT_A_RD_DATA[17]), + .O19(PORT_B_RD_DATA[0]), + .O20(PORT_B_RD_DATA[1]), + .O21(PORT_B_RD_DATA[2]), + .O22(PORT_B_RD_DATA[3]), + .O23(PORT_B_RD_DATA[4]), + .O24(PORT_B_RD_DATA[5]), + .O25(PORT_B_RD_DATA[6]), + .O26(PORT_B_RD_DATA[7]), + .O27(PORT_B_RD_DATA[8]), + .O28(PORT_B_RD_DATA[9]), + .O29(PORT_B_RD_DATA[10]), + .O30(PORT_B_RD_DATA[11]), + .O31(PORT_B_RD_DATA[12]), + .O32(PORT_B_RD_DATA[13]), + .O33(PORT_B_RD_DATA[14]), + .O34(PORT_B_RD_DATA[15]), + .O35(PORT_B_RD_DATA[16]), + .O36(PORT_B_RD_DATA[17]), + .RA1(PORT_A_ADDR[0]), + .RA2(PORT_A_ADDR[1]), + .RA3(PORT_A_ADDR[2]), + .RA4(PORT_A_ADDR[3]), + .RA5(PORT_A_ADDR[4]), + .RA6(PORT_B_ADDR[0]), + .RA7(PORT_B_ADDR[1]), + .RA8(PORT_B_ADDR[2]), + .RA9(PORT_B_ADDR[3]), + .RA10(PORT_B_ADDR[4]), + .WA1(PORT_W_ADDR[0]), + .WA2(PORT_W_ADDR[1]), + .WA3(PORT_W_ADDR[2]), + .WA4(PORT_W_ADDR[3]), + .WA5(PORT_W_ADDR[4]), + .WA6(), .WE(PORT_W_WR_EN), - .WEA(1'b1), - .O(PORT_R_RD_DATA) + .WEA(1'b0) ); -endmodule +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt index 370b62b16..7b80e2f24 100644 --- a/techlibs/nanoxplore/rf_rams_u.txt +++ b/techlibs/nanoxplore/rf_rams_u.txt @@ -1,7 +1,29 @@ -ram distributed $__NX_XRFB_64x18_ { - abits 6; - width 18; - cost 10; +# Register-File RAMs for NanoXplore NG-ULTRA + +# Dual-port RAMs. +# NX_RFB_U in mode 0 (DPREG) +# NX_RFB_U in mode 2 (NX_XRFB_64x18) +# NX_RFB_U in mode 3 (NX_XRFB_32x36) + +ram distributed $__NX_RFB_U_DPREG_ { + option "MODE" 0 { + cost 35; + widthscale 30; + abits 5; + widths 18 global; + } + option "MODE" 2 { + cost 50; + widthscale 30; + abits 6; + widths 18 global; + } + option "MODE" 3 { + cost 50; + widthscale 30; + abits 5; + widths 36 global; + } init no_undef; prune_rom; @@ -12,16 +34,36 @@ ram distributed $__NX_XRFB_64x18_ { } } -ram distributed $__NX_XRFB_32x36_ { - abits 5; - width 36; - cost 10; - init no_undef; - prune_rom; +# Single-port RAMs. +# NX_RFB_U in mode 1 (SPREG) +ram distributed $__NX_RFB_U_SPREG_ { + cost 30; + widthscale; + abits 5; + width 18; + init no_undef; + prune_rom; + port arsw "RW" { + clock anyedge; + } +} + +# Single write dual read RAMs. +# NX_RFB_U in mode 4 (NX_XRFB_2R_1W) + +ram distributed $__NX_XRFB_2R_1W_ { + cost 30; + widthscale; + abits 5; + width 18; + init no_undef; + prune_rom; port sw "W" { clock anyedge; } - port ar "R" { + port ar "A" { } -} \ No newline at end of file + port ar "B" { + } +} diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 9809da928..72f4919ea 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -1,8 +1,66 @@ +# Single-port RAMs. +# NX_RFB_U in mode 1 (SPREG) read_verilog ../common/lutram.v -hierarchy -top lutram_1w1r +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 18 synth_nanoxplore cd lutram_1w1r -select -assert-count 1 t:NX_RFB_U -select -assert-count 8 t:NX_DFF +select -assert-count 1 t:NX_RFB_U r:mode=1 %i +select -assert-count 18 t:NX_DFF select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D +# Dual-port RAMs. +# NX_RFB_U in mode 2 (NX_XRFB_64x18) +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 18 +synth_nanoxplore +cd lutram_1w1r +stat +select -assert-count 1 t:NX_RFB_U r:mode=2 %i +select -assert-count 18 t:NX_DFF +select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D + +# Dual-port RAMs. +# NX_RFB_U in mode 3 (NX_XRFB_32x36) +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 36 +synth_nanoxplore +cd lutram_1w1r +select -assert-count 1 t:NX_RFB_U r:mode=3 %i +select -assert-count 36 t:NX_DFF +select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D + +# Single write dual read RAMs. +# NX_RFB_U in mode 4 (NX_XRFB_2R_1W) +design -reset + +read_verilog < Date: Fri, 17 May 2024 09:28:07 +0200 Subject: [PATCH 059/342] Add RF initialization --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/rf_init.vh | 17 +++++++++++++++++ techlibs/nanoxplore/rf_rams_map_u.v | 16 +++++++++++----- 3 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 techlibs/nanoxplore/rf_init.vh diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 3370adef7..481429c66 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -21,6 +21,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) diff --git a/techlibs/nanoxplore/rf_init.vh b/techlibs/nanoxplore/rf_init.vh new file mode 100644 index 000000000..909a1c0cd --- /dev/null +++ b/techlibs/nanoxplore/rf_init.vh @@ -0,0 +1,17 @@ +function [9728-1:0] rf_init_to_string; + input [1152-1:0] array; + input integer blocks; + input integer width; + reg [9728-1:0] temp; // (1152+1152/18)*8 + integer i; +begin + temp = ""; + for (i = 0; i < blocks; i = i + 1) begin + if (i != 0) begin + temp = {temp, ","}; + end + temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])}; + end + rf_init_to_string = temp; +end +endfunction diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v index b55d3e594..2f572650b 100644 --- a/techlibs/nanoxplore/rf_rams_map_u.v +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -12,13 +12,17 @@ module $__NX_RFB_U_DPREG_ ( parameter OPTION_MODE = 0; parameter WIDTH = 18; parameter BITS_USED = 0; + localparam BLOCK_NUM = OPTION_MODE == 2 ? 64 : 32; + localparam BLOCK_SIZE = OPTION_MODE == 3 ? 36 : 18; + +`include "rf_init.vh" // mode 0 - DPREG // mode 2 - NX_XRFB_64x18 // mode 3 - NX_XRFB_32x36 NX_RFB_U #( .mode(OPTION_MODE), - .mem_ctxt(INIT), + .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, BLOCK_NUM, BLOCK_SIZE))), .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1) ) _TECHMAP_REPLACE_ ( .WCK(PORT_W_CLK), @@ -122,13 +126,14 @@ module $__NX_RFB_U_SPREG_ ( input PORT_RW_WR_EN, output [17:0] PORT_RW_RD_DATA ); - parameter INIT = 1152'bx; + parameter INIT = 576'bx; parameter PORT_RW_CLK_POL = 1'b1; parameter BITS_USED = 0; +`include "rf_init.vh" NX_RFB_U #( .mode(1), - .mem_ctxt(INIT), + .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))), .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1) ) _TECHMAP_REPLACE_ ( .WCK(PORT_RW_CLK), @@ -235,13 +240,14 @@ module $__NX_XRFB_2R_1W_ ( output [17:0] PORT_A_RD_DATA, output [17:0] PORT_B_RD_DATA ); - parameter INIT = 1152'bx; + parameter INIT = 576'bx; parameter PORT_W_CLK_POL = 1'b1; parameter BITS_USED = 0; +`include "rf_init.vh" NX_RFB_U #( .mode(4), - .mem_ctxt(INIT), + .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))), .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1) ) _TECHMAP_REPLACE_ ( .WCK(PORT_W_CLK), From 829dd62054047ce388d751821dc8ff14521219f0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 17 May 2024 15:59:18 +0200 Subject: [PATCH 060/342] block ram mapping for standard modes --- techlibs/nanoxplore/brams.txt | 56 +++++++++++++++------- techlibs/nanoxplore/brams_map.v | 84 ++++++++++++++++++++++++++------- techlibs/nanoxplore/cells_bb.v | 8 ++-- 3 files changed, 109 insertions(+), 39 deletions(-) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt index bc3a1722e..55edc3ef3 100644 --- a/techlibs/nanoxplore/brams.txt +++ b/techlibs/nanoxplore/brams.txt @@ -1,26 +1,46 @@ ram block $__NX_RAM_ { - abits 13; - widths 1 2 4 9 per_port; + option "STD_MODE" "NOECC_48kx1" { + # only 32k used + abits 15; + widths 1 global; + } + option "STD_MODE" "NOECC_24kx2" { + # only 16k used + abits 14; + widths 2 global; + } + option "STD_MODE" "NOECC_16kx3" { + abits 14; + widths 3 global; + } + option "STD_MODE" "NOECC_12kx4" { + # only 8k used + abits 13; + widths 4 global; + } + option "STD_MODE" "NOECC_8kx6" { + abits 13; + widths 6 global; + } + option "STD_MODE" "NOECC_6kx8" { + # only 4k used + abits 12; + widths 8 global; + } + option "STD_MODE" "NOECC_4kx12" { + abits 12; + widths 12 global; + } + option "STD_MODE" "NOECC_2kx24" { + abits 11; + widths 24 global; + } cost 64; init no_undef; port srsw "A" "B" { clock anyedge; clken; - portoption "WRITEMODE" "NORMAL" { - rdwr no_change; - } - portoption "WRITEMODE" "WRITETHROUGH" { - rdwr new; - } - portoption "WRITEMODE" "READBEFOREWRITE" { - rdwr old; - } - option "RESETMODE" "SYNC" { - rdsrst zero ungated block_wr; - } - option "RESETMODE" "ASYNC" { - rdarst zero; - } - rdinit zero; + rdwr no_change; + rdinit none; } } \ No newline at end of file diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v index b025a6782..8b3298203 100644 --- a/techlibs/nanoxplore/brams_map.v +++ b/techlibs/nanoxplore/brams_map.v @@ -1,43 +1,93 @@ module $__NX_RAM_ (...); parameter INIT = 0; -parameter OPTION_RESETMODE = "SYNC"; +parameter OPTION_STD_MODE = ""; -parameter PORT_A_WIDTH = 9; +parameter WIDTH = 24; parameter PORT_A_CLK_POL = 1; -parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; input PORT_A_CLK; input PORT_A_CLK_EN; input PORT_A_WR_EN; -input PORT_A_RD_SRST; -input PORT_A_RD_ARST; -input [12:0] PORT_A_ADDR; -input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; -output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; +input [15:0] PORT_A_ADDR; +input [WIDTH-1:0] PORT_A_WR_DATA; +wire [24-1:0] A_DATA; +output [WIDTH-1:0] PORT_A_RD_DATA; -parameter PORT_B_WIDTH = 9; parameter PORT_B_CLK_POL = 1; -parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; input PORT_B_CLK; input PORT_B_CLK_EN; input PORT_B_WR_EN; -input PORT_B_RD_SRST; -input PORT_B_RD_ARST; -input [12:0] PORT_B_ADDR; -input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; -output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; +input [15:0] PORT_B_ADDR; +input [WIDTH-1:0] PORT_B_WR_DATA; +wire [24-1:0] B_DATA; +output [WIDTH-1:0] PORT_B_RD_DATA; + +generate + if (OPTION_STD_MODE == "NOECC_48kx1") begin + assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_24kx2") begin + assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_16kx3") begin + assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_12kx4") begin + assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_8kx6") begin + assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_6kx8") begin + assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_4kx12") begin + assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}}; + assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}}; + end + else if (OPTION_STD_MODE == "NOECC_2kx24") begin + assign A_DATA = PORT_A_WR_DATA; + assign B_DATA = PORT_B_WR_DATA; + end +endgenerate NX_RAM_WRAP #( + .std_mode(OPTION_STD_MODE), + .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1), + .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1), ) _TECHMAP_REPLACE_ ( .ACK(PORT_A_CLK), + //.ACKS(PORT_A_CLK), + //.ACKD(), // Not used in Non-ECC modes + //.ACKR(), + //.AR(), + //.ACOR(), + //.AERR(), + .ACS(PORT_A_CLK_EN), + .AWE(PORT_A_WR_EN), + .AA(PORT_A_ADDR), - .AI(PORT_A_WR_DATA), + .AI(A_DATA), .AO(PORT_A_RD_DATA), .BCK(PORT_B_CLK), - .BA(PORT_B_ADDR), + //.BCKC(PORT_B_CLK), + //.BCKD(), // Not used in Non-ECC modes + //.BCKR() + //.BR(), + //.BCOR(), + //.BERR(), + .BCS(PORT_B_CLK_EN), + .BWE(PORT_B_WR_EN), + .BA(B_DATA), .BI(PORT_B_WR_DATA), .BO(PORT_B_RD_DATA) ); diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 2f6ae1ec2..634e29b19 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -255,10 +255,10 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, parameter pipe_ob = 1'b0; parameter raw_config0 = 4'b0000; parameter raw_config1 = 16'b0000000000000000; - parameter raw_l_enable = 1'b0; - parameter raw_l_extend = 4'b0000; - parameter raw_u_enable = 1'b0; - parameter raw_u_extend = 8'b00000000; + //parameter raw_l_enable = 1'b0; + //parameter raw_l_extend = 4'b0000; + //parameter raw_u_enable = 1'b0; + //parameter raw_u_extend = 8'b00000000; parameter std_mode = ""; endmodule From 8eb099c1f4e3eb273abc6426c37b52cecdc5b482 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 20 May 2024 13:19:02 +0200 Subject: [PATCH 061/342] remove debug attribute --- techlibs/nanoxplore/nx_carry.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 08701b44e..aec2d1a3c 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -104,7 +104,6 @@ static void nx_carry_chain(Module *module) } } if (j==3) { - cell->set_string_attribute(ID(cnt), std::to_string(cnt)); if (cnt % 24 == 23) { SigBit new_co = module->addWire(NEW_ID); cell->setPort(ID(A4), State::S0); From f4d8ea4c403a482e367a3a130a43d9cc92c637a8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 20 May 2024 18:26:04 +0200 Subject: [PATCH 062/342] Start adding RFB simulation models --- techlibs/nanoxplore/cells_bb_u.v | 103 -------------------- techlibs/nanoxplore/cells_sim_u.v | 150 ++++++++++++++++++++++++++++++ techlibs/nanoxplore/rf_rams_u.txt | 6 +- tests/arch/nanoxplore/fsm.ys | 2 +- tests/arch/nanoxplore/lutram.ys | 93 ++++++++++++++++-- 5 files changed, 240 insertions(+), 114 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 2cc16f410..95cb7158f 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -2338,109 +2338,6 @@ module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, D parameter tx_usrclk_use_pcs_clk_2 = 1'b0; endmodule -(* blackbox *) -module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 -, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 -, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 -, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1 -, WA2, WA3, WA4, WA5, WA6, WE, WEA); - input I1; - input I10; - input I11; - input I12; - input I13; - input I14; - input I15; - input I16; - input I17; - input I18; - input I19; - input I2; - input I20; - input I21; - input I22; - input I23; - input I24; - input I25; - input I26; - input I27; - input I28; - input I29; - input I3; - input I30; - input I31; - input I32; - input I33; - input I34; - input I35; - input I36; - input I4; - input I5; - input I6; - input I7; - input I8; - input I9; - output O1; - output O10; - output O11; - output O12; - output O13; - output O14; - output O15; - output O16; - output O17; - output O18; - output O19; - output O2; - output O20; - output O21; - output O22; - output O23; - output O24; - output O25; - output O26; - output O27; - output O28; - output O29; - output O3; - output O30; - output O31; - output O32; - output O33; - output O34; - output O35; - output O36; - output O4; - output O5; - output O6; - output O7; - output O8; - output O9; - input RA1; - input RA10; - input RA2; - input RA3; - input RA4; - input RA5; - input RA6; - input RA7; - input RA8; - input RA9; - input WA1; - input WA2; - input WA3; - input WA4; - input WA5; - input WA6; - input WCK; - input WE; - input WEA; - parameter mem_ctxt = ""; - parameter mode = 0; - parameter wck_edge = 1'b0; -endmodule - - (* blackbox *) module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17 , I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2 diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 794dd4e6a..e7e8fcc9a 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -1,3 +1,4 @@ +(* abc9_box, lib_whitebox *) module NX_GCK_U(SI1, SI2, CMD, SO); input CMD; input SI1; @@ -28,3 +29,152 @@ module NX_GCK_U(SI1, SI2, CMD, SO); endgenerate assign SO = inv_out ? ~SO_int : SO_int; endmodule + +(* abc9_box, lib_whitebox *) +module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 +, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 +, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 +, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1 +, WA2, WA3, WA4, WA5, WA6, WE, WEA); + input I1; + input I10; + input I11; + input I12; + input I13; + input I14; + input I15; + input I16; + input I17; + input I18; + input I19; + input I2; + input I20; + input I21; + input I22; + input I23; + input I24; + input I25; + input I26; + input I27; + input I28; + input I29; + input I3; + input I30; + input I31; + input I32; + input I33; + input I34; + input I35; + input I36; + input I4; + input I5; + input I6; + input I7; + input I8; + input I9; + output O1; + output O10; + output O11; + output O12; + output O13; + output O14; + output O15; + output O16; + output O17; + output O18; + output O19; + output O2; + output O20; + output O21; + output O22; + output O23; + output O24; + output O25; + output O26; + output O27; + output O28; + output O29; + output O3; + output O30; + output O31; + output O32; + output O33; + output O34; + output O35; + output O36; + output O4; + output O5; + output O6; + output O7; + output O8; + output O9; + input RA1; + input RA10; + input RA2; + input RA3; + input RA4; + input RA5; + input RA6; + input RA7; + input RA8; + input RA9; + input WA1; + input WA2; + input WA3; + input WA4; + input WA5; + input WA6; + input WCK; + input WE; + input WEA; + parameter mem_ctxt = ""; + parameter mode = 0; + parameter wck_edge = 1'b0; + + wire clock = WCK ^ wck_edge; + + localparam MEM_SIZE = mode == 2 ? 64 : 32; + localparam MEM_WIDTH = mode == 3 ? 36 : 18; + localparam ADDR_WIDTH = mode == 2 ? 6 : 5; + + reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0]; + + integer i; + initial begin + for (i = 0; i < MEM_SIZE; i = i + 1) + mem[i] = MEM_SIZE'b0; + end + + wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; + wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, + O27, O26, O25, O24, O23, O22, O21, O20, O19, + O18, O17, O16, O15, O14, O13, O12, O11, O10, + O9, O8, O7, O6, O5, O4, O3, O2, O1 }; + wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28, + I27, I26, I25, I24, I23, I22, I21, I20, I19, + I18, I17, I16, I15, I14, I13, I12, I11, I10, + I9, I8, I7, I6, I5, I4, I3, I2, I1 }; + generate + if (mode==0) begin + assign O[17:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }]; + end + else if (mode==1) begin + assign O[17:0] = mem[{ WA5, WA4, WA3, WA2, WA1 }]; + end + else if (mode==2) begin + assign O[17:0] = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }]; + end + else if (mode==3) begin + assign O[35:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }]; + end + else if (mode==4) begin + assign O[35:0] = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] }; + end + else + $error("Unknown NX_RFB_U mode"); + endgenerate + + always @(posedge clock) + if (WE) + mem[WA] <= I[MEM_WIDTH-1:0]; +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt index 7b80e2f24..3dd3d3614 100644 --- a/techlibs/nanoxplore/rf_rams_u.txt +++ b/techlibs/nanoxplore/rf_rams_u.txt @@ -7,7 +7,7 @@ ram distributed $__NX_RFB_U_DPREG_ { option "MODE" 0 { - cost 35; + cost 30; widthscale 30; abits 5; widths 18 global; @@ -53,8 +53,8 @@ ram distributed $__NX_RFB_U_SPREG_ { # NX_RFB_U in mode 4 (NX_XRFB_2R_1W) ram distributed $__NX_XRFB_2R_1W_ { - cost 30; - widthscale; + cost 40; + widthscale 30; abits 5; width 18; init no_undef; diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys index 8582d111c..f5d44453d 100644 --- a/tests/arch/nanoxplore/fsm.ys +++ b/tests/arch/nanoxplore/fsm.ys @@ -12,5 +12,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 6 t:NX_DFF -select -assert-count 14 t:NX_LUT +select -assert-min 13 t:NX_LUT select -assert-none t:NX_DFF t:NX_LUT %% t:* %D diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 72f4919ea..547e03b30 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -1,8 +1,61 @@ +# Dual-port RAMs. +# NX_RFB_U in mode 0 (DPREG) + +read_verilog < Date: Tue, 21 May 2024 14:07:20 +0200 Subject: [PATCH 063/342] fix --- techlibs/nanoxplore/cells_sim_u.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index e7e8fcc9a..094adcaf8 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -142,7 +142,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 integer i; initial begin for (i = 0; i < MEM_SIZE; i = i + 1) - mem[i] = MEM_SIZE'b0; + mem[i] = MEM_WIDTH'b0; end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; From 4aaab8f3953e44b51b84ca0895b68745be26344b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 22 May 2024 15:45:18 +0200 Subject: [PATCH 064/342] start adding wfg model --- techlibs/nanoxplore/cells_bb_u.v | 21 ------------- techlibs/nanoxplore/cells_sim_u.v | 51 +++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 23 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 95cb7158f..56559fd23 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -539,27 +539,6 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, parameter use_pll = 1'b1; endmodule -(* blackbox *) -module NX_WFG_U(R, SI, ZI, SO, ZO); - input R; - input SI; - output SO; - input ZI; - output ZO; - parameter delay = 0; - parameter delay_on = 1'b0; - parameter div_phase = 1'b0; - parameter div_ratio = 0; - parameter location = ""; - parameter mode = 0; - parameter pattern = 16'b0000000000000000; - parameter pattern_end = 0; - parameter reset_on_cal_lock_n = 1'b0; - parameter reset_on_pll_lock_n = 1'b0; - parameter reset_on_pll_locka_n = 1'b0; - parameter wfg_edge = 1'b0; -endmodule - (* blackbox *) module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO , AO, BO, AI, DI, DO); diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 094adcaf8..209da3b5f 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -142,7 +142,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 integer i; initial begin for (i = 0; i < MEM_SIZE; i = i + 1) - mem[i] = MEM_WIDTH'b0; + mem[i] = 36'b0; end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; @@ -177,4 +177,51 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 always @(posedge clock) if (WE) mem[WA] <= I[MEM_WIDTH-1:0]; -endmodule \ No newline at end of file +endmodule + +(* abc9_box, lib_whitebox *) +module NX_WFG_U(R, SI, ZI, SO, ZO); + input R; + input SI; + output SO; + input ZI; + output ZO; + parameter delay = 0; + parameter delay_on = 1'b0; + parameter div_phase = 1'b0; + parameter div_ratio = 0; + parameter location = ""; + parameter mode = 0; + parameter pattern = 16'b0000000000000000; + parameter pattern_end = 0; + parameter reset_on_cal_lock_n = 1'b0; + parameter reset_on_pll_lock_n = 1'b0; + parameter reset_on_pll_locka_n = 1'b0; + parameter wfg_edge = 1'b0; + + generate + if (mode==0) begin + assign SO = SI; + end + else if (mode==1) begin + wire clock = ZI ^ wfg_edge; + wire reset = R || SI; + reg [3:0] counter = 0; + reg [15:0] rom = pattern; + + always @(posedge clock) + begin + if (reset) + counter <= 4'b0; + else + counter <= counter + 1; + end + assign SO = counter == pattern_end; + assign ZO = rom[counter]; + end + else if (mode==2) begin + end + else + $error("Unknown NX_WFG_U mode"); + endgenerate +endmodule From 57665556424b50ba73031171a1ef8bb6c151aa1d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 28 May 2024 14:21:36 +0200 Subject: [PATCH 065/342] Support brams with initialization --- techlibs/nanoxplore/Makefile.inc | 1 + techlibs/nanoxplore/brams.txt | 16 +-- techlibs/nanoxplore/brams_init.vh | 23 ++++ techlibs/nanoxplore/brams_map.v | 74 +++++------ techlibs/nanoxplore/cells_bb.v | 172 ------------------------- techlibs/nanoxplore/cells_sim.v | 203 ++++++++++++++++++++++++++++++ 6 files changed, 267 insertions(+), 222 deletions(-) create mode 100644 techlibs/nanoxplore/brams_init.vh diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index 481429c66..807cf36a4 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -4,6 +4,7 @@ OBJS += techlibs/nanoxplore/nx_carry.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt index 55edc3ef3..6098ee72e 100644 --- a/techlibs/nanoxplore/brams.txt +++ b/techlibs/nanoxplore/brams.txt @@ -2,38 +2,38 @@ ram block $__NX_RAM_ { option "STD_MODE" "NOECC_48kx1" { # only 32k used abits 15; - widths 1 global; + widths 1 per_port; } option "STD_MODE" "NOECC_24kx2" { # only 16k used abits 14; - widths 2 global; + widths 2 per_port; } option "STD_MODE" "NOECC_16kx3" { abits 14; - widths 3 global; + widths 3 per_port; } option "STD_MODE" "NOECC_12kx4" { # only 8k used abits 13; - widths 4 global; + widths 4 per_port; } option "STD_MODE" "NOECC_8kx6" { abits 13; - widths 6 global; + widths 6 per_port; } option "STD_MODE" "NOECC_6kx8" { # only 4k used abits 12; - widths 8 global; + widths 8 per_port; } option "STD_MODE" "NOECC_4kx12" { abits 12; - widths 12 global; + widths 12 per_port; } option "STD_MODE" "NOECC_2kx24" { abits 11; - widths 24 global; + widths 24 per_port; } cost 64; init no_undef; diff --git a/techlibs/nanoxplore/brams_init.vh b/techlibs/nanoxplore/brams_init.vh new file mode 100644 index 000000000..b93839c5a --- /dev/null +++ b/techlibs/nanoxplore/brams_init.vh @@ -0,0 +1,23 @@ +function [409600-1:0] bram_init_to_string; + input [49152-1:0] array; + input integer blocks; + input integer width; + reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas + reg [24-1:0] temp2; + integer i; + integer j; +begin + temp = ""; + for (i = 0; i < 2048; i = i + 1) begin + if (i != 0) begin + temp = {temp, ","}; + end + temp2 = 24'b0; + for (j = 0; j < blocks; j = j + 1) begin + temp2[j*width +: width] = array[{j, i[10:0]}*width +: width]; + end + temp = {temp, $sformatf("%b",temp2[23:0])}; + end + bram_init_to_string = temp; +end +endfunction diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v index 8b3298203..a721d6775 100644 --- a/techlibs/nanoxplore/brams_map.v +++ b/techlibs/nanoxplore/brams_map.v @@ -1,18 +1,20 @@ module $__NX_RAM_ (...); parameter INIT = 0; -parameter OPTION_STD_MODE = ""; +parameter OPTION_STD_MODE = "NOECC_24kx2"; + +parameter PORT_A_WIDTH = 24; +parameter PORT_B_WIDTH = 24; -parameter WIDTH = 24; parameter PORT_A_CLK_POL = 1; input PORT_A_CLK; input PORT_A_CLK_EN; input PORT_A_WR_EN; input [15:0] PORT_A_ADDR; -input [WIDTH-1:0] PORT_A_WR_DATA; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; wire [24-1:0] A_DATA; -output [WIDTH-1:0] PORT_A_RD_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; parameter PORT_B_CLK_POL = 1; @@ -20,49 +22,37 @@ input PORT_B_CLK; input PORT_B_CLK_EN; input PORT_B_WR_EN; input [15:0] PORT_B_ADDR; -input [WIDTH-1:0] PORT_B_WR_DATA; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; wire [24-1:0] B_DATA; -output [WIDTH-1:0] PORT_B_RD_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; -generate - if (OPTION_STD_MODE == "NOECC_48kx1") begin - assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_24kx2") begin - assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_16kx3") begin - assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_12kx4") begin - assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_8kx6") begin - assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_6kx8") begin - assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_4kx12") begin - assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}}; - assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}}; - end - else if (OPTION_STD_MODE == "NOECC_2kx24") begin - assign A_DATA = PORT_A_WR_DATA; - assign B_DATA = PORT_B_WR_DATA; - end -endgenerate +`include "brams_init.vh" + +localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000: + OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001: + OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110: + OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010: + OPTION_STD_MODE == "NOECC_8kx6" ? 16'b0000111111111111: + OPTION_STD_MODE == "NOECC_6kx8" ? 16'b0000011011011011: + OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100: + OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101: + 'bx; + +localparam A_REPEAT = 24 / PORT_A_WIDTH; +localparam B_REPEAT = 24 / PORT_B_WIDTH; + +assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}}; +assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}}; NX_RAM_WRAP #( .std_mode(OPTION_STD_MODE), .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1), .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1), + .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1), + .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1), + .raw_config0(4'b0000), + .raw_config1(raw_config1_val), + .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))), ) _TECHMAP_REPLACE_ ( .ACK(PORT_A_CLK), //.ACKS(PORT_A_CLK), @@ -87,8 +77,8 @@ NX_RAM_WRAP #( //.BERR(), .BCS(PORT_B_CLK_EN), .BWE(PORT_B_WR_EN), - .BA(B_DATA), - .BI(PORT_B_WR_DATA), + .BA(PORT_B_ADDR), + .BI(B_DATA), .BO(PORT_B_RD_DATA) ); endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 634e29b19..c66bfaf08 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -90,178 +90,6 @@ endmodule // parameter ring = 0; //endmodule -(* blackbox *) -module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 -, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 -, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3 -, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24 -, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21 -, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE -, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR); - input AA1; - input AA10; - input AA11; - input AA12; - input AA13; - input AA14; - input AA15; - input AA16; - input AA2; - input AA3; - input AA4; - input AA5; - input AA6; - input AA7; - input AA8; - input AA9; - input ACK; - input ACKC; - input ACKD; - input ACKR; - output ACOR; - input ACS; - output AERR; - input AI1; - input AI10; - input AI11; - input AI12; - input AI13; - input AI14; - input AI15; - input AI16; - input AI17; - input AI18; - input AI19; - input AI2; - input AI20; - input AI21; - input AI22; - input AI23; - input AI24; - input AI3; - input AI4; - input AI5; - input AI6; - input AI7; - input AI8; - input AI9; - output AO1; - output AO10; - output AO11; - output AO12; - output AO13; - output AO14; - output AO15; - output AO16; - output AO17; - output AO18; - output AO19; - output AO2; - output AO20; - output AO21; - output AO22; - output AO23; - output AO24; - output AO3; - output AO4; - output AO5; - output AO6; - output AO7; - output AO8; - output AO9; - input AR; - input AWE; - input BA1; - input BA10; - input BA11; - input BA12; - input BA13; - input BA14; - input BA15; - input BA16; - input BA2; - input BA3; - input BA4; - input BA5; - input BA6; - input BA7; - input BA8; - input BA9; - input BCK; - input BCKC; - input BCKD; - input BCKR; - output BCOR; - input BCS; - output BERR; - input BI1; - input BI10; - input BI11; - input BI12; - input BI13; - input BI14; - input BI15; - input BI16; - input BI17; - input BI18; - input BI19; - input BI2; - input BI20; - input BI21; - input BI22; - input BI23; - input BI24; - input BI3; - input BI4; - input BI5; - input BI6; - input BI7; - input BI8; - input BI9; - output BO1; - output BO10; - output BO11; - output BO12; - output BO13; - output BO14; - output BO15; - output BO16; - output BO17; - output BO18; - output BO19; - output BO2; - output BO20; - output BO21; - output BO22; - output BO23; - output BO24; - output BO3; - output BO4; - output BO5; - output BO6; - output BO7; - output BO8; - output BO9; - input BR; - input BWE; - parameter mcka_edge = 1'b0; - parameter mckb_edge = 1'b0; - parameter mem_ctxt = ""; - parameter pcka_edge = 1'b0; - parameter pckb_edge = 1'b0; - parameter pipe_ia = 1'b0; - parameter pipe_ib = 1'b0; - parameter pipe_oa = 1'b0; - parameter pipe_ob = 1'b0; - parameter raw_config0 = 4'b0000; - parameter raw_config1 = 16'b0000000000000000; - //parameter raw_l_enable = 1'b0; - //parameter raw_l_extend = 4'b0000; - //parameter raw_u_enable = 1'b0; - //parameter raw_u_extend = 8'b00000000; - parameter std_mode = ""; -endmodule - // NX_RAM related (* blackbox *) module NX_ECC(CKD, CHK, COR, ERR); diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 392ee18e4..86606ce9c 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -185,3 +185,206 @@ module NX_BFR(I, O); assign O = data_inv ? ~I : I; endmodule + +(* abc9_box, lib_whitebox *) +module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 +, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 +, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3 +, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24 +, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21 +, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE +, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR); + input AA1; + input AA10; + input AA11; + input AA12; + input AA13; + input AA14; + input AA15; + input AA16; + input AA2; + input AA3; + input AA4; + input AA5; + input AA6; + input AA7; + input AA8; + input AA9; + input ACK; + input ACKC; + input ACKD; + input ACKR; + output ACOR; + input ACS; + output AERR; + input AI1; + input AI10; + input AI11; + input AI12; + input AI13; + input AI14; + input AI15; + input AI16; + input AI17; + input AI18; + input AI19; + input AI2; + input AI20; + input AI21; + input AI22; + input AI23; + input AI24; + input AI3; + input AI4; + input AI5; + input AI6; + input AI7; + input AI8; + input AI9; + output reg AO1; + output reg AO10; + output reg AO11; + output reg AO12; + output reg AO13; + output reg AO14; + output reg AO15; + output reg AO16; + output reg AO17; + output reg AO18; + output reg AO19; + output reg AO2; + output reg AO20; + output reg AO21; + output reg AO22; + output reg AO23; + output reg AO24; + output reg AO3; + output reg AO4; + output reg AO5; + output reg AO6; + output reg AO7; + output reg AO8; + output reg AO9; + input AR; + input AWE; + input BA1; + input BA10; + input BA11; + input BA12; + input BA13; + input BA14; + input BA15; + input BA16; + input BA2; + input BA3; + input BA4; + input BA5; + input BA6; + input BA7; + input BA8; + input BA9; + input BCK; + input BCKC; + input BCKD; + input BCKR; + output BCOR; + input BCS; + output BERR; + input BI1; + input BI10; + input BI11; + input BI12; + input BI13; + input BI14; + input BI15; + input BI16; + input BI17; + input BI18; + input BI19; + input BI2; + input BI20; + input BI21; + input BI22; + input BI23; + input BI24; + input BI3; + input BI4; + input BI5; + input BI6; + input BI7; + input BI8; + input BI9; + output reg BO1; + output reg BO10; + output reg BO11; + output reg BO12; + output reg BO13; + output reg BO14; + output reg BO15; + output reg BO16; + output reg BO17; + output reg BO18; + output reg BO19; + output reg BO2; + output reg BO20; + output reg BO21; + output reg BO22; + output reg BO23; + output reg BO24; + output reg BO3; + output reg BO4; + output reg BO5; + output reg BO6; + output reg BO7; + output reg BO8; + output reg BO9; + input BR; + input BWE; + parameter mcka_edge = 1'b0; + parameter mckb_edge = 1'b0; + parameter mem_ctxt = ""; + parameter pcka_edge = 1'b0; + parameter pckb_edge = 1'b0; + parameter pipe_ia = 1'b0; + parameter pipe_ib = 1'b0; + parameter pipe_oa = 1'b0; + parameter pipe_ob = 1'b0; + parameter raw_config0 = 4'b0000; + parameter raw_config1 = 16'b0000000000000000; + //parameter raw_l_enable = 1'b0; + //parameter raw_l_extend = 4'b0000; + //parameter raw_u_enable = 1'b0; + //parameter raw_u_extend = 8'b00000000; + parameter std_mode = ""; + + reg [24-1:0] mem [2048-1:0]; // 48 Kbit of memory + + /*integer i; + initial begin + for (i = 0; i < 2048; i = i + 1) + mem[i] = 24'b0; + end*/ + + wire [15:0] AA = { AA16, AA15, AA14, AA13, AA12, AA11, AA10, AA9, AA8, AA7, AA6, AA5, AA4, AA3, AA2, AA1 }; + wire [23:0] AI = { AI24, AI23, AI22, AI21, AI20, AI19, AI18, AI17, AI16, AI15, AI14, AI13, AI12, AI11, AI10, AI9, AI8, AI7, AI6, AI5, AI4, AI3, AI2, AI1 }; + wire [23:0] AO = { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 }; + wire [15:0] BA = { BA16, BA15, BA14, BA13, BA12, BA11, BA10, BA9, BA8, BA7, BA6, BA5, BA4, BA3, BA2, BA1 }; + wire [23:0] BI = { BI24, BI23, BI22, BI21, BI20, BI19, BI18, BI17, BI16, BI15, BI14, BI13, BI12, BI11, BI10, BI9, BI8, BI7, BI6, BI5, BI4, BI3, BI2, BI1 }; + wire [23:0] BO = { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 }; + + always @(posedge ACK) + if (AWE) + mem[AA[10:0]] <= AI; + else + { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 } <= mem[AA[10:0]]; + assign ACOR = 1'b0; + assign AERR = 1'b0; + + always @(posedge BCK) + if (BWE) + mem[BA[10:0]] <= BI; + else + { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 } <= mem[BA[10:0]]; + assign BCOR = 1'b0; + assign BERR = 1'b0; +endmodule From 8909a427964156ba3a915f2cd6697590efc5ec6f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 30 May 2024 08:06:30 +0200 Subject: [PATCH 066/342] Better wire check --- techlibs/nanoxplore/nx_carry.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index aec2d1a3c..544095081 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -80,7 +80,7 @@ static void nx_carry_chain(Module *module) IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) }; IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; - if (c.second.at(0)->getPort(ID(CI)).is_wire()) { + if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) { cell = module->addCell(NEW_ID, ID(NX_CY)); cell->setPort(ID(CI), State::S0); From 596506b88b79511551aa9a6b44a0d0a23d29fba4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 30 May 2024 09:06:12 +0200 Subject: [PATCH 067/342] Add NX_XCDC_U to wrappers --- techlibs/nanoxplore/cells_bb_u.v | 48 ---------- techlibs/nanoxplore/cells_wrap_u.v | 135 +++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+), 48 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v index 56559fd23..bfe04dc25 100644 --- a/techlibs/nanoxplore/cells_bb_u.v +++ b/techlibs/nanoxplore/cells_bb_u.v @@ -539,54 +539,6 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, parameter use_pll = 1'b1; endmodule -(* blackbox *) -module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO -, AO, BO, AI, DI, DO); - input ADRSTI; - output ADRSTO; - input [5:0] AI; - output [5:0] AO; - input ASRSTI; - output ASRSTO; - input BDRSTI; - output BDRSTO; - input [5:0] BI; - output [5:0] BO; - input BSRSTI; - output BSRSTO; - input CDRSTI; - output CDRSTO; - input [5:0] CI; - input CK1; - input CK2; - output [5:0] CO; - input CSRSTI; - output CSRSTO; - input DDRSTI; - output DDRSTO; - input [5:0] DI; - output [5:0] DO; - input DSRSTI; - output DSRSTO; - parameter ack_sel = 1'b0; - parameter bck_sel = 1'b0; - parameter cck_sel = 1'b0; - parameter ck0_edge = 1'b0; - parameter ck1_edge = 1'b0; - parameter dck_sel = 1'b0; - parameter link_BA = 1'b0; - parameter link_CB = 1'b0; - parameter link_DC = 1'b0; - parameter use_adest_arst = 1'b0; - parameter use_asrc_arst = 1'b0; - parameter use_bdest_arst = 1'b0; - parameter use_bsrc_arst = 1'b0; - parameter use_cdest_arst = 1'b0; - parameter use_csrc_arst = 1'b0; - parameter use_ddest_arst = 1'b0; - parameter use_dsrc_arst = 1'b0; -endmodule - (* blackbox *) module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6 , DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27 diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index 74adfaa51..c9eaa5e5b 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -466,6 +466,141 @@ module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI); ); endmodule +module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO +, AO, BO, AI, DI, DO); + input ADRSTI; + output ADRSTO; + input [5:0] AI; + output [5:0] AO; + input ASRSTI; + output ASRSTO; + input BDRSTI; + output BDRSTO; + input [5:0] BI; + output [5:0] BO; + input BSRSTI; + output BSRSTO; + input CDRSTI; + output CDRSTO; + input [5:0] CI; + input CK1; + input CK2; + output [5:0] CO; + input CSRSTI; + output CSRSTO; + input DDRSTI; + output DDRSTO; + input [5:0] DI; + output [5:0] DO; + input DSRSTI; + output DSRSTO; + parameter ack_sel = 1'b0; + parameter bck_sel = 1'b0; + parameter cck_sel = 1'b0; + parameter ck0_edge = 1'b0; + parameter ck1_edge = 1'b0; + parameter dck_sel = 1'b0; + parameter link_BA = 1'b0; + parameter link_CB = 1'b0; + parameter link_DC = 1'b0; + parameter use_adest_arst = 1'b0; + parameter use_asrc_arst = 1'b0; + parameter use_bdest_arst = 1'b0; + parameter use_bsrc_arst = 1'b0; + parameter use_cdest_arst = 1'b0; + parameter use_csrc_arst = 1'b0; + parameter use_ddest_arst = 1'b0; + parameter use_dsrc_arst = 1'b0; + + NX_CDC_U #( + .mode(5), // -- 5: XCDC + .ck0_edge(ck0_edge), + .ck1_edge(ck1_edge), + .ack_sel(ack_sel), + .bck_sel(bck_sel), + .cck_sel(cck_sel), + .dck_sel(dck_sel), + .use_asrc_arst(use_asrc_arst), + .use_adest_arst(use_adest_arst), + .use_bsrc_arst(use_bsrc_arst), + .use_bdest_arst(use_bdest_arst), + .use_csrc_arst(use_csrc_arst), + .use_cdest_arst(use_cdest_arst), + .use_dsrc_arst(use_dsrc_arst), + .use_ddest_arst(use_ddest_arst), + .link_BA(link_BA), + .link_CB(link_CB), + .link_DC(link_DC), + ) _TECHMAP_REPLACE_ ( + .CK1(CK1), + .CK2(CK2), + .ASRSTI(ASRSTI), + .ADRSTI(ADRSTI), + .ASRSTO(ASRSTO), + .ADRSTO(ADRSTO), + .AI1(AI[0]), + .AI2(AI[1]), + .AI3(AI[2]), + .AI4(AI[3]), + .AI5(AI[4]), + .AI6(AI[5]), + .AO1(AO[0]), + .AO2(AO[1]), + .AO3(AO[2]), + .AO4(AO[3]), + .AO5(AO[4]), + .AO6(AO[5]), + .BSRSTI(BSRSTI), + .BDRSTI(BDRSTI), + .BSRSTO(BSRSTO), + .BDRSTO(BDRSTO), + .BI1(BI[0]), + .BI2(BI[1]), + .BI3(BI[2]), + .BI4(BI[3]), + .BI5(BI[4]), + .BI6(BI[5]), + .BO1(BO[0]), + .BO2(BO[1]), + .BO3(BO[2]), + .BO4(BO[3]), + .BO5(BO[4]), + .BO6(BO[5]), + .CSRSTI(CSRSTI), + .CDRSTI(CDRSTI), + .CSRSTO(CSRSTO), + .CDRSTO(CDRSTO), + .CI1(CI[0]), + .CI2(CI[1]), + .CI3(CI[2]), + .CI4(CI[3]), + .CI5(CI[4]), + .CI6(CI[5]), + .CO1(CO[0]), + .CO2(CO[1]), + .CO3(CO[2]), + .CO4(CO[3]), + .CO5(CO[4]), + .CO6(CO[5]), + .DSRSTI(DSRSTI), + .DDRSTI(DDRSTI), + .DSRSTO(DSRSTO), + .DDRSTO(DDRSTO), + .DI1(DI[0]), + .DI2(DI[1]), + .DI3(DI[2]), + .DI4(DI[3]), + .DI5(DI[4]), + .DI6(DI[5]), + .DO1(DO[0]), + .DO2(DO[1]), + .DO3(DO[2]), + .DO4(DO[3]), + .DO5(DO[4]), + .DO6(DO[5]), + ); +endmodule + module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO); input [23:0] A; input [17:0] B; From 40f05009e37372d4cd17be8a03757999f487d76a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 30 May 2024 17:29:33 +0200 Subject: [PATCH 068/342] Fix CY chaining and CI injection --- techlibs/nanoxplore/nx_carry.cc | 8 ++-- tests/arch/nanoxplore/add_sub.ys | 63 +++++++++++++++++++++++++++++++- 2 files changed, 67 insertions(+), 4 deletions(-) diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 544095081..6e6a96035 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -82,7 +82,8 @@ static void nx_carry_chain(Module *module) IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) { cell = module->addCell(NEW_ID, ID(NX_CY)); - cell->setPort(ID(CI), State::S0); + cell->setParam(ID(add_carry), Const(1,2)); + cell->setPort(ID(CI), State::S1); cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); cell->setPort(names_B[0], State::S0); @@ -104,13 +105,14 @@ static void nx_carry_chain(Module *module) } } if (j==3) { - if (cnt % 24 == 23) { + if (cnt !=0 && (cnt % 24 == 0)) { SigBit new_co = module->addWire(NEW_ID); cell->setPort(ID(A4), State::S0); cell->setPort(ID(B4), State::S0); cell->setPort(ID(S4), new_co); cell = module->addCell(NEW_ID, ID(NX_CY)); - cell->setPort(ID(CI), State::S0); + cell->setParam(ID(add_carry), Const(1,2)); + cell->setPort(ID(CI), State::S1); cell->setPort(ID(A1), new_co); cell->setPort(ID(B1), State::S0); j = 1; diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys index 0cfc201f5..9b23cef15 100644 --- a/tests/arch/nanoxplore/add_sub.ys +++ b/tests/arch/nanoxplore/add_sub.ys @@ -1,10 +1,71 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 2 t:NX_CY select -assert-count 4 t:NX_LUT select -assert-none t:NX_CY t:NX_LUT %% t:* %D +design -reset +read_verilog < Date: Thu, 6 Jun 2024 18:07:39 +0200 Subject: [PATCH 069/342] run setundef for all x inputs --- techlibs/nanoxplore/synth_nanoxplore.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 054ca5b0d..babc91391 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -341,6 +341,7 @@ struct SynthNanoXplorePass : public ScriptPass run("stat"); run("check -noinit"); run("blackbox =A:whitebox"); + run("setundef -zero -undriven"); } if (check_label("json")) From 4372487a6f6d1b9fae41d3bd477a59dbf3655a00 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 7 Jun 2024 10:52:44 +0200 Subject: [PATCH 070/342] raw must be 16 bits for nx tools to work --- techlibs/nanoxplore/brams_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v index a721d6775..4609eee84 100644 --- a/techlibs/nanoxplore/brams_map.v +++ b/techlibs/nanoxplore/brams_map.v @@ -36,7 +36,7 @@ localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b000000000000 OPTION_STD_MODE == "NOECC_6kx8" ? 16'b0000011011011011: OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100: OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101: - 'bx; + 16'bx; localparam A_REPEAT = 24 / PORT_A_WIDTH; localparam B_REPEAT = 24 / PORT_B_WIDTH; @@ -51,7 +51,7 @@ NX_RAM_WRAP #( .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1), .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1), .raw_config0(4'b0000), - .raw_config1(raw_config1_val), + .raw_config1(raw_config1_val[15:0]), .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))), ) _TECHMAP_REPLACE_ ( .ACK(PORT_A_CLK), From 7601dc740be084d623fafa2df98d4c36f44f0855 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jun 2024 11:05:45 +0200 Subject: [PATCH 071/342] Some memory types are only supported on NG-LARGE --- techlibs/nanoxplore/brams.txt | 16 ++++++++++------ techlibs/nanoxplore/synth_nanoxplore.cc | 2 ++ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt index 6098ee72e..046f54c23 100644 --- a/techlibs/nanoxplore/brams.txt +++ b/techlibs/nanoxplore/brams.txt @@ -9,18 +9,22 @@ ram block $__NX_RAM_ { abits 14; widths 2 per_port; } - option "STD_MODE" "NOECC_16kx3" { - abits 14; - widths 3 per_port; + ifdef IS_NG_LARGE { + option "STD_MODE" "NOECC_16kx3" { + abits 14; + widths 3 per_port; + } } option "STD_MODE" "NOECC_12kx4" { # only 8k used abits 13; widths 4 per_port; } - option "STD_MODE" "NOECC_8kx6" { - abits 13; - widths 6 per_port; + ifdef IS_NG_LARGE { + option "STD_MODE" "NOECC_8kx6" { + abits 13; + widths 6 per_port; + } } option "STD_MODE" "NOECC_6kx8" { # only 4k used diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index babc91391..2d80a4189 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -264,6 +264,8 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ram")) { std::string args = ""; + if (family == "large") + args += " -D IS_NG_LARGE"; if (nobram) args += " -no-auto-block"; if (norfram) From eb30be6189662165513730d29e5dd55381fe676c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 24 Jun 2024 11:06:41 +0200 Subject: [PATCH 072/342] Impulse does not support these types but NG-ULTRA architecture does --- techlibs/nanoxplore/brams.txt | 4 ++-- techlibs/nanoxplore/synth_nanoxplore.cc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt index 046f54c23..d151cffa4 100644 --- a/techlibs/nanoxplore/brams.txt +++ b/techlibs/nanoxplore/brams.txt @@ -9,7 +9,7 @@ ram block $__NX_RAM_ { abits 14; widths 2 per_port; } - ifdef IS_NG_LARGE { + ifndef IS_NG_MEDIUM { option "STD_MODE" "NOECC_16kx3" { abits 14; widths 3 per_port; @@ -20,7 +20,7 @@ ram block $__NX_RAM_ { abits 13; widths 4 per_port; } - ifdef IS_NG_LARGE { + ifndef IS_NG_MEDIUM { option "STD_MODE" "NOECC_8kx6" { abits 13; widths 6 per_port; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 2d80a4189..b54b0e0d9 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -264,8 +264,8 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_ram")) { std::string args = ""; - if (family == "large") - args += " -D IS_NG_LARGE"; + if (family == "medium") + args += " -D IS_NG_MEDIUM"; if (nobram) args += " -no-auto-block"; if (norfram) From 6876a2754786c1f59ee0f3a752142be0f94f6ed5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 4 Jul 2024 07:41:55 +0200 Subject: [PATCH 073/342] Add NX_DFR simulation model --- techlibs/nanoxplore/cells_bb.v | 38 ++++++++++++++++----------------- techlibs/nanoxplore/cells_sim.v | 31 +++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 19 deletions(-) diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index c66bfaf08..1e98a6f3b 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -57,25 +57,25 @@ // output O; //endmodule -(* blackbox *) -module NX_DFR(I, CK, L, R, O); - input CK; - input I; - input L; - output O; - input R; - parameter data_inv = 1'b0; - parameter dff_edge = 1'b0; - parameter dff_init = 1'b0; - parameter dff_load = 1'b0; - parameter dff_sync = 1'b0; - parameter dff_type = 1'b0; - parameter iobname = ""; - parameter location = ""; - parameter mode = 0; - parameter path = 0; - parameter ring = 0; -endmodule +// (* blackbox *) +// module NX_DFR(I, CK, L, R, O); +// input CK; +// input I; +// input L; +// output O; +// input R; +// parameter data_inv = 1'b0; +// parameter dff_edge = 1'b0; +// parameter dff_init = 1'b0; +// parameter dff_load = 1'b0; +// parameter dff_sync = 1'b0; +// parameter dff_type = 1'b0; +// parameter iobname = ""; +// parameter location = ""; +// parameter mode = 0; +// parameter path = 0; +// parameter ring = 0; +// endmodule // Special mode of NX_DFR //(* blackbox *) diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 86606ce9c..7453821d0 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -36,6 +36,37 @@ always @(posedge clock, posedge async_reset) endmodule +(* abc9_box, lib_whitebox *) +module NX_DFR(input I, CK, L, R, output O); + +parameter data_inv = 1'b0; +parameter dff_edge = 1'b0; +parameter dff_init = 1'b0; +parameter dff_load = 1'b0; +parameter dff_sync = 1'b0; +parameter dff_type = 1'b0; +parameter iobname = ""; +parameter location = ""; +parameter mode = 0; +parameter path = 0; +parameter ring = 0; + +wire clock = CK ^ dff_edge; +wire load = dff_load ? L : 1'b1; +wire async_reset = !dff_sync && dff_init && R; +wire sync_reset = dff_sync && dff_init && R; +reg O_reg; + +always @(posedge clock, posedge async_reset) + if (async_reset) O_reg <= dff_type; + else if (sync_reset) O_reg <= dff_type; + else if (load) O_reg <= I; + +assign O = data_inv ? O_reg : ~O_reg; + +endmodule + + (* abc9_box, lib_whitebox *) module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); parameter add_carry = 0; From 1a6e5c671f5a3f53a2b1bd99519b96554c06b47e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 11 Jul 2024 17:43:46 +0200 Subject: [PATCH 074/342] Add meminit handling for NX_RFB_U --- techlibs/nanoxplore/cells_sim_u.v | 27 ++++++++++++++++- techlibs/nanoxplore/rf_rams_u.txt | 3 -- tests/arch/nanoxplore/meminit.v | 50 +++++++++++++++++++++++++++++++ tests/arch/nanoxplore/meminit.ys | 44 +++++++++++++++++++++++++++ 4 files changed, 120 insertions(+), 4 deletions(-) create mode 100644 tests/arch/nanoxplore/meminit.v create mode 100644 tests/arch/nanoxplore/meminit.ys diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 209da3b5f..c2c9c8b34 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -136,13 +136,38 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 localparam MEM_SIZE = mode == 2 ? 64 : 32; localparam MEM_WIDTH = mode == 3 ? 36 : 18; localparam ADDR_WIDTH = mode == 2 ? 6 : 5; + localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH; + localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1; reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0]; + function [DATA_SIZE-1:0] convert_initval; + input [8*MAX_SIZE-1:0] hex_initval; + reg done; + reg [DATA_SIZE-1:0] temp; + reg [7:0] char; + integer i,j; + begin + done = 1'b0; + temp = 0; + j = 0; + for (i = 0; i < MAX_SIZE; i = i + 1) begin + char = hex_initval[8*i +: 8]; + if (char >= "0" && char <= "1") begin + temp[j] = char - "0"; + j = j + 1; + end + end + convert_initval = temp; + end + endfunction + integer i; + reg [DATA_SIZE-1:0] mem_data; initial begin + mem_data = convert_initval(mem_ctxt); for (i = 0; i < MEM_SIZE; i = i + 1) - mem[i] = 36'b0; + mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH]; end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt index 3dd3d3614..94e002eeb 100644 --- a/techlibs/nanoxplore/rf_rams_u.txt +++ b/techlibs/nanoxplore/rf_rams_u.txt @@ -25,7 +25,6 @@ ram distributed $__NX_RFB_U_DPREG_ { widths 36 global; } init no_undef; - prune_rom; port sw "W" { clock anyedge; @@ -43,7 +42,6 @@ ram distributed $__NX_RFB_U_SPREG_ { abits 5; width 18; init no_undef; - prune_rom; port arsw "RW" { clock anyedge; } @@ -58,7 +56,6 @@ ram distributed $__NX_XRFB_2R_1W_ { abits 5; width 18; init no_undef; - prune_rom; port sw "W" { clock anyedge; } diff --git a/tests/arch/nanoxplore/meminit.v b/tests/arch/nanoxplore/meminit.v new file mode 100644 index 000000000..24d5a57f7 --- /dev/null +++ b/tests/arch/nanoxplore/meminit.v @@ -0,0 +1,50 @@ +module top(clk); +parameter DEPTH_LOG2 = 10; +parameter WIDTH = 36; +parameter PRIME = 237481091; +localparam DEPTH = 2**DEPTH_LOG2; + +input wire clk; + +(* syn_ramstyle = "distributed" *) +reg [WIDTH-1:0] mem [DEPTH-1:0]; + +integer i; +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + // Make up data by multiplying a large prime with the address, + // then cropping and retaining the lower bits + mem[i] = PRIME * (i*2+1); + end +end + +reg [DEPTH_LOG2-1:0] counter = 0; +reg done = 1'b0; + +reg did_read = 1'b0; +reg [DEPTH_LOG2-1:0] read_addr; +reg [WIDTH-1:0] read_val; + +always @(posedge clk) begin + if (!done) begin + did_read <= 1'b1; + read_addr <= counter; + read_val <= mem[counter]; + end else begin + did_read <= 1'b0; + end + + if (!done) + counter = counter + 1; + if (counter == 0) + done = 1; +end + +wire [WIDTH-1:0] expect_val = PRIME * (read_addr*2+1); +always @(posedge clk) begin + if (did_read) begin + $display("addr %x expected %x actual %x", read_addr, expect_val, read_val); + assert(read_val == expect_val); + end +end +endmodule diff --git a/tests/arch/nanoxplore/meminit.ys b/tests/arch/nanoxplore/meminit.ys new file mode 100644 index 000000000..ca93e6500 --- /dev/null +++ b/tests/arch/nanoxplore/meminit.ys @@ -0,0 +1,44 @@ +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 5 -set WIDTH 36 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 66 -clock clk + +design -reset +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 6 -set WIDTH 18 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 34 -clock clk + + +design -reset +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 8 -set WIDTH 18 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 258 -clock clk From 8f806c0d129c6878c4d57999584a4a6fb4a29744 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jul 2024 13:00:56 +0200 Subject: [PATCH 075/342] Added DDFR support --- techlibs/nanoxplore/cells_sim_u.v | 54 +++++++++++++++ techlibs/nanoxplore/cells_wrap_u.v | 105 +++++++++++++++++++++++------ 2 files changed, 138 insertions(+), 21 deletions(-) diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index c2c9c8b34..af46b24b0 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -250,3 +250,57 @@ module NX_WFG_U(R, SI, ZI, SO, ZO); $error("Unknown NX_WFG_U mode"); endgenerate endmodule + +module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2); + input CK; + input CKF; + input R; + input I; + input I2; + input L; + output O; + output O2; + + parameter location = ""; + parameter path = 0; + parameter dff_type = 1'b0; + parameter dff_sync = 1'b0; + parameter dff_load = 1'b0; + + wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF + wire async_reset = !dff_sync && R; + wire sync_reset = dff_sync && R; + + generate + if (path==1) begin + // IDDFR + always @(posedge CK, posedge async_reset) + if (async_reset) O <= dff_type; + else if (sync_reset) O <= dff_type; + else if (load) O <= I; + + always @(posedge CKF, posedge async_reset) + if (async_reset) O2 <= dff_type; + else if (sync_reset) O2 <= dff_type; + else if (load) O2 <= I; + end + else if (path==0 || path==2) begin + reg q1, q2; + // ODDFR + always @(posedge CK, posedge async_reset) + if (async_reset) q1 <= dff_type; + else if (sync_reset) q1 <= dff_type; + else if (load) q1 <= I; + + always @(posedge CKF, posedge async_reset) + if (async_reset) q2 <= dff_type; + else if (sync_reset) q2 <= dff_type; + else if (load) q2 <= I2; + + assign O = CK ? q1 : q2; + end + else + $error("Unknown NX_DDFR_U path"); + endgenerate + +endmodule diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v index c9eaa5e5b..e504f7344 100644 --- a/techlibs/nanoxplore/cells_wrap_u.v +++ b/techlibs/nanoxplore/cells_wrap_u.v @@ -1,18 +1,82 @@ + +module NX_ODDFR_U(CK,R,I1,I2,L,O); + input CK; + input R; + input I1; + input I2; + input L; + output O; + + parameter location = ""; + parameter path = 0; + parameter dff_type = 1'b0; + parameter dff_sync = 1'b0; + parameter dff_load = 1'b0; + + NX_DDFR_U #( + .location(location), + .path(path), + .dff_type(dff_type), + .dff_sync(dff_sync), + .dff_load(dff_load) + ) _TECHMAP_REPLACE_ ( + .CK(CK), + .CKF(CK), + .R(R), + .I(I1), + .I2(I2), + .L(L), + .O(O), + .O2() + ); +endmodule + +module NX_IDDFR_U(CK,R,I,L,O1,O2); + input CK; + input R; + input I; + input L; + output O1; + output O2; + + parameter location = ""; + parameter dff_type = 1'b0; + parameter dff_sync = 1'b0; + parameter dff_load = 1'b0; + + NX_DDFR_U #( + .location(location), + .path(1), + .dff_type(dff_type), + .dff_sync(dff_sync), + .dff_load(dff_load) + ) _TECHMAP_REPLACE_ ( + .CK(CK), + .CKF(CK), + .R(R), + .I(I), + .I2(1'b0), + .L(L), + .O(O1), + .O2(O2) + ); +endmodule + module NX_CKS_U(CKI, CMD, CKO); input CKI; output CKO; input CMD; -NX_GCK_U #( - .inv_in(1'b0), - .inv_out(1'b0), - .std_mode("CKS") -) _TECHMAP_REPLACE_ ( - .CMD(CMD), - .SI1(CKI), - .SI2(), - .SO(CKO) -); + NX_GCK_U #( + .inv_in(1'b0), + .inv_out(1'b0), + .std_mode("CKS") + ) _TECHMAP_REPLACE_ ( + .CMD(CMD), + .SI1(CKI), + .SI2(), + .SO(CKO) + ); endmodule module NX_CMUX_U(CKI0, CKI1, SEL, CKO); @@ -21,16 +85,16 @@ module NX_CMUX_U(CKI0, CKI1, SEL, CKO); output CKO; input SEL; -NX_GCK_U #( - .inv_in(1'b0), - .inv_out(1'b0), - .std_mode("MUX") -) _TECHMAP_REPLACE_ ( - .CMD(SEL), - .SI1(CKI0), - .SI2(CKI1), - .SO(CKO) -); + NX_GCK_U #( + .inv_in(1'b0), + .inv_out(1'b0), + .std_mode("MUX") + ) _TECHMAP_REPLACE_ ( + .CMD(SEL), + .SI1(CKI0), + .SI2(CKI1), + .SO(CKO) + ); endmodule module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI); @@ -3440,4 +3504,3 @@ module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hs parameter rx_usrclk_use_pcs_clk_2 = 1'b0; parameter tx_usrclk_use_pcs_clk_2 = 1'b0; endmodule - From 262ad03cd3a9acc24eeb14b3fb11fa9b0c8b2ccd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jul 2024 13:23:34 +0200 Subject: [PATCH 076/342] Add iopads by default add option to disable and keep old one for compatibility --- techlibs/nanoxplore/synth_nanoxplore.cc | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index b54b0e0d9..394b0ab54 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -85,8 +85,8 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nodsp\n"); log(" do not map multipliers to NX_DSP cells\n"); log("\n"); - log(" -iopad\n"); - log(" insert IO buffers\n"); + log(" -noiopad\n"); + log(" do not insert IO buffers\n"); log("\n"); log(" -no-rw-check\n"); log(" marks all recognized read ports as \"return don't-care value on\n"); @@ -100,7 +100,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, iopad, no_rw_check; + bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check; std::string postfix; void clear_flags() override @@ -115,7 +115,7 @@ struct SynthNanoXplorePass : public ScriptPass norfram = false; nobram = false; nodsp = false; - iopad = false; + noiopad = false; no_rw_check = false; postfix = ""; } @@ -181,7 +181,11 @@ struct SynthNanoXplorePass : public ScriptPass continue; } if (args[argidx] == "-iopad") { - iopad = true; + noiopad = false; + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; continue; } if (args[argidx] == "-no-rw-check") { @@ -293,8 +297,8 @@ struct SynthNanoXplorePass : public ScriptPass run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v"); run("nx_carry"); } - if (help_mode || iopad) { - run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(only if '-iopad')"); + if (help_mode || !noiopad) { + run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(skip if '-noiopad')"); run("techmap -map +/nanoxplore/io_map.v"); } run("opt -fast"); From 3848563600bfc60d2849670a725d1e951dff606c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jul 2024 13:29:51 +0200 Subject: [PATCH 077/342] Update tests --- tests/arch/nanoxplore/add_sub.ys | 6 +++--- tests/arch/nanoxplore/adffs.ys | 8 ++++---- tests/arch/nanoxplore/dffs.ys | 4 ++-- tests/arch/nanoxplore/fsm.ys | 2 +- tests/arch/nanoxplore/latches.ys | 6 +++--- tests/arch/nanoxplore/logic.ys | 2 +- tests/arch/nanoxplore/lutram.ys | 10 +++++----- tests/arch/nanoxplore/mux.ys | 8 ++++---- tests/arch/nanoxplore/shifter.ys | 2 +- tests/arch/nanoxplore/tribuf.ys | 2 +- 10 files changed, 25 insertions(+), 25 deletions(-) diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys index 9b23cef15..f7895ac5b 100644 --- a/tests/arch/nanoxplore/add_sub.ys +++ b/tests/arch/nanoxplore/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -30,7 +30,7 @@ EOT hierarchy -top top proc -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -58,7 +58,7 @@ EOT hierarchy -top top proc -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter diff --git a/tests/arch/nanoxplore/adffs.ys b/tests/arch/nanoxplore/adffs.ys index 9f4e1fac7..7fe24a0b5 100644 --- a/tests/arch/nanoxplore/adffs.ys +++ b/tests/arch/nanoxplore/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF @@ -14,7 +14,7 @@ select -assert-none t:NX_DFF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF @@ -26,7 +26,7 @@ select -assert-none t:NX_DFF t:NX_LUT %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF @@ -38,7 +38,7 @@ select -assert-none t:NX_DFF t:NX_LUT %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys index 898765408..6643b01a5 100644 --- a/tests/arch/nanoxplore/dffs.ys +++ b/tests/arch/nanoxplore/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF @@ -13,7 +13,7 @@ select -assert-none t:NX_DFF %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:NX_DFF diff --git a/tests/arch/nanoxplore/fsm.ys b/tests/arch/nanoxplore/fsm.ys index f5d44453d..136b220b7 100644 --- a/tests/arch/nanoxplore/fsm.ys +++ b/tests/arch/nanoxplore/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/nanoxplore/latches.ys b/tests/arch/nanoxplore/latches.ys index 4625348f9..b2eccfd80 100644 --- a/tests/arch/nanoxplore/latches.ys +++ b/tests/arch/nanoxplore/latches.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top latchp proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore +synth_nanoxplore -noiopad cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT @@ -15,7 +15,7 @@ design -load read hierarchy -top latchn proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore +synth_nanoxplore -noiopad cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT @@ -26,7 +26,7 @@ design -load read hierarchy -top latchsr proc # Can't run any sort of equivalence check because latches are blown to LUTs -synth_nanoxplore +synth_nanoxplore -noiopad cd latchsr # Constrain all select calls below inside the top module select -assert-count 2 t:NX_LUT diff --git a/tests/arch/nanoxplore/logic.ys b/tests/arch/nanoxplore/logic.ys index 2edcbfebd..061ab7a7d 100644 --- a/tests/arch/nanoxplore/logic.ys +++ b/tests/arch/nanoxplore/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 547e03b30..61b813bfb 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -26,7 +26,7 @@ EOT hierarchy -top lutram_dpreg proc memory -nomap -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad memory opt -full @@ -48,7 +48,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 18 proc memory -nomap -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad memory opt -full @@ -68,7 +68,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 18 proc memory -nomap -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad memory opt -full @@ -88,7 +88,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 36 proc memory -nomap -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad memory opt -full @@ -131,7 +131,7 @@ EOT hierarchy -top lutram_1w2r -chparam A_WIDTH 5 -chparam D_WIDTH 18 proc memory -nomap -equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore +equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad memory opt -full diff --git a/tests/arch/nanoxplore/mux.ys b/tests/arch/nanoxplore/mux.ys index 8c92ab156..f6309ce40 100644 --- a/tests/arch/nanoxplore/mux.ys +++ b/tests/arch/nanoxplore/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:NX_LUT @@ -13,7 +13,7 @@ select -assert-none t:NX_LUT %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module #select -assert-count 2 t:NX_LUT @@ -23,7 +23,7 @@ select -assert-none t:NX_LUT %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module #select -assert-count 5 t:NX_LUT @@ -33,7 +33,7 @@ select -assert-none t:NX_LUT %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-max 13 t:NX_LUT diff --git a/tests/arch/nanoxplore/shifter.ys b/tests/arch/nanoxplore/shifter.ys index a3502df2a..f30e653e3 100644 --- a/tests/arch/nanoxplore/shifter.ys +++ b/tests/arch/nanoxplore/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check +equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/nanoxplore/tribuf.ys b/tests/arch/nanoxplore/tribuf.ys index e55764f01..b3df55ac9 100644 --- a/tests/arch/nanoxplore/tribuf.ys +++ b/tests/arch/nanoxplore/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore -iopad # equivalency check +equiv_opt -assert -map +/nanoxplore/cells_sim.v -map +/simcells.v synth_nanoxplore # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. From 7bf623a0c75453bedd4922321226f67c087e2d46 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jul 2024 13:34:41 +0200 Subject: [PATCH 078/342] Fix simulation model warnings --- techlibs/nanoxplore/cells_sim_u.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index af46b24b0..0456a4691 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -181,19 +181,19 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 I9, I8, I7, I6, I5, I4, I3, I2, I1 }; generate if (mode==0) begin - assign O[17:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }]; + assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }]; end else if (mode==1) begin - assign O[17:0] = mem[{ WA5, WA4, WA3, WA2, WA1 }]; + assign O = mem[{ WA5, WA4, WA3, WA2, WA1 }]; end else if (mode==2) begin - assign O[17:0] = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }]; + assign O = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }]; end else if (mode==3) begin - assign O[35:0] = mem[{ RA5, RA4, RA3, RA2, RA1 }]; + assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }]; end else if (mode==4) begin - assign O[35:0] = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] }; + assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] }; end else $error("Unknown NX_RFB_U mode"); From dbf1d037e806e925db6ba249432cc90dd64605a1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jul 2024 13:41:12 +0200 Subject: [PATCH 079/342] Cleanup --- techlibs/nanoxplore/brams_map.v | 2 +- techlibs/nanoxplore/cells_bb.v | 92 ------------------------------- techlibs/nanoxplore/cells_sim_u.v | 30 +++++----- tests/arch/nanoxplore/add_sub.ys | 2 +- 4 files changed, 17 insertions(+), 109 deletions(-) diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v index 4609eee84..506e2dd0b 100644 --- a/techlibs/nanoxplore/brams_map.v +++ b/techlibs/nanoxplore/brams_map.v @@ -81,4 +81,4 @@ NX_RAM_WRAP #( .BI(B_DATA), .BO(PORT_B_RD_DATA) ); -endmodule \ No newline at end of file +endmodule diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v index 1e98a6f3b..919a02f82 100644 --- a/techlibs/nanoxplore/cells_bb.v +++ b/techlibs/nanoxplore/cells_bb.v @@ -1,95 +1,3 @@ -//(* blackbox *) -//module NX_LUT(I1, I2, I3, I4, O); -// input I1; -// input I2; -// input I3; -// input I4; -// output O; -// parameter lut_table = 16'b0000000000000000; -//endmodule - -//(* blackbox *) -//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4); -// input A1; -// input A2; -// input A3; -// input A4; -// input B1; -// input B2; -// input B3; -// input B4; -// input CI; -// output CO; -// output S1; -// output S2; -// output S3; -// output S4; -// parameter add_carry = 0; -//endmodule - -// Bypass mode of NX_GCK_U -//(* blackbox *) -//module NX_BD(I, O); -// input I; -// output O; -// parameter mode = "global_lowskew"; -//endmodule - -//(* blackbox *) -//module NX_DFF(I, CK, L, R, O); -// input CK; -// input I; -// input L; -// output O; -// input R; -// parameter dff_ctxt = 1'b0; -// parameter dff_edge = 1'b0; -// parameter dff_init = 1'b0; -// parameter dff_load = 1'b0; -// parameter dff_sync = 1'b0; -// parameter dff_type = 1'b0; -//endmodule - -// Special mode of NX_DFF -//(* blackbox *) -//module NX_BFF(I, O); -// input I; -// output O; -//endmodule - -// (* blackbox *) -// module NX_DFR(I, CK, L, R, O); -// input CK; -// input I; -// input L; -// output O; -// input R; -// parameter data_inv = 1'b0; -// parameter dff_edge = 1'b0; -// parameter dff_init = 1'b0; -// parameter dff_load = 1'b0; -// parameter dff_sync = 1'b0; -// parameter dff_type = 1'b0; -// parameter iobname = ""; -// parameter location = ""; -// parameter mode = 0; -// parameter path = 0; -// parameter ring = 0; -// endmodule - -// Special mode of NX_DFR -//(* blackbox *) -//module NX_BFR(I, O); -// input I; -// output O; -// parameter data_inv = 1'b0; -// parameter iobname = ""; -// parameter location = ""; -// parameter mode = 0; -// parameter path = 0; -// parameter ring = 0; -//endmodule - // NX_RAM related (* blackbox *) module NX_ECC(CKD, CHK, COR, ERR); diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 0456a4691..e11aaabee 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -12,20 +12,21 @@ module NX_GCK_U(SI1, SI2, CMD, SO); wire SI2_int = inv_in ? ~SI2 : SI2; wire SO_int; - generate if (std_mode == "BYPASS") begin - assign SO_int = SI1_int; - end - else if (std_mode == "MUX") begin - assign SO_int = CMD ? SI1_int : SI2_int; - end - else if (std_mode == "CKS") begin - assign SO_int = CMD ? SI1_int : 1'b0; - end - else if (std_mode == "CSC") begin - assign SO_int = CMD; - end - else - $error("Unrecognised std_mode"); + generate + if (std_mode == "BYPASS") begin + assign SO_int = SI1_int; + end + else if (std_mode == "MUX") begin + assign SO_int = CMD ? SI1_int : SI2_int; + end + else if (std_mode == "CKS") begin + assign SO_int = CMD ? SI1_int : 1'b0; + end + else if (std_mode == "CSC") begin + assign SO_int = CMD; + end + else + $error("Unrecognised std_mode"); endgenerate assign SO = inv_out ? ~SO_int : SO_int; endmodule @@ -302,5 +303,4 @@ module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2); else $error("Unknown NX_DDFR_U path"); endgenerate - endmodule diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys index f7895ac5b..9356944c8 100644 --- a/tests/arch/nanoxplore/add_sub.ys +++ b/tests/arch/nanoxplore/add_sub.ys @@ -68,4 +68,4 @@ design -load postopt cd top stat select -assert-count 48 t:NX_CY -select -assert-none t:NX_CY %% t:* %D \ No newline at end of file +select -assert-none t:NX_CY %% t:* %D From 220ddeac4d3db35cf439ca31c542d860d46efb62 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 14 Aug 2024 12:13:15 +0200 Subject: [PATCH 080/342] Set -mince and -minsrst --- techlibs/nanoxplore/synth_nanoxplore.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 394b0ab54..cb2bb8a96 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -312,7 +312,7 @@ struct SynthNanoXplorePass : public ScriptPass } else if (!nodffe) { dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"; } - dfflegalize_args += " -cell $_DLATCH_?_ x"; + dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8"; run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); From 14e43139cbfcefe75a36ce57f5c345b0de30a339 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 14 Aug 2024 12:14:21 +0200 Subject: [PATCH 081/342] Run opt_merge, helps with inverted reset/load signals --- techlibs/nanoxplore/synth_nanoxplore.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index cb2bb8a96..0948bb5ca 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -314,6 +314,7 @@ struct SynthNanoXplorePass : public ScriptPass } dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8"; run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); + run("opt_merge"); run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); run("opt_expr -undriven -mux_undef"); From 54d237ff82c72714c094f8abd149b5a317aeea9f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 15 Aug 2024 09:42:27 +0200 Subject: [PATCH 082/342] add min_ce_use and min_srst_use parameters --- techlibs/nanoxplore/synth_nanoxplore.cc | 21 ++++++++++++++++++++- tests/arch/nanoxplore/dffs.ys | 3 ++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 0948bb5ca..8349caa21 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -76,6 +76,14 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nodffe\n"); log(" do not use flipflops with L in output netlist\n"); log("\n"); + log(" -min_ce_use \n"); + log(" do not use flip-flops with load signal if the resulting count is less\n"); + log(" than min_ce_use in output netlist\n"); + log("\n"); + log(" -min_srst_use \n"); + log(" do not use flip-flops with async reset signal if the resulting count is less\n"); + log(" than min_srst_use in output netlist\n"); + log("\n"); log(" -norfram\n"); log(" do not use Register File RAM cells in output netlist\n"); log("\n"); @@ -102,6 +110,7 @@ struct SynthNanoXplorePass : public ScriptPass string top_opt, json_file, family; bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check; std::string postfix; + int min_ce_use, min_srst_use; void clear_flags() override { @@ -118,6 +127,8 @@ struct SynthNanoXplorePass : public ScriptPass noiopad = false; no_rw_check = false; postfix = ""; + min_ce_use = 8; + min_srst_use = 8; } void execute(std::vector args, RTLIL::Design *design) override @@ -168,6 +179,14 @@ struct SynthNanoXplorePass : public ScriptPass nodffe = true; continue; } + if (args[argidx] == "-min_ce_use" && argidx+1 < args.size()) { + min_ce_use = atoi(args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-min_srst_use" && argidx+1 < args.size()) { + min_srst_use = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-norfram") { norfram = true; continue; @@ -312,7 +331,7 @@ struct SynthNanoXplorePass : public ScriptPass } else if (!nodffe) { dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"; } - dfflegalize_args += " -cell $_DLATCH_?_ x -mince 8 -minsrst 8"; + dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("opt_merge"); run("techmap -map +/nanoxplore/latches_map.v"); diff --git a/tests/arch/nanoxplore/dffs.ys b/tests/arch/nanoxplore/dffs.ys index 6643b01a5..5b1e2e360 100644 --- a/tests/arch/nanoxplore/dffs.ys +++ b/tests/arch/nanoxplore/dffs.ys @@ -13,9 +13,10 @@ select -assert-none t:NX_DFF %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad # equivalency check +equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore -noiopad -min_ce_use 0 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module +stat select -assert-count 1 t:NX_DFF select -assert-none t:NX_DFF %% t:* %D From 092214256791007a433999635ed39fb9fc5d00ad Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 13:55:54 +0200 Subject: [PATCH 083/342] Add generic topological sort and SCC detection This adds a generic non-recursive implementation of Tarjan's linear time SCC algorithm that produces components in topological order. It can be instantiated to work directly on any graph representation for which the enumerate_nodes and enumerate_successors interface can be implemented. --- kernel/topo_scc.h | 328 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 328 insertions(+) create mode 100644 kernel/topo_scc.h diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h new file mode 100644 index 000000000..0ae0e696b --- /dev/null +++ b/kernel/topo_scc.h @@ -0,0 +1,328 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef TOPO_SCC_H +#define TOPO_SCC_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +class SigCellGraph { +public: + typedef int node_type; + + struct successor_enumerator { + std::vector>::const_iterator current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current->second; + ++current; + return result; + } + }; + + struct node_enumerator { + int current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + +private: + idict cell_ids; + idict sig_ids; + std::vector> edges; + std::vector> edge_ranges; + std::vector indices_; + int offset; + bool computed = false; + + void compute() { + offset = GetSize(sig_ids); + edge_ranges.clear(); + indices_.clear(); + indices_.resize(GetSize(sig_ids) + GetSize(cell_ids), -1); + + std::sort(edges.begin(), edges.end()); + auto last = std::unique(edges.begin(), edges.end()); + edges.erase(last, edges.end()); + auto edge = edges.begin(); + auto edge_end = edges.end(); + int range_begin = 0; + for (int node = -offset, node_end = GetSize(cell_ids); node != node_end; ++node) { + while (edge != edge_end && edge->first <= node) + ++edge; + int range_end = edge - edges.begin(); + edge_ranges.emplace_back(std::make_pair(range_begin, range_end)); + range_begin = range_end; + } + } + +public: + node_type node(RTLIL::Cell *cell) { return cell_ids(cell); } + node_type node(SigBit const &bit) { return ~sig_ids(bit); } + + bool is_cell(node_type node) { return node >= 0; } + bool is_sig(node_type node) { return node < 0; } + + Cell *cell(node_type node) { return node >= 0 ? cell_ids[node] : nullptr; } + SigBit sig(node_type node) { return node < 0 ? sig_ids[~node] : SigBit(); } + + template + void add_edge(Src &&src, Dst &&dst) { + computed = false; + node_type src_node = node(std::forward(src)); + node_type dst_node = node(std::forward(dst)); + edges.emplace_back(std::make_pair(src_node, dst_node)); + } + + node_enumerator enumerate_nodes() { + if (!computed) compute(); + return {-GetSize(sig_ids), GetSize(cell_ids)}; + } + + successor_enumerator enumerate_successors(node_type const &node) const { + auto range = edge_ranges[node + offset]; + return {edges.begin() + range.first, edges.begin() + range.second}; + } + + int &dfs_index(node_type const &node) { + return indices_[node + offset]; + } +}; + + +class IntGraph { +public: + typedef int node_type; + + struct successor_enumerator { + std::vector>::const_iterator current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current->second; + ++current; + return result; + } + }; + + struct node_enumerator { + int current, end; + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + +private: + std::vector> edges; + std::vector> edge_ranges; + std::vector indices_; + bool computed = false; + + void compute() { + edge_ranges.clear(); + + int node_end = 0; + for (auto const &edge : edges) + node_end = std::max(node_end, std::max(edge.first, edge.second) + 1); + indices_.clear(); + indices_.resize(node_end, -1); + + std::sort(edges.begin(), edges.end()); + auto last = std::unique(edges.begin(), edges.end()); + edges.erase(last, edges.end()); + auto edge = edges.begin(); + auto edge_end = edges.end(); + int range_begin = 0; + for (int node = 0; node != node_end; ++node) { + while (edge != edge_end && edge->first <= node) + ++edge; + int range_end = edge - edges.begin(); + edge_ranges.emplace_back(std::make_pair(range_begin, range_end)); + range_begin = range_end; + } + } + +public: + void add_edge(int src, int dst) { + log_assert(src >= 0); + log_assert(dst >= 0); + computed = false; + edges.emplace_back(std::make_pair(src, dst)); + } + + node_enumerator enumerate_nodes() { + if (!computed) compute(); + return {0, GetSize(indices_)}; + } + + successor_enumerator enumerate_successors(int node) const { + auto range = edge_ranges[node]; + return {edges.begin() + range.first, edges.begin() + range.second}; + } + + int &dfs_index(node_type const &node) { + return indices_[node]; + } +}; + +template +void topo_sorted_sccs(G &graph, ComponentCallback component) +{ + typedef typename G::node_enumerator node_enumerator; + typedef typename G::successor_enumerator successor_enumerator; + typedef typename G::node_type node_type; + + struct dfs_entry { + node_type node; + successor_enumerator successors; + int lowlink; + + dfs_entry(node_type node, successor_enumerator successors, int lowlink) : + node(node), successors(successors), lowlink(lowlink) + {} + }; + + std::vector dfs_stack; + std::vector component_stack; + int next_index = 0; + + + node_enumerator nodes = graph.enumerate_nodes(); + + // iterate over all nodes to ensure we process the whole graph + while (!nodes.finished()) { + node_type node = nodes.next(); + // only start a new search if the node wasn't visited yet + if (graph.dfs_index(node) >= 0) + continue; + + while (true) { + // at this point we're visiting the node for the first time during + // the DFS search + + // we record the timestamp of when we first visited the node as the + // dfs_index + int lowlink = next_index; + next_index++; + graph.dfs_index(node) = lowlink; + + // and we add the node to the component stack where it will remain + // until all nodes of the component containing this node are popped + component_stack.push_back(node); + + // then we start iterating over the successors of this node + successor_enumerator successors = graph.enumerate_successors(node); + while (true) { + if (successors.finished()) { + // when we processed all successors, i.e. when we visited + // the complete DFS subtree rooted at the current node, we + // first check whether the current node is a SCC root + // + // (why this check identifies SCC roots is out of scope for + // this comment, see other material on Tarjan's SCC + // algorithm) + if (lowlink == graph.dfs_index(node)) { + // the SCC containing the current node is at the top of + // the component stack, with the current node at the bottom + int current = GetSize(component_stack); + do { + --current; + } while (component_stack[current] != node); + + // we invoke the callback with a pointer range of the + // nodes in the SCC + + node_type *stack_ptr = component_stack.data(); + node_type *component_begin = stack_ptr + current; + node_type *component_end = stack_ptr + component_stack.size(); + + // note that we allow the callback to permute the nodes + // in this range as well as to modify dfs_index of the + // nodes in the SCC. + component(component_begin, component_end); + + // by setting the dfs_index of all already emitted + // nodes to INT_MAX, we don't need a separate check for + // whether successor nodes are still on the component + // stack before updating the lowlink value + for (; component_begin != component_end; ++component_begin) + graph.dfs_index(*component_begin) = INT_MAX; + component_stack.resize(current); + } + + // after checking for a completed SCC the DFS either + // continues the search at the parent node or returns to + // the outer loop if we already are at the root node. + if (dfs_stack.empty()) + goto next_search; + auto &dfs_top = dfs_stack.back(); + + node = dfs_top.node; + successors = std::move(dfs_top.successors); + + // the parent's lowlink is updated when returning + lowlink = min(lowlink, dfs_top.lowlink); + dfs_stack.pop_back(); + // continue checking the remaining successors of the parent node. + } else { + node_type succ = successors.next(); + if (graph.dfs_index(succ) < 0) { + // if the successor wasn't visted yet, the DFS recurses + // into the successor + + // we save the state for this node and make the + // successor the current node. + dfs_stack.emplace_back(node, std::move(successors), lowlink); + node = succ; + + // this break gets us to the section corresponding to + // the function entry in the recursive version + break; + } else { + // the textbook version guards this update with a check + // whether the successor is still on the component + // stack. If the successor node was already visisted + // but is not on the component stack, it must be part + // of an already emitted SCC. We can avoid this check + // by setting the DFS index of all nodes in a SCC to + // INT_MAX when the SCC is emitted. + lowlink = min(lowlink, graph.dfs_index(succ)); + } + } + } + } + next_search:; + } +} + +YOSYS_NAMESPACE_END + +#endif From c73c8a39cf27c1daae8b28b1874fd856efb2509b Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:01:10 +0200 Subject: [PATCH 084/342] kernel/log: Add log_str helper for custom log_* functions/overloads When implementing custom log_... functions or custom overloads for the core log functions like log_signal it is necessary to return `char *` that are valid long enough. The log_... functions implemented in log.cc use either `log_id_cache` or `string_buf` which both are cleared on log_pop. This commit adds a public `log_str` function which stores its argument in the `log_id_cache` and returns the stored copy, such that custom log functions outside of log.cc can also create strings that remain valid until the next `log_pop`. --- kernel/log.cc | 10 ++++++++++ kernel/log.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/kernel/log.cc b/kernel/log.cc index 9a61e8f08..55895da06 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -662,6 +662,16 @@ const char *log_id(const RTLIL::IdString &str) return p+1; } +const char *log_str(const char *str) +{ + log_id_cache.push_back(strdup(str)); + return log_id_cache.back(); +} + +const char *log_str(std::string const &str) { + return log_str(str.c_str()); +} + void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; diff --git a/kernel/log.h b/kernel/log.h index 53aae58c6..4b90cf9dc 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -206,6 +206,8 @@ void log_check_expected(); const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true); const char *log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(const RTLIL::IdString &id); +const char *log_str(const char *str); +const char *log_str(std::string const &str); template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { if (nullstr && obj == nullptr) From f24e2536c657346853ac71b8483eca004f695d0e Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:08:58 +0200 Subject: [PATCH 085/342] kernel/rtlil: Add `SigBit operator[](int offset)` to `SigChunk` This is already supported by `SigSpec` and since both `SigChunk` and `SigSpec` implement `extract` which is the multi-bit variant of this, there is no good reason for `SigChunk` to not support `SigBit operator[](int offset)`. --- kernel/rtlil.cc | 14 ++++++++++++++ kernel/rtlil.h | 1 + 2 files changed, 15 insertions(+) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d3946a620..b77f8f5fe 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3754,6 +3754,20 @@ RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const return ret; } +RTLIL::SigBit RTLIL::SigChunk::operator[](int offset) const +{ + log_assert(offset >= 0); + log_assert(offset <= width); + RTLIL::SigBit ret; + if (wire) { + ret.wire = wire; + ret.offset = this->offset + offset; + } else { + ret.data = data[offset]; + } + return ret; +} + bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const { if (wire && other.wire) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f9da29495..685acf904 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -769,6 +769,7 @@ struct RTLIL::SigChunk SigChunk(const RTLIL::SigBit &bit); RTLIL::SigChunk extract(int offset, int length) const; + RTLIL::SigBit operator[](int offset) const; inline int size() const { return width; } inline bool is_wire() const { return wire != NULL; } From 56572978f51a5f81cfb6b706fbd5c123b9133bc6 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:12:16 +0200 Subject: [PATCH 086/342] drivertools: Utility code for indexing and traversing signal drivers It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent cell ports, undriven bits and multiple drivers. For indexing an RTLIL module and for querying signal drivers it comes with a `DriverMap` type which is somewhat similar to a `SigMap` but is guaranteed to produce signal drivers as returned representatives. A `DriverMap` can also optionally preserve connections via intermediate wires (e.g. querying the driver of a cell input port will return a connected intermediate wire, querying the driver of that wire will return the cell output port that's driving the wire). --- Makefile | 2 + kernel/drivertools.cc | 946 +++++++++++++++++++++++++++++ kernel/drivertools.h | 1317 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 2265 insertions(+) create mode 100644 kernel/drivertools.cc create mode 100644 kernel/drivertools.h diff --git a/Makefile b/Makefile index d5e7e5235..812a69271 100644 --- a/Makefile +++ b/Makefile @@ -598,6 +598,7 @@ $(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/consteval.h)) $(eval $(call add_include_file,kernel/constids.inc)) $(eval $(call add_include_file,kernel/cost.h)) +$(eval $(call add_include_file,kernel/drivertools.h)) $(eval $(call add_include_file,kernel/ff.h)) $(eval $(call add_include_file,kernel/ffinit.h)) $(eval $(call add_include_file,kernel/ffmerge.h)) @@ -638,6 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o +OBJS += kernel/drivertools.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o endif diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc new file mode 100644 index 000000000..499a9399c --- /dev/null +++ b/kernel/drivertools.cc @@ -0,0 +1,946 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/drivertools.h" + +YOSYS_NAMESPACE_BEGIN + +DriveBit::DriveBit(SigBit const &bit) +{ + if (bit.is_wire()) + *this = DriveBitWire(bit.wire, bit.offset); + else + *this = bit.data; +} + +void DriveBit::merge(DriveBit const &other) +{ + if (other.type_ == DriveType::NONE) + return; + if (type_ == DriveType::NONE) { + *this = other; + return; + } + if (type_ != DriveType::MULTIPLE) { + DriveBitMultiple multi(std::move(*this)); + *this = std::move(multi); + } + multiple().merge(other); +} + + +void DriveBitMultiple::merge(DriveBit const &single) +{ + if (single.type() == DriveType::NONE) + return; + if (single.type() == DriveType::MULTIPLE) { + merge(single.multiple()); + return; + } + multiple_.emplace(single); +} + +void DriveBitMultiple::merge(DriveBit &&single) +{ + if (single.type() == DriveType::NONE) + return; + if (single.type() == DriveType::MULTIPLE) { + merge(std::move(single.multiple())); + return; + } + multiple_.emplace(std::move(single)); +} + +DriveBitMultiple DriveChunkMultiple::operator[](int i) const +{ + DriveBitMultiple result; + for (auto const &single : multiple_) + result.merge(single[i]); + return result; +} + + +bool DriveChunkWire::can_append(DriveBitWire const &bit) const +{ + return bit.wire == wire && bit.offset == offset + width; +} + +bool DriveChunkWire::try_append(DriveBitWire const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkWire::try_append(DriveChunkWire const &chunk) +{ + if (chunk.wire != wire || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +bool DriveChunkPort::can_append(DriveBitPort const &bit) const +{ + return bit.cell == cell && bit.port == port && bit.offset == offset + width; +} + +bool DriveChunkPort::try_append(DriveBitPort const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkPort::try_append(DriveChunkPort const &chunk) +{ + if (chunk.cell != cell || chunk.port != port || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + +bool DriveChunkMarker::can_append(DriveBitMarker const &bit) const +{ + return bit.marker == marker && bit.offset == offset + width; +} + +bool DriveChunkMarker::try_append(DriveBitMarker const &bit) +{ + if (!can_append(bit)) + return false; + width += 1; + return true; +} + +bool DriveChunkMarker::try_append(DriveChunkMarker const &chunk) +{ + if (chunk.marker != marker || chunk.offset != offset + width) + return false; + width += chunk.width; + return true; +} + + +bool DriveChunkMultiple::can_append(DriveBitMultiple const &bit) const +{ + if (bit.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveBit next = DriveBitWire(wire.wire, wire.offset + wire.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveBit next = DriveBitPort(port.cell, port.port, port.offset + port.width); + if (!bit.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveBit next = DriveBitMarker(marker.marker, marker.offset + marker.width); + if (!bit.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; +} + +bool DriveChunkMultiple::can_append(DriveChunkMultiple const &chunk) const +{ + if (chunk.multiple().size() != multiple_.size()) + return false; + + int const_drivers = 0; + for (DriveChunk const &single : multiple_) + if (single.is_constant()) + const_drivers += 1; + + if (const_drivers > 1) + return false; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + const_drivers -= 1; + + if (const_drivers != 0) + return false; + + for (DriveChunk const &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + } break; + case DriveType::WIRE: { + auto const &wire = single.wire(); + DriveChunk next = DriveChunkWire(wire.wire, wire.offset + wire.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::PORT: { + auto const &port = single.port(); + DriveChunk next = DriveChunkPort(port.cell, port.port, port.offset + port.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + case DriveType::MARKER: { + auto const &marker = single.marker(); + DriveChunk next = DriveChunkMarker(marker.marker, marker.offset + marker.width, chunk.size()); + if (!chunk.multiple().count(next)) + return false; + } break; + default: + return false; + } + } + + return true; +} + +bool DriveChunkMultiple::try_append(DriveBitMultiple const &bit) +{ + if (!can_append(bit)) + return false; + width_ += 1; + State constant; + + for (DriveBit const &single : bit.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + single.constant().bits.push_back(constant); + } break; + case DriveType::WIRE: { + single.wire().width += 1; + } break; + case DriveType::PORT: { + single.port().width += 1; + } break; + case DriveType::MARKER: { + single.marker().width += 1; + } break; + default: + log_abort(); + } + } + return true; +} + +bool DriveChunkMultiple::try_append(DriveChunkMultiple const &chunk) +{ + if (!can_append(chunk)) + return false; + int width = chunk.size(); + width_ += width; + Const constant; + + for (DriveChunk const &single : chunk.multiple()) + if (single.is_constant()) + constant = single.constant(); + + for (DriveChunk &single : multiple_) + { + switch (single.type()) + { + case DriveType::CONSTANT: { + auto &bits = single.constant().bits; + bits.insert(bits.end(), constant.bits.begin(), constant.bits.end()); + } break; + case DriveType::WIRE: { + single.wire().width += width; + } break; + case DriveType::PORT: { + single.port().width += width; + } break; + case DriveType::MARKER: { + single.marker().width += width; + } break; + default: + log_abort(); + } + } + return true; +} + +bool DriveChunk::can_append(DriveBit const &bit) const +{ + if (size() == 0) + return true; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return true; + case DriveType::WIRE: + return wire_.can_append(bit.wire()); + case DriveType::PORT: + return port_.can_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.can_append(bit.multiple()); + default: + log_abort(); + } +} + +bool DriveChunk::try_append(DriveBit const &bit) +{ + if (size() == 0) + *this = bit; + if (bit.type() != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += 1; + return true; + case DriveType::CONSTANT: + constant_.bits.push_back(bit.constant()); + return true; + case DriveType::WIRE: + return wire_.try_append(bit.wire()); + case DriveType::PORT: + return port_.try_append(bit.port()); + case DriveType::MULTIPLE: + return multiple_.try_append(bit.multiple()); + default: + log_abort(); + } +} + + +bool DriveChunk::try_append(DriveChunk const &chunk) +{ + if (size() == 0) + *this = chunk; + if (chunk.type_ != type_) + return false; + switch (type_) + { + case DriveType::NONE: + none_ += chunk.none_; + return true; + case DriveType::CONSTANT: + constant_.bits.insert(constant_.bits.end(), chunk.constant_.bits.begin(), chunk.constant_.bits.end()); + return true; + case DriveType::WIRE: + return wire_.try_append(chunk.wire()); + case DriveType::PORT: + return port_.try_append(chunk.port()); + case DriveType::MARKER: + return marker_.try_append(chunk.marker()); + case DriveType::MULTIPLE: + return multiple_.try_append(chunk.multiple()); + } + log_abort(); +} + +void DriveSpec::append(DriveBit const &bit) +{ + hash_ = 0; + if (!packed()) { + bits_.push_back(bit); + width_ += 1; + return; + } + + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(bit); + width_ += 1; +} + +void DriveSpec::append(DriveChunk const &chunk) +{ + hash_ = 0; + pack(); + if (chunks_.empty() || !chunks_.back().try_append(chunk)) + chunks_.emplace_back(chunk); + width_ += chunk.size(); +} + +void DriveSpec::pack() const { + if (bits_.empty()) + return; + std::vector bits(std::move(bits_)); + for (auto &bit : bits) + if (chunks_.empty() || !chunks_.back().try_append(bit)) + chunks_.emplace_back(std::move(bit)); +} + +void DriveSpec::unpack() const { + if (chunks_.empty()) + return; + for (auto &chunk : chunks_) + { + for (int i = 0, width = chunk.size(); i != width; ++i) + { + bits_.emplace_back(chunk[i]); + } + } + chunks_.clear(); +} + +void DriveSpec::compute_width() +{ + width_ = 0; + for (auto const &chunk : chunks_) + width_ += chunk.size(); +} + +void DriverMap::DriveBitGraph::add_edge(DriveBitId src, DriveBitId dst) +{ + if (first_edges.emplace(src, dst).first->second == dst) + return; + if (second_edges.emplace(src, dst).first->second == dst) + return; + more_edges[src].emplace(dst); +} + +DriverMap::DriveBitId DriverMap::DriveBitGraph::pop_edge(DriveBitId src) +{ + // TODO unused I think? + auto found_more = more_edges.find(src); + if (found_more != more_edges.end()) { + auto result = found_more->second.pop(); + if (found_more->second.empty()) + more_edges.erase(found_more); + return result; + } + + auto found_second = second_edges.find(src); + if (found_second != second_edges.end()) { + auto result = found_second->second; + second_edges.erase(found_second); + return result; + } + + auto found_first = first_edges.find(src); + if (found_first != first_edges.end()) { + auto result = found_first->second; + first_edges.erase(found_first); + return result; + } + + return DriveBitId(); +} + +void DriverMap::DriveBitGraph::clear(DriveBitId src) +{ + first_edges.erase(src); + second_edges.erase(src); + more_edges.erase(src); +} + +bool DriverMap::DriveBitGraph::contains(DriveBitId src) +{ + return first_edges.count(src); +} + +int DriverMap::DriveBitGraph::count(DriveBitId src) +{ + if (!first_edges.count(src)) + return 0; + if (!second_edges.count(src)) + return 1; + auto found = more_edges.find(src); + if (found == more_edges.end()) + return 2; + return GetSize(found->second); +} + +DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index) +{ + if (index == 0) + return first_edges.at(src); + else if (index == 1) + return second_edges.at(src); + else + return *more_edges.at(src).element(index - 2); +} + + +DriverMap::BitMode DriverMap::bit_mode(DriveBit const &bit) +{ + switch (bit.type()) + { + case DriveType::NONE: + return BitMode::NONE; + case DriveType::CONSTANT: + // TODO how to handle Sx here? + return bit.constant() == State::Sz ? BitMode::NONE : BitMode::DRIVER; + case DriveType::WIRE: { + auto const &wire = bit.wire(); + bool driver = wire.wire->port_input; + bool driven = wire.wire->port_output; + + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN; + else if (driver && driven) + return BitMode::TRISTATE; + else + return keep_wire(bit.wire().wire) ? BitMode::KEEP : BitMode::NONE; + } + case DriveType::PORT: { + auto const &port = bit.port(); + bool driver = celltypes.cell_output(port.cell->type, port.port); + bool driven = celltypes.cell_input(port.cell->type, port.port); + if (driver && !driven) + return BitMode::DRIVER; + else if (driven && !driver) + return BitMode::DRIVEN_UNIQUE; + else + return BitMode::TRISTATE; + } + case DriveType::MARKER: { + // TODO user supplied classification + log_abort(); + } + default: + log_abort(); + } +} + +DriverMap::DriveBitId DriverMap::id_from_drive_bit(DriveBit const &bit) +{ + switch (bit.type()) + { + case DriveType::NONE: + return -1; + case DriveType::CONSTANT: + return (int)bit.constant(); + case DriveType::WIRE: { + auto const &wire_bit = bit.wire(); + int offset = next_offset; + auto insertion = wire_offsets.emplace(wire_bit.wire, offset); + if (insertion.second) { + if (wire_bit.wire->width == 1) { + log_assert(wire_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitWire(wire_bit.wire, 0)); + next_offset += wire_bit.wire->width; + } + return insertion.first->second.id + wire_bit.offset; + } + case DriveType::PORT: { + auto const &port_bit = bit.port(); + auto key = std::make_pair(port_bit.cell, port_bit.port); + int offset = next_offset; + auto insertion = port_offsets.emplace(key, offset); + if (insertion.second) { + int width = port_bit.cell->connections().at(port_bit.port).size(); + if (width == 1 && offset == 0) { + log_assert(port_bit.offset == 0); + isolated_drive_bits.emplace(offset, bit); + } else + drive_bits.emplace(offset, DriveBitPort(port_bit.cell, port_bit.port, 0)); + next_offset += width; + } + return insertion.first->second.id + port_bit.offset; + } + default: + log_assert(false && "unsupported DriveType in DriverMap"); + } + log_abort(); +} + +DriveBit DriverMap::drive_bit_from_id(DriveBitId id) +{ + auto found_isolated = isolated_drive_bits.find(id); + if (found_isolated != isolated_drive_bits.end()) + return found_isolated->second; + + auto found = drive_bits.upper_bound(id); + if (found == drive_bits.begin()) { + return id < 0 ? DriveBit() : DriveBit((State) id.id); + } + --found; + DriveBit result = found->second; + if (result.is_wire()) { + result.wire().offset += id.id - found->first.id; + } else { + log_assert(result.is_port()); + result.port().offset += id.id - found->first.id; + } + return result; +} + +void DriverMap::connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id) +{ + if (driven_id == driver_id) + return; + + same_driver.merge(driven_id, driver_id); + + for (int i = 0, end = connected_drivers.count(driven_id); i != end; ++i) + connected_drivers.add_edge(driver_id, connected_drivers.at(driven_id, i)); + + connected_drivers.clear(driven_id); + + for (int i = 0, end = connected_undirected.count(driven_id); i != end; ++i) + connected_undirected.add_edge(driver_id, connected_undirected.at(driven_id, i)); + + connected_undirected.clear(driven_id); +} + +void DriverMap::connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id) +{ + connected_drivers.add_edge(driven_id, driver_id); +} + +void DriverMap::connect_undirected(DriveBitId a_id, DriveBitId b_id) +{ + connected_undirected.add_edge(a_id, b_id); + connected_undirected.add_edge(b_id, a_id); +} + +void DriverMap::add(Module *module) +{ + for (auto const &conn : module->connections()) + add(conn.first, conn.second); + + for (auto cell : module->cells()) + for (auto const &conn : cell->connections()) + add_port(cell, conn.first, conn.second); +} + +// Add a single bit connection to the driver map. +void DriverMap::add(DriveBit const &a, DriveBit const &b) +{ + DriveBitId a_id = id_from_drive_bit(a); + DriveBitId b_id = id_from_drive_bit(b); + + DriveBitId orig_a_id = a_id; + DriveBitId orig_b_id = b_id; + + a_id = same_driver.find(a_id); + b_id = same_driver.find(b_id); + + if (a_id == b_id) + return; + + BitMode a_mode = bit_mode(orig_a_id == a_id ? a : drive_bit_from_id(a_id)); + BitMode b_mode = bit_mode(orig_b_id == b_id ? b : drive_bit_from_id(b_id)); + + // If either bit is just a wire that we don't need to keep, merge and + // use the other end as representative bit. + if (a_mode == BitMode::NONE) + connect_directed_merge(a_id, b_id); + else if (b_mode == BitMode::NONE) + connect_directed_merge(b_id, a_id); + // If either bit requires a driven value and has a unique driver, merge + // and use the other end as representative bit. + else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_buffer(a_id, b_id); + else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + connect_directed_buffer(b_id, a_id); + // If either bit only drives a value, store a directed connection from + // it to the other bit. + else if (a_mode == BitMode::DRIVER) + connect_directed_buffer(b_id, a_id); + else if (b_mode == BitMode::DRIVER) + connect_directed_buffer(a_id, b_id); + // Otherwise we store an undirected connection which we will resolve + // during querying. + else + connect_undirected(a_id, b_id); + + return; +} + +// Specialized version that avoids unpacking +void DriverMap::add(SigSpec const &a, SigSpec const &b) +{ + log_assert(a.size() == b.size()); + auto const &a_chunks = a.chunks(); + auto const &b_chunks = b.chunks(); + + auto a_chunk = a_chunks.begin(); + auto a_end = a_chunks.end(); + int a_offset = 0; + + auto b_chunk = b_chunks.begin(); + int b_offset = 0; + + SigChunk tmp_a, tmp_b; + while (a_chunk != a_end) { + int a_width = a_chunk->width - a_offset; + if (a_width == 0) { + a_offset = 0; + ++a_chunk; + continue; + } + int b_width = b_chunk->width - b_offset; + if (b_width == 0) { + b_offset = 0; + ++b_chunk; + continue; + } + int width = std::min(a_width, b_width); + log_assert(width > 0); + + SigChunk const &a_subchunk = + a_offset == 0 && a_width == width ? *a_chunk : a_chunk->extract(a_offset, width); + SigChunk const &b_subchunk = + b_offset == 0 && b_width == width ? *b_chunk : b_chunk->extract(b_offset, width); + + add(a_subchunk, b_subchunk); + + a_offset += width; + b_offset += width; + } +} + +void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b) +{ + int offset = 0; + for (auto const &chunk : b.chunks()) { + add(chunk, DriveChunkPort(cell, port, offset, chunk.width)); + offset += chunk.size(); + } +} + +void DriverMap::orient_undirected(DriveBitId id) +{ + pool &seen = orient_undirected_seen; + pool &drivers = orient_undirected_drivers; + dict &distance = orient_undirected_distance; + seen.clear(); + drivers.clear(); + + seen.emplace(id); + + for (int pos = 0; pos < GetSize(seen); ++pos) { + DriveBitId current = *seen.element(seen.size() - 1 - pos); + DriveBit bit = drive_bit_from_id(current); + + BitMode mode = bit_mode(bit); + + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + drivers.emplace(current); + + if (connected_drivers.contains(current)) + drivers.emplace(current); + + int undirected_driver_count = connected_undirected.count(current); + + for (int i = 0; i != undirected_driver_count; ++i) + seen.emplace(same_driver.find(connected_undirected.at(current, i))); + } + + if (drivers.empty()) + for (auto seen_id : seen) + drivers.emplace(seen_id); + + for (auto driver : drivers) + { + distance.clear(); + distance.emplace(driver, 0); + + for (int pos = 0; pos < GetSize(distance); ++pos) { + auto current_it = distance.element(distance.size() - 1 - pos); + + DriveBitId current = current_it->first; + int undirected_driver_count = connected_undirected.count(current); + + for (int i = 0; i != undirected_driver_count; ++i) + { + DriveBitId next = same_driver.find(connected_undirected.at(current, i)); + auto emplaced = distance.emplace(next, current_it->second + 1); + if (emplaced.first->second == current_it->second + 1) + connected_oriented.add_edge(next, current); + } + } + } + + for (auto seen_id : seen) + oriented_present.emplace(seen_id); +} + +DriveBit DriverMap::operator()(DriveBit const &bit) +{ + if (bit.type() == DriveType::MARKER || bit.type() == DriveType::NONE) + return bit; + if (bit.type() == DriveType::MULTIPLE) + { + DriveBit result; + for (auto const &inner : bit.multiple().multiple()) + result.merge((*this)(inner)); + return result; + } + + DriveBitId bit_id = id_from_drive_bit(bit); + + bit_id = same_driver.find(bit_id); + + DriveBit bit_repr = drive_bit_from_id(bit_id); + + BitMode mode = bit_mode(bit_repr); + + int implicit_driver_count = connected_drivers.count(bit_id); + if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id)) + orient_undirected(bit_id); + + DriveBit driver; + + if (mode == BitMode::DRIVER || mode == BitMode::TRISTATE) + driver = bit_repr; + + for (int i = 0; i != implicit_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i))); + + int oriented_driver_count = connected_oriented.count(bit_id); + for (int i = 0; i != oriented_driver_count; ++i) + driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i))); + + return driver; +} + +DriveSpec DriverMap::operator()(DriveSpec spec) +{ + DriveSpec result; + + for (int i = 0, width = spec.size(); i != width; ++i) + result.append((*this)(spec[i])); + + return result; +} + +const char *log_signal(DriveChunkWire const &chunk) +{ + const char *id = log_id(chunk.wire->name); + if (chunk.is_whole()) + return id; + if (chunk.width == 1) + return log_str(stringf("%s [%d]", id, chunk.offset)); + return log_str(stringf("%s [%d:%d]", id, chunk.offset + chunk.width - 1, chunk.offset)); +} + + +const char *log_signal(DriveChunkPort const &chunk) +{ + const char *cell_id = log_id(chunk.cell->name); + const char *port_id = log_id(chunk.port); + if (chunk.is_whole()) + return log_str(stringf("%s <%s>", cell_id, port_id)); + if (chunk.width == 1) + return log_str(stringf("%s <%s> [%d]", cell_id, port_id, chunk.offset)); + return log_str(stringf("%s <%s> [%d:%d]", cell_id, port_id, chunk.offset + chunk.width - 1, chunk.offset)); +} + +const char *log_signal(DriveChunkMarker const &chunk) +{ + if (chunk.width == 1) + return log_str(stringf(" [%d]", chunk.marker, chunk.offset)); + return log_str(stringf(" [%d:%d]", chunk.marker, chunk.offset + chunk.width - 1, chunk.offset)); +} + +const char *log_signal(DriveChunk const &chunk) +{ + switch (chunk.type()) + { + case DriveType::NONE: + return log_str(stringf("", chunk.size())); + case DriveType::CONSTANT: + return log_const(chunk.constant()); + case DriveType::WIRE: + return log_signal(chunk.wire()); + case DriveType::PORT: + return log_signal(chunk.port()); + case DriveType::MARKER: + return log_signal(chunk.marker()); + case DriveType::MULTIPLE: { + std::string str = " + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef DRIVERTOOLS_H +#define DRIVERTOOLS_H + +#include + +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" + +YOSYS_NAMESPACE_BEGIN + +// TODO move implementation into a .cc file + +struct DriveBit; + +struct DriveChunkWire; +struct DriveChunkPort; +struct DriveChunkMarker; +struct DriveChunk; + +struct DriveSpec; + +const char *log_signal(DriveChunkWire const &chunk); +const char *log_signal(DriveChunkPort const &chunk); +const char *log_signal(DriveChunkMarker const &chunk); +const char *log_signal(DriveChunk const &chunk); +const char *log_signal(DriveSpec const &chunk); + +enum class DriveType : unsigned char +{ + NONE, + CONSTANT, + WIRE, + PORT, + MULTIPLE, + MARKER, +}; + +struct DriveBitWire +{ + Wire *wire; + int offset; + + DriveBitWire(Wire *wire, int offset) : wire(wire), offset(offset) {} + + bool operator==(const DriveBitWire &other) const + { + return wire == other.wire && offset == other.offset; + } + + bool operator<(const DriveBitWire &other) const + { + if (wire != other.wire) + return wire->name < other.wire->name; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(wire->name.hash(), offset); + } + + operator SigBit() const + { + return SigBit(wire, offset); + } +}; + +struct DriveBitPort +{ + Cell *cell; + IdString port; + int offset; + + DriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {} + + bool operator==(const DriveBitPort &other) const + { + return cell == other.cell && port == other.port && offset == other.offset; + } + + bool operator<(const DriveBitPort &other) const + { + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(cell->name.hash(), port.hash()), offset); + } +}; + + +struct DriveBitMarker +{ + int marker; + int offset; + + DriveBitMarker(int marker, int offset) : marker(marker), offset(offset) {} + + bool operator==(const DriveBitMarker &other) const + { + return marker == other.marker && offset == other.offset; + } + + bool operator<(const DriveBitMarker &other) const + { + if (marker != other.marker) + return marker < other.marker; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(marker, offset); + } + +}; + +struct DriveBitMultiple +{ +private: + pool multiple_; + +public: + DriveBitMultiple() {} + DriveBitMultiple(DriveBit const &single) + { + multiple_.emplace(single); + } + + pool const &multiple() const { return multiple_; } + + void merge(DriveBitMultiple const &other) + { + for (DriveBit const &single : other.multiple_) + merge(single); + } + + void merge(DriveBitMultiple &&other) + { + for (DriveBit &single : other.multiple_) + merge(std::move(single)); + } + + void merge(DriveBit const &single); + void merge(DriveBit &&single); + + bool operator==(const DriveBitMultiple &other) const + { + return multiple_ == other.multiple_; + } + + unsigned int hash() const + { + return multiple_.hash(); + } +}; + +struct DriveBit +{ +private: + DriveType type_ = DriveType::NONE; + union + { + State constant_; + DriveBitWire wire_; + DriveBitPort port_; + DriveBitMarker marker_; + DriveBitMultiple multiple_; + }; +public: + DriveBit() {} + + DriveBit(SigBit const &bit); + + DriveBit(DriveBit const &other) { *this = other; } + DriveBit(DriveBit &&other) { *this = other; } + + + DriveBit(State constant) { *this = constant; } + DriveBit(DriveBitWire const &wire) { *this = wire; } + DriveBit(DriveBitWire &&wire) { *this = wire; } + DriveBit(DriveBitPort const &port) { *this = port; } + DriveBit(DriveBitPort &&port) { *this = port; } + DriveBit(DriveBitMarker const &marker) { *this = marker; } + DriveBit(DriveBitMarker &&marker) { *this = marker; } + DriveBit(DriveBitMultiple const &multiple) { *this = multiple; } + DriveBit(DriveBitMultiple &&multiple) { *this = multiple; } + + ~DriveBit() { set_none(); } + + void set_none() + { + switch (type_) + { + case DriveType::NONE: + break; + case DriveType::CONSTANT: + break; + case DriveType::WIRE: + wire_.~DriveBitWire(); + break; + case DriveType::PORT: + port_.~DriveBitPort(); + break; + case DriveType::MARKER: + marker_.~DriveBitMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveBitMultiple(); + break; + } + type_ = DriveType::NONE; + } + + DriveBit &operator=(DriveBit const &other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; + } + + DriveBit &operator=(DriveBit &&other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; + } + + DriveBit &operator=(State constant) + { + set_none(); + constant_ = constant; + type_ = DriveType::CONSTANT; + return *this; + } + + DriveBit &operator=(DriveBitWire const &wire) + { + set_none(); + new (&wire_) DriveBitWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveBit &operator=(DriveBitWire &&wire) + { + set_none(); + new (&wire_) DriveBitWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveBit &operator=(DriveBitPort const &port) + { + set_none(); + new (&port_) DriveBitPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveBit &operator=(DriveBitPort &&port) + { + set_none(); + new (&port_) DriveBitPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveBit &operator=(DriveBitMarker const &marker) + { + set_none(); + new (&marker_) DriveBitMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveBit &operator=(DriveBitMarker &&marker) + { + set_none(); + new (&marker_) DriveBitMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveBit &operator=(DriveBitMultiple const &multiple) + { + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveBit &operator=(DriveBitMultiple &&multiple) + { + set_none(); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveBitMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + unsigned int hash() const + { + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_; + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); + } + + bool operator==(const DriveBit &other) const + { + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); + } + + bool operator!=(const DriveBit &other) const + { + return !(*this == other); + } + + bool operator<(const DriveBit &other) const + { + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + log_assert(!"TODO"); + } + log_abort(); + } + + + DriveType type() const { return type_; } + + bool is_none() const { return type_ == DriveType::NONE; } + bool is_constant() const { return type_ == DriveType::CONSTANT; } + bool is_wire() const { return type_ == DriveType::WIRE; } + bool is_port() const { return type_ == DriveType::PORT; } + bool is_marker() const { return type_ == DriveType::MARKER; } + bool is_multiple() const { return type_ == DriveType::MULTIPLE; } + + State &constant() { log_assert(is_constant()); return constant_; } + State const &constant() const { log_assert(is_constant()); return constant_; } + DriveBitWire &wire() { log_assert(is_wire()); return wire_; } + DriveBitWire const &wire() const { log_assert(is_wire()); return wire_; } + DriveBitPort &port() { log_assert(is_port()); return port_; } + DriveBitPort const &port() const { log_assert(is_port()); return port_; } + DriveBitMarker &marker() { log_assert(is_marker()); return marker_; } + DriveBitMarker const &marker() const { log_assert(is_marker()); return marker_; } + DriveBitMultiple &multiple() { log_assert(is_multiple()); return multiple_; } + DriveBitMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } + + void merge(DriveBit const &other); + +}; + + +struct DriveChunkWire +{ + Wire *wire; + int offset; + int width; + + DriveChunkWire(Wire *wire, int offset, int width) : wire(wire), offset(offset), width(width) {} + DriveChunkWire(DriveBitWire const &bit) : wire(bit.wire), offset(bit.offset), width(1) {} + + int size() const { return width; } + + DriveBitWire operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitWire(wire, offset + i); + } + + bool can_append(DriveBitWire const &bit) const; + bool try_append(DriveBitWire const &bit); + bool try_append(DriveChunkWire const &chunk); + + // Whether this chunk is a whole wire + bool is_whole() const { return offset == 0 && width == wire->width; } + + bool operator==(const DriveChunkWire &other) const + { + return wire == other.wire && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkWire &other) const + { + if (wire != other.wire) + return wire->name < other.wire->name; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(wire->name.hash(), width), offset); + } + + explicit operator SigChunk() const + { + return SigChunk(wire, offset, width); + } +}; + +struct DriveChunkPort +{ + Cell *cell; + IdString port; + int offset; + int width; + + DriveChunkPort(Cell *cell, IdString port, int offset, int width) : + cell(cell), port(port), offset(offset), width(width) { } + DriveChunkPort(Cell *cell, IdString port) : + cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { } + DriveChunkPort(Cell *cell, std::pair const &conn) : + cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { } + DriveChunkPort(DriveBitPort const &bit) : + cell(bit.cell), port(bit.port), offset(bit.offset), width(1) { } + + int size() const { return width; } + + DriveBitPort operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitPort(cell, port, offset + i); + } + + bool can_append(DriveBitPort const &bit) const; + bool try_append(DriveBitPort const &bit); + bool try_append(DriveChunkPort const &chunk); + + // Whether this chunk is a whole port + bool is_whole() const + { + return offset == 0 && width == cell->connections().at(port).size(); + } + + bool operator==(const DriveChunkPort &other) const + { + return cell == other.cell && port == other.port && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkPort &other) const + { + if (cell != other.cell) + return cell->name < other.cell->name; + if (port != other.port) + return port < other.port; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(mkhash(cell->name.hash(), port.hash()), width), offset); + } +}; + + +struct DriveChunkMarker +{ + int marker; + int offset; + int width; + + DriveChunkMarker(int marker, int offset, int width) : + marker(marker), offset(offset), width(width) {} + DriveChunkMarker(DriveBitMarker const &bit) : + marker(bit.marker), offset(bit.offset), width(1) {} + + int size() const { return width; } + + DriveBitMarker operator[](int i) const + { + log_assert(i >= 0 && i < width); + return DriveBitMarker(marker, offset + i); + } + + bool can_append(DriveBitMarker const &bit) const; + bool try_append(DriveBitMarker const &bit); + bool try_append(DriveChunkMarker const &chunk); + + bool operator==(const DriveChunkMarker &other) const + { + return marker == other.marker && offset == other.offset && width == other.width; + } + + bool operator<(const DriveChunkMarker &other) const + { + if (marker != other.marker) + return marker < other.marker; + if (width != other.width) + return width < other.width; + return offset < other.offset; + } + + unsigned int hash() const + { + return mkhash_add(mkhash(marker, width), offset); + } +}; + +struct DriveChunkMultiple +{ +private: + mutable pool multiple_; + int width_; + +public: + pool const &multiple() const { return multiple_; } + + DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) { + for (auto const &bit : bit.multiple()) + multiple_.emplace(bit); + } + + int size() const { return width_; } + + DriveBitMultiple operator[](int i) const; + + bool can_append(DriveBitMultiple const &bit) const; + + bool try_append(DriveBitMultiple const &bit); + + + bool can_append(DriveChunkMultiple const &bit) const; + + bool try_append(DriveChunkMultiple const &bit); + + bool operator==(const DriveChunkMultiple &other) const + { + return width_ == other.width_ && multiple_ == other.multiple_; + } + + bool operator<(const DriveChunkMultiple &other) const + { + if (multiple_.size() < other.multiple_.size()) + + multiple_.sort(); + return false; // TODO implement, canonicalize order + } + + unsigned int hash() const + { + return mkhash(width_, multiple_.hash()); + } +}; + +struct DriveChunk +{ +private: + DriveType type_ = DriveType::NONE; + union + { + int none_; + Const constant_; + DriveChunkWire wire_; + DriveChunkPort port_; + DriveChunkMarker marker_; + DriveChunkMultiple multiple_; + }; + +public: + DriveChunk() { set_none(); } + + DriveChunk(DriveChunk const &other) { *this = other; } + DriveChunk(DriveChunk &&other) { *this = other; } + + DriveChunk(DriveBit const &other) { *this = other; } + + DriveChunk(Const const &constant) { *this = constant; } + DriveChunk(Const &&constant) { *this = constant; } + DriveChunk(DriveChunkWire const &wire) { *this = wire; } + DriveChunk(DriveChunkWire &&wire) { *this = wire; } + DriveChunk(DriveChunkPort const &port) { *this = port; } + DriveChunk(DriveChunkPort &&port) { *this = port; } + DriveChunk(DriveChunkMarker const &marker) { *this = marker; } + DriveChunk(DriveChunkMarker &&marker) { *this = marker; } + DriveChunk(DriveChunkMultiple const &multiple) { *this = multiple; } + DriveChunk(DriveChunkMultiple &&multiple) { *this = multiple; } + + ~DriveChunk() { set_none(); } + + DriveBit operator[](int i) const + { + switch (type_) + { + case DriveType::NONE: + return DriveBit(); + case DriveType::CONSTANT: + return constant_[i]; + case DriveType::WIRE: + return wire_[i]; + case DriveType::PORT: + return port_[i]; + case DriveType::MARKER: + return marker_[i]; + case DriveType::MULTIPLE: + return multiple_[i]; + } + log_abort(); + } + + void set_none(int width = 0) + { + switch (type_) + { + case DriveType::NONE: + none_ = width; + break; + case DriveType::CONSTANT: + constant_.~Const(); + break; + case DriveType::WIRE: + wire_.~DriveChunkWire(); + break; + case DriveType::PORT: + port_.~DriveChunkPort(); + break; + case DriveType::MARKER: + marker_.~DriveChunkMarker(); + break; + case DriveType::MULTIPLE: + multiple_.~DriveChunkMultiple(); + break; + } + type_ = DriveType::NONE; + none_ = width; + } + + DriveChunk &operator=(DriveChunk const &other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = other.constant_; + break; + case DriveType::WIRE: + *this = other.wire_; + break; + case DriveType::PORT: + *this = other.port_; + break; + case DriveType::MARKER: + *this = other.marker_; + break; + case DriveType::MULTIPLE: + *this = other.multiple_; + break; + } + return *this; + } + + DriveChunk &operator=(DriveChunk &&other) + { + switch (other.type_) + { + case DriveType::NONE: + set_none(other.none_); + break; + case DriveType::CONSTANT: + *this = std::move(other.constant_); + break; + case DriveType::WIRE: + *this = std::move(other.wire_); + break; + case DriveType::PORT: + *this = std::move(other.port_); + break; + case DriveType::MARKER: + *this = std::move(other.marker_); + break; + case DriveType::MULTIPLE: + *this = std::move(other.multiple_); + break; + } + return *this; + } + + DriveChunk &operator=(Const const &constant) + { + set_none(); + new (&constant_) Const(constant); + type_ = DriveType::CONSTANT; + return *this; + } + + DriveChunk &operator=(Const &&constant) + { + set_none(); + new (&constant_) Const(std::move(constant)); + type_ = DriveType::CONSTANT; + return *this; + } + + DriveChunk &operator=(DriveChunkWire const &wire) + { + set_none(); + new (&wire_) DriveChunkWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveChunk &operator=(DriveChunkWire &&wire) + { + set_none(); + new (&wire_) DriveChunkWire(wire); + type_ = DriveType::WIRE; + return *this; + } + + DriveChunk &operator=(DriveChunkPort const &port) + { + set_none(); + new (&port_) DriveChunkPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveChunk &operator=(DriveChunkPort &&port) + { + set_none(); + new (&port_) DriveChunkPort(port); + type_ = DriveType::PORT; + return *this; + } + + DriveChunk &operator=(DriveChunkMarker const &marker) + { + set_none(); + new (&marker_) DriveChunkMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveChunk &operator=(DriveChunkMarker &&marker) + { + set_none(); + new (&marker_) DriveChunkMarker(marker); + type_ = DriveType::MARKER; + return *this; + } + + DriveChunk &operator=(DriveChunkMultiple const &multiple) + { + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveChunk &operator=(DriveChunkMultiple &&multiple) + { + set_none(multiple.size()); + if (multiple.multiple().empty()) + return *this; + new (&multiple_) DriveChunkMultiple(multiple); + type_ = DriveType::MULTIPLE; + return *this; + } + + DriveChunk &operator=(DriveBit const &other) + { + switch (other.type()) + { + case DriveType::NONE: + set_none(1); + break; + case DriveType::CONSTANT: + *this = Const(other.constant()); + break; + case DriveType::WIRE: + *this = DriveChunkWire(other.wire()); + break; + case DriveType::PORT: + *this = DriveChunkPort(other.port()); + break; + case DriveType::MARKER: + *this = DriveChunkMarker(other.marker()); + break; + case DriveType::MULTIPLE: + *this = DriveChunkMultiple(other.multiple()); + break; + } + return *this; + } + + bool can_append(DriveBit const &bit) const; + bool try_append(DriveBit const &bit); + bool try_append(DriveChunk const &chunk); + + unsigned int hash() const + { + unsigned int inner; + switch (type_) + { + case DriveType::NONE: + inner = 0; + break; + case DriveType::CONSTANT: + inner = constant_.hash(); + break; + case DriveType::WIRE: + inner = wire_.hash(); + break; + case DriveType::PORT: + inner = port_.hash(); + break; + case DriveType::MARKER: + inner = marker_.hash(); + break; + case DriveType::MULTIPLE: + inner = multiple_.hash(); + break; + } + return mkhash((unsigned int)type_, inner); + } + + bool operator==(const DriveChunk &other) const + { + if (type_ != other.type_) + return false; + + switch (type_) + { + case DriveType::NONE: + return true; + case DriveType::CONSTANT: + return constant_ == other.constant_; + case DriveType::WIRE: + return wire_ == other.wire_; + case DriveType::PORT: + return port_ == other.port_; + case DriveType::MARKER: + return marker_ == other.marker_; + case DriveType::MULTIPLE: + return multiple_ == other.multiple_; + } + log_assert(false); + } + + bool operator!=(const DriveChunk &other) const + { + return !(*this == other); + } + + bool operator<(const DriveChunk &other) const + { + if (type_ != other.type_) + return type_ < other.type_; + switch (type_) + { + case DriveType::NONE: + return false; + case DriveType::CONSTANT: + return constant_ < other.constant_; + case DriveType::WIRE: + return wire_ < other.wire_; + case DriveType::PORT: + return port_ < other.port_; + case DriveType::MARKER: + return marker_ < other.marker_; + case DriveType::MULTIPLE: + return multiple_ < other.multiple_; + } + log_assert(false); + } + + DriveType type() const { return type_; } + + bool is_none() const { return type_ == DriveType::NONE; } + bool is_constant() const { return type_ == DriveType::CONSTANT; } + bool is_wire() const { return type_ == DriveType::WIRE; } + bool is_port() const { return type_ == DriveType::PORT; } + bool is_marker() const { return type_ == DriveType::MARKER; } + bool is_multiple() const { return type_ == DriveType::MULTIPLE; } + + Const &constant() { log_assert(is_constant()); return constant_; } + Const const &constant() const { log_assert(is_constant()); return constant_; } + DriveChunkWire &wire() { log_assert(is_wire()); return wire_; } + DriveChunkWire const &wire() const { log_assert(is_wire()); return wire_; } + DriveChunkPort &port() { log_assert(is_port()); return port_; } + DriveChunkPort const &port() const { log_assert(is_port()); return port_; } + DriveChunkMarker &marker() { log_assert(is_marker()); return marker_; } + DriveChunkMarker const &marker() const { log_assert(is_marker()); return marker_; } + DriveChunkMultiple &multiple() { log_assert(is_multiple()); return multiple_; } + DriveChunkMultiple const &multiple() const { log_assert(is_multiple()); return multiple_; } + + + int size() const + { + switch (type_) + { + case DriveType::NONE: + return none_; + case DriveType::CONSTANT: + return constant_.size(); + case DriveType::WIRE: + return wire_.size(); + case DriveType::PORT: + return port_.size(); + case DriveType::MARKER: + return marker_.size(); + case DriveType::MULTIPLE: + return multiple_.size(); + } + } +}; + +struct DriveSpec +{ +private: + int width_ = 0; + mutable std::vector chunks_; + mutable std::vector bits_; + mutable unsigned int hash_ = 0; +public: + + inline bool packed() const { + return bits_.empty(); + } + + DriveSpec() {} + + DriveSpec(DriveChunk const &chunk) { *this = chunk; } + DriveSpec(DriveChunkWire const &chunk) { *this = chunk; } + DriveSpec(DriveChunkPort const &chunk) { *this = chunk; } + DriveSpec(DriveChunkMarker const &chunk) { *this = chunk; } + DriveSpec(DriveChunkMultiple const &chunk) { *this = chunk; } + + DriveSpec(DriveBit const &bit) { *this = bit; } + DriveSpec(DriveBitWire const &bit) { *this = bit; } + DriveSpec(DriveBitPort const &bit) { *this = bit; } + DriveSpec(DriveBitMarker const &bit) { *this = bit; } + DriveSpec(DriveBitMultiple const &bit) { *this = bit; } + + DriveSpec(std::vector const &chunks) : chunks_(chunks) { compute_width(); } + + DriveSpec(std::vector const &bits) + { + for (auto const &bit : bits) + append(bit); + } + + std::vector const &chunks() const { pack(); return chunks_; } + std::vector const &bits() const { unpack(); return bits_; } + + int size() const { return width_; } + + void append(DriveBit const &bit); + + void append(DriveChunk const &chunk); + + void pack() const; + + void unpack() const; + + DriveBit &operator[](int index) + { + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; + } + + const DriveBit &operator[](int index) const + { + log_assert(index >= 0 && index < size()); + unpack(); + return bits_[index]; + } + + void clear() + { + chunks_.clear(); + bits_.clear(); + width_ = 0; + } + + DriveSpec &operator=(DriveChunk const &chunk) + { + chunks_.clear(); + bits_.clear(); + append(chunk); + return *this; + } + + DriveSpec &operator=(DriveChunkWire const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkPort const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkMarker const &chunk) { return *this = DriveChunk(chunk); } + DriveSpec &operator=(DriveChunkMultiple const &chunk) { return *this = DriveChunk(chunk); } + + DriveSpec &operator=(DriveBit const &bit) + { + chunks_.clear(); + bits_.clear(); + append(bit); + return *this; + } + + DriveSpec &operator=(DriveBitWire const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitPort const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitMarker const &bit) { return *this = DriveBit(bit); } + DriveSpec &operator=(DriveBitMultiple const &bit) { return *this = DriveBit(bit); } + + unsigned int hash() const { + if (hash_ != 0) return hash_; + + pack(); + hash_ = hash_ops>().hash(chunks_); + hash_ |= (hash_ == 0); + return hash_; + } + + bool operator==(DriveSpec const &other) const { + if (size() != other.size() || hash() != other.hash()) + return false; + return chunks() == other.chunks(); + } + +private: + void compute_width(); +}; + + + +struct DriverMap +{ + CellTypes celltypes; + + DriverMap() { celltypes.setup(); } + DriverMap(Design *design) { celltypes.setup(); celltypes.setup_design(design); } + +private: + + // Internally we represent all DriveBits by mapping them to DriveBitIds + // which use less memory and are cheaper to compare. + struct DriveBitId + { + int id = -1; + + DriveBitId() {}; + + DriveBitId(int id) : id(id) { } + + bool operator==(const DriveBitId &other) const { return id == other.id; } + bool operator<(const DriveBitId &other) const { return id < other.id; } + unsigned int hash() const { return id; } + }; + // Essentially a dict> but using less memory + // and fewer allocations + struct DriveBitGraph { + dict first_edges; + dict second_edges; + dict> more_edges; + + void add_edge(DriveBitId src, DriveBitId dst); + DriveBitId pop_edge(DriveBitId src); + void clear(DriveBitId src); + bool contains(DriveBitId src); + int count(DriveBitId src); + + DriveBitId at(DriveBitId src, int index); + }; + + // The following two maps maintain a sparse DriveBit to DriveBitId mapping. + // This saves a lot of memory compared to a `dict` or + // `idict`. + + // Maps wires to the first DriveBitId of the consecutive range used for + // that wire. + dict wire_offsets; + + // Maps cell ports to a the first DriveBitId of the consecutive range used + // for that cell port. + dict, DriveBitId> port_offsets; + + // For the inverse map that maps DriveBitIds back to DriveBits we use a + // sorted map containing only the first DriveBit for each wire and cell + // port. + std::map drive_bits; + + // As a memory optimization for gate level net lists we store single-bit + // wires and cell ports in a `dict` which requires less memory and fewer + // allocations than `std::map` but doesn't support the kind of lookups we + // need for a sparse coarse grained mapping. + dict isolated_drive_bits; + + // Used for allocating DriveBitIds, none and constant states use a fixewd + // mapping to the first few ids, which we need to skip. + int next_offset = 1 + (int)State::Sm; + + // Union-Find over directly connected bits that share the same single + // driver or are undriven. We never merge connections between drivers + // and/or kept wires. + mfp same_driver; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally unambiguous (one side only drives or requires a driven value). + DriveBitGraph connected_drivers; + + // For each bit, store a set of connected driver bits for which the + // explicit connection should be preserved and the driving direction is + // locally ambiguous. Every such ambiguous connection is also present in + // the reverse direction and has to be resolved when querying drivers. + DriveBitGraph connected_undirected; + + // Subset of `connected_undirected` for caching the resolved driving + // direction. In case multiple drivers are present this can still contain + // both orientations of a single connection, but for a single driver only + // one will be present. + DriveBitGraph connected_oriented; + + // Stores for which bits we already resolved the orientation (cached in + // `connected_oriented`). + pool oriented_present; + + + enum class BitMode { + NONE = 0, // Not driven, no need to keep wire + DRIVEN = 1, // Not driven, uses a value driven elsewhere + DRIVEN_UNIQUE = 2, // Uses a value driven elsewhere, has at most one direct connection + KEEP = 3, // Wire that should be kept + TRISTATE = 4, // Can drive a value but can also use a value driven elsewhere + DRIVER = 5, // Drives a value + }; + + BitMode bit_mode(DriveBit const &bit); + DriveBitId id_from_drive_bit(DriveBit const &bit); + DriveBit drive_bit_from_id(DriveBitId id); + + void connect_directed_merge(DriveBitId driven_id, DriveBitId driver_id); + void connect_directed_buffer(DriveBitId driven_id, DriveBitId driver_id); + void connect_undirected(DriveBitId a_id, DriveBitId b_id); + +public: + + void add(Module *module); + + // Add a single bit connection to the driver map. + void add(DriveBit const &a, DriveBit const &b); + + template + static constexpr bool is_sig_type() { + return + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value || + std::is_same::value; + } + + // We use the enable_if to produce better compiler errors when unsupported + // types are used + template + typename std::enable_if() && is_sig_type()>::type + add(T const &a, U const &b) + { + log_assert(a.size() == b.size()); + for (int i = 0; i != GetSize(a); ++i) + add(DriveBit(a[i]), DriveBit(b[i])); + } + + + // Specialized version that avoids unpacking + void add(SigSpec const &a, SigSpec const &b); + +private: + void add_port(Cell *cell, IdString const &port, SigSpec const &b); + + // Only used a local variables in `orient_undirected`, always cleared, only + // stored to reduce allocations. + pool orient_undirected_seen; + pool orient_undirected_drivers; + dict orient_undirected_distance; + + void orient_undirected(DriveBitId id); + +public: + DriveBit operator()(DriveBit const &bit); + + DriveSpec operator()(DriveSpec spec); + +private: + bool keep_wire(Wire *wire) { + // TODO configurable + return wire->has_attribute(ID(keep)); + } +}; + +YOSYS_NAMESPACE_END + +#endif From 68c3a47945972a685f65620eef73f10c86b87741 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 15 Apr 2024 14:14:50 +0200 Subject: [PATCH 087/342] WIP temporary drivertools example --- passes/cmds/Makefile.inc | 1 + passes/cmds/example_dt.cc | 140 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 passes/cmds/example_dt.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 33e3ae1bc..0918a07df 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -49,3 +49,4 @@ OBJS += passes/cmds/xprop.o OBJS += passes/cmds/dft_tag.o OBJS += passes/cmds/future.o OBJS += passes/cmds/box_derive.o +OBJS += passes/cmds/example_dt.o diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc new file mode 100644 index 000000000..de84fa3cd --- /dev/null +++ b/passes/cmds/example_dt.cc @@ -0,0 +1,140 @@ +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + + + +struct ExampleWorker +{ + DriverMap dm; + Module *module; + + ExampleWorker(Module *module) : module(module) { + dm.celltypes.setup(); + } +}; + +struct ExampleDtPass : public Pass +{ + ExampleDtPass() : Pass("example_dt", "drivertools example") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + + void execute(std::vector args, RTLIL::Design *design) override + { + size_t argidx = 1; + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + ExampleWorker worker(module); + DriverMap dm; + + dm.add(module); + + idict queue; + idict cells; + + IntGraph edges; + + + for (auto cell : module->cells()) { + if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + queue(DriveBitMarker(cells(cell), 0)); + } + + for (auto wire : module->wires()) { + if (!wire->port_output) + continue; + queue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + } + +#define emit log +// #define emit(X...) do {} while (false) + + for (int i = 0; i != GetSize(queue); ++i) + { + emit("n%d: ", i); + DriveSpec spec = queue[i]; + if (spec.chunks().size() > 1) { + emit("concat %s <-\n", log_signal(spec)); + for (auto const &chunk : spec.chunks()) { + emit(" * %s\n", log_signal(chunk)); + edges.add_edge(i, queue(chunk)); + } + } else if (spec.chunks().size() == 1) { + DriveChunk chunk = spec.chunks()[0]; + if (chunk.is_wire()) { + DriveChunkWire wire_chunk = chunk.wire(); + if (wire_chunk.is_whole()) { + if (wire_chunk.wire->port_input) { + emit("input %s\n", log_signal(spec)); + } else { + DriveSpec driver = dm(DriveSpec(wire_chunk)); + edges.add_edge(i, queue(driver)); + emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver)); + } + } else { + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); + edges.add_edge(i, queue(whole_wire)); + emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire))); + } + } else if (chunk.is_port()) { + DriveChunkPort port_chunk = chunk.port(); + if (port_chunk.is_whole()) { + if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { + int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0)); + if (!port_chunk.cell->type.in(ID($dff), ID($ff))) + edges.add_edge(i, cell_marker); + emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port)); + } else { + DriveSpec driver = dm(DriveSpec(port_chunk)); + edges.add_edge(i, queue(driver)); + emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver)); + } + + } else { + DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); + edges.add_edge(i, queue(whole_port)); + emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port))); + } + } else if (chunk.is_constant()) { + emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant())); + } else if (chunk.is_marker()) { + Cell *cell = cells[chunk.marker().marker]; + emit("cell %s %s\n", log_id(cell->type), log_id(cell)); + for (auto const &conn : cell->connections()) { + if (!dm.celltypes.cell_input(cell->type, conn.first)) + continue; + emit(" * %s <- %s\n", log_id(conn.first), log_signal(conn.second)); + edges.add_edge(i, queue(DriveChunkPort(cell, conn))); + } + } else { + log_abort(); + } + } else { + log_abort(); + } + } + + topo_sorted_sccs(edges, [&](int *begin, int *end) { + emit("scc:"); + for (int *i = begin; i != end; ++i) + emit(" n%d", *i); + emit("\n"); + }); + + } + log("Plugin test passed!\n"); + } +} ExampleDtPass; + +PRIVATE_NAMESPACE_END From f29422f745a534d09cb0917a8587639ac5b08e10 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 11 Apr 2024 13:47:14 +0200 Subject: [PATCH 088/342] topo_scc: Add sources_first option --- kernel/topo_scc.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h index 0ae0e696b..89df8928a 100644 --- a/kernel/topo_scc.h +++ b/kernel/topo_scc.h @@ -194,7 +194,7 @@ public: }; template -void topo_sorted_sccs(G &graph, ComponentCallback component) +void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first = false) { typedef typename G::node_enumerator node_enumerator; typedef typename G::successor_enumerator successor_enumerator; @@ -217,6 +217,23 @@ void topo_sorted_sccs(G &graph, ComponentCallback component) node_enumerator nodes = graph.enumerate_nodes(); + if (sources_first) { + while (!nodes.finished()) { + node_type node = nodes.next(); + successor_enumerator successors = graph.enumerate_successors(node); + if (successors.finished()) + { + graph.dfs_index(node) = next_index; + next_index++; + component_stack.push_back(node); + component(component_stack.data(), component_stack.data() + 1); + component_stack.clear(); + graph.dfs_index(node) = INT_MAX; + } + } + nodes = graph.enumerate_nodes(); + } + // iterate over all nodes to ensure we process the whole graph while (!nodes.finished()) { node_type node = nodes.next(); From d4e3daa9d0037e2397dc74e3862b5b41c67716e5 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Thu, 11 Apr 2024 13:48:25 +0200 Subject: [PATCH 089/342] ComputeGraph datatype for the upcoming functional backend --- kernel/functional.h | 369 ++++++++++++++++++++++++++++++++++++++ passes/cmds/example_dt.cc | 178 ++++++++++++++---- 2 files changed, 515 insertions(+), 32 deletions(-) create mode 100644 kernel/functional.h diff --git a/kernel/functional.h b/kernel/functional.h new file mode 100644 index 000000000..e5ee88240 --- /dev/null +++ b/kernel/functional.h @@ -0,0 +1,369 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef FUNCTIONAL_H +#define FUNCTIONAL_H + +#include +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +template< + typename Fn, // Function type (deduplicated across whole graph) + typename Attr = std::tuple<>, // Call attributes (present in every node) + typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node) + typename Key = std::tuple<> // Stable keys to refer to nodes +> +struct ComputeGraph +{ + struct Ref; +private: + + // Functions are deduplicated by assigning unique ids + idict functions; + + struct Node { + int fn_index; + int arg_offset; + int arg_count; + Attr attr; + + Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {} + + Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {} + }; + + + std::vector nodes; + std::vector args; + dict keys_; + dict sparse_attrs; + +public: + template + struct BaseRef + { + protected: + friend struct ComputeGraph; + Graph *graph_; + int index_; + BaseRef(Graph *graph, int index) : graph_(graph), index_(index) { + log_assert(index_ >= 0); + check(); + } + + void check() const { log_assert(index_ < graph_->size()); } + + Node const &deref() const { check(); return graph_->nodes[index_]; } + + public: + ComputeGraph const &graph() const { return graph_; } + int index() const { return index_; } + + int size() const { return deref().arg_count; } + + BaseRef arg(int n) const + { + Node const &node = deref(); + log_assert(n >= 0 && n < node.arg_count); + return BaseRef(graph_, graph_->args[node.arg_offset + n]); + } + + std::vector::const_iterator arg_indices_cbegin() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset; + } + + std::vector::const_iterator arg_indices_cend() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset + node.arg_count; + } + + Fn const &function() const { return graph_->functions[deref().fn_index]; } + Attr const &attr() const { return deref().attr; } + + bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); } + + SparseAttr const &sparse_attr() const + { + auto found = graph_->sparse_attrs.find(index_); + log_assert(found != graph_->sparse_attrs.end()); + return *found; + } + }; + + using ConstRef = BaseRef; + + struct Ref : public BaseRef + { + private: + friend struct ComputeGraph; + Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} + Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } + + public: + void set_function(Fn const &function) const + { + deref().fn_index = this->graph_->functions(function); + } + + Attr &attr() const { return deref().attr; } + + void append_arg(ConstRef arg) const + { + log_assert(arg.graph_ == this->graph_); + append_arg(arg.index()); + } + + void append_arg(int arg) const + { + log_assert(arg >= 0 && arg < this->graph_->size()); + Node &node = deref(); + if (node.arg_offset + node.arg_count != GetSize(this->graph_->args)) + move_args(node); + this->graph_->args.push_back(arg); + node.arg_count++; + } + + operator ConstRef() const + { + return ConstRef(this->graph_, this->index_); + } + + SparseAttr &sparse_attr() const + { + return this->graph_->sparse_attrs[this->index_]; + } + + void clear_sparse_attr() const + { + this->graph_->sparse_attrs.erase(this->index_); + } + + void assign_key(Key const &key) const + { + this->graph_->keys_.emplace(key, this->index_); + } + + private: + void move_args(Node &node) const + { + auto &args = this->graph_->args; + int old_offset = node.arg_offset; + node.arg_offset = GetSize(args); + for (int i = 0; i != node.arg_count; ++i) + args.push_back(args[old_offset + i]); + } + + }; + + bool has_key(Key const &key) const + { + return keys_.count(key); + } + + dict const &keys() const + { + return keys_; + } + + ConstRef operator()(Key const &key) const + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + Ref operator()(Key const &key) + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + int size() const { return GetSize(nodes); } + + ConstRef operator[](int index) const { return ConstRef(this, index); } + Ref operator[](int index) { return Ref(this, index); } + + Ref add(Fn const &function, Attr &&attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, std::move(attr), GetSize(args)); + return Ref(this, index); + } + + Ref add(Fn const &function, Attr const &attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, attr, GetSize(args)); + return Ref(this, index); + } + + template + Ref add(Fn const &function, Attr const &attr, T const &args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr &&attr, T const &args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr const &attr, T begin, T end) + { + Ref added = add(function, attr); + for (; begin != end; ++begin) + added.append_arg(*begin); + return added; + } + + void permute(std::vector const &perm) + { + log_assert(perm.size() <= nodes.size()); + std::vector inv_perm; + inv_perm.resize(nodes.size(), -1); + for (int i = 0; i < GetSize(perm); ++i) + { + int j = perm[i]; + log_assert(j >= 0 && j < GetSize(perm)); + log_assert(inv_perm[j] == -1); + inv_perm[j] = i; + } + permute(perm, inv_perm); + } + + void permute(std::vector const &perm, std::vector const &inv_perm) + { + log_assert(inv_perm.size() == nodes.size()); + std::vector new_nodes; + new_nodes.reserve(perm.size()); + dict new_sparse_attrs; + for (int i : perm) + { + int j = GetSize(new_nodes); + new_nodes.emplace_back(std::move(nodes[i])); + auto found = sparse_attrs.find(i); + if (found != sparse_attrs.end()) + new_sparse_attrs.emplace(j, std::move(found->second)); + } + + std::swap(nodes, new_nodes); + std::swap(sparse_attrs, new_sparse_attrs); + + for (int &arg : args) + { + log_assert(arg < GetSize(inv_perm)); + arg = inv_perm[arg]; + } + + for (auto &key : keys_) + { + log_assert(key.second < GetSize(inv_perm)); + key.second = inv_perm[key.second]; + } + } + + struct SccAdaptor + { + private: + ComputeGraph const &graph_; + std::vector indices_; + public: + SccAdaptor(ComputeGraph const &graph) : graph_(graph) + { + indices_.resize(graph.size(), -1); + } + + + typedef int node_type; + + struct node_enumerator { + private: + friend struct SccAdaptor; + int current, end; + node_enumerator(int current, int end) : current(current), end(end) {} + + public: + + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + + node_enumerator enumerate_nodes() { + return node_enumerator(0, GetSize(indices_)); + } + + + struct successor_enumerator { + private: + friend struct SccAdaptor; + std::vector::const_iterator current, end; + successor_enumerator(std::vector::const_iterator current, std::vector::const_iterator end) : + current(current), end(end) {} + + public: + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = *current; + ++current; + return result; + } + }; + + successor_enumerator enumerate_successors(int index) const { + auto const &ref = graph_[index]; + return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend()); + } + + int &dfs_index(node_type const &node) { return indices_[node]; } + + std::vector const &dfs_indices() { return indices_; } + }; + +}; + + + +YOSYS_NAMESPACE_END + + +#endif diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index de84fa3cd..dec554d6c 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -1,6 +1,7 @@ #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" +#include "kernel/functional.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -38,86 +39,137 @@ struct ExampleDtPass : public Pass ExampleWorker worker(module); DriverMap dm; + struct ExampleFn { + IdString name; + dict parameters; + + ExampleFn(IdString name) : name(name) {} + ExampleFn(IdString name, dict parameters) : name(name), parameters(parameters) {} + + bool operator==(ExampleFn const &other) const { + return name == other.name && parameters == other.parameters; + } + + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } + }; + + typedef ComputeGraph ExampleGraph; + + ExampleGraph compute_graph; + + dm.add(module); idict queue; idict cells; IntGraph edges; + std::vector graph_nodes; + auto enqueue = [&](DriveSpec const &spec) { + int index = queue(spec); + if (index == GetSize(graph_nodes)) + graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index()); + //if (index >= GetSize(graph_nodes)) + return compute_graph[graph_nodes[index]]; + }; for (auto cell : module->cells()) { if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) - queue(DriveBitMarker(cells(cell), 0)); + enqueue(DriveBitMarker(cells(cell), 0)); } for (auto wire : module->wires()) { if (!wire->port_output) continue; - queue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))).assign_key(wire->name); } -#define emit log -// #define emit(X...) do {} while (false) - for (int i = 0; i != GetSize(queue); ++i) { - emit("n%d: ", i); DriveSpec spec = queue[i]; + ExampleGraph::Ref node = compute_graph[i]; + if (spec.chunks().size() > 1) { - emit("concat %s <-\n", log_signal(spec)); + node.set_function(ID($$concat)); + for (auto const &chunk : spec.chunks()) { - emit(" * %s\n", log_signal(chunk)); - edges.add_edge(i, queue(chunk)); + node.append_arg(enqueue(chunk)); } } else if (spec.chunks().size() == 1) { DriveChunk chunk = spec.chunks()[0]; if (chunk.is_wire()) { DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { + node.sparse_attr() = wire_chunk.wire->name; if (wire_chunk.wire->port_input) { - emit("input %s\n", log_signal(spec)); + node.set_function(ExampleFn(ID($$input), {{wire_chunk.wire->name, {}}})); } else { DriveSpec driver = dm(DriveSpec(wire_chunk)); - edges.add_edge(i, queue(driver)); - emit("wire driver %s <- %s\n", log_signal(spec), log_signal(driver)); + node.set_function(ID($$buf)); + + node.append_arg(enqueue(driver)); } } else { DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); - edges.add_edge(i, queue(whole_wire)); - emit("wire slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_wire))); + node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}})); + node.append_arg(enqueue(whole_wire)); } } else if (chunk.is_port()) { DriveChunkPort port_chunk = chunk.port(); if (port_chunk.is_whole()) { if (dm.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { - int cell_marker = queue(DriveBitMarker(cells(port_chunk.cell), 0)); - if (!port_chunk.cell->type.in(ID($dff), ID($ff))) - edges.add_edge(i, cell_marker); - emit("cell output %s %s\n", log_id(port_chunk.cell), log_id(port_chunk.port)); + if (port_chunk.cell->type.in(ID($dff), ID($ff))) + { + Cell *cell = port_chunk.cell; + node.set_function(ExampleFn(ID($$state), {{cell->name, {}}})); + for (auto const &conn : cell->connections()) { + if (!dm.celltypes.cell_input(cell->type, conn.first)) + continue; + enqueue(DriveChunkPort(cell, conn)).assign_key(cell->name); + } + } + else + { + node.set_function(ExampleFn(ID($$cell_output), {{port_chunk.port, {}}})); + node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0))); + } } else { + node.set_function(ID($$buf)); + DriveSpec driver = dm(DriveSpec(port_chunk)); - edges.add_edge(i, queue(driver)); - emit("cell port driver %s <- %s\n", log_signal(spec), log_signal(driver)); + node.append_arg(enqueue(driver)); } } else { DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); - edges.add_edge(i, queue(whole_port)); - emit("port slice %s <- %s\n", log_signal(spec), log_signal(DriveSpec(whole_port))); + node.set_function(ID($$buf)); + node.append_arg(enqueue(whole_port)); } } else if (chunk.is_constant()) { - emit("constant %s <- %s\n", log_signal(spec), log_const(chunk.constant())); + node.set_function(ExampleFn(ID($$const), {{ID(value), chunk.constant()}})); + + } else if (chunk.is_multiple()) { + node.set_function(ID($$multi)); + for (auto const &driver : chunk.multiple().multiple()) + node.append_arg(enqueue(driver)); } else if (chunk.is_marker()) { Cell *cell = cells[chunk.marker().marker]; - emit("cell %s %s\n", log_id(cell->type), log_id(cell)); + + node.set_function(ExampleFn(cell->type, cell->parameters)); for (auto const &conn : cell->connections()) { if (!dm.celltypes.cell_input(cell->type, conn.first)) continue; - emit(" * %s <- %s\n", log_id(conn.first), log_signal(conn.second)); - edges.add_edge(i, queue(DriveChunkPort(cell, conn))); + + node.append_arg(enqueue(DriveChunkPort(cell, conn))); } + } else if (chunk.is_none()) { + node.set_function(ID($$undriven)); + } else { + log_error("unhandled drivespec: %s\n", log_signal(chunk)); log_abort(); } } else { @@ -125,13 +177,75 @@ struct ExampleDtPass : public Pass } } - topo_sorted_sccs(edges, [&](int *begin, int *end) { - emit("scc:"); - for (int *i = begin; i != end; ++i) - emit(" n%d", *i); - emit("\n"); - }); + // Perform topo sort and detect SCCs + ExampleGraph::SccAdaptor compute_graph_scc(compute_graph); + + + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + } + }, /* sources_first */ true); + compute_graph.permute(perm); + + + // Forward $$buf unless we have a name in the sparse attribute + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + if (compute_graph[i].function().name == ID($$buf) && !compute_graph[i].has_sparse_attr() && compute_graph[i].arg(0).index() < i) + { + + alias.push_back(alias[compute_graph[i].arg(0).index()]); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + log("n%d ", i); + log("%s", log_id(ref.function().name)); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + log("[%s]", log_id(param.first)); + else + log("[%s=%s]", log_id(param.first), log_const(param.second)); + } + log("("); + + for (int i = 0, end = ref.size(); i != end; ++i) + { + if (i > 0) + log(", "); + log("n%d", ref.arg(i).index()); + } + log(")\n"); + if (ref.has_sparse_attr()) + log("// wire %s\n", log_id(ref.sparse_attr())); + log("// was #%d %s\n", ref.attr(), log_signal(queue[ref.attr()])); + } + + for (auto const &key : compute_graph.keys()) + { + log("return %d as %s \n", key.second, log_id(key.first)); + } } log("Plugin test passed!\n"); } From d90268f6104d8b88294629c636ec0ab979785c44 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Wed, 17 Apr 2024 14:52:36 +0200 Subject: [PATCH 090/342] fixup! drivertools: Utility code for indexing and traversing signal drivers --- kernel/drivertools.cc | 23 +++++++++++++---------- kernel/drivertools.h | 1 + 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 499a9399c..286c913a2 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -499,7 +499,7 @@ int DriverMap::DriveBitGraph::count(DriveBitId src) auto found = more_edges.find(src); if (found == more_edges.end()) return 2; - return GetSize(found->second); + return GetSize(found->second) + 2; } DriverMap::DriveBitId DriverMap::DriveBitGraph::at(DriveBitId src, int index) @@ -688,7 +688,7 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b) // and use the other end as representative bit. else if (a_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) connect_directed_buffer(a_id, b_id); - else if (b_mode == BitMode::DRIVEN_UNIQUE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) + else if (b_mode == BitMode::DRIVEN_UNIQUE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) connect_directed_buffer(b_id, a_id); // If either bit only drives a value, store a directed connection from // it to the other bit. @@ -827,15 +827,18 @@ DriveBit DriverMap::operator()(DriveBit const &bit) DriveBitId bit_id = id_from_drive_bit(bit); - bit_id = same_driver.find(bit_id); + DriveBitId bit_repr_id = same_driver.find(bit_id); - DriveBit bit_repr = drive_bit_from_id(bit_id); + DriveBit bit_repr = drive_bit_from_id(bit_repr_id); BitMode mode = bit_mode(bit_repr); - int implicit_driver_count = connected_drivers.count(bit_id); - if (connected_undirected.contains(bit_id) && !oriented_present.count(bit_id)) - orient_undirected(bit_id); + if (mode == BitMode::KEEP && bit_repr_id != bit_id) + return bit_repr; + + int implicit_driver_count = connected_drivers.count(bit_repr_id); + if (connected_undirected.contains(bit_repr_id) && !oriented_present.count(bit_repr_id)) + orient_undirected(bit_repr_id); DriveBit driver; @@ -843,11 +846,11 @@ DriveBit DriverMap::operator()(DriveBit const &bit) driver = bit_repr; for (int i = 0; i != implicit_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_drivers.at(bit_id, i))); + driver.merge(drive_bit_from_id(connected_drivers.at(bit_repr_id, i))); - int oriented_driver_count = connected_oriented.count(bit_id); + int oriented_driver_count = connected_oriented.count(bit_repr_id); for (int i = 0; i != oriented_driver_count; ++i) - driver.merge(drive_bit_from_id(connected_oriented.at(bit_id, i))); + driver.merge(drive_bit_from_id(connected_oriented.at(bit_repr_id, i))); return driver; } diff --git a/kernel/drivertools.h b/kernel/drivertools.h index b440afdda..1cb835df2 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -1165,6 +1165,7 @@ private: DriveBitId(int id) : id(id) { } bool operator==(const DriveBitId &other) const { return id == other.id; } + bool operator!=(const DriveBitId &other) const { return id != other.id; } bool operator<(const DriveBitId &other) const { return id < other.id; } unsigned int hash() const { return id; } }; From dd5ec84a26725a085038a3afcc1e211ae7cdcd5c Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 1 May 2024 11:47:16 +0100 Subject: [PATCH 091/342] fix bugs in drivertools --- kernel/drivertools.cc | 4 ++-- passes/cmds/example_dt.cc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 286c913a2..9627a4670 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -680,9 +680,9 @@ void DriverMap::add(DriveBit const &a, DriveBit const &b) // If either bit is just a wire that we don't need to keep, merge and // use the other end as representative bit. - if (a_mode == BitMode::NONE) + if (a_mode == BitMode::NONE && !(b_mode == BitMode::DRIVEN_UNIQUE || b_mode == BitMode::DRIVEN)) connect_directed_merge(a_id, b_id); - else if (b_mode == BitMode::NONE) + else if (b_mode == BitMode::NONE && !(a_mode == BitMode::DRIVEN_UNIQUE || a_mode == BitMode::DRIVEN)) connect_directed_merge(b_id, a_id); // If either bit requires a driven value and has a unique driver, merge // and use the other end as representative bit. diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index dec554d6c..859b0b7ba 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -113,7 +113,7 @@ struct ExampleDtPass : public Pass node.append_arg(enqueue(driver)); } } else { - DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.width); + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); node.set_function(ExampleFn(ID($$slice), {{ID(offset), wire_chunk.offset}, {ID(width), wire_chunk.width}})); node.append_arg(enqueue(whole_wire)); } @@ -145,7 +145,7 @@ struct ExampleDtPass : public Pass } else { DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); - node.set_function(ID($$buf)); + node.set_function(ExampleFn(ID($$slice), {{ID(offset), port_chunk.offset}})); node.append_arg(enqueue(whole_port)); } } else if (chunk.is_constant()) { From 63dea89facd9676b14da11f2e6bb79aa0ff3c583 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 1 May 2024 11:48:04 +0100 Subject: [PATCH 092/342] add initial version of functional C++ backend --- backends/functional/Makefile.inc | 1 + backends/functional/cxx.cc | 417 ++++++++++++++++++++++++++ backends/functional/cxx_runtime/sim.h | 366 ++++++++++++++++++++++ kernel/graphtools.h | 332 ++++++++++++++++++++ 4 files changed, 1116 insertions(+) create mode 100644 backends/functional/Makefile.inc create mode 100644 backends/functional/cxx.cc create mode 100644 backends/functional/cxx_runtime/sim.h create mode 100644 kernel/graphtools.h diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc new file mode 100644 index 000000000..011e66264 --- /dev/null +++ b/backends/functional/Makefile.inc @@ -0,0 +1 @@ +OBJS += backends/functional/cxx.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc new file mode 100644 index 000000000..46ce88bd6 --- /dev/null +++ b/backends/functional/cxx.cc @@ -0,0 +1,417 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +const char *reserved_keywords[] = { + "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", + "atomic_noexcept","auto","bitand","bitor","bool","break","case", + "catch","char","char16_t","char32_t","char8_t","class","co_await", + "co_return","co_yield","compl","concept","const","const_cast","consteval", + "constexpr","constinit","continue","decltype","default","delete", + "do","double","dynamic_cast","else","enum","explicit","export", + "extern","false","float","for","friend","goto","if","inline", + "int","long","mutable","namespace","new","noexcept","not","not_eq", + "nullptr","operator","or","or_eq","private","protected","public", + "reflexpr","register","reinterpret_cast","requires","return","short", + "signed","sizeof","static","static_assert","static_cast","struct", + "switch","synchronized","template","this","thread_local","throw", + "true","try","typedef","typeid","typename","union","unsigned", + "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", + nullptr +}; + +struct CxxScope { + pool used_names; + dict name_map; + + CxxScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct CxxWriter { + std::ostream &f; + CxxWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } +}; + +struct CxxStruct { + std::string name; + dict types; + CxxScope scope; + CxxStruct(std::string name) : name(name) { + scope.reserve("out"); + scope.reserve("dump"); + } + void insert(IdString name, std::string type) { + scope.insert(name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.printf("struct %s {\n", name.c_str()); + for (auto p : types) { + f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + } + f.printf("\n\ttemplate void dump(T &out) {\n"); + for (auto p : types) { + f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + } + f.printf("\t}\n};\n\n"); + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct CxxFunction { + IdString name; + int width; + dict parameters; + + CxxFunction(IdString name, int width) : name(name), width(width) {} + CxxFunction(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} + + bool operator==(CxxFunction const &other) const { + return name == other.name && parameters == other.parameters && width == other.width; + } + + unsigned int hash() const { + return mkhash(name.hash(), parameters.hash()); + } +}; + +typedef ComputeGraph CxxComputeGraph; + +class CxxComputeGraphFactory { + CxxComputeGraph &graph; + using T = CxxComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } +public: + CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + else + return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); + } + T concat(T a, int a_width, T b, int b_width) { + return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array{a, b}); + } + T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array{a, b}); } + T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array{a, b}); } + T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array{a, b}); } + T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array{a, b}); } + T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array{a, b}); } + T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array{a}); } + T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array{a}); } + T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array{a, b, s}); } + T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array{a, b, s}); } + T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array{a}); } + T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array{a}); } + T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array{a}); } + T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array{a, b}); } + T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array{a, b}); } + T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array{a, b}); } + T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array{a, b}); } + T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array{a, b}); } + T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array{a, b}); } + T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } + + T constant(RTLIL::Const value) { + return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); + } + T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } + T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); + } + T multiple(vector args, int width) { + return graph.add(CxxFunction(ID($$multiple), width), 0, args); + } + T undriven(int width) { + return graph.add(CxxFunction(ID($$undriven), width), 0); + } + + T create_pending(int width) { + return graph.add(CxxFunction(ID($$pending), width), 0); + } + void update_pending(T pending, T node) { + assert(pending.function().name == ID($$pending)); + pending.set_function(CxxFunction(ID($$buf), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name) { + node.assign_key(name); + } + void declare_state(T node, IdString name) { + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +struct FunctionalCxxBackend : public Backend +{ + FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + CxxComputeGraph calculate_compute_graph(RTLIL::Module *module) + { + CxxComputeGraph compute_graph; + CxxComputeGraphFactory factory(compute_graph); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().name == ID($$buf) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); + return compute_graph; + } + + void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) + { + dict inputs, state; + CxxWriter f(stream); + + // Dump the compute graph + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + if(ref.function().name == ID($$input)) + inputs[ref.function().parameters.begin()->first] = ref.function().width; + if(ref.function().name == ID($$state)) + state[ref.function().parameters.begin()->first] = ref.function().width; + } + f.printf("#include \"sim.h\"\n"); + CxxStruct input_struct(name + "_Inputs"); + for (auto const &input : inputs) + input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); + CxxStruct output_struct(name + "_Outputs"); + for (auto const &key : compute_graph.keys()) + if(state.count(key.first) == 0) + output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); + CxxStruct state_struct(name + "_State"); + for (auto const &state_var : state) + state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); + + idict node_names; + CxxScope locals; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + locals.reserve("input"); + locals.reserve("output"); + locals.reserve("current_state"); + locals.reserve("next_state"); + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + int width = ref.function().width; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + if(ref.function().name == ID($$input)) + f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$state)) + f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); + else if(ref.function().name == ID($$buf)) + f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); + else if(ref.function().name == ID($$cell_output)) + f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); + else if(ref.function().name == ID($$const)){ + auto c = ref.function().parameters.begin()->second; + if(c.size() <= 32){ + f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); + }else{ + f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); + while(c.size() > 32){ + c = c.extract(32, c.size() - 32); + f.printf(", %#x", c.as_int()); + } + f.printf("});\n"); + } + }else if(ref.function().name == ID($$undriven)) + f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); + else if(ref.function().name == ID($$slice)) + f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); + else if(ref.function().name == ID($$concat)){ + f.printf("\tauto %s = concat(", name.c_str()); + for (int i = 0, end = ref.size(); i != end; ++i){ + if(i > 0) + f.printf(", "); + f.printf("%s", node_names[ref.arg(i).index()].c_str()); + } + f.printf(");\n"); + }else{ + f.printf("\t"); + if(ref.function().width > 0) + f.printf("Signal<%d>", ref.function().width); + else + f.printf("%s_Outputs", log_id(ref.function().name)); + f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); + if(ref.function().parameters.count(ID(WIDTH))){ + f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); + } + f.printf("("); + for (int i = 0, end = ref.size(); i != end; ++i) + f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); + f.printf("); //"); + for (auto const ¶m : ref.function().parameters) + { + if (param.second.empty()) + f.printf("[%s]", log_id(param.first)); + else + f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); + } + f.printf("\n"); + } + } + + for (auto const &key : compute_graph.keys()) + { + f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); + } + f.printf("}\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional C++ backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + auto compute_graph = calculate_compute_graph(module); + printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); + } + } +} FunctionalCxxBackend; + +PRIVATE_NAMESPACE_END diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h new file mode 100644 index 000000000..4e7d9b601 --- /dev/null +++ b/backends/functional/cxx_runtime/sim.h @@ -0,0 +1,366 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef SIM_H +#define SIM_H + +#include + +template +using Signal = std::array; + +template +Signal slice(Signal const& a, size_t offset) +{ + Signal ret; + + std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin()); + return ret; +} + +template +Signal $const(uint32_t val) +{ + size_t i; + Signal ret; + + for(i = 0; i < n; i++) + if(i < 32) + ret[i] = val & (1< +Signal $const(std::initializer_list vals) +{ + size_t k, i; + Signal ret; + + k = 0; + for (auto val : vals) { + for(i = 0; i < 32; i++) + if(i + k < n) + ret[i + k] = val & (1< +bool as_bool(Signal sig) +{ + for(int i = 0; i < n; i++) + if(sig[i]) + return true; + return false; +} + +template +uint32_t as_int(Signal sig) +{ + uint32_t ret = 0; + for(int i = 0; i < n; i++) + if(sig[i] && i < 32) + ret |= 1< +Signal $mux(Signal const& a, Signal const &b, Signal<1> const &s) +{ + return s[0] ? b : a; +} + +template +Signal $not(Signal const& a) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = !a[i]; + return ret; +} + +template +Signal $neg(Signal const& a) +{ + Signal ret; + bool carry = true; + for(size_t i = 0; i < n; i++) { + int r = !a[i] + carry; + ret[i] = (r & 1) != 0; + carry = (r >> 1) != 0; + } + return ret; +} + +template +Signal<1> $reduce_or(Signal const& a) +{ + return { as_bool(a) }; +} + +template +Signal<1> $reduce_and(Signal const& a) +{ + for(size_t i = 0; i < n; i++) + if(!a[i]) + return { false }; + return { true }; +} + +template +Signal<1> $reduce_bool(Signal const& a) +{ + return { as_bool(a) }; +} + +template +Signal<1> $logic_and(Signal const& a, Signal const& b) +{ + return { as_bool(a) && as_bool(b) }; +} + +template +Signal<1> $logic_or(Signal const& a, Signal const& b) +{ + return { as_bool(a) || as_bool(b) }; +} + +template +Signal<1> $logic_not(Signal const& a) +{ + return { !as_bool(a) }; +} + +template +Signal $add(Signal const& a, Signal const &b) +{ + Signal ret; + size_t i; + int x = 0; + for(i = 0; i < n; i++){ + x += (int)a[i] + (int)b[i]; + ret[i] = x & 1; + x >>= 1; + } + return ret; +} +template +Signal $sub(Signal const& a, Signal const &b) +{ + Signal ret; + int x = 1; + for(size_t i = 0; i < n; i++){ + x += (int)a[i] + (int)!b[i]; + ret[i] = x & 1; + x >>= 1; + } + return ret; +} + +template +Signal<1> $uge(Signal const& a, Signal const &b) +{ + for(size_t i = n; i-- != 0; ) + if(a[i] != b[i]) + return { a[i] }; + return { true }; +} + +template +Signal<1> $ugt(Signal const& a, Signal const &b) +{ + for(size_t i = n; i-- != 0; ) + if(a[i] != b[i]) + return { a[i] }; + return { false }; +} + +template +Signal<1> $ge(Signal const& a, Signal const &b) +{ + if(a[n-1] != b[n-1]) + return { b[n-1] }; + return $uge(a, b); +} + +template +Signal<1> $gt(Signal const& a, Signal const &b) +{ + if(a[n-1] != b[n-1]) + return { b[n-1] }; + return $ugt(a, b); +} + +template Signal<1> $ule(Signal const& a, Signal const &b) { return $uge(b, a); } +template Signal<1> $ult(Signal const& a, Signal const &b) { return $ugt(b, a); } +template Signal<1> $le(Signal const& a, Signal const &b) { return $ge(b, a); } +template Signal<1> $lt(Signal const& a, Signal const &b) { return $gt(b, a); } + +template +Signal $and(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] && b[i]; + return ret; +} + +template +Signal $or(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] || b[i]; + return ret; +} + +template +Signal $xor(Signal const& a, Signal const &b) +{ + Signal ret; + for(size_t i = 0; i < n; i++) + ret[i] = a[i] != b[i]; + return ret; +} + +template +Signal $shl(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret = $const(0); + if(amount < n){ + if(amount + na > n) + std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount); + else + std::copy(a.begin(), a.end(), ret.begin() + amount); + } + return ret; +} + +template +Signal $shr(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret; + for (size_t i = 0; i < n; i++) { + if(i + amount < n) + ret[i] = a[i + amount]; + else + ret[i] = false; + } + return ret; +} + +template +Signal $asr(Signal const& a, Signal const &b) +{ + if(nb >= sizeof(int) * 8 - 1) + for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) + assert(!b[i]); + size_t amount = as_int(b); + Signal ret; + for (size_t i = 0; i < n; i++) { + if(i + amount < n) + ret[i] = a[i + amount]; + else + ret[i] = a[n - 1]; + } + return ret; +} + +template +Signal<1> $eq(Signal const& a, Signal const &b) +{ + for(size_t i = 0; i < n; i++) + if(a[i] != b[i]) + return { false }; + return { true }; +} + +template +Signal<1> $ne(Signal const& a, Signal const &b) +{ + for(size_t i = 0; i < n; i++) + if(a[i] != b[i]) + return { true }; + return { false }; +} + +template +Signal $pmux(Signal const& a, Signal const &b, Signal const &s) +{ + bool found; + Signal ret; + + found = false; + ret = a; + for(size_t i = 0; i < ns; i++){ + if(s[i]){ + if(found) + return $const(0); + found = true; + ret = slice(b, n * i); + } + } + return ret; +} + +template +Signal concat(Signal const& a, Signal const& b) +{ + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + std::copy(b.begin(), b.end(), ret.begin() + n); + return ret; +} + +template +Signal $zero_extend(Signal const& a) +{ + assert(n >= m); + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + for(size_t i = m; i < n; i++) + ret[i] = false; + return ret; +} + +template +Signal $sign_extend(Signal const& a) +{ + assert(n >= m); + Signal ret; + std::copy(a.begin(), a.end(), ret.begin()); + for(size_t i = m; i < n; i++) + ret[i] = a[m-1]; + return ret; +} + +#endif diff --git a/kernel/graphtools.h b/kernel/graphtools.h new file mode 100644 index 000000000..1a59ef1b5 --- /dev/null +++ b/kernel/graphtools.h @@ -0,0 +1,332 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef GRAPHTOOLS_H +#define GRAPHTOOLS_H + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/functional.h" + +USING_YOSYS_NAMESPACE +YOSYS_NAMESPACE_BEGIN + +template +class CellSimplifier { + Factory &factory; + T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { + log_assert(y_width > 0); + int new_width = sizeof(int) * 8 - __builtin_clz(y_width); + if (b_width <= new_width) { + reduced_b_width = b_width; + return b; + } else { + reduced_b_width = new_width; + T lower_b = factory.slice(b, b_width, 0, new_width); + T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); + return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); + } + } +public: + T reduce_or(T a, int width) { + if (width == 1) + return a; + return factory.reduce_or(a, width); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + if(in_width == out_width) + return a; + if(in_width > out_width) + return factory.slice(a, in_width, 0, out_width); + return factory.extend(a, in_width, out_width, is_signed); + } + T logical_shift_left(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width); + } + T logical_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width); + } + T arithmetic_shift_right(T a, T b, int y_width, int b_width) { + int reduced_b_width; + T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); + return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width); + } + CellSimplifier(Factory &f) : factory(f) {} + T handle(IdString cellType, dict parameters, dict inputs) + { + int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); + int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); + int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int(); + bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool(); + bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); + if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){ + bool is_signed = a_signed && b_signed; + T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); + if(cellType == ID($add)) + return factory.add(a, b, y_width); + else if(cellType == ID($sub)) + return factory.sub(a, b, y_width); + else if(cellType == ID($and)) + return factory.bitwise_and(a, b, y_width); + else if(cellType == ID($or)) + return factory.bitwise_or(a, b, y_width); + else if(cellType == ID($xor)) + return factory.bitwise_xor(a, b, y_width); + else if(cellType == ID($xnor)) + return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width); + else + log_abort(); + }else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){ + bool is_signed = a_signed && b_signed; + int width = max(a_width, b_width); + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + if(cellType.in({ID($eq), ID($eqx)})) + return extend(factory.eq(a, b, width), 1, y_width, false); + if(cellType.in({ID($ne), ID($nex)})) + return extend(factory.ne(a, b, width), 1, y_width, false); + else if(cellType == ID($lt)) + return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false); + else if(cellType == ID($le)) + return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false); + else if(cellType == ID($gt)) + return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false); + else if(cellType == ID($ge)) + return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false); + else + log_abort(); + }else if(cellType.in({ID($logic_or), ID($logic_and)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T b = reduce_or(inputs.at(ID(B)), b_width); + T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1); + return extend(y, 1, y_width, false); + }else if(cellType == ID($not)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.bitwise_not(a, y_width); + }else if(cellType == ID($pos)){ + return extend(inputs.at(ID(A)), a_width, y_width, a_signed); + }else if(cellType == ID($neg)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.neg(a, y_width); + }else if(cellType == ID($logic_not)){ + T a = reduce_or(inputs.at(ID(A)), a_width); + T y = factory.bitwise_not(a, 1); + return extend(y, 1, y_width, false); + }else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){ + T a = reduce_or(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType == ID($reduce_and)){ + T a = factory.reduce_and(inputs.at(ID(A)), a_width); + return extend(a, 1, y_width, false); + }else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){ + T a = factory.reduce_xor(inputs.at(ID(A)), a_width); + T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a; + return extend(y, 1, y_width, false); + }else if(cellType == ID($shl) || cellType == ID($sshl)){ + T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); + T b = inputs.at(ID(B)); + return logical_shift_left(a, b, y_width, b_width); + }else if(cellType == ID($shr) || cellType == ID($sshr)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, a_signed); + T b = inputs.at(ID(B)); + T y = a_signed && cellType == ID($sshr) ? + arithmetic_shift_right(a, b, width, b_width) : + logical_shift_right(a, b, width, b_width); + return extend(y, width, y_width, a_signed); + }else if(cellType == ID($shiftx) || cellType == ID($shift)){ + int width = max(a_width, y_width); + T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed); + T b = inputs.at(ID(B)); + T shr = logical_shift_right(a, b, width, b_width); + if(b_signed) { + T sign_b = factory.slice(b, b_width, b_width - 1, 1); + T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width); + T y = factory.mux(shr, shl, sign_b, width); + return extend(y, width, y_width, false); + } else { + return extend(shr, width, y_width, false); + } + }else if(cellType == ID($mux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width); + }else if(cellType == ID($pmux)){ + int width = parameters.at(ID(WIDTH)).as_int(); + int s_width = parameters.at(ID(S_WIDTH)).as_int(); + return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width); + }else if(cellType == ID($concat)){ + T a = inputs.at(ID(A)); + T b = inputs.at(ID(B)); + return factory.concat(a, a_width, b, b_width); + }else if(cellType == ID($slice)){ + int offset = parameters.at(ID(OFFSET)).as_int(); + T a = inputs.at(ID(A)); + return factory.slice(a, a_width, offset, y_width); + }else{ + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + } + } +}; + +template +class ComputeGraphConstruction { + std::deque queue; + dict graph_nodes; + idict cells; + DriverMap driver_map; + Factory& factory; + CellSimplifier simplifier; + + T enqueue(DriveSpec const &spec) + { + auto it = graph_nodes.find(spec); + if(it == graph_nodes.end()){ + auto node = factory.create_pending(spec.size()); + graph_nodes.insert({spec, node}); + queue.emplace_back(spec); + return node; + }else + return it->second; + } +public: + ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {} + void add_module(Module *module) + { + driver_map.add(module); + for (auto cell : module->cells()) { + if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + enqueue(DriveBitMarker(cells(cell), 0)); + } + for (auto wire : module->wires()) { + if (wire->port_output) { + T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + factory.declare_output(node, wire->name); + } + } + } + void process_queue() + { + for (; !queue.empty(); queue.pop_front()) { + DriveSpec spec = queue.front(); + T pending = graph_nodes.at(spec); + + if (spec.chunks().size() > 1) { + auto chunks = spec.chunks(); + T node = enqueue(chunks[0]); + int width = chunks[0].size(); + for(size_t i = 1; i < chunks.size(); i++) { + node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size()); + width += chunks[i].size(); + } + factory.update_pending(pending, node); + } else if (spec.chunks().size() == 1) { + DriveChunk chunk = spec.chunks()[0]; + if (chunk.is_wire()) { + DriveChunkWire wire_chunk = chunk.wire(); + if (wire_chunk.is_whole()) { + if (wire_chunk.wire->port_input) { + T node = factory.input(wire_chunk.wire->name, wire_chunk.width); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } else { + DriveSpec driver = driver_map(DriveSpec(wire_chunk)); + T node = enqueue(driver); + factory.suggest_name(node, wire_chunk.wire->name); + factory.update_pending(pending, node); + } + } else { + DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); + T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_port()) { + DriveChunkPort port_chunk = chunk.port(); + if (port_chunk.is_whole()) { + if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { + if (port_chunk.cell->type.in(ID($dff), ID($ff))) + { + Cell *cell = port_chunk.cell; + T node = factory.state(cell->name, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name); + factory.update_pending(pending, node); + for (auto const &conn : cell->connections()) { + if (driver_map.celltypes.cell_input(cell->type, conn.first)) { + T node = enqueue(DriveChunkPort(cell, conn)); + factory.declare_state(node, cell->name); + } + } + } + else + { + T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); + factory.suggest_name(cell, port_chunk.cell->name); + T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); + factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str()); + factory.update_pending(pending, node); + } + } else { + DriveSpec driver = driver_map(DriveSpec(port_chunk)); + factory.update_pending(pending, enqueue(driver)); + } + } else { + DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); + T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width); + factory.update_pending(pending, node); + } + } else if (chunk.is_constant()) { + T node = factory.constant(chunk.constant()); + factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string()); + factory.update_pending(pending, node); + } else if (chunk.is_multiple()) { + vector args; + for (auto const &driver : chunk.multiple().multiple()) + args.push_back(enqueue(driver)); + T node = factory.multiple(args, chunk.size()); + factory.update_pending(pending, node); + } else if (chunk.is_marker()) { + Cell *cell = cells[chunk.marker().marker]; + dict connections; + for(auto const &conn : cell->connections()) { + if(driver_map.celltypes.cell_input(cell->type, conn.first)) + connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); + } + T node = simplifier.handle(cell->type, cell->parameters, connections); + factory.update_pending(pending, node); + } else if (chunk.is_none()) { + T node = factory.undriven(chunk.size()); + factory.update_pending(pending, node); + } else { + log_error("unhandled drivespec: %s\n", log_signal(chunk)); + log_abort(); + } + } else { + log_abort(); + } + } + } +}; + +YOSYS_NAMESPACE_END + +#endif From 7611dda2ebfbbc29623e13bc8850910d21398a98 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 23 May 2024 11:40:41 +0100 Subject: [PATCH 093/342] add initial version of functional smtlib backend --- backends/functional/Makefile.inc | 1 + backends/functional/cxx.cc | 4 +- backends/functional/smtlib.cc | 541 +++++++++++++++++++++++++++++++ kernel/graphtools.h | 6 +- 4 files changed, 547 insertions(+), 5 deletions(-) create mode 100644 backends/functional/smtlib.cc diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index 011e66264..c712d2aef 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1 +1,2 @@ OBJS += backends/functional/cxx.o +OBJS += backends/functional/smtlib.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 46ce88bd6..c0444e7fe 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -214,10 +214,10 @@ public: pending.set_function(CxxFunction(ID($$buf), pending.function().width)); pending.append_arg(node); } - void declare_output(T node, IdString name) { + void declare_output(T node, IdString name, int) { node.assign_key(name); } - void declare_state(T node, IdString name) { + void declare_state(T node, IdString name, int) { node.assign_key(name); } void suggest_name(T node, IdString name) { diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc new file mode 100644 index 000000000..f6af79791 --- /dev/null +++ b/backends/functional/smtlib.cc @@ -0,0 +1,541 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/drivertools.h" +#include "kernel/topo_scc.h" +#include "kernel/functional.h" +#include "kernel/graphtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SmtlibScope { + pool used_names; + dict name_map; + + SmtlibScope() { + /*for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p);*/ + } + void reserve(std::string name) { + used_names.insert(name); + } + std::string insert(IdString id) { + std::string str = RTLIL::unescape_id(id); + for(size_t i = 0; i < str.size(); i++) + if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i])))) + str[i] = '_'; + if(used_names.count(str) == 0){ + used_names.insert(str); + name_map.insert({id, str}); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if (used_names.count(suffixed) == 0) { + used_names.insert(suffixed); + if(name_map.count(id) == 0) + name_map.insert({id, suffixed}); + return suffixed; + } + } + } + std::string operator[](IdString id) { + if(name_map.count(id) > 0) + return name_map[id]; + else + return insert(id); + } +}; + +struct SmtlibWriter { + std::ostream &f; + SmtlibWriter(std::ostream &out) : f(out) {} + void printf(const char *fmt, ...) + { + va_list va; + va_start(va, fmt); + f << vstringf(fmt, va); + va_end(va); + } + template + SmtlibWriter & operator <<(T &&arg) { + f << std::forward(arg); + return *this; + } +}; + +struct Arg { + int n; + explicit Arg(int n_) : n(n_) {} + bool operator ==(Arg const &other) const { return n == other.n; } +}; + +class SExpr { + enum class Type { + None, + List, + Atom, + Arg, + }; + Type type = Type::None; + union { + std::string atom_; + vector list_; + Arg arg_; + }; + void set_none() { + switch(type) { + case Type::None: break; + case Type::Atom: atom_.~basic_string(); break; + case Type::List: list_.~vector(); break; + case Type::Arg: arg_.~Arg(); break; + } + type = Type::None; + } +public: + SExpr() {} + SExpr(const char *atom) : type(Type::Atom), atom_(atom) {} + SExpr(std::string atom) : type(Type::Atom), atom_(atom) {} + SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {} + SExpr(RTLIL::Const const & n) : type(Type::Atom) { + new(&atom_) std::string("#b"); + atom_.reserve(n.size() + 2); + for (size_t i = n.size(); i > 0; i--) + if(n[i-1] == State::S1) + atom_ += "1"; + else + atom_ += "0"; + } + SExpr(vector &&list) : type(Type::List), list_(list) {} + SExpr(std::initializer_list list) : type(Type::List), list_(list) {} + SExpr(Arg arg) : type(Type::Arg), arg_(arg) {} + SExpr(SExpr const &other) { *this = other; } + SExpr(SExpr &&other) { *this = std::move(other); } + SExpr &operator =(SExpr const &other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(other.atom_); break; + case Type::List: new(&list_) vector(other.list_); break; + case Type::Arg: new(&arg_) Arg(other.arg_); break; + } + type = other.type; + return *this; + } + SExpr &operator =(SExpr &&other) { + set_none(); + switch(other.type) { + case Type::None: break; + case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break; + case Type::List: new(&list_) vector(std::move(other.list_)); break; + case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break; + } + type = other.type; + return *this; + } + ~SExpr() { set_none(); } + bool operator==(SExpr const &other) const { + if(type != other.type) return false; + switch(type) { + case Type::None: return true; + case Type::Atom: return atom_ == other.atom_; + case Type::List: return list_ == other.list_; + case Type::Arg: return arg_ == other.arg_; + } + } + bool is_none() const { return type == Type::None; } + bool is_atom() const { return type == Type::Atom; } + bool is_list() const { return type == Type::List; } + bool is_arg() const { return type == Type::Arg; } + std::string const &atom() const { log_assert(is_atom()); return atom_; } + std::vector const &list() const { log_assert(is_list()); return list_; } + Arg const &arg() const { log_assert(is_arg()); return arg_; } + unsigned int hash() const { + unsigned int inner; + switch(type) { + case Type::None: inner = 0; break; + case Type::Atom: inner = mkhash(atom_); break; + case Type::List: inner = mkhash(list_); break; + case Type::Arg: inner = arg_.n; break; + } + return mkhash((unsigned int) type, inner); + } + SExpr subst_args(std::vector const & args) const { + switch(type) { + case Type::None: + case Type::Atom: + return *this; + case Type::List: { + vector ret; + for(auto & a : list_) + ret.emplace_back(a.subst_args(args)); + return SExpr(std::move(ret)); + } + case Type::Arg: + if(arg_.n >= 1 && (size_t)arg_.n <= args.size()) + return args[arg_.n - 1]; + else + return *this; + } + } +}; + +std::ostream& operator << (std::ostream &os, SExpr const &s) { + if(s.is_atom()) + os << s.atom(); + else if(s.is_list()){ + os << "("; + bool first = true; + for(auto &el: s.list()) { + if(!first) os << " "; + else first = false; + os << el; + } + os << ")"; + }else if(s.is_arg()) + os << "#" << s.arg().n; + else if(s.is_none()) + os << ""; + else + os << "???"; + return os; +} + +struct SmtlibStruct { + SmtlibScope &scope; + std::string name; + idict members; + vector widths; + vector accessors; + SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) { + } + std::string insert(IdString field, int width) { + if(members.at(field, -1) == -1){ + members(field); + scope.insert(field); + widths.push_back(width); + accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field))); + } + return scope[field]; + } + void print(SmtlibWriter &f) { + f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str()); + for (size_t i = 0; i < members.size(); i++) + f.printf(" (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]); + f.printf(")))\n"); + } + void print_value(SmtlibWriter &f, dict values, int indentation) { + std::string spaces(indentation, ' '); + f << spaces << "(" << name << "\n"; + for (size_t i = 0; i < members.size(); i++) + f << spaces << " " << values[members[i]] << " ; " << RTLIL::unescape_id(members[i]) << "\n"; + f << spaces << ")\n"; + } + SExpr access(SExpr record, IdString member) { + int i = members.at(member); + return SExpr{accessors[i], record}; + } + std::string operator[](IdString field) { + return scope[field]; + } +}; + +struct Node { + SExpr expr; + int width; + + Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {} + + bool operator==(Node const &other) const { + return expr == other.expr && width == other.width; + } + + unsigned int hash() const { + return mkhash(expr.hash(), width); + } +}; + +typedef ComputeGraph SmtlibComputeGraph; + +struct SmtlibModule { + std::string name; + SmtlibScope global_scope; + SmtlibStruct input_struct; + SmtlibStruct output_struct; + SmtlibStruct state_struct; + SmtlibComputeGraph compute_graph; + + SmtlibModule(std::string const &name) : + name(name), + input_struct(name + "_inputs", global_scope), + output_struct(name + "_outputs", global_scope), + state_struct(name + "_state", global_scope) + { } + void calculate_compute_graph(RTLIL::Module *module); + void write(std::ostream &stream); +}; + +class SmtlibComputeGraphFactory { + SmtlibModule &module; + SmtlibComputeGraph &graph; + using T = SmtlibComputeGraph::Ref; + static bool is_single_output(IdString type) + { + auto it = yosys_celltypes.cell_types.find(type); + return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; + } + T node(SExpr &&expr, int width, std::initializer_list args) { + return graph.add(Node(std::move(expr), width), 0, args); + } + T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) { + int width = max(y_width, b_width); + T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a; + T b_ = b_width < width ? extend(b, b_width, width, false) : b; + T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_}); + if(y_width < width) + return slice(y_, width, 0, y_width); + else + return y_; + } + SExpr from_bool(SExpr &&arg) { + return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)}; + } + SExpr to_bool(SExpr &&arg) { + return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)}; + } + SExpr extract(SExpr &&arg, int offset, int out_width) { + return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; + } +public: + SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {} + T slice(T a, int in_width, int offset, int out_width) { + assert(offset + out_width <= in_width); + return node(extract(Arg(1), offset, out_width), out_width, {a}); + } + T extend(T a, int in_width, int out_width, bool is_signed) { + assert(in_width < out_width); + if(is_signed) + return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + else + return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a}); + } + T concat(T a, int a_width, T b, int b_width) { + return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b}); + } + T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); } + T sub(T a, T b, int width) { return node(SExpr {"bvsub", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_and(T a, T b, int width) { return node(SExpr {"bvand", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_or(T a, T b, int width) { return node(SExpr {"bvor", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_xor(T a, T b, int width) { return node(SExpr {"bvxor", Arg(1), Arg(2)}, width, {a, b}); } + T bitwise_not(T a, int width) { return node(SExpr {"bvnot", Arg(1)}, width, {a}); } + T neg(T a, int width) { return node(SExpr {"bvneg", Arg(1)}, width, {a}); } + T mux(T a, T b, T s, int width) { return node(SExpr {"ite", to_bool(Arg(1)), Arg(2), Arg(3)}, width, {s, a, b}); } + T pmux(T a, T b, T s, int width, int s_width) { + T rv = a; + for(int i = 0; i < s_width; i++) + rv = node(SExpr {"ite", to_bool(extract(Arg(1), i, 1)), extract(Arg(2), width * i, width), Arg(3)}, width, {s, b, rv}); + return rv; + } + T reduce_and(T a, int width) { return node(from_bool(SExpr {"=", Arg(1), RTLIL::Const(State::S1, width)}), 1, {a}); } + T reduce_or(T a, int width) { return node(from_bool(SExpr {"distinct", Arg(1), RTLIL::Const(State::S0, width)}), 1, {a}); } + T reduce_xor(T a, int) { return node(SExpr {"reduce_xor", Arg(1)}, 1, {a}); } + T eq(T a, T b, int) { return node(from_bool(SExpr {"=", Arg(1), Arg(2)}), 1, {a, b}); } + T ne(T a, T b, int) { return node(from_bool(SExpr {"distinct", Arg(1), Arg(2)}), 1, {a, b}); } + T gt(T a, T b, int) { return node(from_bool(SExpr {"bvsgt", Arg(1), Arg(2)}), 1, {a, b}); } + T ge(T a, T b, int) { return node(from_bool(SExpr {"bvsge", Arg(1), Arg(2)}), 1, {a, b}); } + T ugt(T a, T b, int) { return node(from_bool(SExpr {"bvugt", Arg(1), Arg(2)}), 1, {a, b}); } + T uge(T a, T b, int) { return node(from_bool(SExpr {"bvuge", Arg(1), Arg(2)}), 1, {a, b}); } + T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); } + T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } + T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } + + T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } + T input(IdString name, int width) { + module.input_struct.insert(name, width); + return node(module.input_struct.access("inputs", name), width, {}); + } + T state(IdString name, int width) { + module.state_struct.insert(name, width); + return node(module.state_struct.access("current_state", name), width, {}); + } + T cell_output(T cell, IdString type, IdString name, int width) { + if (is_single_output(type)) + return cell; + else + return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell}); + } + T multiple(vector args, int width) { + vector expr; + expr.reserve(args.size() + 1); + expr.push_back("multiple"); + for(size_t i = 1; i <= args.size(); i++) + expr.push_back(Arg(i)); + return graph.add(Node(SExpr(std::move(expr)), width), 0, args); + } + T undriven(int width) { + return constant(RTLIL::Const(State::S0, width)); + //return node(SExpr {"undriven"}, width, {}); + } + T create_pending(int width) { + return node(SExpr(), width, {}); + } + void update_pending(T pending, T node) { + assert(pending.function().expr.is_none()); + pending.set_function(Node(Arg(1), pending.function().width)); + pending.append_arg(node); + } + void declare_output(T node, IdString name, int width) { + module.output_struct.insert(name, width); + node.assign_key(name); + } + void declare_state(T node, IdString name, int width) { + module.state_struct.insert(name, width); + node.assign_key(name); + } + void suggest_name(T node, IdString name) { + node.sparse_attr() = name; + } +}; + +void SmtlibModule::calculate_compute_graph(RTLIL::Module *module) +{ + SmtlibComputeGraphFactory factory(*this); + ComputeGraphConstruction construction(factory); + construction.add_module(module); + construction.process_queue(); + + // Perform topo sort and detect SCCs + SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph); + + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + compute_graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); + + // Forward $$buf + std::vector alias; + perm.clear(); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto node = compute_graph[i]; + if (node.function().expr == Arg(1) && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = compute_graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()) + target_node.sparse_attr() = node.sparse_attr(); + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + compute_graph.permute(perm, alias); +} + +void SmtlibModule::write(std::ostream &stream) +{ + SmtlibWriter f(stream); + + idict node_names; + SmtlibScope locals; + int paren_count = 0; + + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + + f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n"; + f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n", + name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); + + for (int i = 0; i < compute_graph.size(); ++i) + { + auto ref = compute_graph[i]; + std::string name; + if(ref.has_sparse_attr()) + name = locals.insert(ref.sparse_attr()); + else + name = locals.insert("\\n" + std::to_string(i)); + node_names(name); + vector args; + args.reserve(ref.size()); + for (int i = 0, end = ref.size(); i != end; ++i) + args.push_back(node_names[ref.arg(i).index()]); + f << " (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n"; + paren_count++; + } + dict outputs; + for(auto &a: compute_graph.keys()) + outputs.insert({a.first, node_names[a.second]}); + f.printf(" (pair \n"); + output_struct.print_value(f, outputs, 6); + state_struct.print_value(f, outputs, 6); + f.printf(" )\n"); + while(paren_count > 0){ + int n = min(paren_count, 80); + f << " " << std::string(n, ')') << "\n"; + paren_count -= n; + } + f.printf(")\n"); +} + +struct FunctionalSmtlibBackend : public Backend +{ + FunctionalSmtlibBackend() : Backend("functional_smtlib", "convert design to SMTLIB using the functional backend") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional SMTLIB backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + SmtlibModule smt(RTLIL::unescape_id(module->name)); + smt.calculate_compute_graph(module); + smt.write(*f); + } + } +} FunctionalSmtlibBackend; + +PRIVATE_NAMESPACE_END diff --git a/kernel/graphtools.h b/kernel/graphtools.h index 1a59ef1b5..adf4764c2 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -32,7 +32,7 @@ class CellSimplifier { Factory &factory; T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { log_assert(y_width > 0); - int new_width = sizeof(int) * 8 - __builtin_clz(y_width); + int new_width = ceil_log2(y_width + 1); if (b_width <= new_width) { reduced_b_width = b_width; return b; @@ -221,7 +221,7 @@ public: for (auto wire : module->wires()) { if (wire->port_output) { T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); - factory.declare_output(node, wire->name); + factory.declare_output(node, wire->name, wire->width); } } } @@ -273,7 +273,7 @@ public: for (auto const &conn : cell->connections()) { if (driver_map.celltypes.cell_input(cell->type, conn.first)) { T node = enqueue(DriveChunkPort(cell, conn)); - factory.declare_state(node, cell->name); + factory.declare_state(node, cell->name, port_chunk.width); } } } From 720429b1fd9eef2f87ec4b2d623964ca5b066b0c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 12 Jun 2024 08:32:24 +0200 Subject: [PATCH 094/342] Add test_cell tests for C++ functional backend --- backends/functional/cxx.cc | 93 +++++++++---- backends/functional/cxx_runtime/sim.h | 1 + backends/functional/smtlib.cc | 1 + tests/functional/.gitignore | 4 + .../single_cells/rtlil/test_cell_add_00000.il | 17 +++ .../single_cells/rtlil/test_cell_alu_00000.il | 25 ++++ .../single_cells/rtlil/test_cell_and_00000.il | 17 +++ .../rtlil/test_cell_bmux_00000.il | 14 ++ .../rtlil/test_cell_demux_00000.il | 14 ++ .../single_cells/rtlil/test_cell_div_00000.il | 17 +++ .../rtlil/test_cell_divfloor_00000.il | 17 +++ .../single_cells/rtlil/test_cell_eq_00000.il | 17 +++ .../single_cells/rtlil/test_cell_fa_00000.il | 17 +++ .../single_cells/rtlil/test_cell_ge_00000.il | 17 +++ .../single_cells/rtlil/test_cell_gt_00000.il | 17 +++ .../single_cells/rtlil/test_cell_lcu_00000.il | 15 +++ .../single_cells/rtlil/test_cell_le_00000.il | 17 +++ .../rtlil/test_cell_logic_and_00000.il | 17 +++ .../rtlil/test_cell_logic_not_00000.il | 13 ++ .../rtlil/test_cell_logic_or_00000.il | 17 +++ .../single_cells/rtlil/test_cell_lt_00000.il | 17 +++ .../single_cells/rtlil/test_cell_lut_00000.il | 12 ++ .../rtlil/test_cell_macc_00000.il | 17 +++ .../single_cells/rtlil/test_cell_mod_00000.il | 17 +++ .../rtlil/test_cell_modfloor_00000.il | 17 +++ .../single_cells/rtlil/test_cell_mul_00000.il | 17 +++ .../single_cells/rtlil/test_cell_mux_00000.il | 15 +++ .../single_cells/rtlil/test_cell_ne_00000.il | 17 +++ .../single_cells/rtlil/test_cell_neg_00000.il | 13 ++ .../single_cells/rtlil/test_cell_not_00000.il | 13 ++ .../single_cells/rtlil/test_cell_or_00000.il | 17 +++ .../single_cells/rtlil/test_cell_pos_00000.il | 13 ++ .../rtlil/test_cell_reduce_and_00000.il | 13 ++ .../rtlil/test_cell_reduce_bool_00000.il | 13 ++ .../rtlil/test_cell_reduce_or_00000.il | 13 ++ .../rtlil/test_cell_reduce_xnor_00000.il | 13 ++ .../rtlil/test_cell_reduce_xor_00000.il | 13 ++ .../rtlil/test_cell_shift_00000.il | 17 +++ .../rtlil/test_cell_shiftx_00000.il | 17 +++ .../single_cells/rtlil/test_cell_shl_00000.il | 17 +++ .../single_cells/rtlil/test_cell_shr_00000.il | 17 +++ .../single_cells/rtlil/test_cell_sop_00000.il | 13 ++ .../rtlil/test_cell_sshl_00000.il | 17 +++ .../rtlil/test_cell_sshr_00000.il | 17 +++ .../single_cells/rtlil/test_cell_sub_00000.il | 17 +++ .../rtlil/test_cell_xnor_00000.il | 17 +++ .../single_cells/rtlil/test_cell_xor_00000.il | 17 +++ tests/functional/single_cells/run-test.sh | 83 ++++++++++++ tests/functional/single_cells/vcd_harness.cc | 123 ++++++++++++++++++ 49 files changed, 963 insertions(+), 26 deletions(-) create mode 100644 tests/functional/.gitignore create mode 100644 tests/functional/single_cells/rtlil/test_cell_add_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_alu_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_and_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_bmux_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_demux_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_div_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_eq_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_fa_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_ge_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_gt_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_lcu_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_le_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_lt_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_lut_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_macc_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_mod_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_mul_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_mux_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_ne_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_neg_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_not_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_or_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_shift_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_shl_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_shr_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_sop_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_sshl_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_sshr_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_sub_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_xnor_00000.il create mode 100644 tests/functional/single_cells/rtlil/test_cell_xor_00000.il create mode 100755 tests/functional/single_cells/run-test.sh create mode 100644 tests/functional/single_cells/vcd_harness.cc diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index c0444e7fe..03f33092c 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -17,6 +17,7 @@ * */ +#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" @@ -96,31 +97,70 @@ struct CxxWriter { }; struct CxxStruct { - std::string name; - dict types; - CxxScope scope; - CxxStruct(std::string name) : name(name) { - scope.reserve("out"); - scope.reserve("dump"); - } - void insert(IdString name, std::string type) { - scope.insert(name); - types.insert({name, type}); - } - void print(CxxWriter &f) { - f.printf("struct %s {\n", name.c_str()); - for (auto p : types) { - f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); - } - f.printf("\n\ttemplate void dump(T &out) {\n"); - for (auto p : types) { - f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); - } - f.printf("\t}\n};\n\n"); - } - std::string operator[](IdString field) { - return scope[field]; - } + std::string name; + dict types; + CxxScope scope; + bool generate_methods; + int count; + CxxStruct(std::string name, bool generate_methods = false, int count = 0) + : name(name), generate_methods(generate_methods), count(count) { + scope.reserve("out"); + scope.reserve("dump"); + } + void insert(IdString name, std::string type) { + scope.insert(name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.printf("struct %s {\n", name.c_str()); + for (auto p : types) { + f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + } + f.printf("\n\ttemplate void dump(T &out) const {\n"); + for (auto p : types) { + f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + } + f.printf("\t}\n\n"); + + if (generate_methods) { + // Add size method + f.printf("\tint size() const {\n"); + f.printf("\t\treturn %d;\n", count); + f.printf("\t}\n\n"); + + // Add get_input method + f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str()); + f.printf("\t\tswitch (index) {\n"); + int idx = 0; + for (auto p : types) { + f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str()); + idx++; + } + f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n"); + f.printf("\t\t}\n"); + f.printf("\t}\n"); + } + + f.printf("};\n\n"); + }; + std::string operator[](IdString field) { + return scope[field]; + } + private: + std::string generate_variant_types() const { + std::set unique_types; + for (const auto& p : types) { + unique_types.insert("std::reference_wrapper<" + p.second + ">"); + } + std::ostringstream oss; + for (auto it = unique_types.begin(); it != unique_types.end(); ++it) { + if (it != unique_types.begin()) { + oss << ", "; + } + oss << *it; + } + return oss.str(); + } }; struct CxxFunction { @@ -302,7 +342,8 @@ struct FunctionalCxxBackend : public Backend state[ref.function().parameters.begin()->first] = ref.function().width; } f.printf("#include \"sim.h\"\n"); - CxxStruct input_struct(name + "_Inputs"); + f.printf("#include \n"); + CxxStruct input_struct(name + "_Inputs", true, inputs.size()); for (auto const &input : inputs) input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); CxxStruct output_struct(name + "_Outputs"); diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 4e7d9b601..1e5a28263 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -20,6 +20,7 @@ #ifndef SIM_H #define SIM_H +#include #include template diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index f6af79791..cd11111b9 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -17,6 +17,7 @@ * */ +#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore new file mode 100644 index 000000000..543226b49 --- /dev/null +++ b/tests/functional/.gitignore @@ -0,0 +1,4 @@ +my_module_cxxrtl.cc +my_module_functional_cxx.cc +vcd_harness +*.vcd \ No newline at end of file diff --git a/tests/functional/single_cells/rtlil/test_cell_add_00000.il b/tests/functional/single_cells/rtlil/test_cell_add_00000.il new file mode 100644 index 000000000..531dabe41 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_add_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $add \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 1 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il new file mode 100644 index 000000000..ebdd3b734 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il @@ -0,0 +1,25 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 7 input 2 \B + wire input 3 \BI + wire input 4 \CI + wire width 6 output 5 \CO + wire width 6 output 6 \X + wire width 6 output 7 \Y + cell $alu \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \BI \BI + connect \CI \CI + connect \CO \CO + connect \X \X + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_and_00000.il new file mode 100644 index 000000000..2578f60b7 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_and_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 3 input 2 \B + wire width 2 output 3 \Y + cell $and \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 1 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il new file mode 100644 index 000000000..1b613bd69 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il @@ -0,0 +1,14 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire input 2 \S + wire width 4 output 3 \Y + cell $bmux \UUT + parameter \S_WIDTH 1 + parameter \WIDTH 4 + connect \A \A + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il new file mode 100644 index 000000000..dbe2dee62 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il @@ -0,0 +1,14 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 5 input 2 \S + wire width 192 output 3 \Y + cell $demux \UUT + parameter \S_WIDTH 5 + parameter \WIDTH 6 + connect \A \A + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_div_00000.il b/tests/functional/single_cells/rtlil/test_cell_div_00000.il new file mode 100644 index 000000000..6f278a7a0 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_div_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 6 input 2 \B + wire output 3 \Y + cell $div \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il new file mode 100644 index 000000000..67fce36b3 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $divfloor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il new file mode 100644 index 000000000..06fef02b5 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire input 2 \B + wire width 4 output 3 \Y + cell $eq \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il new file mode 100644 index 000000000..97f0eb029 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire input 2 \B + wire input 3 \C + wire output 4 \X + wire output 5 \Y + cell $fa \UUT + parameter \WIDTH 1 + connect \A \A + connect \B \B + connect \C \C + connect \X \X + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il new file mode 100644 index 000000000..0ac72e943 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 7 input 2 \B + wire width 6 output 3 \Y + cell $ge \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 1 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il new file mode 100644 index 000000000..d4498d36f --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 3 input 2 \B + wire width 4 output 3 \Y + cell $gt \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il new file mode 100644 index 000000000..e1bda0b43 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il @@ -0,0 +1,15 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \CI + wire width 2 output 2 \CO + wire width 2 input 3 \G + wire width 2 input 4 \P + cell $lcu \UUT + parameter \WIDTH 2 + connect \CI \CI + connect \CO \CO + connect \G \G + connect \P \P + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_le_00000.il b/tests/functional/single_cells/rtlil/test_cell_le_00000.il new file mode 100644 index 000000000..609d99ce8 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_le_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 4 input 2 \B + wire width 6 output 3 \Y + cell $le \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 5 + parameter \B_SIGNED 1 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il new file mode 100644 index 000000000..2eae6e3fc --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 7 input 2 \B + wire output 3 \Y + cell $logic_and \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il new file mode 100644 index 000000000..c7898491c --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 8 output 2 \Y + cell $logic_not \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il new file mode 100644 index 000000000..7a1ef6cbd --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 7 input 2 \B + wire width 2 output 3 \Y + cell $logic_or \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il new file mode 100644 index 000000000..fd3ee1f8b --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 5 input 2 \B + wire width 6 output 3 \Y + cell $lt \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il new file mode 100644 index 000000000..7c4882bb6 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il @@ -0,0 +1,12 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire output 2 \Y + cell $lut \UUT + parameter \LUT 4'1111 + parameter \WIDTH 2 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il new file mode 100644 index 000000000..66b51634e --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 0 input 2 \B + wire width 2 output 3 \Y + cell $macc \UUT + parameter \A_WIDTH 3 + parameter \B_WIDTH 0 + parameter \CONFIG 10'0110000010 + parameter \CONFIG_WIDTH 10 + parameter \Y_WIDTH 2 + connect \A \A + connect \B { } + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il new file mode 100644 index 000000000..a484918f0 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 8 input 2 \B + wire width 2 output 3 \Y + cell $mod \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il new file mode 100644 index 000000000..6cd00aeea --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 7 input 2 \B + wire width 4 output 3 \Y + cell $modfloor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il new file mode 100644 index 000000000..c77aaffb8 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 2 input 2 \B + wire width 5 output 3 \Y + cell $mul \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 5 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il new file mode 100644 index 000000000..3fc52ac77 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il @@ -0,0 +1,15 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 input 2 \B + wire input 3 \S + wire width 4 output 4 \Y + cell $mux \UUT + parameter \WIDTH 4 + connect \A \A + connect \B \B + connect \S \S + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il new file mode 100644 index 000000000..47ba31397 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 5 input 2 \B + wire width 4 output 3 \Y + cell $ne \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il new file mode 100644 index 000000000..ee4273508 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 5 output 2 \Y + cell $neg \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 5 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_not_00000.il new file mode 100644 index 000000000..9281ded0d --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_not_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 7 output 2 \Y + cell $not \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_or_00000.il new file mode 100644 index 000000000..100ea42cd --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_or_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire input 2 \B + wire width 2 output 3 \Y + cell $or \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il new file mode 100644 index 000000000..182f0acd3 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 3 output 2 \Y + cell $pos \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il new file mode 100644 index 000000000..079ed33ad --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 5 output 2 \Y + cell $reduce_and \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il new file mode 100644 index 000000000..a417179c8 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 2 output 2 \Y + cell $reduce_bool \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il new file mode 100644 index 000000000..881c6dfe3 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 2 input 1 \A + wire width 7 output 2 \Y + cell $reduce_or \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 7 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il new file mode 100644 index 000000000..c06562729 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire width 4 output 2 \Y + cell $reduce_xnor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il new file mode 100644 index 000000000..428d2ea87 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 4 input 1 \A + wire output 2 \Y + cell $reduce_xor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il new file mode 100644 index 000000000..f82a2a79d --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 6 input 2 \B + wire width 4 output 3 \Y + cell $shift \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 1 + parameter \B_SIGNED 1 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il new file mode 100644 index 000000000..b89ac5bef --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire input 1 \A + wire width 5 input 2 \B + wire width 3 output 3 \Y + cell $shiftx \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 3 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il new file mode 100644 index 000000000..1cfee2a52 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire width 2 input 2 \B + wire width 3 output 3 \Y + cell $shl \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il new file mode 100644 index 000000000..35dd37909 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 6 input 2 \B + wire width 4 output 3 \Y + cell $shr \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 4 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il new file mode 100644 index 000000000..df0f8f20a --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 8 input 1 \A + wire output 2 \Y + cell $sop \UUT + parameter \DEPTH 8 + parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110 + parameter \WIDTH 8 + connect \A \A + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il new file mode 100644 index 000000000..798288754 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 5 input 1 \A + wire width 3 input 2 \B + wire width 6 output 3 \Y + cell $sshl \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il new file mode 100644 index 000000000..3f59a693f --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 3 input 1 \A + wire width 2 input 2 \B + wire width 2 output 3 \Y + cell $sshr \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il new file mode 100644 index 000000000..cb9ec2f79 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 6 input 2 \B + wire width 6 output 3 \Y + cell $sub \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il new file mode 100644 index 000000000..85bd7d239 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 7 input 1 \A + wire width 8 input 2 \B + wire width 7 output 3 \Y + cell $xnor \UUT + parameter \A_SIGNED 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 1 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 7 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il new file mode 100644 index 000000000..2359698b5 --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il @@ -0,0 +1,17 @@ +# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 2 input 2 \B + wire width 8 output 3 \Y + cell $xor \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \A + connect \B \B + connect \Y \Y + end +end diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh new file mode 100755 index 000000000..67cdf4a11 --- /dev/null +++ b/tests/functional/single_cells/run-test.sh @@ -0,0 +1,83 @@ +#!/bin/bash + +# Initialize an array to store the names of failing RTLIL files and their failure types +declare -A failing_files +# Initialize an array to store the names of successful RTLIL files +declare -A successful_files + +# Function to run the test on a given RTLIL file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local rtlil_file=$1 + + # Extract the base name without extension + local base_name=$(basename "$rtlil_file" .v) + + # Run yosys to process each RTLIL file + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then + echo "Yosys processed $rtlil_file successfully." + + # Compile the generated C++ files with vcd_harness.cpp + if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then + echo "Compilation successful." + # Generate VCD files with base_name + if ./vcd_harness ${base_name}_functional_cxx.vcd; then + + # Run yosys to process each RTLIL file + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then + echo "Yosys sim $rtlil_file successfully." + successful_files["$rtlil_file"]="Success" + else + ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us" + echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" + failing_files["$rtlil_file"]="Yosys sim failure" + fi + + else + echo "Failed to generate VCD files for $rtlil_file." + failing_files["$rtlil_file"]="VCD generation failure" + fi + else + echo "Failed to compile harness for $rtlil_file." + failing_files["$rtlil_file"]="Compilation failure" + fi + else + echo "Yosys failed to process $rtlil_file." + failing_files["$rtlil_file"]="Yosys failure" + fi +} + +# Main function to run all tests +run_all_tests() { + # Loop through all RTLIL files in the rtlil directory + for rtlil_file in rtlil/*.il; do + run_test "$rtlil_file" + done + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + echo "The following files passed:" + for file in "${!successful_files[@]}"; do + echo "$file" + done + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"; do + echo "$file: ${failing_files[$file]}" + done + echo "The following files passed:" + for file in "${!successful_files[@]}"; do + echo "$file" + done + return 1 + fi +} + +# If the script is being sourced, do not execute the tests +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests +fi diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc new file mode 100644 index 000000000..10ab10e42 --- /dev/null +++ b/tests/functional/single_cells/vcd_harness.cc @@ -0,0 +1,123 @@ +#include +#include +#include +#include + +#include "my_module_functional_cxx.cc" + +struct DumpHeader { + std::ofstream &ofs; + DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + } +}; + +struct Dump { + std::ofstream &ofs; + Dump(std::ofstream &ofs) : ofs(ofs) {} + template + void operator()(const char *name, Signal value) { + // Bit + if (n == 1) { + ofs << (value[0] ? '1' : '0'); + ofs << name[0] << "\n"; + return; + } + // vector (multi-bit) signals + ofs << "b"; + for (size_t i = n; i-- > 0;) + ofs << (value[i] ? '1' : '0'); + ofs << " " << name[0] << "\n"; + } +}; + +// Function to set all values in a signal to false +template +void set_all_false(Signal& signal) { + std::fill(signal.begin(), signal.end(), false); +} + +template +void set_all_random(Signal& signal) { + std::random_device rd; // Random device for seeding + std::mt19937 gen(rd()); // Mersenne Twister engine + std::bernoulli_distribution dist(0.5); // 50-50 distribution + + for (auto& value : signal) { + value = dist(gen); // Set each value to a random boolean + } +} + +int main(int argc, char **argv) +{ + if (argc != 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } + + const std::string functional_vcd_filename = argv[1]; + + constexpr int steps = 10; + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + gold_Inputs inputs; + gold_Outputs outputs; + gold_State state; + gold_State next_state; + + std::ofstream vcd_file(functional_vcd_filename); + + vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + vcd_file << "$scope module gold $end\n"; + { + DumpHeader d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + vcd_file << "$enddefinitions $end\n$dumpvars\n"; + vcd_file << "#0\n"; + // Set all signals to false + for (int i = 0; i < inputs.size(); ++i) { + auto input_variant = inputs.get_input(i); + std::visit([](auto& signal_ref) { + set_all_false(signal_ref.get()); + }, input_variant); + } + + gold(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + for (int step = 0; step < steps; ++step) { + // Functional backend cxx + vcd_file << "#" << (step + 1) << "\n"; + // Set all signals to random + for (int i = 0; i < inputs.size(); ++i) { + auto input_variant = inputs.get_input(i); + std::visit([](auto& signal_ref) { + set_all_random(signal_ref.get()); + }, input_variant); + } + + gold(inputs, outputs, state, next_state); + { + Dump d(vcd_file); + inputs.dump(d); + outputs.dump(d); + state.dump(d); + } + + state = next_state; + } + + vcd_file.close(); + + return 0; +} From 76371d177fa759c000778a0969b2333fbc4dc594 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 12 Jun 2024 09:23:44 +0200 Subject: [PATCH 095/342] Change assert to log_assert --- backends/functional/cxx.cc | 9 ++++----- backends/functional/cxx_runtime/sim.h | 11 +++++------ backends/functional/smtlib.cc | 7 +++---- 3 files changed, 12 insertions(+), 15 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 03f33092c..b42e20ca7 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -17,7 +17,6 @@ * */ -#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" @@ -38,7 +37,7 @@ const char *reserved_keywords[] = { "int","long","mutable","namespace","new","noexcept","not","not_eq", "nullptr","operator","or","or_eq","private","protected","public", "reflexpr","register","reinterpret_cast","requires","return","short", - "signed","sizeof","static","static_assert","static_cast","struct", + "signed","sizeof","static","static_log_assert","static_cast","struct", "switch","synchronized","template","this","thread_local","throw", "true","try","typedef","typeid","typename","union","unsigned", "using","virtual","void","volatile","wchar_t","while","xor","xor_eq", @@ -193,11 +192,11 @@ class CxxComputeGraphFactory { public: CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} T slice(T a, int in_width, int offset, int out_width) { - assert(offset + out_width <= in_width); + log_assert(offset + out_width <= in_width); return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); } T extend(T a, int in_width, int out_width, bool is_signed) { - assert(in_width < out_width); + log_assert(in_width < out_width); if(is_signed) return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); else @@ -250,7 +249,7 @@ public: return graph.add(CxxFunction(ID($$pending), width), 0); } void update_pending(T pending, T node) { - assert(pending.function().name == ID($$pending)); + log_assert(pending.function().name == ID($$pending)); pending.set_function(CxxFunction(ID($$buf), pending.function().width)); pending.append_arg(node); } diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 1e5a28263..75d045ccf 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -20,7 +20,6 @@ #ifndef SIM_H #define SIM_H -#include #include template @@ -250,7 +249,7 @@ Signal $shl(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); + log_assert(!b[i]); size_t amount = as_int(b); Signal ret = $const(0); if(amount < n){ @@ -267,7 +266,7 @@ Signal $shr(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); + log_assert(!b[i]); size_t amount = as_int(b); Signal ret; for (size_t i = 0; i < n; i++) { @@ -284,7 +283,7 @@ Signal $asr(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); + log_assert(!b[i]); size_t amount = as_int(b); Signal ret; for (size_t i = 0; i < n; i++) { @@ -345,7 +344,7 @@ Signal concat(Signal const& a, Signal const& b) template Signal $zero_extend(Signal const& a) { - assert(n >= m); + log_assert(n >= m); Signal ret; std::copy(a.begin(), a.end(), ret.begin()); for(size_t i = m; i < n; i++) @@ -356,7 +355,7 @@ Signal $zero_extend(Signal const& a) template Signal $sign_extend(Signal const& a) { - assert(n >= m); + log_assert(n >= m); Signal ret; std::copy(a.begin(), a.end(), ret.begin()); for(size_t i = m; i < n; i++) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index cd11111b9..7a283cccf 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -17,7 +17,6 @@ * */ -#include #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" @@ -328,11 +327,11 @@ class SmtlibComputeGraphFactory { public: SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {} T slice(T a, int in_width, int offset, int out_width) { - assert(offset + out_width <= in_width); + log_assert(offset + out_width <= in_width); return node(extract(Arg(1), offset, out_width), out_width, {a}); } T extend(T a, int in_width, int out_width, bool is_signed) { - assert(in_width < out_width); + log_assert(in_width < out_width); if(is_signed) return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a}); else @@ -399,7 +398,7 @@ public: return node(SExpr(), width, {}); } void update_pending(T pending, T node) { - assert(pending.function().expr.is_none()); + log_assert(pending.function().expr.is_none()); pending.set_function(Node(Arg(1), pending.function().width)); pending.append_arg(node); } From 7b29d177ac511cd68a4c51001e6ad3522268b08e Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 12 Jun 2024 11:27:10 +0100 Subject: [PATCH 096/342] add support for memories to c++ and smtlib functional backends --- backends/functional/cxx.cc | 110 ++++++++++++++++++-------- backends/functional/cxx_runtime/sim.h | 19 +++++ backends/functional/smtlib.cc | 72 ++++++++++++++--- kernel/drivertools.h | 7 ++ kernel/graphtools.h | 68 ++++++++++++++-- 5 files changed, 226 insertions(+), 50 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index b42e20ca7..08d9ba791 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -83,6 +83,41 @@ struct CxxScope { } }; +struct CxxType { + bool _is_memory; + int _width; + int _addr_width; +public: + CxxType() : _is_memory(false), _width(0), _addr_width(0) { } + CxxType(int width) : _is_memory(false), _width(width), _addr_width(0) { } + CxxType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { } + static CxxType signal(int width) { return CxxType(width); } + static CxxType memory(int addr_width, int data_width) { return CxxType(addr_width, data_width); } + bool is_signal() const { return !_is_memory; } + bool is_memory() const { return _is_memory; } + int width() const { log_assert(is_signal()); return _width; } + int addr_width() const { log_assert(is_memory()); return _addr_width; } + int data_width() const { log_assert(is_memory()); return _width; } + std::string to_string() const { + if(_is_memory) { + return stringf("Memory<%d, %d>", addr_width(), data_width()); + } else { + return stringf("Signal<%d>", width()); + } + } + bool operator ==(CxxType const& other) const { + if(_is_memory != other._is_memory) return false; + if(_is_memory && _addr_width != other._addr_width) return false; + return _width == other._width; + } + unsigned int hash() const { + if(_is_memory) + return mkhash(1, mkhash(_width, _addr_width)); + else + return mkhash(0, _width); + } +}; + struct CxxWriter { std::ostream &f; CxxWriter(std::ostream &out) : f(out) {} @@ -97,7 +132,7 @@ struct CxxWriter { struct CxxStruct { std::string name; - dict types; + dict types; CxxScope scope; bool generate_methods; int count; @@ -106,14 +141,14 @@ struct CxxStruct { scope.reserve("out"); scope.reserve("dump"); } - void insert(IdString name, std::string type) { + void insert(IdString name, CxxType type) { scope.insert(name); types.insert({name, type}); } void print(CxxWriter &f) { f.printf("struct %s {\n", name.c_str()); for (auto p : types) { - f.printf("\t%s %s;\n", p.second.c_str(), scope[p.first].c_str()); + f.printf("\t%s %s;\n", p.second.to_string().c_str(), scope[p.first].c_str()); } f.printf("\n\ttemplate void dump(T &out) const {\n"); for (auto p : types) { @@ -149,7 +184,7 @@ struct CxxStruct { std::string generate_variant_types() const { std::set unique_types; for (const auto& p : types) { - unique_types.insert("std::reference_wrapper<" + p.second + ">"); + unique_types.insert("std::reference_wrapper<" + p.second.to_string() + ">"); } std::ostringstream oss; for (auto it = unique_types.begin(); it != unique_types.end(); ++it) { @@ -164,18 +199,18 @@ struct CxxStruct { struct CxxFunction { IdString name; - int width; + CxxType type; dict parameters; - CxxFunction(IdString name, int width) : name(name), width(width) {} - CxxFunction(IdString name, int width, dict parameters) : name(name), width(width), parameters(parameters) {} + CxxFunction(IdString name, CxxType type) : name(name), type(type) {} + CxxFunction(IdString name, CxxType type, dict parameters) : name(name), type(type), parameters(parameters) {} bool operator==(CxxFunction const &other) const { - return name == other.name && parameters == other.parameters && width == other.width; + return name == other.name && parameters == other.parameters && type == other.type; } unsigned int hash() const { - return mkhash(name.hash(), parameters.hash()); + return mkhash(name.hash(), mkhash(type.hash(), parameters.hash())); } }; @@ -232,6 +267,9 @@ public: } T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } + T state_memory(IdString name, int addr_width, int data_width) { + return graph.add(CxxFunction(ID($$state), CxxType::memory(addr_width, data_width), {{name, {}}}), 0); + } T cell_output(T cell, IdString type, IdString name, int width) { if (is_single_output(type)) return cell; @@ -245,12 +283,19 @@ public: return graph.add(CxxFunction(ID($$undriven), width), 0); } + T memory_read(T mem, T addr, int addr_width, int data_width) { + return graph.add(CxxFunction(ID($memory_read), data_width), 0, std::array{mem, addr}); + } + T memory_write(T mem, T addr, T data, int addr_width, int data_width) { + return graph.add(CxxFunction(ID($memory_write), CxxType::memory(addr_width, data_width)), 0, std::array{mem, addr, data}); + } + T create_pending(int width) { return graph.add(CxxFunction(ID($$pending), width), 0); } void update_pending(T pending, T node) { log_assert(pending.function().name == ID($$pending)); - pending.set_function(CxxFunction(ID($$buf), pending.function().width)); + pending.set_function(CxxFunction(ID($$buf), pending.function().type)); pending.append_arg(node); } void declare_output(T node, IdString name, int) { @@ -259,6 +304,9 @@ public: void declare_state(T node, IdString name, int) { node.assign_key(name); } + void declare_state_memory(T node, IdString name, int, int) { + node.assign_key(name); + } void suggest_name(T node, IdString name) { node.sparse_attr() = name; } @@ -312,8 +360,10 @@ struct FunctionalCxxBackend : public Backend { int target_index = alias[node.arg(0).index()]; auto target_node = compute_graph[perm[target_index]]; - if(!target_node.has_sparse_attr() && node.has_sparse_attr()) - target_node.sparse_attr() = node.sparse_attr(); + if(!target_node.has_sparse_attr() && node.has_sparse_attr()){ + IdString id = node.sparse_attr(); + target_node.sparse_attr() = id; + } alias.push_back(target_index); } else @@ -328,7 +378,7 @@ struct FunctionalCxxBackend : public Backend void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) { - dict inputs, state; + dict inputs, state; CxxWriter f(stream); // Dump the compute graph @@ -336,22 +386,22 @@ struct FunctionalCxxBackend : public Backend { auto ref = compute_graph[i]; if(ref.function().name == ID($$input)) - inputs[ref.function().parameters.begin()->first] = ref.function().width; + inputs[ref.function().parameters.begin()->first] = ref.function().type; if(ref.function().name == ID($$state)) - state[ref.function().parameters.begin()->first] = ref.function().width; + state[ref.function().parameters.begin()->first] = ref.function().type; } f.printf("#include \"sim.h\"\n"); f.printf("#include \n"); CxxStruct input_struct(name + "_Inputs", true, inputs.size()); for (auto const &input : inputs) - input_struct.insert(input.first, "Signal<" + std::to_string(input.second) + ">"); + input_struct.insert(input.first, input.second); CxxStruct output_struct(name + "_Outputs"); for (auto const &key : compute_graph.keys()) if(state.count(key.first) == 0) - output_struct.insert(key.first, "Signal<" + std::to_string(compute_graph[key.second].function().width) + ">"); + output_struct.insert(key.first, compute_graph[key.second].function().type); CxxStruct state_struct(name + "_State"); for (auto const &state_var : state) - state_struct.insert(state_var.first, "Signal<" + std::to_string(state_var.second) + ">"); + state_struct.insert(state_var.first, state_var.second); idict node_names; CxxScope locals; @@ -368,7 +418,7 @@ struct FunctionalCxxBackend : public Backend for (int i = 0; i < compute_graph.size(); ++i) { auto ref = compute_graph[i]; - int width = ref.function().width; + auto type = ref.function().type; std::string name; if(ref.has_sparse_attr()) name = locals.insert(ref.sparse_attr()); @@ -376,19 +426,19 @@ struct FunctionalCxxBackend : public Backend name = locals.insert("\\n" + std::to_string(i)); node_names(name); if(ref.function().name == ID($$input)) - f.printf("\tSignal<%d> %s = input.%s;\n", width, name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); + f.printf("\t%s %s = input.%s;\n", type.to_string().c_str(), name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); else if(ref.function().name == ID($$state)) - f.printf("\tSignal<%d> %s = current_state.%s;\n", width, name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); + f.printf("\t%s %s = current_state.%s;\n", type.to_string().c_str(), name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); else if(ref.function().name == ID($$buf)) - f.printf("\tSignal<%d> %s = %s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str()); + f.printf("\t%s %s = %s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str()); else if(ref.function().name == ID($$cell_output)) - f.printf("\tSignal<%d> %s = %s.%s;\n", width, name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); + f.printf("\t%s %s = %s.%s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); else if(ref.function().name == ID($$const)){ auto c = ref.function().parameters.begin()->second; if(c.size() <= 32){ - f.printf("\tSignal<%d> %s = $const<%d>(%#x);\n", width, name.c_str(), width, (uint32_t) c.as_int()); + f.printf("\t%s %s = $const<%d>(%#x);\n", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int()); }else{ - f.printf("\tSignal<%d> %s = $const<%d>({%#x", width, name.c_str(), width, (uint32_t) c.as_int()); + f.printf("\t%s %s = $const<%d>({%#x", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int()); while(c.size() > 32){ c = c.extract(32, c.size() - 32); f.printf(", %#x", c.as_int()); @@ -396,9 +446,9 @@ struct FunctionalCxxBackend : public Backend f.printf("});\n"); } }else if(ref.function().name == ID($$undriven)) - f.printf("\tSignal<%d> %s; //undriven\n", width, name.c_str()); + f.printf("\t%s %s; //undriven\n", type.to_string().c_str(), name.c_str()); else if(ref.function().name == ID($$slice)) - f.printf("\tSignal<%d> %s = slice<%d>(%s, %d);\n", width, name.c_str(), width, node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); + f.printf("\t%s %s = slice<%d>(%s, %d);\n", type.to_string().c_str(), name.c_str(), type.width(), node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); else if(ref.function().name == ID($$concat)){ f.printf("\tauto %s = concat(", name.c_str()); for (int i = 0, end = ref.size(); i != end; ++i){ @@ -409,11 +459,7 @@ struct FunctionalCxxBackend : public Backend f.printf(");\n"); }else{ f.printf("\t"); - if(ref.function().width > 0) - f.printf("Signal<%d>", ref.function().width); - else - f.printf("%s_Outputs", log_id(ref.function().name)); - f.printf(" %s = %s", name.c_str(), log_id(ref.function().name)); + f.printf("%s %s = %s", type.to_string().c_str(), name.c_str(), log_id(ref.function().name)); if(ref.function().parameters.count(ID(WIDTH))){ f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); } diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 75d045ccf..310927f5b 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -363,4 +363,23 @@ Signal $sign_extend(Signal const& a) return ret; } +template +struct Memory { + std::array, 1< contents; +}; + +template +Signal $memory_read(Memory memory, Signal addr) +{ + return memory.contents[as_int(addr)]; +} + +template +Memory $memory_write(Memory memory, Signal addr, Signal data) +{ + Memory ret = memory; + ret.contents[as_int(addr)] = data; + return ret; +} + #endif diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 7a283cccf..a90927ab6 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -219,19 +219,54 @@ std::ostream& operator << (std::ostream &os, SExpr const &s) { return os; } +struct SmtlibType { + bool _is_memory; + int _width; + int _addr_width; +public: + SmtlibType() : _is_memory(false), _width(0), _addr_width(0) { } + SmtlibType(int width) : _is_memory(false), _width(width), _addr_width(0) { } + SmtlibType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { } + static SmtlibType signal(int width) { return SmtlibType(width); } + static SmtlibType memory(int addr_width, int data_width) { return SmtlibType(addr_width, data_width); } + bool is_signal() const { return !_is_memory; } + bool is_memory() const { return _is_memory; } + int width() const { log_assert(is_signal()); return _width; } + int addr_width() const { log_assert(is_memory()); return _addr_width; } + int data_width() const { log_assert(is_memory()); return _width; } + SExpr to_sexpr() const { + if(_is_memory) { + return SExpr{ "Array", SExpr{ "_", "BitVec", addr_width() }, SExpr{ "_", "BitVec", data_width() }}; + } else { + return SExpr{ "_", "BitVec", width() }; + } + } + bool operator ==(SmtlibType const& other) const { + if(_is_memory != other._is_memory) return false; + if(_is_memory && _addr_width != other._addr_width) return false; + return _width == other._width; + } + unsigned int hash() const { + if(_is_memory) + return mkhash(1, mkhash(_width, _addr_width)); + else + return mkhash(0, _width); + } +}; + struct SmtlibStruct { SmtlibScope &scope; std::string name; idict members; - vector widths; + vector types; vector accessors; SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) { } - std::string insert(IdString field, int width) { + std::string insert(IdString field, SmtlibType type) { if(members.at(field, -1) == -1){ members(field); scope.insert(field); - widths.push_back(width); + types.push_back(type); accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field))); } return scope[field]; @@ -239,7 +274,7 @@ struct SmtlibStruct { void print(SmtlibWriter &f) { f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str()); for (size_t i = 0; i < members.size(); i++) - f.printf(" (%s (_ BitVec %d))\n", accessors[i].c_str(), widths[i]); + f << " " << SExpr{accessors[i], types[i].to_sexpr()} << "\n"; f.printf(")))\n"); } void print_value(SmtlibWriter &f, dict values, int indentation) { @@ -260,16 +295,16 @@ struct SmtlibStruct { struct Node { SExpr expr; - int width; + SmtlibType type; - Node(SExpr &&expr, int width) : expr(std::move(expr)), width(width) {} + Node(SExpr &&expr, SmtlibType type) : expr(std::move(expr)), type(type) {} bool operator==(Node const &other) const { - return expr == other.expr && width == other.width; + return expr == other.expr && type == other.type; } unsigned int hash() const { - return mkhash(expr.hash(), width); + return mkhash(expr.hash(), type.hash()); } }; @@ -302,8 +337,8 @@ class SmtlibComputeGraphFactory { auto it = yosys_celltypes.cell_types.find(type); return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; } - T node(SExpr &&expr, int width, std::initializer_list args) { - return graph.add(Node(std::move(expr), width), 0, args); + T node(SExpr &&expr, SmtlibType type, std::initializer_list args) { + return graph.add(Node(std::move(expr), type), 0, args); } T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) { int width = max(y_width, b_width); @@ -367,6 +402,13 @@ public: T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } + T memory_read(T mem, T addr, int addr_width, int data_width) { + return node(SExpr {"select", Arg(1), Arg(2)}, data_width, {mem, addr}); + } + T memory_write(T mem, T addr, T data, int addr_width, int data_width) { + return node(SExpr {"store", Arg(1), Arg(2), Arg(3)}, SmtlibType::memory(addr_width, data_width), {mem, addr, data}); + } + T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } T input(IdString name, int width) { module.input_struct.insert(name, width); @@ -376,6 +418,10 @@ public: module.state_struct.insert(name, width); return node(module.state_struct.access("current_state", name), width, {}); } + T state_memory(IdString name, int addr_width, int data_width) { + module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width)); + return node(module.state_struct.access("current_state", name), SmtlibType::memory(addr_width, data_width), {}); + } T cell_output(T cell, IdString type, IdString name, int width) { if (is_single_output(type)) return cell; @@ -399,7 +445,7 @@ public: } void update_pending(T pending, T node) { log_assert(pending.function().expr.is_none()); - pending.set_function(Node(Arg(1), pending.function().width)); + pending.set_function(Node(Arg(1), pending.function().type)); pending.append_arg(node); } void declare_output(T node, IdString name, int width) { @@ -410,6 +456,10 @@ public: module.state_struct.insert(name, width); node.assign_key(name); } + void declare_state_memory(T node, IdString name, int addr_width, int data_width) { + module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width)); + node.assign_key(name); + } void suggest_name(T node, IdString name) { node.sparse_attr() = name; } diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 1cb835df2..48c846b5f 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -1064,6 +1064,13 @@ public: append(bit); } + DriveSpec(SigSpec const &sig) + { + // TODO: converting one chunk at a time would be faster + for (auto const &bit : sig.bits()) + append(bit); + } + std::vector const &chunks() const { pack(); return chunks_; } std::vector const &bits() const { unpack(); return bits_; } diff --git a/kernel/graphtools.h b/kernel/graphtools.h index adf4764c2..98046c6be 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -23,6 +23,7 @@ #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/functional.h" +#include "kernel/mem.h" USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN @@ -71,6 +72,11 @@ public: T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width); } + T bitwise_mux(T a, T b, T s, int width) { + T aa = factory.bitwise_and(a, factory.bitwise_not(s, width), width); + T bb = factory.bitwise_and(b, s, width); + return factory.bitwise_or(aa, bb, width); + } CellSimplifier(Factory &f) : factory(f) {} T handle(IdString cellType, dict parameters, dict inputs) { @@ -104,7 +110,7 @@ public: T b = extend(inputs.at(ID(B)), b_width, width, is_signed); if(cellType.in({ID($eq), ID($eqx)})) return extend(factory.eq(a, b, width), 1, y_width, false); - if(cellType.in({ID($ne), ID($nex)})) + else if(cellType.in({ID($ne), ID($nex)})) return extend(factory.ne(a, b, width), 1, y_width, false); else if(cellType == ID($lt)) return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false); @@ -197,6 +203,8 @@ class ComputeGraphConstruction { DriverMap driver_map; Factory& factory; CellSimplifier simplifier; + vector memories_vector; + dict memories; T enqueue(DriveSpec const &spec) { @@ -224,6 +232,45 @@ public: factory.declare_output(node, wire->name, wire->width); } } + memories_vector = Mem::get_all_memories(module); + for (auto &mem : memories_vector) { + if (mem.cell != nullptr) + memories[mem.cell] = &mem; + } + } + T concatenate_read_results(Mem *mem, vector results) + { + if(results.size() == 0) + return factory.undriven(0); + T node = results[0]; + int size = results[0].size(); + for(size_t i = 1; i < results.size(); i++) { + node = factory.concat(node, size, results[i], results[i].size()); + size += results[i].size(); + } + return node; + } + T handle_memory(Mem *mem) + { + vector read_results; + int addr_width = ceil_log2(mem->size); + int data_width = mem->width; + T node = factory.state_memory(mem->cell->name, addr_width, data_width); + for (auto &rd : mem->rd_ports) { + log_assert(!rd.clk_enable); + T addr = enqueue(driver_map(DriveSpec(rd.addr))); + read_results.push_back(factory.memory_read(node, addr, addr_width, data_width)); + } + for (auto &wr : mem->wr_ports) { + T en = enqueue(driver_map(DriveSpec(wr.en))); + T addr = enqueue(driver_map(DriveSpec(wr.addr))); + T new_data = enqueue(driver_map(DriveSpec(wr.data))); + T old_data = factory.memory_read(node, addr, addr_width, data_width); + T wr_data = simplifier.bitwise_mux(old_data, new_data, en, data_width); + node = factory.memory_write(node, addr, wr_data, addr_width, data_width); + } + factory.declare_state_memory(node, mem->cell->name, addr_width, data_width); + return concatenate_read_results(mem, read_results); } void process_queue() { @@ -306,13 +353,20 @@ public: factory.update_pending(pending, node); } else if (chunk.is_marker()) { Cell *cell = cells[chunk.marker().marker]; - dict connections; - for(auto const &conn : cell->connections()) { - if(driver_map.celltypes.cell_input(cell->type, conn.first)) - connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); + if (cell->is_mem_cell()) { + Mem *mem = memories.at(cell, nullptr); + log_assert(mem != nullptr); + T node = handle_memory(mem); + factory.update_pending(pending, node); + } else { + dict connections; + for(auto const &conn : cell->connections()) { + if(driver_map.celltypes.cell_input(cell->type, conn.first)) + connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); + } + T node = simplifier.handle(cell->type, cell->parameters, connections); + factory.update_pending(pending, node); } - T node = simplifier.handle(cell->type, cell->parameters, connections); - factory.update_pending(pending, node); } else if (chunk.is_none()) { T node = factory.undriven(chunk.size()); factory.update_pending(pending, node); From 3552a8a2b2cfe9ab487bb44377e48d9f4fc4fd84 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 12 Jun 2024 09:41:42 +0200 Subject: [PATCH 097/342] sim.h cannot use log_assert because does not include yosys headers --- backends/functional/cxx_runtime/sim.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 310927f5b..3a398a13a 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -21,6 +21,7 @@ #define SIM_H #include +#include template using Signal = std::array; @@ -249,7 +250,7 @@ Signal $shl(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - log_assert(!b[i]); + assert(!b[i]); size_t amount = as_int(b); Signal ret = $const(0); if(amount < n){ @@ -266,7 +267,7 @@ Signal $shr(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - log_assert(!b[i]); + assert(!b[i]); size_t amount = as_int(b); Signal ret; for (size_t i = 0; i < n; i++) { @@ -283,7 +284,7 @@ Signal $asr(Signal const& a, Signal const &b) { if(nb >= sizeof(int) * 8 - 1) for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - log_assert(!b[i]); + assert(!b[i]); size_t amount = as_int(b); Signal ret; for (size_t i = 0; i < n; i++) { @@ -344,7 +345,7 @@ Signal concat(Signal const& a, Signal const& b) template Signal $zero_extend(Signal const& a) { - log_assert(n >= m); + assert(n >= m); Signal ret; std::copy(a.begin(), a.end(), ret.begin()); for(size_t i = m; i < n; i++) @@ -355,7 +356,7 @@ Signal $zero_extend(Signal const& a) template Signal $sign_extend(Signal const& a) { - log_assert(n >= m); + assert(n >= m); Signal ret; std::copy(a.begin(), a.end(), ret.begin()); for(size_t i = m; i < n; i++) From dbf2bc3b1dfe0a316e33ada2abb99fa65c8e0616 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 12 Jun 2024 12:27:43 +0100 Subject: [PATCH 098/342] need unsigned comparison when checking shift widths for overflow in functional backend --- kernel/graphtools.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/graphtools.h b/kernel/graphtools.h index 98046c6be..4fb7aacf4 100644 --- a/kernel/graphtools.h +++ b/kernel/graphtools.h @@ -40,7 +40,7 @@ class CellSimplifier { } else { reduced_b_width = new_width; T lower_b = factory.slice(b, b_width, 0, new_width); - T overflow = factory.gt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); + T overflow = factory.ugt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); } } From 248d5f72d41c7194b54f493a692f9f312e198979 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 20 Jun 2024 16:25:21 +0100 Subject: [PATCH 099/342] add support for std::variant to hashlib --- kernel/hashlib.h | 19 +++++++++++++++++++ kernel/yosys_common.h | 1 + 2 files changed, 20 insertions(+) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 6b880f3a6..d32db6832 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -186,6 +186,25 @@ inline unsigned int mkhash(const T &v) { return hash_ops().hash(v); } +template<> struct hash_ops { + static inline bool cmp(std::monostate a, std::monostate b) { + return a == b; + } + static inline unsigned int hash(std::monostate) { + return mkhash_init; + } +}; + +template struct hash_ops> { + static inline bool cmp(std::variant a, std::variant b) { + return a == b; + } + static inline unsigned int hash(std::variant a) { + unsigned int h = std::visit([](const auto &v) { return mkhash(v); }, a); + return mkhash(a.index(), h); + } +}; + inline int hashtable_size(int min_size) { // Primes as generated by https://oeis.org/A175953 diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 56d2356b1..e71e94a78 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include From 6f9e21219b8536cd957c49b49f442d4372038590 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 20 Jun 2024 16:40:02 +0100 Subject: [PATCH 100/342] add new generic compute graph and rewrite c++ functional backend to use it --- Makefile | 2 +- backends/functional/Makefile.inc | 3 +- backends/functional/cxx.cc | 392 +++++++---------------- backends/functional/test_generic.cc | 56 ++++ kernel/functional.h | 22 +- kernel/{graphtools.h => functionalir.cc} | 74 ++++- kernel/functionalir.h | 381 ++++++++++++++++++++++ 7 files changed, 628 insertions(+), 302 deletions(-) create mode 100644 backends/functional/test_generic.cc rename kernel/{graphtools.h => functionalir.cc} (88%) create mode 100644 kernel/functionalir.h diff --git a/Makefile b/Makefile index 812a69271..1feeeab95 100644 --- a/Makefile +++ b/Makefile @@ -639,7 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o -OBJS += kernel/drivertools.o +OBJS += kernel/drivertools.o kernel/functionalir.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o endif diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index c712d2aef..f4b968ef3 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,2 +1,3 @@ OBJS += backends/functional/cxx.o -OBJS += backends/functional/smtlib.o +#OBJS += backends/functional/smtlib.o +OBJS += backends/functional/test_generic.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 08d9ba791..789ab7949 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -18,10 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/drivertools.h" -#include "kernel/topo_scc.h" -#include "kernel/functional.h" -#include "kernel/graphtools.h" +#include "kernel/functionalir.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -84,38 +81,17 @@ struct CxxScope { }; struct CxxType { - bool _is_memory; - int _width; - int _addr_width; -public: - CxxType() : _is_memory(false), _width(0), _addr_width(0) { } - CxxType(int width) : _is_memory(false), _width(width), _addr_width(0) { } - CxxType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { } - static CxxType signal(int width) { return CxxType(width); } - static CxxType memory(int addr_width, int data_width) { return CxxType(addr_width, data_width); } - bool is_signal() const { return !_is_memory; } - bool is_memory() const { return _is_memory; } - int width() const { log_assert(is_signal()); return _width; } - int addr_width() const { log_assert(is_memory()); return _addr_width; } - int data_width() const { log_assert(is_memory()); return _width; } + FunctionalIR::Sort sort; + CxxType(FunctionalIR::Sort sort) : sort(sort) {} std::string to_string() const { - if(_is_memory) { - return stringf("Memory<%d, %d>", addr_width(), data_width()); + if(sort.is_memory()) { + return stringf("Memory<%d, %d>", sort.addr_width(), sort.data_width()); + } else if(sort.is_signal()) { + return stringf("Signal<%d>", sort.width()); } else { - return stringf("Signal<%d>", width()); + log_error("unknown sort"); } } - bool operator ==(CxxType const& other) const { - if(_is_memory != other._is_memory) return false; - if(_is_memory && _addr_width != other._addr_width) return false; - return _width == other._width; - } - unsigned int hash() const { - if(_is_memory) - return mkhash(1, mkhash(_width, _addr_width)); - else - return mkhash(0, _width); - } }; struct CxxWriter { @@ -135,9 +111,8 @@ struct CxxStruct { dict types; CxxScope scope; bool generate_methods; - int count; - CxxStruct(std::string name, bool generate_methods = false, int count = 0) - : name(name), generate_methods(generate_methods), count(count) { + CxxStruct(std::string name, bool generate_methods = false) + : name(name), generate_methods(generate_methods) { scope.reserve("out"); scope.reserve("dump"); } @@ -159,7 +134,7 @@ struct CxxStruct { if (generate_methods) { // Add size method f.printf("\tint size() const {\n"); - f.printf("\t\treturn %d;\n", count); + f.printf("\t\treturn %d;\n", types.size()); f.printf("\t}\n\n"); // Add get_input method @@ -197,119 +172,87 @@ struct CxxStruct { } }; -struct CxxFunction { - IdString name; - CxxType type; - dict parameters; - - CxxFunction(IdString name, CxxType type) : name(name), type(type) {} - CxxFunction(IdString name, CxxType type, dict parameters) : name(name), type(type), parameters(parameters) {} - - bool operator==(CxxFunction const &other) const { - return name == other.name && parameters == other.parameters && type == other.type; +struct CxxTemplate { + vector> _v; +public: + CxxTemplate(std::string fmt) { + std::string buf; + for(auto it = fmt.begin(); it != fmt.end(); it++){ + if(*it == '%'){ + it++; + log_assert(it != fmt.end()); + if(*it == '%') + buf += *it; + else { + log_assert(*it >= '0' && *it <= '9'); + _v.emplace_back(std::move(buf)); + _v.emplace_back((int)(*it - '0')); + } + }else + buf += *it; + } + if(!buf.empty()) + _v.emplace_back(std::move(buf)); } - - unsigned int hash() const { - return mkhash(name.hash(), mkhash(type.hash(), parameters.hash())); + template static std::string format(CxxTemplate fmt, Args&&... args) { + vector strs = {args...}; + std::string result; + for(auto &v : fmt._v){ + if(std::string *s = std::get_if(&v)) + result += *s; + else if(int *i = std::get_if(&v)) + result += strs[*i]; + else + log_error("missing case"); + } + return result; } }; -typedef ComputeGraph CxxComputeGraph; - -class CxxComputeGraphFactory { - CxxComputeGraph &graph; - using T = CxxComputeGraph::Ref; - static bool is_single_output(IdString type) - { - auto it = yosys_celltypes.cell_types.find(type); - return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; - } -public: - CxxComputeGraphFactory(CxxComputeGraph &g) : graph(g) {} - T slice(T a, int in_width, int offset, int out_width) { - log_assert(offset + out_width <= in_width); - return graph.add(CxxFunction(ID($$slice), out_width, {{ID(offset), offset}}), 0, std::array{a}); - } - T extend(T a, int in_width, int out_width, bool is_signed) { - log_assert(in_width < out_width); - if(is_signed) - return graph.add(CxxFunction(ID($sign_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); - else - return graph.add(CxxFunction(ID($zero_extend), out_width, {{ID(WIDTH), out_width}}), 0, std::array{a}); - } - T concat(T a, int a_width, T b, int b_width) { - return graph.add(CxxFunction(ID($$concat), a_width + b_width), 0, std::array{a, b}); - } - T add(T a, T b, int width) { return graph.add(CxxFunction(ID($add), width), 0, std::array{a, b}); } - T sub(T a, T b, int width) { return graph.add(CxxFunction(ID($sub), width), 0, std::array{a, b}); } - T bitwise_and(T a, T b, int width) { return graph.add(CxxFunction(ID($and), width), 0, std::array{a, b}); } - T bitwise_or(T a, T b, int width) { return graph.add(CxxFunction(ID($or), width), 0, std::array{a, b}); } - T bitwise_xor(T a, T b, int width) { return graph.add(CxxFunction(ID($xor), width), 0, std::array{a, b}); } - T bitwise_not(T a, int width) { return graph.add(CxxFunction(ID($not), width), 0, std::array{a}); } - T neg(T a, int width) { return graph.add(CxxFunction(ID($neg), width), 0, std::array{a}); } - T mux(T a, T b, T s, int width) { return graph.add(CxxFunction(ID($mux), width), 0, std::array{a, b, s}); } - T pmux(T a, T b, T s, int width, int) { return graph.add(CxxFunction(ID($pmux), width), 0, std::array{a, b, s}); } - T reduce_and(T a, int) { return graph.add(CxxFunction(ID($reduce_and), 1), 0, std::array{a}); } - T reduce_or(T a, int) { return graph.add(CxxFunction(ID($reduce_or), 1), 0, std::array{a}); } - T reduce_xor(T a, int) { return graph.add(CxxFunction(ID($reduce_xor), 1), 0, std::array{a}); } - T eq(T a, T b, int) { return graph.add(CxxFunction(ID($eq), 1), 0, std::array{a, b}); } - T ne(T a, T b, int) { return graph.add(CxxFunction(ID($ne), 1), 0, std::array{a, b}); } - T gt(T a, T b, int) { return graph.add(CxxFunction(ID($gt), 1), 0, std::array{a, b}); } - T ge(T a, T b, int) { return graph.add(CxxFunction(ID($ge), 1), 0, std::array{a, b}); } - T ugt(T a, T b, int) { return graph.add(CxxFunction(ID($ugt), 1), 0, std::array{a, b}); } - T uge(T a, T b, int) { return graph.add(CxxFunction(ID($uge), 1), 0, std::array{a, b}); } - T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array{a, b}); } - - T constant(RTLIL::Const value) { - return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0); - } - T input(IdString name, int width) { return graph.add(CxxFunction(ID($$input), width, {{name, {}}}), 0); } - T state(IdString name, int width) { return graph.add(CxxFunction(ID($$state), width, {{name, {}}}), 0); } - T state_memory(IdString name, int addr_width, int data_width) { - return graph.add(CxxFunction(ID($$state), CxxType::memory(addr_width, data_width), {{name, {}}}), 0); - } - T cell_output(T cell, IdString type, IdString name, int width) { - if (is_single_output(type)) - return cell; - else - return graph.add(CxxFunction(ID($$cell_output), width, {{name, {}}}), 0, std::array{cell}); - } - T multiple(vector args, int width) { - return graph.add(CxxFunction(ID($$multiple), width), 0, args); - } - T undriven(int width) { - return graph.add(CxxFunction(ID($$undriven), width), 0); - } - - T memory_read(T mem, T addr, int addr_width, int data_width) { - return graph.add(CxxFunction(ID($memory_read), data_width), 0, std::array{mem, addr}); - } - T memory_write(T mem, T addr, T data, int addr_width, int data_width) { - return graph.add(CxxFunction(ID($memory_write), CxxType::memory(addr_width, data_width)), 0, std::array{mem, addr, data}); - } - - T create_pending(int width) { - return graph.add(CxxFunction(ID($$pending), width), 0); - } - void update_pending(T pending, T node) { - log_assert(pending.function().name == ID($$pending)); - pending.set_function(CxxFunction(ID($$buf), pending.function().type)); - pending.append_arg(node); - } - void declare_output(T node, IdString name, int) { - node.assign_key(name); - } - void declare_state(T node, IdString name, int) { - node.assign_key(name); - } - void declare_state_memory(T node, IdString name, int, int) { - node.assign_key(name); - } - void suggest_name(T node, IdString name) { - node.sparse_attr() = name; +template struct CxxPrintVisitor { + using Node = FunctionalIR::Node; + NodeNames np; + CxxStruct &input_struct; + CxxStruct &state_struct; + CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { } + template std::string arg_to_string(T n) { return std::to_string(n); } + template<> std::string arg_to_string(std::string n) { return n; } + template<> std::string arg_to_string(Node n) { return np(n); } + template std::string format(std::string fmt, Args&&... args) { + return CxxTemplate::format(fmt, arg_to_string(args)...); } + std::string buf(Node, Node n) { return np(n); } + std::string slice(Node, Node a, int, int offset, int out_width) { return format("slice<%2>(%0, %1)", a, offset, out_width); } + std::string zero_extend(Node, Node a, int, int out_width) { return format("$zero_extend<%1>(%0)", a, out_width); } + std::string sign_extend(Node, Node a, int, int out_width) { return format("$sign_extend<%1>(%0)", a, out_width); } + std::string concat(Node, Node a, int, Node b, int) { return format("concat(%0, %1)", a, b); } + std::string add(Node, Node a, Node b, int) { return format("$add(%0, %1)", a, b); } + std::string sub(Node, Node a, Node b, int) { return format("$sub(%0, %1)", a, b); } + std::string bitwise_and(Node, Node a, Node b, int) { return format("$and(%0, %1)", a, b); } + std::string bitwise_or(Node, Node a, Node b, int) { return format("$or(%0, %1)", a, b); } + std::string bitwise_xor(Node, Node a, Node b, int) { return format("$xor(%0, %1)", a, b); } + std::string bitwise_not(Node, Node a, int) { return format("$not(%0)", a); } + std::string unary_minus(Node, Node a, int) { return format("$neg(%0)", a); } + std::string reduce_and(Node, Node a, int) { return format("$reduce_and(%0)", a); } + std::string reduce_or(Node, Node a, int) { return format("$reduce_or(%0)", a); } + std::string reduce_xor(Node, Node a, int) { return format("$reduce_xor(%0)", a); } + std::string equal(Node, Node a, Node b, int) { return format("$eq(%0, %1)", a, b); } + std::string not_equal(Node, Node a, Node b, int) { return format("$ne(%0, %1)", a, b); } + std::string signed_greater_than(Node, Node a, Node b, int) { return format("$gt(%0, %1)", a, b); } + std::string signed_greater_equal(Node, Node a, Node b, int) { return format("$ge(%0, %1)", a, b); } + std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("$ugt(%0, %1)", a, b); } + std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("$uge(%0, %1)", a, b); } + std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("$shl<%2>(%0, %1)", a, b, a.width()); } + std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("$shr<%2>(%0, %1)", a, b, a.width()); } + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("$asr<%2>(%0, %1)", a, b, a.width()); } + std::string mux(Node, Node a, Node b, Node s, int) { return format("$mux(%0, %1, %2)", a, b, s); } + std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("$pmux(%0, %1, %2)", a, b, s); } + std::string constant(Node, RTLIL::Const value) { return format("$const<%0>(%1)", value.size(), value.as_int()); } + std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); } + std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); } + std::string memory_read(Node, Node mem, Node addr, int, int) { return format("$memory_read(%0, %1)", mem, addr); } + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("$memory_write(%0, %1, %2)", mem, addr, data); } + std::string undriven(Node, int width) { return format("$const<%0>(0)", width); } }; struct FunctionalCxxBackend : public Backend @@ -322,88 +265,24 @@ struct FunctionalCxxBackend : public Backend log("\n"); } - CxxComputeGraph calculate_compute_graph(RTLIL::Module *module) + void printCxx(std::ostream &stream, std::string, std::string const & name, Module *module) { - CxxComputeGraph compute_graph; - CxxComputeGraphFactory factory(compute_graph); - ComputeGraphConstruction construction(factory); - construction.add_module(module); - construction.process_queue(); - - // Perform topo sort and detect SCCs - CxxComputeGraph::SccAdaptor compute_graph_scc(compute_graph); - - bool scc = false; - std::vector perm; - topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { - perm.insert(perm.end(), begin, end); - if (end > begin + 1) - { - log_warning("SCC:"); - for (int *i = begin; i != end; ++i) - log(" %d(%s)(%s)", *i, compute_graph[*i].function().name.c_str(), compute_graph[*i].has_sparse_attr() ? compute_graph[*i].sparse_attr().c_str() : ""); - log("\n"); - scc = true; - } - }, /* sources_first */ true); - compute_graph.permute(perm); - if(scc) log_error("combinational loops, aborting\n"); - - // Forward $$buf - std::vector alias; - perm.clear(); - - for (int i = 0; i < compute_graph.size(); ++i) - { - auto node = compute_graph[i]; - if (node.function().name == ID($$buf) && node.arg(0).index() < i) - { - int target_index = alias[node.arg(0).index()]; - auto target_node = compute_graph[perm[target_index]]; - if(!target_node.has_sparse_attr() && node.has_sparse_attr()){ - IdString id = node.sparse_attr(); - target_node.sparse_attr() = id; - } - alias.push_back(target_index); - } - else - { - alias.push_back(GetSize(perm)); - perm.push_back(i); - } - } - compute_graph.permute(perm, alias); - return compute_graph; - } - - void printCxx(std::ostream &stream, std::string, std::string const & name, CxxComputeGraph &compute_graph) - { - dict inputs, state; + auto ir = FunctionalIR::from_module(module); CxxWriter f(stream); - // Dump the compute graph - for (int i = 0; i < compute_graph.size(); ++i) - { - auto ref = compute_graph[i]; - if(ref.function().name == ID($$input)) - inputs[ref.function().parameters.begin()->first] = ref.function().type; - if(ref.function().name == ID($$state)) - state[ref.function().parameters.begin()->first] = ref.function().type; - } f.printf("#include \"sim.h\"\n"); f.printf("#include \n"); - CxxStruct input_struct(name + "_Inputs", true, inputs.size()); - for (auto const &input : inputs) - input_struct.insert(input.first, input.second); + CxxStruct input_struct(name + "_Inputs", true); + for (auto [name, sort] : ir.inputs()) + input_struct.insert(name, sort); CxxStruct output_struct(name + "_Outputs"); - for (auto const &key : compute_graph.keys()) - if(state.count(key.first) == 0) - output_struct.insert(key.first, compute_graph[key.second].function().type); + for (auto [name, sort] : ir.outputs()) + output_struct.insert(name, sort); CxxStruct state_struct(name + "_State"); - for (auto const &state_var : state) - state_struct.insert(state_var.first, state_var.second); + for (auto [name, sort] : ir.state()) + state_struct.insert(name, sort); - idict node_names; + dict node_names; CxxScope locals; input_struct.print(f); @@ -415,73 +294,17 @@ struct FunctionalCxxBackend : public Backend locals.reserve("output"); locals.reserve("current_state"); locals.reserve("next_state"); - for (int i = 0; i < compute_graph.size(); ++i) + auto node_to_string = [&](FunctionalIR::Node n) { return node_names.at(n.id()); }; + for (auto node : ir) { - auto ref = compute_graph[i]; - auto type = ref.function().type; - std::string name; - if(ref.has_sparse_attr()) - name = locals.insert(ref.sparse_attr()); - else - name = locals.insert("\\n" + std::to_string(i)); - node_names(name); - if(ref.function().name == ID($$input)) - f.printf("\t%s %s = input.%s;\n", type.to_string().c_str(), name.c_str(), input_struct[ref.function().parameters.begin()->first].c_str()); - else if(ref.function().name == ID($$state)) - f.printf("\t%s %s = current_state.%s;\n", type.to_string().c_str(), name.c_str(), state_struct[ref.function().parameters.begin()->first].c_str()); - else if(ref.function().name == ID($$buf)) - f.printf("\t%s %s = %s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str()); - else if(ref.function().name == ID($$cell_output)) - f.printf("\t%s %s = %s.%s;\n", type.to_string().c_str(), name.c_str(), node_names[ref.arg(0).index()].c_str(), RTLIL::unescape_id(ref.function().parameters.begin()->first).c_str()); - else if(ref.function().name == ID($$const)){ - auto c = ref.function().parameters.begin()->second; - if(c.size() <= 32){ - f.printf("\t%s %s = $const<%d>(%#x);\n", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int()); - }else{ - f.printf("\t%s %s = $const<%d>({%#x", type.to_string().c_str(), name.c_str(), type.width(), (uint32_t) c.as_int()); - while(c.size() > 32){ - c = c.extract(32, c.size() - 32); - f.printf(", %#x", c.as_int()); - } - f.printf("});\n"); - } - }else if(ref.function().name == ID($$undriven)) - f.printf("\t%s %s; //undriven\n", type.to_string().c_str(), name.c_str()); - else if(ref.function().name == ID($$slice)) - f.printf("\t%s %s = slice<%d>(%s, %d);\n", type.to_string().c_str(), name.c_str(), type.width(), node_names[ref.arg(0).index()].c_str(), ref.function().parameters.at(ID(offset)).as_int()); - else if(ref.function().name == ID($$concat)){ - f.printf("\tauto %s = concat(", name.c_str()); - for (int i = 0, end = ref.size(); i != end; ++i){ - if(i > 0) - f.printf(", "); - f.printf("%s", node_names[ref.arg(i).index()].c_str()); - } - f.printf(");\n"); - }else{ - f.printf("\t"); - f.printf("%s %s = %s", type.to_string().c_str(), name.c_str(), log_id(ref.function().name)); - if(ref.function().parameters.count(ID(WIDTH))){ - f.printf("<%d>", ref.function().parameters.at(ID(WIDTH)).as_int()); - } - f.printf("("); - for (int i = 0, end = ref.size(); i != end; ++i) - f.printf("%s%s", i>0?", ":"", node_names[ref.arg(i).index()].c_str()); - f.printf("); //"); - for (auto const ¶m : ref.function().parameters) - { - if (param.second.empty()) - f.printf("[%s]", log_id(param.first)); - else - f.printf("[%s=%s]", log_id(param.first), log_const(param.second)); - } - f.printf("\n"); - } - } - - for (auto const &key : compute_graph.keys()) - { - f.printf("\t%s.%s = %s;\n", state.count(key.first) > 0 ? "next_state" : "output", state_struct[key.first].c_str(), node_names[key.second].c_str()); + std::string name = locals.insert(node.name()); + node_names.emplace(node.id(), name); + f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), name.c_str(), node.visit(CxxPrintVisitor(node_to_string, input_struct, state_struct)).c_str()); } + for (auto [name, sort] : ir.state()) + f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_to_string(ir.get_state_next_node(name)).c_str()); + for (auto [name, sort] : ir.outputs()) + f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_to_string(ir.get_output_node(name)).c_str()); f.printf("}\n"); } @@ -494,8 +317,7 @@ struct FunctionalCxxBackend : public Backend for (auto module : design->selected_modules()) { log("Dumping module `%s'.\n", module->name.c_str()); - auto compute_graph = calculate_compute_graph(module); - printCxx(*f, filename, RTLIL::unescape_id(module->name), compute_graph); + printCxx(*f, filename, RTLIL::unescape_id(module->name), module); } } } FunctionalCxxBackend; diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc new file mode 100644 index 000000000..172ac7fd6 --- /dev/null +++ b/backends/functional/test_generic.cc @@ -0,0 +1,56 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/functionalir.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct FunctionalTestGeneric : public Pass +{ + FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Test Generic.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Dumping module `%s'.\n", module->name.c_str()); + auto fir = FunctionalIR::from_module(module); + for(auto node : fir) + std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; + for(auto [name, sort] : fir.outputs()) + std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n"; + for(auto [name, sort] : fir.state()) + std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n"; + } + } +} FunctionalCxxBackend; + +PRIVATE_NAMESPACE_END diff --git a/kernel/functional.h b/kernel/functional.h index e5ee88240..09a882643 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -123,6 +123,8 @@ public: Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } public: + Ref(BaseRef ref) : Ref(ref.graph_, ref.index_) {} + void set_function(Fn const &function) const { deref().fn_index = this->graph_->functions(function); @@ -224,7 +226,7 @@ public: } template - Ref add(Fn const &function, Attr const &attr, T const &args) + Ref add(Fn const &function, Attr const &attr, T &&args) { Ref added = add(function, attr); for (auto arg : args) @@ -233,7 +235,23 @@ public: } template - Ref add(Fn const &function, Attr &&attr, T const &args) + Ref add(Fn const &function, Attr &&attr, T &&args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + Ref add(Fn const &function, Attr const &attr, std::initializer_list args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + Ref add(Fn const &function, Attr &&attr, std::initializer_list args) { Ref added = add(function, std::move(attr)); for (auto arg : args) diff --git a/kernel/graphtools.h b/kernel/functionalir.cc similarity index 88% rename from kernel/graphtools.h rename to kernel/functionalir.cc index 4fb7aacf4..27765ac26 100644 --- a/kernel/graphtools.h +++ b/kernel/functionalir.cc @@ -17,15 +17,8 @@ * */ -#ifndef GRAPHTOOLS_H -#define GRAPHTOOLS_H +#include "kernel/functionalir.h" -#include "kernel/yosys.h" -#include "kernel/drivertools.h" -#include "kernel/functional.h" -#include "kernel/mem.h" - -USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN template @@ -196,7 +189,7 @@ public: }; template -class ComputeGraphConstruction { +class FunctionalIRConstruction { std::deque queue; dict graph_nodes; idict cells; @@ -218,7 +211,7 @@ class ComputeGraphConstruction { return it->second; } public: - ComputeGraphConstruction(Factory &f) : factory(f), simplifier(f) {} + FunctionalIRConstruction(Factory &f) : factory(f), simplifier(f) {} void add_module(Module *module) { driver_map.add(module); @@ -238,8 +231,9 @@ public: memories[mem.cell] = &mem; } } - T concatenate_read_results(Mem *mem, vector results) + T concatenate_read_results(Mem *, vector results) { + /* TODO: write code to check that this is ok to do */ if(results.size() == 0) return factory.undriven(0); T node = results[0]; @@ -381,6 +375,60 @@ public: } }; -YOSYS_NAMESPACE_END +FunctionalIR FunctionalIR::from_module(Module *module) { + FunctionalIR ir; + auto factory = ir.factory(); + FunctionalIRConstruction ctor(factory); + ctor.add_module(module); + ctor.process_queue(); + ir.topological_sort(); + ir.forward_buf(); + return ir; +} -#endif +void FunctionalIR::topological_sort() { + Graph::SccAdaptor compute_graph_scc(_graph); + bool scc = false; + std::vector perm; + topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + perm.insert(perm.end(), begin, end); + if (end > begin + 1) + { + log_warning("SCC:"); + for (int *i = begin; i != end; ++i) + log(" %d", *i); + log("\n"); + scc = true; + } + }, /* sources_first */ true); + _graph.permute(perm); + if(scc) log_error("combinational loops, aborting\n"); +} + +void FunctionalIR::forward_buf() { + std::vector perm, alias; + perm.clear(); + + for (int i = 0; i < _graph.size(); ++i) + { + auto node = _graph[i]; + if (node.function().fn() == Fn::buf && node.arg(0).index() < i) + { + int target_index = alias[node.arg(0).index()]; + auto target_node = _graph[perm[target_index]]; + if(!target_node.has_sparse_attr() && node.has_sparse_attr()){ + IdString id = node.sparse_attr(); + target_node.sparse_attr() = id; + } + alias.push_back(target_index); + } + else + { + alias.push_back(GetSize(perm)); + perm.push_back(i); + } + } + _graph.permute(perm, alias); +} + +YOSYS_NAMESPACE_END diff --git a/kernel/functionalir.h b/kernel/functionalir.h new file mode 100644 index 000000000..7eca9d87f --- /dev/null +++ b/kernel/functionalir.h @@ -0,0 +1,381 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef FUNCTIONALIR_H +#define FUNCTIONALIR_H + +#include "kernel/yosys.h" +#include "kernel/functional.h" +#include "kernel/drivertools.h" +#include "kernel/mem.h" +#include "kernel/topo_scc.h" + +USING_YOSYS_NAMESPACE +YOSYS_NAMESPACE_BEGIN + +class FunctionalIR { + enum class Fn { + invalid, + buf, + slice, + zero_extend, + sign_extend, + concat, + add, + sub, + bitwise_and, + bitwise_or, + bitwise_xor, + bitwise_not, + reduce_and, + reduce_or, + reduce_xor, + unary_minus, + equal, + not_equal, + signed_greater_than, + signed_greater_equal, + unsigned_greater_than, + unsigned_greater_equal, + logical_shift_left, + logical_shift_right, + arithmetic_shift_right, + mux, + pmux, + constant, + input, + state, + multiple, + undriven, + memory_read, + memory_write + }; +public: + class Sort { + std::variant> _v; + public: + explicit Sort(int width) : _v(width) { } + Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { } + bool is_signal() const { return _v.index() == 0; } + bool is_memory() const { return _v.index() == 1; } + int width() const { return std::get<0>(_v); } + int addr_width() const { return std::get<1>(_v).first; } + int data_width() const { return std::get<1>(_v).second; } + bool operator==(Sort const& other) const { return _v == other._v; } + unsigned int hash() const { return mkhash(_v); } + }; +private: + class NodeData { + Fn _fn; + std::variant< + std::monostate, + RTLIL::Const, + IdString, + int + > _extra; + public: + NodeData() : _fn(Fn::invalid) {} + NodeData(Fn fn) : _fn(fn) {} + template NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward(extra)) {} + Fn fn() const { return _fn; } + const RTLIL::Const &as_const() const { return std::get(_extra); } + IdString as_idstring() const { return std::get(_extra); } + int as_int() const { return std::get(_extra); } + int hash() const { + return mkhash((unsigned int) _fn, mkhash(_extra)); + } + bool operator==(NodeData const &other) const { + return _fn == other._fn && _extra == other._extra; + } + }; + struct Attr { + Sort sort; + }; + using Graph = ComputeGraph>; + Graph _graph; + dict _inputs; + dict _outputs; + dict _state; + void add_input(IdString name, Sort sort) { + auto [it, found] = _inputs.emplace(name, std::move(sort)); + if(found) + log_assert(it->second == sort); + } + void add_state(IdString name, Sort sort) { + auto [it, found] = _state.emplace(name, std::move(sort)); + if(found) + log_assert(it->second == sort); + } + void add_output(IdString name, Sort sort) { + auto [it, found] = _outputs.emplace(name, std::move(sort)); + if(found) + log_assert(it->second == sort); + } +public: + class Factory; + class Node { + friend class Factory; + friend class FunctionalIR; + Graph::Ref _ref; + Node(Graph::Ref ref) : _ref(ref) { } + operator Graph::Ref() { return _ref; } + template struct PrintVisitor { + NodePrinter np; + PrintVisitor(NodePrinter np) : np(np) { } + std::string buf(Node, Node n) { return "buf(" + np(n) + ")"; } + std::string slice(Node, Node a, int, int offset, int out_width) { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; } + std::string zero_extend(Node, Node a, int, int out_width) { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } + std::string sign_extend(Node, Node a, int, int out_width) { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } + std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; } + std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; } + std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; } + std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; } + std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; } + std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; } + std::string bitwise_not(Node, Node a, int) { return "bitwise_not(" + np(a) + ")"; } + std::string unary_minus(Node, Node a, int) { return "unary_minus(" + np(a) + ")"; } + std::string reduce_and(Node, Node a, int) { return "reduce_and(" + np(a) + ")"; } + std::string reduce_or(Node, Node a, int) { return "reduce_or(" + np(a) + ")"; } + std::string reduce_xor(Node, Node a, int) { return "reduce_xor(" + np(a) + ")"; } + std::string equal(Node, Node a, Node b, int) { return "equal(" + np(a) + ", " + np(b) + ")"; } + std::string not_equal(Node, Node a, Node b, int) { return "not_equal(" + np(a) + ", " + np(b) + ")"; } + std::string signed_greater_than(Node, Node a, Node b, int) { return "signed_greater_than(" + np(a) + ", " + np(b) + ")"; } + std::string signed_greater_equal(Node, Node a, Node b, int) { return "signed_greater_equal(" + np(a) + ", " + np(b) + ")"; } + std::string unsigned_greater_than(Node, Node a, Node b, int) { return "unsigned_greater_than(" + np(a) + ", " + np(b) + ")"; } + std::string unsigned_greater_equal(Node, Node a, Node b, int) { return "unsigned_greater_equal(" + np(a) + ", " + np(b) + ")"; } + std::string logical_shift_left(Node, Node a, Node b, int, int) { return "logical_shift_left(" + np(a) + ", " + np(b) + ")"; } + std::string logical_shift_right(Node, Node a, Node b, int, int) { return "logical_shift_right(" + np(a) + ", " + np(b) + ")"; } + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return "arithmetic_shift_right(" + np(a) + ", " + np(b) + ")"; } + std::string mux(Node, Node a, Node b, Node s, int) { return "mux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; } + std::string pmux(Node, Node a, Node b, Node s, int, int) { return "pmux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; } + std::string constant(Node, RTLIL::Const value) { return "constant(" + value.as_string() + ")"; } + std::string input(Node, IdString name) { return "input(" + name.str() + ")"; } + std::string state(Node, IdString name) { return "state(" + name.str() + ")"; } + std::string memory_read(Node, Node mem, Node addr, int, int) { return "memory_read(" + np(mem) + ", " + np(addr) + ")"; } + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return "memory_write(" + np(mem) + ", " + np(addr) + ", " + np(data) + ")"; } + std::string undriven(Node, int width) { return "undriven(" + std::to_string(width) + ")"; } + }; + public: + int id() const { return _ref.index(); } + IdString name() const { + if(_ref.has_sparse_attr()) + return _ref.sparse_attr(); + else + return std::string("\\n") + std::to_string(id()); + } + Sort sort() const { return _ref.attr().sort; } + int width() const { return sort().width(); } + Node arg(int n) const { return Node(_ref.arg(n)); } + template auto visit(Visitor v) const + { + switch(_ref.function().fn()) { + case Fn::invalid: log_error("invalid node in visit"); break; + case Fn::buf: return v.buf(*this, arg(0)); break; + case Fn::slice: return v.slice(*this, arg(0), arg(0).width(), _ref.function().as_int(), sort().width()); break; + case Fn::zero_extend: return v.zero_extend(*this, arg(0), arg(0).width(), width()); break; + case Fn::sign_extend: return v.sign_extend(*this, arg(0), arg(0).width(), width()); break; + case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break; + case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break; + case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break; + case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break; + case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break; + case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break; + case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break; + case Fn::unary_minus: return v.bitwise_not(*this, arg(0), sort().width()); break; + case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break; + case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break; + case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break; + case Fn::equal: return v.equal(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1), arg(0).width()); break; + case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; + case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; + case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; + case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2), arg(0).width()); break; + case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2), arg(0).width(), arg(2).width()); break; + case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; + case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; + case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; + case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1), arg(1).width(), width()); break; + case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2), arg(1).width(), arg(2).width()); break; + case Fn::multiple: log_error("multiple in visit"); break; + case Fn::undriven: return v.undriven(*this, width()); break; + } + } + template std::string to_string(NodePrinter np) + { + return visit(PrintVisitor(np)); + } + /* TODO: delete */ int size() const { return sort().width(); } + }; + class Factory { + FunctionalIR &_ir; + friend class FunctionalIR; + explicit Factory(FunctionalIR &ir) : _ir(ir) {} + Node add(NodeData &&fn, Sort &&sort, std::initializer_list args) { + Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); + for (auto arg : args) + ref.append_arg(Graph::Ref(arg)); + return ref; + } + void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } + void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); } + void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } + public: + Node slice(Node a, int, int offset, int out_width) { + log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); + return add(NodeData(Fn::slice, offset), Sort(out_width), {a}); + } + Node extend(Node a, int, int out_width, bool is_signed) { + log_assert(a.sort().is_signal() && a.sort().width() < out_width); + if(is_signed) + return add(Fn::sign_extend, Sort(out_width), {a}); + else + return add(Fn::zero_extend, Sort(out_width), {a}); + } + Node concat(Node a, int, Node b, int) { + log_assert(a.sort().is_signal() && b.sort().is_signal()); + return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b}); + } + Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } + Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } + Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } + Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } + Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } + Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } + Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } + Node reduce_and(Node a, int) { check_unary(a); return add(Fn::reduce_and, Sort(1), {a}); } + Node reduce_or(Node a, int) { check_unary(a); return add(Fn::reduce_or, Sort(1), {a}); } + Node reduce_xor(Node a, int) { check_unary(a); return add(Fn::reduce_xor, Sort(1), {a}); } + Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } + Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } + Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } + Node signed_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); } + Node unsigned_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); } + Node unsigned_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); } + Node logical_shift_left(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); } + Node logical_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); } + Node arithmetic_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); } + Node mux(Node a, Node b, Node s, int) { + log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1)); + return add(Fn::mux, a.sort(), {a, b, s}); + } + Node pmux(Node a, Node b, Node s, int, int) { + log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width()); + return add(Fn::pmux, a.sort(), {a, b, s}); + } + Node memory_read(Node mem, Node addr, int, int) { + log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width()); + return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr}); + } + Node memory_write(Node mem, Node addr, Node data, int, int) { + log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() && + mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width()); + return add(Fn::memory_write, mem.sort(), {mem, addr, data}); + } + Node constant(RTLIL::Const value) { + return add(NodeData(Fn::constant, std::move(value)), Sort(value.size()), {}); + } + Node create_pending(int width) { + return add(Fn::buf, Sort(width), {}); + } + void update_pending(Node node, Node value) { + log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0 && node.sort() == value.sort()); + node._ref.append_arg(value._ref); + } + Node input(IdString name, int width) { + _ir.add_input(name, Sort(width)); + return add(NodeData(Fn::input, name), Sort(width), {}); + } + Node state(IdString name, int width) { + _ir.add_state(name, Sort(width)); + return add(NodeData(Fn::state, name), Sort(width), {}); + } + Node state_memory(IdString name, int addr_width, int data_width) { + _ir.add_state(name, Sort(addr_width, data_width)); + return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {}); + } + Node cell_output(Node node, IdString, IdString, int) { + return node; + } + Node multiple(vector args, int width) { + auto node = add(Fn::multiple, Sort(width), {}); + for(const auto &arg : args) + node._ref.append_arg(arg._ref); + return node; + } + Node undriven(int width) { + return add(Fn::undriven, Sort(width), {}); + } + void declare_output(Node node, IdString name, int width) { + _ir.add_output(name, Sort(width)); + node._ref.assign_key({name, false}); + } + void declare_state(Node node, IdString name, int width) { + _ir.add_state(name, Sort(width)); + node._ref.assign_key({name, true}); + } + void declare_state_memory(Node node, IdString name, int addr_width, int data_width) { + _ir.add_state(name, Sort(addr_width, data_width)); + node._ref.assign_key({name, true}); + } + void suggest_name(Node node, IdString name) { + node._ref.sparse_attr() = name; + } + + /* TODO delete this later*/ + Node eq(Node a, Node b, int) { return equal(a, b, 0); } + Node ne(Node a, Node b, int) { return not_equal(a, b, 0); } + Node gt(Node a, Node b, int) { return signed_greater_than(a, b, 0); } + Node ge(Node a, Node b, int) { return signed_greater_equal(a, b, 0); } + Node ugt(Node a, Node b, int) { return unsigned_greater_than(a, b, 0); } + Node uge(Node a, Node b, int) { return unsigned_greater_equal(a, b, 0); } + Node neg(Node a, int) { return unary_minus(a, 0); } + }; + static FunctionalIR from_module(Module *module); + Factory factory() { return Factory(*this); } + int size() const { return _graph.size(); } + Node operator[](int i) { return _graph[i]; } + void topological_sort(); + void forward_buf(); + dict inputs() const { return _inputs; } + dict outputs() const { return _outputs; } + dict state() const { return _state; } + Node get_output_node(IdString name) { return _graph({name, false}); } + Node get_state_next_node(IdString name) { return _graph({name, true}); } + class Iterator { + friend class FunctionalIR; + FunctionalIR &_ir; + int _index; + Iterator(FunctionalIR &ir, int index) : _ir(ir), _index(index) {} + public: + Node operator*() { return _ir._graph[_index]; } + Iterator &operator++() { _index++; return *this; } + bool operator!=(Iterator const &other) const { return _index != other._index; } + }; + Iterator begin() { return Iterator(*this, 0); } + Iterator end() { return Iterator(*this, _graph.size()); } +}; + +YOSYS_NAMESPACE_END + +#endif From 4e370f4426bf53144b322911d0a68c4724d2dfea Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 21 Jun 2024 12:59:34 +0200 Subject: [PATCH 101/342] Initial functional SMT backend using functional IR --- backends/functional/Makefile.inc | 2 +- backends/functional/cxx.cc | 4 +- backends/functional/smtlib.cc | 833 +++++++++++-------------------- 3 files changed, 290 insertions(+), 549 deletions(-) diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index f4b968ef3..13c962c99 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,3 +1,3 @@ OBJS += backends/functional/cxx.o -#OBJS += backends/functional/smtlib.o +OBJS += backends/functional/smtlib.o OBJS += backends/functional/test_generic.o diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 789ab7949..9571385cc 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -216,8 +216,8 @@ template struct CxxPrintVisitor { CxxStruct &state_struct; CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { } template std::string arg_to_string(T n) { return std::to_string(n); } - template<> std::string arg_to_string(std::string n) { return n; } - template<> std::string arg_to_string(Node n) { return np(n); } + std::string arg_to_string(std::string n) { return n; } + std::string arg_to_string(Node n) { return np(n); } template std::string format(std::string fmt, Args&&... args) { return CxxTemplate::format(fmt, arg_to_string(args)...); } diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index a90927ab6..a24ab8401 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -18,574 +18,315 @@ */ #include "kernel/yosys.h" -#include "kernel/drivertools.h" -#include "kernel/topo_scc.h" -#include "kernel/functional.h" -#include "kernel/graphtools.h" +#include "kernel/functionalir.h" +#include +#include +#include +#include +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SmtlibScope { - pool used_names; - dict name_map; +struct SmtScope { + pool used_names; + dict name_map; - SmtlibScope() { - /*for(const char **p = reserved_keywords; *p != nullptr; p++) - reserve(*p);*/ - } - void reserve(std::string name) { - used_names.insert(name); - } - std::string insert(IdString id) { - std::string str = RTLIL::unescape_id(id); - for(size_t i = 0; i < str.size(); i++) - if(!((unsigned char)str[i] < 0x80 && (isalnum(str[i]) || strchr("~!@$%^&*_-+=<>.?/", str[i])))) - str[i] = '_'; - if(used_names.count(str) == 0){ - used_names.insert(str); - name_map.insert({id, str}); - return str; - } - for (int idx = 0 ; ; idx++){ - std::string suffixed = str + "_" + std::to_string(idx); - if (used_names.count(suffixed) == 0) { - used_names.insert(suffixed); - if(name_map.count(id) == 0) - name_map.insert({id, suffixed}); - return suffixed; - } - } - } - std::string operator[](IdString id) { - if(name_map.count(id) > 0) - return name_map[id]; - else - return insert(id); - } -}; + SmtScope() {} + + void reserve(const std::string& name) { + used_names.insert(name); + } -struct SmtlibWriter { - std::ostream &f; - SmtlibWriter(std::ostream &out) : f(out) {} - void printf(const char *fmt, ...) - { - va_list va; - va_start(va, fmt); - f << vstringf(fmt, va); - va_end(va); - } - template - SmtlibWriter & operator <<(T &&arg) { - f << std::forward(arg); - return *this; - } -}; - -struct Arg { - int n; - explicit Arg(int n_) : n(n_) {} - bool operator ==(Arg const &other) const { return n == other.n; } -}; - -class SExpr { - enum class Type { - None, - List, - Atom, - Arg, - }; - Type type = Type::None; - union { - std::string atom_; - vector list_; - Arg arg_; - }; - void set_none() { - switch(type) { - case Type::None: break; - case Type::Atom: atom_.~basic_string(); break; - case Type::List: list_.~vector(); break; - case Type::Arg: arg_.~Arg(); break; - } - type = Type::None; + std::string insert(IdString id) { + std::string name = RTLIL::unescape_id(id); + if (used_names.count(name) == 0) { + used_names.insert(name); + name_map[id] = name; + return name; } -public: - SExpr() {} - SExpr(const char *atom) : type(Type::Atom), atom_(atom) {} - SExpr(std::string atom) : type(Type::Atom), atom_(atom) {} - SExpr(int n) : type(Type::Atom), atom_(std::to_string(n)) {} - SExpr(RTLIL::Const const & n) : type(Type::Atom) { - new(&atom_) std::string("#b"); - atom_.reserve(n.size() + 2); - for (size_t i = n.size(); i > 0; i--) - if(n[i-1] == State::S1) - atom_ += "1"; - else - atom_ += "0"; - } - SExpr(vector &&list) : type(Type::List), list_(list) {} - SExpr(std::initializer_list list) : type(Type::List), list_(list) {} - SExpr(Arg arg) : type(Type::Arg), arg_(arg) {} - SExpr(SExpr const &other) { *this = other; } - SExpr(SExpr &&other) { *this = std::move(other); } - SExpr &operator =(SExpr const &other) { - set_none(); - switch(other.type) { - case Type::None: break; - case Type::Atom: new(&atom_) std::string(other.atom_); break; - case Type::List: new(&list_) vector(other.list_); break; - case Type::Arg: new(&arg_) Arg(other.arg_); break; - } - type = other.type; - return *this; + for (int idx = 0;; ++idx) { + std::string new_name = name + "_" + std::to_string(idx); + if (used_names.count(new_name) == 0) { + used_names.insert(new_name); + name_map[id] = new_name; + return new_name; + } } - SExpr &operator =(SExpr &&other) { - set_none(); - switch(other.type) { - case Type::None: break; - case Type::Atom: new(&atom_) std::string(std::move(other.atom_)); break; - case Type::List: new(&list_) vector(std::move(other.list_)); break; - case Type::Arg: new(&arg_) Arg(std::move(other.arg_)); break; - } - type = other.type; - return *this; + } + + std::string operator[](IdString id) { + if (name_map.count(id)) { + return name_map[id]; + } else { + return insert(id); } - ~SExpr() { set_none(); } - bool operator==(SExpr const &other) const { - if(type != other.type) return false; - switch(type) { - case Type::None: return true; - case Type::Atom: return atom_ == other.atom_; - case Type::List: return list_ == other.list_; - case Type::Arg: return arg_ == other.arg_; - } - } - bool is_none() const { return type == Type::None; } - bool is_atom() const { return type == Type::Atom; } - bool is_list() const { return type == Type::List; } - bool is_arg() const { return type == Type::Arg; } - std::string const &atom() const { log_assert(is_atom()); return atom_; } - std::vector const &list() const { log_assert(is_list()); return list_; } - Arg const &arg() const { log_assert(is_arg()); return arg_; } - unsigned int hash() const { - unsigned int inner; - switch(type) { - case Type::None: inner = 0; break; - case Type::Atom: inner = mkhash(atom_); break; - case Type::List: inner = mkhash(list_); break; - case Type::Arg: inner = arg_.n; break; - } - return mkhash((unsigned int) type, inner); - } - SExpr subst_args(std::vector const & args) const { - switch(type) { - case Type::None: - case Type::Atom: - return *this; - case Type::List: { - vector ret; - for(auto & a : list_) - ret.emplace_back(a.subst_args(args)); - return SExpr(std::move(ret)); - } - case Type::Arg: - if(arg_.n >= 1 && (size_t)arg_.n <= args.size()) - return args[arg_.n - 1]; - else - return *this; - } - } + } }; -std::ostream& operator << (std::ostream &os, SExpr const &s) { - if(s.is_atom()) - os << s.atom(); - else if(s.is_list()){ - os << "("; - bool first = true; - for(auto &el: s.list()) { - if(!first) os << " "; - else first = false; - os << el; - } - os << ")"; - }else if(s.is_arg()) - os << "#" << s.arg().n; - else if(s.is_none()) - os << ""; - else - os << "???"; - return os; -} +struct SmtWriter { + std::ostream& stream; -struct SmtlibType { - bool _is_memory; - int _width; - int _addr_width; -public: - SmtlibType() : _is_memory(false), _width(0), _addr_width(0) { } - SmtlibType(int width) : _is_memory(false), _width(width), _addr_width(0) { } - SmtlibType(int addr_width, int data_width) : _is_memory(true), _width(data_width), _addr_width(addr_width) { } - static SmtlibType signal(int width) { return SmtlibType(width); } - static SmtlibType memory(int addr_width, int data_width) { return SmtlibType(addr_width, data_width); } - bool is_signal() const { return !_is_memory; } - bool is_memory() const { return _is_memory; } - int width() const { log_assert(is_signal()); return _width; } - int addr_width() const { log_assert(is_memory()); return _addr_width; } - int data_width() const { log_assert(is_memory()); return _width; } - SExpr to_sexpr() const { - if(_is_memory) { - return SExpr{ "Array", SExpr{ "_", "BitVec", addr_width() }, SExpr{ "_", "BitVec", data_width() }}; - } else { - return SExpr{ "_", "BitVec", width() }; - } - } - bool operator ==(SmtlibType const& other) const { - if(_is_memory != other._is_memory) return false; - if(_is_memory && _addr_width != other._addr_width) return false; - return _width == other._width; - } - unsigned int hash() const { - if(_is_memory) - return mkhash(1, mkhash(_width, _addr_width)); - else - return mkhash(0, _width); - } + SmtWriter(std::ostream& out) : stream(out) {} + + void print(const char* fmt, ...) { + va_list args; + va_start(args, fmt); + stream << vstringf(fmt, args); + va_end(args); + } }; -struct SmtlibStruct { - SmtlibScope &scope; - std::string name; - idict members; - vector types; - vector accessors; - SmtlibStruct(std::string name, SmtlibScope &scope) : scope(scope), name(name) { - } - std::string insert(IdString field, SmtlibType type) { - if(members.at(field, -1) == -1){ - members(field); - scope.insert(field); - types.push_back(type); - accessors.push_back(scope.insert(std::string("\\") + name + "_" + RTLIL::unescape_id(field))); - } - return scope[field]; - } - void print(SmtlibWriter &f) { - f.printf("(declare-datatype %s ((%s\n", name.c_str(), name.c_str()); - for (size_t i = 0; i < members.size(); i++) - f << " " << SExpr{accessors[i], types[i].to_sexpr()} << "\n"; - f.printf(")))\n"); - } - void print_value(SmtlibWriter &f, dict values, int indentation) { - std::string spaces(indentation, ' '); - f << spaces << "(" << name << "\n"; - for (size_t i = 0; i < members.size(); i++) - f << spaces << " " << values[members[i]] << " ; " << RTLIL::unescape_id(members[i]) << "\n"; - f << spaces << ")\n"; - } - SExpr access(SExpr record, IdString member) { - int i = members.at(member); - return SExpr{accessors[i], record}; - } - std::string operator[](IdString field) { - return scope[field]; - } -}; +template +struct SmtPrintVisitor { + using Node = FunctionalIR::Node; + NodeNames np; + SmtScope &scope; -struct Node { - SExpr expr; - SmtlibType type; + SmtPrintVisitor(NodeNames np, SmtScope &scope) + : np(np), scope(scope) {} - Node(SExpr &&expr, SmtlibType type) : expr(std::move(expr)), type(type) {} + template + std::string arg_to_string(T n) { return std::to_string(n); } - bool operator==(Node const &other) const { - return expr == other.expr && type == other.type; - } + std::string arg_to_string(std::string n) { return n; } - unsigned int hash() const { - return mkhash(expr.hash(), type.hash()); - } -}; + std::string arg_to_string(Node n) { return np(n); } -typedef ComputeGraph SmtlibComputeGraph; - -struct SmtlibModule { - std::string name; - SmtlibScope global_scope; - SmtlibStruct input_struct; - SmtlibStruct output_struct; - SmtlibStruct state_struct; - SmtlibComputeGraph compute_graph; - - SmtlibModule(std::string const &name) : - name(name), - input_struct(name + "_inputs", global_scope), - output_struct(name + "_outputs", global_scope), - state_struct(name + "_state", global_scope) - { } - void calculate_compute_graph(RTLIL::Module *module); - void write(std::ostream &stream); -}; - -class SmtlibComputeGraphFactory { - SmtlibModule &module; - SmtlibComputeGraph &graph; - using T = SmtlibComputeGraph::Ref; - static bool is_single_output(IdString type) - { - auto it = yosys_celltypes.cell_types.find(type); - return it != yosys_celltypes.cell_types.end() && it->second.outputs.size() <= 1; - } - T node(SExpr &&expr, SmtlibType type, std::initializer_list args) { - return graph.add(Node(std::move(expr), type), 0, args); - } - T shift(const char *name, T a, T b, int y_width, int b_width, bool a_signed = false) { - int width = max(y_width, b_width); - T a_ = y_width < width ? extend(a, y_width, width, a_signed) : a; - T b_ = b_width < width ? extend(b, b_width, width, false) : b; - T y_ = node(SExpr {name, Arg(1), Arg(2)}, width, {a_, b_}); - if(y_width < width) - return slice(y_, width, 0, y_width); - else - return y_; - } - SExpr from_bool(SExpr &&arg) { - return SExpr{"ite", std::move(arg), RTLIL::Const(State::S1), RTLIL::Const(State::S0)}; - } - SExpr to_bool(SExpr &&arg) { - return SExpr{"=", std::move(arg), RTLIL::Const(State::S1)}; - } - SExpr extract(SExpr &&arg, int offset, int out_width) { - return SExpr {SExpr {"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; - } -public: - SmtlibComputeGraphFactory(SmtlibModule &mod) : module(mod), graph(mod.compute_graph) {} - T slice(T a, int in_width, int offset, int out_width) { - log_assert(offset + out_width <= in_width); - return node(extract(Arg(1), offset, out_width), out_width, {a}); - } - T extend(T a, int in_width, int out_width, bool is_signed) { - log_assert(in_width < out_width); - if(is_signed) - return node(SExpr {SExpr {"_", "sign_extend", out_width - in_width}, Arg(1)}, out_width, {a}); - else - return node(SExpr {SExpr {"_", "zero_extend", out_width - in_width}, Arg(1)}, out_width, {a}); - } - T concat(T a, int a_width, T b, int b_width) { - return node(SExpr {"concat", Arg(1), Arg(2)}, a_width + b_width, {a, b}); - } - T add(T a, T b, int width) { return node(SExpr {"bvadd", Arg(1), Arg(2)}, width, {a, b}); } - T sub(T a, T b, int width) { return node(SExpr {"bvsub", Arg(1), Arg(2)}, width, {a, b}); } - T bitwise_and(T a, T b, int width) { return node(SExpr {"bvand", Arg(1), Arg(2)}, width, {a, b}); } - T bitwise_or(T a, T b, int width) { return node(SExpr {"bvor", Arg(1), Arg(2)}, width, {a, b}); } - T bitwise_xor(T a, T b, int width) { return node(SExpr {"bvxor", Arg(1), Arg(2)}, width, {a, b}); } - T bitwise_not(T a, int width) { return node(SExpr {"bvnot", Arg(1)}, width, {a}); } - T neg(T a, int width) { return node(SExpr {"bvneg", Arg(1)}, width, {a}); } - T mux(T a, T b, T s, int width) { return node(SExpr {"ite", to_bool(Arg(1)), Arg(2), Arg(3)}, width, {s, a, b}); } - T pmux(T a, T b, T s, int width, int s_width) { - T rv = a; - for(int i = 0; i < s_width; i++) - rv = node(SExpr {"ite", to_bool(extract(Arg(1), i, 1)), extract(Arg(2), width * i, width), Arg(3)}, width, {s, b, rv}); - return rv; - } - T reduce_and(T a, int width) { return node(from_bool(SExpr {"=", Arg(1), RTLIL::Const(State::S1, width)}), 1, {a}); } - T reduce_or(T a, int width) { return node(from_bool(SExpr {"distinct", Arg(1), RTLIL::Const(State::S0, width)}), 1, {a}); } - T reduce_xor(T a, int) { return node(SExpr {"reduce_xor", Arg(1)}, 1, {a}); } - T eq(T a, T b, int) { return node(from_bool(SExpr {"=", Arg(1), Arg(2)}), 1, {a, b}); } - T ne(T a, T b, int) { return node(from_bool(SExpr {"distinct", Arg(1), Arg(2)}), 1, {a, b}); } - T gt(T a, T b, int) { return node(from_bool(SExpr {"bvsgt", Arg(1), Arg(2)}), 1, {a, b}); } - T ge(T a, T b, int) { return node(from_bool(SExpr {"bvsge", Arg(1), Arg(2)}), 1, {a, b}); } - T ugt(T a, T b, int) { return node(from_bool(SExpr {"bvugt", Arg(1), Arg(2)}), 1, {a, b}); } - T uge(T a, T b, int) { return node(from_bool(SExpr {"bvuge", Arg(1), Arg(2)}), 1, {a, b}); } - T logical_shift_left(T a, T b, int y_width, int b_width) { return shift("bvshl", a, b, y_width, b_width); } - T logical_shift_right(T a, T b, int y_width, int b_width) { return shift("bvlshl", a, b, y_width, b_width); } - T arithmetic_shift_right(T a, T b, int y_width, int b_width) { return shift("bvashr", a, b, y_width, b_width, true); } - - T memory_read(T mem, T addr, int addr_width, int data_width) { - return node(SExpr {"select", Arg(1), Arg(2)}, data_width, {mem, addr}); - } - T memory_write(T mem, T addr, T data, int addr_width, int data_width) { - return node(SExpr {"store", Arg(1), Arg(2), Arg(3)}, SmtlibType::memory(addr_width, data_width), {mem, addr, data}); - } - - T constant(RTLIL::Const value) { return node(SExpr(value), value.size(), {}); } - T input(IdString name, int width) { - module.input_struct.insert(name, width); - return node(module.input_struct.access("inputs", name), width, {}); - } - T state(IdString name, int width) { - module.state_struct.insert(name, width); - return node(module.state_struct.access("current_state", name), width, {}); - } - T state_memory(IdString name, int addr_width, int data_width) { - module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width)); - return node(module.state_struct.access("current_state", name), SmtlibType::memory(addr_width, data_width), {}); - } - T cell_output(T cell, IdString type, IdString name, int width) { - if (is_single_output(type)) - return cell; - else - return node(SExpr {"cell_output", Arg(1), RTLIL::unescape_id(name)}, width, {cell}); - } - T multiple(vector args, int width) { - vector expr; - expr.reserve(args.size() + 1); - expr.push_back("multiple"); - for(size_t i = 1; i <= args.size(); i++) - expr.push_back(Arg(i)); - return graph.add(Node(SExpr(std::move(expr)), width), 0, args); - } - T undriven(int width) { - return constant(RTLIL::Const(State::S0, width)); - //return node(SExpr {"undriven"}, width, {}); - } - T create_pending(int width) { - return node(SExpr(), width, {}); - } - void update_pending(T pending, T node) { - log_assert(pending.function().expr.is_none()); - pending.set_function(Node(Arg(1), pending.function().type)); - pending.append_arg(node); - } - void declare_output(T node, IdString name, int width) { - module.output_struct.insert(name, width); - node.assign_key(name); - } - void declare_state(T node, IdString name, int width) { - module.state_struct.insert(name, width); - node.assign_key(name); - } - void declare_state_memory(T node, IdString name, int addr_width, int data_width) { - module.state_struct.insert(name, SmtlibType::memory(addr_width, data_width)); - node.assign_key(name); - } - void suggest_name(T node, IdString name) { - node.sparse_attr() = name; - } -}; - -void SmtlibModule::calculate_compute_graph(RTLIL::Module *module) -{ - SmtlibComputeGraphFactory factory(*this); - ComputeGraphConstruction construction(factory); - construction.add_module(module); - construction.process_queue(); - - // Perform topo sort and detect SCCs - SmtlibComputeGraph::SccAdaptor compute_graph_scc(compute_graph); - - bool scc = false; - std::vector perm; - topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { - perm.insert(perm.end(), begin, end); - if (end > begin + 1) - { - log_warning("SCC:"); - for (int *i = begin; i != end; ++i) - log(" %d", *i); - log("\n"); - scc = true; - } - }, /* sources_first */ true); - compute_graph.permute(perm); - if(scc) log_error("combinational loops, aborting\n"); - - // Forward $$buf - std::vector alias; - perm.clear(); - - for (int i = 0; i < compute_graph.size(); ++i) - { - auto node = compute_graph[i]; - if (node.function().expr == Arg(1) && node.arg(0).index() < i) - { - int target_index = alias[node.arg(0).index()]; - auto target_node = compute_graph[perm[target_index]]; - if(!target_node.has_sparse_attr() && node.has_sparse_attr()) - target_node.sparse_attr() = node.sparse_attr(); - alias.push_back(target_index); - } - else - { - alias.push_back(GetSize(perm)); - perm.push_back(i); - } - } - compute_graph.permute(perm, alias); -} - -void SmtlibModule::write(std::ostream &stream) -{ - SmtlibWriter f(stream); - - idict node_names; - SmtlibScope locals; - int paren_count = 0; - - input_struct.print(f); - output_struct.print(f); - state_struct.print(f); - - f << "(declare-datatypes ((Pair 2)) ((par (X Y) ((pair (first X) (second Y))))))\n"; - f.printf("(define-fun %s_step ((inputs %s_inputs) (current_state %s_state)) (Pair %s_outputs %s_state)\n", - name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); - - for (int i = 0; i < compute_graph.size(); ++i) - { - auto ref = compute_graph[i]; - std::string name; - if(ref.has_sparse_attr()) - name = locals.insert(ref.sparse_attr()); - else - name = locals.insert("\\n" + std::to_string(i)); - node_names(name); - vector args; - args.reserve(ref.size()); - for (int i = 0, end = ref.size(); i != end; ++i) - args.push_back(node_names[ref.arg(i).index()]); - f << " (let " << SExpr{{SExpr{name, ref.function().expr.subst_args(args)}}} << "\n"; - paren_count++; - } - dict outputs; - for(auto &a: compute_graph.keys()) - outputs.insert({a.first, node_names[a.second]}); - f.printf(" (pair \n"); - output_struct.print_value(f, outputs, 6); - state_struct.print_value(f, outputs, 6); - f.printf(" )\n"); - while(paren_count > 0){ - int n = min(paren_count, 80); - f << " " << std::string(n, ')') << "\n"; - paren_count -= n; - } - f.printf(")\n"); -} - -struct FunctionalSmtlibBackend : public Backend -{ - FunctionalSmtlibBackend() : Backend("functional_smtlib", "convert design to SMTLIB using the functional backend") {} - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); + template + std::string format(std::string fmt, Args&&... args) { + std::vector arg_strings = { arg_to_string(std::forward(args))... }; + for (size_t i = 0; i < arg_strings.size(); ++i) { + std::string placeholder = "%" + std::to_string(i); + size_t pos = 0; + while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { + fmt.replace(pos, placeholder.length(), arg_strings[i]); + pos += arg_strings[i].length(); + } } + return fmt; + } + std::string buf(Node, Node n) { return np(n); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Functional SMTLIB backend.\n"); + std::string slice(Node, Node a, int, int offset, int out_width) { + return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1); + } - size_t argidx = 1; - extra_args(f, filename, args, argidx, design); + std::string zero_extend(Node, Node a, int, int out_width) { + return format("((_ zero_extend %1) %0)", np(a), out_width); + } - for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); - SmtlibModule smt(RTLIL::unescape_id(module->name)); - smt.calculate_compute_graph(module); - smt.write(*f); - } - } -} FunctionalSmtlibBackend; + std::string sign_extend(Node, Node a, int, int out_width) { + return format("((_ sign_extend %1) %0)", np(a), out_width); + } + + std::string concat(Node, Node a, int, Node b, int) { + return format("(concat %0 %1)", np(a), np(b)); + } + + std::string add(Node, Node a, Node b, int) { + return format("(bvadd %0 %1)", np(a), np(b)); + } + + std::string sub(Node, Node a, Node b, int) { + return format("(bvsub %0 %1)", np(a), np(b)); + } + + std::string bitwise_and(Node, Node a, Node b, int) { + return format("(bvand %0 %1)", np(a), np(b)); + } + + std::string bitwise_or(Node, Node a, Node b, int) { + return format("(bvor %0 %1)", np(a), np(b)); + } + + std::string bitwise_xor(Node, Node a, Node b, int) { + return format("(bvxor %0 %1)", np(a), np(b)); + } + + std::string bitwise_not(Node, Node a, int) { + return format("(bvnot %0)", np(a)); + } + + std::string unary_minus(Node, Node a, int) { + return format("(bvneg %0)", np(a)); + } + + std::string reduce_and(Node, Node a, int) { + return format("(= %0 #b1)", np(a)); + } + + std::string reduce_or(Node, Node a, int) { + return format("(distinct %0 #b0)", np(a)); + } + + std::string reduce_xor(Node, Node a, int) { + return format("(bvxor_reduce %0)", np(a)); + } + + std::string equal(Node, Node a, Node b, int) { + return format("(= %0 %1)", np(a), np(b)); + } + + std::string not_equal(Node, Node a, Node b, int) { + return format("(distinct %0 %1)", np(a), np(b)); + } + + std::string signed_greater_than(Node, Node a, Node b, int) { + return format("(bvsgt %0 %1)", np(a), np(b)); + } + + std::string signed_greater_equal(Node, Node a, Node b, int) { + return format("(bvsge %0 %1)", np(a), np(b)); + } + + std::string unsigned_greater_than(Node, Node a, Node b, int) { + return format("(bvugt %0 %1)", np(a), np(b)); + } + + std::string unsigned_greater_equal(Node, Node a, Node b, int) { + return format("(bvuge %0 %1)", np(a), np(b)); + } + + std::string logical_shift_left(Node, Node a, Node b, int, int) { + return format("(bvshl %0 %1)", np(a), np(b)); + } + + std::string logical_shift_right(Node, Node a, Node b, int, int) { + return format("(bvlshr %0 %1)", np(a), np(b)); + } + + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { + return format("(bvashr %0 %1)", np(a), np(b)); + } + + std::string mux(Node, Node a, Node b, Node s, int) { + return format("(ite %2 %0 %1)", np(a), np(b), np(s)); + } + + std::string pmux(Node, Node a, Node b, Node s, int, int) { + // Assume s is a bit vector, combine a and b based on the selection bits + return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); + } + + std::string constant(Node, RTLIL::Const value) { + return format("#b%1", value.as_string()); + } + + std::string input(Node, IdString name) { + return format("%0", scope[name]); + } + + std::string state(Node, IdString name) { + return format("%0", scope[name]); + } + + std::string memory_read(Node, Node mem, Node addr, int, int) { + return format("(select %0 %1)", np(mem), np(addr)); + } + + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { + return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); + } + + std::string undriven(Node, int width) { + return format("#b%0", std::string(width, '0')); + } +}; +struct SmtModule { + std::string name; + SmtScope scope; + FunctionalIR ir; + + SmtModule(const std::string& module_name, FunctionalIR ir) + : name(module_name), ir(std::move(ir)) {} + + void write(std::ostream& out) { + SmtWriter writer(out); + + writer.print("(declare-fun %s () Bool)\n", name.c_str()); + + writer.print("(declare-datatypes () ((Inputs (mk_inputs"); + for (const auto& input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); + } + writer.print("))))\n"); + + writer.print("(declare-datatypes () ((Outputs (mk_outputs"); + for (const auto& output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); + } + writer.print("))))\n"); + + writer.print("(declare-fun state () (_ BitVec 1))\n"); + + writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str()); + + writer.print(" (let (\n"); + for (const auto& input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (%s inputs))\n", input_name.c_str(), input_name.c_str()); + } + writer.print(" )\n"); + + auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; + SmtPrintVisitor visitor(node_to_string, scope); + writer.print(" (let (\n"); + for (auto it = ir.begin(); it != ir.end(); ++it) { + const FunctionalIR::Node& node = *it; + + if (ir.inputs().count(node.name()) > 0) { + continue; + } + + std::string node_name = scope[node.name()]; + std::string node_expr = node.visit(visitor); + writer.print(" (%s %s)\n", node_name.c_str(), node_expr.c_str()); + } + writer.print(" )\n"); + + writer.print(" (let (\n"); + for (const auto& output : ir.outputs()) { + std::string output_name = scope[output.first]; + // writer.print(" (%s %s)\n", output_name.c_str(), scope[output_name].c_str()); + } + writer.print(" )\n"); + + writer.print(" (mk_outputs\n"); + for (const auto& output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" %s\n", output_name.c_str()); + } + writer.print(" )\n"); + writer.print(" )\n"); + writer.print(" )\n"); + writer.print(" )\n"); + writer.print(")\n"); + } +}; + +struct FunctionalSmtBackend : public Backend { + FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} + + void help() override { + log("\nFunctional SMT Backend.\n\n"); + } + + void execute(std::ostream*& f, std::string filename, std::vector args, RTLIL::Design* design) override { + log_header(design, "Executing Functional SMT Backend.\n"); + + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); + + for (auto module : design->selected_modules()) { + log("Processing module `%s`.\n", module->name.c_str()); + auto ir = FunctionalIR::from_module(module); + SmtModule smt(RTLIL::unescape_id(module->name), ir); + smt.write(*f); + } + } +} FunctionalSmtBackend; PRIVATE_NAMESPACE_END From 54225b5c4252778dc39ad0ef912a6ebaa7d99853 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 21 Jun 2024 12:59:45 +0200 Subject: [PATCH 102/342] Add test for SMT backend. Tests if SMT is valid and compares simulation with yosys sim --- tests/functional/single_cells/run-test_smt.sh | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100755 tests/functional/single_cells/run-test_smt.sh diff --git a/tests/functional/single_cells/run-test_smt.sh b/tests/functional/single_cells/run-test_smt.sh new file mode 100755 index 000000000..42e1a7c4b --- /dev/null +++ b/tests/functional/single_cells/run-test_smt.sh @@ -0,0 +1,91 @@ +#!/bin/bash + +# Initialize an array to store the names of failing RTLIL files and their failure types +declare -A failing_files +# Initialize an array to store the names of successful RTLIL files +declare -A successful_files + +# Function to run the test on a given RTLIL file +run_test() { + # Define the common variable for the relative path + BASE_PATH="../../../" + + local rtlil_file=$1 + + # Extract the base name without extension + local base_name=$(basename "$rtlil_file" .il) + + # Run yosys to process each RTLIL file + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then + echo "Yosys processed $rtlil_file successfully." + # Check that the smt file generated is valid + # Execute the Python script to create a VCD file from the SMT2 file + if z3 "${base_name}.smt2"; then + echo "SMT file ${base_name}.smt2 is valid ." + + if python3 using_smtio.py "${base_name}.smt2"; then + echo "Python script generated VCD file for $rtlil_file successfully." + + # Check if VCD file was generated successfully + if [ -f "${base_name}.smt2.vcd" ]; then + echo "VCD file ${base_name}.vcd generated successfully by Python." + + # Run yosys simulation to generate a reference VCD file + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then + echo "Yosys simulation for $rtlil_file completed successfully." + successful_files["$rtlil_file"]="Success" + else + echo "Yosys simulation failed for $rtlil_file." + failing_files["$rtlil_file"]="Yosys simulation failure" + fi + else + + echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " + failing_files["$rtlil_file"]="VCD generation failure" + fi + else + echo "Failed to run Python script for $rtlil_file." + failing_files["$rtlil_file"]="Python script failure" + fi + else + echo "SMT file for $rtlil_file is invalid" + failing_files["$rtlil_file"]="Invalid SMT" + fi + else + echo "Yosys failed to process $rtlil_file." + failing_files["$rtlil_file"]="Yosys failure" + fi +} + +# Main function to run all tests +run_all_tests() { + # Loop through all RTLIL files in the rtlil directory + for rtlil_file in rtlil/*.il; do + run_test "$rtlil_file" + done + + # Check if the array of failing files is empty + if [ ${#failing_files[@]} -eq 0 ]; then + echo "All files passed." + echo "The following files passed:" + for file in "${!successful_files[@]}"; do + echo "$file" + done + return 0 + else + echo "The following files failed:" + for file in "${!failing_files[@]}"]; do + echo "$file: ${failing_files[$file]}" +done +echo "The following files passed:" +for file in "${!successful_files[@]}"]; do + echo "$file" + done + return 1 + fi + } + + # If the script is being sourced, do not execute the tests + if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then + run_all_tests + fi From c6e112686ca93403847a144ded8eefceef674c42 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sun, 23 Jun 2024 22:13:31 +0200 Subject: [PATCH 103/342] Remove unused includes --- backends/functional/smtlib.cc | 5 ----- 1 file changed, 5 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index a24ab8401..65541d8d8 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -19,11 +19,6 @@ #include "kernel/yosys.h" #include "kernel/functionalir.h" -#include -#include -#include -#include -#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From 547c5466ecc74d593793ba30dde20fc941170a89 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 24 Jun 2024 02:40:32 +0200 Subject: [PATCH 104/342] Ignore smt2 files, generated by the execution of the tests --- tests/functional/.gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore index 543226b49..8b20fbedf 100644 --- a/tests/functional/.gitignore +++ b/tests/functional/.gitignore @@ -1,4 +1,5 @@ my_module_cxxrtl.cc my_module_functional_cxx.cc vcd_harness -*.vcd \ No newline at end of file +*.vcd +*.smt2 \ No newline at end of file From 71aaa1c80dcf1ac8c5a9836025d4859a60fe9bd7 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 24 Jun 2024 03:05:44 +0200 Subject: [PATCH 105/342] Consolidate tests scripts into one --- tests/functional/single_cells/run-test.sh | 120 +++++++++++++----- tests/functional/single_cells/run-test_smt.sh | 91 ------------- 2 files changed, 89 insertions(+), 122 deletions(-) delete mode 100755 tests/functional/single_cells/run-test_smt.sh diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 67cdf4a11..fd1b178e4 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -1,80 +1,138 @@ #!/bin/bash -# Initialize an array to store the names of failing RTLIL files and their failure types -declare -A failing_files -# Initialize an array to store the names of successful RTLIL files -declare -A successful_files +declare -A cxx_failing_files +declare -A smt_failing_files +declare -A cxx_successful_files +declare -A smt_successful_files -# Function to run the test on a given RTLIL file -run_test() { - # Define the common variable for the relative path +run_cxx_test() { BASE_PATH="../../../" local rtlil_file=$1 - # Extract the base name without extension local base_name=$(basename "$rtlil_file" .v) - # Run yosys to process each RTLIL file if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then echo "Yosys processed $rtlil_file successfully." - # Compile the generated C++ files with vcd_harness.cpp if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then echo "Compilation successful." - # Generate VCD files with base_name if ./vcd_harness ${base_name}_functional_cxx.vcd; then - # Run yosys to process each RTLIL file if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then echo "Yosys sim $rtlil_file successfully." - successful_files["$rtlil_file"]="Success" + cxx_successful_files["$rtlil_file"]="Success" else ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us" echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" - failing_files["$rtlil_file"]="Yosys sim failure" + cxx_failing_files["$rtlil_file"]="Yosys sim failure" fi else echo "Failed to generate VCD files for $rtlil_file." - failing_files["$rtlil_file"]="VCD generation failure" + cxx_failing_files["$rtlil_file"]="VCD generation failure" fi else echo "Failed to compile harness for $rtlil_file." - failing_files["$rtlil_file"]="Compilation failure" + cxx_failing_files["$rtlil_file"]="Compilation failure" fi else echo "Yosys failed to process $rtlil_file." - failing_files["$rtlil_file"]="Yosys failure" + cxx_failing_files["$rtlil_file"]="Yosys failure" fi } -# Main function to run all tests -run_all_tests() { - # Loop through all RTLIL files in the rtlil directory - for rtlil_file in rtlil/*.il; do - run_test "$rtlil_file" - done +run_smt_test() { + BASE_PATH="../../../" - # Check if the array of failing files is empty - if [ ${#failing_files[@]} -eq 0 ]; then + local rtlil_file=$1 + + local base_name=$(basename "$rtlil_file" .il) + + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then + echo "Yosys processed $rtlil_file successfully." + # TODO: which SMT solver should be run? + if z3 "${base_name}.smt2"; then + echo "SMT file ${base_name}.smt2 is valid ." + + if python3 using_smtio.py "${base_name}.smt2"; then + echo "Python script generated VCD file for $rtlil_file successfully." + + if [ -f "${base_name}.smt2.vcd" ]; then + echo "VCD file ${base_name}.vcd generated successfully by Python." + + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then + echo "Yosys simulation for $rtlil_file completed successfully." + smt_successful_files["$rtlil_file"]="Success" + else + echo "Yosys simulation failed for $rtlil_file." + smt_failing_files["$rtlil_file"]="Yosys simulation failure" + fi + else + + echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " + smt_failing_files["$rtlil_file"]="VCD generation failure" + fi + else + echo "Failed to run Python script for $rtlil_file." + smt_failing_files["$rtlil_file"]="Python script failure" + fi + else + echo "SMT file for $rtlil_file is invalid" + smt_failing_files["$rtlil_file"]="Invalid SMT" + fi + else + echo "Yosys failed to process $rtlil_file." + smt_failing_files["$rtlil_file"]="Yosys failure" + fi +} + + +run_all_tests() { + return_code=0 + for rtlil_file in rtlil/*.il; do + run_cxx_test "$rtlil_file" + run_smt_test "$rtlil_file" + done + + echo "C++ tests results:" + if [ ${#cxx_failing_files[@]} -eq 0 ]; then echo "All files passed." echo "The following files passed:" - for file in "${!successful_files[@]}"; do + for file in "${!cxx_successful_files[@]}"; do echo "$file" done - return 0 else echo "The following files failed:" - for file in "${!failing_files[@]}"; do - echo "$file: ${failing_files[$file]}" + for file in "${!cxx_failing_files[@]}"; do + echo "$file: ${cxx_failing_files[$file]}" done echo "The following files passed:" - for file in "${!successful_files[@]}"; do + for file in "${!cxx_successful_files[@]}"; do echo "$file" done - return 1 + return_code=1 fi + + echo "SMT tests results:" + if [ ${#smt_failing_files[@]} -eq 0 ]; then + echo "All files passed." + echo "The following files passed:" + for file in "${!smt_successful_files[@]}"; do + echo "$file" + done + else + echo "The following files failed:" + for file in "${!smt_failing_files[@]}"; do + echo "$file: ${smt_failing_files[$file]}" + done + echo "The following files passed:" + for file in "${!smt_successful_files[@]}"; do + echo "$file" + done + return_code=1 + fi + return $return_code } # If the script is being sourced, do not execute the tests diff --git a/tests/functional/single_cells/run-test_smt.sh b/tests/functional/single_cells/run-test_smt.sh deleted file mode 100755 index 42e1a7c4b..000000000 --- a/tests/functional/single_cells/run-test_smt.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/bash - -# Initialize an array to store the names of failing RTLIL files and their failure types -declare -A failing_files -# Initialize an array to store the names of successful RTLIL files -declare -A successful_files - -# Function to run the test on a given RTLIL file -run_test() { - # Define the common variable for the relative path - BASE_PATH="../../../" - - local rtlil_file=$1 - - # Extract the base name without extension - local base_name=$(basename "$rtlil_file" .il) - - # Run yosys to process each RTLIL file - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then - echo "Yosys processed $rtlil_file successfully." - # Check that the smt file generated is valid - # Execute the Python script to create a VCD file from the SMT2 file - if z3 "${base_name}.smt2"; then - echo "SMT file ${base_name}.smt2 is valid ." - - if python3 using_smtio.py "${base_name}.smt2"; then - echo "Python script generated VCD file for $rtlil_file successfully." - - # Check if VCD file was generated successfully - if [ -f "${base_name}.smt2.vcd" ]; then - echo "VCD file ${base_name}.vcd generated successfully by Python." - - # Run yosys simulation to generate a reference VCD file - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then - echo "Yosys simulation for $rtlil_file completed successfully." - successful_files["$rtlil_file"]="Success" - else - echo "Yosys simulation failed for $rtlil_file." - failing_files["$rtlil_file"]="Yosys simulation failure" - fi - else - - echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " - failing_files["$rtlil_file"]="VCD generation failure" - fi - else - echo "Failed to run Python script for $rtlil_file." - failing_files["$rtlil_file"]="Python script failure" - fi - else - echo "SMT file for $rtlil_file is invalid" - failing_files["$rtlil_file"]="Invalid SMT" - fi - else - echo "Yosys failed to process $rtlil_file." - failing_files["$rtlil_file"]="Yosys failure" - fi -} - -# Main function to run all tests -run_all_tests() { - # Loop through all RTLIL files in the rtlil directory - for rtlil_file in rtlil/*.il; do - run_test "$rtlil_file" - done - - # Check if the array of failing files is empty - if [ ${#failing_files[@]} -eq 0 ]; then - echo "All files passed." - echo "The following files passed:" - for file in "${!successful_files[@]}"; do - echo "$file" - done - return 0 - else - echo "The following files failed:" - for file in "${!failing_files[@]}"]; do - echo "$file: ${failing_files[$file]}" -done -echo "The following files passed:" -for file in "${!successful_files[@]}"]; do - echo "$file" - done - return 1 - fi - } - - # If the script is being sourced, do not execute the tests - if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then - run_all_tests - fi From b98210d8ac312497bd3523f5b5cc81f602487226 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 26 Jun 2024 19:13:53 +0200 Subject: [PATCH 106/342] Valid SMT is emitted, improved test script --- backends/functional/smtlib.cc | 59 +++++++++++++------- tests/functional/single_cells/run-test.sh | 67 ++++++++++++++++------- 2 files changed, 86 insertions(+), 40 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 65541d8d8..671b3a763 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -108,11 +108,11 @@ struct SmtPrintVisitor { } std::string zero_extend(Node, Node a, int, int out_width) { - return format("((_ zero_extend %1) %0)", np(a), out_width); + return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); } std::string sign_extend(Node, Node a, int, int out_width) { - return format("((_ sign_extend %1) %0)", np(a), out_width); + return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); } std::string concat(Node, Node a, int, Node b, int) { @@ -228,6 +228,7 @@ struct SmtPrintVisitor { return format("#b%0", std::string(width, '0')); } }; + struct SmtModule { std::string name; SmtScope scope; @@ -236,11 +237,24 @@ struct SmtModule { SmtModule(const std::string& module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} + std::string replaceCharacters(const std::string& input) { + std::string result = input; + std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _ + + // Since \ is an escape character, we use a loop to replace it + size_t pos = 0; + while ((pos = result.find('\\', pos)) != std::string::npos) { + result.replace(pos, 1, "_"); + pos += 1; // Move past the replaced character + } + + return result; + } + void write(std::ostream& out) { SmtWriter writer(out); - + writer.print("(declare-fun %s () Bool)\n", name.c_str()); - writer.print("(declare-datatypes () ((Inputs (mk_inputs"); for (const auto& input : ir.inputs()) { std::string input_name = scope[input.first]; @@ -258,7 +272,6 @@ struct SmtModule { writer.print("(declare-fun state () (_ BitVec 1))\n"); writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str()); - writer.print(" (let (\n"); for (const auto& input : ir.inputs()) { std::string input_name = scope[input.first]; @@ -268,35 +281,41 @@ struct SmtModule { auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; SmtPrintVisitor visitor(node_to_string, scope); - writer.print(" (let (\n"); + + std::string nested_lets; for (auto it = ir.begin(); it != ir.end(); ++it) { const FunctionalIR::Node& node = *it; - if (ir.inputs().count(node.name()) > 0) { - continue; - } + if (ir.inputs().count(node.name()) > 0) continue; - std::string node_name = scope[node.name()]; + std::string node_name = replaceCharacters(scope[node.name()]); std::string node_expr = node.visit(visitor); - writer.print(" (%s %s)\n", node_name.c_str(), node_expr.c_str()); + + nested_lets += "(let (\n (" + node_name + " " + node_expr + "))\n"; } - writer.print(" )\n"); - writer.print(" (let (\n"); + nested_lets += " (let (\n"; for (const auto& output : ir.outputs()) { std::string output_name = scope[output.first]; - // writer.print(" (%s %s)\n", output_name.c_str(), scope[output_name].c_str()); + const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); + nested_lets += " (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")\n"; } - writer.print(" )\n"); + nested_lets += " )\n"; + nested_lets += " (mk_outputs\n"; - writer.print(" (mk_outputs\n"); for (const auto& output : ir.outputs()) { std::string output_name = scope[output.first]; - writer.print(" %s\n", output_name.c_str()); + nested_lets += " " + output_name + "\n"; } - writer.print(" )\n"); - writer.print(" )\n"); - writer.print(" )\n"); + nested_lets += " )\n"; + nested_lets += " )\n"; + + // Close the nested lets + for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { + nested_lets += " )\n"; + } + + writer.print("%s", nested_lets.c_str()); writer.print(" )\n"); writer.print(")\n"); } diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index fd1b178e4..473c7faea 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -54,29 +54,29 @@ run_smt_test() { # TODO: which SMT solver should be run? if z3 "${base_name}.smt2"; then echo "SMT file ${base_name}.smt2 is valid ." + smt_successful_files["$rtlil_file"]="Success" + # if python3 using_smtio.py "${base_name}.smt2"; then + # echo "Python script generated VCD file for $rtlil_file successfully." - if python3 using_smtio.py "${base_name}.smt2"; then - echo "Python script generated VCD file for $rtlil_file successfully." + # if [ -f "${base_name}.smt2.vcd" ]; then + # echo "VCD file ${base_name}.vcd generated successfully by Python." - if [ -f "${base_name}.smt2.vcd" ]; then - echo "VCD file ${base_name}.vcd generated successfully by Python." - - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then - echo "Yosys simulation for $rtlil_file completed successfully." - smt_successful_files["$rtlil_file"]="Success" - else - echo "Yosys simulation failed for $rtlil_file." - smt_failing_files["$rtlil_file"]="Yosys simulation failure" - fi - else + # if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then + # echo "Yosys simulation for $rtlil_file completed successfully." + # smt_successful_files["$rtlil_file"]="Success" + # else + # echo "Yosys simulation failed for $rtlil_file." + # smt_failing_files["$rtlil_file"]="Yosys simulation failure" + # fi + # else - echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " - smt_failing_files["$rtlil_file"]="VCD generation failure" - fi - else - echo "Failed to run Python script for $rtlil_file." - smt_failing_files["$rtlil_file"]="Python script failure" - fi + # echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " + # smt_failing_files["$rtlil_file"]="VCD generation failure" + # fi + # else + # echo "Failed to run Python script for $rtlil_file." + # smt_failing_files["$rtlil_file"]="Python script failure" + # fi else echo "SMT file for $rtlil_file is invalid" smt_failing_files["$rtlil_file"]="Invalid SMT" @@ -135,6 +135,33 @@ run_all_tests() { return $return_code } +run_smt_tests() { + return_code=0 + for rtlil_file in rtlil/*.il; do + run_smt_test "$rtlil_file" + done + + echo "SMT tests results:" + if [ ${#smt_failing_files[@]} -eq 0 ]; then + echo "All files passed." + echo "The following files passed:" + for file in "${!smt_successful_files[@]}"; do + echo "$file" + done + else + echo "The following files failed:" + for file in "${!smt_failing_files[@]}"; do + echo "$file: ${smt_failing_files[$file]}" + done + echo "The following files passed:" + for file in "${!smt_successful_files[@]}"; do + echo "$file" + done + return_code=1 + fi + return $return_code +} + # If the script is being sourced, do not execute the tests if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then run_all_tests From 94ddbc957727b6a71064a608a869405d49eb9dcb Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 26 Jun 2024 19:45:54 +0200 Subject: [PATCH 107/342] Fix reduce_or --- backends/functional/smtlib.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 671b3a763..2ece98d89 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -152,7 +152,10 @@ struct SmtPrintVisitor { } std::string reduce_or(Node, Node a, int) { - return format("(distinct %0 #b0)", np(a)); + std::stringstream ss; + // We use ite to set the result to bit vector, to ensure appropriate type + ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; + return ss.str(); } std::string reduce_xor(Node, Node a, int) { From 4109fcedcff1161b2c9a67d6651fdf416cb22e47 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 26 Jun 2024 20:56:29 +0200 Subject: [PATCH 108/342] clang-format smtlib.cc --- backends/functional/smtlib.cc | 452 +++++++++++++++------------------- 1 file changed, 199 insertions(+), 253 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 2ece98d89..49dd5cf0d 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -17,333 +17,279 @@ * */ -#include "kernel/yosys.h" #include "kernel/functionalir.h" +#include "kernel/yosys.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SmtScope { - pool used_names; - dict name_map; + pool used_names; + dict name_map; - SmtScope() {} - - void reserve(const std::string& name) { - used_names.insert(name); - } + SmtScope() {} - std::string insert(IdString id) { - std::string name = RTLIL::unescape_id(id); - if (used_names.count(name) == 0) { - used_names.insert(name); - name_map[id] = name; - return name; - } - for (int idx = 0;; ++idx) { - std::string new_name = name + "_" + std::to_string(idx); - if (used_names.count(new_name) == 0) { - used_names.insert(new_name); - name_map[id] = new_name; - return new_name; - } - } - } + void reserve(const std::string &name) { used_names.insert(name); } - std::string operator[](IdString id) { - if (name_map.count(id)) { - return name_map[id]; - } else { - return insert(id); - } - } + std::string insert(IdString id) + { + std::string name = RTLIL::unescape_id(id); + if (used_names.count(name) == 0) { + used_names.insert(name); + name_map[id] = name; + return name; + } + for (int idx = 0;; ++idx) { + std::string new_name = name + "_" + std::to_string(idx); + if (used_names.count(new_name) == 0) { + used_names.insert(new_name); + name_map[id] = new_name; + return new_name; + } + } + } + + std::string operator[](IdString id) + { + if (name_map.count(id)) { + return name_map[id]; + } else { + return insert(id); + } + } }; struct SmtWriter { - std::ostream& stream; + std::ostream &stream; - SmtWriter(std::ostream& out) : stream(out) {} + SmtWriter(std::ostream &out) : stream(out) {} - void print(const char* fmt, ...) { - va_list args; - va_start(args, fmt); - stream << vstringf(fmt, args); - va_end(args); - } + void print(const char *fmt, ...) + { + va_list args; + va_start(args, fmt); + stream << vstringf(fmt, args); + va_end(args); + } }; -template -struct SmtPrintVisitor { - using Node = FunctionalIR::Node; - NodeNames np; - SmtScope &scope; +template struct SmtPrintVisitor { + using Node = FunctionalIR::Node; + NodeNames np; + SmtScope &scope; - SmtPrintVisitor(NodeNames np, SmtScope &scope) - : np(np), scope(scope) {} + SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {} - template - std::string arg_to_string(T n) { return std::to_string(n); } + template std::string arg_to_string(T n) { return std::to_string(n); } - std::string arg_to_string(std::string n) { return n; } + std::string arg_to_string(std::string n) { return n; } - std::string arg_to_string(Node n) { return np(n); } + std::string arg_to_string(Node n) { return np(n); } - template - std::string format(std::string fmt, Args&&... args) { - std::vector arg_strings = { arg_to_string(std::forward(args))... }; - for (size_t i = 0; i < arg_strings.size(); ++i) { - std::string placeholder = "%" + std::to_string(i); - size_t pos = 0; - while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { - fmt.replace(pos, placeholder.length(), arg_strings[i]); - pos += arg_strings[i].length(); - } - } - return fmt; - } - std::string buf(Node, Node n) { return np(n); } + template std::string format(std::string fmt, Args &&...args) + { + std::vector arg_strings = {arg_to_string(std::forward(args))...}; + for (size_t i = 0; i < arg_strings.size(); ++i) { + std::string placeholder = "%" + std::to_string(i); + size_t pos = 0; + while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { + fmt.replace(pos, placeholder.length(), arg_strings[i]); + pos += arg_strings[i].length(); + } + } + return fmt; + } + std::string buf(Node, Node n) { return np(n); } - std::string slice(Node, Node a, int, int offset, int out_width) { - return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1); - } + std::string slice(Node, Node a, int, int offset, int out_width) + { + return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1); + } - std::string zero_extend(Node, Node a, int, int out_width) { - return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); - } + std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); } - std::string sign_extend(Node, Node a, int, int out_width) { - return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); - } + std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); } - std::string concat(Node, Node a, int, Node b, int) { - return format("(concat %0 %1)", np(a), np(b)); - } + std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); } - std::string add(Node, Node a, Node b, int) { - return format("(bvadd %0 %1)", np(a), np(b)); - } + std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); } - std::string sub(Node, Node a, Node b, int) { - return format("(bvsub %0 %1)", np(a), np(b)); - } + std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); } - std::string bitwise_and(Node, Node a, Node b, int) { - return format("(bvand %0 %1)", np(a), np(b)); - } + std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); } - std::string bitwise_or(Node, Node a, Node b, int) { - return format("(bvor %0 %1)", np(a), np(b)); - } + std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); } - std::string bitwise_xor(Node, Node a, Node b, int) { - return format("(bvxor %0 %1)", np(a), np(b)); - } + std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); } - std::string bitwise_not(Node, Node a, int) { - return format("(bvnot %0)", np(a)); - } + std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); } - std::string unary_minus(Node, Node a, int) { - return format("(bvneg %0)", np(a)); - } + std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); } - std::string reduce_and(Node, Node a, int) { - return format("(= %0 #b1)", np(a)); - } + std::string reduce_and(Node, Node a, int) { return format("(= %0 #b1)", np(a)); } - std::string reduce_or(Node, Node a, int) { - std::stringstream ss; - // We use ite to set the result to bit vector, to ensure appropriate type - ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; - return ss.str(); - } + std::string reduce_or(Node, Node a, int) + { + std::stringstream ss; + // We use ite to set the result to bit vector, to ensure appropriate type + ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; + return ss.str(); + } - std::string reduce_xor(Node, Node a, int) { - return format("(bvxor_reduce %0)", np(a)); - } + std::string reduce_xor(Node, Node a, int) { return format("(bvxor_reduce %0)", np(a)); } - std::string equal(Node, Node a, Node b, int) { - return format("(= %0 %1)", np(a), np(b)); - } + std::string equal(Node, Node a, Node b, int) { return format("(= %0 %1)", np(a), np(b)); } - std::string not_equal(Node, Node a, Node b, int) { - return format("(distinct %0 %1)", np(a), np(b)); - } + std::string not_equal(Node, Node a, Node b, int) { return format("(distinct %0 %1)", np(a), np(b)); } - std::string signed_greater_than(Node, Node a, Node b, int) { - return format("(bvsgt %0 %1)", np(a), np(b)); - } + std::string signed_greater_than(Node, Node a, Node b, int) { return format("(bvsgt %0 %1)", np(a), np(b)); } - std::string signed_greater_equal(Node, Node a, Node b, int) { - return format("(bvsge %0 %1)", np(a), np(b)); - } + std::string signed_greater_equal(Node, Node a, Node b, int) { return format("(bvsge %0 %1)", np(a), np(b)); } - std::string unsigned_greater_than(Node, Node a, Node b, int) { - return format("(bvugt %0 %1)", np(a), np(b)); - } + std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("(bvugt %0 %1)", np(a), np(b)); } - std::string unsigned_greater_equal(Node, Node a, Node b, int) { - return format("(bvuge %0 %1)", np(a), np(b)); - } + std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("(bvuge %0 %1)", np(a), np(b)); } - std::string logical_shift_left(Node, Node a, Node b, int, int) { - return format("(bvshl %0 %1)", np(a), np(b)); - } + std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("(bvshl %0 %1)", np(a), np(b)); } - std::string logical_shift_right(Node, Node a, Node b, int, int) { - return format("(bvlshr %0 %1)", np(a), np(b)); - } + std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("(bvlshr %0 %1)", np(a), np(b)); } - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { - return format("(bvashr %0 %1)", np(a), np(b)); - } + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("(bvashr %0 %1)", np(a), np(b)); } - std::string mux(Node, Node a, Node b, Node s, int) { - return format("(ite %2 %0 %1)", np(a), np(b), np(s)); - } + std::string mux(Node, Node a, Node b, Node s, int) { return format("(ite %2 %0 %1)", np(a), np(b), np(s)); } - std::string pmux(Node, Node a, Node b, Node s, int, int) { - // Assume s is a bit vector, combine a and b based on the selection bits - return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); - } + std::string pmux(Node, Node a, Node b, Node s, int, int) + { + // Assume s is a bit vector, combine a and b based on the selection bits + return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); + } - std::string constant(Node, RTLIL::Const value) { - return format("#b%1", value.as_string()); - } + std::string constant(Node, RTLIL::Const value) { return format("#b%1", value.as_string()); } - std::string input(Node, IdString name) { - return format("%0", scope[name]); - } + std::string input(Node, IdString name) { return format("%0", scope[name]); } - std::string state(Node, IdString name) { - return format("%0", scope[name]); - } + std::string state(Node, IdString name) { return format("%0", scope[name]); } - std::string memory_read(Node, Node mem, Node addr, int, int) { - return format("(select %0 %1)", np(mem), np(addr)); - } + std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { - return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); - } + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); } - std::string undriven(Node, int width) { - return format("#b%0", std::string(width, '0')); - } + std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); } }; struct SmtModule { - std::string name; - SmtScope scope; - FunctionalIR ir; + std::string name; + SmtScope scope; + FunctionalIR ir; - SmtModule(const std::string& module_name, FunctionalIR ir) - : name(module_name), ir(std::move(ir)) {} + SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} - std::string replaceCharacters(const std::string& input) { - std::string result = input; - std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _ - - // Since \ is an escape character, we use a loop to replace it - size_t pos = 0; - while ((pos = result.find('\\', pos)) != std::string::npos) { - result.replace(pos, 1, "_"); - pos += 1; // Move past the replaced character - } - - return result; - } - - void write(std::ostream& out) { - SmtWriter writer(out); - - writer.print("(declare-fun %s () Bool)\n", name.c_str()); - writer.print("(declare-datatypes () ((Inputs (mk_inputs"); - for (const auto& input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); - } - writer.print("))))\n"); + std::string replaceCharacters(const std::string &input) + { + std::string result = input; + std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _ - writer.print("(declare-datatypes () ((Outputs (mk_outputs"); - for (const auto& output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); - } - writer.print("))))\n"); + // Since \ is an escape character, we use a loop to replace it + size_t pos = 0; + while ((pos = result.find('\\', pos)) != std::string::npos) { + result.replace(pos, 1, "_"); + pos += 1; // Move past the replaced character + } - writer.print("(declare-fun state () (_ BitVec 1))\n"); + return result; + } - writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs\n", name.c_str()); - writer.print(" (let (\n"); - for (const auto& input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (%s inputs))\n", input_name.c_str(), input_name.c_str()); - } - writer.print(" )\n"); + void write(std::ostream &out) + { + SmtWriter writer(out); - auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; - SmtPrintVisitor visitor(node_to_string, scope); + writer.print("(declare-fun %s () Bool)\n", name.c_str()); + writer.print("(declare-datatypes () ((Inputs (mk_inputs"); + for (const auto &input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); + } + writer.print("))))\n"); - std::string nested_lets; - for (auto it = ir.begin(); it != ir.end(); ++it) { - const FunctionalIR::Node& node = *it; + writer.print("(declare-datatypes () ((Outputs (mk_outputs"); + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); + } + writer.print("))))\n"); - if (ir.inputs().count(node.name()) > 0) continue; - - std::string node_name = replaceCharacters(scope[node.name()]); - std::string node_expr = node.visit(visitor); - - nested_lets += "(let (\n (" + node_name + " " + node_expr + "))\n"; - } + writer.print("(declare-fun state () (_ BitVec 1))\n"); - nested_lets += " (let (\n"; - for (const auto& output : ir.outputs()) { - std::string output_name = scope[output.first]; - const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); - nested_lets += " (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")\n"; - } - nested_lets += " )\n"; - nested_lets += " (mk_outputs\n"; + writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs", name.c_str()); + writer.print(" (let ("); + for (const auto &input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str()); + } + writer.print(" )"); - for (const auto& output : ir.outputs()) { - std::string output_name = scope[output.first]; - nested_lets += " " + output_name + "\n"; - } - nested_lets += " )\n"; - nested_lets += " )\n"; + auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; + SmtPrintVisitor visitor(node_to_string, scope); - // Close the nested lets - for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { - nested_lets += " )\n"; - } + std::string nested_lets; + for (auto it = ir.begin(); it != ir.end(); ++it) { + const FunctionalIR::Node &node = *it; - writer.print("%s", nested_lets.c_str()); - writer.print(" )\n"); - writer.print(")\n"); - } + if (ir.inputs().count(node.name()) > 0) + continue; + + std::string node_name = replaceCharacters(scope[node.name()]); + std::string node_expr = node.visit(visitor); + + nested_lets += "(let ( (" + node_name + " " + node_expr + "))"; + } + + nested_lets += " (let ("; + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); + nested_lets += " (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")"; + } + nested_lets += " )"; + nested_lets += " (mk_outputs"; + + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + nested_lets += " " + output_name; + } + nested_lets += " )"; + nested_lets += " )"; + + // Close the nested lets + for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { + nested_lets += " )"; + } + + writer.print("%s", nested_lets.c_str()); + writer.print(" )"); + writer.print(")\n"); + } }; struct FunctionalSmtBackend : public Backend { - FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} + FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} - void help() override { - log("\nFunctional SMT Backend.\n\n"); - } + void help() override { log("\nFunctional SMT Backend.\n\n"); } - void execute(std::ostream*& f, std::string filename, std::vector args, RTLIL::Design* design) override { - log_header(design, "Executing Functional SMT Backend.\n"); + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional SMT Backend.\n"); - size_t argidx = 1; - extra_args(f, filename, args, argidx, design); + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); - for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); - auto ir = FunctionalIR::from_module(module); - SmtModule smt(RTLIL::unescape_id(module->name), ir); - smt.write(*f); - } - } + for (auto module : design->selected_modules()) { + log("Processing module `%s`.\n", module->name.c_str()); + auto ir = FunctionalIR::from_module(module); + SmtModule smt(RTLIL::unescape_id(module->name), ir); + smt.write(*f); + } + } } FunctionalSmtBackend; PRIVATE_NAMESPACE_END From 39bf4f04f73ef0f91fc793d277b64047a82e4ea9 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 27 Jun 2024 01:46:10 +0200 Subject: [PATCH 109/342] Create VCD file from SMT file --- backends/functional/smtio.py | 1331 +++++++++++++++++ tests/functional/single_cells/run-test.sh | 39 +- .../single_cells/vcd_harness_smt.py | 199 +++ 3 files changed, 1549 insertions(+), 20 deletions(-) create mode 100644 backends/functional/smtio.py create mode 100644 tests/functional/single_cells/vcd_harness_smt.py diff --git a/backends/functional/smtio.py b/backends/functional/smtio.py new file mode 100644 index 000000000..e32f43c60 --- /dev/null +++ b/backends/functional/smtio.py @@ -0,0 +1,1331 @@ +# +# yosys -- Yosys Open SYnthesis Suite +# +# Copyright (C) 2012 Claire Xenia Wolf +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# + +import sys, re, os, signal, json +import subprocess +if os.name == "posix": + import resource +from copy import copy +from select import select +from time import time +from queue import Queue, Empty +from threading import Thread + + +# This is needed so that the recursive SMT2 S-expression parser +# does not run out of stack frames when parsing large expressions +if os.name == "posix": + smtio_reclimit = 64 * 1024 + if sys.getrecursionlimit() < smtio_reclimit: + sys.setrecursionlimit(smtio_reclimit) + + current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK) + if current_rlimit_stack[0] != resource.RLIM_INFINITY: + smtio_stacksize = 128 * 1024 * 1024 + if os.uname().sysname == "Darwin": + # MacOS has rather conservative stack limits + smtio_stacksize = 8 * 1024 * 1024 + if current_rlimit_stack[1] != resource.RLIM_INFINITY: + smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1]) + if current_rlimit_stack[0] < smtio_stacksize: + try: + resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, current_rlimit_stack[1])) + except ValueError: + # couldn't get more stack, just run with what we have + pass + + +# currently running solvers (so we can kill them) +running_solvers = dict() +forced_shutdown = False +solvers_index = 0 + +def force_shutdown(signum, frame): + global forced_shutdown + if not forced_shutdown: + forced_shutdown = True + if signum is not None: + print("<%s>" % signal.Signals(signum).name) + for p in running_solvers.values(): + # os.killpg(os.getpgid(p.pid), signal.SIGTERM) + os.kill(p.pid, signal.SIGTERM) + sys.exit(1) + +if os.name == "posix": + signal.signal(signal.SIGHUP, force_shutdown) +signal.signal(signal.SIGINT, force_shutdown) +signal.signal(signal.SIGTERM, force_shutdown) + +def except_hook(exctype, value, traceback): + if not forced_shutdown: + sys.__excepthook__(exctype, value, traceback) + force_shutdown(None, None) + +sys.excepthook = except_hook + + +def recursion_helper(iteration, *request): + stack = [iteration(*request)] + + while stack: + top = stack.pop() + try: + request = next(top) + except StopIteration: + continue + + stack.append(top) + stack.append(iteration(*request)) + + +hex_dict = { + "0": "0000", "1": "0001", "2": "0010", "3": "0011", + "4": "0100", "5": "0101", "6": "0110", "7": "0111", + "8": "1000", "9": "1001", "A": "1010", "B": "1011", + "C": "1100", "D": "1101", "E": "1110", "F": "1111", + "a": "1010", "b": "1011", "c": "1100", "d": "1101", + "e": "1110", "f": "1111" +} + + +class SmtModInfo: + def __init__(self): + self.inputs = set() + self.outputs = set() + self.registers = set() + self.memories = dict() + self.wires = set() + self.wsize = dict() + self.clocks = dict() + self.cells = dict() + self.asserts = dict() + self.assumes = dict() + self.covers = dict() + self.maximize = set() + self.minimize = set() + self.anyconsts = dict() + self.anyseqs = dict() + self.allconsts = dict() + self.allseqs = dict() + self.asize = dict() + self.witness = [] + + +class SmtIo: + def __init__(self, opts=None): + global solvers_index + + self.logic = None + self.logic_qf = True + self.logic_ax = True + self.logic_uf = True + self.logic_bv = True + self.logic_dt = False + self.forall = False + self.timeout = 0 + self.produce_models = True + self.recheck = False + self.smt2cache = [list()] + self.smt2_options = dict() + self.smt2_assumptions = dict() + self.p = None + self.p_index = solvers_index + solvers_index += 1 + + if opts is not None: + self.logic = opts.logic + self.solver = opts.solver + self.solver_opts = opts.solver_opts + self.debug_print = opts.debug_print + self.debug_file = opts.debug_file + self.dummy_file = opts.dummy_file + self.timeinfo = opts.timeinfo + self.timeout = opts.timeout + self.unroll = opts.unroll + self.noincr = opts.noincr + self.info_stmts = opts.info_stmts + self.nocomments = opts.nocomments + + else: + self.solver = "yices" + self.solver_opts = list() + self.debug_print = False + self.debug_file = None + self.dummy_file = None + self.timeinfo = os.name != "nt" + self.timeout = 0 + self.unroll = False + self.noincr = False + self.info_stmts = list() + self.nocomments = False + + self.start_time = time() + + self.modinfo = dict() + self.curmod = None + self.topmod = None + self.setup_done = False + + def __del__(self): + if self.p is not None and not forced_shutdown: + os.killpg(os.getpgid(self.p.pid), signal.SIGTERM) + if running_solvers is not None: + del running_solvers[self.p_index] + + def setup(self): + assert not self.setup_done + + if self.forall: + self.unroll = False + + if self.solver == "yices": + if self.forall: + self.noincr = True + + if self.noincr: + self.popen_vargs = ['yices-smt2'] + self.solver_opts + else: + self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts + if self.timeout != 0: + self.popen_vargs.append('-t') + self.popen_vargs.append('%d' % self.timeout); + + if self.solver == "z3": + self.popen_vargs = ['z3', '-smt2', '-in'] + self.solver_opts + if self.timeout != 0: + self.popen_vargs.append('-T:%d' % self.timeout); + + if self.solver in ["cvc4", "cvc5"]: + self.recheck = True + if self.noincr: + self.popen_vargs = [self.solver, '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts + else: + self.popen_vargs = [self.solver, '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts + if self.timeout != 0: + self.popen_vargs.append('--tlimit=%d000' % self.timeout); + + if self.solver == "mathsat": + self.popen_vargs = ['mathsat'] + self.solver_opts + if self.timeout != 0: + print('timeout option is not supported for mathsat.') + sys.exit(1) + + if self.solver in ["boolector", "bitwuzla"]: + if self.noincr: + self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts + else: + self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts + self.unroll = True + if self.timeout != 0: + print('timeout option is not supported for %s.' % self.solver) + sys.exit(1) + + if self.solver == "abc": + if len(self.solver_opts) > 0: + self.popen_vargs = ['yosys-abc', '-S', '; '.join(self.solver_opts)] + else: + self.popen_vargs = ['yosys-abc', '-S', '%blast; &sweep -C 5000; &syn4; &cec -s -m -C 2000'] + self.logic_ax = False + self.unroll = True + self.noincr = True + if self.timeout != 0: + print('timeout option is not supported for abc.') + sys.exit(1) + + if self.solver == "dummy": + assert self.dummy_file is not None + self.dummy_fd = open(self.dummy_file, "r") + else: + if self.dummy_file is not None: + self.dummy_fd = open(self.dummy_file, "w") + if not self.noincr: + self.p_open() + + if self.unroll: + assert not self.forall + self.logic_uf = False + self.unroll_idcnt = 0 + self.unroll_buffer = "" + self.unroll_level = 0 + self.unroll_sorts = set() + self.unroll_objs = set() + self.unroll_decls = dict() + self.unroll_cache = dict() + self.unroll_stack = list() + + if self.logic is None: + self.logic = "" + if self.logic_qf: self.logic += "QF_" + if self.logic_ax: self.logic += "A" + if self.logic_uf: self.logic += "UF" + if self.logic_bv: self.logic += "BV" + if self.logic_dt: self.logic = "ALL" + if self.solver == "yices" and self.forall: self.logic = "BV" + + self.setup_done = True + + for stmt in self.info_stmts: + self.write(stmt) + + if self.produce_models: + self.write("(set-option :produce-models true)") + + #See the SMT-LIB Standard, Section 4.1.7 + modestart_options = [":global-declarations", ":interactive-mode", ":produce-assertions", ":produce-assignments", ":produce-models", ":produce-proofs", ":produce-unsat-assumptions", ":produce-unsat-cores", ":random-seed"] + for key, val in self.smt2_options.items(): + if key in modestart_options: + self.write("(set-option {} {})".format(key, val)) + + self.write("(set-logic %s)" % self.logic) + + if self.forall and self.solver == "yices": + self.write("(set-option :yices-ef-max-iters 1000000000)") + + for key, val in self.smt2_options.items(): + if key not in modestart_options: + self.write("(set-option {} {})".format(key, val)) + + def timestamp(self): + secs = int(time() - self.start_time) + return "## %3d:%02d:%02d " % (secs // (60*60), (secs // 60) % 60, secs % 60) + + def replace_in_stmt(self, stmt, pat, repl): + if stmt == pat: + return repl + + if isinstance(stmt, list): + return [self.replace_in_stmt(s, pat, repl) for s in stmt] + + return stmt + + def unroll_stmt(self, stmt): + result = [] + recursion_helper(self._unroll_stmt_into, stmt, result) + return result.pop() + + def _unroll_stmt_into(self, stmt, output, depth=128): + if not isinstance(stmt, list): + output.append(stmt) + return + + new_stmt = [] + for s in stmt: + if depth: + yield from self._unroll_stmt_into(s, new_stmt, depth - 1) + else: + yield s, new_stmt + stmt = new_stmt + + if len(stmt) >= 2 and not isinstance(stmt[0], list) and stmt[0] in self.unroll_decls: + assert stmt[1] in self.unroll_objs + + key = tuple(stmt) + if key not in self.unroll_cache: + decl = copy(self.unroll_decls[key[0]]) + + self.unroll_cache[key] = "|UNROLL#%d|" % self.unroll_idcnt + decl[1] = self.unroll_cache[key] + self.unroll_idcnt += 1 + + if decl[0] == "declare-fun": + if isinstance(decl[3], list) or decl[3] not in self.unroll_sorts: + self.unroll_objs.add(decl[1]) + decl[2] = list() + else: + self.unroll_objs.add(decl[1]) + decl = list() + + elif decl[0] == "define-fun": + arg_index = 1 + for arg_name, arg_sort in decl[2]: + decl[4] = self.replace_in_stmt(decl[4], arg_name, key[arg_index]) + arg_index += 1 + decl[2] = list() + + if len(decl) > 0: + tmp = [] + if depth: + yield from self._unroll_stmt_into(decl, tmp, depth - 1) + else: + yield decl, tmp + + decl = tmp.pop() + self.write(self.unparse(decl), unroll=False) + + output.append(self.unroll_cache[key]) + return + + output.append(stmt) + + def p_thread_main(self): + while True: + data = self.p.stdout.readline().decode("utf-8") + if data == "": break + self.p_queue.put(data) + self.p_queue.put("") + self.p_running = False + + def p_open(self): + assert self.p is None + try: + self.p = subprocess.Popen(self.popen_vargs, stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + except FileNotFoundError: + print("%s SMT Solver '%s' not found in path." % (self.timestamp(), self.popen_vargs[0]), flush=True) + sys.exit(1) + running_solvers[self.p_index] = self.p + self.p_running = True + self.p_next = None + self.p_queue = Queue() + self.p_thread = Thread(target=self.p_thread_main) + self.p_thread.start() + + def p_write(self, data, flush): + assert self.p is not None + self.p.stdin.write(bytes(data, "utf-8")) + if flush: self.p.stdin.flush() + + def p_read(self): + assert self.p is not None + if self.p_next is not None: + data = self.p_next + self.p_next = None + return data + if not self.p_running: + return "" + return self.p_queue.get() + + def p_poll(self, timeout=0.1): + assert self.p is not None + assert self.p_running + if self.p_next is not None: + return False + try: + self.p_next = self.p_queue.get(True, timeout) + return False + except Empty: + return True + + def p_close(self): + assert self.p is not None + self.p.stdin.close() + self.p_thread.join() + assert not self.p_running + del running_solvers[self.p_index] + self.p = None + self.p_next = None + self.p_queue = None + self.p_thread = None + + def write(self, stmt, unroll=True): + if stmt.startswith(";"): + self.info(stmt) + if not self.setup_done: + self.info_stmts.append(stmt) + return + elif not self.setup_done: + self.setup() + + stmt = stmt.strip() + + if self.nocomments or self.unroll: + stmt = re.sub(r" *;.*", "", stmt) + if stmt == "": return + + recheck = None + + if self.solver != "dummy": + if self.noincr: + # Don't close the solver yet, if we're just unrolling definitions + # required for a (get-...) statement + if self.p is not None and not stmt.startswith("(get-") and unroll: + self.p_close() + + if unroll and self.unroll: + s = re.sub(r"\|[^|]*\|", "", stmt) + self.unroll_level += s.count("(") - s.count(")") + if self.unroll_level > 0: + self.unroll_buffer += stmt + self.unroll_buffer += " " + return + else: + stmt = self.unroll_buffer + stmt + self.unroll_buffer = "" + + s = self.parse(stmt) + + if self.recheck and s and s[0].startswith("get-"): + recheck = self.unroll_idcnt + + if self.debug_print: + print("-> %s" % s) + + if len(s) == 3 and s[0] == "declare-sort" and s[2] == "0": + self.unroll_sorts.add(s[1]) + return + + elif len(s) == 4 and s[0] == "declare-fun" and s[2] == [] and s[3] in self.unroll_sorts: + self.unroll_objs.add(s[1]) + return + + elif len(s) >= 4 and s[0] == "declare-fun": + for arg_sort in s[2]: + if arg_sort in self.unroll_sorts: + self.unroll_decls[s[1]] = s + return + + elif len(s) >= 4 and s[0] == "define-fun": + for arg_name, arg_sort in s[2]: + if arg_sort in self.unroll_sorts: + self.unroll_decls[s[1]] = s + return + + stmt = self.unparse(self.unroll_stmt(s)) + + if recheck is not None and recheck != self.unroll_idcnt: + self.check_sat(["sat"]) + + if stmt == "(push 1)": + self.unroll_stack.append(( + copy(self.unroll_sorts), + copy(self.unroll_objs), + copy(self.unroll_decls), + copy(self.unroll_cache), + )) + + if stmt == "(pop 1)": + self.unroll_sorts, self.unroll_objs, self.unroll_decls, self.unroll_cache = self.unroll_stack.pop() + + if self.debug_print: + print("> %s" % stmt) + + if self.debug_file: + print(stmt, file=self.debug_file) + self.debug_file.flush() + + if self.solver != "dummy": + if self.noincr: + if stmt == "(push 1)": + self.smt2cache.append(list()) + elif stmt == "(pop 1)": + self.smt2cache.pop() + else: + if self.p is not None: + self.p_write(stmt + "\n", True) + self.smt2cache[-1].append(stmt) + else: + self.p_write(stmt + "\n", True) + + def info(self, stmt): + if not stmt.startswith("; yosys-smt2-"): + return + + fields = stmt.split() + + if fields[1] == "yosys-smt2-solver-option": + self.smt2_options[fields[2]] = fields[3] + + if fields[1] == "yosys-smt2-nomem": + if self.logic is None: + self.logic_ax = False + + if fields[1] == "yosys-smt2-nobv": + if self.logic is None: + self.logic_bv = False + + if fields[1] == "yosys-smt2-stdt": + if self.logic is None: + self.logic_dt = True + + if fields[1] == "yosys-smt2-forall": + if self.logic is None: + self.logic_qf = False + self.forall = True + + if fields[1] == "yosys-smt2-module": + self.curmod = fields[2] + self.modinfo[self.curmod] = SmtModInfo() + + if fields[1] == "yosys-smt2-cell": + self.modinfo[self.curmod].cells[fields[3]] = fields[2] + + if fields[1] == "yosys-smt2-topmod": + self.topmod = fields[2] + + if fields[1] == "yosys-smt2-input": + self.modinfo[self.curmod].inputs.add(fields[2]) + self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-output": + self.modinfo[self.curmod].outputs.add(fields[2]) + self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-register": + self.modinfo[self.curmod].registers.add(fields[2]) + self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-memory": + self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]), int(fields[6]), fields[7] == "async") + + if fields[1] == "yosys-smt2-wire": + self.modinfo[self.curmod].wires.add(fields[2]) + self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-clock": + for edge in fields[3:]: + if fields[2] not in self.modinfo[self.curmod].clocks: + self.modinfo[self.curmod].clocks[fields[2]] = edge + elif self.modinfo[self.curmod].clocks[fields[2]] != edge: + self.modinfo[self.curmod].clocks[fields[2]] = "event" + + if fields[1] == "yosys-smt2-assert": + if len(fields) > 4: + self.modinfo[self.curmod].asserts["%s_a %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})' + else: + self.modinfo[self.curmod].asserts["%s_a %s" % (self.curmod, fields[2])] = fields[3] + + if fields[1] == "yosys-smt2-cover": + if len(fields) > 4: + self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})' + else: + self.modinfo[self.curmod].covers["%s_c %s" % (self.curmod, fields[2])] = fields[3] + + if fields[1] == "yosys-smt2-assume": + if len(fields) > 4: + self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = f'{fields[4]} ({fields[3]})' + else: + self.modinfo[self.curmod].assumes["%s_u %s" % (self.curmod, fields[2])] = fields[3] + + if fields[1] == "yosys-smt2-maximize": + self.modinfo[self.curmod].maximize.add(fields[2]) + + if fields[1] == "yosys-smt2-minimize": + self.modinfo[self.curmod].minimize.add(fields[2]) + + if fields[1] == "yosys-smt2-anyconst": + self.modinfo[self.curmod].anyconsts[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5]) + self.modinfo[self.curmod].asize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-anyseq": + self.modinfo[self.curmod].anyseqs[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5]) + self.modinfo[self.curmod].asize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-allconst": + self.modinfo[self.curmod].allconsts[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5]) + self.modinfo[self.curmod].asize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-allseq": + self.modinfo[self.curmod].allseqs[fields[2]] = (fields[4], None if len(fields) <= 5 else fields[5]) + self.modinfo[self.curmod].asize[fields[2]] = int(fields[3]) + + if fields[1] == "yosys-smt2-witness": + data = json.loads(stmt.split(None, 2)[2]) + if data.get("type") in ["cell", "mem", "posedge", "negedge", "input", "reg", "init", "seq", "blackbox"]: + self.modinfo[self.curmod].witness.append(data) + + def hiernets(self, top, regs_only=False): + def hiernets_worker(nets, mod, cursor): + for netname in sorted(self.modinfo[mod].wsize.keys()): + if not regs_only or netname in self.modinfo[mod].registers: + nets.append(cursor + [netname]) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + hiernets_worker(nets, celltype, cursor + [cellname]) + + nets = list() + hiernets_worker(nets, top, []) + return nets + + def hieranyconsts(self, top): + def worker(results, mod, cursor): + for name, value in sorted(self.modinfo[mod].anyconsts.items()): + width = self.modinfo[mod].asize[name] + results.append((cursor, name, value[0], value[1], width)) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + worker(results, celltype, cursor + [cellname]) + + results = list() + worker(results, top, []) + return results + + def hieranyseqs(self, top): + def worker(results, mod, cursor): + for name, value in sorted(self.modinfo[mod].anyseqs.items()): + width = self.modinfo[mod].asize[name] + results.append((cursor, name, value[0], value[1], width)) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + worker(results, celltype, cursor + [cellname]) + + results = list() + worker(results, top, []) + return results + + def hierallconsts(self, top): + def worker(results, mod, cursor): + for name, value in sorted(self.modinfo[mod].allconsts.items()): + width = self.modinfo[mod].asize[name] + results.append((cursor, name, value[0], value[1], width)) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + worker(results, celltype, cursor + [cellname]) + + results = list() + worker(results, top, []) + return results + + def hierallseqs(self, top): + def worker(results, mod, cursor): + for name, value in sorted(self.modinfo[mod].allseqs.items()): + width = self.modinfo[mod].asize[name] + results.append((cursor, name, value[0], value[1], width)) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + worker(results, celltype, cursor + [cellname]) + + results = list() + worker(results, top, []) + return results + + def hiermems(self, top): + def hiermems_worker(mems, mod, cursor): + for memname in sorted(self.modinfo[mod].memories.keys()): + mems.append(cursor + [memname]) + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + hiermems_worker(mems, celltype, cursor + [cellname]) + + mems = list() + hiermems_worker(mems, top, []) + return mems + + def hierwitness(self, top, allregs=False, blackbox=True): + init_witnesses = [] + seq_witnesses = [] + clk_witnesses = [] + mem_witnesses = [] + + def absolute(path, cursor, witness): + return { + **witness, + "path": path + tuple(witness["path"]), + "smtpath": cursor + [witness["smtname"]], + } + + for witness in self.modinfo[top].witness: + if witness["type"] == "input": + seq_witnesses.append(absolute((), [], witness)) + if witness["type"] in ("posedge", "negedge"): + clk_witnesses.append(absolute((), [], witness)) + + init_types = ["init"] + if allregs: + init_types.append("reg") + + seq_types = ["seq"] + if blackbox: + seq_types.append("blackbox") + + def worker(mod, path, cursor): + cell_paths = {} + for witness in self.modinfo[mod].witness: + if witness["type"] in init_types: + init_witnesses.append(absolute(path, cursor, witness)) + if witness["type"] in seq_types: + seq_witnesses.append(absolute(path, cursor, witness)) + if witness["type"] == "mem": + if allregs and not witness["rom"]: + width, size = witness["width"], witness["size"] + witness = {**witness, "uninitialized": [{"width": width * size, "offset": 0}]} + if not witness["uninitialized"]: + continue + + mem_witnesses.append(absolute(path, cursor, witness)) + if witness["type"] == "cell": + cell_paths[witness["smtname"]] = tuple(witness["path"]) + + for cellname, celltype in sorted(self.modinfo[mod].cells.items()): + worker(celltype, path + cell_paths.get(cellname, ("?" + cellname,)), cursor + [cellname]) + + worker(top, (), []) + return init_witnesses, seq_witnesses, clk_witnesses, mem_witnesses + + def read(self): + stmt = [] + count_brackets = 0 + + while True: + if self.solver == "dummy": + line = self.dummy_fd.readline().strip() + else: + line = self.p_read().strip() + if self.dummy_file is not None: + self.dummy_fd.write(line + "\n") + + count_brackets += line.count("(") + count_brackets -= line.count(")") + stmt.append(line) + + if self.debug_print: + print("< %s" % line) + if count_brackets == 0: + break + if self.solver != "dummy" and self.p.poll(): + print("%s Solver terminated unexpectedly: %s" % (self.timestamp(), "".join(stmt)), flush=True) + sys.exit(1) + + stmt = "".join(stmt) + if stmt.startswith("(error"): + print("%s Solver Error: %s" % (self.timestamp(), stmt), flush=True) + if self.solver != "dummy": + self.p_close() + sys.exit(1) + + return stmt + + def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted"]): + if self.smt2_assumptions: + assume_exprs = " ".join(self.smt2_assumptions.values()) + check_stmt = f"(check-sat-assuming ({assume_exprs}))" + else: + check_stmt = "(check-sat)" + if self.debug_print: + print(f"> {check_stmt}") + if self.debug_file and not self.nocomments: + print("; running check-sat..", file=self.debug_file) + self.debug_file.flush() + + if self.solver != "dummy": + if self.noincr: + if self.p is not None: + self.p_close() + self.p_open() + for cache_ctx in self.smt2cache: + for cache_stmt in cache_ctx: + self.p_write(cache_stmt + "\n", False) + + self.p_write(f"{check_stmt}\n", True) + + if self.timeinfo: + i = 0 + s = r"/-\|" + + count = 0 + num_bs = 0 + while self.p_poll(): + count += 1 + + if count < 25: + continue + + if count % 10 == 0 or count == 25: + secs = count // 10 + + if secs < 60: + m = "(%d seconds)" % secs + elif secs < 60*60: + m = "(%d seconds -- %d:%02d)" % (secs, secs // 60, secs % 60) + else: + m = "(%d seconds -- %d:%02d:%02d)" % (secs, secs // (60*60), (secs // 60) % 60, secs % 60) + + print("%s %s %c" % ("\b \b" * num_bs, m, s[i]), end="", file=sys.stderr) + num_bs = len(m) + 3 + + else: + print("\b" + s[i], end="", file=sys.stderr) + + sys.stderr.flush() + i = (i + 1) % len(s) + + if num_bs != 0: + print("\b \b" * num_bs, end="", file=sys.stderr) + sys.stderr.flush() + + else: + count = 0 + while self.p_poll(60): + count += 1 + msg = None + + if count == 1: + msg = "1 minute" + + elif count in [5, 10, 15, 30]: + msg = "%d minutes" % count + + elif count == 60: + msg = "1 hour" + + elif count % 60 == 0: + msg = "%d hours" % (count // 60) + + if msg is not None: + print("%s waiting for solver (%s)" % (self.timestamp(), msg), flush=True) + + if self.forall: + result = self.read() + while result not in ["sat", "unsat", "unknown", "timeout", "interrupted", ""]: + print("%s %s: %s" % (self.timestamp(), self.solver, result)) + result = self.read() + else: + result = self.read() + + if self.debug_file: + print("(set-info :status %s)" % result, file=self.debug_file) + print(check_stmt, file=self.debug_file) + self.debug_file.flush() + + if result not in expected: + if result == "": + print("%s Unexpected EOF response from solver." % (self.timestamp()), flush=True) + else: + print("%s Unexpected response from solver: %s" % (self.timestamp(), result), flush=True) + if self.solver != "dummy": + self.p_close() + sys.exit(1) + + return result + + def parse(self, stmt): + def worker(stmt, cursor=0): + while stmt[cursor] in [" ", "\t", "\r", "\n"]: + cursor += 1 + + if stmt[cursor] == '(': + expr = [] + cursor += 1 + while stmt[cursor] != ')': + el, cursor = worker(stmt, cursor) + expr.append(el) + return expr, cursor+1 + + if stmt[cursor] == '|': + expr = "|" + cursor += 1 + while stmt[cursor] != '|': + expr += stmt[cursor] + cursor += 1 + expr += "|" + return expr, cursor+1 + + expr = "" + while stmt[cursor] not in ["(", ")", "|", " ", "\t", "\r", "\n"]: + expr += stmt[cursor] + cursor += 1 + return expr, cursor + return worker(stmt)[0] + + def unparse(self, stmt): + if isinstance(stmt, list): + return "(" + " ".join([self.unparse(s) for s in stmt]) + ")" + return stmt + + def bv2hex(self, v): + h = "" + v = self.bv2bin(v) + while len(v) > 0: + d = 0 + if len(v) > 0 and v[-1] == "1": d += 1 + if len(v) > 1 and v[-2] == "1": d += 2 + if len(v) > 2 and v[-3] == "1": d += 4 + if len(v) > 3 and v[-4] == "1": d += 8 + h = hex(d)[2:] + h + if len(v) < 4: break + v = v[:-4] + return h + + def bv2bin(self, v): + if type(v) is list and len(v) == 3 and v[0] == "_" and v[1].startswith("bv"): + x, n = int(v[1][2:]), int(v[2]) + return "".join("1" if (x & (1 << i)) else "0" for i in range(n-1, -1, -1)) + if v == "true": return "1" + if v == "false": return "0" + if v.startswith("#b"): + return v[2:] + if v.startswith("#x"): + return "".join(hex_dict.get(x) for x in v[2:]) + assert False + + def bv2int(self, v): + return int(self.bv2bin(v), 2) + + def get_raw_unsat_assumptions(self): + self.write("(get-unsat-assumptions)") + exprs = set(self.unparse(part) for part in self.parse(self.read())) + unsat_assumptions = [] + for key, value in self.smt2_assumptions.items(): + # normalize expression + value = self.unparse(self.parse(value)) + if value in exprs: + exprs.remove(value) + unsat_assumptions.append(key) + return unsat_assumptions + + def get_unsat_assumptions(self, minimize=False): + if not minimize: + return self.get_raw_unsat_assumptions() + required_assumptions = {} + + while True: + candidate_assumptions = {} + for key in self.get_raw_unsat_assumptions(): + if key not in required_assumptions: + candidate_assumptions[key] = self.smt2_assumptions[key] + + while candidate_assumptions: + + candidate_key, candidate_assume = candidate_assumptions.popitem() + + self.smt2_assumptions = {} + for key, assume in candidate_assumptions.items(): + self.smt2_assumptions[key] = assume + for key, assume in required_assumptions.items(): + self.smt2_assumptions[key] = assume + result = self.check_sat() + + if result == 'unsat': + candidate_assumptions = None + else: + required_assumptions[candidate_key] = candidate_assume + + if candidate_assumptions is not None: + return list(required_assumptions) + + def get(self, expr): + self.write("(get-value (%s))" % (expr)) + return self.parse(self.read())[0][1] + + def get_list(self, expr_list): + if len(expr_list) == 0: + return [] + self.write("(get-value (%s))" % " ".join(expr_list)) + return [n[1] for n in self.parse(self.read()) if n] + + def get_path(self, mod, path): + assert mod in self.modinfo + path = path.replace("\\", "/").split(".") + + for i in range(len(path)-1): + first = ".".join(path[0:i+1]) + second = ".".join(path[i+1:]) + + if first in self.modinfo[mod].cells: + nextmod = self.modinfo[mod].cells[first] + return [first] + self.get_path(nextmod, second) + + return [".".join(path)] + + def net_expr(self, mod, base, path): + if len(path) == 0: + return base + + if len(path) == 1: + assert mod in self.modinfo + if path[0] == "": + return base + if isinstance(path[0], int): + return "(|%s#%d| %s)" % (mod, path[0], base) + if path[0] in self.modinfo[mod].cells: + return "(|%s_h %s| %s)" % (mod, path[0], base) + if path[0] in self.modinfo[mod].wsize: + return "(|%s_n %s| %s)" % (mod, path[0], base) + if path[0] in self.modinfo[mod].memories: + return "(|%s_m %s| %s)" % (mod, path[0], base) + assert 0 + + assert mod in self.modinfo + assert path[0] in self.modinfo[mod].cells + + nextmod = self.modinfo[mod].cells[path[0]] + nextbase = "(|%s_h %s| %s)" % (mod, path[0], base) + return self.net_expr(nextmod, nextbase, path[1:]) + + def witness_net_expr(self, mod, base, witness): + net = self.net_expr(mod, base, witness["smtpath"]) + is_bool = self.net_width(mod, witness["smtpath"]) == 1 + if is_bool: + assert witness["width"] == 1 + assert witness["smtoffset"] == 0 + return net + return "((_ extract %d %d) %s)" % (witness["smtoffset"] + witness["width"] - 1, witness["smtoffset"], net) + + def net_width(self, mod, net_path): + for i in range(len(net_path)-1): + assert mod in self.modinfo + assert net_path[i] in self.modinfo[mod].cells + mod = self.modinfo[mod].cells[net_path[i]] + + assert mod in self.modinfo + if isinstance(net_path[-1], int): + return None + assert net_path[-1] in self.modinfo[mod].wsize + return self.modinfo[mod].wsize[net_path[-1]] + + def net_clock(self, mod, net_path): + for i in range(len(net_path)-1): + assert mod in self.modinfo + assert net_path[i] in self.modinfo[mod].cells + mod = self.modinfo[mod].cells[net_path[i]] + + assert mod in self.modinfo + if net_path[-1] not in self.modinfo[mod].clocks: + return None + return self.modinfo[mod].clocks[net_path[-1]] + + def net_exists(self, mod, net_path): + for i in range(len(net_path)-1): + if mod not in self.modinfo: return False + if net_path[i] not in self.modinfo[mod].cells: return False + mod = self.modinfo[mod].cells[net_path[i]] + + if mod not in self.modinfo: return False + if net_path[-1] not in self.modinfo[mod].wsize: return False + return True + + def mem_exists(self, mod, mem_path): + for i in range(len(mem_path)-1): + if mod not in self.modinfo: return False + if mem_path[i] not in self.modinfo[mod].cells: return False + mod = self.modinfo[mod].cells[mem_path[i]] + + if mod not in self.modinfo: return False + if mem_path[-1] not in self.modinfo[mod].memories: return False + return True + + def mem_expr(self, mod, base, path, port=None, infomode=False): + if len(path) == 1: + assert mod in self.modinfo + assert path[0] in self.modinfo[mod].memories + if infomode: + return self.modinfo[mod].memories[path[0]] + return "(|%s_m%s %s| %s)" % (mod, "" if port is None else ":%s" % port, path[0], base) + + assert mod in self.modinfo + assert path[0] in self.modinfo[mod].cells + + nextmod = self.modinfo[mod].cells[path[0]] + nextbase = "(|%s_h %s| %s)" % (mod, path[0], base) + return self.mem_expr(nextmod, nextbase, path[1:], port=port, infomode=infomode) + + def mem_info(self, mod, path): + return self.mem_expr(mod, "", path, infomode=True) + + def get_net(self, mod_name, net_path, state_name): + return self.get(self.net_expr(mod_name, state_name, net_path)) + + def get_net_list(self, mod_name, net_path_list, state_name): + return self.get_list([self.net_expr(mod_name, state_name, n) for n in net_path_list]) + + def get_net_hex(self, mod_name, net_path, state_name): + return self.bv2hex(self.get_net(mod_name, net_path, state_name)) + + def get_net_hex_list(self, mod_name, net_path_list, state_name): + return [self.bv2hex(v) for v in self.get_net_list(mod_name, net_path_list, state_name)] + + def get_net_bin(self, mod_name, net_path, state_name): + return self.bv2bin(self.get_net(mod_name, net_path, state_name)) + + def get_net_bin_list(self, mod_name, net_path_list, state_name): + return [self.bv2bin(v) for v in self.get_net_list(mod_name, net_path_list, state_name)] + + def wait(self): + if self.p is not None: + self.p.wait() + self.p_close() + + +class SmtOpts: + def __init__(self): + self.shortopts = "s:S:v" + self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"] + self.solver = "yices" + self.solver_opts = list() + self.debug_print = False + self.debug_file = None + self.dummy_file = None + self.unroll = False + self.noincr = False + self.timeinfo = os.name != "nt" + self.timeout = 0 + self.logic = None + self.info_stmts = list() + self.nocomments = False + + def handle(self, o, a): + if o == "-s": + self.solver = a + elif o == "-S": + self.solver_opts.append(a) + elif o == "--timeout": + self.timeout = int(a) + elif o == "-v": + self.debug_print = True + elif o == "--unroll": + self.unroll = True + elif o == "--noincr": + self.noincr = True + elif o == "--noprogress": + self.timeinfo = False + elif o == "--dump-smt2": + self.debug_file = open(a, "w") + elif o == "--logic": + self.logic = a + elif o == "--dummy": + self.dummy_file = a + elif o == "--info": + self.info_stmts.append(a) + elif o == "--nocomments": + self.nocomments = True + else: + return False + return True + + def helpmsg(self): + return """ + -s + set SMT solver: z3, yices, boolector, bitwuzla, cvc4, mathsat, dummy + default: yices + + -S + pass as command line argument to the solver + + --timeout + set the solver timeout to the specified value (in seconds). + + --logic + use the specified SMT2 logic (e.g. QF_AUFBV) + + --dummy + if solver is "dummy", read solver output from that file + otherwise: write solver output to that file + + -v + enable debug output + + --unroll + unroll uninterpreted functions + + --noincr + don't use incremental solving, instead restart solver for + each (check-sat). This also avoids (push) and (pop). + + --noprogress + disable timer display during solving + (this option is set implicitly on Windows) + + --dump-smt2 + write smt2 statements to file + + --info + include the specified smt2 info statement in the smt2 output + + --nocomments + strip all comments from the generated smt2 code +""" + + +class MkVcd: + def __init__(self, f): + self.f = f + self.t = -1 + self.nets = dict() + self.clocks = dict() + + def add_net(self, path, width): + path = tuple(path) + assert self.t == -1 + key = "n%d" % len(self.nets) + self.nets[path] = (key, width) + + def add_clock(self, path, edge): + path = tuple(path) + assert self.t == -1 + key = "n%d" % len(self.nets) + self.nets[path] = (key, 1) + self.clocks[path] = (key, edge) + + def set_net(self, path, bits): + path = tuple(path) + assert self.t >= 0 + assert path in self.nets + if path not in self.clocks: + print("b%s %s" % (bits, self.nets[path][0]), file=self.f) + + def escape_name(self, name): + name = re.sub(r"\[([0-9a-zA-Z_]*[a-zA-Z_][0-9a-zA-Z_]*)\]", r"<\1>", name) + if re.match(r"[\[\]]", name) and name[0] != "\\": + name = "\\" + name + return name + + def set_time(self, t): + assert t >= self.t + if t != self.t: + if self.t == -1: + print("$version Generated by Yosys-SMTBMC $end", file=self.f) + print("$timescale 1ns $end", file=self.f) + print("$var integer 32 t smt_step $end", file=self.f) + print("$var event 1 ! smt_clock $end", file=self.f) + + def vcdescape(n): + if n.startswith("$") or ":" in n: + return "\\" + n + return n + + scope = [] + for path in sorted(self.nets): + key, width = self.nets[path] + + uipath = list(path) + if "." in uipath[-1] and not uipath[-1].startswith("$"): + uipath = uipath[0:-1] + uipath[-1].split(".") + for i in range(len(uipath)): + uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i]) + + while uipath[:len(scope)] != scope: + print("$upscope $end", file=self.f) + scope = scope[:-1] + + while uipath[:-1] != scope: + scopename = uipath[len(scope)] + print("$scope module %s $end" % vcdescape(scopename), file=self.f) + scope.append(uipath[len(scope)]) + + if path in self.clocks and self.clocks[path][1] == "event": + print("$var event 1 %s %s $end" % (key, vcdescape(uipath[-1])), file=self.f) + else: + print("$var wire %d %s %s $end" % (width, key, vcdescape(uipath[-1])), file=self.f) + + for i in range(len(scope)): + print("$upscope $end", file=self.f) + + print("$enddefinitions $end", file=self.f) + + self.t = t + assert self.t >= 0 + + if self.t > 0: + print("#%d" % (10 * self.t - 5), file=self.f) + for path in sorted(self.clocks.keys()): + if self.clocks[path][1] == "posedge": + print("b0 %s" % self.nets[path][0], file=self.f) + elif self.clocks[path][1] == "negedge": + print("b1 %s" % self.nets[path][0], file=self.f) + + print("#%d" % (10 * self.t), file=self.f) + print("1!", file=self.f) + print("b%s t" % format(self.t, "032b"), file=self.f) + + for path in sorted(self.clocks.keys()): + if self.clocks[path][1] == "negedge": + print("b0 %s" % self.nets[path][0], file=self.f) + else: + print("b1 %s" % self.nets[path][0], file=self.f) diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 473c7faea..67358639b 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -55,28 +55,27 @@ run_smt_test() { if z3 "${base_name}.smt2"; then echo "SMT file ${base_name}.smt2 is valid ." smt_successful_files["$rtlil_file"]="Success" - # if python3 using_smtio.py "${base_name}.smt2"; then - # echo "Python script generated VCD file for $rtlil_file successfully." + if python3 vcd_harness_smt.py "${base_name}.smt2"; then + echo "Python script generated VCD file for $rtlil_file successfully." - # if [ -f "${base_name}.smt2.vcd" ]; then - # echo "VCD file ${base_name}.vcd generated successfully by Python." + if [ -f "${base_name}.smt2.vcd" ]; then + echo "VCD file ${base_name}.vcd generated successfully by Python." - # if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then - # echo "Yosys simulation for $rtlil_file completed successfully." - # smt_successful_files["$rtlil_file"]="Success" - # else - # echo "Yosys simulation failed for $rtlil_file." - # smt_failing_files["$rtlil_file"]="Yosys simulation failure" - # fi - # else - - # echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " - # smt_failing_files["$rtlil_file"]="VCD generation failure" - # fi - # else - # echo "Failed to run Python script for $rtlil_file." - # smt_failing_files["$rtlil_file"]="Python script failure" - # fi + if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then + echo "Yosys simulation for $rtlil_file completed successfully." + smt_successful_files["$rtlil_file"]="Success" + else + echo "Yosys simulation failed for $rtlil_file." + smt_failing_files["$rtlil_file"]="Yosys simulation failure" + fi + else + echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " + smt_failing_files["$rtlil_file"]="VCD generation failure" + fi + else + echo "Failed to run Python script for $rtlil_file." + smt_failing_files["$rtlil_file"]="Python script failure" + fi else echo "SMT file for $rtlil_file is invalid" smt_failing_files["$rtlil_file"]="Invalid SMT" diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py new file mode 100644 index 000000000..a44bf4570 --- /dev/null +++ b/tests/functional/single_cells/vcd_harness_smt.py @@ -0,0 +1,199 @@ +import sys +import argparse +import random +import os + +# Parse command line arguments +parser = argparse.ArgumentParser(description='Process SMT file for simulation.') +parser.add_argument('smt_file', help='Path to the SMT file to simulate.') +args = parser.parse_args() + +# Get the SMT file path from the command line argument +smt_file_path = args.smt_file +current_file_path = os.path.abspath(__file__) +# Navigate to the directory you need relative to the current script +# Assuming 'backends/smt2' is located three directories up from the current script +desired_path = os.path.join(os.path.dirname(current_file_path), '..', '..', '..', 'backends', 'functional') + +# Normalize the path to resolve any '..' +normalized_path = os.path.normpath(desired_path) + +# Append the directory to the Python path +sys.path.append(normalized_path) + +# Import the module +import smtio + +# Assuming the SmtIo class and other dependencies are available in your environment +# You may need to include the entire script provided above in your script or have it available as a module + +# Step 1: Initialize an SmtIo object + +so = smtio.SmtOpts() +so.solver = "z3" +so.logic = "BV" +so.debug_print = True +# so.debug_file = "my_debug" +smt_io = smtio.SmtIo(opts=so) +# List to store the parsed results +parsed_results = [] + +# Load and execute the SMT file +with open(smt_file_path, 'r') as smt_file: + for line in smt_file: + smt_io.write(line.strip()) +smt_io.check_sat() +# Read and parse the SMT file line by line +with open(smt_file_path, 'r') as smt_file: + for line in smt_file: + # Strip leading/trailing whitespace + stripped_line = line.strip() + + # Ignore empty lines + if not stripped_line: + continue + # comments + if stripped_line.startswith(';'): + smt_io.info(stripped_line) + + # Parse the line using SmtIo's parse method + parsed_line = smt_io.parse(stripped_line) + + # Append the parsed result to the list + parsed_results.append(parsed_line) + +# Display the parsed results +for result in parsed_results: + print(result) + +inputs = {} +outputs = {} + +for lst in parsed_results: + if lst[0] == 'declare-datatypes': + for datatype_group in lst[2]: # Navigate into the nested lists + datatype_name = datatype_group[0] + declarations = datatype_group[1][1:] # Skip the first item (e.g., 'mk_inputs') + if datatype_name == 'Inputs': + for declaration in declarations: + input_name = declaration[0] + bitvec_size = declaration[1][2] + inputs[input_name] = int(bitvec_size) + elif datatype_name == 'Outputs': + for declaration in declarations: + output_name = declaration[0] + bitvec_size = declaration[1][2] + outputs[output_name] = int(bitvec_size) + +print(inputs) +print(outputs) +def set_step(inputs, step): + # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} + # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. + + # Construct input definitions + mk_inputs_parts = [] + for input_name, width in inputs.items(): + value = random.getrandbits(width) # Generate a random number up to the maximum value for the bit size + binary_string = format(value, '0{}b'.format(width)) # Convert value to binary with leading zeros + mk_inputs_parts.append(f"#b{binary_string}") + + # Join all parts for the mk_inputs constructor + mk_inputs_call = "mk_inputs " + " ".join(mk_inputs_parts) + define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n" + + # Create the output definition by calling the gold_step function + define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step #b0 test_inputs_step_n{step}))\n" + smt_commands = [] + smt_commands.append(define_inputs) + smt_commands.append(define_output) + return smt_commands + +num_steps = 10 +smt_commands = [] +# Loop to generate SMT commands for each step +for step in range(num_steps): + for step_command in set_step(inputs, step): + smt_commands.append(step_command) + +# Print or write the SMT commands to a file +smt_file_content = ''.join(smt_commands) +print(smt_file_content) # Print to console + +# Optionally, write to a file +with open('dynamic_commands.smt2', 'w') as smt_file: + smt_file.write(smt_file_content) + +# Execute the SMT commands +for command in smt_commands: + print(command) + smt_io.write(command.strip()) + +# Check for satisfiability +# smt_io.setup() +result = smt_io.check_sat() +print(f'SAT result: {result}') + +value = smt_io.get(f'(Y test_outputs_step_n0)') +print(f" Y: {value}") + +# Store signal values +signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())} +# Retrieve and print values for each state +def hex_to_bin(value): + if value.startswith('x'): + hex_value = value[1:] # Remove the 'x' prefix + bin_value = bin(int(hex_value, 16))[2:] # Convert to binary and remove the '0b' prefix + return f'b{bin_value.zfill(len(hex_value) * 4)}' # Add 'b' prefix and pad with zeros + return value +for step in range(num_steps): + print(f"Values for step {step + 1}:") + for input_name, width in inputs.items(): + value = smt_io.get(f'({input_name} test_inputs_step_n{step})') + value = hex_to_bin(value[1:]) + print(f" {input_name}: {value}") + signals[input_name].append((step, value)) + for output_name, width in outputs.items(): + value = smt_io.get(f'({output_name} test_outputs_step_n{step})') + value = hex_to_bin(value[1:]) + print(f" {output_name}: {value}") + signals[output_name].append((step, value)) + +smt_io.p_close() + +def write_vcd(filename, signals, timescale='1 ns', date='today'): + with open(filename, 'w') as f: + # Write the header + f.write(f"$date\n {date}\n$end\n") + f.write(f"$timescale {timescale} $end\n") + + # Declare signals + f.write("$scope module gold $end\n") + for signal_name, changes in signals.items(): + signal_size = len(changes[0][1]) + f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") + f.write("$upscope $end\n") + f.write("$enddefinitions $end\n") + + # Collect all unique timestamps + timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) + + # Write initial values + f.write("#0\n") + for signal_name, changes in signals.items(): + for time, value in changes: + if time == 0: + f.write(f"{value} {signal_name}\n") + + # Write value changes + for time in timestamps: + if time != 0: + f.write(f"#{time}\n") + for signal_name, changes in signals.items(): + for change_time, value in changes: + if change_time == time: + f.write(f"b{value} {signal_name}\n") + + +# Write the VCD file +write_vcd(smt_file_path + '.vcd', signals) From eb2bb8c45b462203b64e77c943d0e866eae3e85b Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 27 Jun 2024 13:16:57 +0100 Subject: [PATCH 110/342] tidy up generic functional backend, add generic scope class, tidy up c++ functional backend --- backends/functional/cxx.cc | 192 +++++++++++++------------------------ kernel/functionalir.cc | 44 +++++---- kernel/functionalir.h | 82 ++++++++++++---- 3 files changed, 156 insertions(+), 162 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 9571385cc..5f63a0615 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -23,6 +23,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +const char illegal_characters[] = "!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ "; const char *reserved_keywords[] = { "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", "atomic_noexcept","auto","bitand","bitor","bool","break","case", @@ -41,45 +42,6 @@ const char *reserved_keywords[] = { nullptr }; -struct CxxScope { - pool used_names; - dict name_map; - - CxxScope() { - for(const char **p = reserved_keywords; *p != nullptr; p++) - reserve(*p); - } - void reserve(std::string name) { - used_names.insert(name); - } - std::string insert(IdString id) { - std::string str = RTLIL::unescape_id(id); - for(size_t i = 0; i < str.size(); i++) - if(strchr("!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ ", str[i])) - str[i] = '_'; - if(used_names.count(str) == 0){ - used_names.insert(str); - name_map.insert({id, str}); - return str; - } - for (int idx = 0 ; ; idx++){ - std::string suffixed = str + "_" + std::to_string(idx); - if (used_names.count(suffixed) == 0) { - used_names.insert(suffixed); - if(name_map.count(id) == 0) - name_map.insert({id, suffixed}); - return suffixed; - } - } - } - std::string operator[](IdString id) { - if(name_map.count(id) > 0) - return name_map[id]; - else - return insert(id); - } -}; - struct CxxType { FunctionalIR::Sort sort; CxxType(FunctionalIR::Sort sort) : sort(sort) {} @@ -109,66 +71,30 @@ struct CxxWriter { struct CxxStruct { std::string name; dict types; - CxxScope scope; - bool generate_methods; - CxxStruct(std::string name, bool generate_methods = false) - : name(name), generate_methods(generate_methods) { + FunctionalTools::Scope scope; + CxxStruct(std::string name) + : name(name), scope(illegal_characters, reserved_keywords) { scope.reserve("out"); scope.reserve("dump"); } void insert(IdString name, CxxType type) { - scope.insert(name); + scope(name); types.insert({name, type}); } void print(CxxWriter &f) { - f.printf("struct %s {\n", name.c_str()); + f.printf("\tstruct %s {\n", name.c_str()); for (auto p : types) { - f.printf("\t%s %s;\n", p.second.to_string().c_str(), scope[p.first].c_str()); + f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str()); } - f.printf("\n\ttemplate void dump(T &out) const {\n"); + f.printf("\n\t\ttemplate void visit(T &fn) {\n"); for (auto p : types) { - f.printf("\t\tout(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope[p.first].c_str()); + f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str()); } - f.printf("\t}\n\n"); - - if (generate_methods) { - // Add size method - f.printf("\tint size() const {\n"); - f.printf("\t\treturn %d;\n", types.size()); - f.printf("\t}\n\n"); - - // Add get_input method - f.printf("\tstd::variant<%s> get_input(const int index) {\n", generate_variant_types().c_str()); - f.printf("\t\tswitch (index) {\n"); - int idx = 0; - for (auto p : types) { - f.printf("\t\t\tcase %d: return std::ref(%s);\n", idx, scope[p.first].c_str()); - idx++; - } - f.printf("\t\t\tdefault: throw std::out_of_range(\"Invalid input index\");\n"); - f.printf("\t\t}\n"); - f.printf("\t}\n"); - } - - f.printf("};\n\n"); + f.printf("\t\t}\n"); + f.printf("\t};\n\n"); }; std::string operator[](IdString field) { - return scope[field]; - } - private: - std::string generate_variant_types() const { - std::set unique_types; - for (const auto& p : types) { - unique_types.insert("std::reference_wrapper<" + p.second.to_string() + ">"); - } - std::ostringstream oss; - for (auto it = unique_types.begin(); it != unique_types.end(); ++it) { - if (it != unique_types.begin()) { - oss << ", "; - } - oss << *it; - } - return oss.str(); + return scope(field); } }; @@ -255,6 +181,54 @@ template struct CxxPrintVisitor { std::string undriven(Node, int width) { return format("$const<%0>(0)", width); } }; +struct CxxModule { + FunctionalIR ir; + CxxStruct input_struct, output_struct, state_struct; + std::string module_name; + + explicit CxxModule(Module *module) : + ir(FunctionalIR::from_module(module)), + input_struct("Inputs"), + output_struct("Outputs"), + state_struct("State") + { + for (auto [name, sort] : ir.inputs()) + input_struct.insert(name, sort); + for (auto [name, sort] : ir.outputs()) + output_struct.insert(name, sort); + for (auto [name, sort] : ir.state()) + state_struct.insert(name, sort); + module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name); + } + void write_header(CxxWriter &f) { + f.printf("#include \"sim.h\"\n\n"); + } + void write_struct_def(CxxWriter &f) { + f.printf("struct %s {\n", module_name.c_str()); + input_struct.print(f); + output_struct.print(f); + state_struct.print(f); + f.printf("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n"); + f.printf("};\n\n"); + } + void write_eval_def(CxxWriter &f) { + f.printf("void %s::eval(%s::Inputs const &input, %s::Outputs &output, %s::State const ¤t_state, %s::State &next_state)\n{\n", module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str()); + FunctionalTools::Scope locals(illegal_characters, reserved_keywords); + locals.reserve("input"); + locals.reserve("output"); + locals.reserve("current_state"); + locals.reserve("next_state"); + auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); }; + for (auto node : ir) + f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), node_name(node).c_str(), node.visit(CxxPrintVisitor(node_name, input_struct, state_struct)).c_str()); + for (auto [name, sort] : ir.state()) + f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_name(ir.get_state_next_node(name)).c_str()); + for (auto [name, sort] : ir.outputs()) + f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_name(ir.get_output_node(name)).c_str()); + f.printf("}\n"); + } +}; + struct FunctionalCxxBackend : public Backend { FunctionalCxxBackend() : Backend("functional_cxx", "convert design to C++ using the functional backend") {} @@ -265,47 +239,13 @@ struct FunctionalCxxBackend : public Backend log("\n"); } - void printCxx(std::ostream &stream, std::string, std::string const & name, Module *module) + void printCxx(std::ostream &stream, std::string, Module *module) { - auto ir = FunctionalIR::from_module(module); CxxWriter f(stream); - - f.printf("#include \"sim.h\"\n"); - f.printf("#include \n"); - CxxStruct input_struct(name + "_Inputs", true); - for (auto [name, sort] : ir.inputs()) - input_struct.insert(name, sort); - CxxStruct output_struct(name + "_Outputs"); - for (auto [name, sort] : ir.outputs()) - output_struct.insert(name, sort); - CxxStruct state_struct(name + "_State"); - for (auto [name, sort] : ir.state()) - state_struct.insert(name, sort); - - dict node_names; - CxxScope locals; - - input_struct.print(f); - output_struct.print(f); - state_struct.print(f); - - f.printf("void %s(%s_Inputs const &input, %s_Outputs &output, %s_State const ¤t_state, %s_State &next_state)\n{\n", name.c_str(), name.c_str(), name.c_str(), name.c_str(), name.c_str()); - locals.reserve("input"); - locals.reserve("output"); - locals.reserve("current_state"); - locals.reserve("next_state"); - auto node_to_string = [&](FunctionalIR::Node n) { return node_names.at(n.id()); }; - for (auto node : ir) - { - std::string name = locals.insert(node.name()); - node_names.emplace(node.id(), name); - f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), name.c_str(), node.visit(CxxPrintVisitor(node_to_string, input_struct, state_struct)).c_str()); - } - for (auto [name, sort] : ir.state()) - f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_to_string(ir.get_state_next_node(name)).c_str()); - for (auto [name, sort] : ir.outputs()) - f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_to_string(ir.get_output_node(name)).c_str()); - f.printf("}\n"); + CxxModule mod(module); + mod.write_header(f); + mod.write_struct_def(f); + mod.write_eval_def(f); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override @@ -317,7 +257,7 @@ struct FunctionalCxxBackend : public Backend for (auto module : design->selected_modules()) { log("Dumping module `%s'.\n", module->name.c_str()); - printCxx(*f, filename, RTLIL::unescape_id(module->name), module); + printCxx(*f, filename, module); } } } FunctionalCxxBackend; diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 27765ac26..6ae66d680 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -33,7 +33,7 @@ class CellSimplifier { } else { reduced_b_width = new_width; T lower_b = factory.slice(b, b_width, 0, new_width); - T overflow = factory.ugt(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); + T overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); } } @@ -102,17 +102,17 @@ public: T a = extend(inputs.at(ID(A)), a_width, width, is_signed); T b = extend(inputs.at(ID(B)), b_width, width, is_signed); if(cellType.in({ID($eq), ID($eqx)})) - return extend(factory.eq(a, b, width), 1, y_width, false); + return extend(factory.equal(a, b, width), 1, y_width, false); else if(cellType.in({ID($ne), ID($nex)})) - return extend(factory.ne(a, b, width), 1, y_width, false); + return extend(factory.not_equal(a, b, width), 1, y_width, false); else if(cellType == ID($lt)) - return extend(is_signed ? factory.gt(b, a, width) : factory.ugt(b, a, width), 1, y_width, false); + return extend(is_signed ? factory.signed_greater_than(b, a, width) : factory.unsigned_greater_than(b, a, width), 1, y_width, false); else if(cellType == ID($le)) - return extend(is_signed ? factory.ge(b, a, width) : factory.uge(b, a, width), 1, y_width, false); + return extend(is_signed ? factory.signed_greater_equal(b, a, width) : factory.unsigned_greater_equal(b, a, width), 1, y_width, false); else if(cellType == ID($gt)) - return extend(is_signed ? factory.gt(a, b, width) : factory.ugt(a, b, width), 1, y_width, false); + return extend(is_signed ? factory.signed_greater_than(a, b, width) : factory.unsigned_greater_than(a, b, width), 1, y_width, false); else if(cellType == ID($ge)) - return extend(is_signed ? factory.ge(a, b, width) : factory.uge(a, b, width), 1, y_width, false); + return extend(is_signed ? factory.signed_greater_equal(a, b, width) : factory.unsigned_greater_equal(a, b, width), 1, y_width, false); else log_abort(); }else if(cellType.in({ID($logic_or), ID($logic_and)})){ @@ -127,7 +127,7 @@ public: return extend(inputs.at(ID(A)), a_width, y_width, a_signed); }else if(cellType == ID($neg)){ T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); - return factory.neg(a, y_width); + return factory.unary_minus(a, y_width); }else if(cellType == ID($logic_not)){ T a = reduce_or(inputs.at(ID(A)), a_width); T y = factory.bitwise_not(a, 1); @@ -161,7 +161,7 @@ public: T shr = logical_shift_right(a, b, width, b_width); if(b_signed) { T sign_b = factory.slice(b, b_width, b_width - 1, 1); - T shl = logical_shift_left(a, factory.neg(b, b_width), width, b_width); + T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width); T y = factory.mux(shr, shl, sign_b, width); return extend(y, width, y_width, false); } else { @@ -237,10 +237,10 @@ public: if(results.size() == 0) return factory.undriven(0); T node = results[0]; - int size = results[0].size(); + int size = results[0].width(); for(size_t i = 1; i < results.size(); i++) { - node = factory.concat(node, size, results[i], results[i].size()); - size += results[i].size(); + node = factory.concat(node, size, results[i], results[i].width()); + size += results[i].width(); } return node; } @@ -405,6 +405,13 @@ void FunctionalIR::topological_sort() { if(scc) log_error("combinational loops, aborting\n"); } +IdString merge_name(IdString a, IdString b) { + if(a[0] == '$' && b[0] == '\\') + return b; + else + return a; +} + void FunctionalIR::forward_buf() { std::vector perm, alias; perm.clear(); @@ -416,10 +423,15 @@ void FunctionalIR::forward_buf() { { int target_index = alias[node.arg(0).index()]; auto target_node = _graph[perm[target_index]]; - if(!target_node.has_sparse_attr() && node.has_sparse_attr()){ - IdString id = node.sparse_attr(); - target_node.sparse_attr() = id; - } + if(node.has_sparse_attr()) { + if(target_node.has_sparse_attr()) { + IdString id = merge_name(node.sparse_attr(), target_node.sparse_attr()); + target_node.sparse_attr() = id; + } else { + IdString id = node.sparse_attr(); + target_node.sparse_attr() = id; + } + } alias.push_back(target_index); } else diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 7eca9d87f..f49a659f3 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -29,6 +29,58 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN +namespace FunctionalTools { + class Scope { + const char *_illegal_characters; + pool _used_names; + dict _by_id; + dict _by_name; + std::string allocate_name(IdString suggestion) { + std::string str = RTLIL::unescape_id(suggestion); + for(size_t i = 0; i < str.size(); i++) + if(strchr(_illegal_characters, str[i])) + str[i] = '_'; + if(_used_names.count(str) == 0) { + _used_names.insert(str); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if(_used_names.count(suffixed) == 0) { + _used_names.insert(suffixed); + return suffixed; + } + } + } + public: + Scope(const char *illegal_characters = "", const char **keywords = nullptr) { + _illegal_characters = illegal_characters; + if(keywords != nullptr) + for(const char **p = keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + _used_names.insert(std::move(name)); + } + std::string operator()(int id, IdString suggestion) { + auto it = _by_id.find(id); + if(it != _by_id.end()) + return it->second; + std::string str = allocate_name(suggestion); + _by_id.insert({id, str}); + return str; + } + std::string operator()(IdString idstring) { + auto it = _by_name.find(idstring); + if(it != _by_name.end()) + return it->second; + std::string str = allocate_name(idstring); + _by_name.insert({idstring, str}); + return str; + } + }; +} + class FunctionalIR { enum class Fn { invalid, @@ -133,7 +185,7 @@ public: friend class Factory; friend class FunctionalIR; Graph::Ref _ref; - Node(Graph::Ref ref) : _ref(ref) { } + explicit Node(Graph::Ref ref) : _ref(ref) { } operator Graph::Ref() { return _ref; } template struct PrintVisitor { NodePrinter np; @@ -225,7 +277,6 @@ public: { return visit(PrintVisitor(np)); } - /* TODO: delete */ int size() const { return sort().width(); } }; class Factory { FunctionalIR &_ir; @@ -235,7 +286,7 @@ public: Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); for (auto arg : args) ref.append_arg(Graph::Ref(arg)); - return ref; + return Node(ref); } void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); } @@ -341,39 +392,30 @@ public: void suggest_name(Node node, IdString name) { node._ref.sparse_attr() = name; } - - /* TODO delete this later*/ - Node eq(Node a, Node b, int) { return equal(a, b, 0); } - Node ne(Node a, Node b, int) { return not_equal(a, b, 0); } - Node gt(Node a, Node b, int) { return signed_greater_than(a, b, 0); } - Node ge(Node a, Node b, int) { return signed_greater_equal(a, b, 0); } - Node ugt(Node a, Node b, int) { return unsigned_greater_than(a, b, 0); } - Node uge(Node a, Node b, int) { return unsigned_greater_equal(a, b, 0); } - Node neg(Node a, int) { return unary_minus(a, 0); } }; static FunctionalIR from_module(Module *module); Factory factory() { return Factory(*this); } int size() const { return _graph.size(); } - Node operator[](int i) { return _graph[i]; } + Node operator[](int i) { return Node(_graph[i]); } void topological_sort(); void forward_buf(); dict inputs() const { return _inputs; } dict outputs() const { return _outputs; } dict state() const { return _state; } - Node get_output_node(IdString name) { return _graph({name, false}); } - Node get_state_next_node(IdString name) { return _graph({name, true}); } + Node get_output_node(IdString name) { return Node(_graph({name, false})); } + Node get_state_next_node(IdString name) { return Node(_graph({name, true})); } class Iterator { friend class FunctionalIR; - FunctionalIR &_ir; + FunctionalIR *_ir; int _index; - Iterator(FunctionalIR &ir, int index) : _ir(ir), _index(index) {} + Iterator(FunctionalIR *ir, int index) : _ir(ir), _index(index) {} public: - Node operator*() { return _ir._graph[_index]; } + Node operator*() { return Node(_ir->_graph[_index]); } Iterator &operator++() { _index++; return *this; } bool operator!=(Iterator const &other) const { return _index != other._index; } }; - Iterator begin() { return Iterator(*this, 0); } - Iterator end() { return Iterator(*this, _graph.size()); } + Iterator begin() { return Iterator(this, 0); } + Iterator end() { return Iterator(this, _graph.size()); } }; YOSYS_NAMESPACE_END From 21bb1cf1bc0383af88c58b0ddfa20db18ecbac27 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 27 Jun 2024 15:43:57 +0100 Subject: [PATCH 111/342] rewrite functional c++ simulation library --- backends/functional/cxx.cc | 60 +- backends/functional/cxx_runtime/sim.h | 662 +++++++++---------- tests/functional/single_cells/vcd_harness.cc | 79 ++- 3 files changed, 384 insertions(+), 417 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 5f63a0615..d866dfea2 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -86,7 +86,7 @@ struct CxxStruct { for (auto p : types) { f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str()); } - f.printf("\n\t\ttemplate void visit(T &fn) {\n"); + f.printf("\n\t\ttemplate void visit(T &&fn) {\n"); for (auto p : types) { f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str()); } @@ -148,37 +148,37 @@ template struct CxxPrintVisitor { return CxxTemplate::format(fmt, arg_to_string(args)...); } std::string buf(Node, Node n) { return np(n); } - std::string slice(Node, Node a, int, int offset, int out_width) { return format("slice<%2>(%0, %1)", a, offset, out_width); } - std::string zero_extend(Node, Node a, int, int out_width) { return format("$zero_extend<%1>(%0)", a, out_width); } - std::string sign_extend(Node, Node a, int, int out_width) { return format("$sign_extend<%1>(%0)", a, out_width); } - std::string concat(Node, Node a, int, Node b, int) { return format("concat(%0, %1)", a, b); } - std::string add(Node, Node a, Node b, int) { return format("$add(%0, %1)", a, b); } - std::string sub(Node, Node a, Node b, int) { return format("$sub(%0, %1)", a, b); } - std::string bitwise_and(Node, Node a, Node b, int) { return format("$and(%0, %1)", a, b); } - std::string bitwise_or(Node, Node a, Node b, int) { return format("$or(%0, %1)", a, b); } - std::string bitwise_xor(Node, Node a, Node b, int) { return format("$xor(%0, %1)", a, b); } - std::string bitwise_not(Node, Node a, int) { return format("$not(%0)", a); } - std::string unary_minus(Node, Node a, int) { return format("$neg(%0)", a); } - std::string reduce_and(Node, Node a, int) { return format("$reduce_and(%0)", a); } - std::string reduce_or(Node, Node a, int) { return format("$reduce_or(%0)", a); } - std::string reduce_xor(Node, Node a, int) { return format("$reduce_xor(%0)", a); } - std::string equal(Node, Node a, Node b, int) { return format("$eq(%0, %1)", a, b); } - std::string not_equal(Node, Node a, Node b, int) { return format("$ne(%0, %1)", a, b); } - std::string signed_greater_than(Node, Node a, Node b, int) { return format("$gt(%0, %1)", a, b); } - std::string signed_greater_equal(Node, Node a, Node b, int) { return format("$ge(%0, %1)", a, b); } - std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("$ugt(%0, %1)", a, b); } - std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("$uge(%0, %1)", a, b); } - std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("$shl<%2>(%0, %1)", a, b, a.width()); } - std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("$shr<%2>(%0, %1)", a, b, a.width()); } - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("$asr<%2>(%0, %1)", a, b, a.width()); } - std::string mux(Node, Node a, Node b, Node s, int) { return format("$mux(%0, %1, %2)", a, b, s); } - std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("$pmux(%0, %1, %2)", a, b, s); } - std::string constant(Node, RTLIL::Const value) { return format("$const<%0>(%1)", value.size(), value.as_int()); } + std::string slice(Node, Node a, int, int offset, int out_width) { return format("%0.slice<%2>(%1)", a, offset, out_width); } + std::string zero_extend(Node, Node a, int, int out_width) { return format("%0.zero_extend<%1>()", a, out_width); } + std::string sign_extend(Node, Node a, int, int out_width) { return format("%0.sign_extend<%1>()", a, out_width); } + std::string concat(Node, Node a, int, Node b, int) { return format("%0.concat(%1)", a, b); } + std::string add(Node, Node a, Node b, int) { return format("%0 + %1", a, b); } + std::string sub(Node, Node a, Node b, int) { return format("%0 - %1", a, b); } + std::string bitwise_and(Node, Node a, Node b, int) { return format("%0 & %1", a, b); } + std::string bitwise_or(Node, Node a, Node b, int) { return format("%0 | %1", a, b); } + std::string bitwise_xor(Node, Node a, Node b, int) { return format("%0 ^ %1", a, b); } + std::string bitwise_not(Node, Node a, int) { return format("~%0", a); } + std::string unary_minus(Node, Node a, int) { return format("-%0", a); } + std::string reduce_and(Node, Node a, int) { return format("%0.all()", a); } + std::string reduce_or(Node, Node a, int) { return format("%0.any()", a); } + std::string reduce_xor(Node, Node a, int) { return format("%0.parity()", a); } + std::string equal(Node, Node a, Node b, int) { return format("%0 == %1", a, b); } + std::string not_equal(Node, Node a, Node b, int) { return format("%0 != %1", a, b); } + std::string signed_greater_than(Node, Node a, Node b, int) { return format("%0.signed_greater_than(%1)", a, b); } + std::string signed_greater_equal(Node, Node a, Node b, int) { return format("%0.signed_greater_equal(%1)", a, b); } + std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("%0 > %1", a, b); } + std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("%0 >= %1", a, b); } + std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("%0 << %1", a, b); } + std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("%0 >> %1", a, b); } + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("%0.arithmetic_shift_right(%1)", a, b); } + std::string mux(Node, Node a, Node b, Node s, int) { return format("%2.any() ? %1 : %0", a, b, s); } + std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("%0.pmux(%1, %2)", a, b, s); } + std::string constant(Node, RTLIL::Const value) { return format("Signal<%0>(%1)", value.size(), value.as_int()); } std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); } std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); } - std::string memory_read(Node, Node mem, Node addr, int, int) { return format("$memory_read(%0, %1)", mem, addr); } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("$memory_write(%0, %1, %2)", mem, addr, data); } - std::string undriven(Node, int width) { return format("$const<%0>(0)", width); } + std::string memory_read(Node, Node mem, Node addr, int, int) { return format("%0.read(%1)", mem, addr); } + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("%0.write(%1, %2)", mem, addr, data); } + std::string undriven(Node, int width) { return format("Signal<%0>(0)", width); } }; struct CxxModule { diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 3a398a13a..0614fb34c 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -24,363 +24,333 @@ #include template -using Signal = std::array; - -template -Signal slice(Signal const& a, size_t offset) -{ - Signal ret; - - std::copy(a.begin() + offset, a.begin() + offset + n, ret.begin()); - return ret; -} - -template -Signal $const(uint32_t val) -{ - size_t i; - Signal ret; - - for(i = 0; i < n; i++) - if(i < 32) - ret[i] = val & (1< -Signal $const(std::initializer_list vals) -{ - size_t k, i; - Signal ret; - - k = 0; - for (auto val : vals) { - for(i = 0; i < 32; i++) - if(i + k < n) - ret[i + k] = val & (1< friend class Signal; + std::array _bits; +public: + Signal() { } + Signal(uint32_t val) + { + for(size_t i = 0; i < n; i++) + if(i < 32) + _bits[i] = val & (1< -bool as_bool(Signal sig) -{ - for(int i = 0; i < n; i++) - if(sig[i]) - return true; - return false; -} + Signal(std::initializer_list vals) + { + size_t k, i; -template -uint32_t as_int(Signal sig) -{ - uint32_t ret = 0; - for(int i = 0; i < n; i++) - if(sig[i] && i < 32) - ret |= 1< -Signal $mux(Signal const& a, Signal const &b, Signal<1> const &s) -{ - return s[0] ? b : a; -} - -template -Signal $not(Signal const& a) -{ - Signal ret; - for(size_t i = 0; i < n; i++) - ret[i] = !a[i]; - return ret; -} - -template -Signal $neg(Signal const& a) -{ - Signal ret; - bool carry = true; - for(size_t i = 0; i < n; i++) { - int r = !a[i] + carry; - ret[i] = (r & 1) != 0; - carry = (r >> 1) != 0; - } - return ret; -} - -template -Signal<1> $reduce_or(Signal const& a) -{ - return { as_bool(a) }; -} - -template -Signal<1> $reduce_and(Signal const& a) -{ - for(size_t i = 0; i < n; i++) - if(!a[i]) - return { false }; - return { true }; -} - -template -Signal<1> $reduce_bool(Signal const& a) -{ - return { as_bool(a) }; -} - -template -Signal<1> $logic_and(Signal const& a, Signal const& b) -{ - return { as_bool(a) && as_bool(b) }; -} - -template -Signal<1> $logic_or(Signal const& a, Signal const& b) -{ - return { as_bool(a) || as_bool(b) }; -} - -template -Signal<1> $logic_not(Signal const& a) -{ - return { !as_bool(a) }; -} - -template -Signal $add(Signal const& a, Signal const &b) -{ - Signal ret; - size_t i; - int x = 0; - for(i = 0; i < n; i++){ - x += (int)a[i] + (int)b[i]; - ret[i] = x & 1; - x >>= 1; - } - return ret; -} -template -Signal $sub(Signal const& a, Signal const &b) -{ - Signal ret; - int x = 1; - for(size_t i = 0; i < n; i++){ - x += (int)a[i] + (int)!b[i]; - ret[i] = x & 1; - x >>= 1; - } - return ret; -} - -template -Signal<1> $uge(Signal const& a, Signal const &b) -{ - for(size_t i = n; i-- != 0; ) - if(a[i] != b[i]) - return { a[i] }; - return { true }; -} - -template -Signal<1> $ugt(Signal const& a, Signal const &b) -{ - for(size_t i = n; i-- != 0; ) - if(a[i] != b[i]) - return { a[i] }; - return { false }; -} - -template -Signal<1> $ge(Signal const& a, Signal const &b) -{ - if(a[n-1] != b[n-1]) - return { b[n-1] }; - return $uge(a, b); -} - -template -Signal<1> $gt(Signal const& a, Signal const &b) -{ - if(a[n-1] != b[n-1]) - return { b[n-1] }; - return $ugt(a, b); -} - -template Signal<1> $ule(Signal const& a, Signal const &b) { return $uge(b, a); } -template Signal<1> $ult(Signal const& a, Signal const &b) { return $ugt(b, a); } -template Signal<1> $le(Signal const& a, Signal const &b) { return $ge(b, a); } -template Signal<1> $lt(Signal const& a, Signal const &b) { return $gt(b, a); } - -template -Signal $and(Signal const& a, Signal const &b) -{ - Signal ret; - for(size_t i = 0; i < n; i++) - ret[i] = a[i] && b[i]; - return ret; -} - -template -Signal $or(Signal const& a, Signal const &b) -{ - Signal ret; - for(size_t i = 0; i < n; i++) - ret[i] = a[i] || b[i]; - return ret; -} - -template -Signal $xor(Signal const& a, Signal const &b) -{ - Signal ret; - for(size_t i = 0; i < n; i++) - ret[i] = a[i] != b[i]; - return ret; -} - -template -Signal $shl(Signal const& a, Signal const &b) -{ - if(nb >= sizeof(int) * 8 - 1) - for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); - size_t amount = as_int(b); - Signal ret = $const(0); - if(amount < n){ - if(amount + na > n) - std::copy(a.begin(), a.begin() + (n - amount), ret.begin() + amount); - else - std::copy(a.begin(), a.end(), ret.begin() + amount); - } - return ret; -} - -template -Signal $shr(Signal const& a, Signal const &b) -{ - if(nb >= sizeof(int) * 8 - 1) - for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); - size_t amount = as_int(b); - Signal ret; - for (size_t i = 0; i < n; i++) { - if(i + amount < n) - ret[i] = a[i + amount]; - else - ret[i] = false; - } - return ret; -} - -template -Signal $asr(Signal const& a, Signal const &b) -{ - if(nb >= sizeof(int) * 8 - 1) - for(size_t i = sizeof(int) * 8 - 1; i < nb; i++) - assert(!b[i]); - size_t amount = as_int(b); - Signal ret; - for (size_t i = 0; i < n; i++) { - if(i + amount < n) - ret[i] = a[i + amount]; - else - ret[i] = a[n - 1]; - } - return ret; -} - -template -Signal<1> $eq(Signal const& a, Signal const &b) -{ - for(size_t i = 0; i < n; i++) - if(a[i] != b[i]) - return { false }; - return { true }; -} - -template -Signal<1> $ne(Signal const& a, Signal const &b) -{ - for(size_t i = 0; i < n; i++) - if(a[i] != b[i]) - return { true }; - return { false }; -} - -template -Signal $pmux(Signal const& a, Signal const &b, Signal const &s) -{ - bool found; - Signal ret; - - found = false; - ret = a; - for(size_t i = 0; i < ns; i++){ - if(s[i]){ - if(found) - return $const(0); - found = true; - ret = slice(b, n * i); + k = 0; + for (auto val : vals) { + for(i = 0; i < 32; i++) + if(i + k < n) + _bits[i + k] = val & (1< -Signal concat(Signal const& a, Signal const& b) -{ - Signal ret; - std::copy(a.begin(), a.end(), ret.begin()); - std::copy(b.begin(), b.end(), ret.begin() + n); - return ret; -} + template + static Signal from_array(T vals) + { + size_t k, i; + Signal ret; -template -Signal $zero_extend(Signal const& a) -{ - assert(n >= m); - Signal ret; - std::copy(a.begin(), a.end(), ret.begin()); - for(size_t i = m; i < n; i++) - ret[i] = false; - return ret; -} + k = 0; + for (auto val : vals) { + for(i = 0; i < 32; i++) + if(i + k < n) + ret._bits[i + k] = val & (1< -Signal $sign_extend(Signal const& a) -{ - assert(n >= m); - Signal ret; - std::copy(a.begin(), a.end(), ret.begin()); - for(size_t i = m; i < n; i++) - ret[i] = a[m-1]; - return ret; -} + static Signal from_signed(int32_t val) + { + Signal ret; + for(size_t i = 0; i < n; i++) + if(i < 32) + ret._bits[i] = val & (1< ret; + for(size_t i = 0; i < n; i++) + ret._bits[i] = b; + return ret; + } -template -struct Memory { - std::array, 1< contents; + int size() const { return n; } + bool operator[](int i) const { assert(n >= 0 && i < n); return _bits[i]; } + + template + Signal slice(size_t offset) const + { + Signal ret; + + assert(offset + m <= n); + std::copy(_bits.begin() + offset, _bits.begin() + offset + m, ret._bits.begin()); + return ret; + } + + bool any() const + { + for(int i = 0; i < n; i++) + if(_bits[i]) + return true; + return false; + } + + bool all() const + { + for(int i = 0; i < n; i++) + if(!_bits[i]) + return false; + return true; + } + + bool parity() const + { + bool result = false; + for(int i = 0; i < n; i++) + result ^= _bits[i]; + return result; + } + + bool sign() const { return _bits[n-1]; } + + template + T as_numeric() const + { + T ret = 0; + for(size_t i = 0; i < std::min(sizeof(T) * 8, n); i++) + if(_bits[i]) + ret |= ((T)1)< + T as_numeric_clamped() const + { + for(size_t i = sizeof(T) * 8; i < n; i++) + if(_bits[i]) + return ~0; + return as_numeric(); + } + + uint32_t as_int() { return as_numeric(); } + + Signal operator ~() const + { + Signal ret; + for(size_t i = 0; i < n; i++) + ret._bits[i] = !_bits[i]; + return ret; + } + + Signal operator -() const + { + Signal ret; + bool carry = true; + for(size_t i = 0; i < n; i++) { + int r = !_bits[i] + carry; + ret._bits[i] = (r & 1) != 0; + carry = (r >> 1) != 0; + } + return ret; + } + + Signal operator +(Signal const &b) const + { + Signal ret; + size_t i; + int x = 0; + for(i = 0; i < n; i++){ + x += (int)_bits[i] + (int)b._bits[i]; + ret._bits[i] = x & 1; + x >>= 1; + } + return ret; + } + + Signal operator -(Signal const &b) const + { + Signal ret; + int x = 1; + for(size_t i = 0; i < n; i++){ + x += (int)_bits[i] + (int)!b._bits[i]; + ret._bits[i] = x & 1; + x >>= 1; + } + return ret; + } + + bool operator ==(Signal const &b) const + { + for(size_t i = 0; i < n; i++) + if(_bits[i] != b._bits[i]) + return false; + return true; + } + + bool operator >=(Signal const &b) const + { + for(size_t i = n; i-- != 0; ) + if(_bits[i] != b._bits[i]) + return _bits[i]; + return true; + } + + bool operator >(Signal const &b) const + { + for(size_t i = n; i-- != 0; ) + if(_bits[i] != b._bits[i]) + return _bits[i]; + return false; + } + + bool operator !=(Signal const &b) const { return !(*this == b); } + bool operator <=(Signal const &b) const { return b <= *this; } + bool operator <(Signal const &b) const { return b < *this; } + + bool signed_greater_than(Signal const &b) const + { + if(_bits[n-1] != b._bits[n-1]) + return b._bits[n-1]; + return *this > b; + } + + bool signed_greater_equal(Signal const &b) const + { + if(_bits[n-1] != b._bits[n-1]) + return b._bits[n-1]; + return *this >= b; + } + + Signal operator &(Signal const &b) const + { + Signal ret; + for(size_t i = 0; i < n; i++) + ret._bits[i] = _bits[i] && b._bits[i]; + return ret; + } + + Signal operator |(Signal const &b) const + { + Signal ret; + for(size_t i = 0; i < n; i++) + ret._bits[i] = _bits[i] || b._bits[i]; + return ret; + } + + Signal operator ^(Signal const &b) const + { + Signal ret; + for(size_t i = 0; i < n; i++) + ret._bits[i] = _bits[i] != b._bits[i]; + return ret; + } + + template + Signal operator <<(Signal const &b) const + { + Signal ret = 0; + size_t amount = b.template as_numeric_clamped(); + if(amount < n) + std::copy(_bits.begin(), _bits.begin() + (n - amount), ret._bits.begin() + amount); + return ret; + } + + template + Signal operator >>(Signal const &b) const + { + Signal ret = 0; + size_t amount = b.template as_numeric_clamped(); + if(amount < n) + std::copy(_bits.begin() + amount, _bits.end(), ret._bits.begin()); + return ret; + } + + template + Signal arithmetic_shift_right(Signal const &b) const + { + Signal ret = Signal::repeat(sign()); + size_t amount = b.template as_numeric_clamped(); + if(amount < n) + std::copy(_bits.begin() + amount, _bits.end(), ret._bits.begin()); + return ret; + } + + template + Signal pmux(Signal const &b, Signal const &s) const + { + bool found; + Signal ret; + + found = false; + ret = *this; + for(size_t i = 0; i < ns; i++){ + if(s._bits[i]){ + if(found) + return 0; + found = true; + ret = b.template slice(n * i); + } + } + return ret; + } + + template + Signal concat(Signal const& b) const + { + Signal ret; + std::copy(_bits.begin(), _bits.end(), ret._bits.begin()); + std::copy(b._bits.begin(), b._bits.end(), ret._bits.begin() + n); + return ret; + } + + template + Signal zero_extend() const + { + assert(m >= n); + Signal ret = 0; + std::copy(_bits.begin(), _bits.end(), ret._bits.begin()); + return ret; + } + + template + Signal sign_extend() const + { + assert(m >= n); + Signal ret = Signal::repeat(sign()); + std::copy(_bits.begin(), _bits.end(), ret._bits.begin()); + return ret; + } }; template -Signal $memory_read(Memory memory, Signal addr) -{ - return memory.contents[as_int(addr)]; -} - -template -Memory $memory_write(Memory memory, Signal addr, Signal data) -{ - Memory ret = memory; - ret.contents[as_int(addr)] = data; - return ret; -} +class Memory { + std::array, 1< _contents; +public: + Signal read(Signal addr) const + { + return _contents[addr.template as_numeric()]; + } + Memory write(Signal addr, Signal data) const + { + Memory ret = *this; + ret._contents[addr.template as_numeric()] = data; + return ret; + } +}; #endif diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc index 10ab10e42..18c9ed5df 100644 --- a/tests/functional/single_cells/vcd_harness.cc +++ b/tests/functional/single_cells/vcd_harness.cc @@ -33,23 +33,31 @@ struct Dump { } }; -// Function to set all values in a signal to false -template -void set_all_false(Signal& signal) { - std::fill(signal.begin(), signal.end(), false); -} - -template -void set_all_random(Signal& signal) { +template +Signal random_signal() { std::random_device rd; // Random device for seeding std::mt19937 gen(rd()); // Mersenne Twister engine - std::bernoulli_distribution dist(0.5); // 50-50 distribution - - for (auto& value : signal) { - value = dist(gen); // Set each value to a random boolean - } + std::uniform_int_distribution dist; + std::array words; + for(auto &w : words) + w = dist(gen); + return Signal::from_array(words); } +struct Reset { + template + void operator()(const char *, Signal &signal) { + signal = 0; + } +}; + +struct Randomize { + template + void operator()(const char *, Signal &signal) { + signal = random_signal(); + } +}; + int main(int argc, char **argv) { if (argc != 2) { @@ -62,10 +70,10 @@ int main(int argc, char **argv) constexpr int steps = 10; constexpr int number_timescale = 1; const std::string units_timescale = "us"; - gold_Inputs inputs; - gold_Outputs outputs; - gold_State state; - gold_State next_state; + gold::Inputs inputs; + gold::Outputs outputs; + gold::State state; + gold::State next_state; std::ofstream vcd_file(functional_vcd_filename); @@ -73,45 +81,34 @@ int main(int argc, char **argv) vcd_file << "$scope module gold $end\n"; { DumpHeader d(vcd_file); - inputs.dump(d); - outputs.dump(d); - state.dump(d); + inputs.visit(d); + outputs.visit(d); + state.visit(d); } vcd_file << "$enddefinitions $end\n$dumpvars\n"; vcd_file << "#0\n"; // Set all signals to false - for (int i = 0; i < inputs.size(); ++i) { - auto input_variant = inputs.get_input(i); - std::visit([](auto& signal_ref) { - set_all_false(signal_ref.get()); - }, input_variant); - } + inputs.visit(Reset()); - gold(inputs, outputs, state, next_state); + gold::eval(inputs, outputs, state, next_state); { Dump d(vcd_file); - inputs.dump(d); - outputs.dump(d); - state.dump(d); + inputs.visit(d); + outputs.visit(d); + state.visit(d); } for (int step = 0; step < steps; ++step) { // Functional backend cxx vcd_file << "#" << (step + 1) << "\n"; - // Set all signals to random - for (int i = 0; i < inputs.size(); ++i) { - auto input_variant = inputs.get_input(i); - std::visit([](auto& signal_ref) { - set_all_random(signal_ref.get()); - }, input_variant); - } + inputs.visit(Randomize()); - gold(inputs, outputs, state, next_state); + gold::eval(inputs, outputs, state, next_state); { Dump d(vcd_file); - inputs.dump(d); - outputs.dump(d); - state.dump(d); + inputs.visit(d); + outputs.visit(d); + state.visit(d); } state = next_state; From e235fc704dba8726d69f3f5964aa986952488231 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 27 Jun 2024 02:09:19 +0200 Subject: [PATCH 112/342] Create std::mt19937 only once --- tests/functional/single_cells/vcd_harness.cc | 21 ++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/single_cells/vcd_harness.cc index 18c9ed5df..9b3777c37 100644 --- a/tests/functional/single_cells/vcd_harness.cc +++ b/tests/functional/single_cells/vcd_harness.cc @@ -34,9 +34,7 @@ struct Dump { }; template -Signal random_signal() { - std::random_device rd; // Random device for seeding - std::mt19937 gen(rd()); // Mersenne Twister engine +Signal random_signal(std::mt19937 &gen) { std::uniform_int_distribution dist; std::array words; for(auto &w : words) @@ -52,9 +50,12 @@ struct Reset { }; struct Randomize { + std::mt19937 &gen; + Randomize(std::mt19937 &gen) : gen(gen) {} + template void operator()(const char *, Signal &signal) { - signal = random_signal(); + signal = random_signal(gen); } }; @@ -89,7 +90,7 @@ int main(int argc, char **argv) vcd_file << "#0\n"; // Set all signals to false inputs.visit(Reset()); - + gold::eval(inputs, outputs, state, next_state); { Dump d(vcd_file); @@ -97,11 +98,15 @@ int main(int argc, char **argv) outputs.visit(d); state.visit(d); } - + + // Initialize random number generator once + std::random_device rd; + std::mt19937 gen(rd()); + for (int step = 0; step < steps; ++step) { // Functional backend cxx vcd_file << "#" << (step + 1) << "\n"; - inputs.visit(Randomize()); + inputs.visit(Randomize(gen)); gold::eval(inputs, outputs, state, next_state); { @@ -110,7 +115,7 @@ int main(int argc, char **argv) outputs.visit(d); state.visit(d); } - + state = next_state; } From ee6bd5943684f49d933f233ddc1dbe464521921c Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 27 Jun 2024 04:14:05 +0200 Subject: [PATCH 113/342] Removed unnecesary nested_lets variable, use writer.print instead --- backends/functional/smtlib.cc | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 49dd5cf0d..7f1ca0a61 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -231,7 +231,6 @@ struct SmtModule { auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; SmtPrintVisitor visitor(node_to_string, scope); - std::string nested_lets; for (auto it = ir.begin(); it != ir.end(); ++it) { const FunctionalIR::Node &node = *it; @@ -241,31 +240,29 @@ struct SmtModule { std::string node_name = replaceCharacters(scope[node.name()]); std::string node_expr = node.visit(visitor); - nested_lets += "(let ( (" + node_name + " " + node_expr + "))"; + writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str()); } - nested_lets += " (let ("; + writer.print(" (let ("); for (const auto &output : ir.outputs()) { std::string output_name = scope[output.first]; const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); - nested_lets += " (" + output_name + " " + replaceCharacters(output_assignment).substr(1) + ")"; + writer.print(" (%s %s)", output_name.c_str(), replaceCharacters(output_assignment).substr(1).c_str()); } - nested_lets += " )"; - nested_lets += " (mk_outputs"; - + writer.print(" )"); + writer.print(" (mk_outputs"); for (const auto &output : ir.outputs()) { std::string output_name = scope[output.first]; - nested_lets += " " + output_name; + writer.print(" %s", output_name.c_str()); } - nested_lets += " )"; - nested_lets += " )"; + writer.print(" )"); + writer.print(" )"); // Close the nested lets for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { - nested_lets += " )"; + writer.print(" )"); } - writer.print("%s", nested_lets.c_str()); writer.print(" )"); writer.print(")\n"); } From 32cdf25838da8e492935e4b87829b504dfa0aec9 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 27 Jun 2024 04:42:59 +0200 Subject: [PATCH 114/342] Use FunctionalTools::Scope instead of replaceCharacters --- backends/functional/smtlib.cc | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 7f1ca0a61..afddbd834 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -23,11 +23,14 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +const char illegal_characters[] = "$\\"; +const char *reserved_keywords[] = {}; + struct SmtScope { pool used_names; dict name_map; - - SmtScope() {} + FunctionalTools::Scope scope; + SmtScope() : scope(illegal_characters, reserved_keywords) {} void reserve(const std::string &name) { used_names.insert(name); } @@ -184,21 +187,6 @@ struct SmtModule { SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} - std::string replaceCharacters(const std::string &input) - { - std::string result = input; - std::replace(result.begin(), result.end(), '$', '_'); // Replace $ with _ - - // Since \ is an escape character, we use a loop to replace it - size_t pos = 0; - while ((pos = result.find('\\', pos)) != std::string::npos) { - result.replace(pos, 1, "_"); - pos += 1; // Move past the replaced character - } - - return result; - } - void write(std::ostream &out) { SmtWriter writer(out); @@ -237,7 +225,7 @@ struct SmtModule { if (ir.inputs().count(node.name()) > 0) continue; - std::string node_name = replaceCharacters(scope[node.name()]); + std::string node_name = scope[node.name()]; std::string node_expr = node.visit(visitor); writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str()); @@ -247,7 +235,7 @@ struct SmtModule { for (const auto &output : ir.outputs()) { std::string output_name = scope[output.first]; const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); - writer.print(" (%s %s)", output_name.c_str(), replaceCharacters(output_assignment).substr(1).c_str()); + writer.print(" (%s %s)", output_name.c_str(), output_assignment.substr(1).c_str()); } writer.print(" )"); writer.print(" (mk_outputs"); From 9700df50d6818d5df276bcfff41501fef0be0ac3 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 4 Jul 2024 10:22:51 +0100 Subject: [PATCH 115/342] add generic writer class with formatting function to FunctionalTools --- backends/functional/cxx.cc | 180 +++++++++++--------------- backends/functional/cxx_runtime/sim.h | 4 +- kernel/functionalir.cc | 51 ++++++++ kernel/functionalir.h | 128 ++++++++++-------- 4 files changed, 203 insertions(+), 160 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index d866dfea2..21e287a96 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -56,17 +56,7 @@ struct CxxType { } }; -struct CxxWriter { - std::ostream &f; - CxxWriter(std::ostream &out) : f(out) {} - void printf(const char *fmt, ...) - { - va_list va; - va_start(va, fmt); - f << vstringf(fmt, va); - va_end(va); - } -}; +using CxxWriter = FunctionalTools::Writer; struct CxxStruct { std::string name; @@ -74,111 +64,85 @@ struct CxxStruct { FunctionalTools::Scope scope; CxxStruct(std::string name) : name(name), scope(illegal_characters, reserved_keywords) { - scope.reserve("out"); - scope.reserve("dump"); + scope.reserve("fn"); + scope.reserve("visit"); } void insert(IdString name, CxxType type) { scope(name); types.insert({name, type}); } void print(CxxWriter &f) { - f.printf("\tstruct %s {\n", name.c_str()); + f.print("\tstruct {} {{\n", name); for (auto p : types) { - f.printf("\t\t%s %s;\n", p.second.to_string().c_str(), scope(p.first).c_str()); + f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first)); } - f.printf("\n\t\ttemplate void visit(T &&fn) {\n"); + f.print("\n\t\ttemplate void visit(T &&fn) {{\n"); for (auto p : types) { - f.printf("\t\t\tfn(\"%s\", %s);\n", RTLIL::unescape_id(p.first).c_str(), scope(p.first).c_str()); + f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first)); } - f.printf("\t\t}\n"); - f.printf("\t};\n\n"); + f.print("\t\t}}\n"); + f.print("\t}};\n\n"); }; std::string operator[](IdString field) { return scope(field); } }; -struct CxxTemplate { - vector> _v; -public: - CxxTemplate(std::string fmt) { - std::string buf; - for(auto it = fmt.begin(); it != fmt.end(); it++){ - if(*it == '%'){ - it++; - log_assert(it != fmt.end()); - if(*it == '%') - buf += *it; - else { - log_assert(*it >= '0' && *it <= '9'); - _v.emplace_back(std::move(buf)); - _v.emplace_back((int)(*it - '0')); - } - }else - buf += *it; - } - if(!buf.empty()) - _v.emplace_back(std::move(buf)); - } - template static std::string format(CxxTemplate fmt, Args&&... args) { - vector strs = {args...}; - std::string result; - for(auto &v : fmt._v){ - if(std::string *s = std::get_if(&v)) - result += *s; - else if(int *i = std::get_if(&v)) - result += strs[*i]; - else - log_error("missing case"); - } - return result; - } -}; - -template struct CxxPrintVisitor { +template struct CxxPrintVisitor { using Node = FunctionalIR::Node; - NodeNames np; + CxxWriter &f; + NodePrinter np; CxxStruct &input_struct; CxxStruct &state_struct; - CxxPrintVisitor(NodeNames np, CxxStruct &input_struct, CxxStruct &state_struct) : np(np), input_struct(input_struct), state_struct(state_struct) { } - template std::string arg_to_string(T n) { return std::to_string(n); } - std::string arg_to_string(std::string n) { return n; } - std::string arg_to_string(Node n) { return np(n); } - template std::string format(std::string fmt, Args&&... args) { - return CxxTemplate::format(fmt, arg_to_string(args)...); + CxxPrintVisitor(CxxWriter &f, NodePrinter np, CxxStruct &input_struct, CxxStruct &state_struct) : f(f), np(np), input_struct(input_struct), state_struct(state_struct) { } + template void print(const char *fmt, Args&&... args) { + f.print_with(np, fmt, std::forward(args)...); } - std::string buf(Node, Node n) { return np(n); } - std::string slice(Node, Node a, int, int offset, int out_width) { return format("%0.slice<%2>(%1)", a, offset, out_width); } - std::string zero_extend(Node, Node a, int, int out_width) { return format("%0.zero_extend<%1>()", a, out_width); } - std::string sign_extend(Node, Node a, int, int out_width) { return format("%0.sign_extend<%1>()", a, out_width); } - std::string concat(Node, Node a, int, Node b, int) { return format("%0.concat(%1)", a, b); } - std::string add(Node, Node a, Node b, int) { return format("%0 + %1", a, b); } - std::string sub(Node, Node a, Node b, int) { return format("%0 - %1", a, b); } - std::string bitwise_and(Node, Node a, Node b, int) { return format("%0 & %1", a, b); } - std::string bitwise_or(Node, Node a, Node b, int) { return format("%0 | %1", a, b); } - std::string bitwise_xor(Node, Node a, Node b, int) { return format("%0 ^ %1", a, b); } - std::string bitwise_not(Node, Node a, int) { return format("~%0", a); } - std::string unary_minus(Node, Node a, int) { return format("-%0", a); } - std::string reduce_and(Node, Node a, int) { return format("%0.all()", a); } - std::string reduce_or(Node, Node a, int) { return format("%0.any()", a); } - std::string reduce_xor(Node, Node a, int) { return format("%0.parity()", a); } - std::string equal(Node, Node a, Node b, int) { return format("%0 == %1", a, b); } - std::string not_equal(Node, Node a, Node b, int) { return format("%0 != %1", a, b); } - std::string signed_greater_than(Node, Node a, Node b, int) { return format("%0.signed_greater_than(%1)", a, b); } - std::string signed_greater_equal(Node, Node a, Node b, int) { return format("%0.signed_greater_equal(%1)", a, b); } - std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("%0 > %1", a, b); } - std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("%0 >= %1", a, b); } - std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("%0 << %1", a, b); } - std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("%0 >> %1", a, b); } - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("%0.arithmetic_shift_right(%1)", a, b); } - std::string mux(Node, Node a, Node b, Node s, int) { return format("%2.any() ? %1 : %0", a, b, s); } - std::string pmux(Node, Node a, Node b, Node s, int, int) { return format("%0.pmux(%1, %2)", a, b, s); } - std::string constant(Node, RTLIL::Const value) { return format("Signal<%0>(%1)", value.size(), value.as_int()); } - std::string input(Node, IdString name) { return format("input.%0", input_struct[name]); } - std::string state(Node, IdString name) { return format("current_state.%0", state_struct[name]); } - std::string memory_read(Node, Node mem, Node addr, int, int) { return format("%0.read(%1)", mem, addr); } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("%0.write(%1, %2)", mem, addr, data); } - std::string undriven(Node, int width) { return format("Signal<%0>(0)", width); } + void buf(Node, Node n) { print("{}", n); } + void slice(Node, Node a, int, int offset, int out_width) { print("{0}.slice<{2}>({1})", a, offset, out_width); } + void zero_extend(Node, Node a, int, int out_width) { print("{}.zero_extend<{}>()", a, out_width); } + void sign_extend(Node, Node a, int, int out_width) { print("{}.sign_extend<{}>()", a, out_width); } + void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); } + void add(Node, Node a, Node b, int) { print("{} + {}", a, b); } + void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); } + void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); } + void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); } + void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); } + void bitwise_not(Node, Node a, int) { print("~{}", a); } + void unary_minus(Node, Node a, int) { print("-{}", a); } + void reduce_and(Node, Node a, int) { print("{}.all()", a); } + void reduce_or(Node, Node a, int) { print("{}.any()", a); } + void reduce_xor(Node, Node a, int) { print("{}.parity()", a); } + void equal(Node, Node a, Node b, int) { print("{} == {}", a, b); } + void not_equal(Node, Node a, Node b, int) { print("{} != {}", a, b); } + void signed_greater_than(Node, Node a, Node b, int) { print("{}.signed_greater_than({})", a, b); } + void signed_greater_equal(Node, Node a, Node b, int) { print("{}.signed_greater_equal({})", a, b); } + void unsigned_greater_than(Node, Node a, Node b, int) { print("{} > {}", a, b); } + void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); } + void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); } + void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); } + void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right{})", a, b); } + void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); } + void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); } + void constant(Node, RTLIL::Const value) { + std::stringstream ss; + bool multiple = value.size() > 32; + ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase; + if(multiple) ss << "{"; + while(value.size() > 32) { + ss << value.as_int() << ", "; + value = value.extract(32, value.size() - 32); + } + ss << value.as_int(); + if(multiple) ss << "}"; + ss << ")"; + print("{}", ss.str()); + } + void input(Node, IdString name) { print("input.{}", input_struct[name]); } + void state(Node, IdString name) { print("current_state.{}", state_struct[name]); } + void memory_read(Node, Node mem, Node addr, int, int) { print("{}.read({})", mem, addr); } + void memory_write(Node, Node mem, Node addr, Node data, int, int) { print("{}.write({}, {})", mem, addr, data); } + void undriven(Node, int width) { print("Signal<{}>(0)", width); } }; struct CxxModule { @@ -201,31 +165,35 @@ struct CxxModule { module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name); } void write_header(CxxWriter &f) { - f.printf("#include \"sim.h\"\n\n"); + f.print("#include \"sim.h\"\n\n"); } void write_struct_def(CxxWriter &f) { - f.printf("struct %s {\n", module_name.c_str()); + f.print("struct {} {{\n", module_name); input_struct.print(f); output_struct.print(f); state_struct.print(f); - f.printf("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n"); - f.printf("};\n\n"); + f.print("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n"); + f.print("}};\n\n"); } void write_eval_def(CxxWriter &f) { - f.printf("void %s::eval(%s::Inputs const &input, %s::Outputs &output, %s::State const ¤t_state, %s::State &next_state)\n{\n", module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str(), module_name.c_str()); + f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const ¤t_state, {0}::State &next_state)\n{{\n", module_name); FunctionalTools::Scope locals(illegal_characters, reserved_keywords); locals.reserve("input"); locals.reserve("output"); locals.reserve("current_state"); locals.reserve("next_state"); auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); }; - for (auto node : ir) - f.printf("\t%s %s = %s;\n", CxxType(node.sort()).to_string().c_str(), node_name(node).c_str(), node.visit(CxxPrintVisitor(node_name, input_struct, state_struct)).c_str()); + CxxPrintVisitor printVisitor(f, node_name, input_struct, state_struct); + for (auto node : ir) { + f.print("\t{} {} = ", CxxType(node.sort()).to_string(), node_name(node)); + node.visit(printVisitor); + f.print(";\n"); + } for (auto [name, sort] : ir.state()) - f.printf("\tnext_state.%s = %s;\n", state_struct[name].c_str(), node_name(ir.get_state_next_node(name)).c_str()); + f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name))); for (auto [name, sort] : ir.outputs()) - f.printf("\toutput.%s = %s;\n", output_struct[name].c_str(), node_name(ir.get_output_node(name)).c_str()); - f.printf("}\n"); + f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name))); + f.print("}}\n"); } }; diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 0614fb34c..1985322f1 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -143,11 +143,11 @@ public: { for(size_t i = sizeof(T) * 8; i < n; i++) if(_bits[i]) - return ~0; + return ~((T)0); return as_numeric(); } - uint32_t as_int() { return as_numeric(); } + uint32_t as_int() const { return as_numeric(); } Signal operator ~() const { diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 6ae66d680..3fd2d8240 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -443,4 +443,55 @@ void FunctionalIR::forward_buf() { _graph.permute(perm, alias); } +static std::string quote_fmt(const char *fmt) +{ + std::string r; + for(const char *p = fmt; *p != 0; p++) { + switch(*p) { + case '\n': r += "\\n"; break; + case '\t': r += "\\t"; break; + case '"': r += "\\\""; break; + case '\\': r += "\\\\"; break; + default: r += *p; break; + } + } + return r; +} + +void FunctionalTools::Writer::print_impl(const char *fmt, vector> &fns) +{ + size_t next_index = 0; + for(const char *p = fmt; *p != 0; p++) + switch(*p) { + case '{': + if(*++p == '{') { + *os << '{'; + } else { + char *pe; + size_t index = strtoul(p, &pe, 10); + if(*pe != '}') + log_error("invalid format string: expected {}, {} or {{, got \"%s\": \"%s\"\n", + quote_fmt(std::string(p - 1, pe - p + 2).c_str()).c_str(), + quote_fmt(fmt).c_str()); + if(p == pe) + index = next_index; + else + p = pe; + if(index >= fns.size()) + log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt).c_str()); + fns[index](); + next_index = index + 1; + } + break; + case '}': + p++; + if(*p != '}') + log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt).c_str()); + *os << '}'; + break; + default: + *os << *p; + } +} + YOSYS_NAMESPACE_END diff --git a/kernel/functionalir.h b/kernel/functionalir.h index f49a659f3..2c0d0f55c 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -29,58 +29,6 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN -namespace FunctionalTools { - class Scope { - const char *_illegal_characters; - pool _used_names; - dict _by_id; - dict _by_name; - std::string allocate_name(IdString suggestion) { - std::string str = RTLIL::unescape_id(suggestion); - for(size_t i = 0; i < str.size(); i++) - if(strchr(_illegal_characters, str[i])) - str[i] = '_'; - if(_used_names.count(str) == 0) { - _used_names.insert(str); - return str; - } - for (int idx = 0 ; ; idx++){ - std::string suffixed = str + "_" + std::to_string(idx); - if(_used_names.count(suffixed) == 0) { - _used_names.insert(suffixed); - return suffixed; - } - } - } - public: - Scope(const char *illegal_characters = "", const char **keywords = nullptr) { - _illegal_characters = illegal_characters; - if(keywords != nullptr) - for(const char **p = keywords; *p != nullptr; p++) - reserve(*p); - } - void reserve(std::string name) { - _used_names.insert(std::move(name)); - } - std::string operator()(int id, IdString suggestion) { - auto it = _by_id.find(id); - if(it != _by_id.end()) - return it->second; - std::string str = allocate_name(suggestion); - _by_id.insert({id, str}); - return str; - } - std::string operator()(IdString idstring) { - auto it = _by_name.find(idstring); - if(it != _by_name.end()) - return it->second; - std::string str = allocate_name(idstring); - _by_name.insert({idstring, str}); - return str; - } - }; -} - class FunctionalIR { enum class Fn { invalid, @@ -418,6 +366,82 @@ public: Iterator end() { return Iterator(this, _graph.size()); } }; +namespace FunctionalTools { + class Scope { + const char *_illegal_characters; + pool _used_names; + dict _by_id; + dict _by_name; + std::string allocate_name(IdString suggestion) { + std::string str = RTLIL::unescape_id(suggestion); + for(size_t i = 0; i < str.size(); i++) + if(strchr(_illegal_characters, str[i])) + str[i] = '_'; + if(_used_names.count(str) == 0) { + _used_names.insert(str); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if(_used_names.count(suffixed) == 0) { + _used_names.insert(suffixed); + return suffixed; + } + } + } + public: + Scope(const char *illegal_characters = "", const char **keywords = nullptr) { + _illegal_characters = illegal_characters; + if(keywords != nullptr) + for(const char **p = keywords; *p != nullptr; p++) + reserve(*p); + } + void reserve(std::string name) { + _used_names.insert(std::move(name)); + } + std::string operator()(int id, IdString suggestion) { + auto it = _by_id.find(id); + if(it != _by_id.end()) + return it->second; + std::string str = allocate_name(suggestion); + _by_id.insert({id, str}); + return str; + } + std::string operator()(IdString idstring) { + auto it = _by_name.find(idstring); + if(it != _by_name.end()) + return it->second; + std::string str = allocate_name(idstring); + _by_name.insert({idstring, str}); + return str; + } + }; + class Writer { + std::ostream *os; + void print_impl(const char *fmt, vector>& fns); + public: + Writer(std::ostream &os) : os(&os) {} + template Writer& operator <<(T&& arg) { *os << std::forward(arg); return *this; } + template + void print(const char *fmt, Args&&... args) + { + vector> fns { [&]() { *this << args; }... }; + print_impl(fmt, fns); + } + template + void print_with(Fn fn, const char *fmt, Args&&... args) + { + vector> fns { [&]() { + if constexpr (std::is_invocable_v) + *this << fn(args); + else + *this << args; }... + }; + print_impl(fmt, fns); + } + }; +} + YOSYS_NAMESPACE_END #endif From cb5f08364c2a775c9725d94144875539edff8533 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 3 Jul 2024 17:07:50 +0200 Subject: [PATCH 116/342] =?UTF-8?q?=C2=B4SMT=20success=20only=20if=20simul?= =?UTF-8?q?ation=20is=20equivalent?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tests/functional/single_cells/run-test.sh | 1 - tests/functional/single_cells/vcd_harness_smt.py | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 67358639b..11ff1b5ce 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -54,7 +54,6 @@ run_smt_test() { # TODO: which SMT solver should be run? if z3 "${base_name}.smt2"; then echo "SMT file ${base_name}.smt2 is valid ." - smt_successful_files["$rtlil_file"]="Success" if python3 vcd_harness_smt.py "${base_name}.smt2"; then echo "Python script generated VCD file for $rtlil_file successfully." diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py index a44bf4570..5d8c735a6 100644 --- a/tests/functional/single_cells/vcd_harness_smt.py +++ b/tests/functional/single_cells/vcd_harness_smt.py @@ -133,6 +133,9 @@ for command in smt_commands: # smt_io.setup() result = smt_io.check_sat() print(f'SAT result: {result}') +if result != 'sat': + smt_io.p_close() + sys.exit(1) value = smt_io.get(f'(Y test_outputs_step_n0)') print(f" Y: {value}") @@ -197,3 +200,4 @@ def write_vcd(filename, signals, timescale='1 ns', date='today'): # Write the VCD file write_vcd(smt_file_path + '.vcd', signals) +sys.exit(0) From 73ed5146233dca64405a30d82646b286df43144a Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 4 Jul 2024 12:35:00 +0200 Subject: [PATCH 117/342] Check that there are not other solutions other than the first given --- tests/functional/single_cells/vcd_harness_smt.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py index 5d8c735a6..fd5e94f7e 100644 --- a/tests/functional/single_cells/vcd_harness_smt.py +++ b/tests/functional/single_cells/vcd_harness_smt.py @@ -41,7 +41,7 @@ parsed_results = [] # Load and execute the SMT file with open(smt_file_path, 'r') as smt_file: for line in smt_file: - smt_io.write(line.strip()) + smt_io.write(line.strip()) smt_io.check_sat() # Read and parse the SMT file line by line with open(smt_file_path, 'r') as smt_file: @@ -161,6 +161,17 @@ for step in range(num_steps): value = hex_to_bin(value[1:]) print(f" {output_name}: {value}") signals[output_name].append((step, value)) + smt_io.write(f'(push 1)') + smt_io.write(f'(assert (not (= ({output_name} test_outputs_step_n{step}) #{value})))') + result = smt_io.check_sat(["unsat"]) + if result != 'unsat': + smt_io.p_close() + sys.exit(1) + smt_io.write(f'(pop 1)') + result = smt_io.check_sat(["sat"]) + if result != 'sat': + smt_io.p_close() + sys.exit(1) smt_io.p_close() From 762f8dd8228e8b6219d67fb04e87deb434e0215a Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 4 Jul 2024 12:39:45 +0200 Subject: [PATCH 118/342] Add readme explaining how to create test files --- tests/functional/single_cells/rtlil/README.md | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tests/functional/single_cells/rtlil/README.md diff --git a/tests/functional/single_cells/rtlil/README.md b/tests/functional/single_cells/rtlil/README.md new file mode 100644 index 000000000..4bb84565b --- /dev/null +++ b/tests/functional/single_cells/rtlil/README.md @@ -0,0 +1,2 @@ +# Creation of test files +yosys -p "test_cell -n 1 -w test_cell all" \ No newline at end of file From 50f487e08c9a2343b013652e021d7e3314d0bcae Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 4 Jul 2024 16:04:21 +0200 Subject: [PATCH 119/342] Added $ff test --- tests/functional/single_cells/rtlil/ff.il | 83 +++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 tests/functional/single_cells/rtlil/ff.il diff --git a/tests/functional/single_cells/rtlil/ff.il b/tests/functional/single_cells/rtlil/ff.il new file mode 100644 index 000000000..6e5a1a339 --- /dev/null +++ b/tests/functional/single_cells/rtlil/ff.il @@ -0,0 +1,83 @@ +# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC) +autoidx 19 +attribute \cells_not_processed 1 +attribute \src "dff.v:1.1-16.10" +module \gold + attribute \src "dff.v:8.5-14.8" + wire $0\q[0:0] + attribute \init 1'0 + wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 + attribute \init 1'1 + wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 + attribute \init 1'0 + wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 + attribute \init 1'x + wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 + wire $auto$rtlil.cc:2525:Eqx$10 + wire $auto$rtlil.cc:2582:Mux$12 + wire $auto$rtlil.cc:2582:Mux$16 + wire $auto$rtlil.cc:2582:Mux$18 + attribute \src "dff.v:2.16-2.19" + wire input 1 \clk + attribute \src "dff.v:4.16-4.17" + wire input 3 \d + attribute \keep 1 + attribute \src "dff.v:5.16-5.17" + wire output 4 \q + attribute \src "dff.v:3.16-3.21" + wire input 2 \reset + cell $mux $auto$clk2fflogic.cc:113:mux$11 + parameter \WIDTH 1 + connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 + connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 + connect \S $auto$rtlil.cc:2525:Eqx$10 + connect \Y $auto$rtlil.cc:2582:Mux$12 + end + cell $mux $auto$clk2fflogic.cc:113:mux$15 + parameter \WIDTH 1 + connect \A $auto$rtlil.cc:2582:Mux$12 + connect \B 1'0 + connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 + connect \Y $auto$rtlil.cc:2582:Mux$16 + end + cell $mux $auto$clk2fflogic.cc:113:mux$17 + parameter \WIDTH 1 + connect \A $auto$rtlil.cc:2582:Mux$16 + connect \B 1'0 + connect \S \reset + connect \Y $auto$rtlil.cc:2582:Mux$18 + end + cell $ff $auto$clk2fflogic.cc:70:sample_control$14 + parameter \WIDTH 1 + connect \D \reset + connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 + end + cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8 + parameter \WIDTH 1 + connect \D \clk + connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 + end + cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk } + connect \B 2'01 + connect \Y $auto$rtlil.cc:2525:Eqx$10 + end + attribute \clk2fflogic 1 + cell $ff $auto$clk2fflogic.cc:98:sample_data$4 + parameter \WIDTH 1 + connect \D \q + connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 + end + cell $ff $auto$clk2fflogic.cc:98:sample_data$6 + parameter \WIDTH 1 + connect \D \d + connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 + end + connect $0\q[0:0] \d + connect \q $auto$rtlil.cc:2582:Mux$18 +end From 1b2986f7fb85e00a75a0c5c6d88905f78025c467 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 4 Jul 2024 16:58:07 +0100 Subject: [PATCH 120/342] add support for $mul, $div, $divfloor, $mod, $modfloor, $pow in functional backend --- backends/functional/cxx.cc | 3 + backends/functional/cxx_runtime/sim.h | 89 +++++++++++++++++++++++++-- backends/functional/smtlib.cc | 6 ++ kernel/functionalir.cc | 73 +++++++++++++++++++++- kernel/functionalir.h | 17 ++++- 5 files changed, 177 insertions(+), 11 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 21e287a96..81af54c07 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -105,6 +105,9 @@ template struct CxxPrintVisitor { void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); } void add(Node, Node a, Node b, int) { print("{} + {}", a, b); } void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); } + void mul(Node, Node a, Node b, int) { print("{} * {}", a, b); } + void unsigned_div(Node, Node a, Node b, int) { print("{} / {}", a, b); } + void unsigned_mod(Node, Node a, Node b, int) { print("{} % {}", a, b); } void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); } void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); } void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); } diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 1985322f1..040c6aefc 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -22,6 +22,8 @@ #include #include +#include +#include template class Signal { @@ -149,6 +151,48 @@ public: uint32_t as_int() const { return as_numeric(); } +private: + std::string as_string_p2(int b) const { + std::string ret; + for(int i = (n - 1) - (n - 1) % b; i >= 0; i -= b) + ret += "0123456789abcdef"[(*this >> Signal<32>(i)).as_int() & ((1< t = *this; + Signal b = 10; + do{ + ret += (char)('0' + (t % b).as_int()); + t = t / b; + }while(t.any()); + std::reverse(ret.begin(), ret.end()); + return ret; + } +public: + std::string as_string(int base = 16, bool showbase = true) const { + std::string ret; + if(showbase) { + ret += std::to_string(n); + switch(base) { + case 2: ret += "'b"; break; + case 8: ret += "'o"; break; + case 10: ret += "'d"; break; + case 16: ret += "'h"; break; + default: assert(0); + } + } + switch(base) { + case 2: return ret + as_string_p2(1); + case 8: return ret + as_string_p2(3); + case 10: return ret + as_string_b10(); + case 16: return ret + as_string_p2(4); + default: assert(0); + } + } + friend std::ostream &operator << (std::ostream &os, Signal const &s) { return os << s.as_string(); } + Signal operator ~() const { Signal ret; @@ -160,11 +204,11 @@ public: Signal operator -() const { Signal ret; - bool carry = true; + int x = 1; for(size_t i = 0; i < n; i++) { - int r = !_bits[i] + carry; - ret._bits[i] = (r & 1) != 0; - carry = (r >> 1) != 0; + x += (int)!_bits[i]; + ret._bits[i] = (x & 1) != 0; + x >>= 1; } return ret; } @@ -172,9 +216,8 @@ public: Signal operator +(Signal const &b) const { Signal ret; - size_t i; int x = 0; - for(i = 0; i < n; i++){ + for(size_t i = 0; i < n; i++){ x += (int)_bits[i] + (int)b._bits[i]; ret._bits[i] = x & 1; x >>= 1; @@ -194,6 +237,40 @@ public: return ret; } + Signal operator *(Signal const &b) const + { + Signal ret; + int x = 0; + for(size_t i = 0; i < n; i++){ + for(size_t j = 0; j <= i; j++) + x += (int)_bits[j] & (int)b._bits[i-j]; + ret._bits[i] = x & 1; + x >>= 1; + } + return ret; + } + +private: + Signal divmod(Signal const &b, bool modulo) const + { + if(!b.any()) return 0; + Signal q = 0; + Signal r = 0; + for(size_t i = n; i-- != 0; ){ + r = r << Signal<1>(1); + r._bits[0] = _bits[i]; + if(r >= b){ + r = r - b; + q._bits[i] = true; + } + } + return modulo ? r : q; + } +public: + + Signal operator /(Signal const &b) const { return divmod(b, false); } + Signal operator %(Signal const &b) const { return divmod(b, true); } + bool operator ==(Signal const &b) const { for(size_t i = 0; i < n; i++) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index afddbd834..55efc83c1 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -119,6 +119,12 @@ template struct SmtPrintVisitor { std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); } + std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); } + + std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); } + + std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); } + std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); } std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); } diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 3fd2d8240..6498ef636 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -37,6 +37,15 @@ class CellSimplifier { return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); } } + T sign(T a, int a_width) { + return factory.slice(a, a_width, a_width - 1, 1); + } + T neg_if(T a, int a_width, T s) { + return factory.mux(a, factory.unary_minus(a, a_width), s, a_width); + } + T abs(T a, int a_width) { + return neg_if(a, a_width, sign(a, a_width)); + } public: T reduce_or(T a, int width) { if (width == 1) @@ -71,6 +80,23 @@ public: return factory.bitwise_or(aa, bb, width); } CellSimplifier(Factory &f) : factory(f) {} +private: + T handle_pow(T a0, int a_width, T b, int b_width, int y_width, bool is_signed) { + T a = extend(a0, a_width, y_width, is_signed); + T r = factory.constant(Const(1, y_width)); + for(int i = 0; i < b_width; i++) { + T b_bit = factory.slice(b, b_width, i, 1); + r = factory.mux(r, factory.mul(r, a, y_width), b_bit, y_width); + a = factory.mul(a, a, y_width); + } + if (is_signed) { + T a_ge_1 = factory.unsigned_greater_than(abs(a0, a_width), factory.constant(Const(1, a_width)), a_width); + T zero_result = factory.bitwise_and(a_ge_1, sign(b, b_width), 1); + r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result, y_width); + } + return r; + } +public: T handle(IdString cellType, dict parameters, dict inputs) { int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); @@ -78,7 +104,7 @@ public: int y_width = parameters.at(ID(Y_WIDTH), Const(-1)).as_int(); bool a_signed = parameters.at(ID(A_SIGNED), Const(0)).as_bool(); bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); - if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor)})){ + if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul)})){ bool is_signed = a_signed && b_signed; T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); @@ -86,6 +112,8 @@ public: return factory.add(a, b, y_width); else if(cellType == ID($sub)) return factory.sub(a, b, y_width); + else if(cellType == ID($mul)) + return factory.mul(a, b, y_width); else if(cellType == ID($and)) return factory.bitwise_and(a, b, y_width); else if(cellType == ID($or)) @@ -160,7 +188,7 @@ public: T b = inputs.at(ID(B)); T shr = logical_shift_right(a, b, width, b_width); if(b_signed) { - T sign_b = factory.slice(b, b_width, b_width - 1, 1); + T sign_b = sign(b, b_width); T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width); T y = factory.mux(shr, shl, sign_b, width); return extend(y, width, y_width, false); @@ -182,7 +210,46 @@ public: int offset = parameters.at(ID(OFFSET)).as_int(); T a = inputs.at(ID(A)); return factory.slice(a, a_width, offset, y_width); - }else{ + }else if(cellType.in({ID($div), ID($mod), ID($divfloor), ID($modfloor)})) { + int width = max(a_width, b_width); + bool is_signed = a_signed && b_signed; + T a = extend(inputs.at(ID(A)), a_width, width, is_signed); + T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + if(is_signed) { + if(cellType == ID($div)) { + T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width); + T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1); + return neg_if(extend(abs_y, width, y_width, true), y_width, out_sign); + } else if(cellType == ID($mod)) { + T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width); + return neg_if(extend(abs_y, width, y_width, true), y_width, sign(a, width)); + } else if(cellType == ID($divfloor)) { + T b_sign = sign(b, width); + T a1 = neg_if(a, width, b_sign); + T b1 = neg_if(b, width, b_sign); + T a1_sign = sign(a1, width); + T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width); + T y1 = factory.unsigned_div(a2, b1, width); + T y2 = factory.mux(y1, factory.bitwise_not(y1, width), a1_sign, width); + return extend(y2, width, y_width, true); + } else if(cellType == ID($modfloor)) { + T abs_b = abs(b, width); + T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width); + T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1); + T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width); + T y = neg_if(y_flipped, width, sign(b, b_width)); + return extend(y, width, y_width, true); + } else + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + } else { + if(cellType.in({ID($mod), ID($modfloor)})) + return extend(factory.unsigned_mod(a, b, width), width, y_width, false); + else + return extend(factory.unsigned_div(a, b, width), width, y_width, false); + } + } else if(cellType == ID($pow)) { + return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); + } else{ log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } } diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 2c0d0f55c..3e7c55ef4 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -39,6 +39,9 @@ class FunctionalIR { concat, add, sub, + mul, + unsigned_div, + unsigned_mod, bitwise_and, bitwise_or, bitwise_xor, @@ -145,6 +148,9 @@ public: std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; } std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; } std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; } + std::string mul(Node, Node a, Node b, int) { return "mul(" + np(a) + ", " + np(b) + ")"; } + std::string unsigned_div(Node, Node a, Node b, int) { return "unsigned_div(" + np(a) + ", " + np(b) + ")"; } + std::string unsigned_mod(Node, Node a, Node b, int) { return "unsigned_mod(" + np(a) + ", " + np(b) + ")"; } std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; } std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; } std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; } @@ -193,11 +199,14 @@ public: case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break; case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break; case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break; + case Fn::mul: return v.mul(*this, arg(0), arg(1), sort().width()); break; + case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1), sort().width()); break; + case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1), sort().width()); break; case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break; case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break; case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break; case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break; - case Fn::unary_minus: return v.bitwise_not(*this, arg(0), sort().width()); break; + case Fn::unary_minus: return v.unary_minus(*this, arg(0), sort().width()); break; case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break; case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break; case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break; @@ -257,6 +266,9 @@ public: } Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } + Node mul(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); } + Node unsigned_div(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); } + Node unsigned_mod(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); } Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } @@ -298,7 +310,8 @@ public: return add(Fn::buf, Sort(width), {}); } void update_pending(Node node, Node value) { - log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0 && node.sort() == value.sort()); + log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); + log_assert(node.sort() == value.sort()); node._ref.append_arg(value._ref); } Node input(IdString name, int width) { From 57af68af96b534d32abbc636c0bc6f225a1f09a1 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Thu, 4 Jul 2024 19:21:38 +0200 Subject: [PATCH 121/342] include algorithm, needed for std::reverse --- backends/functional/cxx_runtime/sim.h | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 040c6aefc..950d4c5e1 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -24,6 +24,7 @@ #include #include #include +#include template class Signal { From e296b884d5c1ddc610bb4ab916da4447ceb6d502 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 5 Jul 2024 14:50:00 +0200 Subject: [PATCH 122/342] Add Makefile helpers for coverage --- Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Makefile b/Makefile index 1feeeab95..2bbb0dc5b 100644 --- a/Makefile +++ b/Makefile @@ -1047,6 +1047,14 @@ coverage: lcov --capture -d . --no-external -o coverage.info genhtml coverage.info --output-directory coverage_html +clean_coverage: + find . -name "*.gcda" -type f -delete + +coverage_functional: + rm -rf coverage.info coverage_html + lcov --capture -d backends/functional --no-external -o coverage.info + genhtml coverage.info --output-directory coverage_html + qtcreator: echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config { for file in $(basename $(OBJS)); do \ From f0f436cbe7c870e947971e41c74232168dc77db4 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Fri, 5 Jul 2024 15:38:42 +0200 Subject: [PATCH 123/342] Fix parenthesis for arithmetic_shift_right --- backends/functional/cxx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 81af54c07..1d8caaaf4 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -124,7 +124,7 @@ template struct CxxPrintVisitor { void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); } void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); } void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); } - void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right{})", a, b); } + void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right({})", a, b); } void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); } void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); } void constant(Node, RTLIL::Const value) { From 5780357cd91545ddda05a08bf701ac426ac227ed Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sun, 7 Jul 2024 21:01:38 +0200 Subject: [PATCH 124/342] Emit valid SMT for stateful designs, fix some cells --- backends/functional/smtlib.cc | 477 +++++++++++------- tests/functional/.gitignore | 2 +- tests/functional/single_cells/run-test.sh | 6 + .../single_cells/vcd_harness_smt.py | 4 +- 4 files changed, 306 insertions(+), 183 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 55efc83c1..c496b5375 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -23,264 +23,379 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -const char illegal_characters[] = "$\\"; +const char illegal_characters[] = "#:\\"; const char *reserved_keywords[] = {}; struct SmtScope { - pool used_names; - dict name_map; - FunctionalTools::Scope scope; - SmtScope() : scope(illegal_characters, reserved_keywords) {} + pool used_names; + dict name_map; + FunctionalTools::Scope scope; + SmtScope() : scope(illegal_characters, reserved_keywords) {} - void reserve(const std::string &name) { used_names.insert(name); } + void reserve(const std::string &name) { used_names.insert(name); } - std::string insert(IdString id) - { - std::string name = RTLIL::unescape_id(id); - if (used_names.count(name) == 0) { - used_names.insert(name); - name_map[id] = name; - return name; - } - for (int idx = 0;; ++idx) { - std::string new_name = name + "_" + std::to_string(idx); - if (used_names.count(new_name) == 0) { - used_names.insert(new_name); - name_map[id] = new_name; - return new_name; - } - } - } + std::string insert(IdString id) + { - std::string operator[](IdString id) - { - if (name_map.count(id)) { - return name_map[id]; - } else { - return insert(id); - } - } + std::string name = scope(id); + if (used_names.count(name) == 0) { + used_names.insert(name); + name_map[id] = name; + return name; + } + for (int idx = 0;; ++idx) { + std::string new_name = name + "_" + std::to_string(idx); + if (used_names.count(new_name) == 0) { + used_names.insert(new_name); + name_map[id] = new_name; + return new_name; + } + } + } + + std::string operator[](IdString id) + { + if (name_map.count(id)) { + return name_map[id]; + } else { + return insert(id); + } + } }; struct SmtWriter { - std::ostream &stream; + std::ostream &stream; - SmtWriter(std::ostream &out) : stream(out) {} + SmtWriter(std::ostream &out) : stream(out) {} - void print(const char *fmt, ...) - { - va_list args; - va_start(args, fmt); - stream << vstringf(fmt, args); - va_end(args); - } + void print(const char *fmt, ...) + { + va_list args; + va_start(args, fmt); + stream << vstringf(fmt, args); + va_end(args); + } }; template struct SmtPrintVisitor { - using Node = FunctionalIR::Node; - NodeNames np; - SmtScope &scope; + using Node = FunctionalIR::Node; + NodeNames np; + SmtScope &scope; - SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {} + SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {} - template std::string arg_to_string(T n) { return std::to_string(n); } + template std::string arg_to_string(T n) { return std::to_string(n); } - std::string arg_to_string(std::string n) { return n; } + std::string arg_to_string(std::string n) { return n; } - std::string arg_to_string(Node n) { return np(n); } + std::string arg_to_string(Node n) { return np(n); } - template std::string format(std::string fmt, Args &&...args) - { - std::vector arg_strings = {arg_to_string(std::forward(args))...}; - for (size_t i = 0; i < arg_strings.size(); ++i) { - std::string placeholder = "%" + std::to_string(i); - size_t pos = 0; - while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { - fmt.replace(pos, placeholder.length(), arg_strings[i]); - pos += arg_strings[i].length(); - } - } - return fmt; - } - std::string buf(Node, Node n) { return np(n); } + template std::string format(std::string fmt, Args &&...args) + { + std::vector arg_strings = {arg_to_string(std::forward(args))...}; + for (size_t i = 0; i < arg_strings.size(); ++i) { + std::string placeholder = "%" + std::to_string(i); + size_t pos = 0; + while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { + fmt.replace(pos, placeholder.length(), arg_strings[i]); + pos += arg_strings[i].length(); + } + } + return fmt; + } + std::string buf(Node, Node n) { return np(n); } - std::string slice(Node, Node a, int, int offset, int out_width) - { - return format("(_ extract %1 %2 %0)", np(a), offset, offset + out_width - 1); - } + std::string slice(Node, Node a, int, int offset, int out_width) + { + return format("((_ extract %2 %1) %0)", np(a), offset, offset + out_width - 1); + } - std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); } + std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); } - std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); } + std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); } - std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); } + std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); } - std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); } + std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); } - std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); } + std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); } - std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); } + std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); } - std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); } + std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); } - std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); } + std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); } - std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); } + std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); } - std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); } + std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); } - std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); } + std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); } - std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); } + std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); } - std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); } + std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); } - std::string reduce_and(Node, Node a, int) { return format("(= %0 #b1)", np(a)); } + std::string reduce_and(Node, Node a, int) { + std::stringstream ss; + // We use ite to set the result to bit vector, to ensure appropriate type + ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '1') << ") #b1 #b0)"; + return ss.str(); + } + + std::string reduce_or(Node, Node a, int) + { + std::stringstream ss; + // We use ite to set the result to bit vector, to ensure appropriate type + ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; + return ss.str(); + } - std::string reduce_or(Node, Node a, int) - { - std::stringstream ss; - // We use ite to set the result to bit vector, to ensure appropriate type - ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; - return ss.str(); - } + std::string reduce_xor(Node, Node a, int) { + std::stringstream ss; + ss << "(bvxor "; + for (int i = 0; i < a.width(); ++i) { + if (i > 0) ss << " "; + ss << "((_ extract " << i << " " << i << ") " << np(a) << ")"; + } + ss << ")"; + return ss.str(); + } + + std::string equal(Node, Node a, Node b, int) { + return format("(ite (= %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string reduce_xor(Node, Node a, int) { return format("(bvxor_reduce %0)", np(a)); } + std::string not_equal(Node, Node a, Node b, int) { + return format("(ite (distinct %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string equal(Node, Node a, Node b, int) { return format("(= %0 %1)", np(a), np(b)); } + std::string signed_greater_than(Node, Node a, Node b, int) { + return format("(ite (bvsgt %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string not_equal(Node, Node a, Node b, int) { return format("(distinct %0 %1)", np(a), np(b)); } + std::string signed_greater_equal(Node, Node a, Node b, int) { + return format("(ite (bvsge %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string signed_greater_than(Node, Node a, Node b, int) { return format("(bvsgt %0 %1)", np(a), np(b)); } + std::string unsigned_greater_than(Node, Node a, Node b, int) { + return format("(ite (bvugt %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string signed_greater_equal(Node, Node a, Node b, int) { return format("(bvsge %0 %1)", np(a), np(b)); } + std::string unsigned_greater_equal(Node, Node a, Node b, int) { + return format("(ite (bvuge %0 %1) #b1 #b0)", np(a), np(b)); + } - std::string unsigned_greater_than(Node, Node a, Node b, int) { return format("(bvugt %0 %1)", np(a), np(b)); } + std::string logical_shift_left(Node, Node a, Node b, int, int) { + // Get the bit-widths of a and b + int bit_width_a = a.width(); + int bit_width_b = b.width(); - std::string unsigned_greater_equal(Node, Node a, Node b, int) { return format("(bvuge %0 %1)", np(a), np(b)); } + // Extend b to match the bit-width of a if necessary + std::ostringstream oss; + if (bit_width_a > bit_width_b) { + oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; + } else { + oss << np(b); // No extension needed if b's width is already sufficient + } + std::string b_extended = oss.str(); - std::string logical_shift_left(Node, Node a, Node b, int, int) { return format("(bvshl %0 %1)", np(a), np(b)); } + // Format the bvshl operation with the extended b + oss.str(""); // Clear the stringstream + oss << "(bvshl " << np(a) << " " << b_extended << ")"; + return oss.str(); + } - std::string logical_shift_right(Node, Node a, Node b, int, int) { return format("(bvlshr %0 %1)", np(a), np(b)); } + std::string logical_shift_right(Node, Node a, Node b, int, int) { + // Get the bit-widths of a and b + int bit_width_a = a.width(); + int bit_width_b = b.width(); - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return format("(bvashr %0 %1)", np(a), np(b)); } + // Extend b to match the bit-width of a if necessary + std::ostringstream oss; + if (bit_width_a > bit_width_b) { + oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; + } else { + oss << np(b); // No extension needed if b's width is already sufficient + } + std::string b_extended = oss.str(); - std::string mux(Node, Node a, Node b, Node s, int) { return format("(ite %2 %0 %1)", np(a), np(b), np(s)); } + // Format the bvlshr operation with the extended b + oss.str(""); // Clear the stringstream + oss << "(bvlshr " << np(a) << " " << b_extended << ")"; + return oss.str(); + } - std::string pmux(Node, Node a, Node b, Node s, int, int) - { - // Assume s is a bit vector, combine a and b based on the selection bits - return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); - } + std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { + // Get the bit-widths of a and b + int bit_width_a = a.width(); + int bit_width_b = b.width(); - std::string constant(Node, RTLIL::Const value) { return format("#b%1", value.as_string()); } + // Extend b to match the bit-width of a if necessary + std::ostringstream oss; + if (bit_width_a > bit_width_b) { + oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; + } else { + oss << np(b); // No extension needed if b's width is already sufficient + } + std::string b_extended = oss.str(); - std::string input(Node, IdString name) { return format("%0", scope[name]); } + // Format the bvashr operation with the extended b + oss.str(""); // Clear the stringstream + oss << "(bvashr " << np(a) << " " << b_extended << ")"; + return oss.str(); + } + + std::string mux(Node, Node a, Node b, Node s, int) { + return format("(ite (= %2 #b1) %0 %1)", np(a), np(b), np(s)); + } - std::string state(Node, IdString name) { return format("%0", scope[name]); } + std::string pmux(Node, Node a, Node b, Node s, int, int) + { + // Assume s is a bit vector, combine a and b based on the selection bits + return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); + } - std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); } + std::string constant(Node, RTLIL::Const value) { return format("#b%0", value.as_string()); } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); } + std::string input(Node, IdString name) { return format("%0", scope[name]); } - std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); } + std::string state(Node, IdString name) { return format("(%0 current_state)", scope[name]); } + + std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); } + + std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); } + + std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); } }; struct SmtModule { - std::string name; - SmtScope scope; - FunctionalIR ir; + std::string name; + SmtScope scope; + FunctionalIR ir; - SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} + SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} - void write(std::ostream &out) - { - SmtWriter writer(out); + void write(std::ostream &out) + { + const bool stateful = ir.state().size() != 0; + SmtWriter writer(out); - writer.print("(declare-fun %s () Bool)\n", name.c_str()); - writer.print("(declare-datatypes () ((Inputs (mk_inputs"); - for (const auto &input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); - } - writer.print("))))\n"); + writer.print("(declare-fun %s () Bool)\n\n", name.c_str()); - writer.print("(declare-datatypes () ((Outputs (mk_outputs"); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); - } - writer.print("))))\n"); + writer.print("(declare-datatypes () ((Inputs (mk_inputs"); + for (const auto &input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); + } + writer.print("))))\n\n"); - writer.print("(declare-fun state () (_ BitVec 1))\n"); + writer.print("(declare-datatypes () ((Outputs (mk_outputs"); + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); + } + writer.print("))))\n"); - writer.print("(define-fun %s_step ((state (_ BitVec 1)) (inputs Inputs)) Outputs", name.c_str()); - writer.print(" (let ("); - for (const auto &input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str()); - } - writer.print(" )"); + if (stateful) { + writer.print("(declare-datatypes () ((State (mk_state"); + for (const auto &state : ir.state()) { + std::string state_name = scope[state.first]; + writer.print(" (%s (_ BitVec %d))", state_name.c_str(), state.second.width()); + } + writer.print("))))\n"); - auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; - SmtPrintVisitor visitor(node_to_string, scope); + writer.print("(declare-datatypes () ((Pair (mk-pair (outputs Outputs) (next_state State)))))\n"); + } - for (auto it = ir.begin(); it != ir.end(); ++it) { - const FunctionalIR::Node &node = *it; + if (stateful) + writer.print("(define-fun %s_step ((current_state State) (inputs Inputs)) Pair", name.c_str()); + else + writer.print("(define-fun %s_step ((inputs Inputs)) Outputs", name.c_str()); - if (ir.inputs().count(node.name()) > 0) - continue; + writer.print(" (let ("); + for (const auto &input : ir.inputs()) { + std::string input_name = scope[input.first]; + writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str()); + } + writer.print(" )"); - std::string node_name = scope[node.name()]; - std::string node_expr = node.visit(visitor); + auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; + SmtPrintVisitor visitor(node_to_string, scope); - writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str()); - } + for (auto it = ir.begin(); it != ir.end(); ++it) { + const FunctionalIR::Node &node = *it; - writer.print(" (let ("); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - const std::string output_assignment = ir.get_output_node(output.first).name().c_str(); - writer.print(" (%s %s)", output_name.c_str(), output_assignment.substr(1).c_str()); - } - writer.print(" )"); - writer.print(" (mk_outputs"); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" %s", output_name.c_str()); - } - writer.print(" )"); - writer.print(" )"); + if (ir.inputs().count(node.name()) > 0) + continue; - // Close the nested lets - for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { - writer.print(" )"); - } + std::string node_name = scope[node.name()]; + std::string node_expr = node.visit(visitor); - writer.print(" )"); - writer.print(")\n"); - } + writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str()); + } + + if (stateful) { + writer.print(" (let ( (next_state (mk_state "); + for (const auto &state : ir.state()) { + std::string state_name = scope[state.first]; + const std::string state_assignment = ir.get_state_next_node(state.first).name().c_str(); + writer.print(" %s", state_assignment.substr(1).c_str()); + } + writer.print(" )))"); + } + + if (stateful) { + writer.print(" (let ( (outputs (mk_outputs "); + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" %s", output_name.c_str()); + } + writer.print(" )))"); + + writer.print("(mk-pair outputs next_state)"); + } + else { + writer.print(" (mk_outputs "); + for (const auto &output : ir.outputs()) { + std::string output_name = scope[output.first]; + writer.print(" %s", output_name.c_str()); + } + writer.print(" )"); // Closing mk_outputs + } + if (stateful) { + writer.print(" )"); // Closing outputs let statement + writer.print(" )"); // Closing next_state let statement + } + // Close the nested lets + for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { + writer.print(" )"); // Closing each node + } + + writer.print(" )"); // Closing inputs let statement + writer.print(")\n"); // Closing step function + } }; struct FunctionalSmtBackend : public Backend { - FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} + FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} - void help() override { log("\nFunctional SMT Backend.\n\n"); } + void help() override { log("\nFunctional SMT Backend.\n\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Functional SMT Backend.\n"); + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional SMT Backend.\n"); - size_t argidx = 1; - extra_args(f, filename, args, argidx, design); + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); - for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); - auto ir = FunctionalIR::from_module(module); - SmtModule smt(RTLIL::unescape_id(module->name), ir); - smt.write(*f); - } - } + for (auto module : design->selected_modules()) { + log("Processing module `%s`.\n", module->name.c_str()); + auto ir = FunctionalIR::from_module(module); + SmtModule smt(RTLIL::unescape_id(module->name), ir); + smt.write(*f); + } + } } FunctionalSmtBackend; PRIVATE_NAMESPACE_END diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore index 8b20fbedf..1ffe9926e 100644 --- a/tests/functional/.gitignore +++ b/tests/functional/.gitignore @@ -2,4 +2,4 @@ my_module_cxxrtl.cc my_module_functional_cxx.cc vcd_harness *.vcd -*.smt2 \ No newline at end of file +*.smt2 diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh index 11ff1b5ce..cc6bcf160 100755 --- a/tests/functional/single_cells/run-test.sh +++ b/tests/functional/single_cells/run-test.sh @@ -87,6 +87,10 @@ run_smt_test() { run_all_tests() { + declare -A cxx_failing_files + declare -A smt_failing_files + declare -A cxx_successful_files + declare -A smt_successful_files return_code=0 for rtlil_file in rtlil/*.il; do run_cxx_test "$rtlil_file" @@ -134,6 +138,8 @@ run_all_tests() { } run_smt_tests() { + declare -A smt_failing_files + declare -A smt_successful_files return_code=0 for rtlil_file in rtlil/*.il; do run_smt_test "$rtlil_file" diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py index fd5e94f7e..88973eae0 100644 --- a/tests/functional/single_cells/vcd_harness_smt.py +++ b/tests/functional/single_cells/vcd_harness_smt.py @@ -76,6 +76,8 @@ for lst in parsed_results: declarations = datatype_group[1][1:] # Skip the first item (e.g., 'mk_inputs') if datatype_name == 'Inputs': for declaration in declarations: + print("My declaration") + print(declaration) input_name = declaration[0] bitvec_size = declaration[1][2] inputs[input_name] = int(bitvec_size) @@ -103,7 +105,7 @@ def set_step(inputs, step): define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n" # Create the output definition by calling the gold_step function - define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step #b0 test_inputs_step_n{step}))\n" + define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step test_inputs_step_n{step}))\n" smt_commands = [] smt_commands.append(define_inputs) smt_commands.append(define_output) From fad76ce67785c519ca6ed982a7916ccebf5f5411 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sun, 7 Jul 2024 21:12:47 +0200 Subject: [PATCH 125/342] Fix memory leak --- backends/functional/smtlib.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index c496b5375..bc1253b88 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN const char illegal_characters[] = "#:\\"; -const char *reserved_keywords[] = {}; +const char *reserved_keywords[] = {nullptr}; struct SmtScope { pool used_names; From 7cff8fa3a31e999aa16a3f4ab25894939d08bb70 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Sun, 7 Jul 2024 21:29:33 +0200 Subject: [PATCH 126/342] Fix corner case of pos cell with input and output being same width --- backends/functional/smtlib.cc | 4 +++- .../single_cells/rtlil/test_cell_pos_00001.il | 13 +++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 tests/functional/single_cells/rtlil/test_cell_pos_00001.il diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index bc1253b88..501d195eb 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -277,7 +277,7 @@ struct SmtModule { SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} void write(std::ostream &out) - { + { const bool stateful = ir.state().size() != 0; SmtWriter writer(out); @@ -371,6 +371,8 @@ struct SmtModule { for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { writer.print(" )"); // Closing each node } + if (ir.size() == ir.inputs().size()) + writer.print(" )"); // Corner case writer.print(" )"); // Closing inputs let statement writer.print(")\n"); // Closing step function diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il new file mode 100644 index 000000000..96e9c895a --- /dev/null +++ b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il @@ -0,0 +1,13 @@ +# Generated by Yosys 0.40+7 (git sha1 d8b5b90e7, g++ 13.2.0 -Og -fPIC) +autoidx 1 +module \gold + wire width 6 input 1 \A + wire width 6 output 2 \Y + cell $pos \UUT + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \A + connect \Y \Y + end +end From 566e57d24f45dbffec8b40a58d1ef15b45b9bb52 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 8 Jul 2024 00:07:07 +0200 Subject: [PATCH 127/342] Support $lut cells. Both C++ and SMT tests pass --- kernel/functionalir.cc | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 6498ef636..c5406f412 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -248,9 +248,31 @@ public: return extend(factory.unsigned_div(a, b, width), width, y_width, false); } } else if(cellType == ID($pow)) { - return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); + return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); + } else if (cellType == ID($lut)) { + int width = parameters.at(ID(WIDTH)).as_int(); + Const lut_table = parameters.at(ID(LUT)); + T a = inputs.at(ID(A)); + + // Output initialization + T y = factory.constant(Const(0, 1)); + + // Iterate over each possible input combination + for (int i = 0; i < (1 << width); ++i) { + // Create a constant representing the value of i + T i_val = factory.constant(Const(i, width)); + // Check if the input matches this value + T match = factory.equal(a, i_val, width); + // Get the corresponding LUT value + bool lut_val = lut_table.bits[i] == State::S1; + T lut_output = factory.constant(Const(lut_val, 1)); + // Use a multiplexer to select the correct output based on the match + y = factory.mux(y, lut_output, match, 1); + } + + return y; } else{ - log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } } }; From 80582ed3afb7ebbfe1372dd97f57062b68c1eb79 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 8 Jul 2024 18:29:58 +0200 Subject: [PATCH 128/342] Check the existance of a different set of outputs. No need for (push 1) nor (pop 1) --- .../single_cells/rtlil/multiple_outputs.il | 69 +++++++++++++++++++ .../single_cells/vcd_harness_smt.py | 28 ++++---- 2 files changed, 82 insertions(+), 15 deletions(-) create mode 100644 tests/functional/single_cells/rtlil/multiple_outputs.il diff --git a/tests/functional/single_cells/rtlil/multiple_outputs.il b/tests/functional/single_cells/rtlil/multiple_outputs.il new file mode 100644 index 000000000..5e9141a20 --- /dev/null +++ b/tests/functional/single_cells/rtlil/multiple_outputs.il @@ -0,0 +1,69 @@ +# Generated by Yosys 0.40+7 (git sha1 cc795a3f5, g++ 13.2.0 -Og -fPIC) +autoidx 5 +attribute \cells_not_processed 1 +attribute \src "multiple_outputs.v:1.1-15.10" +module \gold + attribute \src "multiple_outputs.v:11.12-11.20" + wire $and$multiple_outputs.v:11$2_Y + attribute \src "multiple_outputs.v:10.12-10.14" + wire $not$multiple_outputs.v:10$1_Y + attribute \src "multiple_outputs.v:12.12-12.20" + wire $or$multiple_outputs.v:12$3_Y + attribute \src "multiple_outputs.v:13.12-13.20" + wire $xor$multiple_outputs.v:13$4_Y + attribute \src "multiple_outputs.v:2.16-2.17" + wire input 1 \a + attribute \src "multiple_outputs.v:3.17-3.18" + wire output 2 \b + attribute \src "multiple_outputs.v:4.17-4.18" + wire output 3 \c + attribute \src "multiple_outputs.v:5.17-5.18" + wire output 4 \d + attribute \src "multiple_outputs.v:6.17-6.18" + wire output 5 \e + attribute \src "multiple_outputs.v:11.12-11.20" + cell $and $and$multiple_outputs.v:11$2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a + connect \B 1'1 + connect \Y $and$multiple_outputs.v:11$2_Y + end + attribute \src "multiple_outputs.v:10.12-10.14" + cell $not $not$multiple_outputs.v:10$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a + connect \Y $not$multiple_outputs.v:10$1_Y + end + attribute \src "multiple_outputs.v:12.12-12.20" + cell $or $or$multiple_outputs.v:12$3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a + connect \B 1'0 + connect \Y $or$multiple_outputs.v:12$3_Y + end + attribute \src "multiple_outputs.v:13.12-13.20" + cell $xor $xor$multiple_outputs.v:13$4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a + connect \B 1'1 + connect \Y $xor$multiple_outputs.v:13$4_Y + end + connect \b $not$multiple_outputs.v:10$1_Y + connect \c $and$multiple_outputs.v:11$2_Y + connect \d $or$multiple_outputs.v:12$3_Y + connect \e $xor$multiple_outputs.v:13$4_Y +end diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py index 88973eae0..95947748f 100644 --- a/tests/functional/single_cells/vcd_harness_smt.py +++ b/tests/functional/single_cells/vcd_harness_smt.py @@ -139,9 +139,6 @@ if result != 'sat': smt_io.p_close() sys.exit(1) -value = smt_io.get(f'(Y test_outputs_step_n0)') -print(f" Y: {value}") - # Store signal values signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())} # Retrieve and print values for each state @@ -151,6 +148,8 @@ def hex_to_bin(value): bin_value = bin(int(hex_value, 16))[2:] # Convert to binary and remove the '0b' prefix return f'b{bin_value.zfill(len(hex_value) * 4)}' # Add 'b' prefix and pad with zeros return value + +combined_assertions = [] for step in range(num_steps): print(f"Values for step {step + 1}:") for input_name, width in inputs.items(): @@ -163,18 +162,17 @@ for step in range(num_steps): value = hex_to_bin(value[1:]) print(f" {output_name}: {value}") signals[output_name].append((step, value)) - smt_io.write(f'(push 1)') - smt_io.write(f'(assert (not (= ({output_name} test_outputs_step_n{step}) #{value})))') - result = smt_io.check_sat(["unsat"]) - if result != 'unsat': - smt_io.p_close() - sys.exit(1) - smt_io.write(f'(pop 1)') - result = smt_io.check_sat(["sat"]) - if result != 'sat': - smt_io.p_close() - sys.exit(1) - + combined_assertions.append(f'(= ({output_name} test_outputs_step_n{step}) #{value})') +# Create a single assertion covering all timesteps +combined_condition = " ".join(combined_assertions) +smt_io.write(f'(assert (not (and {combined_condition})))') + +# Check the combined assertion +result = smt_io.check_sat(["unsat"]) +if result != 'unsat': + smt_io.p_close() + sys.exit(1) + smt_io.p_close() def write_vcd(filename, signals, timescale='1 ns', date='today'): From 9f660b1e4bf125db23d7f5c494d3c5f9fd715ee7 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 10 Jul 2024 14:28:48 +0100 Subject: [PATCH 129/342] rewrite smtlib pass to use SExpr class --- backends/functional/cxx.cc | 28 +- backends/functional/smtlib.cc | 703 +++++++++++++++++----------------- kernel/functionalir.h | 45 +-- 3 files changed, 398 insertions(+), 378 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 1d8caaaf4..4ab9d53a1 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -19,11 +19,11 @@ #include "kernel/yosys.h" #include "kernel/functionalir.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -const char illegal_characters[] = "!\"#%&'()*+,-./:;<=>?@[]\\^`{|}~ "; const char *reserved_keywords[] = { "alignas","alignof","and","and_eq","asm","atomic_cancel","atomic_commit", "atomic_noexcept","auto","bitand","bitor","bool","break","case", @@ -42,6 +42,16 @@ const char *reserved_keywords[] = { nullptr }; +template struct CxxScope : public FunctionalTools::Scope { + CxxScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + this->reserve(*p); + } + bool is_character_legal(char c) override { + return isascii(c) && (isalnum(c) || c == '_' || c == '$'); + } +}; + struct CxxType { FunctionalIR::Sort sort; CxxType(FunctionalIR::Sort sort) : sort(sort) {} @@ -61,30 +71,30 @@ using CxxWriter = FunctionalTools::Writer; struct CxxStruct { std::string name; dict types; - FunctionalTools::Scope scope; + CxxScope scope; CxxStruct(std::string name) - : name(name), scope(illegal_characters, reserved_keywords) { + : name(name) { scope.reserve("fn"); scope.reserve("visit"); } void insert(IdString name, CxxType type) { - scope(name); + scope(name, name); types.insert({name, type}); } void print(CxxWriter &f) { f.print("\tstruct {} {{\n", name); for (auto p : types) { - f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first)); + f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first)); } f.print("\n\t\ttemplate void visit(T &&fn) {{\n"); for (auto p : types) { - f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first)); + f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first)); } f.print("\t\t}}\n"); f.print("\t}};\n\n"); }; std::string operator[](IdString field) { - return scope(field); + return scope(field, field); } }; @@ -165,7 +175,7 @@ struct CxxModule { output_struct.insert(name, sort); for (auto [name, sort] : ir.state()) state_struct.insert(name, sort); - module_name = FunctionalTools::Scope(illegal_characters, reserved_keywords)(module->name); + module_name = CxxScope().unique_name(module->name); } void write_header(CxxWriter &f) { f.print("#include \"sim.h\"\n\n"); @@ -180,7 +190,7 @@ struct CxxModule { } void write_eval_def(CxxWriter &f) { f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const ¤t_state, {0}::State &next_state)\n{{\n", module_name); - FunctionalTools::Scope locals(illegal_characters, reserved_keywords); + CxxScope locals; locals.reserve("input"); locals.reserve("output"); locals.reserve("current_state"); diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 501d195eb..c3e159eb3 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -19,385 +19,406 @@ #include "kernel/functionalir.h" #include "kernel/yosys.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -const char illegal_characters[] = "#:\\"; -const char *reserved_keywords[] = {nullptr}; +const char *reserved_keywords[] = { + "BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par", + "assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes", + "declare-fun", "declare-sort", "define-fun", "define-fun-rec", "define-funs-rec", "define-sort", + "exit", "get-assertions", "symbol", "sort", "get-assignment", "get-info", "get-model", + "get-option", "get-proof", "get-unsat-assumptions", "get-unsat-core", "get-value", + "pop", "push", "reset", "reset-assertions", "set-info", "set-logic", "set-option", -struct SmtScope { - pool used_names; - dict name_map; - FunctionalTools::Scope scope; - SmtScope() : scope(illegal_characters, reserved_keywords) {} - - void reserve(const std::string &name) { used_names.insert(name); } - - std::string insert(IdString id) - { - - std::string name = scope(id); - if (used_names.count(name) == 0) { - used_names.insert(name); - name_map[id] = name; - return name; - } - for (int idx = 0;; ++idx) { - std::string new_name = name + "_" + std::to_string(idx); - if (used_names.count(new_name) == 0) { - used_names.insert(new_name); - name_map[id] = new_name; - return new_name; - } - } - } - - std::string operator[](IdString id) - { - if (name_map.count(id)) { - return name_map[id]; - } else { - return insert(id); - } - } + "pair", "Pair", "first", "second", + "inputs", "state", + nullptr }; -struct SmtWriter { - std::ostream &stream; - - SmtWriter(std::ostream &out) : stream(out) {} - - void print(const char *fmt, ...) - { - va_list args; - va_start(args, fmt); - stream << vstringf(fmt, args); - va_end(args); - } +struct SmtScope : public FunctionalTools::Scope { + SmtScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + bool is_character_legal(char c) override { + return isascii(c) && (isalnum(c) || strchr("~!@$%^&*_-+=<>.?/", c)); + } }; -template struct SmtPrintVisitor { - using Node = FunctionalIR::Node; - NodeNames np; - SmtScope &scope; +class SExpr { + std::variant, std::string> _v; +public: + SExpr(std::string a) : _v(std::move(a)) {} + SExpr(const char *a) : _v(a) {} + SExpr(int n) : _v(std::to_string(n)) {} + SExpr(std::vector const &a) : _v(std::in_place_index<0>, a) {} + SExpr(std::vector &&a) : _v(std::in_place_index<0>, std::move(a)) {} + SExpr(std::initializer_list a) : _v(std::in_place_index<0>, a) {} + bool is_atom() const { return std::holds_alternative(_v); } + std::string const &atom() const { return std::get(_v); } + bool is_list() const { return std::holds_alternative>(_v); } + std::vector const &list() const { return std::get>(_v); } + friend std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) { + if(sexpr.is_atom()) + os << sexpr.atom(); + else if(sexpr.is_list()){ + os << "("; + auto l = sexpr.list(); + for(size_t i = 0; i < l.size(); i++) { + if(i > 0) os << " "; + os << l[i]; + } + os << ")"; + }else + os << ""; + return os; + } + std::string to_string() const { + std::stringstream ss; + ss << *this; + return ss.str(); + } +}; - SmtPrintVisitor(NodeNames np, SmtScope &scope) : np(np), scope(scope) {} - - template std::string arg_to_string(T n) { return std::to_string(n); } - - std::string arg_to_string(std::string n) { return n; } - - std::string arg_to_string(Node n) { return np(n); } - - template std::string format(std::string fmt, Args &&...args) - { - std::vector arg_strings = {arg_to_string(std::forward(args))...}; - for (size_t i = 0; i < arg_strings.size(); ++i) { - std::string placeholder = "%" + std::to_string(i); - size_t pos = 0; - while ((pos = fmt.find(placeholder, pos)) != std::string::npos) { - fmt.replace(pos, placeholder.length(), arg_strings[i]); - pos += arg_strings[i].length(); - } +class SExprWriter { + std::ostream &os; + int _max_line_width; + int _indent = 0; + int _pos = 0; + bool _pending_nl = false; + vector _unclosed; + vector _unclosed_stack; + void nl_if_pending() { + if(_pending_nl) { + os << '\n'; + _pos = 0; + _pending_nl = false; + } + } + void puts(std::string const &s) { + if(s.empty()) return; + nl_if_pending(); + for(auto c : s) { + if(c == '\n') { + os << c; + _pos = 0; + } else { + if(_pos == 0) { + for(int i = 0; i < _indent; i++) + os << " "; + _pos = 2 * _indent; + } + os << c; + _pos++; + } + } } - return fmt; - } - std::string buf(Node, Node n) { return np(n); } - - std::string slice(Node, Node a, int, int offset, int out_width) - { - return format("((_ extract %2 %1) %0)", np(a), offset, offset + out_width - 1); - } - - std::string zero_extend(Node, Node a, int, int out_width) { return format("((_ zero_extend %1) %0)", np(a), out_width - a.width()); } - - std::string sign_extend(Node, Node a, int, int out_width) { return format("((_ sign_extend %1) %0)", np(a), out_width - a.width()); } - - std::string concat(Node, Node a, int, Node b, int) { return format("(concat %0 %1)", np(a), np(b)); } - - std::string add(Node, Node a, Node b, int) { return format("(bvadd %0 %1)", np(a), np(b)); } - - std::string sub(Node, Node a, Node b, int) { return format("(bvsub %0 %1)", np(a), np(b)); } - - std::string mul(Node, Node a, Node b, int) { return format("(bvmul %0 %1)", np(a), np(b)); } - - std::string unsigned_div(Node, Node a, Node b, int) { return format("(bvudiv %0 %1)", np(a), np(b)); } - - std::string unsigned_mod(Node, Node a, Node b, int) { return format("(bvurem %0 %1)", np(a), np(b)); } - - std::string bitwise_and(Node, Node a, Node b, int) { return format("(bvand %0 %1)", np(a), np(b)); } - - std::string bitwise_or(Node, Node a, Node b, int) { return format("(bvor %0 %1)", np(a), np(b)); } - - std::string bitwise_xor(Node, Node a, Node b, int) { return format("(bvxor %0 %1)", np(a), np(b)); } - - std::string bitwise_not(Node, Node a, int) { return format("(bvnot %0)", np(a)); } - - std::string unary_minus(Node, Node a, int) { return format("(bvneg %0)", np(a)); } - - std::string reduce_and(Node, Node a, int) { - std::stringstream ss; - // We use ite to set the result to bit vector, to ensure appropriate type - ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '1') << ") #b1 #b0)"; - return ss.str(); - } - - std::string reduce_or(Node, Node a, int) - { - std::stringstream ss; - // We use ite to set the result to bit vector, to ensure appropriate type - ss << "(ite (= " << np(a) << " #b" << std::string(a.width(), '0') << ") #b0 #b1)"; - return ss.str(); - } - - std::string reduce_xor(Node, Node a, int) { - std::stringstream ss; - ss << "(bvxor "; - for (int i = 0; i < a.width(); ++i) { - if (i > 0) ss << " "; - ss << "((_ extract " << i << " " << i << ") " << np(a) << ")"; + int width(SExpr const &sexpr) { + if(sexpr.is_atom()) + return sexpr.atom().size(); + else if(sexpr.is_list()) { + int w = 2; + for(auto arg : sexpr.list()) + w += width(arg); + if(sexpr.list().size() > 1) + w += sexpr.list().size() - 1; + return w; + } else + return 0; } - ss << ")"; - return ss.str(); - } - - std::string equal(Node, Node a, Node b, int) { - return format("(ite (= %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string not_equal(Node, Node a, Node b, int) { - return format("(ite (distinct %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string signed_greater_than(Node, Node a, Node b, int) { - return format("(ite (bvsgt %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string signed_greater_equal(Node, Node a, Node b, int) { - return format("(ite (bvsge %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string unsigned_greater_than(Node, Node a, Node b, int) { - return format("(ite (bvugt %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string unsigned_greater_equal(Node, Node a, Node b, int) { - return format("(ite (bvuge %0 %1) #b1 #b0)", np(a), np(b)); - } - - std::string logical_shift_left(Node, Node a, Node b, int, int) { - // Get the bit-widths of a and b - int bit_width_a = a.width(); - int bit_width_b = b.width(); - - // Extend b to match the bit-width of a if necessary - std::ostringstream oss; - if (bit_width_a > bit_width_b) { - oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; - } else { - oss << np(b); // No extension needed if b's width is already sufficient + void print(SExpr const &sexpr, bool close = true, bool indent_rest = true) { + if(sexpr.is_atom()) + puts(sexpr.atom()); + else if(sexpr.is_list()) { + auto args = sexpr.list(); + puts("("); + bool vertical = args.size() > 1 && _pos + width(sexpr) > _max_line_width; + if(vertical) _indent++; + for(size_t i = 0; i < args.size(); i++) { + if(i > 0) puts(vertical ? "\n" : " "); + print(args[i]); + } + _indent += (!close && indent_rest) - vertical; + if(close) + puts(")"); + else { + _unclosed.push_back(indent_rest); + _pending_nl = true; + } + }else + log_error("shouldn't happen in SExprWriter::print"); } - std::string b_extended = oss.str(); - - // Format the bvshl operation with the extended b - oss.str(""); // Clear the stringstream - oss << "(bvshl " << np(a) << " " << b_extended << ")"; - return oss.str(); - } - - std::string logical_shift_right(Node, Node a, Node b, int, int) { - // Get the bit-widths of a and b - int bit_width_a = a.width(); - int bit_width_b = b.width(); - - // Extend b to match the bit-width of a if necessary - std::ostringstream oss; - if (bit_width_a > bit_width_b) { - oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; - } else { - oss << np(b); // No extension needed if b's width is already sufficient +public: + SExprWriter(std::ostream &os, int max_line_width = 80) + : os(os) + , _max_line_width(max_line_width) + {} + void open(SExpr const &sexpr, bool indent_rest = true) { + log_assert(sexpr.is_list()); + print(sexpr, false, indent_rest); } - std::string b_extended = oss.str(); - - // Format the bvlshr operation with the extended b - oss.str(""); // Clear the stringstream - oss << "(bvlshr " << np(a) << " " << b_extended << ")"; - return oss.str(); - } - - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { - // Get the bit-widths of a and b - int bit_width_a = a.width(); - int bit_width_b = b.width(); - - // Extend b to match the bit-width of a if necessary - std::ostringstream oss; - if (bit_width_a > bit_width_b) { - oss << "((_ zero_extend " << (bit_width_a - bit_width_b) << ") " << np(b) << ")"; - } else { - oss << np(b); // No extension needed if b's width is already sufficient + void close(size_t n = 1) { + log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n); + while(n-- > 0) { + bool indented = _unclosed[_unclosed.size() - 1]; + _unclosed.pop_back(); + _pending_nl = _pos >= _max_line_width; + if(indented) + _indent--; + puts(")"); + _pending_nl = true; + } } - std::string b_extended = oss.str(); + void push() { + _unclosed_stack.push_back(_unclosed.size()); + } + void pop() { + auto t = _unclosed_stack.back(); + log_assert(_unclosed.size() >= t); + close(_unclosed.size() - t); + _unclosed_stack.pop_back(); + } + SExprWriter &operator <<(SExpr const &sexpr) { + print(sexpr); + _pending_nl = true; + return *this; + } + void comment(std::string const &str, bool hanging = false) { + if(hanging) { + if(_pending_nl) { + _pending_nl = false; + puts(" "); + } + } + puts("; "); + puts(str); + puts("\n"); + } + ~SExprWriter() { + while(!_unclosed_stack.empty()) + pop(); + close(_unclosed.size()); + nl_if_pending(); + } +}; - // Format the bvashr operation with the extended b - oss.str(""); // Clear the stringstream - oss << "(bvashr " << np(a) << " " << b_extended << ")"; - return oss.str(); - } - - std::string mux(Node, Node a, Node b, Node s, int) { - return format("(ite (= %2 #b1) %0 %1)", np(a), np(b), np(s)); - } +struct SmtSort { + FunctionalIR::Sort sort; + SmtSort(FunctionalIR::Sort sort) : sort(sort) {} + SExpr to_sexpr() const { + if(sort.is_memory()) { + return SExpr{"Array", {"_", "BitVec", sort.addr_width()}, {"_", "BitVec", sort.data_width()}}; + } else if(sort.is_signal()) { + return SExpr{"_", "BitVec", sort.width()}; + } else { + log_error("unknown sort"); + } + } +}; - std::string pmux(Node, Node a, Node b, Node s, int, int) - { - // Assume s is a bit vector, combine a and b based on the selection bits - return format("(pmux %0 %1 %2)", np(a), np(b), np(s)); - } +class SmtStruct { + struct Field { + SmtSort sort; + std::string accessor; + }; + idict field_names; + vector fields; + SmtScope &scope; +public: + std::string name; + SmtStruct(std::string name, SmtScope &scope) : scope(scope), name(name) {} + void insert(IdString field_name, SmtSort sort) { + field_names(field_name); + auto accessor = scope.unique_name("\\" + name + "_" + RTLIL::unescape_id(field_name)); + fields.emplace_back(Field{sort, accessor}); + } + void write_definition(SExprWriter &w) { + w.open(SExpr{"declare-datatype", name}); + w.open(SExpr({})); + w.open(SExpr{name}); + for(const auto &field : fields) + w << SExpr{field.accessor, field.sort.to_sexpr()}; + w.close(3); + } + template void write_value(SExprWriter &w, Fn fn) { + w.open(SExpr(std::initializer_list{name})); + for(auto field_name : field_names) { + w << fn(field_name); + w.comment(RTLIL::unescape_id(field_name), true); + } + w.close(); + } + SExpr access(SExpr record, IdString name) { + size_t i = field_names.at(name); + return SExpr{fields[i].accessor, std::move(record)}; + } +}; - std::string constant(Node, RTLIL::Const value) { return format("#b%0", value.as_string()); } +struct SmtPrintVisitor { + using Node = FunctionalIR::Node; + std::function n; + SmtStruct &input_struct; + SmtStruct &state_struct; - std::string input(Node, IdString name) { return format("%0", scope[name]); } + SmtPrintVisitor(SmtStruct &input_struct, SmtStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {} - std::string state(Node, IdString name) { return format("(%0 current_state)", scope[name]); } + std::string literal(RTLIL::Const c) { + std::string s = "#b"; + for(int i = c.size(); i-- > 0; ) + s += c[i] == State::S1 ? '1' : '0'; + return s; + } - std::string memory_read(Node, Node mem, Node addr, int, int) { return format("(select %0 %1)", np(mem), np(addr)); } + SExpr from_bool(SExpr &&arg) { + return SExpr{"ite", std::move(arg), "#b1", "#b0"}; + } + SExpr to_bool(SExpr &&arg) { + return SExpr{"=", std::move(arg), "#b1"}; + } + SExpr extract(SExpr &&arg, int offset, int out_width = 1) { + return SExpr{{"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; + } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return format("(store %0 %1 %2)", np(mem), np(addr), np(data)); } + SExpr buf(Node, Node a) { return n(a); } + SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); } + SExpr zero_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "zero_extend", out_width - a.width()}, n(a)}; } + SExpr sign_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "sign_extend", out_width - a.width()}, n(a)}; } + SExpr concat(Node, Node a, int, Node b, int) { return SExpr{"concat", n(a), n(b)}; } + SExpr add(Node, Node a, Node b, int) { return SExpr{"bvadd", n(a), n(b)}; } + SExpr sub(Node, Node a, Node b, int) { return SExpr{"bvsub", n(a), n(b)}; } + SExpr mul(Node, Node a, Node b, int) { return SExpr{"bvmul", n(a), n(b)}; } + SExpr unsigned_div(Node, Node a, Node b, int) { return SExpr{"bvudiv", n(a), n(b)}; } + SExpr unsigned_mod(Node, Node a, Node b, int) { return SExpr{"bvurem", n(a), n(b)}; } + SExpr bitwise_and(Node, Node a, Node b, int) { return SExpr{"bvand", n(a), n(b)}; } + SExpr bitwise_or(Node, Node a, Node b, int) { return SExpr{"bvor", n(a), n(b)}; } + SExpr bitwise_xor(Node, Node a, Node b, int) { return SExpr{"bvxor", n(a), n(b)}; } + SExpr bitwise_not(Node, Node a, int) { return SExpr{"bvnot", n(a)}; } + SExpr unary_minus(Node, Node a, int) { return SExpr{"bvneg", n(a)}; } + SExpr reduce_and(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S1, a.width()))}); } + SExpr reduce_or(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S0, a.width()))}); } + SExpr reduce_xor(Node, Node a, int) { + vector s { "bvxor" }; + for(int i = 0; i < a.width(); i++) + s.push_back(extract(n(a), i)); + return s; + } + SExpr equal(Node, Node a, Node b, int) { return from_bool(SExpr{"=", n(a), n(b)}); } + SExpr not_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"distinct", n(a), n(b)}); } + SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsgt", n(a), n(b)}); } + SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsge", n(a), n(b)}); } + SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvugt", n(a), n(b)}); } + SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvuge", n(a), n(b)}); } - std::string undriven(Node, int width) { return format("#b%0", std::string(width, '0')); } + SExpr extend(SExpr &&a, int in_width, int out_width) { + if(in_width < out_width) + return SExpr{{"_", "zero_extend", out_width - in_width}, std::move(a)}; + else + return std::move(a); + } + SExpr logical_shift_left(Node, Node a, Node b, int, int) { return SExpr{"bvshl", n(a), extend(n(b), b.width(), a.width())}; } + SExpr logical_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvshr", n(a), extend(n(b), b.width(), a.width())}; } + SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvasr", n(a), extend(n(b), b.width(), a.width())}; } + SExpr mux(Node, Node a, Node b, Node s, int) { return SExpr{"ite", to_bool(n(s)), n(a), n(b)}; } + SExpr pmux(Node, Node a, Node b, Node s, int, int) { + SExpr rv = n(a); + for(int i = 0; i < s.width(); i++) + rv = SExpr{"ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv}; + return rv; + } + SExpr constant(Node, RTLIL::Const value) { return literal(value); } + SExpr memory_read(Node, Node mem, Node addr, int, int) { return SExpr{"select", n(mem), n(addr)}; } + SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return SExpr{"store", n(mem), n(addr), n(data)}; } + + SExpr input(Node, IdString name) { return input_struct.access("inputs", name); } + SExpr state(Node, IdString name) { return state_struct.access("state", name); } + + SExpr undriven(Node, int width) { return literal(RTLIL::Const(State::S0, width)); } }; struct SmtModule { - std::string name; - SmtScope scope; - FunctionalIR ir; + FunctionalIR ir; + SmtScope scope; + std::string name; + + SmtStruct input_struct; + SmtStruct output_struct; + SmtStruct state_struct; - SmtModule(const std::string &module_name, FunctionalIR ir) : name(module_name), ir(std::move(ir)) {} + SmtModule(Module *module) + : ir(FunctionalIR::from_module(module)) + , scope() + , name(scope.unique_name(module->name)) + , input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope) + , output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope) + , state_struct(scope.unique_name(module->name.str() + "_State"), scope) + { + for (const auto &input : ir.inputs()) + input_struct.insert(input.first, input.second); + for (const auto &output : ir.outputs()) + output_struct.insert(output.first, output.second); + for (const auto &state : ir.state()) + state_struct.insert(state.first, state.second); + } - void write(std::ostream &out) - { - const bool stateful = ir.state().size() != 0; - SmtWriter writer(out); + void write(std::ostream &out) + { + SExprWriter w(out); - writer.print("(declare-fun %s () Bool)\n\n", name.c_str()); + input_struct.write_definition(w); + output_struct.write_definition(w); + state_struct.write_definition(w); - writer.print("(declare-datatypes () ((Inputs (mk_inputs"); - for (const auto &input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (_ BitVec %d))", input_name.c_str(), input.second.width()); - } - writer.print("))))\n\n"); + w << SExpr{"declare-datatypes", {{"Pair", 2}}, {{"par", {"X", "Y"}, {{"pair", {"first", "X"}, {"second", "Y"}}}}}}; - writer.print("(declare-datatypes () ((Outputs (mk_outputs"); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" (%s (_ BitVec %d))", output_name.c_str(), output.second.width()); - } - writer.print("))))\n"); - - if (stateful) { - writer.print("(declare-datatypes () ((State (mk_state"); - for (const auto &state : ir.state()) { - std::string state_name = scope[state.first]; - writer.print(" (%s (_ BitVec %d))", state_name.c_str(), state.second.width()); - } - writer.print("))))\n"); - - writer.print("(declare-datatypes () ((Pair (mk-pair (outputs Outputs) (next_state State)))))\n"); - } - - if (stateful) - writer.print("(define-fun %s_step ((current_state State) (inputs Inputs)) Pair", name.c_str()); - else - writer.print("(define-fun %s_step ((inputs Inputs)) Outputs", name.c_str()); - - writer.print(" (let ("); - for (const auto &input : ir.inputs()) { - std::string input_name = scope[input.first]; - writer.print(" (%s (%s inputs))", input_name.c_str(), input_name.c_str()); - } - writer.print(" )"); - - auto node_to_string = [&](FunctionalIR::Node n) { return scope[n.name()]; }; - SmtPrintVisitor visitor(node_to_string, scope); - - for (auto it = ir.begin(); it != ir.end(); ++it) { - const FunctionalIR::Node &node = *it; - - if (ir.inputs().count(node.name()) > 0) - continue; - - std::string node_name = scope[node.name()]; - std::string node_expr = node.visit(visitor); - - writer.print(" (let ( (%s %s))", node_name.c_str(), node_expr.c_str()); - } - - if (stateful) { - writer.print(" (let ( (next_state (mk_state "); - for (const auto &state : ir.state()) { - std::string state_name = scope[state.first]; - const std::string state_assignment = ir.get_state_next_node(state.first).name().c_str(); - writer.print(" %s", state_assignment.substr(1).c_str()); - } - writer.print(" )))"); - } - - if (stateful) { - writer.print(" (let ( (outputs (mk_outputs "); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" %s", output_name.c_str()); - } - writer.print(" )))"); - - writer.print("(mk-pair outputs next_state)"); - } - else { - writer.print(" (mk_outputs "); - for (const auto &output : ir.outputs()) { - std::string output_name = scope[output.first]; - writer.print(" %s", output_name.c_str()); - } - writer.print(" )"); // Closing mk_outputs - } - if (stateful) { - writer.print(" )"); // Closing outputs let statement - writer.print(" )"); // Closing next_state let statement - } - // Close the nested lets - for (size_t i = 0; i < ir.size() - ir.inputs().size(); ++i) { - writer.print(" )"); // Closing each node - } - if (ir.size() == ir.inputs().size()) - writer.print(" )"); // Corner case - - writer.print(" )"); // Closing inputs let statement - writer.print(")\n"); // Closing step function - } + w.push(); + w.open(SExpr{"define-fun", name, + {{"inputs", input_struct.name}, + {"state", state_struct.name}}, + {"Pair", output_struct.name, state_struct.name}}); + auto inlined = [&](FunctionalIR::Node n) { + return n.fn() == FunctionalIR::Fn::constant || + n.fn() == FunctionalIR::Fn::undriven; + }; + SmtPrintVisitor visitor(input_struct, state_struct); + auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr { + if(inlined(n)) + return n.visit(visitor); + else + return scope(n.id(), n.name()); + }; + visitor.n = node_to_sexpr; + for(auto n : ir) + if(!inlined(n)) { + w.open(SExpr{"let", {{node_to_sexpr(n), n.visit(visitor)}}}, false); + w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true); + } + w.open(SExpr{"pair"}); + output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); }); + state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); }); + w.pop(); + } }; struct FunctionalSmtBackend : public Backend { - FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} + FunctionalSmtBackend() : Backend("functional_smt2", "Generate SMT-LIB from Functional IR") {} - void help() override { log("\nFunctional SMT Backend.\n\n"); } + void help() override { log("\nFunctional SMT Backend.\n\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Functional SMT Backend.\n"); + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Functional SMT Backend.\n"); - size_t argidx = 1; - extra_args(f, filename, args, argidx, design); + size_t argidx = 1; + extra_args(f, filename, args, argidx, design); - for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); - auto ir = FunctionalIR::from_module(module); - SmtModule smt(RTLIL::unescape_id(module->name), ir); - smt.write(*f); - } - } + for (auto module : design->selected_modules()) { + log("Processing module `%s`.\n", module->name.c_str()); + SmtModule smt(module); + smt.write(*f); + } + } } FunctionalSmtBackend; PRIVATE_NAMESPACE_END diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 3e7c55ef4..99fc872a8 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -30,6 +30,7 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN class FunctionalIR { +public: enum class Fn { invalid, buf, @@ -69,7 +70,6 @@ class FunctionalIR { memory_read, memory_write }; -public: class Sort { std::variant> _v; public: @@ -185,6 +185,7 @@ public: else return std::string("\\n") + std::to_string(id()); } + Fn fn() const { return _ref.function().fn(); } Sort sort() const { return _ref.attr().sort; } int width() const { return sort().width(); } Node arg(int n) const { return Node(_ref.arg(n)); } @@ -380,16 +381,22 @@ public: }; namespace FunctionalTools { - class Scope { - const char *_illegal_characters; + template class Scope { + protected: + char substitution_character = '_'; + virtual bool is_character_legal(char) = 0; + private: pool _used_names; - dict _by_id; - dict _by_name; - std::string allocate_name(IdString suggestion) { + dict _by_id; + public: + void reserve(std::string name) { + _used_names.insert(std::move(name)); + } + std::string unique_name(IdString suggestion) { std::string str = RTLIL::unescape_id(suggestion); for(size_t i = 0; i < str.size(); i++) - if(strchr(_illegal_characters, str[i])) - str[i] = '_'; + if(!is_character_legal(str[i])) + str[i] = substitution_character; if(_used_names.count(str) == 0) { _used_names.insert(str); return str; @@ -402,32 +409,14 @@ namespace FunctionalTools { } } } - public: - Scope(const char *illegal_characters = "", const char **keywords = nullptr) { - _illegal_characters = illegal_characters; - if(keywords != nullptr) - for(const char **p = keywords; *p != nullptr; p++) - reserve(*p); - } - void reserve(std::string name) { - _used_names.insert(std::move(name)); - } - std::string operator()(int id, IdString suggestion) { + std::string operator()(Id id, IdString suggestion) { auto it = _by_id.find(id); if(it != _by_id.end()) return it->second; - std::string str = allocate_name(suggestion); + std::string str = unique_name(suggestion); _by_id.insert({id, str}); return str; } - std::string operator()(IdString idstring) { - auto it = _by_name.find(idstring); - if(it != _by_name.end()) - return it->second; - std::string str = allocate_name(idstring); - _by_name.insert({idstring, str}); - return str; - } }; class Writer { std::ostream *os; From c659ef29f4a00de5f1d7a656ffd646655fa4e859 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 10 Jul 2024 18:08:12 +0100 Subject: [PATCH 130/342] change smtlib backend to use list() function instead of SExpr{} constructor (leads to weird constructor overloading resolution issues) --- backends/functional/smtlib.cc | 105 ++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 50 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index c3e159eb3..cbff1398e 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -48,14 +48,14 @@ struct SmtScope : public FunctionalTools::Scope { }; class SExpr { +public: std::variant, std::string> _v; public: SExpr(std::string a) : _v(std::move(a)) {} SExpr(const char *a) : _v(a) {} SExpr(int n) : _v(std::to_string(n)) {} - SExpr(std::vector const &a) : _v(std::in_place_index<0>, a) {} - SExpr(std::vector &&a) : _v(std::in_place_index<0>, std::move(a)) {} - SExpr(std::initializer_list a) : _v(std::in_place_index<0>, a) {} + SExpr(std::vector const &l) : _v(l) {} + SExpr(std::vector &&l) : _v(std::move(l)) {} bool is_atom() const { return std::holds_alternative(_v); } std::string const &atom() const { return std::get(_v); } bool is_list() const { return std::holds_alternative>(_v); } @@ -81,6 +81,9 @@ public: return ss.str(); } }; +template SExpr list(Args&&... args) { + return SExpr(std::vector{std::forward(args)...}); +} class SExprWriter { std::ostream &os; @@ -209,9 +212,9 @@ struct SmtSort { SmtSort(FunctionalIR::Sort sort) : sort(sort) {} SExpr to_sexpr() const { if(sort.is_memory()) { - return SExpr{"Array", {"_", "BitVec", sort.addr_width()}, {"_", "BitVec", sort.data_width()}}; + return list("Array", list("_", "BitVec", sort.addr_width()), list("_", "BitVec", sort.data_width())); } else if(sort.is_signal()) { - return SExpr{"_", "BitVec", sort.width()}; + return list("_", "BitVec", sort.width()); } else { log_error("unknown sort"); } @@ -235,15 +238,15 @@ public: fields.emplace_back(Field{sort, accessor}); } void write_definition(SExprWriter &w) { - w.open(SExpr{"declare-datatype", name}); - w.open(SExpr({})); - w.open(SExpr{name}); + w.open(list("declare-datatype", name)); + w.open(list()); + w.open(list(name)); for(const auto &field : fields) - w << SExpr{field.accessor, field.sort.to_sexpr()}; + w << list(field.accessor, field.sort.to_sexpr()); w.close(3); } template void write_value(SExprWriter &w, Fn fn) { - w.open(SExpr(std::initializer_list{name})); + w.open(list(name)); for(auto field_name : field_names) { w << fn(field_name); w.comment(RTLIL::unescape_id(field_name), true); @@ -252,7 +255,7 @@ public: } SExpr access(SExpr record, IdString name) { size_t i = field_names.at(name); - return SExpr{fields[i].accessor, std::move(record)}; + return list(fields[i].accessor, std::move(record)); } }; @@ -272,64 +275,64 @@ struct SmtPrintVisitor { } SExpr from_bool(SExpr &&arg) { - return SExpr{"ite", std::move(arg), "#b1", "#b0"}; + return list("ite", std::move(arg), "#b1", "#b0"); } SExpr to_bool(SExpr &&arg) { - return SExpr{"=", std::move(arg), "#b1"}; + return list("=", std::move(arg), "#b1"); } SExpr extract(SExpr &&arg, int offset, int out_width = 1) { - return SExpr{{"_", "extract", offset + out_width - 1, offset}, std::move(arg)}; + return list(list("_", "extract", offset + out_width - 1, offset), std::move(arg)); } SExpr buf(Node, Node a) { return n(a); } SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); } - SExpr zero_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "zero_extend", out_width - a.width()}, n(a)}; } - SExpr sign_extend(Node, Node a, int, int out_width) { return SExpr{{"_", "sign_extend", out_width - a.width()}, n(a)}; } - SExpr concat(Node, Node a, int, Node b, int) { return SExpr{"concat", n(a), n(b)}; } - SExpr add(Node, Node a, Node b, int) { return SExpr{"bvadd", n(a), n(b)}; } - SExpr sub(Node, Node a, Node b, int) { return SExpr{"bvsub", n(a), n(b)}; } - SExpr mul(Node, Node a, Node b, int) { return SExpr{"bvmul", n(a), n(b)}; } - SExpr unsigned_div(Node, Node a, Node b, int) { return SExpr{"bvudiv", n(a), n(b)}; } - SExpr unsigned_mod(Node, Node a, Node b, int) { return SExpr{"bvurem", n(a), n(b)}; } - SExpr bitwise_and(Node, Node a, Node b, int) { return SExpr{"bvand", n(a), n(b)}; } - SExpr bitwise_or(Node, Node a, Node b, int) { return SExpr{"bvor", n(a), n(b)}; } - SExpr bitwise_xor(Node, Node a, Node b, int) { return SExpr{"bvxor", n(a), n(b)}; } - SExpr bitwise_not(Node, Node a, int) { return SExpr{"bvnot", n(a)}; } - SExpr unary_minus(Node, Node a, int) { return SExpr{"bvneg", n(a)}; } - SExpr reduce_and(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S1, a.width()))}); } - SExpr reduce_or(Node, Node a, int) { return from_bool(SExpr{"=", n(a), literal(RTLIL::Const(State::S0, a.width()))}); } + SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); } + SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); } + SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(a), n(b)); } + SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); } + SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); } + SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); } + SExpr unsigned_div(Node, Node a, Node b, int) { return list("bvudiv", n(a), n(b)); } + SExpr unsigned_mod(Node, Node a, Node b, int) { return list("bvurem", n(a), n(b)); } + SExpr bitwise_and(Node, Node a, Node b, int) { return list("bvand", n(a), n(b)); } + SExpr bitwise_or(Node, Node a, Node b, int) { return list("bvor", n(a), n(b)); } + SExpr bitwise_xor(Node, Node a, Node b, int) { return list("bvxor", n(a), n(b)); } + SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); } + SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); } + SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); } + SExpr reduce_or(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S0, a.width())))); } SExpr reduce_xor(Node, Node a, int) { vector s { "bvxor" }; for(int i = 0; i < a.width(); i++) s.push_back(extract(n(a), i)); return s; } - SExpr equal(Node, Node a, Node b, int) { return from_bool(SExpr{"=", n(a), n(b)}); } - SExpr not_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"distinct", n(a), n(b)}); } - SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsgt", n(a), n(b)}); } - SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvsge", n(a), n(b)}); } - SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(SExpr{"bvugt", n(a), n(b)}); } - SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(SExpr{"bvuge", n(a), n(b)}); } + SExpr equal(Node, Node a, Node b, int) { return from_bool(list("=", n(a), n(b))); } + SExpr not_equal(Node, Node a, Node b, int) { return from_bool(list("distinct", n(a), n(b))); } + SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvsgt", n(a), n(b))); } + SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvsge", n(a), n(b))); } + SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvugt", n(a), n(b))); } + SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvuge", n(a), n(b))); } SExpr extend(SExpr &&a, int in_width, int out_width) { if(in_width < out_width) - return SExpr{{"_", "zero_extend", out_width - in_width}, std::move(a)}; + return list(list("_", "zero_extend", out_width - in_width), std::move(a)); else return std::move(a); } - SExpr logical_shift_left(Node, Node a, Node b, int, int) { return SExpr{"bvshl", n(a), extend(n(b), b.width(), a.width())}; } - SExpr logical_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvshr", n(a), extend(n(b), b.width(), a.width())}; } - SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return SExpr{"bvasr", n(a), extend(n(b), b.width(), a.width())}; } - SExpr mux(Node, Node a, Node b, Node s, int) { return SExpr{"ite", to_bool(n(s)), n(a), n(b)}; } + SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); } + SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvshr", n(a), extend(n(b), b.width(), a.width())); } + SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvasr", n(a), extend(n(b), b.width(), a.width())); } + SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(a), n(b)); } SExpr pmux(Node, Node a, Node b, Node s, int, int) { SExpr rv = n(a); for(int i = 0; i < s.width(); i++) - rv = SExpr{"ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv}; + rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv); return rv; } SExpr constant(Node, RTLIL::Const value) { return literal(value); } - SExpr memory_read(Node, Node mem, Node addr, int, int) { return SExpr{"select", n(mem), n(addr)}; } - SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return SExpr{"store", n(mem), n(addr), n(data)}; } + SExpr memory_read(Node, Node mem, Node addr, int, int) { return list("select", n(mem), n(addr)); } + SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return list("store", n(mem), n(addr), n(data)); } SExpr input(Node, IdString name) { return input_struct.access("inputs", name); } SExpr state(Node, IdString name) { return state_struct.access("state", name); } @@ -370,13 +373,15 @@ struct SmtModule { output_struct.write_definition(w); state_struct.write_definition(w); - w << SExpr{"declare-datatypes", {{"Pair", 2}}, {{"par", {"X", "Y"}, {{"pair", {"first", "X"}, {"second", "Y"}}}}}}; + w << list("declare-datatypes", + list(list("Pair", 2)), + list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y")))))); w.push(); - w.open(SExpr{"define-fun", name, - {{"inputs", input_struct.name}, - {"state", state_struct.name}}, - {"Pair", output_struct.name, state_struct.name}}); + w.open(list("define-fun", name, + list(list("inputs", input_struct.name), + list("state", state_struct.name)), + list("Pair", output_struct.name, state_struct.name))); auto inlined = [&](FunctionalIR::Node n) { return n.fn() == FunctionalIR::Fn::constant || n.fn() == FunctionalIR::Fn::undriven; @@ -391,10 +396,10 @@ struct SmtModule { visitor.n = node_to_sexpr; for(auto n : ir) if(!inlined(n)) { - w.open(SExpr{"let", {{node_to_sexpr(n), n.visit(visitor)}}}, false); + w.open(list("let", list(list(node_to_sexpr(n), n.visit(visitor)))), false); w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true); } - w.open(SExpr{"pair"}); + w.open(list("pair")); output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); }); state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); }); w.pop(); From 00a65754bbf5ac5a456f6fce5812e4400ef5449c Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 11 Jul 2024 11:30:23 +0100 Subject: [PATCH 131/342] factor out SExpr/SExprWriter classes out of smtlib backend, and also tidy them up/document them --- Makefile | 3 +- backends/functional/smtlib.cc | 163 +--------------------------------- kernel/sexpr.cc | 163 ++++++++++++++++++++++++++++++++++ kernel/sexpr.h | 122 +++++++++++++++++++++++++ 4 files changed, 290 insertions(+), 161 deletions(-) create mode 100644 kernel/sexpr.cc create mode 100644 kernel/sexpr.h diff --git a/Makefile b/Makefile index 2bbb0dc5b..68e6fda4a 100644 --- a/Makefile +++ b/Makefile @@ -617,6 +617,7 @@ $(eval $(call add_include_file,kernel/register.h)) $(eval $(call add_include_file,kernel/rtlil.h)) $(eval $(call add_include_file,kernel/satgen.h)) $(eval $(call add_include_file,kernel/scopeinfo.h)) +$(eval $(call add_include_file,kernel/sexpr.h)) $(eval $(call add_include_file,kernel/sigtools.h)) $(eval $(call add_include_file,kernel/timinginfo.h)) $(eval $(call add_include_file,kernel/utils.h)) @@ -638,7 +639,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o -OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o +OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o OBJS += kernel/drivertools.o kernel/functionalir.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index cbff1398e..43e6f5bf4 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -19,11 +19,14 @@ #include "kernel/functionalir.h" #include "kernel/yosys.h" +#include "kernel/sexpr.h" #include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +using SExprUtil::list; + const char *reserved_keywords[] = { "BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par", "assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes", @@ -47,166 +50,6 @@ struct SmtScope : public FunctionalTools::Scope { } }; -class SExpr { -public: - std::variant, std::string> _v; -public: - SExpr(std::string a) : _v(std::move(a)) {} - SExpr(const char *a) : _v(a) {} - SExpr(int n) : _v(std::to_string(n)) {} - SExpr(std::vector const &l) : _v(l) {} - SExpr(std::vector &&l) : _v(std::move(l)) {} - bool is_atom() const { return std::holds_alternative(_v); } - std::string const &atom() const { return std::get(_v); } - bool is_list() const { return std::holds_alternative>(_v); } - std::vector const &list() const { return std::get>(_v); } - friend std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) { - if(sexpr.is_atom()) - os << sexpr.atom(); - else if(sexpr.is_list()){ - os << "("; - auto l = sexpr.list(); - for(size_t i = 0; i < l.size(); i++) { - if(i > 0) os << " "; - os << l[i]; - } - os << ")"; - }else - os << ""; - return os; - } - std::string to_string() const { - std::stringstream ss; - ss << *this; - return ss.str(); - } -}; -template SExpr list(Args&&... args) { - return SExpr(std::vector{std::forward(args)...}); -} - -class SExprWriter { - std::ostream &os; - int _max_line_width; - int _indent = 0; - int _pos = 0; - bool _pending_nl = false; - vector _unclosed; - vector _unclosed_stack; - void nl_if_pending() { - if(_pending_nl) { - os << '\n'; - _pos = 0; - _pending_nl = false; - } - } - void puts(std::string const &s) { - if(s.empty()) return; - nl_if_pending(); - for(auto c : s) { - if(c == '\n') { - os << c; - _pos = 0; - } else { - if(_pos == 0) { - for(int i = 0; i < _indent; i++) - os << " "; - _pos = 2 * _indent; - } - os << c; - _pos++; - } - } - } - int width(SExpr const &sexpr) { - if(sexpr.is_atom()) - return sexpr.atom().size(); - else if(sexpr.is_list()) { - int w = 2; - for(auto arg : sexpr.list()) - w += width(arg); - if(sexpr.list().size() > 1) - w += sexpr.list().size() - 1; - return w; - } else - return 0; - } - void print(SExpr const &sexpr, bool close = true, bool indent_rest = true) { - if(sexpr.is_atom()) - puts(sexpr.atom()); - else if(sexpr.is_list()) { - auto args = sexpr.list(); - puts("("); - bool vertical = args.size() > 1 && _pos + width(sexpr) > _max_line_width; - if(vertical) _indent++; - for(size_t i = 0; i < args.size(); i++) { - if(i > 0) puts(vertical ? "\n" : " "); - print(args[i]); - } - _indent += (!close && indent_rest) - vertical; - if(close) - puts(")"); - else { - _unclosed.push_back(indent_rest); - _pending_nl = true; - } - }else - log_error("shouldn't happen in SExprWriter::print"); - } -public: - SExprWriter(std::ostream &os, int max_line_width = 80) - : os(os) - , _max_line_width(max_line_width) - {} - void open(SExpr const &sexpr, bool indent_rest = true) { - log_assert(sexpr.is_list()); - print(sexpr, false, indent_rest); - } - void close(size_t n = 1) { - log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n); - while(n-- > 0) { - bool indented = _unclosed[_unclosed.size() - 1]; - _unclosed.pop_back(); - _pending_nl = _pos >= _max_line_width; - if(indented) - _indent--; - puts(")"); - _pending_nl = true; - } - } - void push() { - _unclosed_stack.push_back(_unclosed.size()); - } - void pop() { - auto t = _unclosed_stack.back(); - log_assert(_unclosed.size() >= t); - close(_unclosed.size() - t); - _unclosed_stack.pop_back(); - } - SExprWriter &operator <<(SExpr const &sexpr) { - print(sexpr); - _pending_nl = true; - return *this; - } - void comment(std::string const &str, bool hanging = false) { - if(hanging) { - if(_pending_nl) { - _pending_nl = false; - puts(" "); - } - } - puts("; "); - puts(str); - puts("\n"); - } - ~SExprWriter() { - while(!_unclosed_stack.empty()) - pop(); - close(_unclosed.size()); - nl_if_pending(); - } -}; - struct SmtSort { FunctionalIR::Sort sort; SmtSort(FunctionalIR::Sort sort) : sort(sort) {} diff --git a/kernel/sexpr.cc b/kernel/sexpr.cc new file mode 100644 index 000000000..0b977d2a8 --- /dev/null +++ b/kernel/sexpr.cc @@ -0,0 +1,163 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "sexpr.h" + +YOSYS_NAMESPACE_BEGIN + +std::ostream &operator<<(std::ostream &os, SExpr const &sexpr) { + if(sexpr.is_atom()) + os << sexpr.atom(); + else if(sexpr.is_list()){ + os << "("; + auto l = sexpr.list(); + for(size_t i = 0; i < l.size(); i++) { + if(i > 0) os << " "; + os << l[i]; + } + os << ")"; + }else + os << ""; + return os; +} + + std::string SExpr::to_string() const { + std::stringstream ss; + ss << *this; + return ss.str(); +} + +void SExprWriter::nl_if_pending() { + if(_pending_nl) { + os << '\n'; + _pos = 0; + _pending_nl = false; + } +} + +void SExprWriter::puts(std::string_view s) { + if(s.empty()) return; + nl_if_pending(); + for(auto c : s) { + if(c == '\n') { + os << c; + _pos = 0; + } else { + if(_pos == 0) { + for(int i = 0; i < _indent; i++) + os << " "; + _pos = 2 * _indent; + } + os << c; + _pos++; + } + } +} + + +// Calculate how much space would be left if expression was written +// out in full horizontally. Returns any negative value if it doesn't fit. +// +// (Ideally we would avoid recalculating the widths of subexpression, +// but I can't figure out how to store the widths. As an alternative, +// we bail out of the calculation as soon as we can tell the expression +// doesn't fit in the available space.) +int SExprWriter::check_fit(SExpr const &sexpr, int space) { + if(sexpr.is_atom()) + return space - sexpr.atom().size(); + else if(sexpr.is_list()) { + space -= 2; + if(sexpr.list().size() > 1) + space -= sexpr.list().size() - 1; + for(auto arg : sexpr.list()) { + if(space < 0) break; + space = check_fit(arg, space); + } + return space; + } else + return -1; +} + +void SExprWriter::print(SExpr const &sexpr, bool close, bool indent_rest) { + if(sexpr.is_atom()) + puts(sexpr.atom()); + else if(sexpr.is_list()) { + auto args = sexpr.list(); + puts("("); + // Expressions are printed horizontally if they fit on the line. + // We do the check *after* puts("(") to make sure that _pos is accurate. + // (Otherwise there could be a pending newline + indentation) + bool vertical = args.size() > 1 && check_fit(sexpr, _max_line_width - _pos + 1) < 0; + if(vertical) _indent++; + for(size_t i = 0; i < args.size(); i++) { + if(i > 0) puts(vertical ? "\n" : " "); + print(args[i]); + } + // Any remaining arguments are currently always printed vertically, + // but are not indented if indent_rest = false. + _indent += (!close && indent_rest) - vertical; + if(close) + puts(")"); + else { + _unclosed.push_back(indent_rest); + _pending_nl = true; + } + }else + log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string().c_str()); +} + +void SExprWriter::close(size_t n) { + log_assert(_unclosed.size() - (_unclosed_stack.empty() ? 0 : _unclosed_stack.back()) >= n); + while(n-- > 0) { + bool indented = _unclosed[_unclosed.size() - 1]; + _unclosed.pop_back(); + // Only print ) on the same line if it fits. + _pending_nl = _pos >= _max_line_width; + if(indented) + _indent--; + puts(")"); + _pending_nl = true; + } +} + +void SExprWriter::comment(std::string const &str, bool hanging) { + if(hanging) { + if(_pending_nl) { + _pending_nl = false; + puts(" "); + } + } + size_t i = 0, e; + do{ + e = str.find('\n', i); + puts("; "); + puts(std::string_view(str).substr(i, e - i)); + puts("\n"); + i = e + 1; + }while(e != std::string::npos); +} + +SExprWriter::~SExprWriter() { + while(!_unclosed_stack.empty()) + pop(); + close(_unclosed.size()); + nl_if_pending(); +} + +YOSYS_NAMESPACE_END diff --git a/kernel/sexpr.h b/kernel/sexpr.h new file mode 100644 index 000000000..41073ea23 --- /dev/null +++ b/kernel/sexpr.h @@ -0,0 +1,122 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef SEXPR_H +#define SEXPR_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +class SExpr { +public: + std::variant, std::string> _v; +public: + SExpr(std::string a) : _v(std::move(a)) {} + SExpr(const char *a) : _v(a) {} + // FIXME: should maybe be defined for all integral types + SExpr(int n) : _v(std::to_string(n)) {} + SExpr(std::vector const &l) : _v(l) {} + SExpr(std::vector &&l) : _v(std::move(l)) {} + // It would be nicer to have an std::initializer_list constructor, + // but that causes confusing issues with overload resolution sometimes. + template static SExpr list(Args&&... args) { + return SExpr(std::vector{std::forward(args)...}); + } + bool is_atom() const { return std::holds_alternative(_v); } + std::string const &atom() const { return std::get(_v); } + bool is_list() const { return std::holds_alternative>(_v); } + std::vector const &list() const { return std::get>(_v); } + std::string to_string() const; +}; + +std::ostream &operator<<(std::ostream &os, SExpr const &sexpr); + +namespace SExprUtil { + // A little hack so that `using SExprUtil::list` lets you import a shortcut to `SExpr::list` + template SExpr list(Args&&... args) { + return SExpr(std::vector{std::forward(args)...}); + } +} + +// SExprWriter is a pretty printer for s-expr. It does not try very hard to get a good layout. +class SExprWriter { + std::ostream &os; + int _max_line_width; + int _indent = 0; + int _pos = 0; + // If _pending_nl is set, print a newline before the next character. + // This lets us "undo" the last newline so we can put + // closing parentheses or a hanging comment on the same line. + bool _pending_nl = false; + // Unclosed parentheses (boolean stored is indent_rest) + vector _unclosed; + // Used only for push() and pop() (stores _unclosed.size()) + vector _unclosed_stack; + void nl_if_pending(); + void puts(std::string_view s); + int check_fit(SExpr const &sexpr, int space); + void print(SExpr const &sexpr, bool close = true, bool indent_rest = true); +public: + SExprWriter(std::ostream &os, int max_line_width = 80) + : os(os) + , _max_line_width(max_line_width) + {} + // Print an s-expr. + SExprWriter &operator <<(SExpr const &sexpr) { + print(sexpr); + _pending_nl = true; + return *this; + } + // Print an s-expr (which must be a list), but leave room for extra elements + // which may be printed using either << or further calls to open. + // If indent_rest = false, the remaining elements are not intended + // (for avoiding unreasonable indentation on deeply nested structures). + void open(SExpr const &sexpr, bool indent_rest = true) { + log_assert(sexpr.is_list()); + print(sexpr, false, indent_rest); + } + // Close the s-expr opened with the last call to open + // (if an argument is given, close that many s-exprs). + void close(size_t n = 1); + // push() remembers how many s-exprs are currently open + void push() { + _unclosed_stack.push_back(_unclosed.size()); + } + // pop() closes all s-expr opened since the corresponding call to push() + void pop() { + auto t = _unclosed_stack.back(); + log_assert(_unclosed.size() >= t); + close(_unclosed.size() - t); + _unclosed_stack.pop_back(); + } + // Print a comment. + // If hanging = true, append it to the end of the last printed s-expr. + void comment(std::string const &str, bool hanging = false); + // Flush any unprinted characters to the std::ostream, but does not close unclosed parentheses. + void flush() { + nl_if_pending(); + } + // Destructor closes any unclosed parentheses and flushes. + ~SExprWriter(); +}; + +YOSYS_NAMESPACE_END + +#endif From 6e7ae88c6a22980bdcc290851b5a4533b211a84c Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Fri, 12 Jul 2024 10:45:31 +0100 Subject: [PATCH 132/342] fix bugs in smtlib backend --- backends/functional/smtlib.cc | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 43e6f5bf4..113fb7100 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -28,6 +28,7 @@ PRIVATE_NAMESPACE_BEGIN using SExprUtil::list; const char *reserved_keywords[] = { + // reserved keywords from the smtlib spec "BINARY", "DECIMAL", "HEXADECIMAL", "NUMERAL", "STRING", "_", "!", "as", "let", "exists", "forall", "match", "par", "assert", "check-sat", "check-sat-assuming", "declare-const", "declare-datatype", "declare-datatypes", "declare-fun", "declare-sort", "define-fun", "define-fun-rec", "define-funs-rec", "define-sort", @@ -35,6 +36,7 @@ const char *reserved_keywords[] = { "get-option", "get-proof", "get-unsat-assumptions", "get-unsat-core", "get-value", "pop", "push", "reset", "reset-assertions", "set-info", "set-logic", "set-option", + // reserved for our own purposes "pair", "Pair", "first", "second", "inputs", "state", nullptr @@ -89,12 +91,17 @@ public: w.close(3); } template void write_value(SExprWriter &w, Fn fn) { - w.open(list(name)); - for(auto field_name : field_names) { - w << fn(field_name); - w.comment(RTLIL::unescape_id(field_name), true); + if(field_names.empty()) { + // Zero-argument constructors in SMTLIB must not be called as functions. + w << name; + } else { + w.open(list(name)); + for(auto field_name : field_names) { + w << fn(field_name); + w.comment(RTLIL::unescape_id(field_name), true); + } + w.close(); } - w.close(); } SExpr access(SExpr record, IdString name) { size_t i = field_names.at(name); @@ -131,7 +138,7 @@ struct SmtPrintVisitor { SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); } SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); } SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); } - SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(a), n(b)); } + SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(b), n(a)); } SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); } SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); } SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); } @@ -143,7 +150,7 @@ struct SmtPrintVisitor { SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); } SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); } SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); } - SExpr reduce_or(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S0, a.width())))); } + SExpr reduce_or(Node, Node a, int) { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); } SExpr reduce_xor(Node, Node a, int) { vector s { "bvxor" }; for(int i = 0; i < a.width(); i++) @@ -164,9 +171,9 @@ struct SmtPrintVisitor { return std::move(a); } SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); } - SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvshr", n(a), extend(n(b), b.width(), a.width())); } - SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvasr", n(a), extend(n(b), b.width(), a.width())); } - SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(a), n(b)); } + SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } + SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } + SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(b), n(a)); } SExpr pmux(Node, Node a, Node b, Node s, int, int) { SExpr rv = n(a); for(int i = 0; i < s.width(); i++) From 9ad859fc0a9828ba339ec1fc40eecb842a42acac Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Fri, 12 Jul 2024 10:45:58 +0100 Subject: [PATCH 133/342] add bwmux, bweqx, bmux, demux cells --- kernel/functionalir.cc | 80 +++++++++++++++++++++++++++++------------- 1 file changed, 56 insertions(+), 24 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index c5406f412..6983facfb 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -96,6 +96,15 @@ private: } return r; } + T handle_bmux(T a, T s, int a_width, int a_offset, int width, int s_width, int sn) { + if(sn < 1) + return factory.slice(a, a_width, a_offset, width); + else { + T y0 = handle_bmux(a, s, a_width, a_offset, width, s_width, sn - 1); + T y1 = handle_bmux(a, s, a_width, a_offset + (width << (sn - 1)), width, s_width, sn - 1); + return factory.mux(y0, y1, factory.slice(s, s_width, sn - 1, 1), width); + } + } public: T handle(IdString cellType, dict parameters, dict inputs) { @@ -248,31 +257,54 @@ public: return extend(factory.unsigned_div(a, b, width), width, y_width, false); } } else if(cellType == ID($pow)) { - return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); + return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); } else if (cellType == ID($lut)) { - int width = parameters.at(ID(WIDTH)).as_int(); - Const lut_table = parameters.at(ID(LUT)); - T a = inputs.at(ID(A)); - - // Output initialization - T y = factory.constant(Const(0, 1)); - - // Iterate over each possible input combination - for (int i = 0; i < (1 << width); ++i) { - // Create a constant representing the value of i - T i_val = factory.constant(Const(i, width)); - // Check if the input matches this value - T match = factory.equal(a, i_val, width); - // Get the corresponding LUT value - bool lut_val = lut_table.bits[i] == State::S1; - T lut_output = factory.constant(Const(lut_val, 1)); - // Use a multiplexer to select the correct output based on the match - y = factory.mux(y, lut_output, match, 1); - } - - return y; - } else{ - log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + int width = parameters.at(ID(WIDTH)).as_int(); + Const lut_table = parameters.at(ID(LUT)); + T a = inputs.at(ID(A)); + // Output initialization + T y = factory.constant(Const(0, 1)); + // Iterate over each possible input combination + for (int i = 0; i < (1 << width); ++i) { + // Create a constant representing the value of i + T i_val = factory.constant(Const(i, width)); + // Check if the input matches this value + T match = factory.equal(a, i_val, width); + // Get the corresponding LUT value + bool lut_val = lut_table.bits[i] == State::S1; + T lut_output = factory.constant(Const(lut_val, 1)); + // Use a multiplexer to select the correct output based on the match + y = factory.mux(y, lut_output, match, 1); + } + return y; + } else if (cellType == ID($bwmux)) { + int width = parameters.at(ID(WIDTH)).as_int(); + T a = inputs.at(ID(A)); + T b = inputs.at(ID(B)); + T s = inputs.at(ID(S)); + return factory.bitwise_or( + factory.bitwise_and(a, factory.bitwise_not(s, width), width), + factory.bitwise_and(b, s, width), width); + } else if (cellType == ID($bweqx)) { + int width = parameters.at(ID(WIDTH)).as_int(); + T a = inputs.at(ID(A)); + T b = inputs.at(ID(B)); + return factory.bitwise_not(factory.bitwise_xor(a, b, width), width); + } else if(cellType == ID($bmux)) { + int width = parameters.at(ID(WIDTH)).as_int(); + int s_width = parameters.at(ID(S_WIDTH)).as_int(); + return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), width << s_width, 0, width, s_width, s_width); + } else if(cellType == ID($demux)) { + int width = parameters.at(ID(WIDTH)).as_int(); + int s_width = parameters.at(ID(S_WIDTH)).as_int(); + int y_width = width << s_width; + int b_width = ceil_log2(y_width + 1); + T a = extend(inputs.at(ID(A)), width, y_width, false); + T s = factory.extend(inputs.at(ID(S)), s_width, b_width, false); + T b = factory.mul(s, factory.constant(Const(width, b_width)), b_width); + return factory.logical_shift_left(a, b, y_width, b_width); + } else { + log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } } }; From 674e6d201de267806f435077007d41441dedae8d Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Fri, 12 Jul 2024 11:07:33 +0100 Subject: [PATCH 134/342] rewrite functional backend test code in python --- tests/functional/README.md | 19 ++ tests/functional/conftest.py | 14 + tests/functional/rtlil_cells.py | 275 ++++++++++++++++++ tests/functional/run-test.sh | 2 + tests/functional/single_cells/rtlil/README.md | 2 - tests/functional/single_cells/rtlil/ff.il | 83 ------ .../single_cells/rtlil/multiple_outputs.il | 69 ----- .../single_cells/rtlil/test_cell_add_00000.il | 17 -- .../single_cells/rtlil/test_cell_alu_00000.il | 25 -- .../single_cells/rtlil/test_cell_and_00000.il | 17 -- .../rtlil/test_cell_bmux_00000.il | 14 - .../rtlil/test_cell_demux_00000.il | 14 - .../single_cells/rtlil/test_cell_div_00000.il | 17 -- .../rtlil/test_cell_divfloor_00000.il | 17 -- .../single_cells/rtlil/test_cell_eq_00000.il | 17 -- .../single_cells/rtlil/test_cell_fa_00000.il | 17 -- .../single_cells/rtlil/test_cell_ge_00000.il | 17 -- .../single_cells/rtlil/test_cell_gt_00000.il | 17 -- .../single_cells/rtlil/test_cell_lcu_00000.il | 15 - .../single_cells/rtlil/test_cell_le_00000.il | 17 -- .../rtlil/test_cell_logic_and_00000.il | 17 -- .../rtlil/test_cell_logic_not_00000.il | 13 - .../rtlil/test_cell_logic_or_00000.il | 17 -- .../single_cells/rtlil/test_cell_lt_00000.il | 17 -- .../single_cells/rtlil/test_cell_lut_00000.il | 12 - .../rtlil/test_cell_macc_00000.il | 17 -- .../single_cells/rtlil/test_cell_mod_00000.il | 17 -- .../rtlil/test_cell_modfloor_00000.il | 17 -- .../single_cells/rtlil/test_cell_mul_00000.il | 17 -- .../single_cells/rtlil/test_cell_mux_00000.il | 15 - .../single_cells/rtlil/test_cell_ne_00000.il | 17 -- .../single_cells/rtlil/test_cell_neg_00000.il | 13 - .../single_cells/rtlil/test_cell_not_00000.il | 13 - .../single_cells/rtlil/test_cell_or_00000.il | 17 -- .../single_cells/rtlil/test_cell_pos_00000.il | 13 - .../single_cells/rtlil/test_cell_pos_00001.il | 13 - .../rtlil/test_cell_reduce_and_00000.il | 13 - .../rtlil/test_cell_reduce_bool_00000.il | 13 - .../rtlil/test_cell_reduce_or_00000.il | 13 - .../rtlil/test_cell_reduce_xnor_00000.il | 13 - .../rtlil/test_cell_reduce_xor_00000.il | 13 - .../rtlil/test_cell_shift_00000.il | 17 -- .../rtlil/test_cell_shiftx_00000.il | 17 -- .../single_cells/rtlil/test_cell_shl_00000.il | 17 -- .../single_cells/rtlil/test_cell_shr_00000.il | 17 -- .../single_cells/rtlil/test_cell_sop_00000.il | 13 - .../rtlil/test_cell_sshl_00000.il | 17 -- .../rtlil/test_cell_sshr_00000.il | 17 -- .../single_cells/rtlil/test_cell_sub_00000.il | 17 -- .../rtlil/test_cell_xnor_00000.il | 17 -- .../single_cells/rtlil/test_cell_xor_00000.il | 17 -- tests/functional/single_cells/run-test.sh | 172 ----------- .../single_cells/vcd_harness_smt.py | 214 -------------- tests/functional/smt_vcd.py | 180 ++++++++++++ {backends => tests}/functional/smtio.py | 0 tests/functional/test_functional.py | 63 ++++ .../{single_cells => }/vcd_harness.cc | 2 +- 57 files changed, 554 insertions(+), 1238 deletions(-) create mode 100644 tests/functional/README.md create mode 100644 tests/functional/conftest.py create mode 100644 tests/functional/rtlil_cells.py create mode 100755 tests/functional/run-test.sh delete mode 100644 tests/functional/single_cells/rtlil/README.md delete mode 100644 tests/functional/single_cells/rtlil/ff.il delete mode 100644 tests/functional/single_cells/rtlil/multiple_outputs.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_add_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_alu_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_and_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_bmux_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_demux_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_div_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il delete mode 100644 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tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shift_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shl_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_shr_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sop_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sshl_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sshr_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_sub_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_xnor_00000.il delete mode 100644 tests/functional/single_cells/rtlil/test_cell_xor_00000.il delete mode 100755 tests/functional/single_cells/run-test.sh delete mode 100644 tests/functional/single_cells/vcd_harness_smt.py create mode 100644 tests/functional/smt_vcd.py rename {backends => tests}/functional/smtio.py (100%) create mode 100644 tests/functional/test_functional.py rename tests/functional/{single_cells => }/vcd_harness.cc (98%) diff --git a/tests/functional/README.md b/tests/functional/README.md new file mode 100644 index 000000000..1459c3198 --- /dev/null +++ b/tests/functional/README.md @@ -0,0 +1,19 @@ +Tests for the functional backend use pytest as a testrunner. + +Run with `pytest -v` + +Pytest options you might want: + +- `-v`: More progress indication. + +- `--basetemp tmp`: Store test files (including vcd results) in tmp. + CAREFUL: contents of tmp will be deleted + +- `-k `: Run only tests that contain the pattern, e.g. + `-k cxx` or `-k smt` or `-k demux` or `-k 'cxx[demux` + +- `-s`: Don't hide stdout/stderr from the test code. + +Custom options for functional backend tests: + +- `--per-cell N`: Run only N tests for each cell. diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py new file mode 100644 index 000000000..3a66abaab --- /dev/null +++ b/tests/functional/conftest.py @@ -0,0 +1,14 @@ +import pytest +from rtlil_cells import generate_test_cases + +def pytest_addoption(parser): + parser.addoption( + "--per-cell", type=int, default=None, help="run only N tests per cell" + ) + +def pytest_generate_tests(metafunc): + if "cell" in metafunc.fixturenames: + print(dir(metafunc.config)) + per_cell = metafunc.config.getoption("per_cell", default=None) + names, cases = generate_test_cases(per_cell) + metafunc.parametrize("cell,parameters", cases, ids=names) \ No newline at end of file diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py new file mode 100644 index 000000000..e96baa18e --- /dev/null +++ b/tests/functional/rtlil_cells.py @@ -0,0 +1,275 @@ +from itertools import chain +import random + +widths = [ + (16, 32, 48, True), + (16, 32, 48, False), + (32, 16, 48, True), + (32, 16, 48, False), + (32, 32, 16, True), + (32, 32, 16, False) +] + +shift_widths = [ + (32, 6, 32, True, False), + (32, 6, 32, False, False), + (32, 6, 64, True, False), + (32, 6, 64, False, False), + (32, 32, 16, True, False), + (32, 32, 16, False, False), + (32, 6, 32, True, True), + (32, 6, 32, False, True), + (32, 6, 64, True, True), + (32, 6, 64, False, True), + (32, 32, 16, True, True), + (32, 32, 16, False, True), +] + +def write_rtlil_cell(f, cell_type, inputs, outputs, parameters): + f.write('autoidx 1\n') + f.write('module \\gold\n') + idx = 1 + for name, width in inputs.items(): + f.write(f'\twire width {width} input {idx} \\{name}\n') + idx += 1 + for name, width in outputs.items(): + f.write(f'\twire width {width} output {idx} \\{name}\n') + idx += 1 + f.write(f'\tcell ${cell_type} \\UUT\n') + for (name, value) in parameters.items(): + f.write(f'\t\tparameter \\{name} {value}\n') + for name in chain(inputs.keys(), outputs.keys()): + f.write(f'\t\tconnect \\{name} \\{name}\n') + f.write(f'\tend\nend\n') + +class BaseCell: + def __init__(self, name): + self.name = name + +class UnaryCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (a_width, _, y_width, signed) in widths: + yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}', + {'A_WIDTH' : a_width, + 'A_SIGNED' : int(signed), + 'Y_WIDTH' : y_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + +class BinaryCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (a_width, b_width, y_width, signed) in widths: + yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}', + {'A_WIDTH' : a_width, + 'A_SIGNED' : int(signed), + 'B_WIDTH' : b_width, + 'B_SIGNED' : int(signed), + 'Y_WIDTH' : y_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + +class ShiftCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths: + if not self.name in ('shift', 'shiftx') and b_signed: continue + if self.name == 'shiftx' and a_signed: continue + yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}', + {'A_WIDTH' : a_width, + 'A_SIGNED' : int(a_signed), + 'B_WIDTH' : b_width, + 'B_SIGNED' : int(b_signed), + 'Y_WIDTH' : y_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + +class MuxCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for width in [10, 20, 40]: + yield (f'{width}', {'WIDTH' : width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters) + +class BWCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for width in [10, 20, 40]: + yield (f'{width}', {'WIDTH' : width}) + def write_rtlil_file(self, f, parameters): + inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']} + if self.name == "bwmux": inputs['S'] = parameters['WIDTH'] + write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters) + +class PMuxCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (width, s_width) in [(10, 1), (10, 4), (20, 4)]: + yield (f'{width}-{s_width}', + {'WIDTH' : width, + 'S_WIDTH' : s_width}) + def write_rtlil_file(self, f, parameters): + s_width = parameters['S_WIDTH'] + b_width = parameters['WIDTH'] * s_width + write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters) + +class BMuxCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (width, s_width) in [(10, 1), (10, 2), (10, 4)]: + yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters) + +class DemuxCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (width, s_width) in [(10, 1), (32, 2), (16, 4)]: + yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters) + +def seeded_randint(seed, a, b): + r = random.getstate() + random.seed(seed) + n = random.randint(a, b) + random.setstate(r) + return n + +class LUTCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for width in [4, 6, 8]: + lut = seeded_randint(width, 0, 2**width - 1) + yield (f'{width}', {'WIDTH' : width, 'LUT' : lut}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters) + +class ConcatCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]: + yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters) + +class SliceCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]: + yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width}) + def write_rtlil_file(self, f, parameters): + write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + +class FailCell(BaseCell): + def __init__(self, name): + super().__init__(name) + def generate_tests(self): + yield ('', {}) + def write_rtlil_file(self, f, parameters): + raise Exception(f'\'{self.name}\' cell unimplemented in test generator') + +rtlil_cells = [ + UnaryCell("not"), + UnaryCell("pos"), + UnaryCell("neg"), + BinaryCell("and"), + BinaryCell("or"), + BinaryCell("xor"), + BinaryCell("xnor"), + UnaryCell("reduce_and"), + UnaryCell("reduce_or"), + UnaryCell("reduce_xor"), + UnaryCell("reduce_xnor"), + UnaryCell("reduce_bool"), + ShiftCell("shl"), + ShiftCell("shr"), + ShiftCell("sshl"), + ShiftCell("sshr"), + ShiftCell("shift"), + ShiftCell("shiftx"), +# ("fa", ["A", "B", "C", "X", "Y"]), +# ("lcu", ["P", "G", "CI", "CO"]), +# ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]), + BinaryCell("lt"), + BinaryCell("le"), + BinaryCell("eq"), + BinaryCell("ne"), + BinaryCell("eqx"), + BinaryCell("nex"), + BinaryCell("ge"), + BinaryCell("gt"), + BinaryCell("add"), + BinaryCell("sub"), + BinaryCell("mul"), +# BinaryCell("macc"), + BinaryCell("div"), + BinaryCell("mod"), + BinaryCell("divfloor"), + BinaryCell("modfloor"), + BinaryCell("pow"), + UnaryCell("logic_not"), + BinaryCell("logic_and"), + BinaryCell("logic_or"), + SliceCell("slice"), + ConcatCell("concat"), + MuxCell("mux"), + BMuxCell("bmux"), + PMuxCell("pmux"), + DemuxCell("demux"), + LUTCell("lut"), +# ("sop", ["A", "Y"]), +# ("tribuf", ["A", "EN", "Y"]), +# ("specify2", ["EN", "SRC", "DST"]), +# ("specify3", ["EN", "SRC", "DST", "DAT"]), +# ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]), + BWCell("bweqx"), + BWCell("bwmux"), +# ("assert", ["A", "EN"]), +# ("assume", ["A", "EN"]), +# ("live", ["A", "EN"]), +# ("fair", ["A", "EN"]), +# ("cover", ["A", "EN"]), +# ("initstate", ["Y"]), +# ("anyconst", ["Y"]), +# ("anyseq", ["Y"]), +# ("anyinit", ["D", "Q"]), +# ("allconst", ["Y"]), +# ("allseq", ["Y"]), +# ("equiv", ["A", "B", "Y"]), +# ("print", ["EN", "TRG", "ARGS"]), +# ("check", ["A", "EN", "TRG", "ARGS"]), +# ("set_tag", ["A", "SET", "CLR", "Y"]), +# ("get_tag", ["A", "Y"]), +# ("overwrite_tag", ["A", "SET", "CLR"]), +# ("original_tag", ["A", "Y"]), +# ("future_ff", ["A", "Y"]), +# ("scopeinfo", []), +] + +def generate_test_cases(per_cell): + tests = [] + names = [] + for cell in rtlil_cells: + seen_names = set() + for (name, parameters) in cell.generate_tests(): + if not name in seen_names: + seen_names.add(name) + tests.append((cell, parameters)) + names.append(f'{cell.name}-{name}' if name != '' else cell.name) + if per_cell is not None and len(seen_names) >= per_cell: + break + return (names, tests) \ No newline at end of file diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh new file mode 100755 index 000000000..b9a0595f6 --- /dev/null +++ b/tests/functional/run-test.sh @@ -0,0 +1,2 @@ +#!/usr/bin/env bash +pytest -v "$@" diff --git a/tests/functional/single_cells/rtlil/README.md b/tests/functional/single_cells/rtlil/README.md deleted file mode 100644 index 4bb84565b..000000000 --- a/tests/functional/single_cells/rtlil/README.md +++ /dev/null @@ -1,2 +0,0 @@ -# Creation of test files -yosys -p "test_cell -n 1 -w test_cell all" \ No newline at end of file diff --git a/tests/functional/single_cells/rtlil/ff.il b/tests/functional/single_cells/rtlil/ff.il deleted file mode 100644 index 6e5a1a339..000000000 --- a/tests/functional/single_cells/rtlil/ff.il +++ /dev/null @@ -1,83 +0,0 @@ -# Generated by Yosys 0.40+7 (git sha1 4fd5b29f9, g++ 13.2.0 -Og -fPIC) -autoidx 19 -attribute \cells_not_processed 1 -attribute \src "dff.v:1.1-16.10" -module \gold - attribute \src "dff.v:8.5-14.8" - wire $0\q[0:0] - attribute \init 1'0 - wire $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 - attribute \init 1'1 - wire $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 - attribute \init 1'0 - wire $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 - attribute \init 1'x - wire $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 - wire $auto$rtlil.cc:2525:Eqx$10 - wire $auto$rtlil.cc:2582:Mux$12 - wire $auto$rtlil.cc:2582:Mux$16 - wire $auto$rtlil.cc:2582:Mux$18 - attribute \src "dff.v:2.16-2.19" - wire input 1 \clk - attribute \src "dff.v:4.16-4.17" - wire input 3 \d - attribute \keep 1 - attribute \src "dff.v:5.16-5.17" - wire output 4 \q - attribute \src "dff.v:3.16-3.21" - wire input 2 \reset - cell $mux $auto$clk2fflogic.cc:113:mux$11 - parameter \WIDTH 1 - connect \A $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 - connect \B $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 - connect \S $auto$rtlil.cc:2525:Eqx$10 - connect \Y $auto$rtlil.cc:2582:Mux$12 - end - cell $mux $auto$clk2fflogic.cc:113:mux$15 - parameter \WIDTH 1 - connect \A $auto$rtlil.cc:2582:Mux$12 - connect \B 1'0 - connect \S $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 - connect \Y $auto$rtlil.cc:2582:Mux$16 - end - cell $mux $auto$clk2fflogic.cc:113:mux$17 - parameter \WIDTH 1 - connect \A $auto$rtlil.cc:2582:Mux$16 - connect \B 1'0 - connect \S \reset - connect \Y $auto$rtlil.cc:2582:Mux$18 - end - cell $ff $auto$clk2fflogic.cc:70:sample_control$14 - parameter \WIDTH 1 - connect \D \reset - connect \Q $auto$clk2fflogic.cc:65:sample_control$\reset#sampled$13 - end - cell $ff $auto$clk2fflogic.cc:82:sample_control_edge$8 - parameter \WIDTH 1 - connect \D \clk - connect \Q $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 - end - cell $eqx $auto$clk2fflogic.cc:83:sample_control_edge$9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { $auto$clk2fflogic.cc:77:sample_control_edge$\clk#sampled$7 \clk } - connect \B 2'01 - connect \Y $auto$rtlil.cc:2525:Eqx$10 - end - attribute \clk2fflogic 1 - cell $ff $auto$clk2fflogic.cc:98:sample_data$4 - parameter \WIDTH 1 - connect \D \q - connect \Q $auto$clk2fflogic.cc:91:sample_data$\q#sampled$3 - end - cell $ff $auto$clk2fflogic.cc:98:sample_data$6 - parameter \WIDTH 1 - connect \D \d - connect \Q $auto$clk2fflogic.cc:91:sample_data$\d#sampled$5 - end - connect $0\q[0:0] \d - connect \q $auto$rtlil.cc:2582:Mux$18 -end diff --git a/tests/functional/single_cells/rtlil/multiple_outputs.il b/tests/functional/single_cells/rtlil/multiple_outputs.il deleted file mode 100644 index 5e9141a20..000000000 --- a/tests/functional/single_cells/rtlil/multiple_outputs.il +++ /dev/null @@ -1,69 +0,0 @@ -# Generated by Yosys 0.40+7 (git sha1 cc795a3f5, g++ 13.2.0 -Og -fPIC) -autoidx 5 -attribute \cells_not_processed 1 -attribute \src "multiple_outputs.v:1.1-15.10" -module \gold - attribute \src "multiple_outputs.v:11.12-11.20" - wire $and$multiple_outputs.v:11$2_Y - attribute \src "multiple_outputs.v:10.12-10.14" - wire $not$multiple_outputs.v:10$1_Y - attribute \src "multiple_outputs.v:12.12-12.20" - wire $or$multiple_outputs.v:12$3_Y - attribute \src "multiple_outputs.v:13.12-13.20" - wire $xor$multiple_outputs.v:13$4_Y - attribute \src "multiple_outputs.v:2.16-2.17" - wire input 1 \a - attribute \src "multiple_outputs.v:3.17-3.18" - wire output 2 \b - attribute \src "multiple_outputs.v:4.17-4.18" - wire output 3 \c - attribute \src "multiple_outputs.v:5.17-5.18" - wire output 4 \d - attribute \src "multiple_outputs.v:6.17-6.18" - wire output 5 \e - attribute \src "multiple_outputs.v:11.12-11.20" - cell $and $and$multiple_outputs.v:11$2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a - connect \B 1'1 - connect \Y $and$multiple_outputs.v:11$2_Y - end - attribute \src "multiple_outputs.v:10.12-10.14" - cell $not $not$multiple_outputs.v:10$1 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a - connect \Y $not$multiple_outputs.v:10$1_Y - end - attribute \src "multiple_outputs.v:12.12-12.20" - cell $or $or$multiple_outputs.v:12$3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a - connect \B 1'0 - connect \Y $or$multiple_outputs.v:12$3_Y - end - attribute \src "multiple_outputs.v:13.12-13.20" - cell $xor $xor$multiple_outputs.v:13$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a - connect \B 1'1 - connect \Y $xor$multiple_outputs.v:13$4_Y - end - connect \b $not$multiple_outputs.v:10$1_Y - connect \c $and$multiple_outputs.v:11$2_Y - connect \d $or$multiple_outputs.v:12$3_Y - connect \e $xor$multiple_outputs.v:13$4_Y -end diff --git a/tests/functional/single_cells/rtlil/test_cell_add_00000.il b/tests/functional/single_cells/rtlil/test_cell_add_00000.il deleted file mode 100644 index 531dabe41..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_add_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 5 input 1 \A - wire width 4 input 2 \B - wire width 6 output 3 \Y - cell $add \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 5 - parameter \B_SIGNED 1 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il b/tests/functional/single_cells/rtlil/test_cell_alu_00000.il deleted file mode 100644 index ebdd3b734..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_alu_00000.il +++ /dev/null @@ -1,25 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire width 7 input 2 \B - wire input 3 \BI - wire input 4 \CI - wire width 6 output 5 \CO - wire width 6 output 6 \X - wire width 6 output 7 \Y - cell $alu \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \BI \BI - connect \CI \CI - connect \CO \CO - connect \X \X - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_and_00000.il deleted file mode 100644 index 2578f60b7..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_and_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 2 input 1 \A - wire width 3 input 2 \B - wire width 2 output 3 \Y - cell $and \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 2 - parameter \B_SIGNED 1 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 2 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il b/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il deleted file mode 100644 index 1b613bd69..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_bmux_00000.il +++ /dev/null @@ -1,14 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire input 2 \S - wire width 4 output 3 \Y - cell $bmux \UUT - parameter \S_WIDTH 1 - parameter \WIDTH 4 - connect \A \A - connect \S \S - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il b/tests/functional/single_cells/rtlil/test_cell_demux_00000.il deleted file mode 100644 index dbe2dee62..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_demux_00000.il +++ /dev/null @@ -1,14 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 5 input 2 \S - wire width 192 output 3 \Y - cell $demux \UUT - parameter \S_WIDTH 5 - parameter \WIDTH 6 - connect \A \A - connect \S \S - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_div_00000.il b/tests/functional/single_cells/rtlil/test_cell_div_00000.il deleted file mode 100644 index 6f278a7a0..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_div_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire width 6 input 2 \B - wire output 3 \Y - cell $div \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il deleted file mode 100644 index 67fce36b3..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_divfloor_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire width 4 input 2 \B - wire width 6 output 3 \Y - cell $divfloor \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il b/tests/functional/single_cells/rtlil/test_cell_eq_00000.il deleted file mode 100644 index 06fef02b5..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_eq_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 5 input 1 \A - wire input 2 \B - wire width 4 output 3 \Y - cell $eq \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il b/tests/functional/single_cells/rtlil/test_cell_fa_00000.il deleted file mode 100644 index 97f0eb029..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_fa_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \A - wire input 2 \B - wire input 3 \C - wire output 4 \X - wire output 5 \Y - cell $fa \UUT - parameter \WIDTH 1 - connect \A \A - connect \B \B - connect \C \C - connect \X \X - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il b/tests/functional/single_cells/rtlil/test_cell_ge_00000.il deleted file mode 100644 index 0ac72e943..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_ge_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 3 input 1 \A - wire width 7 input 2 \B - wire width 6 output 3 \Y - cell $ge \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 3 - parameter \B_SIGNED 1 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il b/tests/functional/single_cells/rtlil/test_cell_gt_00000.il deleted file mode 100644 index d4498d36f..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_gt_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire width 3 input 2 \B - wire width 4 output 3 \Y - cell $gt \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \B_SIGNED 1 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il b/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il deleted file mode 100644 index e1bda0b43..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_lcu_00000.il +++ /dev/null @@ -1,15 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \CI - wire width 2 output 2 \CO - wire width 2 input 3 \G - wire width 2 input 4 \P - cell $lcu \UUT - parameter \WIDTH 2 - connect \CI \CI - connect \CO \CO - connect \G \G - connect \P \P - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_le_00000.il b/tests/functional/single_cells/rtlil/test_cell_le_00000.il deleted file mode 100644 index 609d99ce8..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_le_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 5 input 1 \A - wire width 4 input 2 \B - wire width 6 output 3 \Y - cell $le \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 5 - parameter \B_SIGNED 1 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il deleted file mode 100644 index 2eae6e3fc..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_logic_and_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 2 input 1 \A - wire width 7 input 2 \B - wire output 3 \Y - cell $logic_and \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il deleted file mode 100644 index c7898491c..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_logic_not_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 3 input 1 \A - wire width 8 output 2 \Y - cell $logic_not \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il deleted file mode 100644 index 7a1ef6cbd..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_logic_or_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire width 7 input 2 \B - wire width 2 output 3 \Y - cell $logic_or \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 2 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il b/tests/functional/single_cells/rtlil/test_cell_lt_00000.il deleted file mode 100644 index fd3ee1f8b..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_lt_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire width 5 input 2 \B - wire width 6 output 3 \Y - cell $lt \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il b/tests/functional/single_cells/rtlil/test_cell_lut_00000.il deleted file mode 100644 index 7c4882bb6..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_lut_00000.il +++ /dev/null @@ -1,12 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 2 input 1 \A - wire output 2 \Y - cell $lut \UUT - parameter \LUT 4'1111 - parameter \WIDTH 2 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il b/tests/functional/single_cells/rtlil/test_cell_macc_00000.il deleted file mode 100644 index 66b51634e..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_macc_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 3 input 1 \A - wire width 0 input 2 \B - wire width 2 output 3 \Y - cell $macc \UUT - parameter \A_WIDTH 3 - parameter \B_WIDTH 0 - parameter \CONFIG 10'0110000010 - parameter \CONFIG_WIDTH 10 - parameter \Y_WIDTH 2 - connect \A \A - connect \B { } - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il b/tests/functional/single_cells/rtlil/test_cell_mod_00000.il deleted file mode 100644 index a484918f0..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_mod_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 8 input 2 \B - wire width 2 output 3 \Y - cell $mod \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 2 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il b/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il deleted file mode 100644 index 6cd00aeea..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_modfloor_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 5 input 1 \A - wire width 7 input 2 \B - wire width 4 output 3 \Y - cell $modfloor \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il b/tests/functional/single_cells/rtlil/test_cell_mul_00000.il deleted file mode 100644 index c77aaffb8..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_mul_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 2 input 2 \B - wire width 5 output 3 \Y - cell $mul \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 5 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il b/tests/functional/single_cells/rtlil/test_cell_mux_00000.il deleted file mode 100644 index 3fc52ac77..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_mux_00000.il +++ /dev/null @@ -1,15 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire width 4 input 2 \B - wire input 3 \S - wire width 4 output 4 \Y - cell $mux \UUT - parameter \WIDTH 4 - connect \A \A - connect \B \B - connect \S \S - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il b/tests/functional/single_cells/rtlil/test_cell_ne_00000.il deleted file mode 100644 index 47ba31397..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_ne_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire width 5 input 2 \B - wire width 4 output 3 \Y - cell $ne \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il b/tests/functional/single_cells/rtlil/test_cell_neg_00000.il deleted file mode 100644 index ee4273508..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_neg_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 2 input 1 \A - wire width 5 output 2 \Y - cell $neg \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 5 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_not_00000.il b/tests/functional/single_cells/rtlil/test_cell_not_00000.il deleted file mode 100644 index 9281ded0d..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_not_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire width 7 output 2 \Y - cell $not \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_or_00000.il deleted file mode 100644 index 100ea42cd..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_or_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire input 2 \B - wire width 2 output 3 \Y - cell $or \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \B_SIGNED 1 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il b/tests/functional/single_cells/rtlil/test_cell_pos_00000.il deleted file mode 100644 index 182f0acd3..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_pos_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \A - wire width 3 output 2 \Y - cell $pos \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il b/tests/functional/single_cells/rtlil/test_cell_pos_00001.il deleted file mode 100644 index 96e9c895a..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_pos_00001.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.40+7 (git sha1 d8b5b90e7, g++ 13.2.0 -Og -fPIC) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 6 output 2 \Y - cell $pos \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il deleted file mode 100644 index 079ed33ad..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_reduce_and_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire width 5 output 2 \Y - cell $reduce_and \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il deleted file mode 100644 index a417179c8..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_reduce_bool_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \A - wire width 2 output 2 \Y - cell $reduce_bool \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il deleted file mode 100644 index 881c6dfe3..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_reduce_or_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 2 input 1 \A - wire width 7 output 2 \Y - cell $reduce_or \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 7 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il deleted file mode 100644 index c06562729..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_reduce_xnor_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire width 4 output 2 \Y - cell $reduce_xnor \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il deleted file mode 100644 index 428d2ea87..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_reduce_xor_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 4 input 1 \A - wire output 2 \Y - cell $reduce_xor \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il b/tests/functional/single_cells/rtlil/test_cell_shift_00000.il deleted file mode 100644 index f82a2a79d..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_shift_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \A - wire width 6 input 2 \B - wire width 4 output 3 \Y - cell $shift \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 1 - parameter \B_SIGNED 1 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il b/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il deleted file mode 100644 index b89ac5bef..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_shiftx_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire input 1 \A - wire width 5 input 2 \B - wire width 3 output 3 \Y - cell $shiftx \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 3 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il b/tests/functional/single_cells/rtlil/test_cell_shl_00000.il deleted file mode 100644 index 1cfee2a52..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_shl_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire width 2 input 2 \B - wire width 3 output 3 \Y - cell $shl \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il b/tests/functional/single_cells/rtlil/test_cell_shr_00000.il deleted file mode 100644 index 35dd37909..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_shr_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire width 6 input 2 \B - wire width 4 output 3 \Y - cell $shr \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 4 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il b/tests/functional/single_cells/rtlil/test_cell_sop_00000.il deleted file mode 100644 index df0f8f20a..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_sop_00000.il +++ /dev/null @@ -1,13 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 8 input 1 \A - wire output 2 \Y - cell $sop \UUT - parameter \DEPTH 8 - parameter \TABLE 128'10010000100100000101101010001001101000101010010100010000010100000101010100000001001010010110101010101010101000100100011001000110 - parameter \WIDTH 8 - connect \A \A - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il deleted file mode 100644 index 798288754..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_sshl_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 5 input 1 \A - wire width 3 input 2 \B - wire width 6 output 3 \Y - cell $sshl \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il b/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il deleted file mode 100644 index 3f59a693f..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_sshr_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 3 input 1 \A - wire width 2 input 2 \B - wire width 2 output 3 \Y - cell $sshr \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il b/tests/functional/single_cells/rtlil/test_cell_sub_00000.il deleted file mode 100644 index cb9ec2f79..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_sub_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 6 input 2 \B - wire width 6 output 3 \Y - cell $sub \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il deleted file mode 100644 index 85bd7d239..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_xnor_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 7 input 1 \A - wire width 8 input 2 \B - wire width 7 output 3 \Y - cell $xnor \UUT - parameter \A_SIGNED 1 - parameter \A_WIDTH 7 - parameter \B_SIGNED 1 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 7 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il b/tests/functional/single_cells/rtlil/test_cell_xor_00000.il deleted file mode 100644 index 2359698b5..000000000 --- a/tests/functional/single_cells/rtlil/test_cell_xor_00000.il +++ /dev/null @@ -1,17 +0,0 @@ -# Generated by Yosys 0.41+101 (git sha1 83a8e5de4, g++ 13.2.0 -fPIC -Os) -autoidx 1 -module \gold - wire width 6 input 1 \A - wire width 2 input 2 \B - wire width 8 output 3 \Y - cell $xor \UUT - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 8 - connect \A \A - connect \B \B - connect \Y \Y - end -end diff --git a/tests/functional/single_cells/run-test.sh b/tests/functional/single_cells/run-test.sh deleted file mode 100755 index cc6bcf160..000000000 --- a/tests/functional/single_cells/run-test.sh +++ /dev/null @@ -1,172 +0,0 @@ -#!/bin/bash - -declare -A cxx_failing_files -declare -A smt_failing_files -declare -A cxx_successful_files -declare -A smt_successful_files - -run_cxx_test() { - BASE_PATH="../../../" - - local rtlil_file=$1 - - local base_name=$(basename "$rtlil_file" .v) - - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_cxx my_module_functional_cxx.cc"; then - echo "Yosys processed $rtlil_file successfully." - - if ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -std=c++17 -o vcd_harness; then - echo "Compilation successful." - if ./vcd_harness ${base_name}_functional_cxx.vcd; then - - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -r ${base_name}_functional_cxx.vcd -scope gold -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-gold"; then - echo "Yosys sim $rtlil_file successfully." - cxx_successful_files["$rtlil_file"]="Success" - else - ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope gold -timescale 1us" - echo "Yosys simulation of $rtlil_file failed. There is a discrepancy with functional cxx" - cxx_failing_files["$rtlil_file"]="Yosys sim failure" - fi - - else - echo "Failed to generate VCD files for $rtlil_file." - cxx_failing_files["$rtlil_file"]="VCD generation failure" - fi - else - echo "Failed to compile harness for $rtlil_file." - cxx_failing_files["$rtlil_file"]="Compilation failure" - fi - else - echo "Yosys failed to process $rtlil_file." - cxx_failing_files["$rtlil_file"]="Yosys failure" - fi -} - -run_smt_test() { - BASE_PATH="../../../" - - local rtlil_file=$1 - - local base_name=$(basename "$rtlil_file" .il) - - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; write_functional_smt2 ${base_name}.smt2"; then - echo "Yosys processed $rtlil_file successfully." - # TODO: which SMT solver should be run? - if z3 "${base_name}.smt2"; then - echo "SMT file ${base_name}.smt2 is valid ." - if python3 vcd_harness_smt.py "${base_name}.smt2"; then - echo "Python script generated VCD file for $rtlil_file successfully." - - if [ -f "${base_name}.smt2.vcd" ]; then - echo "VCD file ${base_name}.vcd generated successfully by Python." - - if ${BASE_PATH}yosys -p "read_rtlil $rtlil_file; sim -vcd ${base_name}_yosys.vcd -r ${base_name}.smt2.vcd -scope gold -timescale 1us"; then - echo "Yosys simulation for $rtlil_file completed successfully." - smt_successful_files["$rtlil_file"]="Success" - else - echo "Yosys simulation failed for $rtlil_file." - smt_failing_files["$rtlil_file"]="Yosys simulation failure" - fi - else - echo "Failed to generate VCD file (${base_name}.vcd) for $rtlil_file. " - smt_failing_files["$rtlil_file"]="VCD generation failure" - fi - else - echo "Failed to run Python script for $rtlil_file." - smt_failing_files["$rtlil_file"]="Python script failure" - fi - else - echo "SMT file for $rtlil_file is invalid" - smt_failing_files["$rtlil_file"]="Invalid SMT" - fi - else - echo "Yosys failed to process $rtlil_file." - smt_failing_files["$rtlil_file"]="Yosys failure" - fi -} - - -run_all_tests() { - declare -A cxx_failing_files - declare -A smt_failing_files - declare -A cxx_successful_files - declare -A smt_successful_files - return_code=0 - for rtlil_file in rtlil/*.il; do - run_cxx_test "$rtlil_file" - run_smt_test "$rtlil_file" - done - - echo "C++ tests results:" - if [ ${#cxx_failing_files[@]} -eq 0 ]; then - echo "All files passed." - echo "The following files passed:" - for file in "${!cxx_successful_files[@]}"; do - echo "$file" - done - else - echo "The following files failed:" - for file in "${!cxx_failing_files[@]}"; do - echo "$file: ${cxx_failing_files[$file]}" - done - echo "The following files passed:" - for file in "${!cxx_successful_files[@]}"; do - echo "$file" - done - return_code=1 - fi - - echo "SMT tests results:" - if [ ${#smt_failing_files[@]} -eq 0 ]; then - echo "All files passed." - echo "The following files passed:" - for file in "${!smt_successful_files[@]}"; do - echo "$file" - done - else - echo "The following files failed:" - for file in "${!smt_failing_files[@]}"; do - echo "$file: ${smt_failing_files[$file]}" - done - echo "The following files passed:" - for file in "${!smt_successful_files[@]}"; do - echo "$file" - done - return_code=1 - fi - return $return_code -} - -run_smt_tests() { - declare -A smt_failing_files - declare -A smt_successful_files - return_code=0 - for rtlil_file in rtlil/*.il; do - run_smt_test "$rtlil_file" - done - - echo "SMT tests results:" - if [ ${#smt_failing_files[@]} -eq 0 ]; then - echo "All files passed." - echo "The following files passed:" - for file in "${!smt_successful_files[@]}"; do - echo "$file" - done - else - echo "The following files failed:" - for file in "${!smt_failing_files[@]}"; do - echo "$file: ${smt_failing_files[$file]}" - done - echo "The following files passed:" - for file in "${!smt_successful_files[@]}"; do - echo "$file" - done - return_code=1 - fi - return $return_code -} - -# If the script is being sourced, do not execute the tests -if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then - run_all_tests -fi diff --git a/tests/functional/single_cells/vcd_harness_smt.py b/tests/functional/single_cells/vcd_harness_smt.py deleted file mode 100644 index 95947748f..000000000 --- a/tests/functional/single_cells/vcd_harness_smt.py +++ /dev/null @@ -1,214 +0,0 @@ -import sys -import argparse -import random -import os - -# Parse command line arguments -parser = argparse.ArgumentParser(description='Process SMT file for simulation.') -parser.add_argument('smt_file', help='Path to the SMT file to simulate.') -args = parser.parse_args() - -# Get the SMT file path from the command line argument -smt_file_path = args.smt_file -current_file_path = os.path.abspath(__file__) -# Navigate to the directory you need relative to the current script -# Assuming 'backends/smt2' is located three directories up from the current script -desired_path = os.path.join(os.path.dirname(current_file_path), '..', '..', '..', 'backends', 'functional') - -# Normalize the path to resolve any '..' -normalized_path = os.path.normpath(desired_path) - -# Append the directory to the Python path -sys.path.append(normalized_path) - -# Import the module -import smtio - -# Assuming the SmtIo class and other dependencies are available in your environment -# You may need to include the entire script provided above in your script or have it available as a module - -# Step 1: Initialize an SmtIo object - -so = smtio.SmtOpts() -so.solver = "z3" -so.logic = "BV" -so.debug_print = True -# so.debug_file = "my_debug" -smt_io = smtio.SmtIo(opts=so) -# List to store the parsed results -parsed_results = [] - -# Load and execute the SMT file -with open(smt_file_path, 'r') as smt_file: - for line in smt_file: - smt_io.write(line.strip()) -smt_io.check_sat() -# Read and parse the SMT file line by line -with open(smt_file_path, 'r') as smt_file: - for line in smt_file: - # Strip leading/trailing whitespace - stripped_line = line.strip() - - # Ignore empty lines - if not stripped_line: - continue - # comments - if stripped_line.startswith(';'): - smt_io.info(stripped_line) - - # Parse the line using SmtIo's parse method - parsed_line = smt_io.parse(stripped_line) - - # Append the parsed result to the list - parsed_results.append(parsed_line) - -# Display the parsed results -for result in parsed_results: - print(result) - -inputs = {} -outputs = {} - -for lst in parsed_results: - if lst[0] == 'declare-datatypes': - for datatype_group in lst[2]: # Navigate into the nested lists - datatype_name = datatype_group[0] - declarations = datatype_group[1][1:] # Skip the first item (e.g., 'mk_inputs') - if datatype_name == 'Inputs': - for declaration in declarations: - print("My declaration") - print(declaration) - input_name = declaration[0] - bitvec_size = declaration[1][2] - inputs[input_name] = int(bitvec_size) - elif datatype_name == 'Outputs': - for declaration in declarations: - output_name = declaration[0] - bitvec_size = declaration[1][2] - outputs[output_name] = int(bitvec_size) - -print(inputs) -print(outputs) -def set_step(inputs, step): - # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} - # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. - - # Construct input definitions - mk_inputs_parts = [] - for input_name, width in inputs.items(): - value = random.getrandbits(width) # Generate a random number up to the maximum value for the bit size - binary_string = format(value, '0{}b'.format(width)) # Convert value to binary with leading zeros - mk_inputs_parts.append(f"#b{binary_string}") - - # Join all parts for the mk_inputs constructor - mk_inputs_call = "mk_inputs " + " ".join(mk_inputs_parts) - define_inputs = f"(define-const test_inputs_step_n{step} Inputs ({mk_inputs_call}))\n" - - # Create the output definition by calling the gold_step function - define_output = f"(define-const test_outputs_step_n{step} Outputs (gold_step test_inputs_step_n{step}))\n" - smt_commands = [] - smt_commands.append(define_inputs) - smt_commands.append(define_output) - return smt_commands - -num_steps = 10 -smt_commands = [] -# Loop to generate SMT commands for each step -for step in range(num_steps): - for step_command in set_step(inputs, step): - smt_commands.append(step_command) - -# Print or write the SMT commands to a file -smt_file_content = ''.join(smt_commands) -print(smt_file_content) # Print to console - -# Optionally, write to a file -with open('dynamic_commands.smt2', 'w') as smt_file: - smt_file.write(smt_file_content) - -# Execute the SMT commands -for command in smt_commands: - print(command) - smt_io.write(command.strip()) - -# Check for satisfiability -# smt_io.setup() -result = smt_io.check_sat() -print(f'SAT result: {result}') -if result != 'sat': - smt_io.p_close() - sys.exit(1) - -# Store signal values -signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())} -# Retrieve and print values for each state -def hex_to_bin(value): - if value.startswith('x'): - hex_value = value[1:] # Remove the 'x' prefix - bin_value = bin(int(hex_value, 16))[2:] # Convert to binary and remove the '0b' prefix - return f'b{bin_value.zfill(len(hex_value) * 4)}' # Add 'b' prefix and pad with zeros - return value - -combined_assertions = [] -for step in range(num_steps): - print(f"Values for step {step + 1}:") - for input_name, width in inputs.items(): - value = smt_io.get(f'({input_name} test_inputs_step_n{step})') - value = hex_to_bin(value[1:]) - print(f" {input_name}: {value}") - signals[input_name].append((step, value)) - for output_name, width in outputs.items(): - value = smt_io.get(f'({output_name} test_outputs_step_n{step})') - value = hex_to_bin(value[1:]) - print(f" {output_name}: {value}") - signals[output_name].append((step, value)) - combined_assertions.append(f'(= ({output_name} test_outputs_step_n{step}) #{value})') -# Create a single assertion covering all timesteps -combined_condition = " ".join(combined_assertions) -smt_io.write(f'(assert (not (and {combined_condition})))') - -# Check the combined assertion -result = smt_io.check_sat(["unsat"]) -if result != 'unsat': - smt_io.p_close() - sys.exit(1) - -smt_io.p_close() - -def write_vcd(filename, signals, timescale='1 ns', date='today'): - with open(filename, 'w') as f: - # Write the header - f.write(f"$date\n {date}\n$end\n") - f.write(f"$timescale {timescale} $end\n") - - # Declare signals - f.write("$scope module gold $end\n") - for signal_name, changes in signals.items(): - signal_size = len(changes[0][1]) - f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") - f.write("$upscope $end\n") - f.write("$enddefinitions $end\n") - - # Collect all unique timestamps - timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) - - # Write initial values - f.write("#0\n") - for signal_name, changes in signals.items(): - for time, value in changes: - if time == 0: - f.write(f"{value} {signal_name}\n") - - # Write value changes - for time in timestamps: - if time != 0: - f.write(f"#{time}\n") - for signal_name, changes in signals.items(): - for change_time, value in changes: - if change_time == time: - f.write(f"b{value} {signal_name}\n") - - -# Write the VCD file -write_vcd(smt_file_path + '.vcd', signals) -sys.exit(0) diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py new file mode 100644 index 000000000..c38fe1bde --- /dev/null +++ b/tests/functional/smt_vcd.py @@ -0,0 +1,180 @@ +import sys +import argparse +import random +import os +import smtio +import re + +class SExprParserError(Exception): + pass + +class SExprParser: + def __init__(self): + self.peekbuf = None + self.stack = [[]] + self.atom_pattern = re.compile(r'[a-zA-Z0-9~!@$%^&*_\-+=<>.?/#]+') + def parse_line(self, line): + ptr = 0 + while ptr < len(line): + if line[ptr].isspace(): + ptr += 1 + elif line[ptr] == ';': + break + elif line[ptr] == '(': + ptr += 1 + self.stack.append([]) + elif line[ptr] == ')': + ptr += 1 + assert len(self.stack) > 1, "too many closed parentheses" + v = self.stack.pop() + self.stack[-1].append(v) + else: + match = self.atom_pattern.match(line, ptr) + if match is None: + raise SExprParserError(f"invalid character '{line[ptr]}' in line '{line}'") + start, ptr = match.span() + self.stack[-1].append(line[start:ptr]) + def finish(self): + assert len(self.stack) == 1, "too many open parentheses" + def retrieve(self): + rv, self.stack[0] = self.stack[0], [] + return rv + +def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io): + inputs = {} + outputs = {} + + def handle_datatype(lst): + print(lst) + datatype_name = lst[1] + declarations = lst[2][0][1:] # Skip the first item (e.g., 'mk_inputs') + if datatype_name.endswith("_Inputs"): + for declaration in declarations: + input_name = declaration[0] + bitvec_size = declaration[1][2] + assert input_name.startswith("gold_Inputs_") + inputs[input_name[len("gold_Inputs_"):]] = int(bitvec_size) + elif datatype_name.endswith("_Outputs"): + for declaration in declarations: + output_name = declaration[0] + bitvec_size = declaration[1][2] + assert output_name.startswith("gold_Outputs_") + outputs[output_name[len("gold_Outputs_"):]] = int(bitvec_size) + + parser = SExprParser() + with open(smt_file_path, 'r') as smt_file: + for line in smt_file: + parser.parse_line(line) + for expr in parser.retrieve(): + smt_io.write(smt_io.unparse(expr)) + if expr[0] == "declare-datatype": + handle_datatype(expr) + + parser.finish() + assert smt_io.check_sat() == 'sat' + + def set_step(inputs, step): + # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} + # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. + + mk_inputs_parts = [] + for input_name, width in inputs.items(): + value = random.getrandbits(width) # Generate a random number up to the maximum value for the bit size + binary_string = format(value, '0{}b'.format(width)) # Convert value to binary with leading zeros + mk_inputs_parts.append(f"#b{binary_string}") + + mk_inputs_call = "gold_Inputs " + " ".join(mk_inputs_parts) + define_inputs = f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n" + + define_outputs = f"(define-const test_outputs_step_n{step} gold_Outputs (first (gold test_inputs_step_n{step} gold_State)))\n" + smt_commands = [define_inputs, define_outputs] + return smt_commands + + num_steps = 1000 + smt_commands = [] + for step in range(num_steps): + for step_command in set_step(inputs, step): + smt_commands.append(step_command) + + for command in smt_commands: + smt_io.write(command) + + assert smt_io.check_sat() == 'sat' + + # Store signal values + signals = {name: [] for name in list(inputs.keys()) + list(outputs.keys())} + # Retrieve and print values for each state + def hex_to_bin(value): + if value.startswith('x'): + hex_value = value[1:] # Remove the 'x' prefix + bin_value = bin(int(hex_value, 16))[2:] # Convert to binary and remove the '0b' prefix + return f'b{bin_value.zfill(len(hex_value) * 4)}' # Add 'b' prefix and pad with zeros + return value + + combined_assertions = [] + for step in range(num_steps): + print(f"Values for step {step + 1}:") + for input_name, width in inputs.items(): + value = smt_io.get(f'(gold_Inputs_{input_name} test_inputs_step_n{step})') + value = hex_to_bin(value[1:]) + print(f" {input_name}: {value}") + signals[input_name].append((step, value)) + for output_name, width in outputs.items(): + value = smt_io.get(f'(gold_Outputs_{output_name} test_outputs_step_n{step})') + value = hex_to_bin(value[1:]) + print(f" {output_name}: {value}") + signals[output_name].append((step, value)) + combined_assertions.append(f'(= (gold_Outputs_{output_name} test_outputs_step_n{step}) #{value})') + # Create a single assertion covering all timesteps + combined_condition = " ".join(combined_assertions) + smt_io.write(f'(assert (not (and {combined_condition})))') + + # Check the combined assertion + assert smt_io.check_sat(["unsat"]) == "unsat" + + def write_vcd(filename, signals, timescale='1 ns', date='today'): + with open(filename, 'w') as f: + # Write the header + f.write(f"$date\n {date}\n$end\n") + f.write(f"$timescale {timescale} $end\n") + + # Declare signals + f.write("$scope module gold $end\n") + for signal_name, changes in signals.items(): + signal_size = len(changes[0][1]) + f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") + f.write("$upscope $end\n") + f.write("$enddefinitions $end\n") + + # Collect all unique timestamps + timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) + + # Write initial values + f.write("#0\n") + for signal_name, changes in signals.items(): + for time, value in changes: + if time == 0: + f.write(f"{value} {signal_name}\n") + + # Write value changes + for time in timestamps: + if time != 0: + f.write(f"#{time}\n") + for signal_name, changes in signals.items(): + for change_time, value in changes: + if change_time == time: + f.write(f"{value} {signal_name}\n") + + + write_vcd(vcd_path, signals) + +def simulate_smt(smt_file_path, vcd_path): + so = smtio.SmtOpts() + so.solver = "z3" + so.logic = "BV" + so.debug_print = True + smt_io = smtio.SmtIo(opts=so) + try: + simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io) + finally: + smt_io.p_close() \ No newline at end of file diff --git a/backends/functional/smtio.py b/tests/functional/smtio.py similarity index 100% rename from backends/functional/smtio.py rename to tests/functional/smtio.py diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py new file mode 100644 index 000000000..9b4fab970 --- /dev/null +++ b/tests/functional/test_functional.py @@ -0,0 +1,63 @@ +import subprocess +import pytest +import sys +import shlex +from pathlib import Path + +base_path = Path(__file__).resolve().parent.parent.parent + +def quote(path): + return shlex.quote(str(path)) + +def run(cmd, **kwargs): + print(' '.join([shlex.quote(str(x)) for x in cmd])) + status = subprocess.run(cmd, **kwargs) + assert status.returncode == 0, f"{cmd[0]} failed" + +def yosys(script): + run([base_path / 'yosys', '-Q', '-p', script]) + +def compile_cpp(in_path, out_path, args): + run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) + +def test_cxx(cell, parameters, tmp_path): + rtlil_file = tmp_path / 'rtlil.il' + vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc' + cc_file = tmp_path / 'my_module_functional_cxx.cc' + vcdharness_exe_file = tmp_path / 'a.out' + vcd_functional_file = tmp_path / 'functional.vcd' + vcd_yosys_sim_file = tmp_path / 'yosys.vcd' + + with open(rtlil_file, 'w') as f: + cell.write_rtlil_file(f, parameters) + yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}") + compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')]) + run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file)]) + try: + yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold") + except: + subprocess.run([base_path / 'yosys', '-Q', '-p', + f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'], + capture_output=True, check=False) + raise + +def test_smt(cell, parameters, tmp_path): + import smt_vcd + + rtlil_file = tmp_path / 'rtlil.il' + smt_file = tmp_path / 'smtlib.smt' + vcd_functional_file = tmp_path / 'functional.vcd' + vcd_yosys_sim_file = tmp_path / 'yosys.vcd' + + with open(rtlil_file, 'w') as f: + cell.write_rtlil_file(f, parameters) + yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}") + run(['z3', smt_file]) + smt_vcd.simulate_smt(smt_file, vcd_functional_file) + try: + yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold") + except: + subprocess.run([base_path / 'yosys', '-Q', '-p', + f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'], + capture_output=True, check=False) + raise \ No newline at end of file diff --git a/tests/functional/single_cells/vcd_harness.cc b/tests/functional/vcd_harness.cc similarity index 98% rename from tests/functional/single_cells/vcd_harness.cc rename to tests/functional/vcd_harness.cc index 9b3777c37..f99d2909b 100644 --- a/tests/functional/single_cells/vcd_harness.cc +++ b/tests/functional/vcd_harness.cc @@ -68,7 +68,7 @@ int main(int argc, char **argv) const std::string functional_vcd_filename = argv[1]; - constexpr int steps = 10; + constexpr int steps = 1000; constexpr int number_timescale = 1; const std::string units_timescale = "us"; gold::Inputs inputs; From 6922633b0b1255975ceda7f3dd734946d85f08ea Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 16 Jul 2024 17:55:26 +0100 Subject: [PATCH 135/342] fix a few bugs in the functional backend and refactor the testing --- kernel/functionalir.cc | 40 ++- tests/functional/conftest.py | 26 +- tests/functional/rtlil_cells.py | 393 +++++++++++++++------------- tests/functional/smt_vcd.py | 53 +++- tests/functional/test_functional.py | 55 ++-- tests/functional/vcd_harness.cc | 69 +++-- 6 files changed, 366 insertions(+), 270 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 6983facfb..b8fa6b88e 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -226,26 +226,36 @@ public: T b = extend(inputs.at(ID(B)), b_width, width, is_signed); if(is_signed) { if(cellType == ID($div)) { + // divide absolute values, then flip the sign if input signs differ + // but extend the width first, to handle the case (most negative value) / (-1) T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width); T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1); - return neg_if(extend(abs_y, width, y_width, true), y_width, out_sign); + return neg_if(extend(abs_y, width, y_width, false), y_width, out_sign); } else if(cellType == ID($mod)) { + // similar to division but output sign == divisor sign T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width); - return neg_if(extend(abs_y, width, y_width, true), y_width, sign(a, width)); + return neg_if(extend(abs_y, width, y_width, false), y_width, sign(a, width)); } else if(cellType == ID($divfloor)) { + // if b is negative, flip both signs so that b is positive T b_sign = sign(b, width); T a1 = neg_if(a, width, b_sign); T b1 = neg_if(b, width, b_sign); - T a1_sign = sign(a1, width); + // if a is now negative, calculate ~((~a) / b) = -((-a - 1) / b + 1) + // which equals the negative of (-a) / b with rounding up rather than down + // note that to handle the case where a = most negative value properly, + // we have to calculate a1_sign from the original values rather than using sign(a1, width) + T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), reduce_or(a, width), 1); T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width); T y1 = factory.unsigned_div(a2, b1, width); - T y2 = factory.mux(y1, factory.bitwise_not(y1, width), a1_sign, width); - return extend(y2, width, y_width, true); + T y2 = extend(y1, width, y_width, false); + return factory.mux(y2, factory.bitwise_not(y2, y_width), a1_sign, y_width); } else if(cellType == ID($modfloor)) { + // calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero T abs_b = abs(b, width); T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width); T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1); T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width); + // since y_flipped is strictly less than |b|, the top bit is always 0 and we can just sign extend the flipped result T y = neg_if(y_flipped, width, sign(b, b_width)); return extend(y, width, y_width, true); } else @@ -261,22 +271,8 @@ public: } else if (cellType == ID($lut)) { int width = parameters.at(ID(WIDTH)).as_int(); Const lut_table = parameters.at(ID(LUT)); - T a = inputs.at(ID(A)); - // Output initialization - T y = factory.constant(Const(0, 1)); - // Iterate over each possible input combination - for (int i = 0; i < (1 << width); ++i) { - // Create a constant representing the value of i - T i_val = factory.constant(Const(i, width)); - // Check if the input matches this value - T match = factory.equal(a, i_val, width); - // Get the corresponding LUT value - bool lut_val = lut_table.bits[i] == State::S1; - T lut_output = factory.constant(Const(lut_val, 1)); - // Use a multiplexer to select the correct output based on the match - y = factory.mux(y, lut_output, match, 1); - } - return y; + lut_table.extu(1 << width); + return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 1 << width, 0, 1, width, width); } else if (cellType == ID($bwmux)) { int width = parameters.at(ID(WIDTH)).as_int(); T a = inputs.at(ID(A)); @@ -526,7 +522,7 @@ void FunctionalIR::topological_sort() { if(scc) log_error("combinational loops, aborting\n"); } -IdString merge_name(IdString a, IdString b) { +static IdString merge_name(IdString a, IdString b) { if(a[0] == '$' && b[0] == '\\') return b; else diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py index 3a66abaab..12db7f1d0 100644 --- a/tests/functional/conftest.py +++ b/tests/functional/conftest.py @@ -1,14 +1,30 @@ import pytest from rtlil_cells import generate_test_cases +import random + +random_seed = random.getrandbits(32) def pytest_addoption(parser): - parser.addoption( - "--per-cell", type=int, default=None, help="run only N tests per cell" - ) + parser.addoption("--per-cell", type=int, default=None, help="run only N tests per cell") + parser.addoption("--steps", type=int, default=1000, help="run each test for N steps") + parser.addoption("--seed", type=int, default=random_seed, help="seed for random number generation, use random seed if unspecified") + +def pytest_collection_finish(session): + print('random seed: {}'.format(session.config.getoption("seed"))) + +@pytest.fixture +def num_steps(request): + return request.config.getoption("steps") + +@pytest.fixture +def rnd(request): + seed1 = request.config.getoption("seed") + return lambda seed2: random.Random('{}-{}'.format(seed1, seed2)) def pytest_generate_tests(metafunc): if "cell" in metafunc.fixturenames: - print(dir(metafunc.config)) per_cell = metafunc.config.getoption("per_cell", default=None) - names, cases = generate_test_cases(per_cell) + seed1 = metafunc.config.getoption("seed") + rnd = lambda seed2: random.Random('{}-{}'.format(seed1, seed2)) + names, cases = generate_test_cases(per_cell, rnd) metafunc.parametrize("cell,parameters", cases, ids=names) \ No newline at end of file diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index e96baa18e..b4c0ad1c1 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -1,30 +1,6 @@ from itertools import chain import random -widths = [ - (16, 32, 48, True), - (16, 32, 48, False), - (32, 16, 48, True), - (32, 16, 48, False), - (32, 32, 16, True), - (32, 32, 16, False) -] - -shift_widths = [ - (32, 6, 32, True, False), - (32, 6, 32, False, False), - (32, 6, 64, True, False), - (32, 6, 64, False, False), - (32, 32, 16, True, False), - (32, 32, 16, False, False), - (32, 6, 32, True, True), - (32, 6, 32, False, True), - (32, 6, 64, True, True), - (32, 6, 64, False, True), - (32, 32, 16, True, True), - (32, 32, 16, False, True), -] - def write_rtlil_cell(f, cell_type, inputs, outputs, parameters): f.write('autoidx 1\n') f.write('module \\gold\n') @@ -37,207 +13,260 @@ def write_rtlil_cell(f, cell_type, inputs, outputs, parameters): idx += 1 f.write(f'\tcell ${cell_type} \\UUT\n') for (name, value) in parameters.items(): - f.write(f'\t\tparameter \\{name} {value}\n') + if value >= 2**32: + f.write(f'\t\tparameter \\{name} {value.bit_length()}\'{value:b}\n') + else: + f.write(f'\t\tparameter \\{name} {value}\n') for name in chain(inputs.keys(), outputs.keys()): f.write(f'\t\tconnect \\{name} \\{name}\n') f.write(f'\tend\nend\n') class BaseCell: - def __init__(self, name): + def __init__(self, name, parameters, inputs, outputs, test_values): self.name = name + self.parameters = parameters + self.inputs = inputs + self.outputs = outputs + self.test_values = test_values + def get_port_width(self, port, parameters): + def parse_specifier(spec): + if isinstance(spec, int): + return spec + if isinstance(spec, str): + return parameters[spec] + if callable(spec): + return spec(parameters) + assert False, "expected int, str or lambda" + if port in self.inputs: + return parse_specifier(self.inputs[port]) + elif port in self.outputs: + return parse_specifier(self.outputs[port]) + else: + assert False, "expected input or output" + def generate_tests(self, rnd): + def print_parameter(v): + if isinstance(v, bool): + return "S" if v else "U" + else: + return str(v) + for values in self.test_values: + if isinstance(values, int): + values = [values] + name = '-'.join([print_parameter(v) for v in values]) + parameters = {parameter: int(values[i]) for i, parameter in enumerate(self.parameters)} + if self.is_test_valid(values): + yield (name, parameters) + def write_rtlil_file(self, path, parameters): + inputs = {port: self.get_port_width(port, parameters) for port in self.inputs} + outputs = {port: self.get_port_width(port, parameters) for port in self.outputs} + with open(path, 'w') as f: + write_rtlil_cell(f, self.name, inputs, outputs, parameters) + def is_test_valid(self, values): + return True class UnaryCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (a_width, _, y_width, signed) in widths: - yield (f'{a_width}-{y_width}-{'S' if signed else 'U'}', - {'A_WIDTH' : a_width, - 'A_SIGNED' : int(signed), - 'Y_WIDTH' : y_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + def __init__(self, name, values): + super().__init__(name, ['A_WIDTH', 'Y_WIDTH', 'A_SIGNED'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values) class BinaryCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (a_width, b_width, y_width, signed) in widths: - yield (f'{a_width}-{b_width}-{y_width}-{'S' if signed else 'U'}', - {'A_WIDTH' : a_width, - 'A_SIGNED' : int(signed), - 'B_WIDTH' : b_width, - 'B_SIGNED' : int(signed), - 'Y_WIDTH' : y_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + def __init__(self, name, values): + super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values) class ShiftCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (a_width, b_width, y_width, a_signed, b_signed) in shift_widths: - if not self.name in ('shift', 'shiftx') and b_signed: continue - if self.name == 'shiftx' and a_signed: continue - yield (f'{a_width}-{b_width}-{y_width}-{'S' if a_signed else 'U'}{'S' if b_signed else 'U'}', - {'A_WIDTH' : a_width, - 'A_SIGNED' : int(a_signed), - 'B_WIDTH' : b_width, - 'B_SIGNED' : int(b_signed), - 'Y_WIDTH' : y_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B': parameters['B_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + def __init__(self, name, values): + super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': 'Y_WIDTH'}, values) + def is_test_valid(self, values): + (a_width, b_width, y_width, a_signed, b_signed) = values + if not self.name in ('shift', 'shiftx') and b_signed: return False + if self.name == 'shiftx' and a_signed: return False + return True class MuxCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for width in [10, 20, 40]: - yield (f'{width}', {'WIDTH' : width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': parameters['WIDTH'], 'S': 1}, {'Y': parameters['WIDTH']}, parameters) + def __init__(self, name, values): + super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'S': 1}, {'Y': 'WIDTH'}, values) class BWCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for width in [10, 20, 40]: - yield (f'{width}', {'WIDTH' : width}) - def write_rtlil_file(self, f, parameters): - inputs = {'A': parameters['WIDTH'], 'B': parameters['WIDTH']} - if self.name == "bwmux": inputs['S'] = parameters['WIDTH'] - write_rtlil_cell(f, self.name, inputs, {'Y': parameters['WIDTH']}, parameters) + def __init__(self, name, values): + inputs = {'A': 'WIDTH', 'B': 'WIDTH'} + if name == "bwmux": inputs['S'] = 'WIDTH' + super().__init__(name, ['WIDTH'], inputs, {'Y': 'WIDTH'}, values) class PMuxCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (width, s_width) in [(10, 1), (10, 4), (20, 4)]: - yield (f'{width}-{s_width}', - {'WIDTH' : width, - 'S_WIDTH' : s_width}) - def write_rtlil_file(self, f, parameters): - s_width = parameters['S_WIDTH'] - b_width = parameters['WIDTH'] * s_width - write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'B': b_width, 'S': s_width}, {'Y': parameters['WIDTH']}, parameters) + def __init__(self, name, values): + b_width = lambda par: par['WIDTH'] * par['S_WIDTH'] + super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'B': b_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values) class BMuxCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (width, s_width) in [(10, 1), (10, 2), (10, 4)]: - yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'] << parameters['S_WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH']}, parameters) + def __init__(self, name, values): + a_width = lambda par: par['WIDTH'] << par['S_WIDTH'] + super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': a_width, 'S': 'S_WIDTH'}, {'Y': 'WIDTH'}, values) class DemuxCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (width, s_width) in [(10, 1), (32, 2), (16, 4)]: - yield (f'{width}-{s_width}', {'WIDTH' : width, 'S_WIDTH' : s_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['WIDTH'], 'S': parameters['S_WIDTH']}, {'Y': parameters['WIDTH'] << parameters['S_WIDTH']}, parameters) - -def seeded_randint(seed, a, b): - r = random.getstate() - random.seed(seed) - n = random.randint(a, b) - random.setstate(r) - return n + def __init__(self, name, values): + y_width = lambda par: par['WIDTH'] << par['S_WIDTH'] + super().__init__(name, ['WIDTH', 'S_WIDTH'], {'A': 'WIDTH', 'S': 'S_WIDTH'}, {'Y': y_width}, values) class LUTCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for width in [4, 6, 8]: - lut = seeded_randint(width, 0, 2**width - 1) + def __init__(self, name, values): + super().__init__(name, ['WIDTH', 'LUT'], {'A': 'WIDTH'}, {'Y': 1}, values) + def generate_tests(self, rnd): + for width in self.test_values: + lut = rnd(f'lut-{width}').getrandbits(2**width) yield (f'{width}', {'WIDTH' : width, 'LUT' : lut}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['WIDTH']}, {'Y': 1}, parameters) class ConcatCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (a_width, b_width) in [(16, 16), (8, 14), (20, 10)]: - yield (f'{a_width}-{b_width}', {'A_WIDTH' : a_width, 'B_WIDTH' : b_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH'], 'B' : parameters['B_WIDTH']}, {'Y': parameters['A_WIDTH'] + parameters['B_WIDTH']}, parameters) + def __init__(self, name, values): + y_width = lambda par: par['A_WIDTH'] + par['B_WIDTH'] + super().__init__(name, ['A_WIDTH', 'B_WIDTH'], {'A': 'A_WIDTH', 'B': 'B_WIDTH'}, {'Y': y_width}, values) class SliceCell(BaseCell): - def __init__(self, name): - super().__init__(name) - def generate_tests(self): - for (a_width, offset, y_width) in [(32, 10, 15), (8, 0, 4), (10, 0, 10)]: - yield (f'{a_width}-{offset}-{y_width}', {'A_WIDTH' : a_width, 'OFFSET' : offset, 'Y_WIDTH': y_width}) - def write_rtlil_file(self, f, parameters): - write_rtlil_cell(f, self.name, {'A': parameters['A_WIDTH']}, {'Y': parameters['Y_WIDTH']}, parameters) + def __init__(self, name, values): + super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values) class FailCell(BaseCell): def __init__(self, name): - super().__init__(name) - def generate_tests(self): + super().__init__(name, [], {}, {}) + def generate_tests(self, rnd): yield ('', {}) - def write_rtlil_file(self, f, parameters): + def write_rtlil_file(self, path, parameters): raise Exception(f'\'{self.name}\' cell unimplemented in test generator') +class FFCell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['WIDTH'], ['D'], ['Q'], values) + def write_rtlil_file(self, path, parameters): + from test_functional import yosys_synth + verilog_file = path.parent / 'verilog.v' + with open(verilog_file, 'w') as f: + f.write(""" +module gold( + input wire clk, + input wire [{0}:0] D, + output reg [{0}:0] Q +); + always @(posedge clk) + Q <= D; +endmodule""".format(parameters['WIDTH'] - 1)) + yosys_synth(verilog_file, path) + +class MemCell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'], {'WA': 'ADDR_WIDTH', 'RA': 'ADDR_WIDTH', 'WD': 'DATA_WIDTH'}, {'RD': 'DATA_WIDTH'}, values) + def write_rtlil_file(self, path, parameters): + from test_functional import yosys_synth + verilog_file = path.parent / 'verilog.v' + with open(verilog_file, 'w') as f: + f.write(""" +module gold( + input wire clk, + input wire [{1}:0] WA, + input wire [{0}:0] WD, + output reg [{0}:0] RD +); + reg [{0}:0] mem[0:{1}]; + always @(*) + RD = mem[RA]; + always @(posedge clk) + mem[WA] <= WD; +endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1)) + yosys_synth(verilog_file, path) + +binary_widths = [ + # try to cover extending A operand, extending B operand, extending/truncating result + (16, 32, 48, True, True), + (16, 32, 48, False, False), + (32, 16, 48, True, True), + (32, 16, 48, False, False), + (32, 32, 16, True, True), + (32, 32, 16, False, False), + # have at least one test that checks small inputs, which will exercise the cornercases more + (4, 4, 8, True, True), + (4, 4, 8, False, False) +] + +unary_widths = [ + (6, 12, True), + (6, 12, False), + (32, 16, True), + (32, 16, False) +] + +# note that meaningless combinations of signednesses are eliminated, +# like e.g. most shift operations don't take signed shift amounts +shift_widths = [ + # one set of tests that definitely checks all possible shift amounts + # with a bigger result width to make sure it's not truncated + (32, 6, 64, True, False), + (32, 6, 64, False, False), + (32, 6, 64, True, True), + (32, 6, 64, False, True), + # one set that checks very oversized shifts + (32, 32, 64, True, False), + (32, 32, 64, False, False), + (32, 32, 64, True, True), + (32, 32, 64, False, True), + # at least one test where the result is going to be truncated + (32, 6, 16, False, False) +] + rtlil_cells = [ - UnaryCell("not"), - UnaryCell("pos"), - UnaryCell("neg"), - BinaryCell("and"), - BinaryCell("or"), - BinaryCell("xor"), - BinaryCell("xnor"), - UnaryCell("reduce_and"), - UnaryCell("reduce_or"), - UnaryCell("reduce_xor"), - UnaryCell("reduce_xnor"), - UnaryCell("reduce_bool"), - ShiftCell("shl"), - ShiftCell("shr"), - ShiftCell("sshl"), - ShiftCell("sshr"), - ShiftCell("shift"), - ShiftCell("shiftx"), + UnaryCell("not", unary_widths), + UnaryCell("pos", unary_widths), + UnaryCell("neg", unary_widths), + BinaryCell("and", binary_widths), + BinaryCell("or", binary_widths), + BinaryCell("xor", binary_widths), + BinaryCell("xnor", binary_widths), + UnaryCell("reduce_and", unary_widths), + UnaryCell("reduce_or", unary_widths), + UnaryCell("reduce_xor", unary_widths), + UnaryCell("reduce_xnor", unary_widths), + UnaryCell("reduce_bool", unary_widths), + ShiftCell("shl", shift_widths), + ShiftCell("shr", shift_widths), + ShiftCell("sshl", shift_widths), + ShiftCell("sshr", shift_widths), + ShiftCell("shift", shift_widths), + ShiftCell("shiftx", shift_widths), # ("fa", ["A", "B", "C", "X", "Y"]), # ("lcu", ["P", "G", "CI", "CO"]), # ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]), - BinaryCell("lt"), - BinaryCell("le"), - BinaryCell("eq"), - BinaryCell("ne"), - BinaryCell("eqx"), - BinaryCell("nex"), - BinaryCell("ge"), - BinaryCell("gt"), - BinaryCell("add"), - BinaryCell("sub"), - BinaryCell("mul"), + BinaryCell("lt", binary_widths), + BinaryCell("le", binary_widths), + BinaryCell("eq", binary_widths), + BinaryCell("ne", binary_widths), + BinaryCell("eqx", binary_widths), + BinaryCell("nex", binary_widths), + BinaryCell("ge", binary_widths), + BinaryCell("gt", binary_widths), + BinaryCell("add", binary_widths), + BinaryCell("sub", binary_widths), + BinaryCell("mul", binary_widths), # BinaryCell("macc"), - BinaryCell("div"), - BinaryCell("mod"), - BinaryCell("divfloor"), - BinaryCell("modfloor"), - BinaryCell("pow"), - UnaryCell("logic_not"), - BinaryCell("logic_and"), - BinaryCell("logic_or"), - SliceCell("slice"), - ConcatCell("concat"), - MuxCell("mux"), - BMuxCell("bmux"), - PMuxCell("pmux"), - DemuxCell("demux"), - LUTCell("lut"), + BinaryCell("div", binary_widths), + BinaryCell("mod", binary_widths), + BinaryCell("divfloor", binary_widths), + BinaryCell("modfloor", binary_widths), + BinaryCell("pow", binary_widths), + UnaryCell("logic_not", unary_widths), + BinaryCell("logic_and", binary_widths), + BinaryCell("logic_or", binary_widths), + SliceCell("slice", [(32, 10, 15), (8, 0, 4), (10, 0, 10)]), + ConcatCell("concat", [(16, 16), (8, 14), (20, 10)]), + MuxCell("mux", [10, 16, 40]), + BMuxCell("bmux", [(10, 1), (10, 2), (10, 4)]), + PMuxCell("pmux", [(10, 1), (10, 4), (20, 4)]), + DemuxCell("demux", [(10, 1), (32, 2), (16, 4)]), + LUTCell("lut", [4, 6, 8]), # ("sop", ["A", "Y"]), # ("tribuf", ["A", "EN", "Y"]), # ("specify2", ["EN", "SRC", "DST"]), # ("specify3", ["EN", "SRC", "DST", "DAT"]), # ("specrule", ["EN_SRC", "EN_DST", "SRC", "DST"]), - BWCell("bweqx"), - BWCell("bwmux"), + BWCell("bweqx", [10, 16, 40]), + BWCell("bwmux", [10, 16, 40]), + FFCell("ff", [10, 20, 40]), + MemCell("mem", [(32, 4)]) # ("assert", ["A", "EN"]), # ("assume", ["A", "EN"]), # ("live", ["A", "EN"]), @@ -260,12 +289,12 @@ rtlil_cells = [ # ("scopeinfo", []), ] -def generate_test_cases(per_cell): +def generate_test_cases(per_cell, rnd): tests = [] names = [] for cell in rtlil_cells: seen_names = set() - for (name, parameters) in cell.generate_tests(): + for (name, parameters) in cell.generate_tests(rnd): if not name in seen_names: seen_names.add(name) tests.append((cell, parameters)) diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index c38fe1bde..37d2a209f 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -1,6 +1,5 @@ import sys import argparse -import random import os import smtio import re @@ -40,9 +39,10 @@ class SExprParser: rv, self.stack[0] = self.stack[0], [] return rv -def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io): +def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): inputs = {} outputs = {} + states = {} def handle_datatype(lst): print(lst) @@ -60,6 +60,14 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io): bitvec_size = declaration[1][2] assert output_name.startswith("gold_Outputs_") outputs[output_name[len("gold_Outputs_"):]] = int(bitvec_size) + elif datatype_name.endswith("_State"): + for declaration in declarations: + state_name = declaration[0] + assert state_name.startswith("gold_State_") + if declaration[1][0] == "_": + states[state_name[len("gold_State_"):]] = int(declaration[1][2]) + else: + states[state_name[len("gold_State_"):]] = (declaration[1][1][2], declaration[1][2][2]) parser = SExprParser() with open(smt_file_path, 'r') as smt_file: @@ -73,25 +81,44 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io): parser.finish() assert smt_io.check_sat() == 'sat' + def initial_state(states): + mk_state_parts = [] + rv = [] + for name, width in states.items(): + if isinstance(width, int): + binary_string = format(0, '0{}b'.format(width)) + mk_state_parts.append(f"#b{binary_string}") + else: + binary_string = format(0, '0{}b'.format(width[1])) + rv.append(f"(declare-const test_state_initial_mem_{name} (Array (_ BitVec {width[0]}) (_ BitVec {width[1]})))") + rv.append(f"(assert (forall ((i (_ BitVec {width[0]}))) (= (select test_state_initial_mem_{name} i) #b{binary_string})))") + mk_state_parts.append(f"test_state_initial_mem_{name}") + if len(states) == 0: + mk_state_call = "gold_State" + else: + mk_state_call = "(gold_State {})".format(" ".join(mk_state_parts)) + rv.append(f"(define-const test_state_step_n0 gold_State {mk_state_call})\n") + return rv + def set_step(inputs, step): # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. mk_inputs_parts = [] for input_name, width in inputs.items(): - value = random.getrandbits(width) # Generate a random number up to the maximum value for the bit size + value = rnd.getrandbits(width) # Generate a random number up to the maximum value for the bit size binary_string = format(value, '0{}b'.format(width)) # Convert value to binary with leading zeros mk_inputs_parts.append(f"#b{binary_string}") mk_inputs_call = "gold_Inputs " + " ".join(mk_inputs_parts) - define_inputs = f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n" + return [ + f"(define-const test_inputs_step_n{step} gold_Inputs ({mk_inputs_call}))\n", + f"(define-const test_results_step_n{step} (Pair gold_Outputs gold_State) (gold test_inputs_step_n{step} test_state_step_n{step}))\n", + f"(define-const test_outputs_step_n{step} gold_Outputs (first test_results_step_n{step}))\n", + f"(define-const test_state_step_n{step+1} gold_State (second test_results_step_n{step}))\n", + ] - define_outputs = f"(define-const test_outputs_step_n{step} gold_Outputs (first (gold test_inputs_step_n{step} gold_State)))\n" - smt_commands = [define_inputs, define_outputs] - return smt_commands - - num_steps = 1000 - smt_commands = [] + smt_commands = initial_state(states) for step in range(num_steps): for step_command in set_step(inputs, step): smt_commands.append(step_command) @@ -168,13 +195,13 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io): write_vcd(vcd_path, signals) -def simulate_smt(smt_file_path, vcd_path): +def simulate_smt(smt_file_path, vcd_path, num_steps, rnd): so = smtio.SmtOpts() so.solver = "z3" - so.logic = "BV" + so.logic = "ABV" so.debug_print = True smt_io = smtio.SmtIo(opts=so) try: - simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io) + simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd) finally: smt_io.p_close() \ No newline at end of file diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 9b4fab970..86e515d90 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -6,11 +6,14 @@ from pathlib import Path base_path = Path(__file__).resolve().parent.parent.parent +# quote a string or pathlib path so that it can be used by bash or yosys +# TODO: is this really appropriate for yosys? def quote(path): return shlex.quote(str(path)) +# run a shell command and require the return code to be 0 def run(cmd, **kwargs): - print(' '.join([shlex.quote(str(x)) for x in cmd])) + print(' '.join([quote(x) for x in cmd])) status = subprocess.run(cmd, **kwargs) assert status.returncode == 0, f"{cmd[0]} failed" @@ -20,7 +23,24 @@ def yosys(script): def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) -def test_cxx(cell, parameters, tmp_path): +def yosys_synth(verilog_file, rtlil_file): + yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}") + +# simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file +def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file): + try: + yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold") + except: + # if yosys sim fails it's probably because of a simulation mismatch + # since yosys sim aborts on simulation mismatch to generate vcd output + # we have to re-run with a different set of flags + # on this run we ignore output and return code, we just want a best-effort attempt to get a vcd + subprocess.run([base_path / 'yosys', '-Q', '-p', + f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us'], + capture_output=True, check=False) + raise + +def test_cxx(cell, parameters, tmp_path, num_steps, rnd): rtlil_file = tmp_path / 'rtlil.il' vcdharness_cc_file = base_path / 'tests/functional/vcd_harness.cc' cc_file = tmp_path / 'my_module_functional_cxx.cc' @@ -28,20 +48,14 @@ def test_cxx(cell, parameters, tmp_path): vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' - with open(rtlil_file, 'w') as f: - cell.write_rtlil_file(f, parameters) + cell.write_rtlil_file(rtlil_file, parameters) yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}") compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')]) - run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file)]) - try: - yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold") - except: - subprocess.run([base_path / 'yosys', '-Q', '-p', - f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'], - capture_output=True, check=False) - raise + seed = str(rnd(cell.name + "-cxx").getrandbits(32)) + run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)]) + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file) -def test_smt(cell, parameters, tmp_path): +def test_smt(cell, parameters, tmp_path, num_steps, rnd): import smt_vcd rtlil_file = tmp_path / 'rtlil.il' @@ -49,15 +63,8 @@ def test_smt(cell, parameters, tmp_path): vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' - with open(rtlil_file, 'w') as f: - cell.write_rtlil_file(f, parameters) + cell.write_rtlil_file(rtlil_file, parameters) yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}") - run(['z3', smt_file]) - smt_vcd.simulate_smt(smt_file, vcd_functional_file) - try: - yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_functional_file)} -scope gold -vcd {quote(vcd_yosys_sim_file)} -timescale 1us -sim-gold") - except: - subprocess.run([base_path / 'yosys', '-Q', '-p', - f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_yosys_sim_file)} -r {quote(vcd_functional_file)} -scope gold -timescale 1us'], - capture_output=True, check=False) - raise \ No newline at end of file + run(['z3', smt_file]) # check if output is valid smtlib before continuing + smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file) \ No newline at end of file diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc index f99d2909b..f01adf218 100644 --- a/tests/functional/vcd_harness.cc +++ b/tests/functional/vcd_harness.cc @@ -2,15 +2,46 @@ #include #include #include +#include +#include #include "my_module_functional_cxx.cc" +std::string vcd_name_mangle(std::string name) { + std::string ret = name; + bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_'; + for(size_t i = 0; i < ret.size(); i++) { + if(isspace(ret[i])) ret[i] = '_'; + if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$') + escape = true; + } + if(escape) + return "\\" + ret; + else + return ret; +} +std::unordered_map codes; + struct DumpHeader { std::ofstream &ofs; + std::string code = "!"; DumpHeader(std::ofstream &ofs) : ofs(ofs) {} + void increment_code() { + for(size_t i = 0; i < code.size(); i++) + if(code[i]++ == '~') + code[i] = '!'; + else + return; + code.push_back('!'); + } template void operator()(const char *name, Signal value) { - ofs << "$var wire " << n << " " << name[0] << " " << name << " $end\n"; + ofs << "$var wire " << n << " " << code << " " << vcd_name_mangle(name) << " $end\n"; + codes[name] = code; + increment_code(); + } + template + void operator()(const char *name, Memory value) { } }; @@ -22,14 +53,17 @@ struct Dump { // Bit if (n == 1) { ofs << (value[0] ? '1' : '0'); - ofs << name[0] << "\n"; + ofs << codes[name] << "\n"; return; } // vector (multi-bit) signals ofs << "b"; for (size_t i = n; i-- > 0;) ofs << (value[i] ? '1' : '0'); - ofs << " " << name[0] << "\n"; + ofs << " " << codes[name] << "\n"; + } + template + void operator()(const char *name, Memory value) { } }; @@ -61,14 +95,15 @@ struct Randomize { int main(int argc, char **argv) { - if (argc != 2) { - std::cerr << "Usage: " << argv[0] << " \n"; + if (argc != 4) { + std::cerr << "Usage: " << argv[0] << " \n"; return 1; } const std::string functional_vcd_filename = argv[1]; + const int steps = atoi(argv[2]); + const uint32_t seed = atoi(argv[3]); - constexpr int steps = 1000; constexpr int number_timescale = 1; const std::string units_timescale = "us"; gold::Inputs inputs; @@ -87,27 +122,12 @@ int main(int argc, char **argv) state.visit(d); } vcd_file << "$enddefinitions $end\n$dumpvars\n"; - vcd_file << "#0\n"; - // Set all signals to false + std::mt19937 gen(seed); + inputs.visit(Reset()); - gold::eval(inputs, outputs, state, next_state); - { - Dump d(vcd_file); - inputs.visit(d); - outputs.visit(d); - state.visit(d); - } - - // Initialize random number generator once - std::random_device rd; - std::mt19937 gen(rd()); - for (int step = 0; step < steps; ++step) { - // Functional backend cxx - vcd_file << "#" << (step + 1) << "\n"; - inputs.visit(Randomize(gen)); - + vcd_file << "#" << step << "\n"; gold::eval(inputs, outputs, state, next_state); { Dump d(vcd_file); @@ -117,6 +137,7 @@ int main(int argc, char **argv) } state = next_state; + inputs.visit(Randomize(gen)); } vcd_file.close(); From 55c2c1785332ce862528ae06c60e551f7e5316a5 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 17 Jul 2024 11:53:42 +0100 Subject: [PATCH 136/342] document functionalir.h and change visitors to derive from AbstractVisitor. remove extraneous widths arguments from visitors. --- backends/functional/cxx.cc | 72 ++++---- backends/functional/smtlib.cc | 72 ++++---- kernel/functional.h | 2 +- kernel/functionalir.cc | 93 +++++++++- kernel/functionalir.h | 331 +++++++++++++++++++++++++--------- 5 files changed, 400 insertions(+), 170 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 4ab9d53a1..920ccf363 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -98,7 +98,7 @@ struct CxxStruct { } }; -template struct CxxPrintVisitor { +template struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor { using Node = FunctionalIR::Node; CxxWriter &f; NodePrinter np; @@ -108,36 +108,36 @@ template struct CxxPrintVisitor { template void print(const char *fmt, Args&&... args) { f.print_with(np, fmt, std::forward(args)...); } - void buf(Node, Node n) { print("{}", n); } - void slice(Node, Node a, int, int offset, int out_width) { print("{0}.slice<{2}>({1})", a, offset, out_width); } - void zero_extend(Node, Node a, int, int out_width) { print("{}.zero_extend<{}>()", a, out_width); } - void sign_extend(Node, Node a, int, int out_width) { print("{}.sign_extend<{}>()", a, out_width); } - void concat(Node, Node a, int, Node b, int) { print("{}.concat({})", a, b); } - void add(Node, Node a, Node b, int) { print("{} + {}", a, b); } - void sub(Node, Node a, Node b, int) { print("{} - {}", a, b); } - void mul(Node, Node a, Node b, int) { print("{} * {}", a, b); } - void unsigned_div(Node, Node a, Node b, int) { print("{} / {}", a, b); } - void unsigned_mod(Node, Node a, Node b, int) { print("{} % {}", a, b); } - void bitwise_and(Node, Node a, Node b, int) { print("{} & {}", a, b); } - void bitwise_or(Node, Node a, Node b, int) { print("{} | {}", a, b); } - void bitwise_xor(Node, Node a, Node b, int) { print("{} ^ {}", a, b); } - void bitwise_not(Node, Node a, int) { print("~{}", a); } - void unary_minus(Node, Node a, int) { print("-{}", a); } - void reduce_and(Node, Node a, int) { print("{}.all()", a); } - void reduce_or(Node, Node a, int) { print("{}.any()", a); } - void reduce_xor(Node, Node a, int) { print("{}.parity()", a); } - void equal(Node, Node a, Node b, int) { print("{} == {}", a, b); } - void not_equal(Node, Node a, Node b, int) { print("{} != {}", a, b); } - void signed_greater_than(Node, Node a, Node b, int) { print("{}.signed_greater_than({})", a, b); } - void signed_greater_equal(Node, Node a, Node b, int) { print("{}.signed_greater_equal({})", a, b); } - void unsigned_greater_than(Node, Node a, Node b, int) { print("{} > {}", a, b); } - void unsigned_greater_equal(Node, Node a, Node b, int) { print("{} >= {}", a, b); } - void logical_shift_left(Node, Node a, Node b, int, int) { print("{} << {}", a, b); } - void logical_shift_right(Node, Node a, Node b, int, int) { print("{} >> {}", a, b); } - void arithmetic_shift_right(Node, Node a, Node b, int, int) { print("{}.arithmetic_shift_right({})", a, b); } - void mux(Node, Node a, Node b, Node s, int) { print("{2}.any() ? {1} : {0}", a, b, s); } - void pmux(Node, Node a, Node b, Node s, int, int) { print("{0}.pmux({1}, {2})", a, b, s); } - void constant(Node, RTLIL::Const value) { + void buf(Node, Node n) override { print("{}", n); } + void slice(Node, Node a, int offset, int out_width) override { print("{0}.slice<{2}>({1})", a, offset, out_width); } + void zero_extend(Node, Node a, int out_width) override { print("{}.zero_extend<{}>()", a, out_width); } + void sign_extend(Node, Node a, int out_width) override { print("{}.sign_extend<{}>()", a, out_width); } + void concat(Node, Node a, Node b) override { print("{}.concat({})", a, b); } + void add(Node, Node a, Node b) override { print("{} + {}", a, b); } + void sub(Node, Node a, Node b) override { print("{} - {}", a, b); } + void mul(Node, Node a, Node b) override { print("{} * {}", a, b); } + void unsigned_div(Node, Node a, Node b) override { print("{} / {}", a, b); } + void unsigned_mod(Node, Node a, Node b) override { print("{} % {}", a, b); } + void bitwise_and(Node, Node a, Node b) override { print("{} & {}", a, b); } + void bitwise_or(Node, Node a, Node b) override { print("{} | {}", a, b); } + void bitwise_xor(Node, Node a, Node b) override { print("{} ^ {}", a, b); } + void bitwise_not(Node, Node a) override { print("~{}", a); } + void unary_minus(Node, Node a) override { print("-{}", a); } + void reduce_and(Node, Node a) override { print("{}.all()", a); } + void reduce_or(Node, Node a) override { print("{}.any()", a); } + void reduce_xor(Node, Node a) override { print("{}.parity()", a); } + void equal(Node, Node a, Node b) override { print("{} == {}", a, b); } + void not_equal(Node, Node a, Node b) override { print("{} != {}", a, b); } + void signed_greater_than(Node, Node a, Node b) override { print("{}.signed_greater_than({})", a, b); } + void signed_greater_equal(Node, Node a, Node b) override { print("{}.signed_greater_equal({})", a, b); } + void unsigned_greater_than(Node, Node a, Node b) override { print("{} > {}", a, b); } + void unsigned_greater_equal(Node, Node a, Node b) override { print("{} >= {}", a, b); } + void logical_shift_left(Node, Node a, Node b) override { print("{} << {}", a, b); } + void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); } + void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); } + void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); } + void pmux(Node, Node a, Node b, Node s) override { print("{0}.pmux({1}, {2})", a, b, s); } + void constant(Node, RTLIL::Const value) override { std::stringstream ss; bool multiple = value.size() > 32; ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase; @@ -151,11 +151,11 @@ template struct CxxPrintVisitor { ss << ")"; print("{}", ss.str()); } - void input(Node, IdString name) { print("input.{}", input_struct[name]); } - void state(Node, IdString name) { print("current_state.{}", state_struct[name]); } - void memory_read(Node, Node mem, Node addr, int, int) { print("{}.read({})", mem, addr); } - void memory_write(Node, Node mem, Node addr, Node data, int, int) { print("{}.write({}, {})", mem, addr, data); } - void undriven(Node, int width) { print("Signal<{}>(0)", width); } + void input(Node, IdString name) override { print("input.{}", input_struct[name]); } + void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); } + void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); } + void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); } + void undriven(Node, int width) override { print("Signal<{}>(0)", width); } }; struct CxxModule { diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 113fb7100..c35a48dd8 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -109,7 +109,7 @@ public: } }; -struct SmtPrintVisitor { +struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { using Node = FunctionalIR::Node; std::function n; SmtStruct &input_struct; @@ -134,35 +134,35 @@ struct SmtPrintVisitor { return list(list("_", "extract", offset + out_width - 1, offset), std::move(arg)); } - SExpr buf(Node, Node a) { return n(a); } - SExpr slice(Node, Node a, int, int offset, int out_width) { return extract(n(a), offset, out_width); } - SExpr zero_extend(Node, Node a, int, int out_width) { return list(list("_", "zero_extend", out_width - a.width()), n(a)); } - SExpr sign_extend(Node, Node a, int, int out_width) { return list(list("_", "sign_extend", out_width - a.width()), n(a)); } - SExpr concat(Node, Node a, int, Node b, int) { return list("concat", n(b), n(a)); } - SExpr add(Node, Node a, Node b, int) { return list("bvadd", n(a), n(b)); } - SExpr sub(Node, Node a, Node b, int) { return list("bvsub", n(a), n(b)); } - SExpr mul(Node, Node a, Node b, int) { return list("bvmul", n(a), n(b)); } - SExpr unsigned_div(Node, Node a, Node b, int) { return list("bvudiv", n(a), n(b)); } - SExpr unsigned_mod(Node, Node a, Node b, int) { return list("bvurem", n(a), n(b)); } - SExpr bitwise_and(Node, Node a, Node b, int) { return list("bvand", n(a), n(b)); } - SExpr bitwise_or(Node, Node a, Node b, int) { return list("bvor", n(a), n(b)); } - SExpr bitwise_xor(Node, Node a, Node b, int) { return list("bvxor", n(a), n(b)); } - SExpr bitwise_not(Node, Node a, int) { return list("bvnot", n(a)); } - SExpr unary_minus(Node, Node a, int) { return list("bvneg", n(a)); } - SExpr reduce_and(Node, Node a, int) { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); } - SExpr reduce_or(Node, Node a, int) { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); } - SExpr reduce_xor(Node, Node a, int) { + SExpr buf(Node, Node a) override { return n(a); } + SExpr slice(Node, Node a, int offset, int out_width) override { return extract(n(a), offset, out_width); } + SExpr zero_extend(Node, Node a, int out_width) override { return list(list("_", "zero_extend", out_width - a.width()), n(a)); } + SExpr sign_extend(Node, Node a, int out_width) override { return list(list("_", "sign_extend", out_width - a.width()), n(a)); } + SExpr concat(Node, Node a, Node b) override { return list("concat", n(b), n(a)); } + SExpr add(Node, Node a, Node b) override { return list("bvadd", n(a), n(b)); } + SExpr sub(Node, Node a, Node b) override { return list("bvsub", n(a), n(b)); } + SExpr mul(Node, Node a, Node b) override { return list("bvmul", n(a), n(b)); } + SExpr unsigned_div(Node, Node a, Node b) override { return list("bvudiv", n(a), n(b)); } + SExpr unsigned_mod(Node, Node a, Node b) override { return list("bvurem", n(a), n(b)); } + SExpr bitwise_and(Node, Node a, Node b) override { return list("bvand", n(a), n(b)); } + SExpr bitwise_or(Node, Node a, Node b) override { return list("bvor", n(a), n(b)); } + SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); } + SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); } + SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); } + SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); } + SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); } + SExpr reduce_xor(Node, Node a) override { vector s { "bvxor" }; for(int i = 0; i < a.width(); i++) s.push_back(extract(n(a), i)); return s; } - SExpr equal(Node, Node a, Node b, int) { return from_bool(list("=", n(a), n(b))); } - SExpr not_equal(Node, Node a, Node b, int) { return from_bool(list("distinct", n(a), n(b))); } - SExpr signed_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvsgt", n(a), n(b))); } - SExpr signed_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvsge", n(a), n(b))); } - SExpr unsigned_greater_than(Node, Node a, Node b, int) { return from_bool(list("bvugt", n(a), n(b))); } - SExpr unsigned_greater_equal(Node, Node a, Node b, int) { return from_bool(list("bvuge", n(a), n(b))); } + SExpr equal(Node, Node a, Node b) override { return from_bool(list("=", n(a), n(b))); } + SExpr not_equal(Node, Node a, Node b) override { return from_bool(list("distinct", n(a), n(b))); } + SExpr signed_greater_than(Node, Node a, Node b) override { return from_bool(list("bvsgt", n(a), n(b))); } + SExpr signed_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvsge", n(a), n(b))); } + SExpr unsigned_greater_than(Node, Node a, Node b) override { return from_bool(list("bvugt", n(a), n(b))); } + SExpr unsigned_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvuge", n(a), n(b))); } SExpr extend(SExpr &&a, int in_width, int out_width) { if(in_width < out_width) @@ -170,24 +170,24 @@ struct SmtPrintVisitor { else return std::move(a); } - SExpr logical_shift_left(Node, Node a, Node b, int, int) { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); } - SExpr logical_shift_right(Node, Node a, Node b, int, int) { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } - SExpr arithmetic_shift_right(Node, Node a, Node b, int, int) { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } - SExpr mux(Node, Node a, Node b, Node s, int) { return list("ite", to_bool(n(s)), n(b), n(a)); } - SExpr pmux(Node, Node a, Node b, Node s, int, int) { + SExpr logical_shift_left(Node, Node a, Node b) override { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); } + SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } + SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } + SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); } + SExpr pmux(Node, Node a, Node b, Node s) override { SExpr rv = n(a); for(int i = 0; i < s.width(); i++) rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv); return rv; } - SExpr constant(Node, RTLIL::Const value) { return literal(value); } - SExpr memory_read(Node, Node mem, Node addr, int, int) { return list("select", n(mem), n(addr)); } - SExpr memory_write(Node, Node mem, Node addr, Node data, int, int) { return list("store", n(mem), n(addr), n(data)); } + SExpr constant(Node, RTLIL::Const value) override { return literal(value); } + SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); } + SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); } - SExpr input(Node, IdString name) { return input_struct.access("inputs", name); } - SExpr state(Node, IdString name) { return state_struct.access("state", name); } + SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); } + SExpr state(Node, IdString name) override { return state_struct.access("state", name); } - SExpr undriven(Node, int width) { return literal(RTLIL::Const(State::S0, width)); } + SExpr undriven(Node, int width) override { return literal(RTLIL::Const(State::S0, width)); } }; struct SmtModule { diff --git a/kernel/functional.h b/kernel/functional.h index 09a882643..09f66c981 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -109,7 +109,7 @@ public: { auto found = graph_->sparse_attrs.find(index_); log_assert(found != graph_->sparse_attrs.end()); - return *found; + return found->second; } }; diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index b8fa6b88e..9b8076a0e 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -21,6 +21,83 @@ YOSYS_NAMESPACE_BEGIN +const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) { + switch(fn) { + case FunctionalIR::Fn::invalid: return "invalid"; + case FunctionalIR::Fn::buf: return "buf"; + case FunctionalIR::Fn::slice: return "slice"; + case FunctionalIR::Fn::zero_extend: return "zero_extend"; + case FunctionalIR::Fn::sign_extend: return "sign_extend"; + case FunctionalIR::Fn::concat: return "concat"; + case FunctionalIR::Fn::add: return "add"; + case FunctionalIR::Fn::sub: return "sub"; + case FunctionalIR::Fn::mul: return "mul"; + case FunctionalIR::Fn::unsigned_div: return "unsigned_div"; + case FunctionalIR::Fn::unsigned_mod: return "unsigned_mod"; + case FunctionalIR::Fn::bitwise_and: return "bitwise_and"; + case FunctionalIR::Fn::bitwise_or: return "bitwise_or"; + case FunctionalIR::Fn::bitwise_xor: return "bitwise_xor"; + case FunctionalIR::Fn::bitwise_not: return "bitwise_not"; + case FunctionalIR::Fn::reduce_and: return "reduce_and"; + case FunctionalIR::Fn::reduce_or: return "reduce_or"; + case FunctionalIR::Fn::reduce_xor: return "reduce_xor"; + case FunctionalIR::Fn::unary_minus: return "unary_minus"; + case FunctionalIR::Fn::equal: return "equal"; + case FunctionalIR::Fn::not_equal: return "not_equal"; + case FunctionalIR::Fn::signed_greater_than: return "signed_greater_than"; + case FunctionalIR::Fn::signed_greater_equal: return "signed_greater_equal"; + case FunctionalIR::Fn::unsigned_greater_than: return "unsigned_greater_than"; + case FunctionalIR::Fn::unsigned_greater_equal: return "unsigned_greater_equal"; + case FunctionalIR::Fn::logical_shift_left: return "logical_shift_left"; + case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right"; + case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right"; + case FunctionalIR::Fn::mux: return "mux"; + case FunctionalIR::Fn::pmux: return "pmux"; + case FunctionalIR::Fn::constant: return "constant"; + case FunctionalIR::Fn::input: return "input"; + case FunctionalIR::Fn::state: return "state"; + case FunctionalIR::Fn::multiple: return "multiple"; + case FunctionalIR::Fn::undriven: return "undriven"; + case FunctionalIR::Fn::memory_read: return "memory_read"; + case FunctionalIR::Fn::memory_write: return "memory_write"; + } + log_error("fn_to_string: unknown FunctionalIR::Fn value %d", (int)fn); +} + +struct PrintVisitor : FunctionalIR::DefaultVisitor { + using Node = FunctionalIR::Node; + std::function np; + PrintVisitor(std::function np) : np(np) { } + // as a general rule the default handler is good enough iff the only arguments are of type Node + std::string slice(Node, Node a, int offset, int out_width) override { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; } + std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } + std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } + std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; } + std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; } + std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; } + std::string undriven(Node, int width) override { return "undriven(" + std::to_string(width) + ")"; } + std::string default_handler(Node self) override { + std::string ret = FunctionalIR::fn_to_string(self.fn()); + ret += "("; + for(size_t i = 0; i < self.arg_count(); i++) { + if(i > 0) ret += ", "; + ret += np(self.arg(i)); + } + ret += ")"; + return ret; + } +}; + +std::string FunctionalIR::Node::to_string() +{ + return to_string([](Node n) { return RTLIL::unescape_id(n.name()); }); +} + +std::string FunctionalIR::Node::to_string(std::function np) +{ + return visit(PrintVisitor(np)); +} + template class CellSimplifier { Factory &factory; @@ -47,11 +124,6 @@ class CellSimplifier { return neg_if(a, a_width, sign(a, a_width)); } public: - T reduce_or(T a, int width) { - if (width == 1) - return a; - return factory.reduce_or(a, width); - } T extend(T a, int in_width, int out_width, bool is_signed) { if(in_width == out_width) return a; @@ -153,8 +225,8 @@ public: else log_abort(); }else if(cellType.in({ID($logic_or), ID($logic_and)})){ - T a = reduce_or(inputs.at(ID(A)), a_width); - T b = reduce_or(inputs.at(ID(B)), b_width); + T a = factory.reduce_or(inputs.at(ID(A)), a_width); + T b = factory.reduce_or(inputs.at(ID(B)), b_width); T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1); return extend(y, 1, y_width, false); }else if(cellType == ID($not)){ @@ -166,11 +238,11 @@ public: T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); return factory.unary_minus(a, y_width); }else if(cellType == ID($logic_not)){ - T a = reduce_or(inputs.at(ID(A)), a_width); + T a = factory.reduce_or(inputs.at(ID(A)), a_width); T y = factory.bitwise_not(a, 1); return extend(y, 1, y_width, false); }else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){ - T a = reduce_or(inputs.at(ID(A)), a_width); + T a = factory.reduce_or(inputs.at(ID(A)), a_width); return extend(a, 1, y_width, false); }else if(cellType == ID($reduce_and)){ T a = factory.reduce_and(inputs.at(ID(A)), a_width); @@ -244,7 +316,7 @@ public: // which equals the negative of (-a) / b with rounding up rather than down // note that to handle the case where a = most negative value properly, // we have to calculate a1_sign from the original values rather than using sign(a1, width) - T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), reduce_or(a, width), 1); + T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), factory.reduce_or(a, width), 1); T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width); T y1 = factory.unsigned_div(a2, b1, width); T y2 = extend(y1, width, y_width, false); @@ -560,6 +632,7 @@ void FunctionalIR::forward_buf() { _graph.permute(perm, alias); } +// Quoting routine to make error messages nicer static std::string quote_fmt(const char *fmt) { std::string r; diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 99fc872a8..e58669569 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -31,45 +31,123 @@ YOSYS_NAMESPACE_BEGIN class FunctionalIR { public: + // each function is documented with a short pseudocode declaration or definition + // standard C/Verilog operators are used to describe the result + // + // the types used in this are: + // - bit[N]: a bitvector of N bits + // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend + // but is meant to indicate how the value is interpreted + // if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation + // - memory[N, M]: a memory with N address and M data bits + // - int: C++ int + // - Const[N]: yosys RTLIL::Const (with size() == N) + // - IdString: yosys IdString + // - any: used in documentation to indicate that the type is unconstrained + // + // nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int) + // additionally, they can carry a constant of type int, Const[N] or IdString + // each node has a 'sort' field that stores the type of the node + // slice, zero_extend, sign_extend use the type field to store out_width enum class Fn { + // invalid() = known-invalid/shouldn't happen value + // TODO: maybe remove this and use e.g. std::optional instead? invalid, + // buf(a: any): any = a + // no-op operation + // when constructing the compute graph we generate invalid buf() nodes as a placeholder + // and later insert the argument buf, + // slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width] + // required: offset + out_width <= in_width slice, + // zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended) + // required: out_width > in_width zero_extend, + // sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended) + // required: out_width > in_width sign_extend, + // concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax) + // concatenates two bitvectors, with a in the least significant position and b in the more significant position concat, + // add(a: bit[N], b: bit[N]): bit[N] = a + b add, + // sub(a: bit[N], b: bit[N]): bit[N] = a - b sub, + // mul(a: bit[N], b: bit[N]): bit[N] = a * b mul, + // unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b unsigned_div, + // unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b unsigned_mod, + // bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b bitwise_and, + // bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b bitwise_or, + // bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b bitwise_xor, + // bitwise_not(a: bit[N]): bit[N] = ~a bitwise_not, + // reduce_and(a: bit[N]): bit[1] = &a reduce_and, + // reduce_or(a: bit[N]): bit[1] = |a reduce_or, + // reduce_xor(a: bit[N]): bit[1] = ^a reduce_xor, + // unary_minus(a: bit[N]): bit[N] = -a unary_minus, + // equal(a: bit[N], b: bit[N]): bit[1] = (a == b) equal, + // not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b) not_equal, + // signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b) signed_greater_than, + // signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b) signed_greater_equal, + // unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b) unsigned_greater_than, + // unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b) unsigned_greater_equal, + // logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b + // required: M <= clog2(N + 1) logical_shift_left, + // logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b + // required: M <= clog2(N + 1) logical_shift_right, + // arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b + // required: M <= clog2(N + 1) arithmetic_shift_right, + // mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a mux, + // pmux(a: bit[N], b: bit[N*M], s: bit[M]): bit[N] + // required: no more than one bit in b is set + // if s[i] = 1 for any i, then returns b[i * N +: N] + // returns a if s == 0 pmux, + // constant(a: Const[N]): bit[N] = a constant, + // input(a: IdString): any + // returns the current value of the input with the specified name input, + // state(a: IdString): any + // returns the current value of the state variable with the specified name state, + // multiple(a: any, b: any, c: any, ...): any + // indicates a value driven by multiple inputs multiple, + // undriven(width: int): bit[width] + // indicates an undriven value undriven, + // memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr] memory_read, + // memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width] + // returns a copy of `memory` but with the value at `addr` changed to `data` memory_write }; + // returns the name of a FunctionalIR::Fn value, as a string literal + static const char *fn_to_string(Fn); + // FunctionalIR::Sort represents the sort or type of a node + // currently the only two types are signal/bit and memory class Sort { std::variant> _v; public: @@ -77,13 +155,18 @@ public: Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { } bool is_signal() const { return _v.index() == 0; } bool is_memory() const { return _v.index() == 1; } + // returns the width of a bitvector type, errors out for other types int width() const { return std::get<0>(_v); } + // returns the address width of a bitvector type, errors out for other types int addr_width() const { return std::get<1>(_v).first; } + // returns the data width of a bitvector type, errors out for other types int data_width() const { return std::get<1>(_v).second; } bool operator==(Sort const& other) const { return _v == other._v; } unsigned int hash() const { return mkhash(_v); } }; private: + // one NodeData is stored per Node, containing the function and non-node arguments + // note that NodeData is deduplicated by ComputeGraph class NodeData { Fn _fn; std::variant< @@ -107,9 +190,14 @@ private: return _fn == other._fn && _extra == other._extra; } }; + // Attr contains all the information about a note that should not be deduplicated struct Attr { Sort sort; }; + // our specialised version of ComputeGraph + // the sparse_attr IdString stores a naming suggestion, retrieved with name() + // the key is currently used to identify the nodes that represent output and next state values + // the bool is true for next state values using Graph = ComputeGraph>; Graph _graph; dict _inputs; @@ -132,53 +220,17 @@ private: } public: class Factory; + // Node is an immutable reference to a FunctionalIR node class Node { friend class Factory; friend class FunctionalIR; - Graph::Ref _ref; - explicit Node(Graph::Ref ref) : _ref(ref) { } - operator Graph::Ref() { return _ref; } - template struct PrintVisitor { - NodePrinter np; - PrintVisitor(NodePrinter np) : np(np) { } - std::string buf(Node, Node n) { return "buf(" + np(n) + ")"; } - std::string slice(Node, Node a, int, int offset, int out_width) { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; } - std::string zero_extend(Node, Node a, int, int out_width) { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } - std::string sign_extend(Node, Node a, int, int out_width) { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } - std::string concat(Node, Node a, int, Node b, int) { return "concat(" + np(a) + ", " + np(b) + ")"; } - std::string add(Node, Node a, Node b, int) { return "add(" + np(a) + ", " + np(b) + ")"; } - std::string sub(Node, Node a, Node b, int) { return "sub(" + np(a) + ", " + np(b) + ")"; } - std::string mul(Node, Node a, Node b, int) { return "mul(" + np(a) + ", " + np(b) + ")"; } - std::string unsigned_div(Node, Node a, Node b, int) { return "unsigned_div(" + np(a) + ", " + np(b) + ")"; } - std::string unsigned_mod(Node, Node a, Node b, int) { return "unsigned_mod(" + np(a) + ", " + np(b) + ")"; } - std::string bitwise_and(Node, Node a, Node b, int) { return "bitwise_and(" + np(a) + ", " + np(b) + ")"; } - std::string bitwise_or(Node, Node a, Node b, int) { return "bitwise_or(" + np(a) + ", " + np(b) + ")"; } - std::string bitwise_xor(Node, Node a, Node b, int) { return "bitwise_xor(" + np(a) + ", " + np(b) + ")"; } - std::string bitwise_not(Node, Node a, int) { return "bitwise_not(" + np(a) + ")"; } - std::string unary_minus(Node, Node a, int) { return "unary_minus(" + np(a) + ")"; } - std::string reduce_and(Node, Node a, int) { return "reduce_and(" + np(a) + ")"; } - std::string reduce_or(Node, Node a, int) { return "reduce_or(" + np(a) + ")"; } - std::string reduce_xor(Node, Node a, int) { return "reduce_xor(" + np(a) + ")"; } - std::string equal(Node, Node a, Node b, int) { return "equal(" + np(a) + ", " + np(b) + ")"; } - std::string not_equal(Node, Node a, Node b, int) { return "not_equal(" + np(a) + ", " + np(b) + ")"; } - std::string signed_greater_than(Node, Node a, Node b, int) { return "signed_greater_than(" + np(a) + ", " + np(b) + ")"; } - std::string signed_greater_equal(Node, Node a, Node b, int) { return "signed_greater_equal(" + np(a) + ", " + np(b) + ")"; } - std::string unsigned_greater_than(Node, Node a, Node b, int) { return "unsigned_greater_than(" + np(a) + ", " + np(b) + ")"; } - std::string unsigned_greater_equal(Node, Node a, Node b, int) { return "unsigned_greater_equal(" + np(a) + ", " + np(b) + ")"; } - std::string logical_shift_left(Node, Node a, Node b, int, int) { return "logical_shift_left(" + np(a) + ", " + np(b) + ")"; } - std::string logical_shift_right(Node, Node a, Node b, int, int) { return "logical_shift_right(" + np(a) + ", " + np(b) + ")"; } - std::string arithmetic_shift_right(Node, Node a, Node b, int, int) { return "arithmetic_shift_right(" + np(a) + ", " + np(b) + ")"; } - std::string mux(Node, Node a, Node b, Node s, int) { return "mux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; } - std::string pmux(Node, Node a, Node b, Node s, int, int) { return "pmux(" + np(a) + ", " + np(b) + ", " + np(s) + ")"; } - std::string constant(Node, RTLIL::Const value) { return "constant(" + value.as_string() + ")"; } - std::string input(Node, IdString name) { return "input(" + name.str() + ")"; } - std::string state(Node, IdString name) { return "state(" + name.str() + ")"; } - std::string memory_read(Node, Node mem, Node addr, int, int) { return "memory_read(" + np(mem) + ", " + np(addr) + ")"; } - std::string memory_write(Node, Node mem, Node addr, Node data, int, int) { return "memory_write(" + np(mem) + ", " + np(addr) + ", " + np(data) + ")"; } - std::string undriven(Node, int width) { return "undriven(" + std::to_string(width) + ")"; } - }; + Graph::ConstRef _ref; + explicit Node(Graph::ConstRef ref) : _ref(ref) { } + explicit operator Graph::ConstRef() { return _ref; } public: + // the node's index. may change if nodes are added or removed int id() const { return _ref.index(); } + // a name suggestion for the node, which need not be unique IdString name() const { if(_ref.has_sparse_attr()) return _ref.sparse_attr(); @@ -187,55 +239,135 @@ public: } Fn fn() const { return _ref.function().fn(); } Sort sort() const { return _ref.attr().sort; } + // returns the width of a bitvector node, errors out for other nodes int width() const { return sort().width(); } + size_t arg_count() const { return _ref.size(); } Node arg(int n) const { return Node(_ref.arg(n)); } + // visit calls the appropriate visitor method depending on the type of the node template auto visit(Visitor v) const { + // currently templated but could be switched to AbstractVisitor & switch(_ref.function().fn()) { case Fn::invalid: log_error("invalid node in visit"); break; case Fn::buf: return v.buf(*this, arg(0)); break; - case Fn::slice: return v.slice(*this, arg(0), arg(0).width(), _ref.function().as_int(), sort().width()); break; - case Fn::zero_extend: return v.zero_extend(*this, arg(0), arg(0).width(), width()); break; - case Fn::sign_extend: return v.sign_extend(*this, arg(0), arg(0).width(), width()); break; - case Fn::concat: return v.concat(*this, arg(0), arg(0).width(), arg(1), arg(1).width()); break; - case Fn::add: return v.add(*this, arg(0), arg(1), sort().width()); break; - case Fn::sub: return v.sub(*this, arg(0), arg(1), sort().width()); break; - case Fn::mul: return v.mul(*this, arg(0), arg(1), sort().width()); break; - case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1), sort().width()); break; - case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1), sort().width()); break; - case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1), sort().width()); break; - case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1), sort().width()); break; - case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1), sort().width()); break; - case Fn::bitwise_not: return v.bitwise_not(*this, arg(0), sort().width()); break; - case Fn::unary_minus: return v.unary_minus(*this, arg(0), sort().width()); break; - case Fn::reduce_and: return v.reduce_and(*this, arg(0), arg(0).width()); break; - case Fn::reduce_or: return v.reduce_or(*this, arg(0), arg(0).width()); break; - case Fn::reduce_xor: return v.reduce_xor(*this, arg(0), arg(0).width()); break; - case Fn::equal: return v.equal(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1), arg(0).width()); break; - case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; - case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; - case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1), arg(0).width(), arg(1).width()); break; - case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2), arg(0).width()); break; - case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2), arg(0).width(), arg(2).width()); break; + case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break; + case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break; + case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break; + case Fn::concat: return v.concat(*this, arg(0), arg(1)); break; + case Fn::add: return v.add(*this, arg(0), arg(1)); break; + case Fn::sub: return v.sub(*this, arg(0), arg(1)); break; + case Fn::mul: return v.mul(*this, arg(0), arg(1)); break; + case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break; + case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break; + case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break; + case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break; + case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break; + case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break; + case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break; + case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break; + case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break; + case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break; + case Fn::equal: return v.equal(*this, arg(0), arg(1)); break; + case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break; + case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; + case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break; + case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break; + case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; + case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break; + case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break; + case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2)); break; case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; - case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1), arg(1).width(), width()); break; - case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2), arg(1).width(), arg(2).width()); break; + case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; + case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; case Fn::multiple: log_error("multiple in visit"); break; case Fn::undriven: return v.undriven(*this, width()); break; } } - template std::string to_string(NodePrinter np) - { - return visit(PrintVisitor(np)); - } + std::string to_string(); + std::string to_string(std::function); }; + // AbstractVisitor provides an abstract base class for visitors + template struct AbstractVisitor { + virtual T buf(Node self, Node n) = 0; + virtual T slice(Node self, Node a, int offset, int out_width) = 0; + virtual T zero_extend(Node self, Node a, int out_width) = 0; + virtual T sign_extend(Node self, Node a, int out_width) = 0; + virtual T concat(Node self, Node a, Node b) = 0; + virtual T add(Node self, Node a, Node b) = 0; + virtual T sub(Node self, Node a, Node b) = 0; + virtual T mul(Node self, Node a, Node b) = 0; + virtual T unsigned_div(Node self, Node a, Node b) = 0; + virtual T unsigned_mod(Node self, Node a, Node b) = 0; + virtual T bitwise_and(Node self, Node a, Node b) = 0; + virtual T bitwise_or(Node self, Node a, Node b) = 0; + virtual T bitwise_xor(Node self, Node a, Node b) = 0; + virtual T bitwise_not(Node self, Node a) = 0; + virtual T unary_minus(Node self, Node a) = 0; + virtual T reduce_and(Node self, Node a) = 0; + virtual T reduce_or(Node self, Node a) = 0; + virtual T reduce_xor(Node self, Node a) = 0; + virtual T equal(Node self, Node a, Node b) = 0; + virtual T not_equal(Node self, Node a, Node b) = 0; + virtual T signed_greater_than(Node self, Node a, Node b) = 0; + virtual T signed_greater_equal(Node self, Node a, Node b) = 0; + virtual T unsigned_greater_than(Node self, Node a, Node b) = 0; + virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0; + virtual T logical_shift_left(Node self, Node a, Node b) = 0; + virtual T logical_shift_right(Node self, Node a, Node b) = 0; + virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; + virtual T mux(Node self, Node a, Node b, Node s) = 0; + virtual T pmux(Node self, Node a, Node b, Node s) = 0; + virtual T constant(Node self, RTLIL::Const value) = 0; + virtual T input(Node self, IdString name) = 0; + virtual T state(Node self, IdString name) = 0; + virtual T memory_read(Node self, Node mem, Node addr) = 0; + virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; + virtual T undriven(Node self, int width) = 0; + }; + // DefaultVisitor provides defaults for all visitor methods which just calls default_handler + template struct DefaultVisitor : public AbstractVisitor { + virtual T default_handler(Node self) = 0; + T buf(Node self, Node) override { return default_handler(self); } + T slice(Node self, Node, int, int) override { return default_handler(self); } + T zero_extend(Node self, Node, int) override { return default_handler(self); } + T sign_extend(Node self, Node, int) override { return default_handler(self); } + T concat(Node self, Node, Node) override { return default_handler(self); } + T add(Node self, Node, Node) override { return default_handler(self); } + T sub(Node self, Node, Node) override { return default_handler(self); } + T mul(Node self, Node, Node) override { return default_handler(self); } + T unsigned_div(Node self, Node, Node) override { return default_handler(self); } + T unsigned_mod(Node self, Node, Node) override { return default_handler(self); } + T bitwise_and(Node self, Node, Node) override { return default_handler(self); } + T bitwise_or(Node self, Node, Node) override { return default_handler(self); } + T bitwise_xor(Node self, Node, Node) override { return default_handler(self); } + T bitwise_not(Node self, Node) override { return default_handler(self); } + T unary_minus(Node self, Node) override { return default_handler(self); } + T reduce_and(Node self, Node) override { return default_handler(self); } + T reduce_or(Node self, Node) override { return default_handler(self); } + T reduce_xor(Node self, Node) override { return default_handler(self); } + T equal(Node self, Node, Node) override { return default_handler(self); } + T not_equal(Node self, Node, Node) override { return default_handler(self); } + T signed_greater_than(Node self, Node, Node) override { return default_handler(self); } + T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); } + T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); } + T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); } + T logical_shift_left(Node self, Node, Node) override { return default_handler(self); } + T logical_shift_right(Node self, Node, Node) override { return default_handler(self); } + T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } + T mux(Node self, Node, Node, Node) override { return default_handler(self); } + T pmux(Node self, Node, Node, Node) override { return default_handler(self); } + T constant(Node self, RTLIL::Const) override { return default_handler(self); } + T input(Node self, IdString) override { return default_handler(self); } + T state(Node self, IdString) override { return default_handler(self); } + T memory_read(Node self, Node, Node) override { return default_handler(self); } + T memory_write(Node self, Node, Node, Node) override { return default_handler(self); } + T undriven(Node self, int) override { return default_handler(self); } + }; + // a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes. class Factory { FunctionalIR &_ir; friend class FunctionalIR; @@ -243,19 +375,29 @@ public: Node add(NodeData &&fn, Sort &&sort, std::initializer_list args) { Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); for (auto arg : args) - ref.append_arg(Graph::Ref(arg)); + ref.append_arg(Graph::ConstRef(arg)); return Node(ref); } + Graph::Ref mutate(Node n) { + return _ir._graph[n._ref.index()]; + } void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); } void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } public: Node slice(Node a, int, int offset, int out_width) { log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); + if(offset == 0 && out_width == a.width()) + return a; return add(NodeData(Fn::slice, offset), Sort(out_width), {a}); } Node extend(Node a, int, int out_width, bool is_signed) { - log_assert(a.sort().is_signal() && a.sort().width() < out_width); + int in_width = a.sort().width(); + log_assert(a.sort().is_signal()); + if(in_width == out_width) + return a; + if(in_width < out_width) + return slice(a, in_width, 0, out_width); if(is_signed) return add(Fn::sign_extend, Sort(out_width), {a}); else @@ -275,9 +417,24 @@ public: Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } - Node reduce_and(Node a, int) { check_unary(a); return add(Fn::reduce_and, Sort(1), {a}); } - Node reduce_or(Node a, int) { check_unary(a); return add(Fn::reduce_or, Sort(1), {a}); } - Node reduce_xor(Node a, int) { check_unary(a); return add(Fn::reduce_xor, Sort(1), {a}); } + Node reduce_and(Node a, int) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_and, Sort(1), {a}); + } + Node reduce_or(Node a, int) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_or, Sort(1), {a}); + } + Node reduce_xor(Node a, int) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_xor, Sort(1), {a}); + } Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } @@ -313,7 +470,7 @@ public: void update_pending(Node node, Node value) { log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); log_assert(node.sort() == value.sort()); - node._ref.append_arg(value._ref); + mutate(node).append_arg(value._ref); } Node input(IdString name, int width) { _ir.add_input(name, Sort(width)); @@ -333,7 +490,7 @@ public: Node multiple(vector args, int width) { auto node = add(Fn::multiple, Sort(width), {}); for(const auto &arg : args) - node._ref.append_arg(arg._ref); + mutate(node).append_arg(arg._ref); return node; } Node undriven(int width) { @@ -341,18 +498,18 @@ public: } void declare_output(Node node, IdString name, int width) { _ir.add_output(name, Sort(width)); - node._ref.assign_key({name, false}); + mutate(node).assign_key({name, false}); } void declare_state(Node node, IdString name, int width) { _ir.add_state(name, Sort(width)); - node._ref.assign_key({name, true}); + mutate(node).assign_key({name, true}); } void declare_state_memory(Node node, IdString name, int addr_width, int data_width) { _ir.add_state(name, Sort(addr_width, data_width)); - node._ref.assign_key({name, true}); + mutate(node).assign_key({name, true}); } void suggest_name(Node node, IdString name) { - node._ref.sparse_attr() = name; + mutate(node).sparse_attr() = name; } }; static FunctionalIR from_module(Module *module); From 7f8f21b980770f2771aae61f830a5784fc16fbe6 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 17 Jul 2024 12:42:24 +0100 Subject: [PATCH 137/342] remove widths parameters from FunctionalIR factory methods and from functionalir.cc --- kernel/functionalir.cc | 391 +++++++++++++++++++---------------------- kernel/functionalir.h | 66 ++++--- 2 files changed, 216 insertions(+), 241 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 9b8076a0e..48baad716 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -98,87 +98,75 @@ std::string FunctionalIR::Node::to_string(std::function np) return visit(PrintVisitor(np)); } -template class CellSimplifier { - Factory &factory; - T reduce_shift_width(T b, int b_width, int y_width, int &reduced_b_width) { + using Node = FunctionalIR::Node; + FunctionalIR::Factory &factory; + Node reduce_shift_width(Node b, int y_width) { log_assert(y_width > 0); int new_width = ceil_log2(y_width + 1); - if (b_width <= new_width) { - reduced_b_width = b_width; + if (b.width() <= new_width) { return b; } else { - reduced_b_width = new_width; - T lower_b = factory.slice(b, b_width, 0, new_width); - T overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b_width)), b_width); - return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow, new_width); + Node lower_b = factory.slice(b, 0, new_width); + Node overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b.width()))); + return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow); } } - T sign(T a, int a_width) { - return factory.slice(a, a_width, a_width - 1, 1); + Node sign(Node a) { + return factory.slice(a, a.width() - 1, 1); } - T neg_if(T a, int a_width, T s) { - return factory.mux(a, factory.unary_minus(a, a_width), s, a_width); + Node neg_if(Node a, Node s) { + return factory.mux(a, factory.unary_minus(a), s); } - T abs(T a, int a_width) { - return neg_if(a, a_width, sign(a, a_width)); + Node abs(Node a) { + return neg_if(a, sign(a)); } public: - T extend(T a, int in_width, int out_width, bool is_signed) { - if(in_width == out_width) - return a; - if(in_width > out_width) - return factory.slice(a, in_width, 0, out_width); - return factory.extend(a, in_width, out_width, is_signed); + Node logical_shift_left(Node a, Node b) { + Node reduced_b = reduce_shift_width(b, a.width()); + return factory.logical_shift_left(a, reduced_b); } - T logical_shift_left(T a, T b, int y_width, int b_width) { - int reduced_b_width; - T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); - return factory.logical_shift_left(a, reduced_b, y_width, reduced_b_width); + Node logical_shift_right(Node a, Node b) { + Node reduced_b = reduce_shift_width(b, a.width()); + return factory.logical_shift_right(a, reduced_b); } - T logical_shift_right(T a, T b, int y_width, int b_width) { - int reduced_b_width; - T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); - return factory.logical_shift_right(a, reduced_b, y_width, reduced_b_width); + Node arithmetic_shift_right(Node a, Node b) { + Node reduced_b = reduce_shift_width(b, a.width()); + return factory.arithmetic_shift_right(a, reduced_b); } - T arithmetic_shift_right(T a, T b, int y_width, int b_width) { - int reduced_b_width; - T reduced_b = reduce_shift_width(b, b_width, y_width, reduced_b_width); - return factory.arithmetic_shift_right(a, reduced_b, y_width, reduced_b_width); + Node bitwise_mux(Node a, Node b, Node s) { + Node aa = factory.bitwise_and(a, factory.bitwise_not(s)); + Node bb = factory.bitwise_and(b, s); + return factory.bitwise_or(aa, bb); } - T bitwise_mux(T a, T b, T s, int width) { - T aa = factory.bitwise_and(a, factory.bitwise_not(s, width), width); - T bb = factory.bitwise_and(b, s, width); - return factory.bitwise_or(aa, bb, width); - } - CellSimplifier(Factory &f) : factory(f) {} + CellSimplifier(FunctionalIR::Factory &f) : factory(f) {} private: - T handle_pow(T a0, int a_width, T b, int b_width, int y_width, bool is_signed) { - T a = extend(a0, a_width, y_width, is_signed); - T r = factory.constant(Const(1, y_width)); - for(int i = 0; i < b_width; i++) { - T b_bit = factory.slice(b, b_width, i, 1); - r = factory.mux(r, factory.mul(r, a, y_width), b_bit, y_width); - a = factory.mul(a, a, y_width); + Node handle_pow(Node a0, Node b, int y_width, bool is_signed) { + Node a = factory.extend(a0, y_width, is_signed); + Node r = factory.constant(Const(1, y_width)); + for(int i = 0; i < b.width(); i++) { + Node b_bit = factory.slice(b, i, 1); + r = factory.mux(r, factory.mul(r, a), b_bit); + a = factory.mul(a, a); } if (is_signed) { - T a_ge_1 = factory.unsigned_greater_than(abs(a0, a_width), factory.constant(Const(1, a_width)), a_width); - T zero_result = factory.bitwise_and(a_ge_1, sign(b, b_width), 1); - r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result, y_width); + Node a_ge_1 = factory.unsigned_greater_than(abs(a0), factory.constant(Const(1, a0.width()))); + Node zero_result = factory.bitwise_and(a_ge_1, sign(b)); + r = factory.mux(r, factory.constant(Const(0, y_width)), zero_result); } return r; } - T handle_bmux(T a, T s, int a_width, int a_offset, int width, int s_width, int sn) { + Node handle_bmux(Node a, Node s, int a_offset, int width, int sn) { if(sn < 1) - return factory.slice(a, a_width, a_offset, width); + return factory.slice(a, a_offset, width); else { - T y0 = handle_bmux(a, s, a_width, a_offset, width, s_width, sn - 1); - T y1 = handle_bmux(a, s, a_width, a_offset + (width << (sn - 1)), width, s_width, sn - 1); - return factory.mux(y0, y1, factory.slice(s, s_width, sn - 1, 1), width); + Node y0 = handle_bmux(a, s, a_offset, width, sn - 1); + Node y1 = handle_bmux(a, s, a_offset + (width << (sn - 1)), width, sn - 1); + return factory.mux(y0, y1, factory.slice(s, sn - 1, 1)); } } public: - T handle(IdString cellType, dict parameters, dict inputs) + Node handle(IdString cellType, dict parameters, dict inputs) { int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); @@ -187,208 +175,202 @@ public: bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); if(cellType.in({ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul)})){ bool is_signed = a_signed && b_signed; - T a = extend(inputs.at(ID(A)), a_width, y_width, is_signed); - T b = extend(inputs.at(ID(B)), b_width, y_width, is_signed); + Node a = factory.extend(inputs.at(ID(A)), y_width, is_signed); + Node b = factory.extend(inputs.at(ID(B)), y_width, is_signed); if(cellType == ID($add)) - return factory.add(a, b, y_width); + return factory.add(a, b); else if(cellType == ID($sub)) - return factory.sub(a, b, y_width); + return factory.sub(a, b); else if(cellType == ID($mul)) - return factory.mul(a, b, y_width); + return factory.mul(a, b); else if(cellType == ID($and)) - return factory.bitwise_and(a, b, y_width); + return factory.bitwise_and(a, b); else if(cellType == ID($or)) - return factory.bitwise_or(a, b, y_width); + return factory.bitwise_or(a, b); else if(cellType == ID($xor)) - return factory.bitwise_xor(a, b, y_width); + return factory.bitwise_xor(a, b); else if(cellType == ID($xnor)) - return factory.bitwise_not(factory.bitwise_xor(a, b, y_width), y_width); + return factory.bitwise_not(factory.bitwise_xor(a, b)); else log_abort(); }else if(cellType.in({ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt)})){ bool is_signed = a_signed && b_signed; int width = max(a_width, b_width); - T a = extend(inputs.at(ID(A)), a_width, width, is_signed); - T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + Node a = factory.extend(inputs.at(ID(A)), width, is_signed); + Node b = factory.extend(inputs.at(ID(B)), width, is_signed); if(cellType.in({ID($eq), ID($eqx)})) - return extend(factory.equal(a, b, width), 1, y_width, false); + return factory.extend(factory.equal(a, b), y_width, false); else if(cellType.in({ID($ne), ID($nex)})) - return extend(factory.not_equal(a, b, width), 1, y_width, false); + return factory.extend(factory.not_equal(a, b), y_width, false); else if(cellType == ID($lt)) - return extend(is_signed ? factory.signed_greater_than(b, a, width) : factory.unsigned_greater_than(b, a, width), 1, y_width, false); + return factory.extend(is_signed ? factory.signed_greater_than(b, a) : factory.unsigned_greater_than(b, a), y_width, false); else if(cellType == ID($le)) - return extend(is_signed ? factory.signed_greater_equal(b, a, width) : factory.unsigned_greater_equal(b, a, width), 1, y_width, false); + return factory.extend(is_signed ? factory.signed_greater_equal(b, a) : factory.unsigned_greater_equal(b, a), y_width, false); else if(cellType == ID($gt)) - return extend(is_signed ? factory.signed_greater_than(a, b, width) : factory.unsigned_greater_than(a, b, width), 1, y_width, false); + return factory.extend(is_signed ? factory.signed_greater_than(a, b) : factory.unsigned_greater_than(a, b), y_width, false); else if(cellType == ID($ge)) - return extend(is_signed ? factory.signed_greater_equal(a, b, width) : factory.unsigned_greater_equal(a, b, width), 1, y_width, false); + return factory.extend(is_signed ? factory.signed_greater_equal(a, b) : factory.unsigned_greater_equal(a, b), y_width, false); else log_abort(); }else if(cellType.in({ID($logic_or), ID($logic_and)})){ - T a = factory.reduce_or(inputs.at(ID(A)), a_width); - T b = factory.reduce_or(inputs.at(ID(B)), b_width); - T y = cellType == ID($logic_and) ? factory.bitwise_and(a, b, 1) : factory.bitwise_or(a, b, 1); - return extend(y, 1, y_width, false); + Node a = factory.reduce_or(inputs.at(ID(A))); + Node b = factory.reduce_or(inputs.at(ID(B))); + Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b); + return factory.extend(y, y_width, false); }else if(cellType == ID($not)){ - T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); - return factory.bitwise_not(a, y_width); + Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); + return factory.bitwise_not(a); }else if(cellType == ID($pos)){ - return extend(inputs.at(ID(A)), a_width, y_width, a_signed); + return factory.extend(inputs.at(ID(A)), y_width, a_signed); }else if(cellType == ID($neg)){ - T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); - return factory.unary_minus(a, y_width); + Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); + return factory.unary_minus(a); }else if(cellType == ID($logic_not)){ - T a = factory.reduce_or(inputs.at(ID(A)), a_width); - T y = factory.bitwise_not(a, 1); - return extend(y, 1, y_width, false); + Node a = factory.reduce_or(inputs.at(ID(A))); + Node y = factory.bitwise_not(a); + return factory.extend(y, y_width, false); }else if(cellType.in({ID($reduce_or), ID($reduce_bool)})){ - T a = factory.reduce_or(inputs.at(ID(A)), a_width); - return extend(a, 1, y_width, false); + Node a = factory.reduce_or(inputs.at(ID(A))); + return factory.extend(a, y_width, false); }else if(cellType == ID($reduce_and)){ - T a = factory.reduce_and(inputs.at(ID(A)), a_width); - return extend(a, 1, y_width, false); + Node a = factory.reduce_and(inputs.at(ID(A))); + return factory.extend(a, y_width, false); }else if(cellType.in({ID($reduce_xor), ID($reduce_xnor)})){ - T a = factory.reduce_xor(inputs.at(ID(A)), a_width); - T y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a, 1) : a; - return extend(y, 1, y_width, false); + Node a = factory.reduce_xor(inputs.at(ID(A))); + Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a; + return factory.extend(y, y_width, false); }else if(cellType == ID($shl) || cellType == ID($sshl)){ - T a = extend(inputs.at(ID(A)), a_width, y_width, a_signed); - T b = inputs.at(ID(B)); - return logical_shift_left(a, b, y_width, b_width); + Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); + Node b = inputs.at(ID(B)); + return logical_shift_left(a, b); }else if(cellType == ID($shr) || cellType == ID($sshr)){ int width = max(a_width, y_width); - T a = extend(inputs.at(ID(A)), a_width, width, a_signed); - T b = inputs.at(ID(B)); - T y = a_signed && cellType == ID($sshr) ? - arithmetic_shift_right(a, b, width, b_width) : - logical_shift_right(a, b, width, b_width); - return extend(y, width, y_width, a_signed); + Node a = factory.extend(inputs.at(ID(A)), width, a_signed); + Node b = inputs.at(ID(B)); + Node y = a_signed && cellType == ID($sshr) ? + arithmetic_shift_right(a, b) : + logical_shift_right(a, b); + return factory.extend(y, y_width, a_signed); }else if(cellType == ID($shiftx) || cellType == ID($shift)){ int width = max(a_width, y_width); - T a = extend(inputs.at(ID(A)), a_width, width, cellType == ID($shift) && a_signed); - T b = inputs.at(ID(B)); - T shr = logical_shift_right(a, b, width, b_width); + Node a = factory.extend(inputs.at(ID(A)), width, cellType == ID($shift) && a_signed); + Node b = inputs.at(ID(B)); + Node shr = logical_shift_right(a, b); if(b_signed) { - T sign_b = sign(b, b_width); - T shl = logical_shift_left(a, factory.unary_minus(b, b_width), width, b_width); - T y = factory.mux(shr, shl, sign_b, width); - return extend(y, width, y_width, false); + Node shl = logical_shift_left(a, factory.unary_minus(b)); + Node y = factory.mux(shr, shl, sign(b)); + return factory.extend(y, y_width, false); } else { - return extend(shr, width, y_width, false); + return factory.extend(shr, y_width, false); } }else if(cellType == ID($mux)){ - int width = parameters.at(ID(WIDTH)).as_int(); - return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width); + return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); }else if(cellType == ID($pmux)){ - int width = parameters.at(ID(WIDTH)).as_int(); - int s_width = parameters.at(ID(S_WIDTH)).as_int(); - return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S)), width, s_width); + return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); }else if(cellType == ID($concat)){ - T a = inputs.at(ID(A)); - T b = inputs.at(ID(B)); - return factory.concat(a, a_width, b, b_width); + Node a = inputs.at(ID(A)); + Node b = inputs.at(ID(B)); + return factory.concat(a, b); }else if(cellType == ID($slice)){ int offset = parameters.at(ID(OFFSET)).as_int(); - T a = inputs.at(ID(A)); - return factory.slice(a, a_width, offset, y_width); + Node a = inputs.at(ID(A)); + return factory.slice(a, offset, y_width); }else if(cellType.in({ID($div), ID($mod), ID($divfloor), ID($modfloor)})) { int width = max(a_width, b_width); bool is_signed = a_signed && b_signed; - T a = extend(inputs.at(ID(A)), a_width, width, is_signed); - T b = extend(inputs.at(ID(B)), b_width, width, is_signed); + Node a = factory.extend(inputs.at(ID(A)), width, is_signed); + Node b = factory.extend(inputs.at(ID(B)), width, is_signed); if(is_signed) { if(cellType == ID($div)) { // divide absolute values, then flip the sign if input signs differ // but extend the width first, to handle the case (most negative value) / (-1) - T abs_y = factory.unsigned_div(abs(a, width), abs(b, width), width); - T out_sign = factory.not_equal(sign(a, width), sign(b, width), 1); - return neg_if(extend(abs_y, width, y_width, false), y_width, out_sign); + Node abs_y = factory.unsigned_div(abs(a), abs(b)); + Node out_sign = factory.not_equal(sign(a), sign(b)); + return neg_if(factory.extend(abs_y, y_width, false), out_sign); } else if(cellType == ID($mod)) { // similar to division but output sign == divisor sign - T abs_y = factory.unsigned_mod(abs(a, width), abs(b, width), width); - return neg_if(extend(abs_y, width, y_width, false), y_width, sign(a, width)); + Node abs_y = factory.unsigned_mod(abs(a), abs(b)); + return neg_if(factory.extend(abs_y, y_width, false), sign(a)); } else if(cellType == ID($divfloor)) { // if b is negative, flip both signs so that b is positive - T b_sign = sign(b, width); - T a1 = neg_if(a, width, b_sign); - T b1 = neg_if(b, width, b_sign); + Node b_sign = sign(b); + Node a1 = neg_if(a, b_sign); + Node b1 = neg_if(b, b_sign); // if a is now negative, calculate ~((~a) / b) = -((-a - 1) / b + 1) // which equals the negative of (-a) / b with rounding up rather than down // note that to handle the case where a = most negative value properly, - // we have to calculate a1_sign from the original values rather than using sign(a1, width) - T a1_sign = factory.bitwise_and(factory.not_equal(sign(a, width), sign(b, width), 1), factory.reduce_or(a, width), 1); - T a2 = factory.mux(a1, factory.bitwise_not(a1, width), a1_sign, width); - T y1 = factory.unsigned_div(a2, b1, width); - T y2 = extend(y1, width, y_width, false); - return factory.mux(y2, factory.bitwise_not(y2, y_width), a1_sign, y_width); + // we have to calculate a1_sign from the original values rather than using sign(a1) + Node a1_sign = factory.bitwise_and(factory.not_equal(sign(a), sign(b)), factory.reduce_or(a)); + Node a2 = factory.mux(a1, factory.bitwise_not(a1), a1_sign); + Node y1 = factory.unsigned_div(a2, b1); + Node y2 = factory.extend(y1, y_width, false); + return factory.mux(y2, factory.bitwise_not(y2), a1_sign); } else if(cellType == ID($modfloor)) { // calculate |a| % |b| and then subtract from |b| if input signs differ and the remainder is non-zero - T abs_b = abs(b, width); - T abs_y = factory.unsigned_mod(abs(a, width), abs_b, width); - T flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a, width), sign(b, width), 1), factory.reduce_or(abs_y, width), 1); - T y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y, width), flip_y, width); + Node abs_b = abs(b); + Node abs_y = factory.unsigned_mod(abs(a), abs_b); + Node flip_y = factory.bitwise_and(factory.bitwise_xor(sign(a), sign(b)), factory.reduce_or(abs_y)); + Node y_flipped = factory.mux(abs_y, factory.sub(abs_b, abs_y), flip_y); // since y_flipped is strictly less than |b|, the top bit is always 0 and we can just sign extend the flipped result - T y = neg_if(y_flipped, width, sign(b, b_width)); - return extend(y, width, y_width, true); + Node y = neg_if(y_flipped, sign(b)); + return factory.extend(y, y_width, true); } else log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } else { if(cellType.in({ID($mod), ID($modfloor)})) - return extend(factory.unsigned_mod(a, b, width), width, y_width, false); + return factory.extend(factory.unsigned_mod(a, b), y_width, false); else - return extend(factory.unsigned_div(a, b, width), width, y_width, false); + return factory.extend(factory.unsigned_div(a, b), y_width, false); } } else if(cellType == ID($pow)) { - return handle_pow(inputs.at(ID(A)), a_width, inputs.at(ID(B)), b_width, y_width, a_signed && b_signed); + return handle_pow(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed); } else if (cellType == ID($lut)) { int width = parameters.at(ID(WIDTH)).as_int(); Const lut_table = parameters.at(ID(LUT)); lut_table.extu(1 << width); - return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 1 << width, 0, 1, width, width); + return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 0, 1, width); } else if (cellType == ID($bwmux)) { - int width = parameters.at(ID(WIDTH)).as_int(); - T a = inputs.at(ID(A)); - T b = inputs.at(ID(B)); - T s = inputs.at(ID(S)); + Node a = inputs.at(ID(A)); + Node b = inputs.at(ID(B)); + Node s = inputs.at(ID(S)); return factory.bitwise_or( - factory.bitwise_and(a, factory.bitwise_not(s, width), width), - factory.bitwise_and(b, s, width), width); + factory.bitwise_and(a, factory.bitwise_not(s)), + factory.bitwise_and(b, s)); } else if (cellType == ID($bweqx)) { - int width = parameters.at(ID(WIDTH)).as_int(); - T a = inputs.at(ID(A)); - T b = inputs.at(ID(B)); - return factory.bitwise_not(factory.bitwise_xor(a, b, width), width); + Node a = inputs.at(ID(A)); + Node b = inputs.at(ID(B)); + return factory.bitwise_not(factory.bitwise_xor(a, b)); } else if(cellType == ID($bmux)) { int width = parameters.at(ID(WIDTH)).as_int(); int s_width = parameters.at(ID(S_WIDTH)).as_int(); - return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), width << s_width, 0, width, s_width, s_width); + return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), 0, width, s_width); } else if(cellType == ID($demux)) { int width = parameters.at(ID(WIDTH)).as_int(); int s_width = parameters.at(ID(S_WIDTH)).as_int(); int y_width = width << s_width; int b_width = ceil_log2(y_width + 1); - T a = extend(inputs.at(ID(A)), width, y_width, false); - T s = factory.extend(inputs.at(ID(S)), s_width, b_width, false); - T b = factory.mul(s, factory.constant(Const(width, b_width)), b_width); - return factory.logical_shift_left(a, b, y_width, b_width); + Node a = factory.extend(inputs.at(ID(A)), y_width, false); + Node s = factory.extend(inputs.at(ID(S)), b_width, false); + Node b = factory.mul(s, factory.constant(Const(width, b_width))); + return factory.logical_shift_left(a, b); } else { log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); } } }; -template class FunctionalIRConstruction { + using Node = FunctionalIR::Node; std::deque queue; - dict graph_nodes; + dict graph_nodes; idict cells; DriverMap driver_map; - Factory& factory; - CellSimplifier simplifier; + FunctionalIR::Factory& factory; + CellSimplifier simplifier; vector memories_vector; dict memories; - T enqueue(DriveSpec const &spec) + Node enqueue(DriveSpec const &spec) { auto it = graph_nodes.find(spec); if(it == graph_nodes.end()){ @@ -400,7 +382,7 @@ class FunctionalIRConstruction { return it->second; } public: - FunctionalIRConstruction(Factory &f) : factory(f), simplifier(f) {} + FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {} void add_module(Module *module) { driver_map.add(module); @@ -410,7 +392,7 @@ public: } for (auto wire : module->wires()) { if (wire->port_output) { - T node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + Node node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); factory.declare_output(node, wire->name, wire->width); } } @@ -420,37 +402,34 @@ public: memories[mem.cell] = &mem; } } - T concatenate_read_results(Mem *, vector results) + Node concatenate_read_results(Mem *, vector results) { /* TODO: write code to check that this is ok to do */ if(results.size() == 0) return factory.undriven(0); - T node = results[0]; - int size = results[0].width(); - for(size_t i = 1; i < results.size(); i++) { - node = factory.concat(node, size, results[i], results[i].width()); - size += results[i].width(); - } + Node node = results[0]; + for(size_t i = 1; i < results.size(); i++) + node = factory.concat(node, results[i]); return node; } - T handle_memory(Mem *mem) + Node handle_memory(Mem *mem) { - vector read_results; + vector read_results; int addr_width = ceil_log2(mem->size); int data_width = mem->width; - T node = factory.state_memory(mem->cell->name, addr_width, data_width); + Node node = factory.state_memory(mem->cell->name, addr_width, data_width); for (auto &rd : mem->rd_ports) { log_assert(!rd.clk_enable); - T addr = enqueue(driver_map(DriveSpec(rd.addr))); - read_results.push_back(factory.memory_read(node, addr, addr_width, data_width)); + Node addr = enqueue(driver_map(DriveSpec(rd.addr))); + read_results.push_back(factory.memory_read(node, addr)); } for (auto &wr : mem->wr_ports) { - T en = enqueue(driver_map(DriveSpec(wr.en))); - T addr = enqueue(driver_map(DriveSpec(wr.addr))); - T new_data = enqueue(driver_map(DriveSpec(wr.data))); - T old_data = factory.memory_read(node, addr, addr_width, data_width); - T wr_data = simplifier.bitwise_mux(old_data, new_data, en, data_width); - node = factory.memory_write(node, addr, wr_data, addr_width, data_width); + Node en = enqueue(driver_map(DriveSpec(wr.en))); + Node addr = enqueue(driver_map(DriveSpec(wr.addr))); + Node new_data = enqueue(driver_map(DriveSpec(wr.data))); + Node old_data = factory.memory_read(node, addr); + Node wr_data = simplifier.bitwise_mux(old_data, new_data, en); + node = factory.memory_write(node, addr, wr_data); } factory.declare_state_memory(node, mem->cell->name, addr_width, data_width); return concatenate_read_results(mem, read_results); @@ -459,16 +438,13 @@ public: { for (; !queue.empty(); queue.pop_front()) { DriveSpec spec = queue.front(); - T pending = graph_nodes.at(spec); + Node pending = graph_nodes.at(spec); if (spec.chunks().size() > 1) { auto chunks = spec.chunks(); - T node = enqueue(chunks[0]); - int width = chunks[0].size(); - for(size_t i = 1; i < chunks.size(); i++) { - node = factory.concat(node, width, enqueue(chunks[i]), chunks[i].size()); - width += chunks[i].size(); - } + Node node = enqueue(chunks[0]); + for(size_t i = 1; i < chunks.size(); i++) + node = factory.concat(node, enqueue(chunks[i])); factory.update_pending(pending, node); } else if (spec.chunks().size() == 1) { DriveChunk chunk = spec.chunks()[0]; @@ -476,18 +452,18 @@ public: DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { if (wire_chunk.wire->port_input) { - T node = factory.input(wire_chunk.wire->name, wire_chunk.width); + Node node = factory.input(wire_chunk.wire->name, wire_chunk.width); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(wire_chunk)); - T node = enqueue(driver); + Node node = enqueue(driver); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); } } else { DriveChunkWire whole_wire(wire_chunk.wire, 0, wire_chunk.wire->width); - T node = factory.slice(enqueue(whole_wire), wire_chunk.wire->width, wire_chunk.offset, wire_chunk.width); + Node node = factory.slice(enqueue(whole_wire), wire_chunk.offset, wire_chunk.width); factory.update_pending(pending, node); } } else if (chunk.is_port()) { @@ -497,21 +473,22 @@ public: if (port_chunk.cell->type.in(ID($dff), ID($ff))) { Cell *cell = port_chunk.cell; - T node = factory.state(cell->name, port_chunk.width); + Node node = factory.state(cell->name, port_chunk.width); factory.suggest_name(node, port_chunk.cell->name); factory.update_pending(pending, node); for (auto const &conn : cell->connections()) { if (driver_map.celltypes.cell_input(cell->type, conn.first)) { - T node = enqueue(DriveChunkPort(cell, conn)); + Node node = enqueue(DriveChunkPort(cell, conn)); factory.declare_state(node, cell->name, port_chunk.width); } } } else { - T cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); + Node cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); factory.suggest_name(cell, port_chunk.cell->name); - T node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); + //Node node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); + Node node = cell; factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str()); factory.update_pending(pending, node); } @@ -521,37 +498,37 @@ public: } } else { DriveChunkPort whole_port(port_chunk.cell, port_chunk.port, 0, GetSize(port_chunk.cell->connections().at(port_chunk.port))); - T node = factory.slice(enqueue(whole_port), whole_port.width, port_chunk.offset, port_chunk.width); + Node node = factory.slice(enqueue(whole_port), port_chunk.offset, port_chunk.width); factory.update_pending(pending, node); } } else if (chunk.is_constant()) { - T node = factory.constant(chunk.constant()); + Node node = factory.constant(chunk.constant()); factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string()); factory.update_pending(pending, node); } else if (chunk.is_multiple()) { - vector args; + vector args; for (auto const &driver : chunk.multiple().multiple()) args.push_back(enqueue(driver)); - T node = factory.multiple(args, chunk.size()); + Node node = factory.multiple(args, chunk.size()); factory.update_pending(pending, node); } else if (chunk.is_marker()) { Cell *cell = cells[chunk.marker().marker]; if (cell->is_mem_cell()) { Mem *mem = memories.at(cell, nullptr); log_assert(mem != nullptr); - T node = handle_memory(mem); + Node node = handle_memory(mem); factory.update_pending(pending, node); } else { - dict connections; + dict connections; for(auto const &conn : cell->connections()) { if(driver_map.celltypes.cell_input(cell->type, conn.first)) connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); } - T node = simplifier.handle(cell->type, cell->parameters, connections); + Node node = simplifier.handle(cell->type, cell->parameters, connections); factory.update_pending(pending, node); } } else if (chunk.is_none()) { - T node = factory.undriven(chunk.size()); + Node node = factory.undriven(chunk.size()); factory.update_pending(pending, node); } else { log_error("unhandled drivespec: %s\n", log_signal(chunk)); @@ -567,7 +544,7 @@ public: FunctionalIR FunctionalIR::from_module(Module *module) { FunctionalIR ir; auto factory = ir.factory(); - FunctionalIRConstruction ctor(factory); + FunctionalIRConstruction ctor(factory); ctor.add_module(module); ctor.process_queue(); ir.topological_sort(); diff --git a/kernel/functionalir.h b/kernel/functionalir.h index e58669569..44e3589db 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -385,78 +385,79 @@ public: void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); } void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } public: - Node slice(Node a, int, int offset, int out_width) { + Node slice(Node a, int offset, int out_width) { log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); if(offset == 0 && out_width == a.width()) return a; return add(NodeData(Fn::slice, offset), Sort(out_width), {a}); } - Node extend(Node a, int, int out_width, bool is_signed) { + // extend will either extend or truncate the provided value to reach the desired width + Node extend(Node a, int out_width, bool is_signed) { int in_width = a.sort().width(); log_assert(a.sort().is_signal()); if(in_width == out_width) return a; - if(in_width < out_width) - return slice(a, in_width, 0, out_width); + if(in_width > out_width) + return slice(a, 0, out_width); if(is_signed) return add(Fn::sign_extend, Sort(out_width), {a}); else return add(Fn::zero_extend, Sort(out_width), {a}); } - Node concat(Node a, int, Node b, int) { + Node concat(Node a, Node b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b}); } - Node add(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } - Node sub(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } - Node mul(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); } - Node unsigned_div(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); } - Node unsigned_mod(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); } - Node bitwise_and(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } - Node bitwise_or(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } - Node bitwise_xor(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } - Node bitwise_not(Node a, int) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } - Node unary_minus(Node a, int) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } - Node reduce_and(Node a, int) { + Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } + Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } + Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); } + Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); } + Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); } + Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } + Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } + Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } + Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } + Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } + Node reduce_and(Node a) { check_unary(a); if(a.width() == 1) return a; return add(Fn::reduce_and, Sort(1), {a}); } - Node reduce_or(Node a, int) { + Node reduce_or(Node a) { check_unary(a); if(a.width() == 1) return a; return add(Fn::reduce_or, Sort(1), {a}); } - Node reduce_xor(Node a, int) { + Node reduce_xor(Node a) { check_unary(a); if(a.width() == 1) return a; return add(Fn::reduce_xor, Sort(1), {a}); } - Node equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } - Node not_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } - Node signed_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } - Node signed_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); } - Node unsigned_greater_than(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); } - Node unsigned_greater_equal(Node a, Node b, int) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); } - Node logical_shift_left(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); } - Node logical_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); } - Node arithmetic_shift_right(Node a, Node b, int, int) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); } - Node mux(Node a, Node b, Node s, int) { + Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } + Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } + Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } + Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); } + Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); } + Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); } + Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); } + Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); } + Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); } + Node mux(Node a, Node b, Node s) { log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1)); return add(Fn::mux, a.sort(), {a, b, s}); } - Node pmux(Node a, Node b, Node s, int, int) { + Node pmux(Node a, Node b, Node s) { log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width()); return add(Fn::pmux, a.sort(), {a, b, s}); } - Node memory_read(Node mem, Node addr, int, int) { + Node memory_read(Node mem, Node addr) { log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width()); return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr}); } - Node memory_write(Node mem, Node addr, Node data, int, int) { + Node memory_write(Node mem, Node addr, Node data) { log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() && mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width()); return add(Fn::memory_write, mem.sort(), {mem, addr, data}); @@ -484,9 +485,6 @@ public: _ir.add_state(name, Sort(addr_width, data_width)); return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {}); } - Node cell_output(Node node, IdString, IdString, int) { - return node; - } Node multiple(vector args, int width) { auto node = add(Fn::multiple, Sort(width), {}); for(const auto &arg : args) From c0c90c2c312e8f1675613904a67d5e016a62bb03 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 17 Jul 2024 13:26:53 +0100 Subject: [PATCH 138/342] functional backend: require shift width == clog2(operand width) --- kernel/functionalir.cc | 48 ++++++++++++++++----------------- kernel/functionalir.h | 10 ++++--- tests/functional/rtlil_cells.py | 5 +++- 3 files changed, 34 insertions(+), 29 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 48baad716..ddd821ada 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -101,17 +101,6 @@ std::string FunctionalIR::Node::to_string(std::function np) class CellSimplifier { using Node = FunctionalIR::Node; FunctionalIR::Factory &factory; - Node reduce_shift_width(Node b, int y_width) { - log_assert(y_width > 0); - int new_width = ceil_log2(y_width + 1); - if (b.width() <= new_width) { - return b; - } else { - Node lower_b = factory.slice(b, 0, new_width); - Node overflow = factory.unsigned_greater_than(b, factory.constant(RTLIL::Const(y_width, b.width()))); - return factory.mux(lower_b, factory.constant(RTLIL::Const(y_width, new_width)), overflow); - } - } Node sign(Node a) { return factory.slice(a, a.width() - 1, 1); } @@ -121,19 +110,30 @@ class CellSimplifier { Node abs(Node a) { return neg_if(a, sign(a)); } + Node handle_shift(Node a, Node b, bool is_right, bool is_signed) { + // to prevent new_width == 0, we handle this case separately + if(a.width() == 1) { + if(!is_signed) + return factory.bitwise_and(a, factory.bitwise_not(factory.reduce_or(b))); + else + return a; + } + int new_width = ceil_log2(a.width()); + Node b_truncated = factory.extend(b, new_width, false); + Node y = + !is_right ? factory.logical_shift_left(a, b_truncated) : + !is_signed ? factory.logical_shift_right(a, b_truncated) : + factory.arithmetic_shift_right(a, b_truncated); + if(b.width() <= new_width) + return y; + Node overflow = factory.unsigned_greater_equal(b, factory.constant(RTLIL::Const(a.width(), b.width()))); + Node y_if_overflow = is_signed ? factory.extend(sign(a), a.width(), true) : factory.constant(RTLIL::Const(State::S0, a.width())); + return factory.mux(y, y_if_overflow, overflow); + } public: - Node logical_shift_left(Node a, Node b) { - Node reduced_b = reduce_shift_width(b, a.width()); - return factory.logical_shift_left(a, reduced_b); - } - Node logical_shift_right(Node a, Node b) { - Node reduced_b = reduce_shift_width(b, a.width()); - return factory.logical_shift_right(a, reduced_b); - } - Node arithmetic_shift_right(Node a, Node b) { - Node reduced_b = reduce_shift_width(b, a.width()); - return factory.arithmetic_shift_right(a, reduced_b); - } + Node logical_shift_left(Node a, Node b) { return handle_shift(a, b, false, false); } + Node logical_shift_right(Node a, Node b) { return handle_shift(a, b, true, false); } + Node arithmetic_shift_right(Node a, Node b) { return handle_shift(a, b, true, true); } Node bitwise_mux(Node a, Node b, Node s) { Node aa = factory.bitwise_and(a, factory.bitwise_not(s)); Node bb = factory.bitwise_and(b, s); @@ -348,7 +348,7 @@ public: int width = parameters.at(ID(WIDTH)).as_int(); int s_width = parameters.at(ID(S_WIDTH)).as_int(); int y_width = width << s_width; - int b_width = ceil_log2(y_width + 1); + int b_width = ceil_log2(y_width); Node a = factory.extend(inputs.at(ID(A)), y_width, false); Node s = factory.extend(inputs.at(ID(S)), b_width, false); Node b = factory.mul(s, factory.constant(Const(width, b_width))); diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 44e3589db..0559eae89 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -109,13 +109,13 @@ public: // unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b) unsigned_greater_equal, // logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b - // required: M <= clog2(N + 1) + // required: M == clog2(N) logical_shift_left, // logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b - // required: M <= clog2(N + 1) + // required: M == clog2(N) logical_shift_right, // arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b - // required: M <= clog2(N + 1) + // required: M == clog2(N) arithmetic_shift_right, // mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a mux, @@ -373,6 +373,8 @@ public: friend class FunctionalIR; explicit Factory(FunctionalIR &ir) : _ir(ir) {} Node add(NodeData &&fn, Sort &&sort, std::initializer_list args) { + log_assert(!sort.is_signal() || sort.width() > 0); + log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0); Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); for (auto arg : args) ref.append_arg(Graph::ConstRef(arg)); @@ -382,7 +384,7 @@ public: return _ir._graph[n._ref.index()]; } void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } - void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal()); } + void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); } void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } public: Node slice(Node a, int offset, int out_width) { diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index b4c0ad1c1..7858e3781 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -206,7 +206,10 @@ shift_widths = [ (32, 32, 64, True, True), (32, 32, 64, False, True), # at least one test where the result is going to be truncated - (32, 6, 16, False, False) + (32, 6, 16, False, False), + # since 1-bit shifts are special cased + (1, 4, 1, False, False), + (1, 4, 1, True, False), ] rtlil_cells = [ From 13bacc5c8f77fc98cf20d3d2c67d1f5dee1c84a6 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 17 Jul 2024 13:35:58 +0100 Subject: [PATCH 139/342] eliminate pmux in functional backend --- backends/functional/cxx.cc | 1 - backends/functional/cxx_runtime/sim.h | 19 ------------------- backends/functional/smtlib.cc | 6 ------ kernel/functionalir.cc | 11 +++++++++-- kernel/functionalir.h | 12 ------------ 5 files changed, 9 insertions(+), 40 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 920ccf363..0fa310164 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -136,7 +136,6 @@ template struct CxxPrintVisitor : public FunctionalIR::Abstra void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); } void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); } void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); } - void pmux(Node, Node a, Node b, Node s) override { print("{0}.pmux({1}, {2})", a, b, s); } void constant(Node, RTLIL::Const value) override { std::stringstream ss; bool multiple = value.size() > 32; diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index 950d4c5e1..ed1a25ed4 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -368,25 +368,6 @@ public: return ret; } - template - Signal pmux(Signal const &b, Signal const &s) const - { - bool found; - Signal ret; - - found = false; - ret = *this; - for(size_t i = 0; i < ns; i++){ - if(s._bits[i]){ - if(found) - return 0; - found = true; - ret = b.template slice(n * i); - } - } - return ret; - } - template Signal concat(Signal const& b) const { diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index c35a48dd8..a2bb6666c 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -174,12 +174,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); } - SExpr pmux(Node, Node a, Node b, Node s) override { - SExpr rv = n(a); - for(int i = 0; i < s.width(); i++) - rv = list("ite", to_bool(extract(n(s), i)), extract(n(b), a.width() * i, a.width()), rv); - return rv; - } SExpr constant(Node, RTLIL::Const value) override { return literal(value); } SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); } SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); } diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index ddd821ada..4b2ad8c0b 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -52,7 +52,6 @@ const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) { case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right"; case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right"; case FunctionalIR::Fn::mux: return "mux"; - case FunctionalIR::Fn::pmux: return "pmux"; case FunctionalIR::Fn::constant: return "constant"; case FunctionalIR::Fn::input: return "input"; case FunctionalIR::Fn::state: return "state"; @@ -165,6 +164,14 @@ private: return factory.mux(y0, y1, factory.slice(s, sn - 1, 1)); } } + Node handle_pmux(Node a, Node b, Node s) { + // TODO : what to do about multiple b bits set ? + log_assert(b.width() == a.width() * s.width()); + Node y = a; + for(int i = 0; i < s.width(); i++) + y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1)); + return y; + } public: Node handle(IdString cellType, dict parameters, dict inputs) { @@ -266,7 +273,7 @@ public: }else if(cellType == ID($mux)){ return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); }else if(cellType == ID($pmux)){ - return factory.pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); + return handle_pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); }else if(cellType == ID($concat)){ Node a = inputs.at(ID(A)); Node b = inputs.at(ID(B)); diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 0559eae89..d0ec1bce6 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -119,11 +119,6 @@ public: arithmetic_shift_right, // mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a mux, - // pmux(a: bit[N], b: bit[N*M], s: bit[M]): bit[N] - // required: no more than one bit in b is set - // if s[i] = 1 for any i, then returns b[i * N +: N] - // returns a if s == 0 - pmux, // constant(a: Const[N]): bit[N] = a constant, // input(a: IdString): any @@ -277,7 +272,6 @@ public: case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break; case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break; - case Fn::pmux: return v.pmux(*this, arg(0), arg(1), arg(2)); break; case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; @@ -320,7 +314,6 @@ public: virtual T logical_shift_right(Node self, Node a, Node b) = 0; virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; virtual T mux(Node self, Node a, Node b, Node s) = 0; - virtual T pmux(Node self, Node a, Node b, Node s) = 0; virtual T constant(Node self, RTLIL::Const value) = 0; virtual T input(Node self, IdString name) = 0; virtual T state(Node self, IdString name) = 0; @@ -359,7 +352,6 @@ public: T logical_shift_right(Node self, Node, Node) override { return default_handler(self); } T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } T mux(Node self, Node, Node, Node) override { return default_handler(self); } - T pmux(Node self, Node, Node, Node) override { return default_handler(self); } T constant(Node self, RTLIL::Const) override { return default_handler(self); } T input(Node self, IdString) override { return default_handler(self); } T state(Node self, IdString) override { return default_handler(self); } @@ -451,10 +443,6 @@ public: log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1)); return add(Fn::mux, a.sort(), {a, b, s}); } - Node pmux(Node a, Node b, Node s) { - log_assert(a.sort().is_signal() && b.sort().is_signal() && s.sort().is_signal() && a.sort().width() * s.sort().width() == b.sort().width()); - return add(Fn::pmux, a.sort(), {a, b, s}); - } Node memory_read(Node mem, Node addr) { log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width()); return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr}); From 3cd5f4ed83413cf4df695217ff85e3190ae4a8c7 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 17 Jul 2024 16:33:34 +0100 Subject: [PATCH 140/342] add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu --- kernel/functionalir.cc | 123 ++++++++++++++++++++++------ tests/functional/rtlil_cells.py | 21 ++++- tests/functional/test_functional.py | 8 +- 3 files changed, 118 insertions(+), 34 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 4b2ad8c0b..e768be400 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -18,6 +18,7 @@ */ #include "kernel/functionalir.h" +#include YOSYS_NAMESPACE_BEGIN @@ -172,8 +173,38 @@ private: y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1)); return y; } + dict handle_fa(Node a, Node b, Node c) { + Node t1 = factory.bitwise_xor(a, b); + Node t2 = factory.bitwise_and(a, b); + Node t3 = factory.bitwise_and(c, t1); + Node y = factory.bitwise_xor(c, t1); + Node x = factory.bitwise_or(t2, t3); + return {{ID(X), x}, {ID(Y), y}}; + } + Node handle_lcu(Node p, Node g, Node ci) { + Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci)); + Node c = rv; + for(int i = 1; i < p.width(); i++) { + c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c)); + rv = factory.concat(rv, c); + } + return rv; + } + dict handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) { + Node a = factory.extend(a_in, y_width, is_signed); + Node b_uninverted = factory.extend(b_in, y_width, is_signed); + Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi); + Node x = factory.bitwise_xor(a, b); + Node a_extra = factory.extend(a, y_width + 1, false); + Node b_extra = factory.extend(b, y_width + 1, false); + Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false)); + Node y = factory.slice(y_extra, 0, y_width); + Node carries = factory.bitwise_xor(y_extra, factory.bitwise_xor(a_extra, b_extra)); + Node co = factory.slice(carries, 1, y_width); + return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}}; + } public: - Node handle(IdString cellType, dict parameters, dict inputs) + std::variant, Node> handle(IdString cellType, dict parameters, dict inputs) { int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); @@ -360,17 +391,23 @@ public: Node s = factory.extend(inputs.at(ID(S)), b_width, false); Node b = factory.mul(s, factory.constant(Const(width, b_width))); return factory.logical_shift_left(a, b); + } else if(cellType == ID($fa)) { + return handle_fa(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(C))); + } else if(cellType == ID($lcu)) { + return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI))); + } else if(cellType == ID($alu)) { + return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI))); } else { - log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str()); } } }; class FunctionalIRConstruction { using Node = FunctionalIR::Node; - std::deque queue; + std::deque> queue; dict graph_nodes; - idict cells; + dict, Node> cell_outputs; DriverMap driver_map; FunctionalIR::Factory& factory; CellSimplifier simplifier; @@ -388,6 +425,24 @@ class FunctionalIRConstruction { }else return it->second; } + Node enqueue_cell(Cell *cell, IdString port_name) + { + auto it = cell_outputs.find({cell, port_name}); + if(it == cell_outputs.end()) { + queue.emplace_back(cell); + std::optional rv; + for(auto const &[name, sigspec] : cell->connections()) + if(driver_map.celltypes.cell_output(cell->type, name)) { + auto node = factory.create_pending(sigspec.size()); + factory.suggest_name(node, cell->name.str() + "$" + name.str()); + cell_outputs.emplace({cell, name}, node); + if(name == port_name) + rv = node; + } + return *rv; + } else + return it->second; + } public: FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {} void add_module(Module *module) @@ -395,7 +450,7 @@ public: driver_map.add(module); for (auto cell : module->cells()) { if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) - enqueue(DriveBitMarker(cells(cell), 0)); + queue.emplace_back(cell); } for (auto wire : module->wires()) { if (wire->port_output) { @@ -441,10 +496,44 @@ public: factory.declare_state_memory(node, mem->cell->name, addr_width, data_width); return concatenate_read_results(mem, read_results); } + void process_cell(Cell *cell) + { + if (cell->is_mem_cell()) { + Mem *mem = memories.at(cell, nullptr); + log_assert(mem != nullptr); + Node node = handle_memory(mem); + factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); + } else { + dict connections; + IdString output_name; // for the single output case + int n_outputs = 0; + for(auto const &[name, sigspec] : cell->connections()) { + if(driver_map.celltypes.cell_input(cell->type, name)) + connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) }); + if(driver_map.celltypes.cell_output(cell->type, name)) { + output_name = name; + n_outputs++; + } + } + std::variant, Node> outputs = simplifier.handle(cell->type, cell->parameters, connections); + if(auto *nodep = std::get_if(&outputs); nodep != nullptr) { + log_assert(n_outputs == 1); + factory.update_pending(cell_outputs.at({cell, output_name}), *nodep); + } else { + for(auto [name, node] : std::get>(outputs)) + factory.update_pending(cell_outputs.at({cell, name}), node); + } + } + } void process_queue() { for (; !queue.empty(); queue.pop_front()) { - DriveSpec spec = queue.front(); + if(auto p = std::get_if(&queue.front()); p != nullptr) { + process_cell(*p); + continue; + } + + DriveSpec spec = std::get(queue.front()); Node pending = graph_nodes.at(spec); if (spec.chunks().size() > 1) { @@ -492,11 +581,7 @@ public: } else { - Node cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width)); - factory.suggest_name(cell, port_chunk.cell->name); - //Node node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width); - Node node = cell; - factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str()); + Node node = enqueue_cell(port_chunk.cell, port_chunk.port); factory.update_pending(pending, node); } } else { @@ -518,22 +603,6 @@ public: args.push_back(enqueue(driver)); Node node = factory.multiple(args, chunk.size()); factory.update_pending(pending, node); - } else if (chunk.is_marker()) { - Cell *cell = cells[chunk.marker().marker]; - if (cell->is_mem_cell()) { - Mem *mem = memories.at(cell, nullptr); - log_assert(mem != nullptr); - Node node = handle_memory(mem); - factory.update_pending(pending, node); - } else { - dict connections; - for(auto const &conn : cell->connections()) { - if(driver_map.celltypes.cell_input(cell->type, conn.first)) - connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) }); - } - Node node = simplifier.handle(cell->type, cell->parameters, connections); - factory.update_pending(pending, node); - } } else if (chunk.is_none()) { Node node = factory.undriven(chunk.size()); factory.update_pending(pending, node); diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index 7858e3781..4dbea6015 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -123,6 +123,21 @@ class SliceCell(BaseCell): def __init__(self, name, values): super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values) +class FACell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'C': 'WIDTH'}, {'X': 'WIDTH', 'Y': 'WIDTH'}, values) + self.sim_preprocessing = "techmap" # because FA is not implemented in yosys sim + +class LCUCell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['WIDTH'], {'P': 'WIDTH', 'G': 'WIDTH', 'CI': 1}, {'CO': 'WIDTH'}, values) + self.sim_preprocessing = "techmap" # because LCU is not implemented in yosys sim + +class ALUCell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH', 'CI': 1, 'BI': 1}, {'X': 'Y_WIDTH', 'Y': 'Y_WIDTH', 'CO': 'Y_WIDTH'}, values) + self.sim_preprocessing = "techmap" # because ALU is not implemented in yosys sim + class FailCell(BaseCell): def __init__(self, name): super().__init__(name, [], {}, {}) @@ -231,9 +246,9 @@ rtlil_cells = [ ShiftCell("sshr", shift_widths), ShiftCell("shift", shift_widths), ShiftCell("shiftx", shift_widths), -# ("fa", ["A", "B", "C", "X", "Y"]), -# ("lcu", ["P", "G", "CI", "CO"]), -# ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]), + FACell("fa", [8, 20]), + LCUCell("lcu", [1, 10]), + ALUCell("alu", binary_widths), BinaryCell("lt", binary_widths), BinaryCell("le", binary_widths), BinaryCell("eq", binary_widths), diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 86e515d90..150642a00 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -27,9 +27,9 @@ def yosys_synth(verilog_file, rtlil_file): yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file -def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file): +def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): try: - yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold") + yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold") except: # if yosys sim fails it's probably because of a simulation mismatch # since yosys sim aborts on simulation mismatch to generate vcd output @@ -53,7 +53,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd): compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')]) seed = str(rnd(cell.name + "-cxx").getrandbits(32)) run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)]) - yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file) + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) def test_smt(cell, parameters, tmp_path, num_steps, rnd): import smt_vcd @@ -67,4 +67,4 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}") run(['z3', smt_file]) # check if output is valid smtlib before continuing smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) - yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file) \ No newline at end of file + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) \ No newline at end of file From 4722f13a5d917d2c464ef74de7facabd85fc63aa Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 18 Jul 2024 07:50:49 +0100 Subject: [PATCH 141/342] functional backend: reduce $lcu to $alu --- kernel/functionalir.cc | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index e768be400..778b6a825 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -181,20 +181,14 @@ private: Node x = factory.bitwise_or(t2, t3); return {{ID(X), x}, {ID(Y), y}}; } - Node handle_lcu(Node p, Node g, Node ci) { - Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci)); - Node c = rv; - for(int i = 1; i < p.width(); i++) { - c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c)); - rv = factory.concat(rv, c); - } - return rv; - } dict handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) { Node a = factory.extend(a_in, y_width, is_signed); Node b_uninverted = factory.extend(b_in, y_width, is_signed); Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi); Node x = factory.bitwise_xor(a, b); + // we can compute the carry into each bit using (a+b+c)^a^b. since we want the carry out, + // i.e. the carry into the next bit, we have to add an extra bit to a and b, and + // then slice off the bottom bit of the result. Node a_extra = factory.extend(a, y_width + 1, false); Node b_extra = factory.extend(b, y_width + 1, false); Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false)); @@ -203,6 +197,9 @@ private: Node co = factory.slice(carries, 1, y_width); return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}}; } + Node handle_lcu(Node p, Node g, Node ci) { + return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO)); + } public: std::variant, Node> handle(IdString cellType, dict parameters, dict inputs) { From 145af6f10dd38441f0b549bfcd7547b7e749b8bb Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 18 Jul 2024 14:10:15 +0100 Subject: [PATCH 142/342] fix memory handling in functional backend, add more error messages and comments for memory edgecases --- kernel/functionalir.cc | 52 +++++++++++++++++++++++------ tests/functional/rtlil_cells.py | 45 +++++++++++++++++++++++-- tests/functional/test_functional.py | 6 ++-- 3 files changed, 86 insertions(+), 17 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 778b6a825..f6d2f5560 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -461,11 +461,19 @@ public: memories[mem.cell] = &mem; } } - Node concatenate_read_results(Mem *, vector results) + Node concatenate_read_results(Mem *mem, vector results) { - /* TODO: write code to check that this is ok to do */ - if(results.size() == 0) - return factory.undriven(0); + // sanity check: all read ports concatenated should equal to the RD_DATA port + const SigSpec &rd_data = mem->cell->connections().at(ID(RD_DATA)); + int current = 0; + for(size_t i = 0; i < mem->rd_ports.size(); i++) { + int width = mem->width << mem->rd_ports[i].wide_log2; + log_assert (results[i].width() == width); + log_assert (mem->rd_ports[i].data == rd_data.extract(current, width)); + current += width; + } + log_assert (current == rd_data.size()); + log_assert (!results.empty()); Node node = results[0]; for(size_t i = 1; i < results.size(); i++) node = factory.concat(node, results[i]); @@ -473,16 +481,23 @@ public: } Node handle_memory(Mem *mem) { + // To simplify memory handling, the functional backend makes the following assumptions: + // - Since async2sync or clk2fflogic must be run to use the functional backend, + // we can assume that all ports are asynchronous. + // - Async rd/wr are always transparent and so we must do reads after writes, + // but we can ignore transparency_mask. + // - We ignore collision_x_mask because x is a dont care value for us anyway. + // - Since wr port j can only have priority over wr port i if j > i, if we do writes in + // ascending index order the result will obey the priorty relation. vector read_results; int addr_width = ceil_log2(mem->size); int data_width = mem->width; Node node = factory.state_memory(mem->cell->name, addr_width, data_width); - for (auto &rd : mem->rd_ports) { - log_assert(!rd.clk_enable); - Node addr = enqueue(driver_map(DriveSpec(rd.addr))); - read_results.push_back(factory.memory_read(node, addr)); - } - for (auto &wr : mem->wr_ports) { + for (size_t i = 0; i < mem->wr_ports.size(); i++) { + const auto &wr = mem->wr_ports[i]; + if (wr.clk_enable) + log_error("Write port %zd of memory %s.%s is clocked. This is not supported by the functional backend. " + "Call async2sync or clk2fflogic to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid)); Node en = enqueue(driver_map(DriveSpec(wr.en))); Node addr = enqueue(driver_map(DriveSpec(wr.addr))); Node new_data = enqueue(driver_map(DriveSpec(wr.data))); @@ -490,6 +505,17 @@ public: Node wr_data = simplifier.bitwise_mux(old_data, new_data, en); node = factory.memory_write(node, addr, wr_data); } + if (mem->rd_ports.empty()) + log_error("Memory %s.%s has no read ports. This is not supported by the functional backend. " + "Call opt_clean to remove it.", log_id(mem->module), log_id(mem->memid)); + for (size_t i = 0; i < mem->rd_ports.size(); i++) { + const auto &rd = mem->rd_ports[i]; + if (rd.clk_enable) + log_error("Read port %zd of memory %s.%s is clocked. This is not supported by the functional backend. " + "Call memory_nordff to avoid this error.\n", i, log_id(mem->module), log_id(mem->memid)); + Node addr = enqueue(driver_map(DriveSpec(rd.addr))); + read_results.push_back(factory.memory_read(node, addr)); + } factory.declare_state_memory(node, mem->cell->name, addr_width, data_width); return concatenate_read_results(mem, read_results); } @@ -497,7 +523,11 @@ public: { if (cell->is_mem_cell()) { Mem *mem = memories.at(cell, nullptr); - log_assert(mem != nullptr); + if (mem == nullptr) { + log_assert(cell->has_memid()); + log_error("The design contains an unpacked memory at %s. This is not supported by the functional backend. " + "Call memory_collect to avoid this error.\n", log_const(cell->parameters.at(ID(MEMID)))); + } Node node = handle_memory(mem); factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); } else { diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index 4dbea6015..90417579e 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -176,14 +176,52 @@ module gold( input wire clk, input wire [{1}:0] WA, input wire [{0}:0] WD, + input wire [{1}:0] RA, output reg [{0}:0] RD ); - reg [{0}:0] mem[0:{1}]; + reg [{0}:0] mem[0:{2}]; always @(*) RD = mem[RA]; always @(posedge clk) mem[WA] <= WD; -endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1)) +endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1)) + yosys_synth(verilog_file, path) + +class MemDualCell(BaseCell): + def __init__(self, name, values): + super().__init__(name, ['DATA_WIDTH', 'ADDR_WIDTH'], + {'WA1': 'ADDR_WIDTH', 'WA2': 'ADDR_WIDTH', + 'RA1': 'ADDR_WIDTH', 'RA2': 'ADDR_WIDTH', + 'WD1': 'DATA_WIDTH', 'WD2': 'DATA_WIDTH'}, + {'RD1': 'DATA_WIDTH', 'RD2': 'DATA_WIDTH'}, values) + self.sim_preprocessing = "memory_map" # issue #4496 in yosys -sim prevents this example from working without memory_map + def write_rtlil_file(self, path, parameters): + from test_functional import yosys_synth + verilog_file = path.parent / 'verilog.v' + with open(verilog_file, 'w') as f: + f.write(""" +module gold( + input wire clk, + input wire [{1}:0] WA1, + input wire [{0}:0] WD1, + input wire [{1}:0] WA2, + input wire [{0}:0] WD2, + input wire [{1}:0] RA1, + input wire [{1}:0] RA2, + output reg [{0}:0] RD1, + output reg [{0}:0] RD2 +); + (*keep*) + reg [{0}:0] mem[0:{2}]; + always @(*) + RD1 = mem[RA1]; + always @(*) + RD2 = mem[RA2]; + always @(posedge clk) begin + mem[WA1] <= WD1; + mem[WA2] <= WD2; + end +endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1)) yosys_synth(verilog_file, path) binary_widths = [ @@ -284,7 +322,8 @@ rtlil_cells = [ BWCell("bweqx", [10, 16, 40]), BWCell("bwmux", [10, 16, 40]), FFCell("ff", [10, 20, 40]), - MemCell("mem", [(32, 4)]) + MemCell("mem", [(16, 4)]), + MemDualCell("mem-dual", [(16, 4)]), # ("assert", ["A", "EN"]), # ("assume", ["A", "EN"]), # ("live", ["A", "EN"]), diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 150642a00..c31f4b86f 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args): run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)]) def yosys_synth(verilog_file, rtlil_file): - yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}") + yosys(f"read_verilog {quote(verilog_file)} ; prep ; write_rtlil {quote(rtlil_file)}") # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): @@ -49,7 +49,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd): vcd_yosys_sim_file = tmp_path / 'yosys.vcd' cell.write_rtlil_file(rtlil_file, parameters) - yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_cxx {quote(cc_file)}") + yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_cxx {quote(cc_file)}") compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')]) seed = str(rnd(cell.name + "-cxx").getrandbits(32)) run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)]) @@ -64,7 +64,7 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): vcd_yosys_sim_file = tmp_path / 'yosys.vcd' cell.write_rtlil_file(rtlil_file, parameters) - yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}") + yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}") run(['z3', smt_file]) # check if output is valid smtlib before continuing smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) \ No newline at end of file From 6d329e142dbe16edfe772864a5c9debc72896e0f Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 18 Jul 2024 14:23:00 +0100 Subject: [PATCH 143/342] functional backend: error out if multiply driven or undriven signals are seen, dont bother putting them in functionalir --- backends/functional/cxx.cc | 1 - backends/functional/smtlib.cc | 5 +---- kernel/functionalir.cc | 14 ++++---------- kernel/functionalir.h | 19 ------------------- 4 files changed, 5 insertions(+), 34 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 0fa310164..69f1973f2 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -154,7 +154,6 @@ template struct CxxPrintVisitor : public FunctionalIR::Abstra void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); } void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); } void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); } - void undriven(Node, int width) override { print("Signal<{}>(0)", width); } }; struct CxxModule { diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index a2bb6666c..d40a4489f 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -180,8 +180,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); } SExpr state(Node, IdString name) override { return state_struct.access("state", name); } - - SExpr undriven(Node, int width) override { return literal(RTLIL::Const(State::S0, width)); } }; struct SmtModule { @@ -227,8 +225,7 @@ struct SmtModule { list("state", state_struct.name)), list("Pair", output_struct.name, state_struct.name))); auto inlined = [&](FunctionalIR::Node n) { - return n.fn() == FunctionalIR::Fn::constant || - n.fn() == FunctionalIR::Fn::undriven; + return n.fn() == FunctionalIR::Fn::constant; }; SmtPrintVisitor visitor(input_struct, state_struct); auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr { diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index f6d2f5560..155cb3bbc 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -56,8 +56,6 @@ const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) { case FunctionalIR::Fn::constant: return "constant"; case FunctionalIR::Fn::input: return "input"; case FunctionalIR::Fn::state: return "state"; - case FunctionalIR::Fn::multiple: return "multiple"; - case FunctionalIR::Fn::undriven: return "undriven"; case FunctionalIR::Fn::memory_read: return "memory_read"; case FunctionalIR::Fn::memory_write: return "memory_write"; } @@ -75,7 +73,6 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor { std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; } std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; } std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; } - std::string undriven(Node, int width) override { return "undriven(" + std::to_string(width) + ")"; } std::string default_handler(Node self) override { std::string ret = FunctionalIR::fn_to_string(self.fn()); ret += "("; @@ -625,14 +622,11 @@ public: factory.suggest_name(node, "$const" + std::to_string(chunk.size()) + "b" + chunk.constant().as_string()); factory.update_pending(pending, node); } else if (chunk.is_multiple()) { - vector args; - for (auto const &driver : chunk.multiple().multiple()) - args.push_back(enqueue(driver)); - Node node = factory.multiple(args, chunk.size()); - factory.update_pending(pending, node); + log_error("Signal %s has multiple drivers. This is not supported by the functional backend. " + "If tristate drivers are used, call tristate -formal to avoid this error.\n", log_signal(chunk)); } else if (chunk.is_none()) { - Node node = factory.undriven(chunk.size()); - factory.update_pending(pending, node); + log_error("The design contains an undriven signal %s. This is not supported by the functional backend. " + "Call setundef with appropriate options to avoid this error.\n", log_signal(chunk)); } else { log_error("unhandled drivespec: %s\n", log_signal(chunk)); log_abort(); diff --git a/kernel/functionalir.h b/kernel/functionalir.h index d0ec1bce6..852937612 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -127,12 +127,6 @@ public: // state(a: IdString): any // returns the current value of the state variable with the specified name state, - // multiple(a: any, b: any, c: any, ...): any - // indicates a value driven by multiple inputs - multiple, - // undriven(width: int): bit[width] - // indicates an undriven value - undriven, // memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr] memory_read, // memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width] @@ -277,8 +271,6 @@ public: case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; - case Fn::multiple: log_error("multiple in visit"); break; - case Fn::undriven: return v.undriven(*this, width()); break; } } std::string to_string(); @@ -319,7 +311,6 @@ public: virtual T state(Node self, IdString name) = 0; virtual T memory_read(Node self, Node mem, Node addr) = 0; virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; - virtual T undriven(Node self, int width) = 0; }; // DefaultVisitor provides defaults for all visitor methods which just calls default_handler template struct DefaultVisitor : public AbstractVisitor { @@ -357,7 +348,6 @@ public: T state(Node self, IdString) override { return default_handler(self); } T memory_read(Node self, Node, Node) override { return default_handler(self); } T memory_write(Node self, Node, Node, Node) override { return default_handler(self); } - T undriven(Node self, int) override { return default_handler(self); } }; // a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes. class Factory { @@ -475,15 +465,6 @@ public: _ir.add_state(name, Sort(addr_width, data_width)); return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {}); } - Node multiple(vector args, int width) { - auto node = add(Fn::multiple, Sort(width), {}); - for(const auto &arg : args) - mutate(node).append_arg(arg._ref); - return node; - } - Node undriven(int width) { - return add(Fn::undriven, Sort(width), {}); - } void declare_output(Node node, IdString name, int width) { _ir.add_output(name, Sort(width)); mutate(node).assign_key({name, false}); From 12a31a4418d5fcc33c93cef192fc3066ab999f86 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 24 Jul 2024 17:23:18 +0100 Subject: [PATCH 144/342] add MemContents class to mem.h --- kernel/mem.cc | 216 ++++++++++++++++++++++++++++++++++++++++++++++++++ kernel/mem.h | 116 +++++++++++++++++++++++++++ 2 files changed, 332 insertions(+) diff --git a/kernel/mem.cc b/kernel/mem.cc index 01c866770..46e4331c5 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -1679,3 +1679,219 @@ SigSpec MemWr::decompress_en(const std::vector &swizzle, SigSpec sig) { res.append(sig[i]); return res; } + +using addr_t = MemContents::addr_t; + +MemContents::MemContents(Mem *mem) : + MemContents(ceil_log2(mem->size), mem->width) +{ + for(const auto &init : mem->inits) { + if(init.en.is_fully_zero()) continue; + log_assert(init.en.size() == _data_width); + if(init.en.is_fully_ones()) + insert_concatenated(init.addr.as_int(), init.data); + else { + // TODO: this case could be handled more efficiently by adding + // a flag to reserve_range that tells it to preserve + // previous contents + addr_t addr = init.addr.as_int(); + addr_t words = init.data.size() / _data_width; + RTLIL::Const data = init.data; + log_assert(data.size() % _data_width == 0); + for(addr_t i = 0; i < words; i++) { + RTLIL::Const previous = (*this)[addr + i]; + for(int j = 0; j < _data_width; j++) + if(init.en[j] != State::S1) + data[_data_width * i + j] = previous[j]; + } + insert_concatenated(init.addr.as_int(), data); + } + } +} + +MemContents::iterator & MemContents::iterator::operator++() { + auto it = _memory->_values.upper_bound(_addr); + if(it == _memory->_values.end()) { + _memory = nullptr; + _addr = ~(addr_t) 0; + } else + _addr = it->first; + return *this; +} + +void MemContents::check() { + log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); + log_assert(_data_width > 0); + log_assert(_default_value.size() == _data_width); + if(_values.empty()) return; + auto it = _values.begin(); + for(;;) { + log_assert(!it->second.empty()); + log_assert(it->second.size() % _data_width == 0); + auto end1 = _range_end(it); + log_assert(_range_begin(it) < (1<<_addr_width)); + log_assert(end1 <= (1<<_addr_width)); + if(++it == _values.end()) + break; + // check that ranges neither overlap nor touch + log_assert(_range_begin(it) > end1); + } +} + +bool MemContents::_range_contains(std::map::iterator it, addr_t addr) const { + // if addr < begin, the subtraction will overflow, and the comparison will always fail + // (since we have an invariant that begin + size <= 2^(addr_t bits)) + return it != _values.end() && addr - _range_begin(it) < _range_size(it); +} + + +bool MemContents::_range_contains(std::map::iterator it, addr_t begin_addr, addr_t end_addr) const { + // note that we assume begin_addr <= end_addr + return it != _values.end() && _range_begin(it) <= begin_addr && end_addr - _range_begin(it) <= _range_size(it); +} + +bool MemContents::_range_overlaps(std::map::iterator it, addr_t begin_addr, addr_t end_addr) const { + if(it == _values.end() || begin_addr >= end_addr) + return false; + auto top1 = _range_end(it) - 1; + auto top2 = end_addr - 1; + return !(top1 < begin_addr || top2 < _range_begin(it)); +} + +std::map::iterator MemContents::_range_at(addr_t addr) const { + // allow addr == 1<<_addr_width (which will just return end()) + log_assert(addr <= 1<<_addr_width); + // get the first range with base > addr + // (we use const_cast since map::iterators are only passed around internally and not exposed to the user + // and using map::iterator in both the const and non-const case simplifies the code a little, + // at the cost of having to be a little careful when implementing const methods) + auto it = const_cast &>(_values).upper_bound(addr); + // if we get the very first range, all ranges are past the addr, so return the first one + if(it == _values.begin()) + return it; + // otherwise, go back to the previous interval + // this must be the last interval with base <= addr + auto it_prev = std::next(it, -1); + if(_range_contains(it_prev, addr)) + return it_prev; + else + return it; +} + +RTLIL::Const MemContents::operator[](addr_t addr) const { + auto it = _range_at(addr); + if(_range_contains(it, addr)) + return it->second.extract(_range_offset(it, addr), _data_width); + else + return _default_value; +} + +addr_t MemContents::count_range(addr_t begin_addr, addr_t end_addr) const { + addr_t count = 0; + for(auto it = _range_at(begin_addr); _range_overlaps(it, begin_addr, end_addr); it++) { + auto first = std::max(_range_begin(it), begin_addr); + auto last = std::min(_range_end(it), end_addr); + count += last - first; + } + return count; +} + +void MemContents::clear_range(addr_t begin_addr, addr_t end_addr) { + if(begin_addr >= end_addr) return; + // identify which ranges are affected by this operation + // the first iterator affected is the first one containing any addr >= begin_addr + auto begin_it = _range_at(begin_addr); + // the first iterator *not* affected is the first one with base addr > end_addr - 1 + auto end_it = _values.upper_bound(end_addr - 1); + if(begin_it == end_it) + return; // nothing to do + // the last iterator affected is one before the first one not affected + auto last_it = std::next(end_it, -1); + // the first and last range may need to be truncated, the rest can just be deleted + // to handle the begin_it == last_it case correctly, do the end case first by inserting a new range past the end + if(_range_contains(last_it, end_addr - 1)) { + auto new_begin = end_addr; + auto end = _range_end(last_it); + // if there is data past the end address, preserve it by creating a new range + if(new_begin != end) + end_it = _values.emplace_hint(last_it, new_begin, last_it->second.extract(_range_offset(last_it, new_begin), (_range_end(last_it) - new_begin) * _data_width)); + // the original range will either be truncated in the next if() block or deleted in the erase, so we can leave it untruncated + } + if(_range_contains(begin_it, begin_addr)) { + auto new_end = begin_addr; + // if there is data before the start address, truncate but don't delete + if(new_end != begin_it->first) { + begin_it->second.extu(_range_offset(begin_it, new_end)); + ++begin_it; + } + // else: begin_it will be deleted + } + _values.erase(begin_it, end_it); +} + +std::map::iterator MemContents::_reserve_range(addr_t begin_addr, addr_t end_addr) { + if(begin_addr >= end_addr) + return _values.end(); // need a dummy value to return, end() is cheap + // find the first range containing any addr >= begin_addr - 1 + auto lower_it = begin_addr == 0 ? _values.begin() : _range_at(begin_addr - 1); + // check if our range is already covered by a single range + // note that since ranges are not allowed to touch, if any range contains begin_addr, lower_it equals that range + if (_range_contains(lower_it, begin_addr, end_addr)) + return lower_it; + // find the first range containing any addr >= end_addr + auto upper_it = _range_at(end_addr); + // check if either of the two ranges we just found touch our range + bool lower_touch = begin_addr > 0 && _range_contains(lower_it, begin_addr - 1); + bool upper_touch = _range_contains(upper_it, end_addr); + if (lower_touch && upper_touch) { + log_assert (lower_it != upper_it); // lower_it == upper_it should be excluded by the check above + // we have two different ranges touching at either end, we need to merge them + auto upper_end = _range_end(upper_it); + // make range bigger (maybe reserve here instead of resize?) + lower_it->second.bits.resize(_range_offset(lower_it, upper_end), State::Sx); + // copy only the data beyond our range + std::copy(_range_data(upper_it, end_addr), _range_data(upper_it, upper_end), _range_data(lower_it, end_addr)); + // keep lower_it, but delete upper_it + _values.erase(std::next(lower_it), std::next(upper_it)); + return lower_it; + } else if (lower_touch) { + // we have a range to the left, just make it bigger and delete any other that may exist. + lower_it->second.bits.resize(_range_offset(lower_it, end_addr), State::Sx); + // keep lower_it and upper_it + _values.erase(std::next(lower_it), upper_it); + return lower_it; + } else if (upper_touch) { + // we have a range to the right, we need to expand it + // since we need to erase and reinsert to a new address, steal the data + RTLIL::Const data = std::move(upper_it->second); + // note that begin_addr is not in upper_it, otherwise the whole range covered check would have tripped + data.bits.insert(data.bits.begin(), (_range_begin(upper_it) - begin_addr) * _data_width, State::Sx); + // delete lower_it and upper_it, then reinsert + _values.erase(lower_it, std::next(upper_it)); + return _values.emplace(begin_addr, std::move(data)).first; + } else { + // no ranges are touching, so just delete all ranges in our range and allocate a new one + // could try to resize an existing range but not sure if that actually helps + _values.erase(lower_it, upper_it); + return _values.emplace(begin_addr, RTLIL::Const(State::Sx, (end_addr - begin_addr) * _data_width)).first; + } +} + +void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) { + addr_t words = (values.size() + _data_width - 1) / _data_width; + log_assert(addr < 1<<_addr_width); + log_assert(words <= (1<<_addr_width) - addr); + auto it = _reserve_range(addr, addr + words); + auto to_begin = _range_data(it, addr); + std::copy(values.bits.begin(), values.bits.end(), to_begin); + // if values is not word-aligned, fill any missing bits with 0 + std::fill(to_begin + values.size(), to_begin + words * _data_width, State::S0); +} + +std::vector::iterator MemContents::_range_write(std::vector::iterator it, RTLIL::Const const &word) { + auto from_end = word.size() <= _data_width ? word.bits.end() : word.bits.begin() + _data_width; + auto to_end = std::copy(word.bits.begin(), from_end, it); + auto it_next = std::next(it, _data_width); + std::fill(to_end, it_next, State::S0); + return it_next; +} \ No newline at end of file diff --git a/kernel/mem.h b/kernel/mem.h index 8c484274c..4be4b6864 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -224,6 +224,122 @@ struct Mem : RTLIL::AttrObject { Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {} }; +// this class is used for implementing operator-> on iterators that return values rather than references +// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained +template +struct arrow_proxy { + T v; + explicit arrow_proxy(T const & v) : v(v) {} + T* operator->() { return &v; } +}; + +// MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined +class MemContents { +public: + class range; class iterator; + using addr_t = uint32_t; +private: + // we ban _addr_width == sizeof(addr_t) * 8 because it adds too many cornercases + int _addr_width; + int _data_width; + RTLIL::Const _default_value; + // for each range, store the concatenation of the words at the start address + // invariants: + // - no overlapping or adjacent ranges + // - no empty ranges + // - all Consts are a multiple of the word size + std::map _values; + // returns an iterator to the range containing addr, if it exists, or the first range past addr + std::map::iterator _range_at(addr_t addr) const; + addr_t _range_size(std::map::iterator it) const { return it->second.size() / _data_width; } + addr_t _range_begin(std::map::iterator it) const { return it->first; } + addr_t _range_end(std::map::iterator it) const { return _range_begin(it) + _range_size(it); } + // check if the iterator points to a range containing addr + bool _range_contains(std::map::iterator it, addr_t addr) const; + // check if the iterator points to a range containing [begin_addr, end_addr). assumes end_addr >= begin_addr. + bool _range_contains(std::map::iterator it, addr_t begin_addr, addr_t end_addr) const; + // check if the iterator points to a range overlapping with [begin_addr, end_addr) + bool _range_overlaps(std::map::iterator it, addr_t begin_addr, addr_t end_addr) const; + // return the offset the addr would have in the range at `it` + size_t _range_offset(std::map::iterator it, addr_t addr) const { return (addr - it->first) * _data_width; } + // assuming _range_contains(it, addr), return an iterator pointing to the data at addr + std::vector::iterator _range_data(std::map::iterator it, addr_t addr) { return it->second.bits.begin() + _range_offset(it, addr); } + // internal version of reserve_range that returns an iterator to the range + std::map::iterator _reserve_range(addr_t begin_addr, addr_t end_addr); + // write a single word at addr, return iterator to next word + std::vector::iterator _range_write(std::vector::iterator it, RTLIL::Const const &data); +public: + class range { + int _data_width; + addr_t _base; + RTLIL::Const const &_values; + friend class iterator; + range(int data_width, addr_t base, RTLIL::Const const &values) + : _data_width(data_width), _base(base), _values(values) {} + public: + addr_t base() const { return _base; } + addr_t size() const { return ((addr_t) _values.size()) / _data_width; } + addr_t limit() const { return _base + size(); } + RTLIL::Const const &concatenated() const { return _values; } + RTLIL::Const operator[](addr_t addr) const { + log_assert(addr - _base < size()); + return _values.extract((addr - _base) * _data_width, _data_width); + } + RTLIL::Const at_offset(addr_t offset) const { return (*this)[_base + offset]; } + }; + class iterator { + MemContents const *_memory; + // storing addr instead of an iterator gives more well-defined behaviour under insertions/deletions + // use ~0 for end so that all end iterators compare the same + addr_t _addr; + friend class MemContents; + iterator(MemContents const *memory, addr_t addr) : _memory(memory), _addr(addr) {} + public: + using iterator_category = std::input_iterator_tag; + using value_type = range; + using pointer = arrow_proxy; + using reference = range; + using difference_type = addr_t; + reference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); } + pointer operator->() const { return arrow_proxy(**this); } + bool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; } + iterator &operator++(); + }; + MemContents(int addr_width, int data_width, RTLIL::Const default_value) + : _addr_width(addr_width), _data_width(data_width) + , _default_value((default_value.extu(data_width), std::move(default_value))) + { log_assert(_addr_width > 0 && _addr_width < (int)sizeof(addr_t) * 8); log_assert(_data_width > 0); } + MemContents(int addr_width, int data_width) : MemContents(addr_width, data_width, RTLIL::Const(State::Sx, data_width)) {} + explicit MemContents(Mem *mem); + int addr_width() const { return _addr_width; } + int data_width() const { return _data_width; } + RTLIL::Const const &default_value() const { return _default_value; } + // return the value at the address if it exists, the default_value of the memory otherwise. address must not exceed 2**addr_width. + RTLIL::Const operator [](addr_t addr) const; + // return the number of defined words in the range [begin_addr, end_addr) + addr_t count_range(addr_t begin_addr, addr_t end_addr) const; + // allocate memory for the range [begin_addr, end_addr), but leave the contents undefined. + void reserve_range(addr_t begin_addr, addr_t end_addr) { _reserve_range(begin_addr, end_addr); } + // insert multiple words (provided as a single concatenated RTLIL::Const) at the given address, overriding any previous assignment. + void insert_concatenated(addr_t addr, RTLIL::Const const &values); + // insert multiple words at the given address, overriding any previous assignment. + template void insert_range(addr_t addr, Iterator begin, Iterator end) { + auto words = end - begin; + log_assert(addr < 1<<_addr_width); log_assert(words <= (1<<_addr_width) - addr); + auto range = _reserve_range(addr, addr + words); + auto it = _range_data(range, addr); + for(; begin != end; ++begin) + it = _range_write(it, *begin); + } + // undefine all words in the range [begin_addr, end_addr) + void clear_range(addr_t begin_addr, addr_t end_addr); + // check invariants, abort if invariants failed + void check(); + iterator end() const { return iterator(nullptr, ~(addr_t) 0); } + iterator begin() const { return _values.empty() ? end() : iterator(this, _values.begin()->first); } + bool empty() const { return _values.empty(); } +}; + YOSYS_NAMESPACE_END #endif From bdb59ffc8e82985b99dc9fed3311f177c0caa885 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 24 Jul 2024 17:33:32 +0100 Subject: [PATCH 145/342] add -fst-noinit flag to sim for not initializing the state from the fst file --- passes/sat/sim.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index dd17a2eba..c83dfe254 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -123,6 +123,7 @@ struct SimShared std::vector triggered_assertions; std::vector display_output; bool serious_asserts = false; + bool fst_noinit = false; bool initstate = true; }; @@ -1553,7 +1554,7 @@ struct SimWorker : SimShared bool did_something = top->setInputs(); if (initial) { - did_something |= top->setInitState(); + if (!fst_noinit) did_something |= top->setInitState(); initialize_stable_past(); initial = false; } @@ -2688,6 +2689,10 @@ struct SimPass : public Pass { log(" fail the simulation command if, in the course of simulating,\n"); log(" any of the asserts in the design fail\n"); log("\n"); + log(" -fst-noinit\n"); + log(" do not initialize latches and memories from an input FST or VCD file\n"); + log(" (use the initial defined by the design instead)\n"); + log("\n"); log(" -q\n"); log(" disable per-cycle/sample log message\n"); log("\n"); @@ -2850,6 +2855,10 @@ struct SimPass : public Pass { worker.serious_asserts = true; continue; } + if (args[argidx] == "-fst-noinit") { + worker.fst_noinit = true; + continue; + } if (args[argidx] == "-x") { worker.ignore_x = true; continue; From 99effb6789b1c3ff62879d5404102da91a2bf70d Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 24 Jul 2024 17:37:17 +0100 Subject: [PATCH 146/342] add support for initializing registers and memories to the functional backend --- backends/functional/cxx.cc | 101 ++++++----- backends/functional/cxx_runtime/sim.h | 3 + backends/functional/smtlib.cc | 68 +++++--- backends/functional/test_generic.cc | 99 +++++++++++ kernel/functionalir.cc | 64 +++---- kernel/functionalir.h | 84 ++++----- tests/functional/rtlil_cells.py | 19 ++- tests/functional/smt_vcd.py | 21 +-- tests/functional/test_functional.py | 4 +- tests/functional/vcd_harness.cc | 237 +++++++++++++------------- 10 files changed, 418 insertions(+), 282 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 69f1973f2..324a8831c 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -69,35 +69,48 @@ struct CxxType { using CxxWriter = FunctionalTools::Writer; struct CxxStruct { - std::string name; - dict types; - CxxScope scope; - CxxStruct(std::string name) - : name(name) { - scope.reserve("fn"); - scope.reserve("visit"); - } - void insert(IdString name, CxxType type) { - scope(name, name); - types.insert({name, type}); - } - void print(CxxWriter &f) { - f.print("\tstruct {} {{\n", name); - for (auto p : types) { - f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first)); - } - f.print("\n\t\ttemplate void visit(T &&fn) {{\n"); - for (auto p : types) { - f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first)); - } - f.print("\t\t}}\n"); - f.print("\t}};\n\n"); - }; - std::string operator[](IdString field) { - return scope(field, field); - } + std::string name; + dict types; + CxxScope scope; + CxxStruct(std::string name) : name(name) + { + scope.reserve("fn"); + scope.reserve("visit"); + } + void insert(IdString name, CxxType type) { + scope(name, name); + types.insert({name, type}); + } + void print(CxxWriter &f) { + f.print("\tstruct {} {{\n", name); + for (auto p : types) { + f.print("\t\t{} {};\n", p.second.to_string(), scope(p.first, p.first)); + } + f.print("\n\t\ttemplate void visit(T &&fn) {{\n"); + for (auto p : types) { + f.print("\t\t\tfn(\"{}\", {});\n", RTLIL::unescape_id(p.first), scope(p.first, p.first)); + } + f.print("\t\t}}\n"); + f.print("\t}};\n\n"); + }; + std::string operator[](IdString field) { + return scope(field, field); + } }; +std::string cxx_const(RTLIL::Const const &value) { + std::stringstream ss; + ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase; + if(value.size() > 32) ss << "{"; + for(int i = 0; i < value.size(); i += 32) { + if(i > 0) ss << ", "; + ss << value.extract(i, 32).as_int(); + } + if(value.size() > 32) ss << "}"; + ss << ")"; + return ss.str(); +} + template struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor { using Node = FunctionalIR::Node; CxxWriter &f; @@ -136,20 +149,7 @@ template struct CxxPrintVisitor : public FunctionalIR::Abstra void logical_shift_right(Node, Node a, Node b) override { print("{} >> {}", a, b); } void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); } void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); } - void constant(Node, RTLIL::Const value) override { - std::stringstream ss; - bool multiple = value.size() > 32; - ss << "Signal<" << value.size() << ">(" << std::hex << std::showbase; - if(multiple) ss << "{"; - while(value.size() > 32) { - ss << value.as_int() << ", "; - value = value.extract(32, value.size() - 32); - } - ss << value.as_int(); - if(multiple) ss << "}"; - ss << ")"; - print("{}", ss.str()); - } + void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); } void input(Node, IdString name) override { print("input.{}", input_struct[name]); } void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); } void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); } @@ -184,8 +184,24 @@ struct CxxModule { output_struct.print(f); state_struct.print(f); f.print("\tstatic void eval(Inputs const &, Outputs &, State const &, State &);\n"); + f.print("\tstatic void initialize(State &);\n"); f.print("}};\n\n"); } + void write_initial_def(CxxWriter &f) { + f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name); + for (auto [name, sort] : ir.state()) { + if (sort.is_signal()) + f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name))); + else if (sort.is_memory()) { + const auto &contents = ir.get_initial_state_memory(name); + f.print("\tstate.{}.fill({});\n", state_struct[name], cxx_const(contents.default_value())); + for(auto range : contents) + for(auto addr = range.base(); addr < range.limit(); addr++) + f.print("\tstate.{}[{}] = {};\n", state_struct[name], addr, cxx_const(range[addr])); + } + } + f.print("}}\n\n"); + } void write_eval_def(CxxWriter &f) { f.print("void {0}::eval({0}::Inputs const &input, {0}::Outputs &output, {0}::State const ¤t_state, {0}::State &next_state)\n{{\n", module_name); CxxScope locals; @@ -204,7 +220,7 @@ struct CxxModule { f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name))); for (auto [name, sort] : ir.outputs()) f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name))); - f.print("}}\n"); + f.print("}}\n\n"); } }; @@ -225,6 +241,7 @@ struct FunctionalCxxBackend : public Backend mod.write_header(f); mod.write_struct_def(f); mod.write_eval_def(f); + mod.write_initial_def(f); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index ed1a25ed4..6cce4e845 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -410,6 +410,9 @@ public: ret._contents[addr.template as_numeric()] = data; return ret; } + // mutating methods for initializing a state + void fill(Signal data) { _contents.fill(data); } + Signal &operator[](Signal addr) { return _contents[addr.template as_numeric()]; } }; #endif diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index d40a4489f..0d2763d32 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -109,6 +109,13 @@ public: } }; +std::string smt_const(RTLIL::Const const &c) { + std::string s = "#b"; + for(int i = c.size(); i-- > 0; ) + s += c[i] == State::S1 ? '1' : '0'; + return s; +} + struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { using Node = FunctionalIR::Node; std::function n; @@ -117,13 +124,6 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { SmtPrintVisitor(SmtStruct &input_struct, SmtStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {} - std::string literal(RTLIL::Const c) { - std::string s = "#b"; - for(int i = c.size(); i-- > 0; ) - s += c[i] == State::S1 ? '1' : '0'; - return s; - } - SExpr from_bool(SExpr &&arg) { return list("ite", std::move(arg), "#b1", "#b0"); } @@ -149,8 +149,8 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); } SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); } SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); } - SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), literal(RTLIL::Const(State::S1, a.width())))); } - SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), literal(RTLIL::Const(State::S0, a.width())))); } + SExpr reduce_and(Node, Node a) override { return from_bool(list("=", n(a), smt_const(RTLIL::Const(State::S1, a.width())))); } + SExpr reduce_or(Node, Node a) override { return from_bool(list("distinct", n(a), smt_const(RTLIL::Const(State::S0, a.width())))); } SExpr reduce_xor(Node, Node a) override { vector s { "bvxor" }; for(int i = 0; i < a.width(); i++) @@ -174,7 +174,7 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } SExpr mux(Node, Node a, Node b, Node s) override { return list("ite", to_bool(n(s)), n(b), n(a)); } - SExpr constant(Node, RTLIL::Const value) override { return literal(value); } + SExpr constant(Node, RTLIL::Const const &value) override { return smt_const(value); } SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); } SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); } @@ -199,6 +199,7 @@ struct SmtModule { , output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope) , state_struct(scope.unique_name(module->name.str() + "_State"), scope) { + scope.reserve(name + "-initial"); for (const auto &input : ir.inputs()) input_struct.insert(input.first, input.second); for (const auto &output : ir.outputs()) @@ -207,18 +208,8 @@ struct SmtModule { state_struct.insert(state.first, state.second); } - void write(std::ostream &out) - { - SExprWriter w(out); - - input_struct.write_definition(w); - output_struct.write_definition(w); - state_struct.write_definition(w); - - w << list("declare-datatypes", - list(list("Pair", 2)), - list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y")))))); - + void write_eval(SExprWriter &w) + { w.push(); w.open(list("define-fun", name, list(list("inputs", input_struct.name), @@ -245,6 +236,39 @@ struct SmtModule { state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); }); w.pop(); } + + void write_initial(SExprWriter &w) + { + std::string initial = name + "-initial"; + w << list("declare-const", initial, state_struct.name); + for (const auto &[name, sort] : ir.state()) { + if(sort.is_signal()) + w << list("assert", list("=", state_struct.access(initial, name), smt_const(ir.get_initial_state_signal(name)))); + else if(sort.is_memory()) { + auto contents = ir.get_initial_state_memory(name); + for(int i = 0; i < 1< USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +struct MemContentsTest { + int addr_width, data_width; + MemContents state; + using addr_t = MemContents::addr_t; + std::map reference; + MemContentsTest(int addr_width, int data_width) : addr_width(addr_width), data_width(data_width), state(addr_width, data_width, RTLIL::Const(State::S0, data_width)) {} + void check() { + state.check(); + for(auto addr = 0; addr < (1<second != state[addr]) goto error; + } else { + if(state.count_range(addr, addr + 1) != 0) goto error; + } + } + return; + error: + printf("FAIL\n"); + int digits = (data_width + 3) / 4; + + for(auto addr = 0; addr < (1<second : state.default_value(); + std::string ref_string = stringf("%.*x", digits, ref_value.as_int()); + bool sta_def = state.count_range(addr, addr + 1) == 1; + RTLIL::Const sta_value = state[addr]; + std::string sta_string = stringf("%.*x", digits, sta_value.as_int()); + if(ref_def && sta_def) { + if(ref_value == sta_value) printf("%s%s", ref_string.c_str(), string(digits, ' ').c_str()); + else printf("%s%s", ref_string.c_str(), sta_string.c_str()); + } else if(ref_def) { + printf("%s%s", ref_string.c_str(), string(digits, 'M').c_str()); + } else if(sta_def) { + printf("%s%s", sta_string.c_str(), string(digits, 'X').c_str()); + } else { + printf("%s", string(2*digits, ' ').c_str()); + } + printf(" "); + if(addr % 8 == 7) printf("\n"); + } + printf("\n"); + //log_abort(); + } + void clear_range(addr_t begin_addr, addr_t end_addr) { + for(auto addr = begin_addr; addr != end_addr; addr++) + reference.erase(addr); + state.clear_range(begin_addr, end_addr); + check(); + } + void insert_concatenated(addr_t addr, RTLIL::Const const &values) { + addr_t words = ((addr_t) values.size() + data_width - 1) / data_width; + for(addr_t i = 0; i < words; i++) { + reference.erase(addr + i); + reference.emplace(addr + i, values.extract(i * data_width, data_width)); + } + state.insert_concatenated(addr, values); + check(); + } + template void run(Rnd &rnd, int n) { + std::uniform_int_distribution addr_dist(0, (1< length_dist(10); + std::uniform_int_distribution data_dist(0, ((uint64_t)1< 0) { + addr_t low = addr_dist(rnd); + //addr_t length = std::min((1< high) std::swap(low, high); + if((rnd() & 7) == 0) { + log_debug("clear %.2x to %.2x\n", (int)low, (int)high); + clear_range(low, high + 1); + } else { + log_debug("insert %.2x to %.2x\n", (int)low, (int)high); + RTLIL::Const values; + for(addr_t addr = low; addr <= high; addr++) { + RTLIL::Const word(data_dist(rnd), data_width); + values.bits.insert(values.bits.end(), word.bits.begin(), word.bits.end()); + } + insert_concatenated(low, values); + } + } + } + +}; + struct FunctionalTestGeneric : public Pass { FunctionalTestGeneric() : Pass("test_generic", "test the generic compute graph") {} @@ -40,6 +130,14 @@ struct FunctionalTestGeneric : public Pass size_t argidx = 1; extra_args(args, argidx, design); + MemContentsTest test(8, 16); + + std::random_device seed_dev; + std::mt19937 rnd(23); //seed_dev()); + test.run(rnd, 1000); + +/* + for (auto module : design->selected_modules()) { log("Dumping module `%s'.\n", module->name.c_str()); auto fir = FunctionalIR::from_module(module); @@ -50,6 +148,7 @@ struct FunctionalTestGeneric : public Pass for(auto [name, sort] : fir.state()) std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n"; } +*/ } } FunctionalCxxBackend; diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 155cb3bbc..bc21b4d36 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -19,6 +19,8 @@ #include "kernel/functionalir.h" #include +#include "ff.h" +#include "ffinit.h" YOSYS_NAMESPACE_BEGIN @@ -70,7 +72,7 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor { std::string slice(Node, Node a, int offset, int out_width) override { return "slice(" + np(a) + ", " + std::to_string(offset) + ", " + std::to_string(out_width) + ")"; } std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } - std::string constant(Node, RTLIL::Const value) override { return "constant(" + value.as_string() + ")"; } + std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; } std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; } std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; } std::string default_handler(Node self) override { @@ -407,6 +409,8 @@ class FunctionalIRConstruction { CellSimplifier simplifier; vector memories_vector; dict memories; + SigMap sig_map; // TODO: this is only for FfInitVals, remove this once FfInitVals supports DriverMap + FfInitVals ff_initvals; Node enqueue(DriveSpec const &spec) { @@ -438,8 +442,11 @@ class FunctionalIRConstruction { return it->second; } public: - FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {} - void add_module(Module *module) + FunctionalIRConstruction(Module *module, FunctionalIR::Factory &f) + : factory(f) + , simplifier(f) + , sig_map(module) + , ff_initvals(&sig_map, module) { driver_map.add(module); for (auto cell : module->cells()) { @@ -447,9 +454,12 @@ public: queue.emplace_back(cell); } for (auto wire : module->wires()) { + if (wire->port_input) + factory.add_input(wire->name, wire->width); if (wire->port_output) { - Node node = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); - factory.declare_output(node, wire->name, wire->width); + factory.add_output(wire->name, wire->width); + Node value = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); + factory.set_output(wire->name, value); } } memories_vector = Mem::get_all_memories(module); @@ -487,9 +497,9 @@ public: // - Since wr port j can only have priority over wr port i if j > i, if we do writes in // ascending index order the result will obey the priorty relation. vector read_results; - int addr_width = ceil_log2(mem->size); - int data_width = mem->width; - Node node = factory.state_memory(mem->cell->name, addr_width, data_width); + factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width)); + factory.set_initial_state(mem->cell->name, MemContents(mem)); + Node node = factory.get_current_state(mem->cell->name); for (size_t i = 0; i < mem->wr_ports.size(); i++) { const auto &wr = mem->wr_ports[i]; if (wr.clk_enable) @@ -513,7 +523,7 @@ public: Node addr = enqueue(driver_map(DriveSpec(rd.addr))); read_results.push_back(factory.memory_read(node, addr)); } - factory.declare_state_memory(node, mem->cell->name, addr_width, data_width); + factory.set_next_state(mem->cell->name, node); return concatenate_read_results(mem, read_results); } void process_cell(Cell *cell) @@ -527,6 +537,17 @@ public: } Node node = handle_memory(mem); factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); + } else if (RTLIL::builtin_ff_cell_types().count(cell->type)) { + FfData ff(&ff_initvals, cell); + if (!ff.has_gclk) + log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " + "Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell)); + factory.add_state(ff.name, FunctionalIR::Sort(ff.width)); + Node q_value = factory.get_current_state(ff.name); + factory.suggest_name(q_value, ff.name); + factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); + factory.set_next_state(ff.name, enqueue(ff.sig_d)); + factory.set_initial_state(ff.name, ff.val_init); } else { dict connections; IdString output_name; // for the single output case @@ -572,7 +593,7 @@ public: DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { if (wire_chunk.wire->port_input) { - Node node = factory.input(wire_chunk.wire->name, wire_chunk.width); + Node node = factory.get_input(wire_chunk.wire->name); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); } else { @@ -590,24 +611,8 @@ public: DriveChunkPort port_chunk = chunk.port(); if (port_chunk.is_whole()) { if (driver_map.celltypes.cell_output(port_chunk.cell->type, port_chunk.port)) { - if (port_chunk.cell->type.in(ID($dff), ID($ff))) - { - Cell *cell = port_chunk.cell; - Node node = factory.state(cell->name, port_chunk.width); - factory.suggest_name(node, port_chunk.cell->name); - factory.update_pending(pending, node); - for (auto const &conn : cell->connections()) { - if (driver_map.celltypes.cell_input(cell->type, conn.first)) { - Node node = enqueue(DriveChunkPort(cell, conn)); - factory.declare_state(node, cell->name, port_chunk.width); - } - } - } - else - { - Node node = enqueue_cell(port_chunk.cell, port_chunk.port); - factory.update_pending(pending, node); - } + Node node = enqueue_cell(port_chunk.cell, port_chunk.port); + factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(port_chunk)); factory.update_pending(pending, enqueue(driver)); @@ -641,8 +646,7 @@ public: FunctionalIR FunctionalIR::from_module(Module *module) { FunctionalIR ir; auto factory = ir.factory(); - FunctionalIRConstruction ctor(factory); - ctor.add_module(module); + FunctionalIRConstruction ctor(module, factory); ctor.process_queue(); ir.topological_sort(); ir.forward_buf(); diff --git a/kernel/functionalir.h b/kernel/functionalir.h index 852937612..e0af89d9f 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -189,24 +189,11 @@ private: // the bool is true for next state values using Graph = ComputeGraph>; Graph _graph; - dict _inputs; - dict _outputs; - dict _state; - void add_input(IdString name, Sort sort) { - auto [it, found] = _inputs.emplace(name, std::move(sort)); - if(found) - log_assert(it->second == sort); - } - void add_state(IdString name, Sort sort) { - auto [it, found] = _state.emplace(name, std::move(sort)); - if(found) - log_assert(it->second == sort); - } - void add_output(IdString name, Sort sort) { - auto [it, found] = _outputs.emplace(name, std::move(sort)); - if(found) - log_assert(it->second == sort); - } + dict _input_sorts; + dict _output_sorts; + dict _state_sorts; + dict _initial_state_signal; + dict _initial_state_memory; public: class Factory; // Node is an immutable reference to a FunctionalIR node @@ -306,7 +293,7 @@ public: virtual T logical_shift_right(Node self, Node a, Node b) = 0; virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; virtual T mux(Node self, Node a, Node b, Node s) = 0; - virtual T constant(Node self, RTLIL::Const value) = 0; + virtual T constant(Node self, RTLIL::Const const & value) = 0; virtual T input(Node self, IdString name) = 0; virtual T state(Node self, IdString name) = 0; virtual T memory_read(Node self, Node mem, Node addr) = 0; @@ -343,7 +330,7 @@ public: T logical_shift_right(Node self, Node, Node) override { return default_handler(self); } T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } T mux(Node self, Node, Node, Node) override { return default_handler(self); } - T constant(Node self, RTLIL::Const) override { return default_handler(self); } + T constant(Node self, RTLIL::Const const &) override { return default_handler(self); } T input(Node self, IdString) override { return default_handler(self); } T state(Node self, IdString) override { return default_handler(self); } T memory_read(Node self, Node, Node) override { return default_handler(self); } @@ -452,30 +439,41 @@ public: log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); log_assert(node.sort() == value.sort()); mutate(node).append_arg(value._ref); - } - Node input(IdString name, int width) { - _ir.add_input(name, Sort(width)); - return add(NodeData(Fn::input, name), Sort(width), {}); } - Node state(IdString name, int width) { - _ir.add_state(name, Sort(width)); - return add(NodeData(Fn::state, name), Sort(width), {}); + void add_input(IdString name, int width) { + auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width)); + if (!inserted) log_error("input `%s` was re-defined", name.c_str()); } - Node state_memory(IdString name, int addr_width, int data_width) { - _ir.add_state(name, Sort(addr_width, data_width)); - return add(NodeData(Fn::state, name), Sort(addr_width, data_width), {}); + void add_output(IdString name, int width) { + auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width)); + if (!inserted) log_error("output `%s` was re-defined", name.c_str()); } - void declare_output(Node node, IdString name, int width) { - _ir.add_output(name, Sort(width)); - mutate(node).assign_key({name, false}); + void add_state(IdString name, Sort sort) { + auto [it, inserted] = _ir._state_sorts.emplace(name, sort); + if (!inserted) log_error("state `%s` was re-defined", name.c_str()); } - void declare_state(Node node, IdString name, int width) { - _ir.add_state(name, Sort(width)); - mutate(node).assign_key({name, true}); + Node get_input(IdString name) { + return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); } - void declare_state_memory(Node node, IdString name, int addr_width, int data_width) { - _ir.add_state(name, Sort(addr_width, data_width)); - mutate(node).assign_key({name, true}); + Node get_current_state(IdString name) { + return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); + } + void set_output(IdString output, Node value) { + log_assert(_ir._output_sorts.at(output) == value.sort()); + mutate(value).assign_key({output, false}); + } + void set_initial_state(IdString state, RTLIL::Const value) { + Sort &sort = _ir._state_sorts.at(state); + value.extu(sort.width()); + _ir._initial_state_signal.emplace(state, std::move(value)); + } + void set_initial_state(IdString state, MemContents value) { + log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state)); + _ir._initial_state_memory.emplace(state, std::move(value)); + } + void set_next_state(IdString state, Node value) { + log_assert(_ir._state_sorts.at(state) == value.sort()); + mutate(value).assign_key({state, true}); } void suggest_name(Node node, IdString name) { mutate(node).sparse_attr() = name; @@ -487,9 +485,11 @@ public: Node operator[](int i) { return Node(_graph[i]); } void topological_sort(); void forward_buf(); - dict inputs() const { return _inputs; } - dict outputs() const { return _outputs; } - dict state() const { return _state; } + dict inputs() const { return _input_sorts; } + dict outputs() const { return _output_sorts; } + dict state() const { return _state_sorts; } + RTLIL::Const const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); } + MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); } Node get_output_node(IdString name) { return Node(_graph({name, false})); } Node get_state_next_node(IdString name) { return Node(_graph({name, true})); } class Iterator { diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index 90417579e..ed867b695 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -153,15 +153,17 @@ class FFCell(BaseCell): from test_functional import yosys_synth verilog_file = path.parent / 'verilog.v' with open(verilog_file, 'w') as f: - f.write(""" + width = parameters['WIDTH'] + f.write(f""" module gold( input wire clk, - input wire [{0}:0] D, - output reg [{0}:0] Q + input wire [{width-1}:0] D, + output reg [{width-1}:0] Q ); + initial Q = {width}'b{("101" * width)[:width]}; always @(posedge clk) Q <= D; -endmodule""".format(parameters['WIDTH'] - 1)) +endmodule""") yosys_synth(verilog_file, path) class MemCell(BaseCell): @@ -180,6 +182,10 @@ module gold( output reg [{0}:0] RD ); reg [{0}:0] mem[0:{2}]; + integer i; + initial + for(i = 0; i <= {2}; i = i + 1) + mem[i] = 9192 * (i + 1); always @(*) RD = mem[RA]; always @(posedge clk) @@ -211,8 +217,11 @@ module gold( output reg [{0}:0] RD1, output reg [{0}:0] RD2 ); - (*keep*) reg [{0}:0] mem[0:{2}]; + integer i; + initial + for(i = 0; i <= {2}; i = i + 1) + mem[i] = 9192 * (i + 1); always @(*) RD1 = mem[RA1]; always @(*) diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index 37d2a209f..c23be440e 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -81,25 +81,6 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): parser.finish() assert smt_io.check_sat() == 'sat' - def initial_state(states): - mk_state_parts = [] - rv = [] - for name, width in states.items(): - if isinstance(width, int): - binary_string = format(0, '0{}b'.format(width)) - mk_state_parts.append(f"#b{binary_string}") - else: - binary_string = format(0, '0{}b'.format(width[1])) - rv.append(f"(declare-const test_state_initial_mem_{name} (Array (_ BitVec {width[0]}) (_ BitVec {width[1]})))") - rv.append(f"(assert (forall ((i (_ BitVec {width[0]}))) (= (select test_state_initial_mem_{name} i) #b{binary_string})))") - mk_state_parts.append(f"test_state_initial_mem_{name}") - if len(states) == 0: - mk_state_call = "gold_State" - else: - mk_state_call = "(gold_State {})".format(" ".join(mk_state_parts)) - rv.append(f"(define-const test_state_step_n0 gold_State {mk_state_call})\n") - return rv - def set_step(inputs, step): # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. @@ -118,7 +99,7 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): f"(define-const test_state_step_n{step+1} gold_State (second test_results_step_n{step}))\n", ] - smt_commands = initial_state(states) + smt_commands = [f"(define-const test_state_step_n0 gold_State gold-initial)\n"] for step in range(num_steps): for step_command in set_step(inputs, step): smt_commands.append(step_command) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index c31f4b86f..7bfe19fc4 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -29,14 +29,14 @@ def yosys_synth(verilog_file, rtlil_file): # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""): try: - yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold") + yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold -fst-noinit") except: # if yosys sim fails it's probably because of a simulation mismatch # since yosys sim aborts on simulation mismatch to generate vcd output # we have to re-run with a different set of flags # on this run we ignore output and return code, we just want a best-effort attempt to get a vcd subprocess.run([base_path / 'yosys', '-Q', '-p', - f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us'], + f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us -fst-noinit'], capture_output=True, check=False) raise diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc index f01adf218..723217234 100644 --- a/tests/functional/vcd_harness.cc +++ b/tests/functional/vcd_harness.cc @@ -7,140 +7,139 @@ #include "my_module_functional_cxx.cc" -std::string vcd_name_mangle(std::string name) { - std::string ret = name; - bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_'; - for(size_t i = 0; i < ret.size(); i++) { - if(isspace(ret[i])) ret[i] = '_'; - if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$') - escape = true; - } - if(escape) - return "\\" + ret; - else - return ret; +class VcdFile { + std::ofstream &ofs; + std::string code_alloc = "!"; + std::unordered_map codes; + std::string name_mangle(std::string name) { + std::string ret = name; + bool escape = ret.empty() || !isalpha(ret[0]) && ret[0] != '_'; + for(size_t i = 0; i < ret.size(); i++) { + if(isspace(ret[i])) ret[i] = '_'; + if(!isalnum(ret[i]) && ret[i] != '_' && ret[i] != '$') + escape = true; + } + if(escape) + return "\\" + ret; + else + return ret; + } + std::string allocate_code() { + std::string ret = code_alloc; + for (size_t i = 0; i < code_alloc.size(); i++) + if (code_alloc[i]++ == '~') + code_alloc[i] = '!'; + else + return ret; + code_alloc.push_back('!'); + return ret; + } +public: + VcdFile(std::ofstream &ofs) : ofs(ofs) {} + struct DumpHeader { + VcdFile *file; + explicit DumpHeader(VcdFile *file) : file(file) {} + template void operator()(const char *name, Signal value) + { + auto it = file->codes.find(name); + if(it == file->codes.end()) + it = file->codes.emplace(name, file->allocate_code()).first; + file->ofs << "$var wire " << n << " " << it->second << " " << file->name_mangle(name) << " $end\n"; + } + template void operator()(const char *name, Memory value) {} + }; + struct Dump { + VcdFile *file; + explicit Dump(VcdFile *file) : file(file) {} + template void operator()(const char *name, Signal value) + { + if (n == 1) { + file->ofs << (value[0] ? '1' : '0'); + file->ofs << file->codes.at(name) << "\n"; + } else { + file->ofs << "b"; + for (size_t i = n; i-- > 0;) + file->ofs << (value[i] ? '1' : '0'); + file->ofs << " " << file->codes.at(name) << "\n"; + } + } + template void operator()(const char *name, Memory value) {} + }; + void begin_header() { + constexpr int number_timescale = 1; + const std::string units_timescale = "us"; + ofs << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; + ofs << "$scope module gold $end\n"; + } + void end_header() { + ofs << "$enddefinitions $end\n$dumpvars\n"; + } + template void header(Args ...args) { + begin_header(); + DumpHeader d(this); + (args.visit(d), ...); + end_header(); + } + void begin_data(int step) { + ofs << "#" << step << "\n"; + } + template void data(int step, Args ...args) { + begin_data(step); + Dump d(this); + (args.visit(d), ...); + } + DumpHeader dump_header() { return DumpHeader(this); } + Dump dump() { return Dump(this); } +}; + +template Signal random_signal(std::mt19937 &gen) +{ + std::uniform_int_distribution dist; + std::array words; + for (auto &w : words) + w = dist(gen); + return Signal::from_array(words); } -std::unordered_map codes; - -struct DumpHeader { - std::ofstream &ofs; - std::string code = "!"; - DumpHeader(std::ofstream &ofs) : ofs(ofs) {} - void increment_code() { - for(size_t i = 0; i < code.size(); i++) - if(code[i]++ == '~') - code[i] = '!'; - else - return; - code.push_back('!'); - } - template - void operator()(const char *name, Signal value) { - ofs << "$var wire " << n << " " << code << " " << vcd_name_mangle(name) << " $end\n"; - codes[name] = code; - increment_code(); - } - template - void operator()(const char *name, Memory value) { - } -}; - -struct Dump { - std::ofstream &ofs; - Dump(std::ofstream &ofs) : ofs(ofs) {} - template - void operator()(const char *name, Signal value) { - // Bit - if (n == 1) { - ofs << (value[0] ? '1' : '0'); - ofs << codes[name] << "\n"; - return; - } - // vector (multi-bit) signals - ofs << "b"; - for (size_t i = n; i-- > 0;) - ofs << (value[i] ? '1' : '0'); - ofs << " " << codes[name] << "\n"; - } - template - void operator()(const char *name, Memory value) { - } -}; - -template -Signal random_signal(std::mt19937 &gen) { - std::uniform_int_distribution dist; - std::array words; - for(auto &w : words) - w = dist(gen); - return Signal::from_array(words); -} - -struct Reset { - template - void operator()(const char *, Signal &signal) { - signal = 0; - } -}; struct Randomize { - std::mt19937 &gen; - Randomize(std::mt19937 &gen) : gen(gen) {} + std::mt19937 &gen; + Randomize(std::mt19937 &gen) : gen(gen) {} - template - void operator()(const char *, Signal &signal) { - signal = random_signal(gen); - } + template void operator()(const char *, Signal &signal) { signal = random_signal(gen); } }; int main(int argc, char **argv) { - if (argc != 4) { - std::cerr << "Usage: " << argv[0] << " \n"; - return 1; - } + if (argc != 4) { + std::cerr << "Usage: " << argv[0] << " \n"; + return 1; + } - const std::string functional_vcd_filename = argv[1]; - const int steps = atoi(argv[2]); - const uint32_t seed = atoi(argv[3]); + const std::string functional_vcd_filename = argv[1]; + const int steps = atoi(argv[2]); + const uint32_t seed = atoi(argv[3]); - constexpr int number_timescale = 1; - const std::string units_timescale = "us"; - gold::Inputs inputs; - gold::Outputs outputs; - gold::State state; - gold::State next_state; + gold::Inputs inputs; + gold::Outputs outputs; + gold::State state; + gold::State next_state; - std::ofstream vcd_file(functional_vcd_filename); + std::ofstream vcd_file(functional_vcd_filename); + VcdFile vcd(vcd_file); + vcd.header(inputs, outputs, state); - vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n"; - vcd_file << "$scope module gold $end\n"; - { - DumpHeader d(vcd_file); - inputs.visit(d); - outputs.visit(d); - state.visit(d); - } - vcd_file << "$enddefinitions $end\n$dumpvars\n"; - std::mt19937 gen(seed); + std::mt19937 gen(seed); - inputs.visit(Reset()); + gold::initialize(state); - for (int step = 0; step < steps; ++step) { - vcd_file << "#" << step << "\n"; - gold::eval(inputs, outputs, state, next_state); - { - Dump d(vcd_file); - inputs.visit(d); - outputs.visit(d); - state.visit(d); - } + for (int step = 0; step < steps; ++step) { + inputs.visit(Randomize(gen)); - state = next_state; - inputs.visit(Randomize(gen)); - } + gold::eval(inputs, outputs, state, next_state); + vcd.data(step, inputs, outputs, state); - vcd_file.close(); + state = next_state; + } - return 0; + return 0; } From 95d28c22a2d6aecc7bdb400f85896b271561c95a Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 24 Jul 2024 18:50:03 +0100 Subject: [PATCH 147/342] functional backend: make Memory in the C++ simulation library read-only again --- backends/functional/cxx.cc | 17 +++++++++++++++-- backends/functional/cxx_runtime/sim.h | 5 ++--- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 324a8831c..8d53c9e03 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -156,6 +156,14 @@ template struct CxxPrintVisitor : public FunctionalIR::Abstra void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); } }; +bool equal_def(RTLIL::Const const &a, RTLIL::Const const &b) { + if(a.size() != b.size()) return false; + for(int i = 0; i < a.size(); i++) + if((a[i] == State::S1) != (b[i] == State::S1)) + return false; + return true; +} + struct CxxModule { FunctionalIR ir; CxxStruct input_struct, output_struct, state_struct; @@ -193,11 +201,16 @@ struct CxxModule { if (sort.is_signal()) f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name))); else if (sort.is_memory()) { + f.print("\t{{\n"); + f.print("\t\tstd::array, {}> mem;\n", sort.data_width(), 1< class Memory { std::array, 1< _contents; public: + Memory() {} + Memory(std::array, 1< const &contents) : _contents(contents) {} Signal read(Signal addr) const { return _contents[addr.template as_numeric()]; @@ -410,9 +412,6 @@ public: ret._contents[addr.template as_numeric()] = data; return ret; } - // mutating methods for initializing a state - void fill(Signal data) { _contents.fill(data); } - Signal &operator[](Signal addr) { return _contents[addr.template as_numeric()]; } }; #endif From 7ac0e92d35e49704a9eb37d6ed5b451fa0db60fd Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 07:59:00 +0100 Subject: [PATCH 148/342] functional backend: rename get_input and get_current_state to input and current_state (more consistent with other methods) --- kernel/functionalir.cc | 6 +++--- kernel/functionalir.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index bc21b4d36..195e47b12 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -499,7 +499,7 @@ public: vector read_results; factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width)); factory.set_initial_state(mem->cell->name, MemContents(mem)); - Node node = factory.get_current_state(mem->cell->name); + Node node = factory.current_state(mem->cell->name); for (size_t i = 0; i < mem->wr_ports.size(); i++) { const auto &wr = mem->wr_ports[i]; if (wr.clk_enable) @@ -543,7 +543,7 @@ public: log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " "Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell)); factory.add_state(ff.name, FunctionalIR::Sort(ff.width)); - Node q_value = factory.get_current_state(ff.name); + Node q_value = factory.current_state(ff.name); factory.suggest_name(q_value, ff.name); factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); factory.set_next_state(ff.name, enqueue(ff.sig_d)); @@ -593,7 +593,7 @@ public: DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { if (wire_chunk.wire->port_input) { - Node node = factory.get_input(wire_chunk.wire->name); + Node node = factory.input(wire_chunk.wire->name); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); } else { diff --git a/kernel/functionalir.h b/kernel/functionalir.h index e0af89d9f..fdbdcbde3 100644 --- a/kernel/functionalir.h +++ b/kernel/functionalir.h @@ -452,10 +452,10 @@ public: auto [it, inserted] = _ir._state_sorts.emplace(name, sort); if (!inserted) log_error("state `%s` was re-defined", name.c_str()); } - Node get_input(IdString name) { + Node input(IdString name) { return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); } - Node get_current_state(IdString name) { + Node current_state(IdString name) { return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); } void set_output(IdString output, Node value) { From 8c0f625c3aaeb378a4b86cb2e75fc801cf4bef2c Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 10:35:32 +0100 Subject: [PATCH 149/342] functional backend: topological sort starts with the output and next states nodes, other nodes get deleted --- backends/functional/test_generic.cc | 10 +++----- kernel/functional.h | 18 +++++++++++++- kernel/functionalir.cc | 20 ++++++++++----- kernel/topo_scc.h | 38 +++++++++++++++++++---------- passes/cmds/example_dt.cc | 4 +-- 5 files changed, 62 insertions(+), 28 deletions(-) diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index ba713b36c..5d9349276 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -129,14 +129,13 @@ struct FunctionalTestGeneric : public Pass size_t argidx = 1; extra_args(args, argidx, design); - +/* MemContentsTest test(8, 16); std::random_device seed_dev; std::mt19937 rnd(23); //seed_dev()); test.run(rnd, 1000); - -/* +*/ for (auto module : design->selected_modules()) { log("Dumping module `%s'.\n", module->name.c_str()); @@ -144,11 +143,10 @@ struct FunctionalTestGeneric : public Pass for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; for(auto [name, sort] : fir.outputs()) - std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n"; + std::cout << "output " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n"; for(auto [name, sort] : fir.state()) - std::cout << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n"; + std::cout << "state " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n"; } -*/ } } FunctionalCxxBackend; diff --git a/kernel/functional.h b/kernel/functional.h index 09f66c981..77e965f64 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -268,6 +268,19 @@ public: return added; } + void compact_args() + { + std::vector new_args; + for (auto &node : nodes) + { + int new_offset = GetSize(new_args); + for (int i = 0; i < node.arg_count; i++) + new_args.push_back(args[node.arg_offset + i]); + node.arg_offset = new_offset; + } + std::swap(args, new_args); + } + void permute(std::vector const &perm) { log_assert(perm.size() <= nodes.size()); @@ -276,7 +289,7 @@ public: for (int i = 0; i < GetSize(perm); ++i) { int j = perm[i]; - log_assert(j >= 0 && j < GetSize(perm)); + log_assert(j >= 0 && j < GetSize(nodes)); log_assert(inv_perm[j] == -1); inv_perm[j] = i; } @@ -301,15 +314,18 @@ public: std::swap(nodes, new_nodes); std::swap(sparse_attrs, new_sparse_attrs); + compact_args(); for (int &arg : args) { log_assert(arg < GetSize(inv_perm)); + log_assert(inv_perm[arg] >= 0); arg = inv_perm[arg]; } for (auto &key : keys_) { log_assert(key.second < GetSize(inv_perm)); + log_assert(inv_perm[key.second] >= 0); key.second = inv_perm[key.second]; } } diff --git a/kernel/functionalir.cc b/kernel/functionalir.cc index 195e47b12..223fdaa91 100644 --- a/kernel/functionalir.cc +++ b/kernel/functionalir.cc @@ -657,19 +657,27 @@ void FunctionalIR::topological_sort() { Graph::SccAdaptor compute_graph_scc(_graph); bool scc = false; std::vector perm; - topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + TopoSortedSccs toposort(compute_graph_scc, [&](int *begin, int *end) { perm.insert(perm.end(), begin, end); if (end > begin + 1) { - log_warning("SCC:"); - for (int *i = begin; i != end; ++i) - log(" %d", *i); + log_warning("Combinational loop:\n"); + for (int *i = begin; i != end; ++i) { + Node node(_graph[*i]); + log("- %s = %s\n", RTLIL::unescape_id(node.name()).c_str(), node.to_string().c_str()); + } log("\n"); scc = true; } - }, /* sources_first */ true); + }); + for(const auto &[name, sort]: _state_sorts) + toposort.process(get_state_next_node(name).id()); + for(const auto &[name, sort]: _output_sorts) + toposort.process(get_output_node(name).id()); + // any nodes untouched by this point are dead code and will be removed by permute _graph.permute(perm); - if(scc) log_error("combinational loops, aborting\n"); + if(scc) log_error("The design contains combinational loops. This is not supported by the functional backend. " + "Try `scc -select; simplemap; select -clear` to avoid this error.\n"); } static IdString merge_name(IdString a, IdString b) { diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h index 89df8928a..7e730bb27 100644 --- a/kernel/topo_scc.h +++ b/kernel/topo_scc.h @@ -194,7 +194,7 @@ public: }; template -void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first = false) +class TopoSortedSccs { typedef typename G::node_enumerator node_enumerator; typedef typename G::successor_enumerator successor_enumerator; @@ -210,14 +210,20 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first {} }; + G &graph; + ComponentCallback component; + std::vector dfs_stack; std::vector component_stack; int next_index = 0; +public: + TopoSortedSccs(G &graph, ComponentCallback component) + : graph(graph), component(component) {} - node_enumerator nodes = graph.enumerate_nodes(); - - if (sources_first) { + // process all sources (nodes without a successor) + TopoSortedSccs &process_sources() { + node_enumerator nodes = graph.enumerate_nodes(); while (!nodes.finished()) { node_type node = nodes.next(); successor_enumerator successors = graph.enumerate_successors(node); @@ -231,16 +237,23 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first graph.dfs_index(node) = INT_MAX; } } - nodes = graph.enumerate_nodes(); + return *this; } - // iterate over all nodes to ensure we process the whole graph - while (!nodes.finished()) { - node_type node = nodes.next(); + // process all remaining nodes in the graph + TopoSortedSccs &process_all() { + node_enumerator nodes = graph.enumerate_nodes(); + // iterate over all nodes to ensure we process the whole graph + while (!nodes.finished()) + process(nodes.next()); + return *this; + } + + // process all nodes that are reachable from a given start node + TopoSortedSccs &process(node_type node) { // only start a new search if the node wasn't visited yet if (graph.dfs_index(node) >= 0) - continue; - + return *this; while (true) { // at this point we're visiting the node for the first time during // the DFS search @@ -299,7 +312,7 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first // continues the search at the parent node or returns to // the outer loop if we already are at the root node. if (dfs_stack.empty()) - goto next_search; + return *this; auto &dfs_top = dfs_stack.back(); node = dfs_top.node; @@ -336,9 +349,8 @@ void topo_sorted_sccs(G &graph, ComponentCallback component, bool sources_first } } } - next_search:; } -} +}; YOSYS_NAMESPACE_END diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index 859b0b7ba..4b836d75b 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -183,7 +183,7 @@ struct ExampleDtPass : public Pass std::vector perm; - topo_sorted_sccs(compute_graph_scc, [&](int *begin, int *end) { + TopoSortedSccs(compute_graph_scc, [&](int *begin, int *end) { perm.insert(perm.end(), begin, end); if (end > begin + 1) { @@ -192,7 +192,7 @@ struct ExampleDtPass : public Pass log(" %d", *i); log("\n"); } - }, /* sources_first */ true); + }).process_sources().process_all(); compute_graph.permute(perm); From 850b3a6c29b8b1ffd76ed24493d85ffa721f8109 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 12:10:59 +0100 Subject: [PATCH 150/342] convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h --- Makefile | 2 +- backends/functional/cxx.cc | 20 +- backends/functional/smtlib.cc | 22 +- backends/functional/test_generic.cc | 4 +- kernel/compute_graph.h | 403 ++++++++++ kernel/{functionalir.cc => functional.cc} | 111 ++- kernel/functional.h | 935 +++++++++++++--------- kernel/functionalir.h | 575 ------------- kernel/mem.h | 11 +- kernel/utils.h | 9 + passes/cmds/example_dt.cc | 2 +- 11 files changed, 1055 insertions(+), 1039 deletions(-) create mode 100644 kernel/compute_graph.h rename kernel/{functionalir.cc => functional.cc} (90%) delete mode 100644 kernel/functionalir.h diff --git a/Makefile b/Makefile index 68e6fda4a..e61948cb4 100644 --- a/Makefile +++ b/Makefile @@ -640,7 +640,7 @@ $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o -OBJS += kernel/drivertools.o kernel/functionalir.o +OBJS += kernel/drivertools.o kernel/functional.o ifeq ($(ENABLE_ZLIB),1) OBJS += kernel/fstdata.o endif diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 8d53c9e03..a4755e144 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -18,7 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/functionalir.h" +#include "kernel/functional.h" #include USING_YOSYS_NAMESPACE @@ -42,7 +42,7 @@ const char *reserved_keywords[] = { nullptr }; -template struct CxxScope : public FunctionalTools::Scope { +template struct CxxScope : public Functional::Scope { CxxScope() { for(const char **p = reserved_keywords; *p != nullptr; p++) this->reserve(*p); @@ -53,8 +53,8 @@ template struct CxxScope : public FunctionalTools::Scope { }; struct CxxType { - FunctionalIR::Sort sort; - CxxType(FunctionalIR::Sort sort) : sort(sort) {} + Functional::Sort sort; + CxxType(Functional::Sort sort) : sort(sort) {} std::string to_string() const { if(sort.is_memory()) { return stringf("Memory<%d, %d>", sort.addr_width(), sort.data_width()); @@ -66,7 +66,7 @@ struct CxxType { } }; -using CxxWriter = FunctionalTools::Writer; +using CxxWriter = Functional::Writer; struct CxxStruct { std::string name; @@ -111,8 +111,8 @@ std::string cxx_const(RTLIL::Const const &value) { return ss.str(); } -template struct CxxPrintVisitor : public FunctionalIR::AbstractVisitor { - using Node = FunctionalIR::Node; +template struct CxxPrintVisitor : public Functional::AbstractVisitor { + using Node = Functional::Node; CxxWriter &f; NodePrinter np; CxxStruct &input_struct; @@ -165,12 +165,12 @@ bool equal_def(RTLIL::Const const &a, RTLIL::Const const &b) { } struct CxxModule { - FunctionalIR ir; + Functional::IR ir; CxxStruct input_struct, output_struct, state_struct; std::string module_name; explicit CxxModule(Module *module) : - ir(FunctionalIR::from_module(module)), + ir(Functional::IR::from_module(module)), input_struct("Inputs"), output_struct("Outputs"), state_struct("State") @@ -222,7 +222,7 @@ struct CxxModule { locals.reserve("output"); locals.reserve("current_state"); locals.reserve("next_state"); - auto node_name = [&](FunctionalIR::Node n) { return locals(n.id(), n.name()); }; + auto node_name = [&](Functional::Node n) { return locals(n.id(), n.name()); }; CxxPrintVisitor printVisitor(f, node_name, input_struct, state_struct); for (auto node : ir) { f.print("\t{} {} = ", CxxType(node.sort()).to_string(), node_name(node)); diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 0d2763d32..7fd6fe564 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -17,7 +17,7 @@ * */ -#include "kernel/functionalir.h" +#include "kernel/functional.h" #include "kernel/yosys.h" #include "kernel/sexpr.h" #include @@ -42,7 +42,7 @@ const char *reserved_keywords[] = { nullptr }; -struct SmtScope : public FunctionalTools::Scope { +struct SmtScope : public Functional::Scope { SmtScope() { for(const char **p = reserved_keywords; *p != nullptr; p++) reserve(*p); @@ -53,8 +53,8 @@ struct SmtScope : public FunctionalTools::Scope { }; struct SmtSort { - FunctionalIR::Sort sort; - SmtSort(FunctionalIR::Sort sort) : sort(sort) {} + Functional::Sort sort; + SmtSort(Functional::Sort sort) : sort(sort) {} SExpr to_sexpr() const { if(sort.is_memory()) { return list("Array", list("_", "BitVec", sort.addr_width()), list("_", "BitVec", sort.data_width())); @@ -116,8 +116,8 @@ std::string smt_const(RTLIL::Const const &c) { return s; } -struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { - using Node = FunctionalIR::Node; +struct SmtPrintVisitor : public Functional::AbstractVisitor { + using Node = Functional::Node; std::function n; SmtStruct &input_struct; SmtStruct &state_struct; @@ -183,7 +183,7 @@ struct SmtPrintVisitor : public FunctionalIR::AbstractVisitor { }; struct SmtModule { - FunctionalIR ir; + Functional::IR ir; SmtScope scope; std::string name; @@ -192,7 +192,7 @@ struct SmtModule { SmtStruct state_struct; SmtModule(Module *module) - : ir(FunctionalIR::from_module(module)) + : ir(Functional::IR::from_module(module)) , scope() , name(scope.unique_name(module->name)) , input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope) @@ -215,11 +215,11 @@ struct SmtModule { list(list("inputs", input_struct.name), list("state", state_struct.name)), list("Pair", output_struct.name, state_struct.name))); - auto inlined = [&](FunctionalIR::Node n) { - return n.fn() == FunctionalIR::Fn::constant; + auto inlined = [&](Functional::Node n) { + return n.fn() == Functional::Fn::constant; }; SmtPrintVisitor visitor(input_struct, state_struct); - auto node_to_sexpr = [&](FunctionalIR::Node n) -> SExpr { + auto node_to_sexpr = [&](Functional::Node n) -> SExpr { if(inlined(n)) return n.visit(visitor); else diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 5d9349276..83ea09d8d 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -18,7 +18,7 @@ */ #include "kernel/yosys.h" -#include "kernel/functionalir.h" +#include "kernel/functional.h" #include USING_YOSYS_NAMESPACE @@ -139,7 +139,7 @@ struct FunctionalTestGeneric : public Pass for (auto module : design->selected_modules()) { log("Dumping module `%s'.\n", module->name.c_str()); - auto fir = FunctionalIR::from_module(module); + auto fir = Functional::IR::from_module(module); for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; for(auto [name, sort] : fir.outputs()) diff --git a/kernel/compute_graph.h b/kernel/compute_graph.h new file mode 100644 index 000000000..aeba17f8c --- /dev/null +++ b/kernel/compute_graph.h @@ -0,0 +1,403 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef COMPUTE_GRAPH_H +#define COMPUTE_GRAPH_H + +#include +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +template< + typename Fn, // Function type (deduplicated across whole graph) + typename Attr = std::tuple<>, // Call attributes (present in every node) + typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node) + typename Key = std::tuple<> // Stable keys to refer to nodes +> +struct ComputeGraph +{ + struct Ref; +private: + + // Functions are deduplicated by assigning unique ids + idict functions; + + struct Node { + int fn_index; + int arg_offset; + int arg_count; + Attr attr; + + Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {} + + Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0) + : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {} + }; + + + std::vector nodes; + std::vector args; + dict keys_; + dict sparse_attrs; + +public: + template + struct BaseRef + { + protected: + friend struct ComputeGraph; + Graph *graph_; + int index_; + BaseRef(Graph *graph, int index) : graph_(graph), index_(index) { + log_assert(index_ >= 0); + check(); + } + + void check() const { log_assert(index_ < graph_->size()); } + + Node const &deref() const { check(); return graph_->nodes[index_]; } + + public: + ComputeGraph const &graph() const { return graph_; } + int index() const { return index_; } + + int size() const { return deref().arg_count; } + + BaseRef arg(int n) const + { + Node const &node = deref(); + log_assert(n >= 0 && n < node.arg_count); + return BaseRef(graph_, graph_->args[node.arg_offset + n]); + } + + std::vector::const_iterator arg_indices_cbegin() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset; + } + + std::vector::const_iterator arg_indices_cend() const + { + Node const &node = deref(); + return graph_->args.cbegin() + node.arg_offset + node.arg_count; + } + + Fn const &function() const { return graph_->functions[deref().fn_index]; } + Attr const &attr() const { return deref().attr; } + + bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); } + + SparseAttr const &sparse_attr() const + { + auto found = graph_->sparse_attrs.find(index_); + log_assert(found != graph_->sparse_attrs.end()); + return found->second; + } + }; + + using ConstRef = BaseRef; + + struct Ref : public BaseRef + { + private: + friend struct ComputeGraph; + Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} + Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } + + public: + Ref(BaseRef ref) : Ref(ref.graph_, ref.index_) {} + + void set_function(Fn const &function) const + { + deref().fn_index = this->graph_->functions(function); + } + + Attr &attr() const { return deref().attr; } + + void append_arg(ConstRef arg) const + { + log_assert(arg.graph_ == this->graph_); + append_arg(arg.index()); + } + + void append_arg(int arg) const + { + log_assert(arg >= 0 && arg < this->graph_->size()); + Node &node = deref(); + if (node.arg_offset + node.arg_count != GetSize(this->graph_->args)) + move_args(node); + this->graph_->args.push_back(arg); + node.arg_count++; + } + + operator ConstRef() const + { + return ConstRef(this->graph_, this->index_); + } + + SparseAttr &sparse_attr() const + { + return this->graph_->sparse_attrs[this->index_]; + } + + void clear_sparse_attr() const + { + this->graph_->sparse_attrs.erase(this->index_); + } + + void assign_key(Key const &key) const + { + this->graph_->keys_.emplace(key, this->index_); + } + + private: + void move_args(Node &node) const + { + auto &args = this->graph_->args; + int old_offset = node.arg_offset; + node.arg_offset = GetSize(args); + for (int i = 0; i != node.arg_count; ++i) + args.push_back(args[old_offset + i]); + } + + }; + + bool has_key(Key const &key) const + { + return keys_.count(key); + } + + dict const &keys() const + { + return keys_; + } + + ConstRef operator()(Key const &key) const + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + Ref operator()(Key const &key) + { + auto it = keys_.find(key); + log_assert(it != keys_.end()); + return (*this)[it->second]; + } + + int size() const { return GetSize(nodes); } + + ConstRef operator[](int index) const { return ConstRef(this, index); } + Ref operator[](int index) { return Ref(this, index); } + + Ref add(Fn const &function, Attr &&attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, std::move(attr), GetSize(args)); + return Ref(this, index); + } + + Ref add(Fn const &function, Attr const &attr) + { + int index = GetSize(nodes); + int fn_index = functions(function); + nodes.emplace_back(fn_index, attr, GetSize(args)); + return Ref(this, index); + } + + template + Ref add(Fn const &function, Attr const &attr, T &&args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr &&attr, T &&args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + Ref add(Fn const &function, Attr const &attr, std::initializer_list args) + { + Ref added = add(function, attr); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + Ref add(Fn const &function, Attr &&attr, std::initializer_list args) + { + Ref added = add(function, std::move(attr)); + for (auto arg : args) + added.append_arg(arg); + return added; + } + + template + Ref add(Fn const &function, Attr const &attr, T begin, T end) + { + Ref added = add(function, attr); + for (; begin != end; ++begin) + added.append_arg(*begin); + return added; + } + + void compact_args() + { + std::vector new_args; + for (auto &node : nodes) + { + int new_offset = GetSize(new_args); + for (int i = 0; i < node.arg_count; i++) + new_args.push_back(args[node.arg_offset + i]); + node.arg_offset = new_offset; + } + std::swap(args, new_args); + } + + void permute(std::vector const &perm) + { + log_assert(perm.size() <= nodes.size()); + std::vector inv_perm; + inv_perm.resize(nodes.size(), -1); + for (int i = 0; i < GetSize(perm); ++i) + { + int j = perm[i]; + log_assert(j >= 0 && j < GetSize(nodes)); + log_assert(inv_perm[j] == -1); + inv_perm[j] = i; + } + permute(perm, inv_perm); + } + + void permute(std::vector const &perm, std::vector const &inv_perm) + { + log_assert(inv_perm.size() == nodes.size()); + std::vector new_nodes; + new_nodes.reserve(perm.size()); + dict new_sparse_attrs; + for (int i : perm) + { + int j = GetSize(new_nodes); + new_nodes.emplace_back(std::move(nodes[i])); + auto found = sparse_attrs.find(i); + if (found != sparse_attrs.end()) + new_sparse_attrs.emplace(j, std::move(found->second)); + } + + std::swap(nodes, new_nodes); + std::swap(sparse_attrs, new_sparse_attrs); + + compact_args(); + for (int &arg : args) + { + log_assert(arg < GetSize(inv_perm)); + log_assert(inv_perm[arg] >= 0); + arg = inv_perm[arg]; + } + + for (auto &key : keys_) + { + log_assert(key.second < GetSize(inv_perm)); + log_assert(inv_perm[key.second] >= 0); + key.second = inv_perm[key.second]; + } + } + + struct SccAdaptor + { + private: + ComputeGraph const &graph_; + std::vector indices_; + public: + SccAdaptor(ComputeGraph const &graph) : graph_(graph) + { + indices_.resize(graph.size(), -1); + } + + + typedef int node_type; + + struct node_enumerator { + private: + friend struct SccAdaptor; + int current, end; + node_enumerator(int current, int end) : current(current), end(end) {} + + public: + + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = current; + ++current; + return result; + } + }; + + node_enumerator enumerate_nodes() { + return node_enumerator(0, GetSize(indices_)); + } + + + struct successor_enumerator { + private: + friend struct SccAdaptor; + std::vector::const_iterator current, end; + successor_enumerator(std::vector::const_iterator current, std::vector::const_iterator end) : + current(current), end(end) {} + + public: + bool finished() const { return current == end; } + node_type next() { + log_assert(!finished()); + node_type result = *current; + ++current; + return result; + } + }; + + successor_enumerator enumerate_successors(int index) const { + auto const &ref = graph_[index]; + return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend()); + } + + int &dfs_index(node_type const &node) { return indices_[node]; } + + std::vector const &dfs_indices() { return indices_; } + }; + +}; + + + +YOSYS_NAMESPACE_END + + +#endif diff --git a/kernel/functionalir.cc b/kernel/functional.cc similarity index 90% rename from kernel/functionalir.cc rename to kernel/functional.cc index 223fdaa91..ad507187d 100644 --- a/kernel/functionalir.cc +++ b/kernel/functional.cc @@ -17,55 +17,55 @@ * */ -#include "kernel/functionalir.h" -#include +#include "kernel/functional.h" +#include "kernel/topo_scc.h" #include "ff.h" #include "ffinit.h" YOSYS_NAMESPACE_BEGIN +namespace Functional { -const char *FunctionalIR::fn_to_string(FunctionalIR::Fn fn) { +const char *fn_to_string(Fn fn) { switch(fn) { - case FunctionalIR::Fn::invalid: return "invalid"; - case FunctionalIR::Fn::buf: return "buf"; - case FunctionalIR::Fn::slice: return "slice"; - case FunctionalIR::Fn::zero_extend: return "zero_extend"; - case FunctionalIR::Fn::sign_extend: return "sign_extend"; - case FunctionalIR::Fn::concat: return "concat"; - case FunctionalIR::Fn::add: return "add"; - case FunctionalIR::Fn::sub: return "sub"; - case FunctionalIR::Fn::mul: return "mul"; - case FunctionalIR::Fn::unsigned_div: return "unsigned_div"; - case FunctionalIR::Fn::unsigned_mod: return "unsigned_mod"; - case FunctionalIR::Fn::bitwise_and: return "bitwise_and"; - case FunctionalIR::Fn::bitwise_or: return "bitwise_or"; - case FunctionalIR::Fn::bitwise_xor: return "bitwise_xor"; - case FunctionalIR::Fn::bitwise_not: return "bitwise_not"; - case FunctionalIR::Fn::reduce_and: return "reduce_and"; - case FunctionalIR::Fn::reduce_or: return "reduce_or"; - case FunctionalIR::Fn::reduce_xor: return "reduce_xor"; - case FunctionalIR::Fn::unary_minus: return "unary_minus"; - case FunctionalIR::Fn::equal: return "equal"; - case FunctionalIR::Fn::not_equal: return "not_equal"; - case FunctionalIR::Fn::signed_greater_than: return "signed_greater_than"; - case FunctionalIR::Fn::signed_greater_equal: return "signed_greater_equal"; - case FunctionalIR::Fn::unsigned_greater_than: return "unsigned_greater_than"; - case FunctionalIR::Fn::unsigned_greater_equal: return "unsigned_greater_equal"; - case FunctionalIR::Fn::logical_shift_left: return "logical_shift_left"; - case FunctionalIR::Fn::logical_shift_right: return "logical_shift_right"; - case FunctionalIR::Fn::arithmetic_shift_right: return "arithmetic_shift_right"; - case FunctionalIR::Fn::mux: return "mux"; - case FunctionalIR::Fn::constant: return "constant"; - case FunctionalIR::Fn::input: return "input"; - case FunctionalIR::Fn::state: return "state"; - case FunctionalIR::Fn::memory_read: return "memory_read"; - case FunctionalIR::Fn::memory_write: return "memory_write"; + case Fn::invalid: return "invalid"; + case Fn::buf: return "buf"; + case Fn::slice: return "slice"; + case Fn::zero_extend: return "zero_extend"; + case Fn::sign_extend: return "sign_extend"; + case Fn::concat: return "concat"; + case Fn::add: return "add"; + case Fn::sub: return "sub"; + case Fn::mul: return "mul"; + case Fn::unsigned_div: return "unsigned_div"; + case Fn::unsigned_mod: return "unsigned_mod"; + case Fn::bitwise_and: return "bitwise_and"; + case Fn::bitwise_or: return "bitwise_or"; + case Fn::bitwise_xor: return "bitwise_xor"; + case Fn::bitwise_not: return "bitwise_not"; + case Fn::reduce_and: return "reduce_and"; + case Fn::reduce_or: return "reduce_or"; + case Fn::reduce_xor: return "reduce_xor"; + case Fn::unary_minus: return "unary_minus"; + case Fn::equal: return "equal"; + case Fn::not_equal: return "not_equal"; + case Fn::signed_greater_than: return "signed_greater_than"; + case Fn::signed_greater_equal: return "signed_greater_equal"; + case Fn::unsigned_greater_than: return "unsigned_greater_than"; + case Fn::unsigned_greater_equal: return "unsigned_greater_equal"; + case Fn::logical_shift_left: return "logical_shift_left"; + case Fn::logical_shift_right: return "logical_shift_right"; + case Fn::arithmetic_shift_right: return "arithmetic_shift_right"; + case Fn::mux: return "mux"; + case Fn::constant: return "constant"; + case Fn::input: return "input"; + case Fn::state: return "state"; + case Fn::memory_read: return "memory_read"; + case Fn::memory_write: return "memory_write"; } - log_error("fn_to_string: unknown FunctionalIR::Fn value %d", (int)fn); + log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn); } -struct PrintVisitor : FunctionalIR::DefaultVisitor { - using Node = FunctionalIR::Node; +struct PrintVisitor : DefaultVisitor { std::function np; PrintVisitor(std::function np) : np(np) { } // as a general rule the default handler is good enough iff the only arguments are of type Node @@ -76,7 +76,7 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor { std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; } std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; } std::string default_handler(Node self) override { - std::string ret = FunctionalIR::fn_to_string(self.fn()); + std::string ret = fn_to_string(self.fn()); ret += "("; for(size_t i = 0; i < self.arg_count(); i++) { if(i > 0) ret += ", "; @@ -87,19 +87,18 @@ struct PrintVisitor : FunctionalIR::DefaultVisitor { } }; -std::string FunctionalIR::Node::to_string() +std::string Node::to_string() { return to_string([](Node n) { return RTLIL::unescape_id(n.name()); }); } -std::string FunctionalIR::Node::to_string(std::function np) +std::string Node::to_string(std::function np) { return visit(PrintVisitor(np)); } class CellSimplifier { - using Node = FunctionalIR::Node; - FunctionalIR::Factory &factory; + Factory &factory; Node sign(Node a) { return factory.slice(a, a.width() - 1, 1); } @@ -138,7 +137,7 @@ public: Node bb = factory.bitwise_and(b, s); return factory.bitwise_or(aa, bb); } - CellSimplifier(FunctionalIR::Factory &f) : factory(f) {} + CellSimplifier(Factory &f) : factory(f) {} private: Node handle_pow(Node a0, Node b, int y_width, bool is_signed) { Node a = factory.extend(a0, y_width, is_signed); @@ -400,12 +399,11 @@ public: }; class FunctionalIRConstruction { - using Node = FunctionalIR::Node; std::deque> queue; dict graph_nodes; dict, Node> cell_outputs; DriverMap driver_map; - FunctionalIR::Factory& factory; + Factory& factory; CellSimplifier simplifier; vector memories_vector; dict memories; @@ -442,7 +440,7 @@ class FunctionalIRConstruction { return it->second; } public: - FunctionalIRConstruction(Module *module, FunctionalIR::Factory &f) + FunctionalIRConstruction(Module *module, Factory &f) : factory(f) , simplifier(f) , sig_map(module) @@ -497,7 +495,7 @@ public: // - Since wr port j can only have priority over wr port i if j > i, if we do writes in // ascending index order the result will obey the priorty relation. vector read_results; - factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width)); + factory.add_state(mem->cell->name, Sort(ceil_log2(mem->size), mem->width)); factory.set_initial_state(mem->cell->name, MemContents(mem)); Node node = factory.current_state(mem->cell->name); for (size_t i = 0; i < mem->wr_ports.size(); i++) { @@ -542,7 +540,7 @@ public: if (!ff.has_gclk) log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " "Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell)); - factory.add_state(ff.name, FunctionalIR::Sort(ff.width)); + factory.add_state(ff.name, Sort(ff.width)); Node q_value = factory.current_state(ff.name); factory.suggest_name(q_value, ff.name); factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); @@ -643,8 +641,8 @@ public: } }; -FunctionalIR FunctionalIR::from_module(Module *module) { - FunctionalIR ir; +IR IR::from_module(Module *module) { + IR ir; auto factory = ir.factory(); FunctionalIRConstruction ctor(module, factory); ctor.process_queue(); @@ -653,7 +651,7 @@ FunctionalIR FunctionalIR::from_module(Module *module) { return ir; } -void FunctionalIR::topological_sort() { +void IR::topological_sort() { Graph::SccAdaptor compute_graph_scc(_graph); bool scc = false; std::vector perm; @@ -687,7 +685,7 @@ static IdString merge_name(IdString a, IdString b) { return a; } -void FunctionalIR::forward_buf() { +void IR::forward_buf() { std::vector perm, alias; perm.clear(); @@ -734,7 +732,7 @@ static std::string quote_fmt(const char *fmt) return r; } -void FunctionalTools::Writer::print_impl(const char *fmt, vector> &fns) +void Writer::print_impl(const char *fmt, vector> &fns) { size_t next_index = 0; for(const char *p = fmt; *p != 0; p++) @@ -770,4 +768,5 @@ void FunctionalTools::Writer::print_impl(const char *fmt, vector + * Copyright (C) 2024 Emily Schmidt * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -20,384 +20,571 @@ #ifndef FUNCTIONAL_H #define FUNCTIONAL_H -#include #include "kernel/yosys.h" +#include "kernel/compute_graph.h" +#include "kernel/drivertools.h" +#include "kernel/mem.h" +#include "kernel/utils.h" +USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN -template< - typename Fn, // Function type (deduplicated across whole graph) - typename Attr = std::tuple<>, // Call attributes (present in every node) - typename SparseAttr = std::tuple<>, // Sparse call attributes (optional per node) - typename Key = std::tuple<> // Stable keys to refer to nodes -> -struct ComputeGraph -{ - struct Ref; -private: - - // Functions are deduplicated by assigning unique ids - idict functions; - - struct Node { - int fn_index; - int arg_offset; - int arg_count; - Attr attr; - - Node(int fn_index, Attr &&attr, int arg_offset, int arg_count = 0) - : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(std::move(attr)) {} - - Node(int fn_index, Attr const &attr, int arg_offset, int arg_count = 0) - : fn_index(fn_index), arg_offset(arg_offset), arg_count(arg_count), attr(attr) {} - }; - - - std::vector nodes; - std::vector args; - dict keys_; - dict sparse_attrs; - -public: - template - struct BaseRef - { - protected: - friend struct ComputeGraph; - Graph *graph_; - int index_; - BaseRef(Graph *graph, int index) : graph_(graph), index_(index) { - log_assert(index_ >= 0); - check(); - } - - void check() const { log_assert(index_ < graph_->size()); } - - Node const &deref() const { check(); return graph_->nodes[index_]; } - - public: - ComputeGraph const &graph() const { return graph_; } - int index() const { return index_; } - - int size() const { return deref().arg_count; } - - BaseRef arg(int n) const - { - Node const &node = deref(); - log_assert(n >= 0 && n < node.arg_count); - return BaseRef(graph_, graph_->args[node.arg_offset + n]); - } - - std::vector::const_iterator arg_indices_cbegin() const - { - Node const &node = deref(); - return graph_->args.cbegin() + node.arg_offset; - } - - std::vector::const_iterator arg_indices_cend() const - { - Node const &node = deref(); - return graph_->args.cbegin() + node.arg_offset + node.arg_count; - } - - Fn const &function() const { return graph_->functions[deref().fn_index]; } - Attr const &attr() const { return deref().attr; } - - bool has_sparse_attr() const { return graph_->sparse_attrs.count(index_); } - - SparseAttr const &sparse_attr() const - { - auto found = graph_->sparse_attrs.find(index_); - log_assert(found != graph_->sparse_attrs.end()); - return found->second; - } - }; - - using ConstRef = BaseRef; - - struct Ref : public BaseRef - { - private: - friend struct ComputeGraph; - Ref(ComputeGraph *graph, int index) : BaseRef(graph, index) {} - Node &deref() const { this->check(); return this->graph_->nodes[this->index_]; } - - public: - Ref(BaseRef ref) : Ref(ref.graph_, ref.index_) {} - - void set_function(Fn const &function) const - { - deref().fn_index = this->graph_->functions(function); - } - - Attr &attr() const { return deref().attr; } - - void append_arg(ConstRef arg) const - { - log_assert(arg.graph_ == this->graph_); - append_arg(arg.index()); - } - - void append_arg(int arg) const - { - log_assert(arg >= 0 && arg < this->graph_->size()); - Node &node = deref(); - if (node.arg_offset + node.arg_count != GetSize(this->graph_->args)) - move_args(node); - this->graph_->args.push_back(arg); - node.arg_count++; - } - - operator ConstRef() const - { - return ConstRef(this->graph_, this->index_); - } - - SparseAttr &sparse_attr() const - { - return this->graph_->sparse_attrs[this->index_]; - } - - void clear_sparse_attr() const - { - this->graph_->sparse_attrs.erase(this->index_); - } - - void assign_key(Key const &key) const - { - this->graph_->keys_.emplace(key, this->index_); - } - - private: - void move_args(Node &node) const - { - auto &args = this->graph_->args; - int old_offset = node.arg_offset; - node.arg_offset = GetSize(args); - for (int i = 0; i != node.arg_count; ++i) - args.push_back(args[old_offset + i]); - } - - }; - - bool has_key(Key const &key) const - { - return keys_.count(key); - } - - dict const &keys() const - { - return keys_; - } - - ConstRef operator()(Key const &key) const - { - auto it = keys_.find(key); - log_assert(it != keys_.end()); - return (*this)[it->second]; - } - - Ref operator()(Key const &key) - { - auto it = keys_.find(key); - log_assert(it != keys_.end()); - return (*this)[it->second]; - } - - int size() const { return GetSize(nodes); } - - ConstRef operator[](int index) const { return ConstRef(this, index); } - Ref operator[](int index) { return Ref(this, index); } - - Ref add(Fn const &function, Attr &&attr) - { - int index = GetSize(nodes); - int fn_index = functions(function); - nodes.emplace_back(fn_index, std::move(attr), GetSize(args)); - return Ref(this, index); - } - - Ref add(Fn const &function, Attr const &attr) - { - int index = GetSize(nodes); - int fn_index = functions(function); - nodes.emplace_back(fn_index, attr, GetSize(args)); - return Ref(this, index); - } - - template - Ref add(Fn const &function, Attr const &attr, T &&args) - { - Ref added = add(function, attr); - for (auto arg : args) - added.append_arg(arg); - return added; - } - - template - Ref add(Fn const &function, Attr &&attr, T &&args) - { - Ref added = add(function, std::move(attr)); - for (auto arg : args) - added.append_arg(arg); - return added; - } - - Ref add(Fn const &function, Attr const &attr, std::initializer_list args) - { - Ref added = add(function, attr); - for (auto arg : args) - added.append_arg(arg); - return added; - } - - Ref add(Fn const &function, Attr &&attr, std::initializer_list args) - { - Ref added = add(function, std::move(attr)); - for (auto arg : args) - added.append_arg(arg); - return added; - } - - template - Ref add(Fn const &function, Attr const &attr, T begin, T end) - { - Ref added = add(function, attr); - for (; begin != end; ++begin) - added.append_arg(*begin); - return added; - } - - void compact_args() - { - std::vector new_args; - for (auto &node : nodes) - { - int new_offset = GetSize(new_args); - for (int i = 0; i < node.arg_count; i++) - new_args.push_back(args[node.arg_offset + i]); - node.arg_offset = new_offset; - } - std::swap(args, new_args); - } - - void permute(std::vector const &perm) - { - log_assert(perm.size() <= nodes.size()); - std::vector inv_perm; - inv_perm.resize(nodes.size(), -1); - for (int i = 0; i < GetSize(perm); ++i) - { - int j = perm[i]; - log_assert(j >= 0 && j < GetSize(nodes)); - log_assert(inv_perm[j] == -1); - inv_perm[j] = i; - } - permute(perm, inv_perm); - } - - void permute(std::vector const &perm, std::vector const &inv_perm) - { - log_assert(inv_perm.size() == nodes.size()); - std::vector new_nodes; - new_nodes.reserve(perm.size()); - dict new_sparse_attrs; - for (int i : perm) - { - int j = GetSize(new_nodes); - new_nodes.emplace_back(std::move(nodes[i])); - auto found = sparse_attrs.find(i); - if (found != sparse_attrs.end()) - new_sparse_attrs.emplace(j, std::move(found->second)); - } - - std::swap(nodes, new_nodes); - std::swap(sparse_attrs, new_sparse_attrs); - - compact_args(); - for (int &arg : args) - { - log_assert(arg < GetSize(inv_perm)); - log_assert(inv_perm[arg] >= 0); - arg = inv_perm[arg]; - } - - for (auto &key : keys_) - { - log_assert(key.second < GetSize(inv_perm)); - log_assert(inv_perm[key.second] >= 0); - key.second = inv_perm[key.second]; - } - } - - struct SccAdaptor - { - private: - ComputeGraph const &graph_; - std::vector indices_; - public: - SccAdaptor(ComputeGraph const &graph) : graph_(graph) - { - indices_.resize(graph.size(), -1); - } - - - typedef int node_type; - - struct node_enumerator { - private: - friend struct SccAdaptor; - int current, end; - node_enumerator(int current, int end) : current(current), end(end) {} - - public: - - bool finished() const { return current == end; } - node_type next() { - log_assert(!finished()); - node_type result = current; - ++current; - return result; - } - }; - - node_enumerator enumerate_nodes() { - return node_enumerator(0, GetSize(indices_)); - } - - - struct successor_enumerator { - private: - friend struct SccAdaptor; - std::vector::const_iterator current, end; - successor_enumerator(std::vector::const_iterator current, std::vector::const_iterator end) : - current(current), end(end) {} - - public: - bool finished() const { return current == end; } - node_type next() { - log_assert(!finished()); - node_type result = *current; - ++current; - return result; - } - }; - - successor_enumerator enumerate_successors(int index) const { - auto const &ref = graph_[index]; - return successor_enumerator(ref.arg_indices_cbegin(), ref.arg_indices_cend()); - } - - int &dfs_index(node_type const &node) { return indices_[node]; } - - std::vector const &dfs_indices() { return indices_; } - }; - -}; - - +namespace Functional { + // each function is documented with a short pseudocode declaration or definition + // standard C/Verilog operators are used to describe the result + // + // the types used in this are: + // - bit[N]: a bitvector of N bits + // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend + // but is meant to indicate how the value is interpreted + // if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation + // - memory[N, M]: a memory with N address and M data bits + // - int: C++ int + // - Const[N]: yosys RTLIL::Const (with size() == N) + // - IdString: yosys IdString + // - any: used in documentation to indicate that the type is unconstrained + // + // nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int) + // additionally, they can carry a constant of type int, Const[N] or IdString + // each node has a 'sort' field that stores the type of the node + // slice, zero_extend, sign_extend use the type field to store out_width + enum class Fn { + // invalid() = known-invalid/shouldn't happen value + // TODO: maybe remove this and use e.g. std::optional instead? + invalid, + // buf(a: any): any = a + // no-op operation + // when constructing the compute graph we generate invalid buf() nodes as a placeholder + // and later insert the argument + buf, + // slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width] + // required: offset + out_width <= in_width + slice, + // zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended) + // required: out_width > in_width + zero_extend, + // sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended) + // required: out_width > in_width + sign_extend, + // concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax) + // concatenates two bitvectors, with a in the least significant position and b in the more significant position + concat, + // add(a: bit[N], b: bit[N]): bit[N] = a + b + add, + // sub(a: bit[N], b: bit[N]): bit[N] = a - b + sub, + // mul(a: bit[N], b: bit[N]): bit[N] = a * b + mul, + // unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b + unsigned_div, + // unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b + unsigned_mod, + // bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b + bitwise_and, + // bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b + bitwise_or, + // bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b + bitwise_xor, + // bitwise_not(a: bit[N]): bit[N] = ~a + bitwise_not, + // reduce_and(a: bit[N]): bit[1] = &a + reduce_and, + // reduce_or(a: bit[N]): bit[1] = |a + reduce_or, + // reduce_xor(a: bit[N]): bit[1] = ^a + reduce_xor, + // unary_minus(a: bit[N]): bit[N] = -a + unary_minus, + // equal(a: bit[N], b: bit[N]): bit[1] = (a == b) + equal, + // not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b) + not_equal, + // signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b) + signed_greater_than, + // signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b) + signed_greater_equal, + // unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b) + unsigned_greater_than, + // unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b) + unsigned_greater_equal, + // logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b + // required: M == clog2(N) + logical_shift_left, + // logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b + // required: M == clog2(N) + logical_shift_right, + // arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b + // required: M == clog2(N) + arithmetic_shift_right, + // mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a + mux, + // constant(a: Const[N]): bit[N] = a + constant, + // input(a: IdString): any + // returns the current value of the input with the specified name + input, + // state(a: IdString): any + // returns the current value of the state variable with the specified name + state, + // memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr] + memory_read, + // memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width] + // returns a copy of `memory` but with the value at `addr` changed to `data` + memory_write + }; + // returns the name of a Fn value, as a string literal + const char *fn_to_string(Fn); + // Sort represents the sort or type of a node + // currently the only two types are signal/bit and memory + class Sort { + std::variant> _v; + public: + explicit Sort(int width) : _v(width) { } + Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { } + bool is_signal() const { return _v.index() == 0; } + bool is_memory() const { return _v.index() == 1; } + // returns the width of a bitvector type, errors out for other types + int width() const { return std::get<0>(_v); } + // returns the address width of a bitvector type, errors out for other types + int addr_width() const { return std::get<1>(_v).first; } + // returns the data width of a bitvector type, errors out for other types + int data_width() const { return std::get<1>(_v).second; } + bool operator==(Sort const& other) const { return _v == other._v; } + unsigned int hash() const { return mkhash(_v); } + }; + class Factory; + class Node; + class IR { + friend class Factory; + friend class Node; + // one NodeData is stored per Node, containing the function and non-node arguments + // note that NodeData is deduplicated by ComputeGraph + class NodeData { + Fn _fn; + std::variant< + std::monostate, + RTLIL::Const, + IdString, + int + > _extra; + public: + NodeData() : _fn(Fn::invalid) {} + NodeData(Fn fn) : _fn(fn) {} + template NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward(extra)) {} + Fn fn() const { return _fn; } + const RTLIL::Const &as_const() const { return std::get(_extra); } + IdString as_idstring() const { return std::get(_extra); } + int as_int() const { return std::get(_extra); } + int hash() const { + return mkhash((unsigned int) _fn, mkhash(_extra)); + } + bool operator==(NodeData const &other) const { + return _fn == other._fn && _extra == other._extra; + } + }; + // Attr contains all the information about a note that should not be deduplicated + struct Attr { + Sort sort; + }; + // our specialised version of ComputeGraph + // the sparse_attr IdString stores a naming suggestion, retrieved with name() + // the key is currently used to identify the nodes that represent output and next state values + // the bool is true for next state values + using Graph = ComputeGraph>; + Graph _graph; + dict _input_sorts; + dict _output_sorts; + dict _state_sorts; + dict _initial_state_signal; + dict _initial_state_memory; + public: + static IR from_module(Module *module); + Factory factory(); + int size() const { return _graph.size(); } + Node operator[](int i); + void topological_sort(); + void forward_buf(); + dict inputs() const { return _input_sorts; } + dict outputs() const { return _output_sorts; } + dict state() const { return _state_sorts; } + RTLIL::Const const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); } + MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); } + Node get_output_node(IdString name); + Node get_state_next_node(IdString name); + class iterator { + friend class IR; + IR *_ir; + int _index; + iterator(IR *ir, int index) : _ir(ir), _index(index) {} + public: + using iterator_category = std::input_iterator_tag; + using value_type = Node; + using pointer = arrow_proxy; + using reference = Node; + using difference_type = ptrdiff_t; + Node operator*(); + iterator &operator++() { _index++; return *this; } + bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; } + bool operator==(iterator const &other) const { return !(*this != other); } + pointer operator->(); + // TODO: implement operator-> using the arrow_proxy class currently in mem.h + }; + iterator begin() { return iterator(this, 0); } + iterator end() { return iterator(this, _graph.size()); } + }; + // Node is an immutable reference to a FunctionalIR node + class Node { + friend class Factory; + friend class IR; + IR::Graph::ConstRef _ref; + explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { } + explicit operator IR::Graph::ConstRef() { return _ref; } + public: + // the node's index. may change if nodes are added or removed + int id() const { return _ref.index(); } + // a name suggestion for the node, which need not be unique + IdString name() const { + if(_ref.has_sparse_attr()) + return _ref.sparse_attr(); + else + return std::string("\\n") + std::to_string(id()); + } + Fn fn() const { return _ref.function().fn(); } + Sort sort() const { return _ref.attr().sort; } + // returns the width of a bitvector node, errors out for other nodes + int width() const { return sort().width(); } + size_t arg_count() const { return _ref.size(); } + Node arg(int n) const { return Node(_ref.arg(n)); } + // visit calls the appropriate visitor method depending on the type of the node + template auto visit(Visitor v) const + { + // currently templated but could be switched to AbstractVisitor & + switch(_ref.function().fn()) { + case Fn::invalid: log_error("invalid node in visit"); break; + case Fn::buf: return v.buf(*this, arg(0)); break; + case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break; + case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break; + case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break; + case Fn::concat: return v.concat(*this, arg(0), arg(1)); break; + case Fn::add: return v.add(*this, arg(0), arg(1)); break; + case Fn::sub: return v.sub(*this, arg(0), arg(1)); break; + case Fn::mul: return v.mul(*this, arg(0), arg(1)); break; + case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break; + case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break; + case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break; + case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break; + case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break; + case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break; + case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break; + case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break; + case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break; + case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break; + case Fn::equal: return v.equal(*this, arg(0), arg(1)); break; + case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break; + case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; + case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break; + case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break; + case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; + case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break; + case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break; + case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; + case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; + case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; + case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; + case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; + } + } + std::string to_string(); + std::string to_string(std::function); + }; + inline Node IR::operator[](int i) { return Node(_graph[i]); } + inline Node IR::get_output_node(IdString name) { return Node(_graph({name, false})); } + inline Node IR::get_state_next_node(IdString name) { return Node(_graph({name, true})); } + inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); } + inline arrow_proxy IR::iterator::operator->() { return arrow_proxy(**this); } + // AbstractVisitor provides an abstract base class for visitors + template struct AbstractVisitor { + virtual T buf(Node self, Node n) = 0; + virtual T slice(Node self, Node a, int offset, int out_width) = 0; + virtual T zero_extend(Node self, Node a, int out_width) = 0; + virtual T sign_extend(Node self, Node a, int out_width) = 0; + virtual T concat(Node self, Node a, Node b) = 0; + virtual T add(Node self, Node a, Node b) = 0; + virtual T sub(Node self, Node a, Node b) = 0; + virtual T mul(Node self, Node a, Node b) = 0; + virtual T unsigned_div(Node self, Node a, Node b) = 0; + virtual T unsigned_mod(Node self, Node a, Node b) = 0; + virtual T bitwise_and(Node self, Node a, Node b) = 0; + virtual T bitwise_or(Node self, Node a, Node b) = 0; + virtual T bitwise_xor(Node self, Node a, Node b) = 0; + virtual T bitwise_not(Node self, Node a) = 0; + virtual T unary_minus(Node self, Node a) = 0; + virtual T reduce_and(Node self, Node a) = 0; + virtual T reduce_or(Node self, Node a) = 0; + virtual T reduce_xor(Node self, Node a) = 0; + virtual T equal(Node self, Node a, Node b) = 0; + virtual T not_equal(Node self, Node a, Node b) = 0; + virtual T signed_greater_than(Node self, Node a, Node b) = 0; + virtual T signed_greater_equal(Node self, Node a, Node b) = 0; + virtual T unsigned_greater_than(Node self, Node a, Node b) = 0; + virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0; + virtual T logical_shift_left(Node self, Node a, Node b) = 0; + virtual T logical_shift_right(Node self, Node a, Node b) = 0; + virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; + virtual T mux(Node self, Node a, Node b, Node s) = 0; + virtual T constant(Node self, RTLIL::Const const & value) = 0; + virtual T input(Node self, IdString name) = 0; + virtual T state(Node self, IdString name) = 0; + virtual T memory_read(Node self, Node mem, Node addr) = 0; + virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; + }; + // DefaultVisitor provides defaults for all visitor methods which just calls default_handler + template struct DefaultVisitor : public AbstractVisitor { + virtual T default_handler(Node self) = 0; + T buf(Node self, Node) override { return default_handler(self); } + T slice(Node self, Node, int, int) override { return default_handler(self); } + T zero_extend(Node self, Node, int) override { return default_handler(self); } + T sign_extend(Node self, Node, int) override { return default_handler(self); } + T concat(Node self, Node, Node) override { return default_handler(self); } + T add(Node self, Node, Node) override { return default_handler(self); } + T sub(Node self, Node, Node) override { return default_handler(self); } + T mul(Node self, Node, Node) override { return default_handler(self); } + T unsigned_div(Node self, Node, Node) override { return default_handler(self); } + T unsigned_mod(Node self, Node, Node) override { return default_handler(self); } + T bitwise_and(Node self, Node, Node) override { return default_handler(self); } + T bitwise_or(Node self, Node, Node) override { return default_handler(self); } + T bitwise_xor(Node self, Node, Node) override { return default_handler(self); } + T bitwise_not(Node self, Node) override { return default_handler(self); } + T unary_minus(Node self, Node) override { return default_handler(self); } + T reduce_and(Node self, Node) override { return default_handler(self); } + T reduce_or(Node self, Node) override { return default_handler(self); } + T reduce_xor(Node self, Node) override { return default_handler(self); } + T equal(Node self, Node, Node) override { return default_handler(self); } + T not_equal(Node self, Node, Node) override { return default_handler(self); } + T signed_greater_than(Node self, Node, Node) override { return default_handler(self); } + T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); } + T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); } + T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); } + T logical_shift_left(Node self, Node, Node) override { return default_handler(self); } + T logical_shift_right(Node self, Node, Node) override { return default_handler(self); } + T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } + T mux(Node self, Node, Node, Node) override { return default_handler(self); } + T constant(Node self, RTLIL::Const const &) override { return default_handler(self); } + T input(Node self, IdString) override { return default_handler(self); } + T state(Node self, IdString) override { return default_handler(self); } + T memory_read(Node self, Node, Node) override { return default_handler(self); } + T memory_write(Node self, Node, Node, Node) override { return default_handler(self); } + }; + // a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes. + class Factory { + friend class IR; + IR &_ir; + explicit Factory(IR &ir) : _ir(ir) {} + Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list args) { + log_assert(!sort.is_signal() || sort.width() > 0); + log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0); + IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); + for (auto arg : args) + ref.append_arg(IR::Graph::ConstRef(arg)); + return Node(ref); + } + IR::Graph::Ref mutate(Node n) { + return _ir._graph[n._ref.index()]; + } + void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } + void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); } + void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } + public: + Node slice(Node a, int offset, int out_width) { + log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); + if(offset == 0 && out_width == a.width()) + return a; + return add(IR::NodeData(Fn::slice, offset), Sort(out_width), {a}); + } + // extend will either extend or truncate the provided value to reach the desired width + Node extend(Node a, int out_width, bool is_signed) { + int in_width = a.sort().width(); + log_assert(a.sort().is_signal()); + if(in_width == out_width) + return a; + if(in_width > out_width) + return slice(a, 0, out_width); + if(is_signed) + return add(Fn::sign_extend, Sort(out_width), {a}); + else + return add(Fn::zero_extend, Sort(out_width), {a}); + } + Node concat(Node a, Node b) { + log_assert(a.sort().is_signal() && b.sort().is_signal()); + return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b}); + } + Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } + Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } + Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); } + Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); } + Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); } + Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } + Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } + Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } + Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } + Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } + Node reduce_and(Node a) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_and, Sort(1), {a}); + } + Node reduce_or(Node a) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_or, Sort(1), {a}); + } + Node reduce_xor(Node a) { + check_unary(a); + if(a.width() == 1) + return a; + return add(Fn::reduce_xor, Sort(1), {a}); + } + Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } + Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } + Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } + Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); } + Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); } + Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); } + Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); } + Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); } + Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); } + Node mux(Node a, Node b, Node s) { + log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1)); + return add(Fn::mux, a.sort(), {a, b, s}); + } + Node memory_read(Node mem, Node addr) { + log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width()); + return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr}); + } + Node memory_write(Node mem, Node addr, Node data) { + log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() && + mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width()); + return add(Fn::memory_write, mem.sort(), {mem, addr, data}); + } + Node constant(RTLIL::Const value) { + return add(IR::NodeData(Fn::constant, std::move(value)), Sort(value.size()), {}); + } + Node create_pending(int width) { + return add(Fn::buf, Sort(width), {}); + } + void update_pending(Node node, Node value) { + log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); + log_assert(node.sort() == value.sort()); + mutate(node).append_arg(value._ref); + } + void add_input(IdString name, int width) { + auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width)); + if (!inserted) log_error("input `%s` was re-defined", name.c_str()); + } + void add_output(IdString name, int width) { + auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width)); + if (!inserted) log_error("output `%s` was re-defined", name.c_str()); + } + void add_state(IdString name, Sort sort) { + auto [it, inserted] = _ir._state_sorts.emplace(name, sort); + if (!inserted) log_error("state `%s` was re-defined", name.c_str()); + } + Node input(IdString name) { + return add(IR::NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); + } + Node current_state(IdString name) { + return add(IR::NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); + } + void set_output(IdString output, Node value) { + log_assert(_ir._output_sorts.at(output) == value.sort()); + mutate(value).assign_key({output, false}); + } + void set_initial_state(IdString state, RTLIL::Const value) { + Sort &sort = _ir._state_sorts.at(state); + value.extu(sort.width()); + _ir._initial_state_signal.emplace(state, std::move(value)); + } + void set_initial_state(IdString state, MemContents value) { + log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state)); + _ir._initial_state_memory.emplace(state, std::move(value)); + } + void set_next_state(IdString state, Node value) { + log_assert(_ir._state_sorts.at(state) == value.sort()); + mutate(value).assign_key({state, true}); + } + void suggest_name(Node node, IdString name) { + mutate(node).sparse_attr() = name; + } + }; + inline Factory IR::factory() { return Factory(*this); } + template class Scope { + protected: + char substitution_character = '_'; + virtual bool is_character_legal(char) = 0; + private: + pool _used_names; + dict _by_id; + public: + void reserve(std::string name) { + _used_names.insert(std::move(name)); + } + std::string unique_name(IdString suggestion) { + std::string str = RTLIL::unescape_id(suggestion); + for(size_t i = 0; i < str.size(); i++) + if(!is_character_legal(str[i])) + str[i] = substitution_character; + if(_used_names.count(str) == 0) { + _used_names.insert(str); + return str; + } + for (int idx = 0 ; ; idx++){ + std::string suffixed = str + "_" + std::to_string(idx); + if(_used_names.count(suffixed) == 0) { + _used_names.insert(suffixed); + return suffixed; + } + } + } + std::string operator()(Id id, IdString suggestion) { + auto it = _by_id.find(id); + if(it != _by_id.end()) + return it->second; + std::string str = unique_name(suggestion); + _by_id.insert({id, str}); + return str; + } + }; + class Writer { + std::ostream *os; + void print_impl(const char *fmt, vector>& fns); + public: + Writer(std::ostream &os) : os(&os) {} + template Writer& operator <<(T&& arg) { *os << std::forward(arg); return *this; } + template + void print(const char *fmt, Args&&... args) + { + vector> fns { [&]() { *this << args; }... }; + print_impl(fmt, fns); + } + template + void print_with(Fn fn, const char *fmt, Args&&... args) + { + vector> fns { [&]() { + if constexpr (std::is_invocable_v) + *this << fn(args); + else + *this << args; }... + }; + print_impl(fmt, fns); + } + }; + +} YOSYS_NAMESPACE_END - #endif diff --git a/kernel/functionalir.h b/kernel/functionalir.h deleted file mode 100644 index fdbdcbde3..000000000 --- a/kernel/functionalir.h +++ /dev/null @@ -1,575 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2024 Emily Schmidt - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#ifndef FUNCTIONALIR_H -#define FUNCTIONALIR_H - -#include "kernel/yosys.h" -#include "kernel/functional.h" -#include "kernel/drivertools.h" -#include "kernel/mem.h" -#include "kernel/topo_scc.h" - -USING_YOSYS_NAMESPACE -YOSYS_NAMESPACE_BEGIN - -class FunctionalIR { -public: - // each function is documented with a short pseudocode declaration or definition - // standard C/Verilog operators are used to describe the result - // - // the types used in this are: - // - bit[N]: a bitvector of N bits - // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend - // but is meant to indicate how the value is interpreted - // if a bit[N] is marked as neither signed nor unsigned, this means the result should be valid with *either* interpretation - // - memory[N, M]: a memory with N address and M data bits - // - int: C++ int - // - Const[N]: yosys RTLIL::Const (with size() == N) - // - IdString: yosys IdString - // - any: used in documentation to indicate that the type is unconstrained - // - // nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int) - // additionally, they can carry a constant of type int, Const[N] or IdString - // each node has a 'sort' field that stores the type of the node - // slice, zero_extend, sign_extend use the type field to store out_width - enum class Fn { - // invalid() = known-invalid/shouldn't happen value - // TODO: maybe remove this and use e.g. std::optional instead? - invalid, - // buf(a: any): any = a - // no-op operation - // when constructing the compute graph we generate invalid buf() nodes as a placeholder - // and later insert the argument - buf, - // slice(a: bit[in_width], offset: int, out_width: int): bit[out_width] = a[offset +: out_width] - // required: offset + out_width <= in_width - slice, - // zero_extend(a: unsigned bit[in_width], out_width: int): unsigned bit[out_width] = a (zero extended) - // required: out_width > in_width - zero_extend, - // sign_extend(a: signed bit[in_width], out_width: int): signed bit[out_width] = a (sign extended) - // required: out_width > in_width - sign_extend, - // concat(a: bit[N], b: bit[M]): bit[N+M] = {b, a} (verilog syntax) - // concatenates two bitvectors, with a in the least significant position and b in the more significant position - concat, - // add(a: bit[N], b: bit[N]): bit[N] = a + b - add, - // sub(a: bit[N], b: bit[N]): bit[N] = a - b - sub, - // mul(a: bit[N], b: bit[N]): bit[N] = a * b - mul, - // unsigned_div(a: unsigned bit[N], b: unsigned bit[N]): bit[N] = a / b - unsigned_div, - // unsigned_mod(a: signed bit[N], b: signed bit[N]): bit[N] = a % b - unsigned_mod, - // bitwise_and(a: bit[N], b: bit[N]): bit[N] = a & b - bitwise_and, - // bitwise_or(a: bit[N], b: bit[N]): bit[N] = a | b - bitwise_or, - // bitwise_xor(a: bit[N], b: bit[N]): bit[N] = a ^ b - bitwise_xor, - // bitwise_not(a: bit[N]): bit[N] = ~a - bitwise_not, - // reduce_and(a: bit[N]): bit[1] = &a - reduce_and, - // reduce_or(a: bit[N]): bit[1] = |a - reduce_or, - // reduce_xor(a: bit[N]): bit[1] = ^a - reduce_xor, - // unary_minus(a: bit[N]): bit[N] = -a - unary_minus, - // equal(a: bit[N], b: bit[N]): bit[1] = (a == b) - equal, - // not_equal(a: bit[N], b: bit[N]): bit[1] = (a != b) - not_equal, - // signed_greater_than(a: signed bit[N], b: signed bit[N]): bit[1] = (a > b) - signed_greater_than, - // signed_greater_equal(a: signed bit[N], b: signed bit[N]): bit[1] = (a >= b) - signed_greater_equal, - // unsigned_greater_than(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a > b) - unsigned_greater_than, - // unsigned_greater_equal(a: unsigned bit[N], b: unsigned bit[N]): bit[1] = (a >= b) - unsigned_greater_equal, - // logical_shift_left(a: bit[N], b: unsigned bit[M]): bit[N] = a << b - // required: M == clog2(N) - logical_shift_left, - // logical_shift_right(a: unsigned bit[N], b: unsigned bit[M]): unsigned bit[N] = a >> b - // required: M == clog2(N) - logical_shift_right, - // arithmetic_shift_right(a: signed bit[N], b: unsigned bit[M]): signed bit[N] = a >> b - // required: M == clog2(N) - arithmetic_shift_right, - // mux(a: bit[N], b: bit[N], s: bit[1]): bit[N] = s ? b : a - mux, - // constant(a: Const[N]): bit[N] = a - constant, - // input(a: IdString): any - // returns the current value of the input with the specified name - input, - // state(a: IdString): any - // returns the current value of the state variable with the specified name - state, - // memory_read(memory: memory[addr_width, data_width], addr: bit[addr_width]): bit[data_width] = memory[addr] - memory_read, - // memory_write(memory: memory[addr_width, data_width], addr: bit[addr_width], data: bit[data_width]): memory[addr_width, data_width] - // returns a copy of `memory` but with the value at `addr` changed to `data` - memory_write - }; - // returns the name of a FunctionalIR::Fn value, as a string literal - static const char *fn_to_string(Fn); - // FunctionalIR::Sort represents the sort or type of a node - // currently the only two types are signal/bit and memory - class Sort { - std::variant> _v; - public: - explicit Sort(int width) : _v(width) { } - Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { } - bool is_signal() const { return _v.index() == 0; } - bool is_memory() const { return _v.index() == 1; } - // returns the width of a bitvector type, errors out for other types - int width() const { return std::get<0>(_v); } - // returns the address width of a bitvector type, errors out for other types - int addr_width() const { return std::get<1>(_v).first; } - // returns the data width of a bitvector type, errors out for other types - int data_width() const { return std::get<1>(_v).second; } - bool operator==(Sort const& other) const { return _v == other._v; } - unsigned int hash() const { return mkhash(_v); } - }; -private: - // one NodeData is stored per Node, containing the function and non-node arguments - // note that NodeData is deduplicated by ComputeGraph - class NodeData { - Fn _fn; - std::variant< - std::monostate, - RTLIL::Const, - IdString, - int - > _extra; - public: - NodeData() : _fn(Fn::invalid) {} - NodeData(Fn fn) : _fn(fn) {} - template NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward(extra)) {} - Fn fn() const { return _fn; } - const RTLIL::Const &as_const() const { return std::get(_extra); } - IdString as_idstring() const { return std::get(_extra); } - int as_int() const { return std::get(_extra); } - int hash() const { - return mkhash((unsigned int) _fn, mkhash(_extra)); - } - bool operator==(NodeData const &other) const { - return _fn == other._fn && _extra == other._extra; - } - }; - // Attr contains all the information about a note that should not be deduplicated - struct Attr { - Sort sort; - }; - // our specialised version of ComputeGraph - // the sparse_attr IdString stores a naming suggestion, retrieved with name() - // the key is currently used to identify the nodes that represent output and next state values - // the bool is true for next state values - using Graph = ComputeGraph>; - Graph _graph; - dict _input_sorts; - dict _output_sorts; - dict _state_sorts; - dict _initial_state_signal; - dict _initial_state_memory; -public: - class Factory; - // Node is an immutable reference to a FunctionalIR node - class Node { - friend class Factory; - friend class FunctionalIR; - Graph::ConstRef _ref; - explicit Node(Graph::ConstRef ref) : _ref(ref) { } - explicit operator Graph::ConstRef() { return _ref; } - public: - // the node's index. may change if nodes are added or removed - int id() const { return _ref.index(); } - // a name suggestion for the node, which need not be unique - IdString name() const { - if(_ref.has_sparse_attr()) - return _ref.sparse_attr(); - else - return std::string("\\n") + std::to_string(id()); - } - Fn fn() const { return _ref.function().fn(); } - Sort sort() const { return _ref.attr().sort; } - // returns the width of a bitvector node, errors out for other nodes - int width() const { return sort().width(); } - size_t arg_count() const { return _ref.size(); } - Node arg(int n) const { return Node(_ref.arg(n)); } - // visit calls the appropriate visitor method depending on the type of the node - template auto visit(Visitor v) const - { - // currently templated but could be switched to AbstractVisitor & - switch(_ref.function().fn()) { - case Fn::invalid: log_error("invalid node in visit"); break; - case Fn::buf: return v.buf(*this, arg(0)); break; - case Fn::slice: return v.slice(*this, arg(0), _ref.function().as_int(), sort().width()); break; - case Fn::zero_extend: return v.zero_extend(*this, arg(0), width()); break; - case Fn::sign_extend: return v.sign_extend(*this, arg(0), width()); break; - case Fn::concat: return v.concat(*this, arg(0), arg(1)); break; - case Fn::add: return v.add(*this, arg(0), arg(1)); break; - case Fn::sub: return v.sub(*this, arg(0), arg(1)); break; - case Fn::mul: return v.mul(*this, arg(0), arg(1)); break; - case Fn::unsigned_div: return v.unsigned_div(*this, arg(0), arg(1)); break; - case Fn::unsigned_mod: return v.unsigned_mod(*this, arg(0), arg(1)); break; - case Fn::bitwise_and: return v.bitwise_and(*this, arg(0), arg(1)); break; - case Fn::bitwise_or: return v.bitwise_or(*this, arg(0), arg(1)); break; - case Fn::bitwise_xor: return v.bitwise_xor(*this, arg(0), arg(1)); break; - case Fn::bitwise_not: return v.bitwise_not(*this, arg(0)); break; - case Fn::unary_minus: return v.unary_minus(*this, arg(0)); break; - case Fn::reduce_and: return v.reduce_and(*this, arg(0)); break; - case Fn::reduce_or: return v.reduce_or(*this, arg(0)); break; - case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break; - case Fn::equal: return v.equal(*this, arg(0), arg(1)); break; - case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break; - case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; - case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break; - case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; - case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break; - case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break; - case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; - case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break; - case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break; - case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; - case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; - case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; - case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; - case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; - } - } - std::string to_string(); - std::string to_string(std::function); - }; - // AbstractVisitor provides an abstract base class for visitors - template struct AbstractVisitor { - virtual T buf(Node self, Node n) = 0; - virtual T slice(Node self, Node a, int offset, int out_width) = 0; - virtual T zero_extend(Node self, Node a, int out_width) = 0; - virtual T sign_extend(Node self, Node a, int out_width) = 0; - virtual T concat(Node self, Node a, Node b) = 0; - virtual T add(Node self, Node a, Node b) = 0; - virtual T sub(Node self, Node a, Node b) = 0; - virtual T mul(Node self, Node a, Node b) = 0; - virtual T unsigned_div(Node self, Node a, Node b) = 0; - virtual T unsigned_mod(Node self, Node a, Node b) = 0; - virtual T bitwise_and(Node self, Node a, Node b) = 0; - virtual T bitwise_or(Node self, Node a, Node b) = 0; - virtual T bitwise_xor(Node self, Node a, Node b) = 0; - virtual T bitwise_not(Node self, Node a) = 0; - virtual T unary_minus(Node self, Node a) = 0; - virtual T reduce_and(Node self, Node a) = 0; - virtual T reduce_or(Node self, Node a) = 0; - virtual T reduce_xor(Node self, Node a) = 0; - virtual T equal(Node self, Node a, Node b) = 0; - virtual T not_equal(Node self, Node a, Node b) = 0; - virtual T signed_greater_than(Node self, Node a, Node b) = 0; - virtual T signed_greater_equal(Node self, Node a, Node b) = 0; - virtual T unsigned_greater_than(Node self, Node a, Node b) = 0; - virtual T unsigned_greater_equal(Node self, Node a, Node b) = 0; - virtual T logical_shift_left(Node self, Node a, Node b) = 0; - virtual T logical_shift_right(Node self, Node a, Node b) = 0; - virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; - virtual T mux(Node self, Node a, Node b, Node s) = 0; - virtual T constant(Node self, RTLIL::Const const & value) = 0; - virtual T input(Node self, IdString name) = 0; - virtual T state(Node self, IdString name) = 0; - virtual T memory_read(Node self, Node mem, Node addr) = 0; - virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; - }; - // DefaultVisitor provides defaults for all visitor methods which just calls default_handler - template struct DefaultVisitor : public AbstractVisitor { - virtual T default_handler(Node self) = 0; - T buf(Node self, Node) override { return default_handler(self); } - T slice(Node self, Node, int, int) override { return default_handler(self); } - T zero_extend(Node self, Node, int) override { return default_handler(self); } - T sign_extend(Node self, Node, int) override { return default_handler(self); } - T concat(Node self, Node, Node) override { return default_handler(self); } - T add(Node self, Node, Node) override { return default_handler(self); } - T sub(Node self, Node, Node) override { return default_handler(self); } - T mul(Node self, Node, Node) override { return default_handler(self); } - T unsigned_div(Node self, Node, Node) override { return default_handler(self); } - T unsigned_mod(Node self, Node, Node) override { return default_handler(self); } - T bitwise_and(Node self, Node, Node) override { return default_handler(self); } - T bitwise_or(Node self, Node, Node) override { return default_handler(self); } - T bitwise_xor(Node self, Node, Node) override { return default_handler(self); } - T bitwise_not(Node self, Node) override { return default_handler(self); } - T unary_minus(Node self, Node) override { return default_handler(self); } - T reduce_and(Node self, Node) override { return default_handler(self); } - T reduce_or(Node self, Node) override { return default_handler(self); } - T reduce_xor(Node self, Node) override { return default_handler(self); } - T equal(Node self, Node, Node) override { return default_handler(self); } - T not_equal(Node self, Node, Node) override { return default_handler(self); } - T signed_greater_than(Node self, Node, Node) override { return default_handler(self); } - T signed_greater_equal(Node self, Node, Node) override { return default_handler(self); } - T unsigned_greater_than(Node self, Node, Node) override { return default_handler(self); } - T unsigned_greater_equal(Node self, Node, Node) override { return default_handler(self); } - T logical_shift_left(Node self, Node, Node) override { return default_handler(self); } - T logical_shift_right(Node self, Node, Node) override { return default_handler(self); } - T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } - T mux(Node self, Node, Node, Node) override { return default_handler(self); } - T constant(Node self, RTLIL::Const const &) override { return default_handler(self); } - T input(Node self, IdString) override { return default_handler(self); } - T state(Node self, IdString) override { return default_handler(self); } - T memory_read(Node self, Node, Node) override { return default_handler(self); } - T memory_write(Node self, Node, Node, Node) override { return default_handler(self); } - }; - // a factory is used to modify a FunctionalIR. it creates new nodes and allows for some modification of existing nodes. - class Factory { - FunctionalIR &_ir; - friend class FunctionalIR; - explicit Factory(FunctionalIR &ir) : _ir(ir) {} - Node add(NodeData &&fn, Sort &&sort, std::initializer_list args) { - log_assert(!sort.is_signal() || sort.width() > 0); - log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0); - Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); - for (auto arg : args) - ref.append_arg(Graph::ConstRef(arg)); - return Node(ref); - } - Graph::Ref mutate(Node n) { - return _ir._graph[n._ref.index()]; - } - void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } - void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); } - void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } - public: - Node slice(Node a, int offset, int out_width) { - log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); - if(offset == 0 && out_width == a.width()) - return a; - return add(NodeData(Fn::slice, offset), Sort(out_width), {a}); - } - // extend will either extend or truncate the provided value to reach the desired width - Node extend(Node a, int out_width, bool is_signed) { - int in_width = a.sort().width(); - log_assert(a.sort().is_signal()); - if(in_width == out_width) - return a; - if(in_width > out_width) - return slice(a, 0, out_width); - if(is_signed) - return add(Fn::sign_extend, Sort(out_width), {a}); - else - return add(Fn::zero_extend, Sort(out_width), {a}); - } - Node concat(Node a, Node b) { - log_assert(a.sort().is_signal() && b.sort().is_signal()); - return add(Fn::concat, Sort(a.sort().width() + b.sort().width()), {a, b}); - } - Node add(Node a, Node b) { check_basic_binary(a, b); return add(Fn::add, a.sort(), {a, b}); } - Node sub(Node a, Node b) { check_basic_binary(a, b); return add(Fn::sub, a.sort(), {a, b}); } - Node mul(Node a, Node b) { check_basic_binary(a, b); return add(Fn::mul, a.sort(), {a, b}); } - Node unsigned_div(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_div, a.sort(), {a, b}); } - Node unsigned_mod(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_mod, a.sort(), {a, b}); } - Node bitwise_and(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_and, a.sort(), {a, b}); } - Node bitwise_or(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_or, a.sort(), {a, b}); } - Node bitwise_xor(Node a, Node b) { check_basic_binary(a, b); return add(Fn::bitwise_xor, a.sort(), {a, b}); } - Node bitwise_not(Node a) { check_unary(a); return add(Fn::bitwise_not, a.sort(), {a}); } - Node unary_minus(Node a) { check_unary(a); return add(Fn::unary_minus, a.sort(), {a}); } - Node reduce_and(Node a) { - check_unary(a); - if(a.width() == 1) - return a; - return add(Fn::reduce_and, Sort(1), {a}); - } - Node reduce_or(Node a) { - check_unary(a); - if(a.width() == 1) - return a; - return add(Fn::reduce_or, Sort(1), {a}); - } - Node reduce_xor(Node a) { - check_unary(a); - if(a.width() == 1) - return a; - return add(Fn::reduce_xor, Sort(1), {a}); - } - Node equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::equal, Sort(1), {a, b}); } - Node not_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::not_equal, Sort(1), {a, b}); } - Node signed_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_than, Sort(1), {a, b}); } - Node signed_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::signed_greater_equal, Sort(1), {a, b}); } - Node unsigned_greater_than(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_than, Sort(1), {a, b}); } - Node unsigned_greater_equal(Node a, Node b) { check_basic_binary(a, b); return add(Fn::unsigned_greater_equal, Sort(1), {a, b}); } - Node logical_shift_left(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_left, a.sort(), {a, b}); } - Node logical_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::logical_shift_right, a.sort(), {a, b}); } - Node arithmetic_shift_right(Node a, Node b) { check_shift(a, b); return add(Fn::arithmetic_shift_right, a.sort(), {a, b}); } - Node mux(Node a, Node b, Node s) { - log_assert(a.sort().is_signal() && a.sort() == b.sort() && s.sort() == Sort(1)); - return add(Fn::mux, a.sort(), {a, b, s}); - } - Node memory_read(Node mem, Node addr) { - log_assert(mem.sort().is_memory() && addr.sort().is_signal() && mem.sort().addr_width() == addr.sort().width()); - return add(Fn::memory_read, Sort(mem.sort().data_width()), {mem, addr}); - } - Node memory_write(Node mem, Node addr, Node data) { - log_assert(mem.sort().is_memory() && addr.sort().is_signal() && data.sort().is_signal() && - mem.sort().addr_width() == addr.sort().width() && mem.sort().data_width() == data.sort().width()); - return add(Fn::memory_write, mem.sort(), {mem, addr, data}); - } - Node constant(RTLIL::Const value) { - return add(NodeData(Fn::constant, std::move(value)), Sort(value.size()), {}); - } - Node create_pending(int width) { - return add(Fn::buf, Sort(width), {}); - } - void update_pending(Node node, Node value) { - log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); - log_assert(node.sort() == value.sort()); - mutate(node).append_arg(value._ref); - } - void add_input(IdString name, int width) { - auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width)); - if (!inserted) log_error("input `%s` was re-defined", name.c_str()); - } - void add_output(IdString name, int width) { - auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width)); - if (!inserted) log_error("output `%s` was re-defined", name.c_str()); - } - void add_state(IdString name, Sort sort) { - auto [it, inserted] = _ir._state_sorts.emplace(name, sort); - if (!inserted) log_error("state `%s` was re-defined", name.c_str()); - } - Node input(IdString name) { - return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); - } - Node current_state(IdString name) { - return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); - } - void set_output(IdString output, Node value) { - log_assert(_ir._output_sorts.at(output) == value.sort()); - mutate(value).assign_key({output, false}); - } - void set_initial_state(IdString state, RTLIL::Const value) { - Sort &sort = _ir._state_sorts.at(state); - value.extu(sort.width()); - _ir._initial_state_signal.emplace(state, std::move(value)); - } - void set_initial_state(IdString state, MemContents value) { - log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state)); - _ir._initial_state_memory.emplace(state, std::move(value)); - } - void set_next_state(IdString state, Node value) { - log_assert(_ir._state_sorts.at(state) == value.sort()); - mutate(value).assign_key({state, true}); - } - void suggest_name(Node node, IdString name) { - mutate(node).sparse_attr() = name; - } - }; - static FunctionalIR from_module(Module *module); - Factory factory() { return Factory(*this); } - int size() const { return _graph.size(); } - Node operator[](int i) { return Node(_graph[i]); } - void topological_sort(); - void forward_buf(); - dict inputs() const { return _input_sorts; } - dict outputs() const { return _output_sorts; } - dict state() const { return _state_sorts; } - RTLIL::Const const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); } - MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); } - Node get_output_node(IdString name) { return Node(_graph({name, false})); } - Node get_state_next_node(IdString name) { return Node(_graph({name, true})); } - class Iterator { - friend class FunctionalIR; - FunctionalIR *_ir; - int _index; - Iterator(FunctionalIR *ir, int index) : _ir(ir), _index(index) {} - public: - Node operator*() { return Node(_ir->_graph[_index]); } - Iterator &operator++() { _index++; return *this; } - bool operator!=(Iterator const &other) const { return _index != other._index; } - }; - Iterator begin() { return Iterator(this, 0); } - Iterator end() { return Iterator(this, _graph.size()); } -}; - -namespace FunctionalTools { - template class Scope { - protected: - char substitution_character = '_'; - virtual bool is_character_legal(char) = 0; - private: - pool _used_names; - dict _by_id; - public: - void reserve(std::string name) { - _used_names.insert(std::move(name)); - } - std::string unique_name(IdString suggestion) { - std::string str = RTLIL::unescape_id(suggestion); - for(size_t i = 0; i < str.size(); i++) - if(!is_character_legal(str[i])) - str[i] = substitution_character; - if(_used_names.count(str) == 0) { - _used_names.insert(str); - return str; - } - for (int idx = 0 ; ; idx++){ - std::string suffixed = str + "_" + std::to_string(idx); - if(_used_names.count(suffixed) == 0) { - _used_names.insert(suffixed); - return suffixed; - } - } - } - std::string operator()(Id id, IdString suggestion) { - auto it = _by_id.find(id); - if(it != _by_id.end()) - return it->second; - std::string str = unique_name(suggestion); - _by_id.insert({id, str}); - return str; - } - }; - class Writer { - std::ostream *os; - void print_impl(const char *fmt, vector>& fns); - public: - Writer(std::ostream &os) : os(&os) {} - template Writer& operator <<(T&& arg) { *os << std::forward(arg); return *this; } - template - void print(const char *fmt, Args&&... args) - { - vector> fns { [&]() { *this << args; }... }; - print_impl(fmt, fns); - } - template - void print_with(Fn fn, const char *fmt, Args&&... args) - { - vector> fns { [&]() { - if constexpr (std::is_invocable_v) - *this << fn(args); - else - *this << args; }... - }; - print_impl(fmt, fns); - } - }; -} - -YOSYS_NAMESPACE_END - -#endif diff --git a/kernel/mem.h b/kernel/mem.h index 4be4b6864..8c935adc1 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -22,6 +22,7 @@ #include "kernel/yosys.h" #include "kernel/ffinit.h" +#include "kernel/utils.h" YOSYS_NAMESPACE_BEGIN @@ -224,15 +225,6 @@ struct Mem : RTLIL::AttrObject { Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {} }; -// this class is used for implementing operator-> on iterators that return values rather than references -// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained -template -struct arrow_proxy { - T v; - explicit arrow_proxy(T const & v) : v(v) {} - T* operator->() { return &v; } -}; - // MemContents efficiently represents the contents of a potentially sparse memory by storing only those segments that are actually defined class MemContents { public: @@ -303,6 +295,7 @@ public: reference operator *() const { return range(_memory->_data_width, _addr, _memory->_values.at(_addr)); } pointer operator->() const { return arrow_proxy(**this); } bool operator !=(iterator const &other) const { return _memory != other._memory || _addr != other._addr; } + bool operator ==(iterator const &other) const { return !(*this != other); } iterator &operator++(); }; MemContents(int addr_width, int data_width, RTLIL::Const default_value) diff --git a/kernel/utils.h b/kernel/utils.h index 3216c5eb5..99f327db4 100644 --- a/kernel/utils.h +++ b/kernel/utils.h @@ -253,6 +253,15 @@ template , typename OPS = hash_ops> cla } }; +// this class is used for implementing operator-> on iterators that return values rather than references +// it's necessary because in C++ operator-> is called recursively until a raw pointer is obtained +template +struct arrow_proxy { + T v; + explicit arrow_proxy(T const & v) : v(v) {} + T* operator->() { return &v; } +}; + YOSYS_NAMESPACE_END #endif diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index 4b836d75b..aaf07dadd 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -1,7 +1,7 @@ #include "kernel/yosys.h" #include "kernel/drivertools.h" #include "kernel/topo_scc.h" -#include "kernel/functional.h" +#include "kernel/compute_graph.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From fbee31080e04ebef3ae99e1dfd876a93060c24d2 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 12:25:19 +0100 Subject: [PATCH 151/342] add optional header and hashlib implementation for optional --- kernel/hashlib.h | 12 ++++++++++++ kernel/yosys_common.h | 1 + 2 files changed, 13 insertions(+) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index d32db6832..157ccf4ce 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -205,6 +205,18 @@ template struct hash_ops> { } }; +template struct hash_ops> { + static inline bool cmp(std::optional a, std::optional b) { + return a == b; + } + static inline unsigned int hash(std::optional a) { + if(a.has_value()) + return mkhash(*a); + else + return 0; + } +}; + inline int hashtable_size(int min_size) { // Primes as generated by https://oeis.org/A175953 diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index e71e94a78..ec1b5aba2 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include From 8f774942635a09cd9a30733612d47a92b11fcbd5 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 12:54:58 +0100 Subject: [PATCH 152/342] silence some warnings --- kernel/drivertools.h | 8 +++++--- kernel/functional.h | 3 ++- kernel/mem.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 48c846b5f..b0e435f40 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -388,6 +388,8 @@ public: case DriveType::MULTIPLE: inner = multiple_.hash(); break; + default: + log_abort(); } return mkhash((unsigned int)type_, inner); } @@ -412,7 +414,7 @@ public: case DriveType::MULTIPLE: return multiple_ == other.multiple_; } - log_assert(false); + log_abort(); } bool operator!=(const DriveBit &other) const @@ -958,7 +960,7 @@ public: case DriveType::MULTIPLE: return multiple_ == other.multiple_; } - log_assert(false); + log_abort(); } bool operator!=(const DriveChunk &other) const @@ -985,7 +987,7 @@ public: case DriveType::MULTIPLE: return multiple_ < other.multiple_; } - log_assert(false); + log_abort(); } DriveType type() const { return type_; } diff --git a/kernel/functional.h b/kernel/functional.h index e0592259c..08b7b99ca 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -295,6 +295,7 @@ namespace Functional { case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; } + log_abort(); } std::string to_string(); std::string to_string(std::function); @@ -384,7 +385,7 @@ namespace Functional { explicit Factory(IR &ir) : _ir(ir) {} Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list args) { log_assert(!sort.is_signal() || sort.width() > 0); - log_assert(!sort.is_memory() || sort.addr_width() > 0 && sort.data_width() > 0); + log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0)); IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); for (auto arg : args) ref.append_arg(IR::Graph::ConstRef(arg)); diff --git a/kernel/mem.h b/kernel/mem.h index 8c935adc1..4a6a9a431 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -318,7 +318,7 @@ public: // insert multiple words at the given address, overriding any previous assignment. template void insert_range(addr_t addr, Iterator begin, Iterator end) { auto words = end - begin; - log_assert(addr < 1<<_addr_width); log_assert(words <= (1<<_addr_width) - addr); + log_assert(addr < (addr_t)(1<<_addr_width)); log_assert(words <= (addr_t)(1<<_addr_width) - addr); auto range = _reserve_range(addr, addr + words); auto it = _range_data(range, addr); for(; begin != end; ++begin) From 79a1b691ea159230ee5c3938f1e136a25fc896b0 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 25 Jul 2024 13:11:56 +0100 Subject: [PATCH 153/342] silence some more warnings, undo mistaken addition --- kernel/drivertools.h | 3 +-- kernel/mem.cc | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index b0e435f40..8a51b88d9 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -388,8 +388,6 @@ public: case DriveType::MULTIPLE: inner = multiple_.hash(); break; - default: - log_abort(); } return mkhash((unsigned int)type_, inner); } @@ -1028,6 +1026,7 @@ public: case DriveType::MULTIPLE: return multiple_.size(); } + log_abort(); } }; diff --git a/kernel/mem.cc b/kernel/mem.cc index 46e4331c5..80be52a0e 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -1729,8 +1729,8 @@ void MemContents::check() { log_assert(!it->second.empty()); log_assert(it->second.size() % _data_width == 0); auto end1 = _range_end(it); - log_assert(_range_begin(it) < (1<<_addr_width)); - log_assert(end1 <= (1<<_addr_width)); + log_assert(_range_begin(it) < (addr_t)(1<<_addr_width)); + log_assert(end1 <= (addr_t)(1<<_addr_width)); if(++it == _values.end()) break; // check that ranges neither overlap nor touch @@ -1760,7 +1760,7 @@ bool MemContents::_range_overlaps(std::map::iterator it, a std::map::iterator MemContents::_range_at(addr_t addr) const { // allow addr == 1<<_addr_width (which will just return end()) - log_assert(addr <= 1<<_addr_width); + log_assert(addr <= (addr_t)(1<<_addr_width)); // get the first range with base > addr // (we use const_cast since map::iterators are only passed around internally and not exposed to the user // and using map::iterator in both the const and non-const case simplifies the code a little, @@ -1879,8 +1879,8 @@ std::map::iterator MemContents::_reserve_range(addr_t begi void MemContents::insert_concatenated(addr_t addr, RTLIL::Const const &values) { addr_t words = (values.size() + _data_width - 1) / _data_width; - log_assert(addr < 1<<_addr_width); - log_assert(words <= (1<<_addr_width) - addr); + log_assert(addr < (addr_t)(1<<_addr_width)); + log_assert(words <= (addr_t)(1<<_addr_width) - addr); auto it = _reserve_range(addr, addr + words); auto to_begin = _range_data(it, addr); std::copy(values.bits.begin(), values.bits.end(), to_begin); From 50047d25b3806fb614c983a950de85b09db8fcfc Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 6 Aug 2024 09:56:28 +0100 Subject: [PATCH 154/342] functional backend: add different types of input/output/state variables --- backends/functional/cxx.cc | 38 +++---- backends/functional/smtlib.cc | 36 +++--- backends/functional/test_generic.cc | 8 +- kernel/functional.cc | 112 +++++++++++++++---- kernel/functional.h | 163 ++++++++++++++++++---------- 5 files changed, 237 insertions(+), 120 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index a4755e144..19740777f 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -150,8 +150,8 @@ template struct CxxPrintVisitor : public Functional::Abstract void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); } void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); } void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); } - void input(Node, IdString name) override { print("input.{}", input_struct[name]); } - void state(Node, IdString name) override { print("current_state.{}", state_struct[name]); } + void input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); print("input.{}", input_struct[name]); } + void state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); print("current_state.{}", state_struct[name]); } void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); } void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); } }; @@ -175,12 +175,12 @@ struct CxxModule { output_struct("Outputs"), state_struct("State") { - for (auto [name, sort] : ir.inputs()) - input_struct.insert(name, sort); - for (auto [name, sort] : ir.outputs()) - output_struct.insert(name, sort); - for (auto [name, sort] : ir.state()) - state_struct.insert(name, sort); + for (auto input : ir.inputs()) + input_struct.insert(input->name, input->sort); + for (auto output : ir.outputs()) + output_struct.insert(output->name, output->sort); + for (auto state : ir.states()) + state_struct.insert(state->name, state->sort); module_name = CxxScope().unique_name(module->name); } void write_header(CxxWriter &f) { @@ -197,19 +197,19 @@ struct CxxModule { } void write_initial_def(CxxWriter &f) { f.print("void {0}::initialize({0}::State &state)\n{{\n", module_name); - for (auto [name, sort] : ir.state()) { - if (sort.is_signal()) - f.print("\tstate.{} = {};\n", state_struct[name], cxx_const(ir.get_initial_state_signal(name))); - else if (sort.is_memory()) { + for (auto state : ir.states()) { + if (state->sort.is_signal()) + f.print("\tstate.{} = {};\n", state_struct[state->name], cxx_const(state->initial_value_signal())); + else if (state->sort.is_memory()) { f.print("\t{{\n"); - f.print("\t\tstd::array, {}> mem;\n", sort.data_width(), 1<, {}> mem;\n", state->sort.data_width(), 1<sort.addr_width()); + const auto &contents = state->initial_value_memory(); f.print("\t\tmem.fill({});\n", cxx_const(contents.default_value())); for(auto range : contents) for(auto addr = range.base(); addr < range.limit(); addr++) if(!equal_def(range[addr], contents.default_value())) f.print("\t\tmem[{}] = {};\n", addr, cxx_const(range[addr])); - f.print("\t\tstate.{} = mem;\n", state_struct[name]); + f.print("\t\tstate.{} = mem;\n", state_struct[state->name]); f.print("\t}}\n"); } } @@ -229,10 +229,10 @@ struct CxxModule { node.visit(printVisitor); f.print(";\n"); } - for (auto [name, sort] : ir.state()) - f.print("\tnext_state.{} = {};\n", state_struct[name], node_name(ir.get_state_next_node(name))); - for (auto [name, sort] : ir.outputs()) - f.print("\toutput.{} = {};\n", output_struct[name], node_name(ir.get_output_node(name))); + for (auto state : ir.states()) + f.print("\tnext_state.{} = {};\n", state_struct[state->name], node_name(state->next_value())); + for (auto output : ir.outputs()) + f.print("\toutput.{} = {};\n", output_struct[output->name], node_name(output->value())); f.print("}}\n\n"); } }; diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 7fd6fe564..ec9e6b242 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -178,8 +178,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor { SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); } SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); } - SExpr input(Node, IdString name) override { return input_struct.access("inputs", name); } - SExpr state(Node, IdString name) override { return state_struct.access("state", name); } + SExpr input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); return input_struct.access("inputs", name); } + SExpr state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); return state_struct.access("state", name); } }; struct SmtModule { @@ -200,12 +200,12 @@ struct SmtModule { , state_struct(scope.unique_name(module->name.str() + "_State"), scope) { scope.reserve(name + "-initial"); - for (const auto &input : ir.inputs()) - input_struct.insert(input.first, input.second); - for (const auto &output : ir.outputs()) - output_struct.insert(output.first, output.second); - for (const auto &state : ir.state()) - state_struct.insert(state.first, state.second); + for (auto input : ir.inputs()) + input_struct.insert(input->name, input->sort); + for (auto output : ir.outputs()) + output_struct.insert(output->name, output->sort); + for (auto state : ir.states()) + state_struct.insert(state->name, state->sort); } void write_eval(SExprWriter &w) @@ -232,8 +232,8 @@ struct SmtModule { w.comment(SmtSort(n.sort()).to_sexpr().to_string(), true); } w.open(list("pair")); - output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_output_node(name)); }); - state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.get_state_next_node(name)); }); + output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.output(name).value()); }); + state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.state(name).next_value()); }); w.pop(); } @@ -241,14 +241,14 @@ struct SmtModule { { std::string initial = name + "-initial"; w << list("declare-const", initial, state_struct.name); - for (const auto &[name, sort] : ir.state()) { - if(sort.is_signal()) - w << list("assert", list("=", state_struct.access(initial, name), smt_const(ir.get_initial_state_signal(name)))); - else if(sort.is_memory()) { - auto contents = ir.get_initial_state_memory(name); - for(int i = 0; i < 1<sort.is_signal()) + w << list("assert", list("=", state_struct.access(initial, state->name), smt_const(state->initial_value_signal()))); + else if(state->sort.is_memory()) { + const auto &contents = state->initial_value_memory(); + for(int i = 0; i < 1<sort.addr_width(); i++) { + auto addr = smt_const(RTLIL::Const(i, state->sort.addr_width())); + w << list("assert", list("=", list("select", state_struct.access(initial, state->name), addr), smt_const(contents[i]))); } } } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 83ea09d8d..1617d54c0 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -142,10 +142,10 @@ struct FunctionalTestGeneric : public Pass auto fir = Functional::IR::from_module(module); for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; - for(auto [name, sort] : fir.outputs()) - std::cout << "output " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_output_node(name).name()) << "\n"; - for(auto [name, sort] : fir.state()) - std::cout << "state " << RTLIL::unescape_id(name) << " = " << RTLIL::unescape_id(fir.get_state_next_node(name).name()) << "\n"; + for(auto output : fir.all_outputs()) + std::cout << RTLIL::unescape_id(output->type) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n"; + for(auto state : fir.all_states()) + std::cout << RTLIL::unescape_id(state->type) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n"; } } } FunctionalCxxBackend; diff --git a/kernel/functional.cc b/kernel/functional.cc index ad507187d..202eaa502 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -65,6 +65,51 @@ const char *fn_to_string(Fn fn) { log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn); } +vector IR::inputs(IdString type) const { + vector ret; + for (const auto &[name, input] : _inputs) + if(input.type == type) + ret.push_back(&input); + return ret; +} + +vector IR::outputs(IdString type) const { + vector ret; + for (const auto &[name, output] : _outputs) + if(output.type == type) + ret.push_back(&output); + return ret; +} + +vector IR::states(IdString type) const { + vector ret; + for (const auto &[name, state] : _states) + if(state.type == type) + ret.push_back(&state); + return ret; +} + +vector IR::all_inputs() const { + vector ret; + for (const auto &[name, input] : _inputs) + ret.push_back(&input); + return ret; +} + +vector IR::all_outputs() const { + vector ret; + for (const auto &[name, output] : _outputs) + ret.push_back(&output); + return ret; +} + +vector IR::all_states() const { + vector ret; + for (const auto &[name, state] : _states) + ret.push_back(&state); + return ret; +} + struct PrintVisitor : DefaultVisitor { std::function np; PrintVisitor(std::function np) : np(np) { } @@ -73,8 +118,8 @@ struct PrintVisitor : DefaultVisitor { std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; } - std::string input(Node, IdString name) override { return "input(" + name.str() + ")"; } - std::string state(Node, IdString name) override { return "state(" + name.str() + ")"; } + std::string input(Node, IdString name, IdString type) override { return "input(" + name.str() + ", " + type.str() + ")"; } + std::string state(Node, IdString name, IdString type) override { return "state(" + name.str() + ", " + type.str() + ")"; } std::string default_handler(Node self) override { std::string ret = fn_to_string(self.fn()); ret += "("; @@ -199,7 +244,7 @@ private: return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO)); } public: - std::variant, Node> handle(IdString cellType, dict parameters, dict inputs) + std::variant, Node> handle(IdString cellName, IdString cellType, dict parameters, dict inputs) { int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); @@ -392,6 +437,26 @@ public: return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI))); } else if(cellType == ID($alu)) { return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI))); + } else if(cellType.in({ID($assert), ID($assume), ID($live), ID($fair), ID($cover)})) { + Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(ID(A)), inputs.at(ID(EN))); + auto &output = factory.add_output(cellName, cellType, Sort(1)); + output.set_value(a); + return {}; + } else if(cellType.in({ID($anyconst), ID($allconst), ID($anyseq), ID($allseq)})) { + int width = parameters.at(ID(WIDTH)).as_int(); + auto &input = factory.add_input(cellName, cellType, Sort(width)); + return factory.value(input); + } else if(cellType == ID($initstate)) { + if(factory.ir().has_state(ID($initstate), ID($state))) + return factory.value(factory.ir().state(ID($initstate))); + else { + auto &state = factory.add_state(ID($initstate), ID($state), Sort(1)); + state.set_initial_value(RTLIL::Const(State::S1, 1)); + state.set_next_value(factory.constant(RTLIL::Const(State::S0, 1))); + return factory.value(state); + } + } else if(cellType == ID($check)) { + log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName.c_str()); } else { log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str()); } @@ -448,16 +513,15 @@ public: { driver_map.add(module); for (auto cell : module->cells()) { - if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check))) + if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover), ID($check))) queue.emplace_back(cell); } for (auto wire : module->wires()) { if (wire->port_input) - factory.add_input(wire->name, wire->width); + factory.add_input(wire->name, ID($input), Sort(wire->width)); if (wire->port_output) { - factory.add_output(wire->name, wire->width); - Node value = enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width))); - factory.set_output(wire->name, value); + auto &output = factory.add_output(wire->name, ID($output), Sort(wire->width)); + output.set_value(enqueue(DriveChunk(DriveChunkWire(wire, 0, wire->width)))); } } memories_vector = Mem::get_all_memories(module); @@ -495,9 +559,9 @@ public: // - Since wr port j can only have priority over wr port i if j > i, if we do writes in // ascending index order the result will obey the priorty relation. vector read_results; - factory.add_state(mem->cell->name, Sort(ceil_log2(mem->size), mem->width)); - factory.set_initial_state(mem->cell->name, MemContents(mem)); - Node node = factory.current_state(mem->cell->name); + auto &state = factory.add_state(mem->cell->name, ID($state), Sort(ceil_log2(mem->size), mem->width)); + state.set_initial_value(MemContents(mem)); + Node node = factory.value(state); for (size_t i = 0; i < mem->wr_ports.size(); i++) { const auto &wr = mem->wr_ports[i]; if (wr.clk_enable) @@ -521,7 +585,7 @@ public: Node addr = enqueue(driver_map(DriveSpec(rd.addr))); read_results.push_back(factory.memory_read(node, addr)); } - factory.set_next_state(mem->cell->name, node); + state.set_next_value(node); return concatenate_read_results(mem, read_results); } void process_cell(Cell *cell) @@ -540,25 +604,25 @@ public: if (!ff.has_gclk) log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " "Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell)); - factory.add_state(ff.name, Sort(ff.width)); - Node q_value = factory.current_state(ff.name); + auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width)); + Node q_value = factory.value(state); factory.suggest_name(q_value, ff.name); factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); - factory.set_next_state(ff.name, enqueue(ff.sig_d)); - factory.set_initial_state(ff.name, ff.val_init); + state.set_next_value(enqueue(ff.sig_d)); + state.set_initial_value(ff.val_init); } else { dict connections; IdString output_name; // for the single output case int n_outputs = 0; for(auto const &[name, sigspec] : cell->connections()) { - if(driver_map.celltypes.cell_input(cell->type, name)) + if(driver_map.celltypes.cell_input(cell->type, name) && sigspec.size() > 0) connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) }); if(driver_map.celltypes.cell_output(cell->type, name)) { output_name = name; n_outputs++; } } - std::variant, Node> outputs = simplifier.handle(cell->type, cell->parameters, connections); + std::variant, Node> outputs = simplifier.handle(cell->name, cell->type, cell->parameters, connections); if(auto *nodep = std::get_if(&outputs); nodep != nullptr) { log_assert(n_outputs == 1); factory.update_pending(cell_outputs.at({cell, output_name}), *nodep); @@ -591,7 +655,7 @@ public: DriveChunkWire wire_chunk = chunk.wire(); if (wire_chunk.is_whole()) { if (wire_chunk.wire->port_input) { - Node node = factory.input(wire_chunk.wire->name); + Node node = factory.value(factory.ir().input(wire_chunk.wire->name)); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); } else { @@ -668,10 +732,12 @@ void IR::topological_sort() { scc = true; } }); - for(const auto &[name, sort]: _state_sorts) - toposort.process(get_state_next_node(name).id()); - for(const auto &[name, sort]: _output_sorts) - toposort.process(get_output_node(name).id()); + for(const auto &[name, state]: _states) + if(state.has_next_value()) + toposort.process(state.next_value().id()); + for(const auto &[name, output]: _outputs) + if(output.has_value()) + toposort.process(output.value().id()); // any nodes untouched by this point are dead code and will be removed by permute _graph.permute(perm); if(scc) log_error("The design contains combinational loops. This is not supported by the functional backend. " diff --git a/kernel/functional.h b/kernel/functional.h index 08b7b99ca..f7ff08228 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -152,11 +152,60 @@ namespace Functional { bool operator==(Sort const& other) const { return _v == other._v; } unsigned int hash() const { return mkhash(_v); } }; + class IR; class Factory; class Node; + class IRInput { + friend class Factory; + public: + IdString name; + IdString type; + Sort sort; + private: + IRInput(IR &, IdString name, IdString type, Sort sort) + : name(name), type(type), sort(std::move(sort)) {} + }; + class IROutput { + friend class Factory; + IR &_ir; + public: + IdString name; + IdString type; + Sort sort; + private: + IROutput(IR &ir, IdString name, IdString type, Sort sort) + : _ir(ir), name(name), type(type), sort(std::move(sort)) {} + public: + Node value() const; + bool has_value() const; + void set_value(Node value); + }; + class IRState { + friend class Factory; + IR &_ir; + public: + IdString name; + IdString type; + Sort sort; + private: + std::variant _initial; + IRState(IR &ir, IdString name, IdString type, Sort sort) + : _ir(ir), name(name), type(type), sort(std::move(sort)) {} + public: + Node next_value() const; + bool has_next_value() const; + RTLIL::Const const& initial_value_signal() const { return std::get(_initial); } + MemContents const& initial_value_memory() const { return std::get(_initial); } + void set_next_value(Node value); + void set_initial_value(RTLIL::Const value) { value.extu(sort.width()); _initial = std::move(value); } + void set_initial_value(MemContents value) { log_assert(Sort(value.addr_width(), value.data_width()) == sort); _initial = std::move(value); } + }; class IR { friend class Factory; friend class Node; + friend class IRInput; + friend class IROutput; + friend class IRState; // one NodeData is stored per Node, containing the function and non-node arguments // note that NodeData is deduplicated by ComputeGraph class NodeData { @@ -164,7 +213,7 @@ namespace Functional { std::variant< std::monostate, RTLIL::Const, - IdString, + std::pair, int > _extra; public: @@ -173,7 +222,7 @@ namespace Functional { template NodeData(Fn fn, T &&extra) : _fn(fn), _extra(std::forward(extra)) {} Fn fn() const { return _fn; } const RTLIL::Const &as_const() const { return std::get(_extra); } - IdString as_idstring() const { return std::get(_extra); } + std::pair as_idstring_pair() const { return std::get>(_extra); } int as_int() const { return std::get(_extra); } int hash() const { return mkhash((unsigned int) _fn, mkhash(_extra)); @@ -190,13 +239,12 @@ namespace Functional { // the sparse_attr IdString stores a naming suggestion, retrieved with name() // the key is currently used to identify the nodes that represent output and next state values // the bool is true for next state values - using Graph = ComputeGraph>; + using Graph = ComputeGraph>; Graph _graph; - dict _input_sorts; - dict _output_sorts; - dict _state_sorts; - dict _initial_state_signal; - dict _initial_state_memory; + dict, IRInput> _inputs; + dict, IROutput> _outputs; + dict, IRState> _states; + IR::Graph::Ref mutate(Node n); public: static IR from_module(Module *module); Factory factory(); @@ -204,13 +252,24 @@ namespace Functional { Node operator[](int i); void topological_sort(); void forward_buf(); - dict inputs() const { return _input_sorts; } - dict outputs() const { return _output_sorts; } - dict state() const { return _state_sorts; } - RTLIL::Const const &get_initial_state_signal(IdString name) { return _initial_state_signal.at(name); } - MemContents const &get_initial_state_memory(IdString name) { return _initial_state_memory.at(name); } - Node get_output_node(IdString name); - Node get_state_next_node(IdString name); + IRInput const& input(IdString name, IdString type) const { return _inputs.at({name, type}); } + IRInput const& input(IdString name) const { return input(name, ID($input)); } + IROutput const& output(IdString name, IdString type) const { return _outputs.at({name, type}); } + IROutput const& output(IdString name) const { return output(name, ID($output)); } + IRState const& state(IdString name, IdString type) const { return _states.at({name, type}); } + IRState const& state(IdString name) const { return state(name, ID($state)); } + bool has_input(IdString name, IdString type) const { return _inputs.count({name, type}); } + bool has_output(IdString name, IdString type) const { return _outputs.count({name, type}); } + bool has_state(IdString name, IdString type) const { return _states.count({name, type}); } + vector inputs(IdString type) const; + vector inputs() const { return inputs(ID($input)); } + vector outputs(IdString type) const; + vector outputs() const { return outputs(ID($output)); } + vector states(IdString type) const; + vector states() const { return states(ID($state)); } + vector all_inputs() const; + vector all_outputs() const; + vector all_states() const; class iterator { friend class IR; IR *_ir; @@ -236,6 +295,9 @@ namespace Functional { class Node { friend class Factory; friend class IR; + friend class IRInput; + friend class IROutput; + friend class IRState; IR::Graph::ConstRef _ref; explicit Node(IR::Graph::ConstRef ref) : _ref(ref) { } explicit operator IR::Graph::ConstRef() { return _ref; } @@ -290,8 +352,8 @@ namespace Functional { case Fn::arithmetic_shift_right: return v.arithmetic_shift_right(*this, arg(0), arg(1)); break; case Fn::mux: return v.mux(*this, arg(0), arg(1), arg(2)); break; case Fn::constant: return v.constant(*this, _ref.function().as_const()); break; - case Fn::input: return v.input(*this, _ref.function().as_idstring()); break; - case Fn::state: return v.state(*this, _ref.function().as_idstring()); break; + case Fn::input: return v.input(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break; + case Fn::state: return v.state(*this, _ref.function().as_idstring_pair().first, _ref.function().as_idstring_pair().second); break; case Fn::memory_read: return v.memory_read(*this, arg(0), arg(1)); break; case Fn::memory_write: return v.memory_write(*this, arg(0), arg(1), arg(2)); break; } @@ -300,9 +362,14 @@ namespace Functional { std::string to_string(); std::string to_string(std::function); }; + inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; } inline Node IR::operator[](int i) { return Node(_graph[i]); } - inline Node IR::get_output_node(IdString name) { return Node(_graph({name, false})); } - inline Node IR::get_state_next_node(IdString name) { return Node(_graph({name, true})); } + inline Node IROutput::value() const { return Node(_ir._graph({name, type, false})); } + inline bool IROutput::has_value() const { return _ir._graph.has_key({name, type, false}); } + inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, false}); } + inline Node IRState::next_value() const { return Node(_ir._graph({name, type, true})); } + inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, type, true}); } + inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, true}); } inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); } inline arrow_proxy IR::iterator::operator->() { return arrow_proxy(**this); } // AbstractVisitor provides an abstract base class for visitors @@ -336,8 +403,8 @@ namespace Functional { virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; virtual T mux(Node self, Node a, Node b, Node s) = 0; virtual T constant(Node self, RTLIL::Const const & value) = 0; - virtual T input(Node self, IdString name) = 0; - virtual T state(Node self, IdString name) = 0; + virtual T input(Node self, IdString name, IdString type) = 0; + virtual T state(Node self, IdString name, IdString type) = 0; virtual T memory_read(Node self, Node mem, Node addr) = 0; virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; }; @@ -373,8 +440,8 @@ namespace Functional { T arithmetic_shift_right(Node self, Node, Node) override { return default_handler(self); } T mux(Node self, Node, Node, Node) override { return default_handler(self); } T constant(Node self, RTLIL::Const const &) override { return default_handler(self); } - T input(Node self, IdString) override { return default_handler(self); } - T state(Node self, IdString) override { return default_handler(self); } + T input(Node self, IdString, IdString) override { return default_handler(self); } + T state(Node self, IdString, IdString) override { return default_handler(self); } T memory_read(Node self, Node, Node) override { return default_handler(self); } T memory_write(Node self, Node, Node, Node) override { return default_handler(self); } }; @@ -383,7 +450,7 @@ namespace Functional { friend class IR; IR &_ir; explicit Factory(IR &ir) : _ir(ir) {} - Node add(IR::NodeData &&fn, Sort &&sort, std::initializer_list args) { + Node add(IR::NodeData &&fn, Sort const &sort, std::initializer_list args) { log_assert(!sort.is_signal() || sort.width() > 0); log_assert(!sort.is_memory() || (sort.addr_width() > 0 && sort.data_width() > 0)); IR::Graph::Ref ref = _ir._graph.add(std::move(fn), {std::move(sort)}); @@ -391,13 +458,11 @@ namespace Functional { ref.append_arg(IR::Graph::ConstRef(arg)); return Node(ref); } - IR::Graph::Ref mutate(Node n) { - return _ir._graph[n._ref.index()]; - } void check_basic_binary(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && a.sort() == b.sort()); } void check_shift(Node const &a, Node const &b) { log_assert(a.sort().is_signal() && b.sort().is_signal() && b.width() == ceil_log2(a.width())); } void check_unary(Node const &a) { log_assert(a.sort().is_signal()); } public: + IR &ir() { return _ir; } Node slice(Node a, int offset, int out_width) { log_assert(a.sort().is_signal() && offset + out_width <= a.sort().width()); if(offset == 0 && out_width == a.width()) @@ -480,45 +545,31 @@ namespace Functional { void update_pending(Node node, Node value) { log_assert(node._ref.function() == Fn::buf && node._ref.size() == 0); log_assert(node.sort() == value.sort()); - mutate(node).append_arg(value._ref); + _ir.mutate(node).append_arg(value._ref); } - void add_input(IdString name, int width) { - auto [it, inserted] = _ir._input_sorts.emplace(name, Sort(width)); + IRInput &add_input(IdString name, IdString type, Sort sort) { + auto [it, inserted] = _ir._inputs.emplace({name, type}, IRInput(_ir, name, type, std::move(sort))); if (!inserted) log_error("input `%s` was re-defined", name.c_str()); + return it->second; } - void add_output(IdString name, int width) { - auto [it, inserted] = _ir._output_sorts.emplace(name, Sort(width)); + IROutput &add_output(IdString name, IdString type, Sort sort) { + auto [it, inserted] = _ir._outputs.emplace({name, type}, IROutput(_ir, name, type, std::move(sort))); if (!inserted) log_error("output `%s` was re-defined", name.c_str()); + return it->second; } - void add_state(IdString name, Sort sort) { - auto [it, inserted] = _ir._state_sorts.emplace(name, sort); + IRState &add_state(IdString name, IdString type, Sort sort) { + auto [it, inserted] = _ir._states.emplace({name, type}, IRState(_ir, name, type, std::move(sort))); if (!inserted) log_error("state `%s` was re-defined", name.c_str()); + return it->second; } - Node input(IdString name) { - return add(IR::NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); + Node value(IRInput const& input) { + return add(IR::NodeData(Fn::input, std::pair(input.name, input.type)), input.sort, {}); } - Node current_state(IdString name) { - return add(IR::NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); - } - void set_output(IdString output, Node value) { - log_assert(_ir._output_sorts.at(output) == value.sort()); - mutate(value).assign_key({output, false}); - } - void set_initial_state(IdString state, RTLIL::Const value) { - Sort &sort = _ir._state_sorts.at(state); - value.extu(sort.width()); - _ir._initial_state_signal.emplace(state, std::move(value)); - } - void set_initial_state(IdString state, MemContents value) { - log_assert(Sort(value.addr_width(), value.data_width()) == _ir._state_sorts.at(state)); - _ir._initial_state_memory.emplace(state, std::move(value)); - } - void set_next_state(IdString state, Node value) { - log_assert(_ir._state_sorts.at(state) == value.sort()); - mutate(value).assign_key({state, true}); + Node value(IRState const& state) { + return add(IR::NodeData(Fn::state, std::pair(state.name, state.type)), state.sort, {}); } void suggest_name(Node node, IdString name) { - mutate(node).sparse_attr() = name; + _ir.mutate(node).sparse_attr() = name; } }; inline Factory IR::factory() { return Factory(*this); } From 831da512554aa5adc6875b8894be4a413656b2fb Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 8 Aug 2024 15:38:24 +0100 Subject: [PATCH 155/342] add picorv test to functional backend --- kernel/functional.cc | 17 +- tests/functional/picorv32.v | 3044 +++++++++++++++++++++++++++ tests/functional/picorv32_tb.v | 62 + tests/functional/rtlil_cells.py | 11 + tests/functional/test_functional.py | 3 + 5 files changed, 3135 insertions(+), 2 deletions(-) create mode 100644 tests/functional/picorv32.v create mode 100644 tests/functional/picorv32_tb.v diff --git a/kernel/functional.cc b/kernel/functional.cc index 202eaa502..eaae3f098 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -530,6 +530,7 @@ public: memories[mem.cell] = &mem; } } +private: Node concatenate_read_results(Mem *mem, vector results) { // sanity check: all read ports concatenated should equal to the RD_DATA port @@ -632,6 +633,17 @@ public: } } } + void undriven(const char *name) { + log_error("The design contains an undriven signal %s. This is not supported by the functional backend. " + "Call setundef with appropriate options to avoid this error.\n", name); + } + // we perform this check separately to give better error messages that include the wire or port name + void check_undriven(DriveSpec const& spec, std::string const& name) { + for(auto const &chunk : spec.chunks()) + if(chunk.is_none()) + undriven(name.c_str()); + } +public: void process_queue() { for (; !queue.empty(); queue.pop_front()) { @@ -660,6 +672,7 @@ public: factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(wire_chunk)); + check_undriven(driver, RTLIL::unescape_id(wire_chunk.wire->name)); Node node = enqueue(driver); factory.suggest_name(node, wire_chunk.wire->name); factory.update_pending(pending, node); @@ -677,6 +690,7 @@ public: factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(port_chunk)); + check_undriven(driver, RTLIL::unescape_id(port_chunk.cell->name) + " port " + RTLIL::unescape_id(port_chunk.port)); factory.update_pending(pending, enqueue(driver)); } } else { @@ -692,8 +706,7 @@ public: log_error("Signal %s has multiple drivers. This is not supported by the functional backend. " "If tristate drivers are used, call tristate -formal to avoid this error.\n", log_signal(chunk)); } else if (chunk.is_none()) { - log_error("The design contains an undriven signal %s. This is not supported by the functional backend. " - "Call setundef with appropriate options to avoid this error.\n", log_signal(chunk)); + undriven(log_signal(chunk)); } else { log_error("unhandled drivespec: %s\n", log_signal(chunk)); log_abort(); diff --git a/tests/functional/picorv32.v b/tests/functional/picorv32.v new file mode 100644 index 000000000..cfc7ce062 --- /dev/null +++ b/tests/functional/picorv32.v @@ -0,0 +1,3044 @@ +/* + * PicoRV32 -- A Small RISC-V (RV32I) Processor Core + * + * Copyright (C) 2015 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* verilator lint_off WIDTH */ +/* verilator lint_off PINMISSING */ +/* verilator lint_off CASEOVERLAP */ +/* verilator lint_off CASEINCOMPLETE */ + +`timescale 1 ns / 1 ps +// `default_nettype none +// `define DEBUGNETS +// `define DEBUGREGS +// `define DEBUGASM +// `define DEBUG + +`ifdef DEBUG + `define debug(debug_command) debug_command +`else + `define debug(debug_command) +`endif + +`ifdef FORMAL + `define FORMAL_KEEP (* keep *) + `define assert(assert_expr) assert(assert_expr) +`else + `ifdef DEBUGNETS + `define FORMAL_KEEP (* keep *) + `else + `define FORMAL_KEEP + `endif + `define assert(assert_expr) empty_statement +`endif + +// uncomment this for register file in extra module +// `define PICORV32_REGS picorv32_regs + +// this macro can be used to check if the verilog files in your +// design are read in the correct order. +`define PICORV32_V + + +/*************************************************************** + * picorv32 + ***************************************************************/ + +module picorv32 #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output reg trap, + + output reg mem_valid, + output reg mem_instr, + input mem_ready, + + output reg [31:0] mem_addr, + output reg [31:0] mem_wdata, + output reg [ 3:0] mem_wstrb, + input [31:0] mem_rdata, + + // Look-Ahead Interface + output mem_la_read, + output mem_la_write, + output [31:0] mem_la_addr, + output reg [31:0] mem_la_wdata, + output reg [ 3:0] mem_la_wstrb, + + // Pico Co-Processor Interface (PCPI) + output reg pcpi_valid, + output reg [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ Interface + input [31:0] irq, + output reg [31:0] eoi, + +`ifdef RISCV_FORMAL + output reg rvfi_valid, + output reg [63:0] rvfi_order, + output reg [31:0] rvfi_insn, + output reg rvfi_trap, + output reg rvfi_halt, + output reg rvfi_intr, + output reg [ 1:0] rvfi_mode, + output reg [ 1:0] rvfi_ixl, + output reg [ 4:0] rvfi_rs1_addr, + output reg [ 4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [ 4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [ 3:0] rvfi_mem_rmask, + output reg [ 3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, + + output reg [63:0] rvfi_csr_mcycle_rmask, + output reg [63:0] rvfi_csr_mcycle_wmask, + output reg [63:0] rvfi_csr_mcycle_rdata, + output reg [63:0] rvfi_csr_mcycle_wdata, + + output reg [63:0] rvfi_csr_minstret_rmask, + output reg [63:0] rvfi_csr_minstret_wmask, + output reg [63:0] rvfi_csr_minstret_rdata, + output reg [63:0] rvfi_csr_minstret_wdata, +`endif + + // Trace Interface + output reg trace_valid, + output reg [35:0] trace_data +); + localparam integer irq_timer = 0; + localparam integer irq_ebreak = 1; + localparam integer irq_buserror = 2; + + localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; + localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; + localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS; + + localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV; + + localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; + localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; + localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; + + reg [63:0] count_cycle, count_instr; + reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; + reg [4:0] reg_sh; + + reg [31:0] next_insn_opcode; + reg [31:0] dbg_insn_opcode; + reg [31:0] dbg_insn_addr; + + wire dbg_mem_valid = mem_valid; + wire dbg_mem_instr = mem_instr; + wire dbg_mem_ready = mem_ready; + wire [31:0] dbg_mem_addr = mem_addr; + wire [31:0] dbg_mem_wdata = mem_wdata; + wire [ 3:0] dbg_mem_wstrb = mem_wstrb; + wire [31:0] dbg_mem_rdata = mem_rdata; + + assign pcpi_rs1 = reg_op1; + assign pcpi_rs2 = reg_op2; + + wire [31:0] next_pc; + + reg irq_delay; + reg irq_active; + reg [31:0] irq_mask; + reg [31:0] irq_pending; + reg [31:0] timer; + +`ifndef PICORV32_REGS + reg [31:0] cpuregs [0:regfile_size-1]; + + integer i; + initial begin + if (REGS_INIT_ZERO) begin + for (i = 0; i < regfile_size; i = i+1) + cpuregs[i] = 0; + end + end +`endif + + task empty_statement; + // This task is used by the `assert directive in non-formal mode to + // avoid empty statement (which are unsupported by plain Verilog syntax). + begin end + endtask + +`ifdef DEBUGREGS + wire [31:0] dbg_reg_x0 = 0; + wire [31:0] dbg_reg_x1 = cpuregs[1]; + wire [31:0] dbg_reg_x2 = cpuregs[2]; + wire [31:0] dbg_reg_x3 = cpuregs[3]; + wire [31:0] dbg_reg_x4 = cpuregs[4]; + wire [31:0] dbg_reg_x5 = cpuregs[5]; + wire [31:0] dbg_reg_x6 = cpuregs[6]; + wire [31:0] dbg_reg_x7 = cpuregs[7]; + wire [31:0] dbg_reg_x8 = cpuregs[8]; + wire [31:0] dbg_reg_x9 = cpuregs[9]; + wire [31:0] dbg_reg_x10 = cpuregs[10]; + wire [31:0] dbg_reg_x11 = cpuregs[11]; + wire [31:0] dbg_reg_x12 = cpuregs[12]; + wire [31:0] dbg_reg_x13 = cpuregs[13]; + wire [31:0] dbg_reg_x14 = cpuregs[14]; + wire [31:0] dbg_reg_x15 = cpuregs[15]; + wire [31:0] dbg_reg_x16 = cpuregs[16]; + wire [31:0] dbg_reg_x17 = cpuregs[17]; + wire [31:0] dbg_reg_x18 = cpuregs[18]; + wire [31:0] dbg_reg_x19 = cpuregs[19]; + wire [31:0] dbg_reg_x20 = cpuregs[20]; + wire [31:0] dbg_reg_x21 = cpuregs[21]; + wire [31:0] dbg_reg_x22 = cpuregs[22]; + wire [31:0] dbg_reg_x23 = cpuregs[23]; + wire [31:0] dbg_reg_x24 = cpuregs[24]; + wire [31:0] dbg_reg_x25 = cpuregs[25]; + wire [31:0] dbg_reg_x26 = cpuregs[26]; + wire [31:0] dbg_reg_x27 = cpuregs[27]; + wire [31:0] dbg_reg_x28 = cpuregs[28]; + wire [31:0] dbg_reg_x29 = cpuregs[29]; + wire [31:0] dbg_reg_x30 = cpuregs[30]; + wire [31:0] dbg_reg_x31 = cpuregs[31]; +`endif + + // Internal PCPI Cores + + wire pcpi_mul_wr; + wire [31:0] pcpi_mul_rd; + wire pcpi_mul_wait; + wire pcpi_mul_ready; + + wire pcpi_div_wr; + wire [31:0] pcpi_div_rd; + wire pcpi_div_wait; + wire pcpi_div_ready; + + reg pcpi_int_wr; + reg [31:0] pcpi_int_rd; + reg pcpi_int_wait; + reg pcpi_int_ready; + + generate if (ENABLE_FAST_MUL) begin + picorv32_pcpi_fast_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else if (ENABLE_MUL) begin + picorv32_pcpi_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else begin + assign pcpi_mul_wr = 0; + assign pcpi_mul_rd = 32'bx; + assign pcpi_mul_wait = 0; + assign pcpi_mul_ready = 0; + end endgenerate + + generate if (ENABLE_DIV) begin + picorv32_pcpi_div pcpi_div ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_div_wr ), + .pcpi_rd (pcpi_div_rd ), + .pcpi_wait (pcpi_div_wait ), + .pcpi_ready(pcpi_div_ready ) + ); + end else begin + assign pcpi_div_wr = 0; + assign pcpi_div_rd = 32'bx; + assign pcpi_div_wait = 0; + assign pcpi_div_ready = 0; + end endgenerate + + always @* begin + pcpi_int_wr = 0; + pcpi_int_rd = 32'bx; + pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait}; + pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready}; + + (* parallel_case *) + case (1'b1) + ENABLE_PCPI && pcpi_ready: begin + pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0; + pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0; + end + (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin + pcpi_int_wr = pcpi_mul_wr; + pcpi_int_rd = pcpi_mul_rd; + end + ENABLE_DIV && pcpi_div_ready: begin + pcpi_int_wr = pcpi_div_wr; + pcpi_int_rd = pcpi_div_rd; + end + endcase + end + + + // Memory Interface + + reg [1:0] mem_state; + reg [1:0] mem_wordsize; + reg [31:0] mem_rdata_word; + reg [31:0] mem_rdata_q; + reg mem_do_prefetch; + reg mem_do_rinst; + reg mem_do_rdata; + reg mem_do_wdata; + + wire mem_xfer; + reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid; + wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword; + wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg); + + reg prefetched_high_word; + reg clear_prefetched_high_word; + reg [15:0] mem_16bit_buffer; + + wire [31:0] mem_rdata_latched_noshuffle; + wire [31:0] mem_rdata_latched; + + wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word; + assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst); + + wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; + wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && + (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer)); + + assign mem_la_write = resetn && !mem_state && mem_do_wdata; + assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || + (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0])); + assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00}; + + assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q; + + assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle; + + always @(posedge clk) begin + if (!resetn) begin + mem_la_firstword_reg <= 0; + last_mem_valid <= 0; + end else begin + if (!last_mem_valid) + mem_la_firstword_reg <= mem_la_firstword; + last_mem_valid <= mem_valid && !mem_ready; + end + end + + always @* begin + (* full_case *) + case (mem_wordsize) + 0: begin + mem_la_wdata = reg_op2; + mem_la_wstrb = 4'b1111; + mem_rdata_word = mem_rdata; + end + 1: begin + mem_la_wdata = {2{reg_op2[15:0]}}; + mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; + case (reg_op1[1]) + 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; + 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; + endcase + end + 2: begin + mem_la_wdata = {4{reg_op2[7:0]}}; + mem_la_wstrb = 4'b0001 << reg_op1[1:0]; + case (reg_op1[1:0]) + 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; + 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; + 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; + 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; + endcase + end + endcase + end + + always @(posedge clk) begin + if (mem_xfer) begin + mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + end + + if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00}; + end + 3'b010: begin // C.LW + mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b 110: begin // C.SW + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b 000: begin // C.ADDI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 010: begin // C.LI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 011: begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3], + mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000}); + end else begin // C.LUI + mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + end + 3'b100: begin + if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI + mem_rdata_q[31:25] <= 7'b0100000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000; + if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100; + if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110; + if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000; + end + end + 3'b 110: begin // C.BEQZ + mem_rdata_q[14:12] <= 3'b000; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + 3'b 111: begin // C.BNEZ + mem_rdata_q[14:12] <= 3'b001; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 001; + end + 3'b010: begin // C.LWSP + mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + end + 3'b110: begin // C.SWSP + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + endcase + end + end + + always @(posedge clk) begin + if (resetn && !trap) begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) + `assert(!mem_do_wdata); + + if (mem_do_prefetch || mem_do_rinst) + `assert(!mem_do_rdata); + + if (mem_do_rdata) + `assert(!mem_do_prefetch && !mem_do_rinst); + + if (mem_do_wdata) + `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata)); + + if (mem_state == 2 || mem_state == 3) + `assert(mem_valid || mem_do_prefetch); + end + end + + always @(posedge clk) begin + if (!resetn || trap) begin + if (!resetn) + mem_state <= 0; + if (!resetn || mem_ready) + mem_valid <= 0; + mem_la_secondword <= 0; + prefetched_high_word <= 0; + end else begin + if (mem_la_read || mem_la_write) begin + mem_addr <= mem_la_addr; + mem_wstrb <= mem_la_wstrb & {4{mem_la_write}}; + end + if (mem_la_write) begin + mem_wdata <= mem_la_wdata; + end + case (mem_state) + 0: begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin + mem_valid <= !mem_la_use_prefetched_high_word; + mem_instr <= mem_do_prefetch || mem_do_rinst; + mem_wstrb <= 0; + mem_state <= 1; + end + if (mem_do_wdata) begin + mem_valid <= 1; + mem_instr <= 0; + mem_state <= 2; + end + end + 1: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata); + `assert(mem_valid == !mem_la_use_prefetched_high_word); + `assert(mem_instr == (mem_do_prefetch || mem_do_rinst)); + if (mem_xfer) begin + if (COMPRESSED_ISA && mem_la_read) begin + mem_valid <= 1; + mem_la_secondword <= 1; + if (!mem_la_use_prefetched_high_word) + mem_16bit_buffer <= mem_rdata[31:16]; + end else begin + mem_valid <= 0; + mem_la_secondword <= 0; + if (COMPRESSED_ISA && !mem_do_rdata) begin + if (~&mem_rdata[1:0] || mem_la_secondword) begin + mem_16bit_buffer <= mem_rdata[31:16]; + prefetched_high_word <= 1; + end else begin + prefetched_high_word <= 0; + end + end + mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3; + end + end + end + 2: begin + `assert(mem_wstrb != 0); + `assert(mem_do_wdata); + if (mem_xfer) begin + mem_valid <= 0; + mem_state <= 0; + end + end + 3: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch); + if (mem_do_rinst) begin + mem_state <= 0; + end + end + endcase + end + + if (clear_prefetched_high_word) + prefetched_high_word <= 0; + end + + + // Instruction Decoder + + reg instr_lui, instr_auipc, instr_jal, instr_jalr; + reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; + reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; + reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; + reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; + reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; + wire instr_trap; + + reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2; + reg [31:0] decoded_imm, decoded_imm_j; + reg decoder_trigger; + reg decoder_trigger_q; + reg decoder_pseudo_trigger; + reg decoder_pseudo_trigger_q; + reg compressed_instr; + + reg is_lui_auipc_jal; + reg is_lb_lh_lw_lbu_lhu; + reg is_slli_srli_srai; + reg is_jalr_addi_slti_sltiu_xori_ori_andi; + reg is_sb_sh_sw; + reg is_sll_srl_sra; + reg is_lui_auipc_jal_jalr_addi_add_sub; + reg is_slti_blt_slt; + reg is_sltiu_bltu_sltu; + reg is_beq_bne_blt_bge_bltu_bgeu; + reg is_lbu_lhu_lw; + reg is_alu_reg_imm; + reg is_alu_reg_reg; + reg is_compare; + + assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, + instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, + instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, + instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, + instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, + instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, + instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; + + wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; + assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; + + reg [63:0] new_ascii_instr; + `FORMAL_KEEP reg [63:0] dbg_ascii_instr; + `FORMAL_KEEP reg [31:0] dbg_insn_imm; + `FORMAL_KEEP reg [4:0] dbg_insn_rs1; + `FORMAL_KEEP reg [4:0] dbg_insn_rs2; + `FORMAL_KEEP reg [4:0] dbg_insn_rd; + `FORMAL_KEEP reg [31:0] dbg_rs1val; + `FORMAL_KEEP reg [31:0] dbg_rs2val; + `FORMAL_KEEP reg dbg_rs1val_valid; + `FORMAL_KEEP reg dbg_rs2val_valid; + + always @* begin + new_ascii_instr = ""; + + if (instr_lui) new_ascii_instr = "lui"; + if (instr_auipc) new_ascii_instr = "auipc"; + if (instr_jal) new_ascii_instr = "jal"; + if (instr_jalr) new_ascii_instr = "jalr"; + + if (instr_beq) new_ascii_instr = "beq"; + if (instr_bne) new_ascii_instr = "bne"; + if (instr_blt) new_ascii_instr = "blt"; + if (instr_bge) new_ascii_instr = "bge"; + if (instr_bltu) new_ascii_instr = "bltu"; + if (instr_bgeu) new_ascii_instr = "bgeu"; + + if (instr_lb) new_ascii_instr = "lb"; + if (instr_lh) new_ascii_instr = "lh"; + if (instr_lw) new_ascii_instr = "lw"; + if (instr_lbu) new_ascii_instr = "lbu"; + if (instr_lhu) new_ascii_instr = "lhu"; + if (instr_sb) new_ascii_instr = "sb"; + if (instr_sh) new_ascii_instr = "sh"; + if (instr_sw) new_ascii_instr = "sw"; + + if (instr_addi) new_ascii_instr = "addi"; + if (instr_slti) new_ascii_instr = "slti"; + if (instr_sltiu) new_ascii_instr = "sltiu"; + if (instr_xori) new_ascii_instr = "xori"; + if (instr_ori) new_ascii_instr = "ori"; + if (instr_andi) new_ascii_instr = "andi"; + if (instr_slli) new_ascii_instr = "slli"; + if (instr_srli) new_ascii_instr = "srli"; + if (instr_srai) new_ascii_instr = "srai"; + + if (instr_add) new_ascii_instr = "add"; + if (instr_sub) new_ascii_instr = "sub"; + if (instr_sll) new_ascii_instr = "sll"; + if (instr_slt) new_ascii_instr = "slt"; + if (instr_sltu) new_ascii_instr = "sltu"; + if (instr_xor) new_ascii_instr = "xor"; + if (instr_srl) new_ascii_instr = "srl"; + if (instr_sra) new_ascii_instr = "sra"; + if (instr_or) new_ascii_instr = "or"; + if (instr_and) new_ascii_instr = "and"; + + if (instr_rdcycle) new_ascii_instr = "rdcycle"; + if (instr_rdcycleh) new_ascii_instr = "rdcycleh"; + if (instr_rdinstr) new_ascii_instr = "rdinstr"; + if (instr_rdinstrh) new_ascii_instr = "rdinstrh"; + + if (instr_getq) new_ascii_instr = "getq"; + if (instr_setq) new_ascii_instr = "setq"; + if (instr_retirq) new_ascii_instr = "retirq"; + if (instr_maskirq) new_ascii_instr = "maskirq"; + if (instr_waitirq) new_ascii_instr = "waitirq"; + if (instr_timer) new_ascii_instr = "timer"; + end + + reg [63:0] q_ascii_instr; + reg [31:0] q_insn_imm; + reg [31:0] q_insn_opcode; + reg [4:0] q_insn_rs1; + reg [4:0] q_insn_rs2; + reg [4:0] q_insn_rd; + reg dbg_next; + + wire launch_next_insn; + reg dbg_valid_insn; + + reg [63:0] cached_ascii_instr; + reg [31:0] cached_insn_imm; + reg [31:0] cached_insn_opcode; + reg [4:0] cached_insn_rs1; + reg [4:0] cached_insn_rs2; + reg [4:0] cached_insn_rd; + + always @(posedge clk) begin + q_ascii_instr <= dbg_ascii_instr; + q_insn_imm <= dbg_insn_imm; + q_insn_opcode <= dbg_insn_opcode; + q_insn_rs1 <= dbg_insn_rs1; + q_insn_rs2 <= dbg_insn_rs2; + q_insn_rd <= dbg_insn_rd; + dbg_next <= launch_next_insn; + + if (!resetn || trap) + dbg_valid_insn <= 0; + else if (launch_next_insn) + dbg_valid_insn <= 1; + + if (decoder_trigger_q) begin + cached_ascii_instr <= new_ascii_instr; + cached_insn_imm <= decoded_imm; + if (&next_insn_opcode[1:0]) + cached_insn_opcode <= next_insn_opcode; + else + cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]}; + cached_insn_rs1 <= decoded_rs1; + cached_insn_rs2 <= decoded_rs2; + cached_insn_rd <= decoded_rd; + end + + if (launch_next_insn) begin + dbg_insn_addr <= next_pc; + end + end + + always @* begin + dbg_ascii_instr = q_ascii_instr; + dbg_insn_imm = q_insn_imm; + dbg_insn_opcode = q_insn_opcode; + dbg_insn_rs1 = q_insn_rs1; + dbg_insn_rs2 = q_insn_rs2; + dbg_insn_rd = q_insn_rd; + + if (dbg_next) begin + if (decoder_pseudo_trigger_q) begin + dbg_ascii_instr = cached_ascii_instr; + dbg_insn_imm = cached_insn_imm; + dbg_insn_opcode = cached_insn_opcode; + dbg_insn_rs1 = cached_insn_rs1; + dbg_insn_rs2 = cached_insn_rs2; + dbg_insn_rd = cached_insn_rd; + end else begin + dbg_ascii_instr = new_ascii_instr; + if (&next_insn_opcode[1:0]) + dbg_insn_opcode = next_insn_opcode; + else + dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]}; + dbg_insn_imm = decoded_imm; + dbg_insn_rs1 = decoded_rs1; + dbg_insn_rs2 = decoded_rs2; + dbg_insn_rd = decoded_rd; + end + end + end + +`ifdef DEBUGASM + always @(posedge clk) begin + if (dbg_next) begin + $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); + end + end +`endif + +`ifdef DEBUG + always @(posedge clk) begin + if (dbg_next) begin + if (&dbg_insn_opcode[1:0]) + $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + else + $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + end + end +`endif + + always @(posedge clk) begin + is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; + is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; + is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt}; + is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu}; + is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw}; + is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu}; + + if (mem_do_rinst && mem_done) begin + instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; + instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; + instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; + instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000; + instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; + instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; + + is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011; + is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011; + is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011; + is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; + is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; + + { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); + + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[19:15]; + decoded_rs2 <= mem_rdata_latched[24:20]; + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS) + decoded_rs1[regindex_bits-1] <= 1; // instr_getq + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ) + decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq + + compressed_instr <= 0; + if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin + compressed_instr <= 1; + decoded_rd <= 0; + decoded_rs1 <= 0; + decoded_rs2 <= 0; + + { decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6], + decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0}); + + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + is_alu_reg_imm <= |mem_rdata_latched[12:5]; + decoded_rs1 <= 2; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b010: begin // C.LW + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b110: begin // C.SW + is_sb_sh_sw <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.NOP / C.ADDI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + 3'b001: begin // C.JAL + instr_jal <= 1; + decoded_rd <= 1; + end + 3'b 010: begin // C.LI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + 3'b 011: begin + if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end else begin // C.LUI + instr_lui <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + end + end + 3'b100: begin + if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + is_alu_reg_reg <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + end + 3'b101: begin // C.J + instr_jal <= 1; + end + 3'b110: begin // C.BEQZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + 3'b111: begin // C.BNEZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + if (!mem_rdata_latched[12]) begin + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + end + 3'b010: begin // C.LWSP + if (mem_rdata_latched[11:7]) begin + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 2; + end + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + instr_jalr <= 1; + decoded_rd <= 0; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + instr_jalr <= 1; + decoded_rd <= 1; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + end + 3'b110: begin // C.SWSP + is_sb_sh_sw <= 1; + decoded_rs1 <= 2; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + endcase + end + endcase + end + end + + if (decoder_trigger && !decoder_pseudo_trigger) begin + pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx; + + instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000; + instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001; + instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100; + instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101; + instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110; + instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111; + + instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000; + instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001; + instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010; + instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100; + instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101; + + instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000; + instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001; + instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010; + + instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000; + instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010; + instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011; + instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100; + instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110; + instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111; + + instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + + instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000; + instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000; + instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000; + instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000; + instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000; + instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000; + instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000; + + instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS; + instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; + instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); + + instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; + instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER; + + is_slli_srli_srai <= is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b000, + mem_rdata_q[14:12] == 3'b010, + mem_rdata_q[14:12] == 3'b011, + mem_rdata_q[14:12] == 3'b100, + mem_rdata_q[14:12] == 3'b110, + mem_rdata_q[14:12] == 3'b111 + }; + + is_sll_srl_sra <= is_alu_reg_reg && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_lui_auipc_jal_jalr_addi_add_sub <= 0; + is_compare <= 0; + + (* parallel_case *) + case (1'b1) + instr_jal: + decoded_imm <= decoded_imm_j; + |{instr_lui, instr_auipc}: + decoded_imm <= mem_rdata_q[31:12] << 12; + |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}: + decoded_imm <= $signed(mem_rdata_q[31:20]); + is_beq_bne_blt_bge_bltu_bgeu: + decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); + is_sb_sh_sw: + decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); + default: + decoded_imm <= 1'bx; + endcase + end + + if (!resetn) begin + is_beq_bne_blt_bge_bltu_bgeu <= 0; + is_compare <= 0; + + instr_beq <= 0; + instr_bne <= 0; + instr_blt <= 0; + instr_bge <= 0; + instr_bltu <= 0; + instr_bgeu <= 0; + + instr_addi <= 0; + instr_slti <= 0; + instr_sltiu <= 0; + instr_xori <= 0; + instr_ori <= 0; + instr_andi <= 0; + + instr_add <= 0; + instr_sub <= 0; + instr_sll <= 0; + instr_slt <= 0; + instr_sltu <= 0; + instr_xor <= 0; + instr_srl <= 0; + instr_sra <= 0; + instr_or <= 0; + instr_and <= 0; + end + end + + + // Main State Machine + + localparam cpu_state_trap = 8'b10000000; + localparam cpu_state_fetch = 8'b01000000; + localparam cpu_state_ld_rs1 = 8'b00100000; + localparam cpu_state_ld_rs2 = 8'b00010000; + localparam cpu_state_exec = 8'b00001000; + localparam cpu_state_shift = 8'b00000100; + localparam cpu_state_stmem = 8'b00000010; + localparam cpu_state_ldmem = 8'b00000001; + + reg [7:0] cpu_state; + reg [1:0] irq_state; + + `FORMAL_KEEP reg [127:0] dbg_ascii_state; + + always @* begin + dbg_ascii_state = ""; + if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap"; + if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch"; + if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1"; + if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2"; + if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec"; + if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift"; + if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem"; + if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; + end + + reg set_mem_do_rinst; + reg set_mem_do_rdata; + reg set_mem_do_wdata; + + reg latched_store; + reg latched_stalu; + reg latched_branch; + reg latched_compr; + reg latched_trace; + reg latched_is_lu; + reg latched_is_lh; + reg latched_is_lb; + reg [regindex_bits-1:0] latched_rd; + + reg [31:0] current_pc; + assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc; + + reg [3:0] pcpi_timeout_counter; + reg pcpi_timeout; + + reg [31:0] next_irq_pending; + reg do_waitirq; + + reg [31:0] alu_out, alu_out_q; + reg alu_out_0, alu_out_0_q; + reg alu_wait, alu_wait_2; + + reg [31:0] alu_add_sub; + reg [31:0] alu_shl, alu_shr; + reg alu_eq, alu_ltu, alu_lts; + + generate if (TWO_CYCLE_ALU) begin + always @(posedge clk) begin + alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq <= reg_op1 == reg_op2; + alu_lts <= $signed(reg_op1) < $signed(reg_op2); + alu_ltu <= reg_op1 < reg_op2; + alu_shl <= reg_op1 << reg_op2[4:0]; + alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end else begin + always @* begin + alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq = reg_op1 == reg_op2; + alu_lts = $signed(reg_op1) < $signed(reg_op2); + alu_ltu = reg_op1 < reg_op2; + alu_shl = reg_op1 << reg_op2[4:0]; + alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end endgenerate + + always @* begin + alu_out_0 = 'bx; + (* parallel_case, full_case *) + case (1'b1) + instr_beq: + alu_out_0 = alu_eq; + instr_bne: + alu_out_0 = !alu_eq; + instr_bge: + alu_out_0 = !alu_lts; + instr_bgeu: + alu_out_0 = !alu_ltu; + is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_lts; + is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_ltu; + endcase + + alu_out = 'bx; + (* parallel_case, full_case *) + case (1'b1) + is_lui_auipc_jal_jalr_addi_add_sub: + alu_out = alu_add_sub; + is_compare: + alu_out = alu_out_0; + instr_xori || instr_xor: + alu_out = reg_op1 ^ reg_op2; + instr_ori || instr_or: + alu_out = reg_op1 | reg_op2; + instr_andi || instr_and: + alu_out = reg_op1 & reg_op2; + BARREL_SHIFTER && (instr_sll || instr_slli): + alu_out = alu_shl; + BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): + alu_out = alu_shr; + endcase + +`ifdef RISCV_FORMAL_BLACKBOX_ALU + alu_out_0 = $anyseq; + alu_out = $anyseq; +`endif + end + + reg clear_prefetched_high_word_q; + always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word; + + always @* begin + clear_prefetched_high_word = clear_prefetched_high_word_q; + if (!prefetched_high_word) + clear_prefetched_high_word = 0; + if (latched_branch || irq_state || !resetn) + clear_prefetched_high_word = COMPRESSED_ISA; + end + + reg cpuregs_write; + reg [31:0] cpuregs_wrdata; + reg [31:0] cpuregs_rs1; + reg [31:0] cpuregs_rs2; + reg [regindex_bits-1:0] decoded_rs; + + always @* begin + cpuregs_write = 0; + cpuregs_wrdata = 'bx; + + if (cpu_state == cpu_state_fetch) begin + (* parallel_case *) + case (1'b1) + latched_branch: begin + cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); + cpuregs_write = 1; + end + latched_store && !latched_branch: begin + cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[0]: begin + cpuregs_wrdata = reg_next_pc | latched_compr; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[1]: begin + cpuregs_wrdata = irq_pending & ~irq_mask; + cpuregs_write = 1; + end + endcase + end + end + +`ifndef PICORV32_REGS + always @(posedge clk) begin + if (resetn && cpuregs_write && latched_rd) +`ifdef PICORV32_TESTBUG_001 + cpuregs[latched_rd ^ 1] <= cpuregs_wrdata; +`elsif PICORV32_TESTBUG_002 + cpuregs[latched_rd] <= cpuregs_wrdata ^ 1; +`else + cpuregs[latched_rd] <= cpuregs_wrdata; +`endif + end + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; +`else + cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; + cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; +`endif + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; +`else + cpuregs_rs1 = decoded_rs ? $anyseq : 0; +`endif + cpuregs_rs2 = cpuregs_rs1; + end + end +`else + wire[31:0] cpuregs_rdata1; + wire[31:0] cpuregs_rdata2; + + wire [5:0] cpuregs_waddr = latched_rd; + wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; + wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; + + `PICORV32_REGS cpuregs ( + .clk(clk), + .wen(resetn && cpuregs_write && latched_rd), + .waddr(cpuregs_waddr), + .raddr1(cpuregs_raddr1), + .raddr2(cpuregs_raddr2), + .wdata(cpuregs_wrdata), + .rdata1(cpuregs_rdata1), + .rdata2(cpuregs_rdata2) + ); + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin + cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; + cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; + cpuregs_rs2 = cpuregs_rs1; + end + end +`endif + + assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask)); + + always @(posedge clk) begin + trap <= 0; + reg_sh <= 'bx; + reg_out <= 'bx; + set_mem_do_rinst = 0; + set_mem_do_rdata = 0; + set_mem_do_wdata = 0; + + alu_out_0_q <= alu_out_0; + alu_out_q <= alu_out; + + alu_wait <= 0; + alu_wait_2 <= 0; + + if (launch_next_insn) begin + dbg_rs1val <= 'bx; + dbg_rs2val <= 'bx; + dbg_rs1val_valid <= 0; + dbg_rs2val_valid <= 0; + end + + if (WITH_PCPI && CATCH_ILLINSN) begin + if (resetn && pcpi_valid && !pcpi_int_wait) begin + if (pcpi_timeout_counter) + pcpi_timeout_counter <= pcpi_timeout_counter - 1; + end else + pcpi_timeout_counter <= ~0; + pcpi_timeout <= !pcpi_timeout_counter; + end + + if (ENABLE_COUNTERS) begin + count_cycle <= resetn ? count_cycle + 1 : 0; + if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0; + end else begin + count_cycle <= 'bx; + count_instr <= 'bx; + end + + next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; + + if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin + timer <= timer - 1; + end + + decoder_trigger <= mem_do_rinst && mem_done; + decoder_trigger_q <= decoder_trigger; + decoder_pseudo_trigger <= 0; + decoder_pseudo_trigger_q <= decoder_pseudo_trigger; + do_waitirq <= 0; + + trace_valid <= 0; + + if (!ENABLE_TRACE) + trace_data <= 'bx; + + if (!resetn) begin + reg_pc <= PROGADDR_RESET; + reg_next_pc <= PROGADDR_RESET; + if (ENABLE_COUNTERS) + count_instr <= 0; + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_trace <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + pcpi_valid <= 0; + pcpi_timeout <= 0; + irq_active <= 0; + irq_delay <= 0; + irq_mask <= ~0; + next_irq_pending = 0; + irq_state <= 0; + eoi <= 0; + timer <= 0; + if (~STACKADDR) begin + latched_store <= 1; + latched_rd <= 2; + reg_out <= STACKADDR; + end + cpu_state <= cpu_state_fetch; + end else + (* parallel_case, full_case *) + case (cpu_state) + cpu_state_trap: begin + trap <= 1; + end + + cpu_state_fetch: begin + mem_do_rinst <= !decoder_trigger && !do_waitirq; + mem_wordsize <= 0; + + current_pc = reg_next_pc; + + (* parallel_case *) + case (1'b1) + latched_branch: begin + current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; + `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) + end + latched_store && !latched_branch: begin + `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) + end + ENABLE_IRQ && irq_state[0]: begin + current_pc = PROGADDR_IRQ; + irq_active <= 1; + mem_do_rinst <= 1; + end + ENABLE_IRQ && irq_state[1]: begin + eoi <= irq_pending & ~irq_mask; + next_irq_pending = next_irq_pending & irq_mask; + end + endcase + + if (ENABLE_TRACE && latched_trace) begin + latched_trace <= 0; + trace_valid <= 1; + if (latched_branch) + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); + else + trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out); + end + + reg_pc <= current_pc; + reg_next_pc <= current_pc; + + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + latched_rd <= decoded_rd; + latched_compr <= compressed_instr; + + if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin + irq_state <= + irq_state == 2'b00 ? 2'b01 : + irq_state == 2'b01 ? 2'b10 : 2'b00; + latched_compr <= latched_compr; + if (ENABLE_IRQ_QREGS) + latched_rd <= irqregs_offset | irq_state[0]; + else + latched_rd <= irq_state[0] ? 4 : 3; + end else + if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin + if (irq_pending) begin + latched_store <= 1; + reg_out <= irq_pending; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + mem_do_rinst <= 1; + end else + do_waitirq <= 1; + end else + if (decoder_trigger) begin + `debug($display("-- %-0t", $time);) + irq_delay <= irq_active; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + if (ENABLE_TRACE) + latched_trace <= 1; + if (ENABLE_COUNTERS) begin + count_instr <= count_instr + 1; + if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0; + end + if (instr_jal) begin + mem_do_rinst <= 1; + reg_next_pc <= current_pc + decoded_imm_j; + latched_branch <= 1; + end else begin + mem_do_rinst <= 0; + mem_do_prefetch <= !instr_jalr && !instr_retirq; + cpu_state <= cpu_state_ld_rs1; + end + end + end + + cpu_state_ld_rs1: begin + reg_op1 <= 'bx; + reg_op2 <= 'bx; + + (* parallel_case *) + case (1'b1) + (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin + if (WITH_PCPI) begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + pcpi_valid <= 1; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end else begin + cpu_state <= cpu_state_ld_rs2; + end + end else begin + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin + (* parallel_case, full_case *) + case (1'b1) + instr_rdcycle: + reg_out <= count_cycle[31:0]; + instr_rdcycleh && ENABLE_COUNTERS64: + reg_out <= count_cycle[63:32]; + instr_rdinstr: + reg_out <= count_instr[31:0]; + instr_rdinstrh && ENABLE_COUNTERS64: + reg_out <= count_instr[63:32]; + endcase + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + is_lui_auipc_jal: begin + reg_op1 <= instr_lui ? 0 : reg_pc; + reg_op2 <= decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_rd <= latched_rd | irqregs_offset; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_retirq: begin + eoi <= 0; + irq_active <= 0; + latched_branch <= 1; + latched_store <= 1; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_maskirq: begin + latched_store <= 1; + reg_out <= irq_mask; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + irq_mask <= cpuregs_rs1 | MASKED_IRQ; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin + latched_store <= 1; + reg_out <= timer; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + timer <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + is_lb_lh_lw_lbu_lhu && !instr_trap: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_ldmem; + mem_do_rinst <= 1; + end + is_slli_srli_srai && !BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_sh <= decoded_rs2; + cpu_state <= cpu_state_shift; + end + is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + default: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + (* parallel_case *) + case (1'b1) + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end else + cpu_state <= cpu_state_ld_rs2; + end + endcase + end + + cpu_state_ld_rs2: begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + + (* parallel_case *) + case (1'b1) + WITH_PCPI && instr_trap: begin + pcpi_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end + + cpu_state_exec: begin + reg_out <= reg_pc + decoded_imm; + if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin + mem_do_rinst <= mem_do_prefetch && !alu_wait_2; + alu_wait <= alu_wait_2; + end else + if (is_beq_bne_blt_bge_bltu_bgeu) begin + latched_rd <= 0; + latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + if (mem_done) + cpu_state <= cpu_state_fetch; + if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin + decoder_trigger <= 0; + set_mem_do_rinst = 1; + end + end else begin + latched_branch <= instr_jalr; + latched_store <= 1; + latched_stalu <= 1; + cpu_state <= cpu_state_fetch; + end + end + + cpu_state_shift: begin + latched_store <= 1; + if (reg_sh == 0) begin + reg_out <= reg_op1; + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_fetch; + end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4; + endcase + reg_sh <= reg_sh - 4; + end else begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 1; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1; + endcase + reg_sh <= reg_sh - 1; + end + end + + cpu_state_stmem: begin + if (ENABLE_TRACE) + reg_out <= reg_op2; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_wdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_sb: mem_wordsize <= 2; + instr_sh: mem_wordsize <= 1; + instr_sw: mem_wordsize <= 0; + endcase + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_wdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + cpu_state <= cpu_state_fetch; + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + end + end + end + + cpu_state_ldmem: begin + latched_store <= 1; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_rdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_lb || instr_lbu: mem_wordsize <= 2; + instr_lh || instr_lhu: mem_wordsize <= 1; + instr_lw: mem_wordsize <= 0; + endcase + latched_is_lu <= is_lbu_lhu_lw; + latched_is_lh <= instr_lh; + latched_is_lb <= instr_lb; + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_rdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + (* parallel_case, full_case *) + case (1'b1) + latched_is_lu: reg_out <= mem_rdata_word; + latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]); + latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]); + endcase + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + cpu_state <= cpu_state_fetch; + end + end + end + endcase + + if (ENABLE_IRQ) begin + next_irq_pending = next_irq_pending | irq; + if(ENABLE_IRQ_TIMER && timer) + if (timer - 1 == 0) + next_irq_pending[irq_timer] = 1; + end + + if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin + if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin + `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (mem_wordsize == 1 && reg_op1[0] != 0) begin + `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + end + if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin + `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin + cpu_state <= cpu_state_trap; + end + + if (!resetn || mem_done) begin + mem_do_prefetch <= 0; + mem_do_rinst <= 0; + mem_do_rdata <= 0; + mem_do_wdata <= 0; + end + + if (set_mem_do_rinst) + mem_do_rinst <= 1; + if (set_mem_do_rdata) + mem_do_rdata <= 1; + if (set_mem_do_wdata) + mem_do_wdata <= 1; + + irq_pending <= next_irq_pending & ~MASKED_IRQ; + + if (!CATCH_MISALIGN) begin + if (COMPRESSED_ISA) begin + reg_pc[0] <= 0; + reg_next_pc[0] <= 0; + end else begin + reg_pc[1:0] <= 0; + reg_next_pc[1:0] <= 0; + end + end + current_pc = 'bx; + end + +`ifdef RISCV_FORMAL + reg dbg_irq_call; + reg dbg_irq_enter; + reg [31:0] dbg_irq_ret; + always @(posedge clk) begin + rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn; + rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0; + + rvfi_insn <= dbg_insn_opcode; + rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0; + rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0; + rvfi_pc_rdata <= dbg_insn_addr; + rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0; + rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0; + rvfi_trap <= trap; + rvfi_halt <= trap; + rvfi_intr <= dbg_irq_enter; + rvfi_mode <= 3; + rvfi_ixl <= 1; + + if (!resetn) begin + dbg_irq_call <= 0; + dbg_irq_enter <= 0; + end else + if (rvfi_valid) begin + dbg_irq_call <= 0; + dbg_irq_enter <= dbg_irq_call; + end else + if (irq_state == 1) begin + dbg_irq_call <= 1; + dbg_irq_ret <= next_pc; + end + + if (!resetn) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end else + if (cpuregs_write && !irq_state) begin +`ifdef PICORV32_TESTBUG_003 + rvfi_rd_addr <= latched_rd ^ 1; +`else + rvfi_rd_addr <= latched_rd; +`endif +`ifdef PICORV32_TESTBUG_004 + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0; +`else + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0; +`endif + end else + if (rvfi_valid) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + + casez (dbg_insn_opcode) + 32'b 0000000_?????_000??_???_?????_0001011: begin // getq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + 32'b 0000001_?????_?????_???_000??_0001011: begin // setq + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + endcase + + if (!dbg_irq_call) begin + if (dbg_mem_instr) begin + rvfi_mem_addr <= 0; + rvfi_mem_rmask <= 0; + rvfi_mem_wmask <= 0; + rvfi_mem_rdata <= 0; + rvfi_mem_wdata <= 0; + end else + if (dbg_mem_valid && dbg_mem_ready) begin + rvfi_mem_addr <= dbg_mem_addr; + rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0; + rvfi_mem_wmask <= dbg_mem_wstrb; + rvfi_mem_rdata <= dbg_mem_rdata; + rvfi_mem_wdata <= dbg_mem_wdata; + end + end + end + + always @* begin +`ifdef PICORV32_TESTBUG_005 + rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4; +`else + rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr; +`endif + + rvfi_csr_mcycle_rmask = 0; + rvfi_csr_mcycle_wmask = 0; + rvfi_csr_mcycle_rdata = 0; + rvfi_csr_mcycle_wdata = 0; + + rvfi_csr_minstret_rmask = 0; + rvfi_csr_minstret_wmask = 0; + rvfi_csr_minstret_rdata = 0; + rvfi_csr_minstret_wdata = 0; + + if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin + if (rvfi_insn[31:20] == 12'h C00) begin + rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF; + rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata}; + end + if (rvfi_insn[31:20] == 12'h C80) begin + rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000; + rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000}; + end + if (rvfi_insn[31:20] == 12'h C02) begin + rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF; + rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata}; + end + if (rvfi_insn[31:20] == 12'h C82) begin + rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000; + rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000}; + end + end + end +`endif + + // Formal Verification +`ifdef FORMAL + reg [3:0] last_mem_nowait; + always @(posedge clk) + last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid}; + + // stall the memory interface for max 4 cycles + restrict property (|last_mem_nowait || mem_ready || !mem_valid); + + // resetn low in first cycle, after that resetn high + restrict property (resetn != $initstate); + + // this just makes it much easier to read traces. uncomment as needed. + // assume property (mem_valid || !mem_ready); + + reg ok; + always @* begin + if (resetn) begin + // instruction fetches are read-only + if (mem_valid && mem_instr) + assert (mem_wstrb == 0); + + // cpu_state must be valid + ok = 0; + if (cpu_state == cpu_state_trap) ok = 1; + if (cpu_state == cpu_state_fetch) ok = 1; + if (cpu_state == cpu_state_ld_rs1) ok = 1; + if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT; + if (cpu_state == cpu_state_exec) ok = 1; + if (cpu_state == cpu_state_shift) ok = 1; + if (cpu_state == cpu_state_stmem) ok = 1; + if (cpu_state == cpu_state_ldmem) ok = 1; + assert (ok); + end + end + + reg last_mem_la_read = 0; + reg last_mem_la_write = 0; + reg [31:0] last_mem_la_addr; + reg [31:0] last_mem_la_wdata; + reg [3:0] last_mem_la_wstrb = 0; + + always @(posedge clk) begin + last_mem_la_read <= mem_la_read; + last_mem_la_write <= mem_la_write; + last_mem_la_addr <= mem_la_addr; + last_mem_la_wdata <= mem_la_wdata; + last_mem_la_wstrb <= mem_la_wstrb; + + if (last_mem_la_read) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wstrb == 0); + end + if (last_mem_la_write) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wdata == last_mem_la_wdata); + assert(mem_wstrb == last_mem_la_wstrb); + end + if (mem_la_read || mem_la_write) begin + assert(!mem_valid || mem_ready); + end + end +`endif +endmodule + +// This is a simple example implementation of PICORV32_REGS. +// Use the PICORV32_REGS mechanism if you want to use custom +// memory resources to implement the processor register file. +// Note that your implementation must match the requirements of +// the PicoRV32 configuration. (e.g. QREGS, etc) +module picorv32_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:30]; + + always @(posedge clk) + if (wen) regs[~waddr[4:0]] <= wdata; + + assign rdata1 = regs[~raddr1[4:0]]; + assign rdata2 = regs[~raddr2[4:0]]; +endmodule + + +/*************************************************************** + * picorv32_pcpi_mul + ***************************************************************/ + +module picorv32_pcpi_mul #( + parameter STEPS_AT_ONCE = 1, + parameter CARRY_CHAIN = 4 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg pcpi_wait_q; + wire mul_start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_mul <= 0; + instr_mulh <= 0; + instr_mulhsu <= 0; + instr_mulhu <= 0; + + if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul <= 1; + 3'b001: instr_mulh <= 1; + 3'b010: instr_mulhsu <= 1; + 3'b011: instr_mulhu <= 1; + endcase + end + + pcpi_wait <= instr_any_mul; + pcpi_wait_q <= pcpi_wait; + end + + reg [63:0] rs1, rs2, rd, rdx; + reg [63:0] next_rs1, next_rs2, this_rs2; + reg [63:0] next_rd, next_rdx, next_rdt; + reg [6:0] mul_counter; + reg mul_waiting; + reg mul_finish; + integer i, j; + + // carry save accumulator + always @* begin + next_rd = rd; + next_rdx = rdx; + next_rs1 = rs1; + next_rs2 = rs2; + + for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin + this_rs2 = next_rs1[0] ? next_rs2 : 0; + if (CARRY_CHAIN == 0) begin + next_rdt = next_rd ^ next_rdx ^ this_rs2; + next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1; + next_rd = next_rdt; + end else begin + next_rdt = 0; + for (j = 0; j < 64; j = j + CARRY_CHAIN) + {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} = + next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN]; + next_rdx = next_rdt << 1; + end + next_rs1 = next_rs1 >> 1; + next_rs2 = next_rs2 << 1; + end + end + + always @(posedge clk) begin + mul_finish <= 0; + if (!resetn) begin + mul_waiting <= 1; + end else + if (mul_waiting) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + + rd <= 0; + rdx <= 0; + mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE); + mul_waiting <= !mul_start; + end else begin + rd <= next_rd; + rdx <= next_rdx; + rs1 <= next_rs1; + rs2 <= next_rs2; + + mul_counter <= mul_counter - STEPS_AT_ONCE; + if (mul_counter[6]) begin + mul_finish <= 1; + mul_waiting <= 1; + end + end + end + + always @(posedge clk) begin + pcpi_wr <= 0; + pcpi_ready <= 0; + if (mul_finish && resetn) begin + pcpi_wr <= 1; + pcpi_ready <= 1; + pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; + end + end +endmodule + +module picorv32_pcpi_fast_mul #( + parameter EXTRA_MUL_FFS = 0, + parameter EXTRA_INSN_FFS = 0, + parameter MUL_CLKGATE = 0 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output pcpi_wr, + output [31:0] pcpi_rd, + output pcpi_wait, + output pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg shift_out; + reg [3:0] active; + reg [32:0] rs1, rs2, rs1_q, rs2_q; + reg [63:0] rd, rd_q; + + wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001; + reg pcpi_insn_valid_q; + + always @* begin + instr_mul = 0; + instr_mulh = 0; + instr_mulhsu = 0; + instr_mulhu = 0; + + if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul = 1; + 3'b001: instr_mulh = 1; + 3'b010: instr_mulhsu = 1; + 3'b011: instr_mulhu = 1; + endcase + end + end + + always @(posedge clk) begin + pcpi_insn_valid_q <= pcpi_insn_valid; + if (!MUL_CLKGATE || active[0]) begin + rs1_q <= rs1; + rs2_q <= rs2; + end + if (!MUL_CLKGATE || active[1]) begin + rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2); + end + if (!MUL_CLKGATE || active[2]) begin + rd_q <= rd; + end + end + + always @(posedge clk) begin + if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + active[0] <= 1; + end else begin + active[0] <= 0; + end + + active[3:1] <= active; + shift_out <= instr_any_mulh; + + if (!resetn) + active <= 0; + end + + assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; + assign pcpi_wait = 0; + assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; +`ifdef RISCV_FORMAL_ALTOPS + assign pcpi_rd = + instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e : + instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 : + instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 : + instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx; +`else + assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); +`endif +endmodule + + +/*************************************************************** + * picorv32_pcpi_div + ***************************************************************/ + +module picorv32_pcpi_div ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_div, instr_divu, instr_rem, instr_remu; + wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu}; + + reg pcpi_wait_q; + wire start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_div <= 0; + instr_divu <= 0; + instr_rem <= 0; + instr_remu <= 0; + + if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b100: instr_div <= 1; + 3'b101: instr_divu <= 1; + 3'b110: instr_rem <= 1; + 3'b111: instr_remu <= 1; + endcase + end + + pcpi_wait <= instr_any_div_rem && resetn; + pcpi_wait_q <= pcpi_wait && resetn; + end + + reg [31:0] dividend; + reg [62:0] divisor; + reg [31:0] quotient; + reg [31:0] quotient_msk; + reg running; + reg outsign; + + always @(posedge clk) begin + pcpi_ready <= 0; + pcpi_wr <= 0; + pcpi_rd <= 'bx; + + if (!resetn) begin + running <= 0; + end else + if (start) begin + running <= 1; + dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; + divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; + outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); + quotient <= 0; + quotient_msk <= 1 << 31; + end else + if (!quotient_msk && running) begin + running <= 0; + pcpi_ready <= 1; + pcpi_wr <= 1; +`ifdef RISCV_FORMAL_ALTOPS + case (1) + instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec; + instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70; + instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5; + instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1; + endcase +`else + if (instr_div || instr_divu) + pcpi_rd <= outsign ? -quotient : quotient; + else + pcpi_rd <= outsign ? -dividend : dividend; +`endif + end else begin + if (divisor <= dividend) begin + dividend <= dividend - divisor; + quotient <= quotient | quotient_msk; + end + divisor <= divisor >> 1; +`ifdef RISCV_FORMAL_ALTOPS + quotient_msk <= quotient_msk >> 5; +`else + quotient_msk <= quotient_msk >> 1; +`endif + end + end +endmodule + + +/*************************************************************** + * picorv32_axi + ***************************************************************/ + +module picorv32_axi #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output trap, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_rdata; + + picorv32_axi_adapter axi_adapter ( + .clk (clk ), + .resetn (resetn ), + .mem_axi_awvalid(mem_axi_awvalid), + .mem_axi_awready(mem_axi_awready), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + .mem_axi_arvalid(mem_axi_arvalid), + .mem_axi_arready(mem_axi_arready), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); +endmodule + + +/*************************************************************** + * picorv32_axi_adapter + ***************************************************************/ + +module picorv32_axi_adapter ( + input clk, resetn, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Native PicoRV32 memory interface + + input mem_valid, + input mem_instr, + output mem_ready, + input [31:0] mem_addr, + input [31:0] mem_wdata, + input [ 3:0] mem_wstrb, + output [31:0] mem_rdata +); + reg ack_awvalid; + reg ack_arvalid; + reg ack_wvalid; + reg xfer_done; + + assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; + assign mem_axi_awaddr = mem_addr; + assign mem_axi_awprot = 0; + + assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid; + assign mem_axi_araddr = mem_addr; + assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000; + + assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid; + assign mem_axi_wdata = mem_wdata; + assign mem_axi_wstrb = mem_wstrb; + + assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; + assign mem_axi_bready = mem_valid && |mem_wstrb; + assign mem_axi_rready = mem_valid && !mem_wstrb; + assign mem_rdata = mem_axi_rdata; + + always @(posedge clk) begin + if (!resetn) begin + ack_awvalid <= 0; + end else begin + xfer_done <= mem_valid && mem_ready; + if (mem_axi_awready && mem_axi_awvalid) + ack_awvalid <= 1; + if (mem_axi_arready && mem_axi_arvalid) + ack_arvalid <= 1; + if (mem_axi_wready && mem_axi_wvalid) + ack_wvalid <= 1; + if (xfer_done || !mem_valid) begin + ack_awvalid <= 0; + ack_arvalid <= 0; + ack_wvalid <= 0; + end + end + end +endmodule + + +/*************************************************************** + * picorv32_wb + ***************************************************************/ + +module picorv32_wb #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + output trap, + + // Wishbone interfaces + input wb_rst_i, + input wb_clk_i, + + output reg [31:0] wbm_adr_o, + output reg [31:0] wbm_dat_o, + input [31:0] wbm_dat_i, + output reg wbm_we_o, + output reg [3:0] wbm_sel_o, + output reg wbm_stb_o, + input wbm_ack_i, + output reg wbm_cyc_o, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data, + + output mem_instr +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg mem_ready; + reg [31:0] mem_rdata; + + wire clk; + wire resetn; + + assign clk = wb_clk_i; + assign resetn = ~wb_rst_i; + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); + + localparam IDLE = 2'b00; + localparam WBSTART = 2'b01; + localparam WBEND = 2'b10; + + reg [1:0] state; + + wire we; + assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]); + + always @(posedge wb_clk_i) begin + if (wb_rst_i) begin + wbm_adr_o <= 0; + wbm_dat_o <= 0; + wbm_we_o <= 0; + wbm_sel_o <= 0; + wbm_stb_o <= 0; + wbm_cyc_o <= 0; + state <= IDLE; + end else begin + case (state) + IDLE: begin + if (mem_valid) begin + wbm_adr_o <= mem_addr; + wbm_dat_o <= mem_wdata; + wbm_we_o <= we; + wbm_sel_o <= mem_wstrb; + + wbm_stb_o <= 1'b1; + wbm_cyc_o <= 1'b1; + state <= WBSTART; + end else begin + mem_ready <= 1'b0; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBSTART:begin + if (wbm_ack_i) begin + mem_rdata <= wbm_dat_i; + mem_ready <= 1'b1; + + state <= WBEND; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBEND: begin + mem_ready <= 1'b0; + + state <= IDLE; + end + default: + state <= IDLE; + endcase + end + end +endmodule diff --git a/tests/functional/picorv32_tb.v b/tests/functional/picorv32_tb.v new file mode 100644 index 000000000..1404c2d8c --- /dev/null +++ b/tests/functional/picorv32_tb.v @@ -0,0 +1,62 @@ +module gold( + input wire clk, + output reg resetn, + output wire trap, + output wire mem_valid, + output wire mem_instr, + output wire mem_ready, + output wire [31:0] mem_addr, + output wire [31:0] mem_wdata, + output wire [31:0] mem_wstrb, + output wire [31:0] mem_rdata, +); + + initial resetn = 1'b0; + always @(posedge clk) resetn <= 1'b1; + + reg [31:0] rom[0:15]; + + initial begin + rom[0] = 32'h00200093; + rom[1] = 32'h00200113; + rom[2] = 32'h00111863; + rom[3] = 32'h00102023; + rom[4] = 32'h00108093; + rom[5] = 32'hfe0008e3; + rom[6] = 32'h00008193; + rom[7] = 32'h402181b3; + rom[8] = 32'hfe304ee3; + rom[9] = 32'hfe0186e3; + rom[10] = 32'h00110113; + rom[11] = 32'hfc000ee3; + end + + assign mem_ready = 1'b1; + assign mem_rdata = rom[mem_addr[5:2]]; + + wire pcpi_wr = 1'b0; + wire [31:0] pcpi_rd = 32'b0; + wire pcpi_wait = 1'b0; + wire pcpi_ready = 1'b0; + + wire [31:0] irq = 32'b0; + + picorv32 picorv32_i( + .clk(clk), + .resetn(resetn), + .trap(trap), + .mem_valid(mem_valid), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_addr(mem_addr), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_rdata(mem_rdata), + .pcpi_wr(pcpi_wr), + .pcpi_rd(pcpi_rd), + .pcpi_wait(pcpi_wait), + .pcpi_ready(pcpi_ready), + .irq(irq) + ); + +endmodule diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index ed867b695..964d81ddf 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -233,6 +233,16 @@ module gold( endmodule""".format(parameters['DATA_WIDTH'] - 1, parameters['ADDR_WIDTH'] - 1, 2**parameters['ADDR_WIDTH'] - 1)) yosys_synth(verilog_file, path) +class PicorvCell(BaseCell): + def __init__(self): + super().__init__("picorv", [], {}, {}, [()]) + self.smt_max_steps = 50 # z3 is too slow for more steps + def write_rtlil_file(self, path, parameters): + from test_functional import yosys, base_path, quote + tb_file = base_path / 'tests/functional/picorv32_tb.v' + cpu_file = base_path / 'tests/functional/picorv32.v' + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; write_rtlil {quote(path)}") + binary_widths = [ # try to cover extending A operand, extending B operand, extending/truncating result (16, 32, 48, True, True), @@ -353,6 +363,7 @@ rtlil_cells = [ # ("original_tag", ["A", "Y"]), # ("future_ff", ["A", "Y"]), # ("scopeinfo", []), + PicorvCell() ] def generate_test_cases(per_cell, rnd): diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 7bfe19fc4..107ca6862 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -63,6 +63,9 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): vcd_functional_file = tmp_path / 'functional.vcd' vcd_yosys_sim_file = tmp_path / 'yosys.vcd' + if hasattr(cell, 'smt_max_steps'): + num_steps = min(num_steps, cell.smt_max_steps) + cell.write_rtlil_file(rtlil_file, parameters) yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}") run(['z3', smt_file]) # check if output is valid smtlib before continuing From f456761e88886053c503393fb2356afa45ef750f Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 13 Aug 2024 14:04:04 +0100 Subject: [PATCH 156/342] add sandia copyright notice to the functional backend --- backends/functional/cxx.cc | 1 + backends/functional/cxx_runtime/sim.h | 1 + backends/functional/smtlib.cc | 1 + backends/functional/test_generic.cc | 1 + kernel/functional.cc | 1 + kernel/functional.h | 1 + 6 files changed, 6 insertions(+) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 19740777f..282eb8f67 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/backends/functional/cxx_runtime/sim.h b/backends/functional/cxx_runtime/sim.h index c50bc2cd8..941f067b9 100644 --- a/backends/functional/cxx_runtime/sim.h +++ b/backends/functional/cxx_runtime/sim.h @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index ec9e6b242..4e176c2fd 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 1617d54c0..aab2260f1 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/kernel/functional.cc b/kernel/functional.cc index eaae3f098..1ece145e5 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/kernel/functional.h b/kernel/functional.h index f7ff08228..88a48dba9 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above From 9b5e81b13fbc2e4947ad591bd49971a278082247 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 22 Aug 2024 10:40:56 +0100 Subject: [PATCH 157/342] drivertools: fix C++20 "incomplete type" error by moving constructors below other definitions --- kernel/drivertools.h | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 8a51b88d9..079701c35 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -146,11 +146,8 @@ private: pool multiple_; public: - DriveBitMultiple() {} - DriveBitMultiple(DriveBit const &single) - { - multiple_.emplace(single); - } + DriveBitMultiple(); + DriveBitMultiple(DriveBit const &single); pool const &multiple() const { return multiple_; } @@ -467,6 +464,11 @@ public: }; +inline DriveBitMultiple::DriveBitMultiple() {} +inline DriveBitMultiple::DriveBitMultiple(DriveBit const &single) +{ + multiple_.emplace(single); +} struct DriveChunkWire { @@ -626,10 +628,7 @@ private: public: pool const &multiple() const { return multiple_; } - DriveChunkMultiple(DriveBitMultiple const &bit) : width_(1) { - for (auto const &bit : bit.multiple()) - multiple_.emplace(bit); - } + DriveChunkMultiple(DriveBitMultiple const &bit); int size() const { return width_; } @@ -1030,6 +1029,13 @@ public: } }; +inline DriveChunkMultiple::DriveChunkMultiple(DriveBitMultiple const &bit) + : width_(1) +{ + for (auto const &bit : bit.multiple()) + multiple_.emplace(bit); +} + struct DriveSpec { private: From 761eff594f0d21f73af3cfc4d9d9c3fe08d61edc Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Thu, 22 Aug 2024 11:13:58 +0100 Subject: [PATCH 158/342] functional backend: missing includes for stl containers --- kernel/functional.cc | 1 + tests/functional/vcd_harness.cc | 1 + 2 files changed, 2 insertions(+) diff --git a/kernel/functional.cc b/kernel/functional.cc index 1ece145e5..11f030eae 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -22,6 +22,7 @@ #include "kernel/topo_scc.h" #include "ff.h" #include "ffinit.h" +#include YOSYS_NAMESPACE_BEGIN namespace Functional { diff --git a/tests/functional/vcd_harness.cc b/tests/functional/vcd_harness.cc index 723217234..30238429b 100644 --- a/tests/functional/vcd_harness.cc +++ b/tests/functional/vcd_harness.cc @@ -4,6 +4,7 @@ #include #include #include +#include #include "my_module_functional_cxx.cc" From 2e1335a0233abcfc833df2b5f6169f817ed12c40 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 10:06:32 +1200 Subject: [PATCH 159/342] Docs: Fix local builds Based on the docs-test-fork PR branch, includes PR preview announcement, linking to the relevant tyrtd page --- docs/source/conf.py | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 23efe2b43..4719dc89e 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -41,13 +41,21 @@ html_static_path = ['_static', "_images"] pygments_style = 'colorful' highlight_language = 'none' -extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex', 'rtds_action'] +extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex'] -# rtds_action -rtds_action_github_repo = "YosysHQ/yosys" -rtds_action_path = "." -rtds_action_artifact_prefix = "cmd-ref-" -rtds_action_github_token = os.environ["GITHUB_TOKEN"] +if os.getenv("READTHEDOCS"): + # Use rtds_action if we are building on read the docs and have a github token env var + if os.getenv("GITHUB_TOKEN"): + extensions += ['rtds_action'] + rtds_action_github_repo = "YosysHQ/yosys" + rtds_action_path = "." + rtds_action_artifact_prefix = "cmd-ref-" + rtds_action_github_token = os.environ["GITHUB_TOKEN"] + else: + # We're on read the docs but have no github token, this is probably a PR preview build + html_theme_options["announcement"] = 'Missing content? Check PR preview limitations.' + html_theme_options["light_css_variables"]["color-announcement-background"] = "var(--color-admonition-title-background--caution)" + html_theme_options["light_css_variables"]["color-announcement-text"] = "var(--color-content-foreground)" # Ensure that autosectionlabel will produce unique names autosectionlabel_prefix_document = True From 0b53b10770f747926ecedd46a68571eb6ef1ee73 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 12:36:41 +1200 Subject: [PATCH 160/342] Makefile: Stop unconditionally install docs prereqs --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0888ae3b5..1967f0c63 100644 --- a/Makefile +++ b/Makefile @@ -1010,7 +1010,7 @@ docs/reqs: $(Q) $(MAKE) -C docs reqs DOC_TARGET ?= html -docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs +docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage $(Q) $(MAKE) -C docs $(DOC_TARGET) clean: From 5d5d890d5b8283ac42c7f912d3c23f5a70387b2c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 12:52:15 +1200 Subject: [PATCH 161/342] Docs: macos-safe build Swap `cp -u` for `rsync -t`. Drop the workaround to get the list of dot files after copying them, and instead just run the makefile twice. Swap `$(wildcard **/*.x)` for `$(shell find . -name *.x)`, --- docs/Makefile | 1 + docs/source/_images/Makefile | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index 701157ee6..8be970391 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -250,6 +250,7 @@ test-macros: .PHONY: images images: $(MAKE) -C source/_images + $(MAKE) -C source/_images convert .PHONY: reqs reqs: diff --git a/docs/source/_images/Makefile b/docs/source/_images/Makefile index 955805f9c..26cc47284 100644 --- a/docs/source/_images/Makefile +++ b/docs/source/_images/Makefile @@ -8,24 +8,22 @@ FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' CODE_EXAMPLES := ../code_examples/*/Makefile examples: $(CODE_EXAMPLES) -# target to convert specified dot file(s) +# target to convert all dot files +# needs to be run *after* examples, otherwise no dot files will be found .PHONY: convert -TARG_DOT ?= -convert: $(TARG_DOT:.dot=.pdf) $(TARG_DOT:.dot=.svg) +DOT_FILES := $(shell find . -name *.dot) +convert: $(DOT_FILES:.dot=.pdf) $(DOT_FILES:.dot=.svg) -# use empty FORCE target because .PHONY ignores % expansion, using find allows -# us to generate everything in one pass, since we don't know all of the possible -# outputs until the sub-makes run +# use empty FORCE target because .PHONY ignores % expansion FORCE: ../%/Makefile: FORCE @make -C $(@D) dots @mkdir -p $* - @find $(@D) -name *.dot -exec cp -u {} -t $* \; - @find $* -name *.dot -printf "%p " | xargs -i make --no-print-directory convert TARG_DOT="{}" + @find $(@D) -name *.dot -exec rsync -t {} $* \; # find and build all tex files .PHONY: all_tex -TEX_FILES := $(wildcard **/*.tex) +TEX_FILES := $(shell find . -name *.tex) all_tex: $(TEX_FILES:.tex=.pdf) $(TEX_FILES:.tex=.svg) %.pdf: %.dot From 7d63fdd88eb99e4d6951fd86dab87537eff3bb43 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 12:53:38 +1200 Subject: [PATCH 162/342] README: building docs on macos --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 7437bb283..c806ec283 100644 --- a/README.md +++ b/README.md @@ -629,6 +629,10 @@ following are used for building the website: $ sudo apt install pdf2svg faketime +Or for MacOS, using homebrew: + + $ brew install pdf2svg libfaketime + PDFLaTeX, included with most LaTeX distributions, is also needed during the build process for the website. Or, run the following: From 98d26bdd2c054d31cb17785e3192ccaa944972f9 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 26 Aug 2024 10:55:01 +1200 Subject: [PATCH 163/342] Docs: Fix nested list on build_verific page --- .../yosys_internals/extending_yosys/build_verific.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst index b20517bd3..2585ebae4 100644 --- a/docs/source/yosys_internals/extending_yosys/build_verific.rst +++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst @@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters, are required for the Yosys-Verific patch: * RTL elaboration with - * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or - * VHDL support with ``ENABLE_VERIFIC_VHDL``. + + * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or + * VHDL support with ``ENABLE_VERIFIC_VHDL``. + * Hierarchy tree support and static elaboration with ``ENABLE_VERIFIC_HIER_TREE``. From 83692075df13430e641c8e263c0615136dd3857e Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 27 Aug 2024 09:50:29 +1200 Subject: [PATCH 164/342] ci: Don't cancel previous builds Which is what the comment said, but the code didn't match. --- .github/workflows/test-verific.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 627a70d47..07c2aa4d1 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -13,7 +13,7 @@ jobs: with: paths_ignore: '["**/README.md"]' # don't cancel previous builds - cancel_others: 'true' + cancel_others: 'false' # only run on push *or* pull_request, not both concurrent_skipping: 'same_content_newer' # we have special actions when running on main, so this should be off From a20756676cc9dc56bdd42686525736f8145dcb84 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 27 Aug 2024 09:56:07 +1200 Subject: [PATCH 165/342] ci: Update RTDs trigger conditional Trigger on main, on a branch called `docs-preview*`, or on any tag. --- .github/workflows/test-verific.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 07c2aa4d1..181723242 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -112,7 +112,7 @@ jobs: docs/source/code_examples - name: Trigger RTDs build - if: ${{ github.ref == 'refs/heads/main' }} + if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} From ecff434886f685b1dce0637ed7af62a342d0d304 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 27 Aug 2024 10:21:31 +1200 Subject: [PATCH 166/342] Docs: Use version name from readthedocs Latest still gets -dev, but if it's a docs preview use the tag/branch name. --- docs/source/conf.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4719dc89e..2dc370c4b 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -62,8 +62,12 @@ autosectionlabel_prefix_document = True autosectionlabel_maxdepth = 1 # set version -if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest": - release = yosys_ver + "-dev" +if os.getenv("READTHEDOCS"): + rtds_version = os.getenv("READTHEDOCS_VERSION") + if rtds_version == "latest": + release = yosys_ver + "-dev" + else: + release = rtds_version else: release = yosys_ver From 459e6b913a95beed390b650fef787a466b582332 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 27 Aug 2024 11:11:02 +0100 Subject: [PATCH 167/342] add functional ir documentation --- .../extending_yosys/functional_ir.rst | 42 +++++++++++++++++++ kernel/functional.h | 1 - 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 docs/source/yosys_internals/extending_yosys/functional_ir.rst diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst new file mode 100644 index 000000000..c0794519d --- /dev/null +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -0,0 +1,42 @@ +Writing a new backend using FunctionalIR +=========================================== + +To simplify the writing of backends for functional languages or similar targets, Yosys provides an alternative intermediate representation called FunctionalIR which maps more directly on those targets. + +FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`. +This function is broken down into a series of assignments to variables. +Those assignments only use simple operations, like a simple addition. +Unlike RTLIL cells there is no support for automatically extending operands, every sign and zero extension has to be encoded as a separate operation. + +Like SSA form, each variable is assigned to exactly once. +We can thus treat variables and assignments as equivalent and, since this is a graph-like representation, those variables are also called "nodes". +Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use. + +Nodes are strongly typed, the two types (also called "sorts") available are +- `bit[n]` for an `n`-bit bitvector, and +- `memory[n,m]` for an immutable array of `2**n` values of type `bit[m]`. + +In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR. +`Functional::IR::from_module` generates an instance from an RTLIL module. +The entire design is stored as a whole in an internal data structure. +To access the design, the `Functional::Node` class provides a reference to a particular node in the design. +The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node. + +`Functional::IR` also keeps track of inputs, outputs and "states" (registers and memories). +They all have a name (equal to their name in RTLIL), a sort and a "type". +The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states. +- To access an individual input/output/"state", use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type. +- To iterate over all inputs/outputs/"states" of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned. +- To iterate over inputs/outputs/"states" of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. +- Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`. +- States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`. + They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort. + +Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see `functional.h`). +Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`. +Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern. +For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`. +Thus typically one would implement class with a method for every function. +Visitors should inherit from either `Functional::AbstractVisitor` or `Functional::DefaultVisitor`. +The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead. +Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong. \ No newline at end of file diff --git a/kernel/functional.h b/kernel/functional.h index 88a48dba9..bc7b86ac1 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -287,7 +287,6 @@ namespace Functional { bool operator!=(iterator const &other) const { return _ir != other._ir || _index != other._index; } bool operator==(iterator const &other) const { return !(*this != other); } pointer operator->(); - // TODO: implement operator-> using the arrow_proxy class currently in mem.h }; iterator begin() { return iterator(this, 0); } iterator end() { return iterator(this, _graph.size()); } From b428bf4600774b49de780e1dae7ff00f6564e72f Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 27 Aug 2024 13:10:34 +0100 Subject: [PATCH 168/342] functional backends: identifiers in c++/smtlib may not start with digits --- backends/functional/cxx.cc | 4 ++-- backends/functional/smtlib.cc | 4 ++-- kernel/functional.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 282eb8f67..de7737a42 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -48,8 +48,8 @@ template struct CxxScope : public Functional::Scope { for(const char **p = reserved_keywords; *p != nullptr; p++) this->reserve(*p); } - bool is_character_legal(char c) override { - return isascii(c) && (isalnum(c) || c == '_' || c == '$'); + bool is_character_legal(char c, int index) override { + return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || c == '_' || c == '$'); } }; diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 4e176c2fd..ae6ae40ca 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -48,8 +48,8 @@ struct SmtScope : public Functional::Scope { for(const char **p = reserved_keywords; *p != nullptr; p++) reserve(*p); } - bool is_character_legal(char c) override { - return isascii(c) && (isalnum(c) || strchr("~!@$%^&*_-+=<>.?/", c)); + bool is_character_legal(char c, int index) override { + return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c)); } }; diff --git a/kernel/functional.h b/kernel/functional.h index bc7b86ac1..2afdd7fc3 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -576,7 +576,7 @@ namespace Functional { template class Scope { protected: char substitution_character = '_'; - virtual bool is_character_legal(char) = 0; + virtual bool is_character_legal(char, int) = 0; private: pool _used_names; dict _by_id; @@ -587,7 +587,7 @@ namespace Functional { std::string unique_name(IdString suggestion) { std::string str = RTLIL::unescape_id(suggestion); for(size_t i = 0; i < str.size(); i++) - if(!is_character_legal(str[i])) + if(!is_character_legal(str[i], i)) str[i] = substitution_character; if(_used_names.count(str) == 0) { _used_names.insert(str); From 27efed27c2ed94bd9778f6b4fc9640c2ebd1bf5b Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 28 Aug 2024 11:28:24 +0100 Subject: [PATCH 169/342] functional backend: more documentation --- .../extending_yosys/functional_ir.rst | 65 +++++++++++++++---- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst index c0794519d..887d44a6e 100644 --- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -5,16 +5,17 @@ To simplify the writing of backends for functional languages or similar targets, FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`. This function is broken down into a series of assignments to variables. -Those assignments only use simple operations, like a simple addition. -Unlike RTLIL cells there is no support for automatically extending operands, every sign and zero extension has to be encoded as a separate operation. +Each assignment is a simple operation, such as an addition. +Complex operations are broken up into multiple steps. +For example, an RTLIL addition will be translated into a sign/zero extension of the inputs, followed by an addition. Like SSA form, each variable is assigned to exactly once. We can thus treat variables and assignments as equivalent and, since this is a graph-like representation, those variables are also called "nodes". Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use. -Nodes are strongly typed, the two types (also called "sorts") available are +Every node has a "sort" (the FunctionalIR term for what might otherwise be called a "type"). The sorts available are - `bit[n]` for an `n`-bit bitvector, and -- `memory[n,m]` for an immutable array of `2**n` values of type `bit[m]`. +- `memory[n,m]` for an immutable array of `2**n` values of sort `bit[m]`. In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR. `Functional::IR::from_module` generates an instance from an RTLIL module. @@ -22,12 +23,14 @@ The entire design is stored as a whole in an internal data structure. To access the design, the `Functional::Node` class provides a reference to a particular node in the design. The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node. -`Functional::IR` also keeps track of inputs, outputs and "states" (registers and memories). -They all have a name (equal to their name in RTLIL), a sort and a "type". +`Functional::IR` also keeps track of inputs, outputs and states. +By a "state" we mean a pair of a "current state" input and a "next state" output. +One such pair is created for every register and for every memory. +Every input, output and state has a name (equal to their name in RTLIL), a sort and a "type". The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states. -- To access an individual input/output/"state", use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type. -- To iterate over all inputs/outputs/"states" of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned. -- To iterate over inputs/outputs/"states" of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. +- To access an individual input/output/state, use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type. +- To iterate over all inputs/outputs/states of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned. +- To iterate over inputs/outputs/states of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. - Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`. - States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`. They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort. @@ -36,7 +39,47 @@ Each node has a "function", which defines its operation (for a complete list of Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`. Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern. For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`. -Thus typically one would implement class with a method for every function. +Thus typically one would implement a class with a method for every function. Visitors should inherit from either `Functional::AbstractVisitor` or `Functional::DefaultVisitor`. The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead. -Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong. \ No newline at end of file +Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong. + +Utility classes +----------------- + +`functional.h` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends. + +`Functional::Writer` provides a simple formatting class that wraps a `std::ostream` and provides the following methods: +- `writer << value` wraps `os << value`. +- `writer.print(fmt, value0, value1, value2, ...)` replaces `{0}`, `{1}`, `{2}`, etc in the string `fmt` with `value0`, `value1`, `value2`, resp. + Each value is formatted using `os << value`. + It is also possible to write `{}` to refer to one past the last index, i.e. `{1} {} {} {7} {}` is equivalent to `{1} {2} {3} {7} {8}`. +- `writer.print_with(fn, fmt, value0, value1, value2, ...)` functions much the same as `print` but it uses `os << fn(value)` to print each value and falls back to `os << value` if `fn(value)` is not legal. + +`Functional::Scope` keeps track of variable names in a target language. +It is used to translate between different sets of legal characters and to avoid accidentally re-defining identifiers. +Users should derive a class from `Scope` and supply the following: +- `Scope` takes a template argument that specifies a type that's used to uniquely distinguish variables. + Typically this would be `int` (if variables are used for `Functional::IR` nodes) or `IdString`. +- The derived class should provide a constructor that calls `reserve` for every reserved word in the target language. +- A method `bool is_legal_character(char c, int index)` has to be provided that returns `true` iff `c` is legal in an identifier at position `index`. +Given an instance `scope` of the derived class, the following methods are then available: +- `scope.reserve(std::string name)` marks the given name as being in-use +- `scope.unique_name(IdString suggestion)` generates a previously unused name and attempts to make it similar to `suggestion`. +- `scope(Id id, IdString suggestion)` functions similar to `unique_name`, except that multiple calls with the same `id` are guaranteed to retrieve the same name (independent of `suggestion`). + +`sexpr.h` provides classes that represent and pretty-print s-expressions. +S-expressions can be constructed with `SExpr::list`, for example `SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))` represents `(add x (mul y z))` +(by adding `using SExprUtil::list` to the top of the file, `list` can be used as shorthand for `SExpr::list`). +For prettyprinting, `SExprWriter` wraps an `std::ostream` and provides the following methods: +- `writer << sexpr` writes the provided expression to the output, breaking long lines and adding appropriate indentation. +- `writer.open(sexpr)` is similar to `writer << sexpr` but will omit the last closing parenthesis. + Further arguments can then be added separately with `<<` or `open`. + This allows for printing large s-expressions without needing the construct the whole expression in memory first. +- `writer.open(sexpr, false)` is similar to `writer.open(sexpr)` but further arguments will not be indented. + This is used to avoid unlimited indentation on structures with unlimited nesting. +- `writer.close(n = 1)` closes the last `n` open s-expressions. +- `writer.push()` and `writer.pop()` are used to automatically close s-expressions. + `writer.pop()` closes all s-expressions opened since the last call to `writer.push()`. +- `writer.comment(string)` writes a comment on a separate-line. + `writer.comment(string, true)` appends a comment to the last printed s-expression. \ No newline at end of file From 4eeb8d326acbd2c3d4fcdc4cef798abb1a2e0728 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 28 Aug 2024 12:39:41 +0100 Subject: [PATCH 170/342] functional backend: rename "type" to either "kind" or "sort" to make the terminology consistent --- backends/functional/cxx.cc | 4 +- backends/functional/smtlib.cc | 4 +- backends/functional/test_generic.cc | 4 +- .../extending_yosys/functional_ir.rst | 10 +-- kernel/functional.cc | 16 ++-- kernel/functional.h | 88 +++++++++---------- 6 files changed, 63 insertions(+), 63 deletions(-) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index de7737a42..b8b25df8b 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -151,8 +151,8 @@ template struct CxxPrintVisitor : public Functional::Abstract void arithmetic_shift_right(Node, Node a, Node b) override { print("{}.arithmetic_shift_right({})", a, b); } void mux(Node, Node a, Node b, Node s) override { print("{2}.any() ? {1} : {0}", a, b, s); } void constant(Node, RTLIL::Const const & value) override { print("{}", cxx_const(value)); } - void input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); print("input.{}", input_struct[name]); } - void state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); print("current_state.{}", state_struct[name]); } + void input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); print("input.{}", input_struct[name]); } + void state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); print("current_state.{}", state_struct[name]); } void memory_read(Node, Node mem, Node addr) override { print("{}.read({})", mem, addr); } void memory_write(Node, Node mem, Node addr, Node data) override { print("{}.write({}, {})", mem, addr, data); } }; diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index ae6ae40ca..3eacf407c 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -179,8 +179,8 @@ struct SmtPrintVisitor : public Functional::AbstractVisitor { SExpr memory_read(Node, Node mem, Node addr) override { return list("select", n(mem), n(addr)); } SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("store", n(mem), n(addr), n(data)); } - SExpr input(Node, IdString name, IdString type) override { log_assert(type == ID($input)); return input_struct.access("inputs", name); } - SExpr state(Node, IdString name, IdString type) override { log_assert(type == ID($state)); return state_struct.access("state", name); } + SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); } + SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); } }; struct SmtModule { diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index aab2260f1..10a7a50f0 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -144,9 +144,9 @@ struct FunctionalTestGeneric : public Pass for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; for(auto output : fir.all_outputs()) - std::cout << RTLIL::unescape_id(output->type) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n"; + std::cout << RTLIL::unescape_id(output->kind) << " " << RTLIL::unescape_id(output->name) << " = " << RTLIL::unescape_id(output->value().name()) << "\n"; for(auto state : fir.all_states()) - std::cout << RTLIL::unescape_id(state->type) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n"; + std::cout << RTLIL::unescape_id(state->kind) << " " << RTLIL::unescape_id(state->name) << " = " << RTLIL::unescape_id(state->next_value().name()) << "\n"; } } } FunctionalCxxBackend; diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst index 887d44a6e..38d000556 100644 --- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -26,11 +26,11 @@ The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate `Functional::IR` also keeps track of inputs, outputs and states. By a "state" we mean a pair of a "current state" input and a "next state" output. One such pair is created for every register and for every memory. -Every input, output and state has a name (equal to their name in RTLIL), a sort and a "type". -The "type" field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different type to distinguish them from ordinary RTLIL inputs/outputs/states. -- To access an individual input/output/state, use `ir.input(name, type)`, `ir.output(name, type)` or `ir.state(name, type)`. `type` defaults to the default type. -- To iterate over all inputs/outputs/states of a certain "type", methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default types mentioned. -- To iterate over inputs/outputs/states of any "type", use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. +Every input, output and state has a name (equal to their name in RTLIL), a sort and a kind. +The kind field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states. +- To access an individual input/output/state, use `ir.input(name, kind)`, `ir.output(name, kind)` or `ir.state(name, kind)`. `kind` defaults to the default kind. +- To iterate over all inputs/outputs/states of a certain kind, methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default kinds mentioned. +- To iterate over inputs/outputs/states of any kind, use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. - Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`. - States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`. They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort. diff --git a/kernel/functional.cc b/kernel/functional.cc index 11f030eae..c270a2bb6 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -67,26 +67,26 @@ const char *fn_to_string(Fn fn) { log_error("fn_to_string: unknown Functional::Fn value %d", (int)fn); } -vector IR::inputs(IdString type) const { +vector IR::inputs(IdString kind) const { vector ret; for (const auto &[name, input] : _inputs) - if(input.type == type) + if(input.kind == kind) ret.push_back(&input); return ret; } -vector IR::outputs(IdString type) const { +vector IR::outputs(IdString kind) const { vector ret; for (const auto &[name, output] : _outputs) - if(output.type == type) + if(output.kind == kind) ret.push_back(&output); return ret; } -vector IR::states(IdString type) const { +vector IR::states(IdString kind) const { vector ret; for (const auto &[name, state] : _states) - if(state.type == type) + if(state.kind == kind) ret.push_back(&state); return ret; } @@ -120,8 +120,8 @@ struct PrintVisitor : DefaultVisitor { std::string zero_extend(Node, Node a, int out_width) override { return "zero_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } std::string sign_extend(Node, Node a, int out_width) override { return "sign_extend(" + np(a) + ", " + std::to_string(out_width) + ")"; } std::string constant(Node, RTLIL::Const const& value) override { return "constant(" + value.as_string() + ")"; } - std::string input(Node, IdString name, IdString type) override { return "input(" + name.str() + ", " + type.str() + ")"; } - std::string state(Node, IdString name, IdString type) override { return "state(" + name.str() + ", " + type.str() + ")"; } + std::string input(Node, IdString name, IdString kind) override { return "input(" + name.str() + ", " + kind.str() + ")"; } + std::string state(Node, IdString name, IdString kind) override { return "state(" + name.str() + ", " + kind.str() + ")"; } std::string default_handler(Node self) override { std::string ret = fn_to_string(self.fn()); ret += "("; diff --git a/kernel/functional.h b/kernel/functional.h index 2afdd7fc3..f1fb2767f 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -34,7 +34,7 @@ namespace Functional { // each function is documented with a short pseudocode declaration or definition // standard C/Verilog operators are used to describe the result // - // the types used in this are: + // the sorts used in this are: // - bit[N]: a bitvector of N bits // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend // but is meant to indicate how the value is interpreted @@ -43,12 +43,12 @@ namespace Functional { // - int: C++ int // - Const[N]: yosys RTLIL::Const (with size() == N) // - IdString: yosys IdString - // - any: used in documentation to indicate that the type is unconstrained + // - any: used in documentation to indicate that the sort is unconstrained // - // nodes in the functional backend are either of type bit[N] or memory[N,M] (for some N, M: int) - // additionally, they can carry a constant of type int, Const[N] or IdString - // each node has a 'sort' field that stores the type of the node - // slice, zero_extend, sign_extend use the type field to store out_width + // nodes in the functional backend are either of sort bit[N] or memory[N,M] (for some N, M: int) + // additionally, they can carry a constant of sort int, Const[N] or IdString + // each node has a 'sort' field that stores the sort of the node + // slice, zero_extend, sign_extend use the sort field to store out_width enum class Fn { // invalid() = known-invalid/shouldn't happen value // TODO: maybe remove this and use e.g. std::optional instead? @@ -136,7 +136,7 @@ namespace Functional { // returns the name of a Fn value, as a string literal const char *fn_to_string(Fn); // Sort represents the sort or type of a node - // currently the only two types are signal/bit and memory + // currently the only two sorts are signal/bit and memory class Sort { std::variant> _v; public: @@ -144,11 +144,11 @@ namespace Functional { Sort(int addr_width, int data_width) : _v(std::make_pair(addr_width, data_width)) { } bool is_signal() const { return _v.index() == 0; } bool is_memory() const { return _v.index() == 1; } - // returns the width of a bitvector type, errors out for other types + // returns the width of a bitvector sort, errors out for other sorts int width() const { return std::get<0>(_v); } - // returns the address width of a bitvector type, errors out for other types + // returns the address width of a bitvector sort, errors out for other sorts int addr_width() const { return std::get<1>(_v).first; } - // returns the data width of a bitvector type, errors out for other types + // returns the data width of a bitvector sort, errors out for other sorts int data_width() const { return std::get<1>(_v).second; } bool operator==(Sort const& other) const { return _v == other._v; } unsigned int hash() const { return mkhash(_v); } @@ -160,22 +160,22 @@ namespace Functional { friend class Factory; public: IdString name; - IdString type; + IdString kind; Sort sort; private: - IRInput(IR &, IdString name, IdString type, Sort sort) - : name(name), type(type), sort(std::move(sort)) {} + IRInput(IR &, IdString name, IdString kind, Sort sort) + : name(name), kind(kind), sort(std::move(sort)) {} }; class IROutput { friend class Factory; IR &_ir; public: IdString name; - IdString type; + IdString kind; Sort sort; private: - IROutput(IR &ir, IdString name, IdString type, Sort sort) - : _ir(ir), name(name), type(type), sort(std::move(sort)) {} + IROutput(IR &ir, IdString name, IdString kind, Sort sort) + : _ir(ir), name(name), kind(kind), sort(std::move(sort)) {} public: Node value() const; bool has_value() const; @@ -186,12 +186,12 @@ namespace Functional { IR &_ir; public: IdString name; - IdString type; + IdString kind; Sort sort; private: std::variant _initial; - IRState(IR &ir, IdString name, IdString type, Sort sort) - : _ir(ir), name(name), type(type), sort(std::move(sort)) {} + IRState(IR &ir, IdString name, IdString kind, Sort sort) + : _ir(ir), name(name), kind(kind), sort(std::move(sort)) {} public: Node next_value() const; bool has_next_value() const; @@ -253,20 +253,20 @@ namespace Functional { Node operator[](int i); void topological_sort(); void forward_buf(); - IRInput const& input(IdString name, IdString type) const { return _inputs.at({name, type}); } + IRInput const& input(IdString name, IdString kind) const { return _inputs.at({name, kind}); } IRInput const& input(IdString name) const { return input(name, ID($input)); } - IROutput const& output(IdString name, IdString type) const { return _outputs.at({name, type}); } + IROutput const& output(IdString name, IdString kind) const { return _outputs.at({name, kind}); } IROutput const& output(IdString name) const { return output(name, ID($output)); } - IRState const& state(IdString name, IdString type) const { return _states.at({name, type}); } + IRState const& state(IdString name, IdString kind) const { return _states.at({name, kind}); } IRState const& state(IdString name) const { return state(name, ID($state)); } - bool has_input(IdString name, IdString type) const { return _inputs.count({name, type}); } - bool has_output(IdString name, IdString type) const { return _outputs.count({name, type}); } - bool has_state(IdString name, IdString type) const { return _states.count({name, type}); } - vector inputs(IdString type) const; + bool has_input(IdString name, IdString kind) const { return _inputs.count({name, kind}); } + bool has_output(IdString name, IdString kind) const { return _outputs.count({name, kind}); } + bool has_state(IdString name, IdString kind) const { return _states.count({name, kind}); } + vector inputs(IdString kind) const; vector inputs() const { return inputs(ID($input)); } - vector outputs(IdString type) const; + vector outputs(IdString kind) const; vector outputs() const { return outputs(ID($output)); } - vector states(IdString type) const; + vector states(IdString kind) const; vector states() const { return states(ID($state)); } vector all_inputs() const; vector all_outputs() const; @@ -364,12 +364,12 @@ namespace Functional { }; inline IR::Graph::Ref IR::mutate(Node n) { return _graph[n._ref.index()]; } inline Node IR::operator[](int i) { return Node(_graph[i]); } - inline Node IROutput::value() const { return Node(_ir._graph({name, type, false})); } - inline bool IROutput::has_value() const { return _ir._graph.has_key({name, type, false}); } - inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, false}); } - inline Node IRState::next_value() const { return Node(_ir._graph({name, type, true})); } - inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, type, true}); } - inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, type, true}); } + inline Node IROutput::value() const { return Node(_ir._graph({name, kind, false})); } + inline bool IROutput::has_value() const { return _ir._graph.has_key({name, kind, false}); } + inline void IROutput::set_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, false}); } + inline Node IRState::next_value() const { return Node(_ir._graph({name, kind, true})); } + inline bool IRState::has_next_value() const { return _ir._graph.has_key({name, kind, true}); } + inline void IRState::set_next_value(Node value) { log_assert(sort == value.sort()); _ir.mutate(value).assign_key({name, kind, true}); } inline Node IR::iterator::operator*() { return Node(_ir->_graph[_index]); } inline arrow_proxy IR::iterator::operator->() { return arrow_proxy(**this); } // AbstractVisitor provides an abstract base class for visitors @@ -403,8 +403,8 @@ namespace Functional { virtual T arithmetic_shift_right(Node self, Node a, Node b) = 0; virtual T mux(Node self, Node a, Node b, Node s) = 0; virtual T constant(Node self, RTLIL::Const const & value) = 0; - virtual T input(Node self, IdString name, IdString type) = 0; - virtual T state(Node self, IdString name, IdString type) = 0; + virtual T input(Node self, IdString name, IdString kind) = 0; + virtual T state(Node self, IdString name, IdString kind) = 0; virtual T memory_read(Node self, Node mem, Node addr) = 0; virtual T memory_write(Node self, Node mem, Node addr, Node data) = 0; }; @@ -547,26 +547,26 @@ namespace Functional { log_assert(node.sort() == value.sort()); _ir.mutate(node).append_arg(value._ref); } - IRInput &add_input(IdString name, IdString type, Sort sort) { - auto [it, inserted] = _ir._inputs.emplace({name, type}, IRInput(_ir, name, type, std::move(sort))); + IRInput &add_input(IdString name, IdString kind, Sort sort) { + auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort))); if (!inserted) log_error("input `%s` was re-defined", name.c_str()); return it->second; } - IROutput &add_output(IdString name, IdString type, Sort sort) { - auto [it, inserted] = _ir._outputs.emplace({name, type}, IROutput(_ir, name, type, std::move(sort))); + IROutput &add_output(IdString name, IdString kind, Sort sort) { + auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort))); if (!inserted) log_error("output `%s` was re-defined", name.c_str()); return it->second; } - IRState &add_state(IdString name, IdString type, Sort sort) { - auto [it, inserted] = _ir._states.emplace({name, type}, IRState(_ir, name, type, std::move(sort))); + IRState &add_state(IdString name, IdString kind, Sort sort) { + auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort))); if (!inserted) log_error("state `%s` was re-defined", name.c_str()); return it->second; } Node value(IRInput const& input) { - return add(IR::NodeData(Fn::input, std::pair(input.name, input.type)), input.sort, {}); + return add(IR::NodeData(Fn::input, std::pair(input.name, input.kind)), input.sort, {}); } Node value(IRState const& state) { - return add(IR::NodeData(Fn::state, std::pair(state.name, state.type)), state.sort, {}); + return add(IR::NodeData(Fn::state, std::pair(state.name, state.kind)), state.sort, {}); } void suggest_name(Node node, IdString name) { _ir.mutate(node).sparse_attr() = name; From bdb5d45591d7501825349bedcb2952d0b80a1112 Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 28 Aug 2024 15:38:27 +0100 Subject: [PATCH 171/342] proc_dff: respect sync rule priorities when generating complex dffsrs * This fixes #4560, where previously the order that sync rules were processed in depended on the order they were pulled out of a std::map. This PR changes this to process them in the order they are found in, respecting the priorities among the async signals --- passes/proc/proc_dff.cc | 205 ++++++++++++++-------------------------- 1 file changed, 73 insertions(+), 132 deletions(-) diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index fd56786f2..3aad9ac1c 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -54,90 +54,35 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc) } void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity, - std::map> &async_rules, RTLIL::Process *proc) + std::vector> &async_rules, RTLIL::Process *proc) { + // A signal should be set/cleared if there is a load trigger that is enabled + // such that the load value is 1/0 and it is the highest priority trigger RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size()); RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size()); - for (auto &it : async_rules) + // Reverse iterate through the rules as the first ones are the highest priority + // so need to be at the top of the mux trees + for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++) { - RTLIL::SigSpec sync_value = it.first; - RTLIL::SigSpec sync_value_inv; - RTLIL::SigSpec sync_high_signals; - RTLIL::SigSpec sync_low_signals; + const auto& [sync_value, rule] = *it; + const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal); - for (auto &it2 : it.second) - if (it2->type == RTLIL::SyncType::ST0) - sync_low_signals.append(it2->signal); - else if (it2->type == RTLIL::SyncType::ST1) - sync_high_signals.append(it2->signal); - else - log_abort(); + // If pos_trig is true, we have priority at this point in the tree so + // set a bit if sync_value has a set bit. Otherwise, defer to the rest + // of the priority tree + sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig); - if (sync_low_signals.size() > 1) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or)); - cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); - cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size()); - cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - cell->setPort(ID::A, sync_low_signals); - cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID)); - } - - if (sync_low_signals.size() > 0) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not)); - cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); - cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size()); - cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - cell->setPort(ID::A, sync_low_signals); - cell->setPort(ID::Y, mod->addWire(NEW_ID)); - sync_high_signals.append(cell->getPort(ID::Y)); - } - - if (sync_high_signals.size() > 1) { - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or)); - cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); - cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size()); - cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - cell->setPort(ID::A, sync_high_signals); - cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID)); - } - - RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not)); - inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); - inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size()); - inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size()); - inv_cell->setPort(ID::A, sync_value); - inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); - - RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux)); - mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); - mux_set_cell->setPort(ID::A, sig_sr_set); - mux_set_cell->setPort(ID::B, sync_value); - mux_set_cell->setPort(ID::S, sync_high_signals); - mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); - - RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux)); - mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); - mux_clr_cell->setPort(ID::A, sig_sr_clr); - mux_clr_cell->setPort(ID::B, sync_value_inv); - mux_clr_cell->setPort(ID::S, sync_high_signals); - mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size())); + // Same deal with clear bit + const auto sync_value_inv = mod->Not(NEW_ID, sync_value); + sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig); } std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr)); + RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity); cell->attributes = proc->attributes; - cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size()); - cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1); - cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1); - cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1); - cell->setPort(ID::D, sig_d); - cell->setPort(ID::Q, sig_q); - cell->setPort(ID::CLK, clk); - cell->setPort(ID::SET, sig_sr_set); - cell->setPort(ID::CLR, sig_sr_clr); log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); @@ -204,7 +149,6 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) while (1) { RTLIL::SigSpec sig = find_any_lvalue(proc); - bool free_sync_level = false; if (sig.size() == 0) break; @@ -213,13 +157,17 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); - RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); - RTLIL::SyncRule *sync_level = NULL; RTLIL::SyncRule *sync_edge = NULL; RTLIL::SyncRule *sync_always = NULL; bool global_clock = false; - std::map> many_async_rules; + // A priority ordered set of rules, pairing the value to be assigned for + // that rule to the rule + std::vector> async_rules; + + // Needed when the async rules are collapsed into one as async_rules + // works with pointers to SyncRule + RTLIL::SyncRule single_async_rule; for (auto sync : proc->syncs) for (auto &action : sync->actions) @@ -228,14 +176,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) continue; if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) { - if (sync_level != NULL && sync_level != sync) { - // log_error("Multiple level sensitive events found for this signal!\n"); - many_async_rules[rstval].insert(sync_level); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); - } - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); + RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); sig.replace(action.first, action.second, &rstval); - sync_level = sync; + async_rules.emplace_back(rstval, sync); } else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) { if (sync_edge != NULL && sync_edge != sync) @@ -260,59 +203,51 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) action.first.remove2(sig, &action.second); } - if (many_async_rules.size() > 0) + // If all async rules assign the same value, priority ordering between + // them doesn't matter so they can be collapsed together into one rule + // with the disjunction of triggers + if (!async_rules.empty() && + std::all_of(async_rules.begin(), async_rules.end(), [&](auto& p) { + return p.first == async_rules.front().first; + })) { - many_async_rules[rstval].insert(sync_level); - if (many_async_rules.size() == 1) - { - sync_level = new RTLIL::SyncRule; - sync_level->type = RTLIL::SyncType::ST1; - sync_level->signal = mod->addWire(NEW_ID); - sync_level->actions.push_back(RTLIL::SigSig(sig, rstval)); - free_sync_level = true; + const auto rstval = async_rules.front().first; - RTLIL::SigSpec inputs, compare; - for (auto &it : many_async_rules[rstval]) { - inputs.append(it->signal); - compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0); - } - log_assert(inputs.size() == compare.size()); + // The trigger is the disjunction of existing triggers + // (with appropriate negation) + RTLIL::SigSpec triggers; + for (const auto &[_, it] : async_rules) + triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal)); - RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne)); - cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1); - cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1); - cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size()); - cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size()); - cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1); - cell->setPort(ID::A, inputs); - cell->setPort(ID::B, compare); - cell->setPort(ID::Y, sync_level->signal); + // Put this into the dummy sync rule so it can be treated the same + // as ones coming from the module + single_async_rule.type = RTLIL::SyncType::ST1; + single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers); + single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval)); - many_async_rules.clear(); - } - else - { - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); - sync_level = NULL; - } + // Replace existing rules with this new rule + async_rules.clear(); + async_rules.emplace_back(rstval, &single_async_rule); } SigSpec sig_q = sig; ce.assign_map.apply(insig); - ce.assign_map.apply(rstval); ce.assign_map.apply(sig); - if (rstval == sig && sync_level) { - if (sync_level->type == RTLIL::SyncType::ST1) - insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal); + // If the reset value assigns the reg to itself, add this as part of + // the input signal and delete the rule + if (async_rules.size() == 1 && async_rules.front().first == sig) { + const auto& [_, rule] = async_rules.front(); + if (rule->type == RTLIL::SyncType::ST1) + insig = mod->Mux(NEW_ID, insig, sig, rule->signal); else - insig = mod->Mux(NEW_ID, sig, insig, sync_level->signal); - rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); - sync_level = NULL; + insig = mod->Mux(NEW_ID, sig, insig, rule->signal); + + async_rules.clear(); } if (sync_always) { - if (sync_edge || sync_level || many_async_rules.size() > 0) + if (sync_edge || !async_rules.empty()) log_error("Mixed always event with edge and/or level sensitive events!\n"); log(" created direct connection (no actual register cell created).\n"); mod->connect(RTLIL::SigSig(sig, insig)); @@ -322,28 +257,34 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (!sync_edge && !global_clock) log_error("Missing edge-sensitive event for this signal!\n"); - if (many_async_rules.size() > 0) + // More than one reset value so we derive a dffsr formulation + if (async_rules.size() > 1) { log_warning("Complex async reset for dff `%s'.\n", log_signal(sig)); - gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc); + gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc); + return; } - else if (!rstval.is_fully_const() && !ce.eval(rstval)) + + // If there is a reset condition in the async rules, use it + SigSpec rstval = async_rules.empty() ? RTLIL::SigSpec(RTLIL::State::Sz, sig.size()) : async_rules.front().first; + RTLIL::SyncRule* sync_level = async_rules.empty() ? nullptr : async_rules.front().second; + ce.assign_map.apply(rstval); + + if (!rstval.is_fully_const() && !ce.eval(rstval)) { log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval)); gen_aldff(mod, insig, rstval, sig_q, sync_edge->type == RTLIL::SyncType::STp, sync_level && sync_level->type == RTLIL::SyncType::ST1, sync_edge->signal, sync_level->signal, proc); + return; } - else - gen_dff(mod, insig, rstval.as_const(), sig_q, - sync_edge && sync_edge->type == RTLIL::SyncType::STp, - sync_level && sync_level->type == RTLIL::SyncType::ST1, - sync_edge ? sync_edge->signal : SigSpec(), - sync_level ? &sync_level->signal : NULL, proc); - if (free_sync_level) - delete sync_level; + gen_dff(mod, insig, rstval.as_const(), sig_q, + sync_edge && sync_edge->type == RTLIL::SyncType::STp, + sync_level && sync_level->type == RTLIL::SyncType::ST1, + sync_edge ? sync_edge->signal : SigSpec(), + sync_level ? &sync_level->signal : NULL, proc); } } From 8206951f77a95f0d7818d98aaf3e577a7aff5fae Mon Sep 17 00:00:00 2001 From: George Rennie Date: Wed, 28 Aug 2024 16:24:47 +0100 Subject: [PATCH 172/342] proc_dff: add tests --- tests/proc/proc_dff.ys | 80 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 tests/proc/proc_dff.ys diff --git a/tests/proc/proc_dff.ys b/tests/proc/proc_dff.ys new file mode 100644 index 000000000..1b719da36 --- /dev/null +++ b/tests/proc/proc_dff.ys @@ -0,0 +1,80 @@ +read_verilog -formal < Date: Thu, 29 Aug 2024 13:14:18 +0100 Subject: [PATCH 173/342] functional backend: add test to verify test_generic --- Makefile | 5 +++-- tests/functional/test_functional.py | 8 +++++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index e61948cb4..fbe099042 100644 --- a/Makefile +++ b/Makefile @@ -1052,9 +1052,10 @@ clean_coverage: find . -name "*.gcda" -type f -delete coverage_functional: - rm -rf coverage.info coverage_html + rm -rf coverage.info coverage2.info coverage_html lcov --capture -d backends/functional --no-external -o coverage.info - genhtml coverage.info --output-directory coverage_html + lcov --capture -d kernel --include kernel/functional.cc --include kernel/functional.h --include kernel/sexpr.cc --include kernel/sexpr.h --include kernel/compute_graph.h --no-external -o coverage2.info + genhtml coverage.info coverage2.info --output-directory coverage_html qtcreator: echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 107ca6862..55e4acc33 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -70,4 +70,10 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_smt2 {quote(smt_file)}") run(['z3', smt_file]) # check if output is valid smtlib before continuing smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) - yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) \ No newline at end of file + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) + +def test_print_graph(tmp_path): + tb_file = base_path / 'tests/functional/picorv32_tb.v' + cpu_file = base_path / 'tests/functional/picorv32.v' + # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl + yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; flatten; clk2fflogic; test_generic") From 840c515ffc61cf6c8f5b79f9435c8fabbc8f7c75 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 10:20:24 +1200 Subject: [PATCH 174/342] RTDs: Fail on warning Fix outstanding sphinx warnings; - Change mycells.lib to use `text` parsing instead of (currently) unsupported `Liberty`. - Remove unused `troubleshooting.rst`, moving the todo into the index. --- .readthedocs.yaml | 1 + docs/source/using_yosys/more_scripting/index.rst | 2 ++ docs/source/using_yosys/more_scripting/troubleshooting.rst | 6 ------ docs/source/using_yosys/synthesis/cell_libs.rst | 4 +++- 4 files changed, 6 insertions(+), 7 deletions(-) delete mode 100644 docs/source/using_yosys/more_scripting/troubleshooting.rst diff --git a/.readthedocs.yaml b/.readthedocs.yaml index cb700dc1c..4a04219de 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -13,6 +13,7 @@ formats: sphinx: configuration: docs/source/conf.py + fail_on_warning: true python: install: diff --git a/docs/source/using_yosys/more_scripting/index.rst b/docs/source/using_yosys/more_scripting/index.rst index 490a5a7ad..090b9e0b9 100644 --- a/docs/source/using_yosys/more_scripting/index.rst +++ b/docs/source/using_yosys/more_scripting/index.rst @@ -3,6 +3,8 @@ More scripting .. todo:: brief overview for the more scripting index +.. todo:: troubleshooting document(?) + .. toctree:: :maxdepth: 3 diff --git a/docs/source/using_yosys/more_scripting/troubleshooting.rst b/docs/source/using_yosys/more_scripting/troubleshooting.rst deleted file mode 100644 index a17a552d2..000000000 --- a/docs/source/using_yosys/more_scripting/troubleshooting.rst +++ /dev/null @@ -1,6 +0,0 @@ -Troubleshooting -~~~~~~~~~~~~~~~ - -.. todo:: troubleshooting document(?) - -See :doc:`/cmd/bugpoint` diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst index 92b6dab3f..4e800bdf2 100644 --- a/docs/source/using_yosys/synthesis/cell_libs.rst +++ b/docs/source/using_yosys/synthesis/cell_libs.rst @@ -90,8 +90,10 @@ Mapping to hardware For this example, we are using a Liberty file to describe a cell library which our internal cell library will be mapped to: +.. todo:: find a Liberty pygments style? + .. literalinclude:: /code_examples/intro/mycells.lib - :language: Liberty + :language: text :linenos: :name: mycells-lib :caption: :file:`mycells.lib` From a97d99cbac73d52b71aeea655790fd5877617e97 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 11:00:28 +1200 Subject: [PATCH 175/342] ci: Verific skipping conditional on github.ref Docs jobs should not skip on concurrent jobs (in case a non-docs job is already running, such as when a commit has been tagged for docs-preview). However, a successful `test-verific` can allow for a future docs job to skip testing and go straight to the preview. --- .github/workflows/test-verific.yml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 181723242..c7190fd18 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -1,6 +1,10 @@ name: Build and run tests with Verific (Linux) on: [push, pull_request] +# docs builds are needed for anything on main, any tagged versions, and any tag +# or branch starting with docs-preview +env: + is_docs_job: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} jobs: pre-job: @@ -16,8 +20,8 @@ jobs: cancel_others: 'false' # only run on push *or* pull_request, not both concurrent_skipping: 'same_content_newer' - # we have special actions when running on main, so this should be off - skip_after_successful_duplicate: 'false' + # we can skip testing if it has already passed + skip_after_successful_duplicate: 'true' test-verific: needs: pre-job @@ -74,7 +78,6 @@ jobs: prepare-docs: name: Generate docs artifact needs: [pre-job, test-verific] - if: needs.pre-job.outputs.should_skip != 'true' runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -82,11 +85,13 @@ jobs: with: persist-credentials: false submodules: true + - name: Runtime environment run: | echo "procs=$(nproc)" >> $GITHUB_ENV - name: Build Yosys + if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} run: | make config-clang echo "ENABLE_VERIFIC := 1" >> Makefile.conf @@ -97,11 +102,13 @@ jobs: make -j${{ env.procs }} ENABLE_LTO=1 - name: Prepare docs + if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} shell: bash run: make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS= - name: Upload artifact + if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} uses: actions/upload-artifact@v4 with: name: cmd-ref-${{ github.sha }} @@ -112,7 +119,7 @@ jobs: docs/source/code_examples - name: Trigger RTDs build - if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + if: ${{ env.is_docs_job }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} From cab781d958476a1f549084f26965021988167a13 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 29 Aug 2024 09:58:41 +1200 Subject: [PATCH 176/342] Makefile: Move docs prereqs to separate target --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1967f0c63..21608126d 100644 --- a/Makefile +++ b/Makefile @@ -1009,8 +1009,11 @@ docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE docs/reqs: $(Q) $(MAKE) -C docs reqs +.PHONY: docs/prep +docs/prep: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage + DOC_TARGET ?= html -docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage +docs: docs/prep $(Q) $(MAKE) -C docs $(DOC_TARGET) clean: From 6c833d83b8670694d0216858527e893443b5374a Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 29 Aug 2024 09:59:20 +1200 Subject: [PATCH 177/342] ci: Use docs/prep target --- .github/workflows/test-verific.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index c7190fd18..1b38b5f42 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -105,7 +105,7 @@ jobs: if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} shell: bash run: - make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS= + make docs/prep TARGETS= EXTRA_TARGETS= - name: Upload artifact if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} From e92de01ab30c5402ff633a99c6a696a67785b11f Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 11:40:47 +1200 Subject: [PATCH 178/342] ci: Split out prepare-docs --- .github/workflows/prepare-docs.yml | 52 ++++++++++++++++++++++++++++ .github/workflows/test-verific.yml | 55 ------------------------------ 2 files changed, 52 insertions(+), 55 deletions(-) create mode 100644 .github/workflows/prepare-docs.yml diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml new file mode 100644 index 000000000..9233e6295 --- /dev/null +++ b/.github/workflows/prepare-docs.yml @@ -0,0 +1,52 @@ +name: Build docs artifact with Verific + +on: push + +jobs: + prepare-docs: + # docs builds are needed for anything on main, any tagged versions, and any tag + # or branch starting with docs-preview + if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + runs-on: [self-hosted, linux, x64, fast] + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + persist-credentials: false + submodules: true + + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV + + - name: Build Yosys + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j${{ env.procs }} ENABLE_LTO=1 + + - name: Prepare docs + shell: bash + run: + make docs/prep TARGETS= EXTRA_TARGETS= + + - name: Upload artifact + uses: actions/upload-artifact@v4 + with: + name: cmd-ref-${{ github.sha }} + path: | + docs/source/cmd + docs/source/generated + docs/source/_images + docs/source/code_examples + + - name: Trigger RTDs build + uses: dfm/rtds-action@v1.1.0 + with: + webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} + webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }} + commit_ref: ${{ github.ref }} diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 1b38b5f42..7b55be779 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -1,10 +1,6 @@ name: Build and run tests with Verific (Linux) on: [push, pull_request] -# docs builds are needed for anything on main, any tagged versions, and any tag -# or branch starting with docs-preview -env: - is_docs_job: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} jobs: pre-job: @@ -74,54 +70,3 @@ jobs: if: ${{ github.ref == 'refs/heads/main' }} run: | make -C sby run_ci - - prepare-docs: - name: Generate docs artifact - needs: [pre-job, test-verific] - runs-on: [self-hosted, linux, x64, fast] - steps: - - name: Checkout Yosys - uses: actions/checkout@v4 - with: - persist-credentials: false - submodules: true - - - name: Runtime environment - run: | - echo "procs=$(nproc)" >> $GITHUB_ENV - - - name: Build Yosys - if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} - run: | - make config-clang - echo "ENABLE_VERIFIC := 1" >> Makefile.conf - echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf - echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf - echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf - echo "ENABLE_CCACHE := 1" >> Makefile.conf - make -j${{ env.procs }} ENABLE_LTO=1 - - - name: Prepare docs - if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} - shell: bash - run: - make docs/prep TARGETS= EXTRA_TARGETS= - - - name: Upload artifact - if: ${{ (needs.pre-job.outputs.should_skip != 'true') || env.is_docs_job }} - uses: actions/upload-artifact@v4 - with: - name: cmd-ref-${{ github.sha }} - path: | - docs/source/cmd - docs/source/generated - docs/source/_images - docs/source/code_examples - - - name: Trigger RTDs build - if: ${{ env.is_docs_job }} - uses: dfm/rtds-action@v1.1.0 - with: - webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} - webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }} - commit_ref: ${{ github.ref }} From 25623b1010bcdb00f6b16724687aea63494d38b8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 11:45:00 +1200 Subject: [PATCH 179/342] ci: test-verific no longer needs special casing --- .github/workflows/test-verific.yml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 7b55be779..43b68e06d 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -11,13 +11,11 @@ jobs: - id: skip_check uses: fkirc/skip-duplicate-actions@v5 with: - paths_ignore: '["**/README.md"]' - # don't cancel previous builds - cancel_others: 'false' + paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' + # cancel previous builds if a new commit is pushed + cancel_others: 'true' # only run on push *or* pull_request, not both concurrent_skipping: 'same_content_newer' - # we can skip testing if it has already passed - skip_after_successful_duplicate: 'true' test-verific: needs: pre-job From 558f313a78ecdf3ad6692ac17a4aede4afe23a73 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 29 Aug 2024 10:43:01 +1200 Subject: [PATCH 180/342] Docs: Show todos in previews That includes local builds. Also fix release version numbers. --- docs/source/conf.py | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 2dc370c4b..723a0ea7f 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -61,15 +61,24 @@ if os.getenv("READTHEDOCS"): autosectionlabel_prefix_document = True autosectionlabel_maxdepth = 1 +# include todos for previews +extensions.append('sphinx.ext.todo') + # set version if os.getenv("READTHEDOCS"): rtds_version = os.getenv("READTHEDOCS_VERSION") if rtds_version == "latest": release = yosys_ver + "-dev" + todo_include_todos = False + elif rtds_version.startswith("yosys-"): + release = yosys_ver + todo_include_todos = False else: release = rtds_version + todo_include_todos = True else: release = yosys_ver + todo_include_todos = True # assign figure numbers numfig = True @@ -84,10 +93,6 @@ latex_elements = { ''' } -# include todos during rewrite -extensions.append('sphinx.ext.todo') -todo_include_todos = False - # custom cmd-ref parsing/linking sys.path += [os.path.dirname(__file__) + "/../"] extensions.append('util.cmdref') From 6b9321250b25c6904daca34f56b502bafd9dfb35 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 3 Sep 2024 00:20:12 +0000 Subject: [PATCH 181/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0888ae3b5..8b3b72196 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.44+60 +YOSYS_VER := 0.44+71 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From c0ce0b82a8382dca94fe501aa624a20198bbd10d Mon Sep 17 00:00:00 2001 From: "Emily (aiju)" Date: Thu, 22 Aug 2024 11:54:20 +0100 Subject: [PATCH 182/342] docs: gvpack on macos requires the file name to appear after the flags --- docs/source/code_examples/opt/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/code_examples/opt/Makefile b/docs/source/code_examples/opt/Makefile index 4cb51e90b..12c1c93b1 100644 --- a/docs/source/code_examples/opt/Makefile +++ b/docs/source/code_examples/opt/Makefile @@ -13,7 +13,7 @@ dots: $(DOTS) $(YOSYS) $< %.dot: %_full.dot - gvpack -u $*_full.dot -o $@ + gvpack -u -o $@ $*_full.dot .PHONY: clean clean: From 9c1bcb38d97eca203e44872109a9d1e92c363c4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 3 Sep 2024 08:53:51 +0200 Subject: [PATCH 183/342] write_xaiger: Get by without endianness helpers --- backends/aiger/xaiger.cc | 60 ++++++++-------------------------------- 1 file changed, 11 insertions(+), 49 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 68c2ff52f..3ca8b205a 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -18,32 +18,6 @@ * */ -// https://stackoverflow.com/a/46137633 -#ifdef _MSC_VER -#include -#define bswap32 _byteswap_ulong -#elif defined(__APPLE__) -#include -#define bswap32 OSSwapInt32 -#elif defined(__GNUC__) -#define bswap32 __builtin_bswap32 -#else -#include -inline static uint32_t bswap32(uint32_t x) -{ - // https://stackoverflow.com/a/27796212 - register uint32_t value = number_to_be_reversed; - uint8_t lolo = (value >> 0) & 0xFF; - uint8_t lohi = (value >> 8) & 0xFF; - uint8_t hilo = (value >> 16) & 0xFF; - uint8_t hihi = (value >> 24) & 0xFF; - return (hihi << 24) - | (hilo << 16) - | (lohi << 8) - | (lolo << 0); -} -#endif - #include "kernel/yosys.h" #include "kernel/sigtools.h" #include "kernel/utils.h" @@ -52,16 +26,6 @@ inline static uint32_t bswap32(uint32_t x) USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -inline int32_t to_big_endian(int32_t i32) { -#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ - return bswap32(i32); -#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ - return i32; -#else -#error "Unknown endianness" -#endif -} - void aiger_encode(std::ostream &f, int x) { log_assert(x >= 0); @@ -537,9 +501,12 @@ struct XAigerWriter f << "c"; - auto write_buffer = [](std::stringstream &buffer, int i32) { - int32_t i32_be = to_big_endian(i32); - buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); + auto write_buffer = [](std::ostream &buffer, unsigned int u32) { + typedef unsigned char uchar; + unsigned char u32_be[4] = { + (uchar) (u32 >> 24), (uchar) (u32 >> 16), (uchar) (u32 >> 8), (uchar) u32 + }; + buffer.write((char *) u32_be, sizeof(u32_be)); }; std::stringstream h_buffer; auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1); @@ -640,14 +607,12 @@ struct XAigerWriter f << "r"; std::string buffer_str = r_buffer.str(); - int32_t buffer_size_be = to_big_endian(buffer_str.size()); - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + write_buffer(f, buffer_str.size()); f.write(buffer_str.data(), buffer_str.size()); f << "s"; buffer_str = s_buffer.str(); - buffer_size_be = to_big_endian(buffer_str.size()); - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + write_buffer(f, buffer_str.size()); f.write(buffer_str.data(), buffer_str.size()); RTLIL::Design *holes_design; @@ -664,22 +629,19 @@ struct XAigerWriter f << "a"; std::string buffer_str = a_buffer.str(); - int32_t buffer_size_be = to_big_endian(buffer_str.size()); - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + write_buffer(f, buffer_str.size()); f.write(buffer_str.data(), buffer_str.size()); } } f << "h"; std::string buffer_str = h_buffer.str(); - int32_t buffer_size_be = to_big_endian(buffer_str.size()); - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + write_buffer(f, buffer_str.size()); f.write(buffer_str.data(), buffer_str.size()); f << "i"; buffer_str = i_buffer.str(); - buffer_size_be = to_big_endian(buffer_str.size()); - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + write_buffer(f, buffer_str.size()); f.write(buffer_str.data(), buffer_str.size()); //f << "o"; //buffer_str = o_buffer.str(); From 89cbca4f44aec2912024a0f60d8a14244bf323f9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 3 Sep 2024 09:15:12 +0200 Subject: [PATCH 184/342] Add macOS instructions for latexpdf --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index c806ec283..d215d8442 100644 --- a/README.md +++ b/README.md @@ -638,6 +638,12 @@ build process for the website. Or, run the following: $ sudo apt install texlive-latex-base texlive-latex-extra latexmk +Or for MacOS, using homebrew: + + $ brew install basictex + $ sudo tlmgr update --self + $ sudo tlmgr install collection-latexextra latexmk tex-gyre + The Python package, Sphinx, is needed along with those listed in `docs/source/requirements.txt`: From 556c705a897015f940fa4199fc1c9cfb70f5b850 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 3 Sep 2024 10:15:50 +0200 Subject: [PATCH 185/342] Cleanup of synth_nanoxplore pass --- techlibs/nanoxplore/synth_nanoxplore.cc | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 8349caa21..4674559fb 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -53,7 +53,6 @@ struct SynthNanoXplorePass : public ScriptPass log(" - medium: NG-Medium\n"); log(" - large: NG-Large\n"); log(" - ultra: NG-Ultra\n"); - log(" - u300: NG-Ultra300\n"); log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); @@ -90,9 +89,6 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nobram\n"); log(" do not use block NX_RAM cells in output netlist\n"); log("\n"); - log(" -nodsp\n"); - log(" do not map multipliers to NX_DSP cells\n"); - log("\n"); log(" -noiopad\n"); log(" do not insert IO buffers\n"); log("\n"); @@ -108,7 +104,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, nodffe, norfram, nobram, nodsp, noiopad, no_rw_check; + bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; std::string postfix; int min_ce_use, min_srst_use; @@ -123,7 +119,6 @@ struct SynthNanoXplorePass : public ScriptPass nodffe = false; norfram = false; nobram = false; - nodsp = false; noiopad = false; no_rw_check = false; postfix = ""; @@ -195,10 +190,6 @@ struct SynthNanoXplorePass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-nodsp") { - nodsp = true; - continue; - } if (args[argidx] == "-iopad") { noiopad = false; continue; @@ -222,8 +213,6 @@ struct SynthNanoXplorePass : public ScriptPass if (family == "ultra") { postfix = "_u"; - } else if (family == "u300") { - postfix = "_u"; } else if (family == "medium") { postfix = "_m"; } else if (family == "large") { From 3e0dc2ff1ee0dfec10e96b7eaaa774231ba4a248 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 3 Sep 2024 10:28:56 +0200 Subject: [PATCH 186/342] Release version 0.45 --- CHANGELOG | 7 ++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 3d22bfe60..855d6f597 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,13 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.44 .. Yosys 0.45-dev +Yosys 0.44 .. Yosys 0.45 -------------------------- + * Various + - Added cell types help messages. + + * New back-ends + - Added initial NG-Ultra support. ( synth_nanoxplore ) Yosys 0.43 .. Yosys 0.44 -------------------------- diff --git a/Makefile b/Makefile index 209eac337..fc2955f1d 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.44+71 +YOSYS_VER := 0.45 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -169,7 +169,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 723a0ea7f..4b7dc1737 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,7 +5,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2024 YosysHQ GmbH' -yosys_ver = "0.44" +yosys_ver = "0.45" # select HTML theme html_theme = 'furo' From 9ed031ddd588442f22be13ce608547a5809b62f0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 3 Sep 2024 12:28:25 +0200 Subject: [PATCH 187/342] Fix TODOs in docs --- docs/source/conf.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4b7dc1737..4371b79f1 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -70,12 +70,12 @@ if os.getenv("READTHEDOCS"): if rtds_version == "latest": release = yosys_ver + "-dev" todo_include_todos = False - elif rtds_version.startswith("yosys-"): - release = yosys_ver - todo_include_todos = False - else: + elif rtds_version.startswith("docs"): release = rtds_version todo_include_todos = True + else: + release = yosys_ver + todo_include_todos = False else: release = yosys_ver todo_include_todos = True From 8b29629ca9873e7caff091223170e33014598aed Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 09:05:44 +1200 Subject: [PATCH 188/342] smtr: Fork smtlib for rosette --- backends/functional/Makefile.inc | 1 + backends/functional/smtlib_rosette.cc | 303 ++++++++++++++++++++++++++ 2 files changed, 304 insertions(+) create mode 100644 backends/functional/smtlib_rosette.cc diff --git a/backends/functional/Makefile.inc b/backends/functional/Makefile.inc index 13c962c99..16d1c0542 100644 --- a/backends/functional/Makefile.inc +++ b/backends/functional/Makefile.inc @@ -1,3 +1,4 @@ OBJS += backends/functional/cxx.o OBJS += backends/functional/smtlib.o +OBJS += backends/functional/smtlib_rosette.o OBJS += backends/functional/test_generic.o diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc new file mode 100644 index 000000000..601f311af --- /dev/null +++ b/backends/functional/smtlib_rosette.cc @@ -0,0 +1,303 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Emily Schmidt + * Copyright (C) 2024 National Technology and Engineering Solutions of Sandia, LLC + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/functional.h" +#include "kernel/yosys.h" +#include "kernel/sexpr.h" +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +using SExprUtil::list; + +const char *reserved_keywords[] = { + // reserved keywords from the racket spec + "struct", "lambda", "values", "extract", "concat", "bv", "let", "define", "cons", "list", "read", "write", + "stream", "error", "raise", "exit", "for", "for/list", "begin", "when", "unless", "module", "require", + "provide", "apply", "if", "cond", "even", "odd", "any", "and", "or", "match", "match-define", "values", + + // reserved for our own purposes + "inputs", "state", "name", + nullptr +}; + +struct SmtrScope : public Functional::Scope { + SmtrScope() { + for(const char **p = reserved_keywords; *p != nullptr; p++) + reserve(*p); + } + bool is_character_legal(char c, int index) override { + return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c)); + } +}; + +struct SmtrSort { + Functional::Sort sort; + SmtrSort(Functional::Sort sort) : sort(sort) {} + SExpr to_sexpr() const { + if(sort.is_memory()) { + return list("list", list("bitvector", sort.addr_width()), list("bitvector", sort.data_width())); + } else if(sort.is_signal()) { + return list("bitvector", sort.width()); + } else { + log_error("unknown sort"); + } + } +}; + +class SmtrStruct { + struct Field { + SmtrSort sort; + std::string accessor; + std::string name; + }; + idict field_names; + vector fields; + SmtrScope &scope; +public: + std::string name; + SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {} + void insert(IdString field_name, SmtrSort sort) { + field_names(field_name); + auto base_name = RTLIL::unescape_id(field_name); + auto accessor = name + "-" + base_name; + scope.reserve(accessor); + fields.emplace_back(Field{sort, accessor, base_name}); + } + void write_definition(SExprWriter &w) { + vector field_list; + for(const auto &field : fields) { + field_list.emplace_back(field.name); + } + w.push(); + w.open(list("struct", name, field_list, "#:transparent")); + if (field_names.size()) { + for (const auto &field : fields) { + auto bv_type = field.sort.to_sexpr(); + w.comment(field.name + " " + bv_type.to_string()); + } + } + w.pop(); + } + template void write_value(SExprWriter &w, Fn fn) { + w.open(list(name)); + for(auto field_name : field_names) { + w << fn(field_name); + w.comment(RTLIL::unescape_id(field_name), true); + } + w.close(); + } + SExpr access(SExpr record, IdString name) { + size_t i = field_names.at(name); + return list(fields[i].accessor, std::move(record)); + } +}; + +std::string smt_const(RTLIL::Const const &c) { + std::string s = "#b"; + for(int i = c.size(); i-- > 0; ) + s += c[i] == State::S1 ? '1' : '0'; + return s; +} + +struct SmtrPrintVisitor : public Functional::AbstractVisitor { + using Node = Functional::Node; + std::function n; + SmtrStruct &input_struct; + SmtrStruct &state_struct; + + SmtrPrintVisitor(SmtrStruct &input_struct, SmtrStruct &state_struct) : input_struct(input_struct), state_struct(state_struct) {} + + SExpr from_bool(SExpr &&arg) { + return list("bool->bitvector", std::move(arg)); + } + SExpr to_bool(SExpr &&arg) { + return list("bitvector->bool", std::move(arg)); + } + SExpr to_list(SExpr &&arg) { + return list("bitvector->bits", std::move(arg)); + } + + SExpr buf(Node, Node a) override { return n(a); } + SExpr slice(Node, Node a, int offset, int out_width) override { return list("extract", offset + out_width - 1, offset, n(a)); } + SExpr zero_extend(Node, Node a, int out_width) override { return list("zero-extend", n(a), list("bitvector", out_width)); } + SExpr sign_extend(Node, Node a, int out_width) override { return list("sign-extend", n(a), list("bitvector", out_width)); } + SExpr concat(Node, Node a, Node b) override { return list("concat", n(b), n(a)); } + SExpr add(Node, Node a, Node b) override { return list("bvadd", n(a), n(b)); } + SExpr sub(Node, Node a, Node b) override { return list("bvsub", n(a), n(b)); } + SExpr mul(Node, Node a, Node b) override { return list("bvmul", n(a), n(b)); } + SExpr unsigned_div(Node, Node a, Node b) override { return list("bvudiv", n(a), n(b)); } + SExpr unsigned_mod(Node, Node a, Node b) override { return list("bvurem", n(a), n(b)); } + SExpr bitwise_and(Node, Node a, Node b) override { return list("bvand", n(a), n(b)); } + SExpr bitwise_or(Node, Node a, Node b) override { return list("bvor", n(a), n(b)); } + SExpr bitwise_xor(Node, Node a, Node b) override { return list("bvxor", n(a), n(b)); } + SExpr bitwise_not(Node, Node a) override { return list("bvnot", n(a)); } + SExpr unary_minus(Node, Node a) override { return list("bvneg", n(a)); } + SExpr reduce_and(Node, Node a) override { return list("apply", "bvand", to_list(n(a))); } + SExpr reduce_or(Node, Node a) override { return list("apply", "bvor", to_list(n(a))); } + SExpr reduce_xor(Node, Node a) override { return list("apply", "bvxor", to_list(n(a))); } + SExpr equal(Node, Node a, Node b) override { return from_bool(list("bveq", n(a), n(b))); } + SExpr not_equal(Node, Node a, Node b) override { return from_bool(list("not", list("bveq", n(a), n(b)))); } + SExpr signed_greater_than(Node, Node a, Node b) override { return from_bool(list("bvsgt", n(a), n(b))); } + SExpr signed_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvsge", n(a), n(b))); } + SExpr unsigned_greater_than(Node, Node a, Node b) override { return from_bool(list("bvugt", n(a), n(b))); } + SExpr unsigned_greater_equal(Node, Node a, Node b) override { return from_bool(list("bvuge", n(a), n(b))); } + + SExpr extend(SExpr &&a, int in_width, int out_width) { + if(in_width < out_width) + return list("zero-extend", std::move(a), list("bitvector", out_width)); + else + return std::move(a); + } + SExpr logical_shift_left(Node, Node a, Node b) override { return list("bvshl", n(a), extend(n(b), b.width(), a.width())); } + SExpr logical_shift_right(Node, Node a, Node b) override { return list("bvlshr", n(a), extend(n(b), b.width(), a.width())); } + SExpr arithmetic_shift_right(Node, Node a, Node b) override { return list("bvashr", n(a), extend(n(b), b.width(), a.width())); } + SExpr mux(Node, Node a, Node b, Node s) override { return list("if", to_bool(n(s)), n(b), n(a)); } + SExpr constant(Node, RTLIL::Const const& value) override { return list("bv", smt_const(value), value.size()); } + SExpr memory_read(Node, Node mem, Node addr) override { return list("list-ref-bv", n(mem), n(addr)); } + SExpr memory_write(Node, Node mem, Node addr, Node data) override { return list("list-set-bv", n(mem), n(addr), n(data)); } + + SExpr input(Node, IdString name, IdString kind) override { log_assert(kind == ID($input)); return input_struct.access("inputs", name); } + SExpr state(Node, IdString name, IdString kind) override { log_assert(kind == ID($state)); return state_struct.access("state", name); } +}; + +struct SmtrModule { + Functional::IR ir; + SmtrScope scope; + std::string name; + + SmtrStruct input_struct; + SmtrStruct output_struct; + SmtrStruct state_struct; + + SmtrModule(Module *module) + : ir(Functional::IR::from_module(module)) + , scope() + , name(scope.unique_name(module->name)) + , input_struct(scope.unique_name(module->name.str() + "_Inputs"), scope) + , output_struct(scope.unique_name(module->name.str() + "_Outputs"), scope) + , state_struct(scope.unique_name(module->name.str() + "_State"), scope) + { + scope.reserve(name + "_initial"); + for (auto input : ir.inputs()) + input_struct.insert(input->name, input->sort); + for (auto output : ir.outputs()) + output_struct.insert(output->name, output->sort); + for (auto state : ir.states()) + state_struct.insert(state->name, state->sort); + } + + void write(std::ostream &out) + { + SExprWriter w(out); + + input_struct.write_definition(w); + output_struct.write_definition(w); + state_struct.write_definition(w); + + w.push(); + w.open(list("define", list(name, "inputs", "state"))); + auto inlined = [&](Functional::Node n) { + return n.fn() == Functional::Fn::constant; + }; + SmtrPrintVisitor visitor(input_struct, state_struct); + auto node_to_sexpr = [&](Functional::Node n) -> SExpr { + if(inlined(n)) + return n.visit(visitor); + else + return scope(n.id(), n.name()); + }; + visitor.n = node_to_sexpr; + for(auto n : ir) + if(!inlined(n)) { + w.open(list("let", list(list(node_to_sexpr(n), n.visit(visitor)))), false); + w.comment(SmtrSort(n.sort()).to_sexpr().to_string(), true); + } + w.open(list("cons")); + output_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.output(name).value()); }); + state_struct.write_value(w, [&](IdString name) { return node_to_sexpr(ir.state(name).next_value()); }); + w.pop(); + + w.push(); + auto initial = name + "_initial"; + w.open(list("define", initial)); + w.open(list(state_struct.name)); + for (auto state : ir.states()) { + if (state->sort.is_signal()) + w << list("bv", smt_const(state->initial_value_signal()), state->sort.width()); + else if (state->sort.is_memory()) { + const auto &contents = state->initial_value_memory(); + w.open(list("list")); + for(int i = 0; i < 1<sort.addr_width(); i++) { + w << list("bv", smt_const(contents[i]), state->sort.data_width()); + } + w.close(); + } + } + w.pop(); + } +}; + +struct FunctionalSmtrBackend : public Backend { + FunctionalSmtrBackend() : Backend("functional_rosette", "Generate Rosette compatible Racket from Functional IR") {} + + void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_functional_rosette [options] [selection] [filename]\n"); + log("\n"); + log("Functional Rosette Backend.\n"); + log("\n"); + log(" -provides\n"); + log(" include 'provide' statement(s) for loading output as a module\n"); + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + auto provides = false; + + log_header(design, "Executing Functional Rosette Backend.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-provides") + provides = true; + else + break; + } + extra_args(f, filename, args, argidx); + + *f << "#lang rosette\n"; + if (provides) { + *f << "(provide (all-defined-out))\n"; + } + + for (auto module : design->selected_modules()) { + log("Processing module `%s`.\n", module->name.c_str()); + SmtrModule smtr(module); + smtr.write(*f); + } + } +} FunctionalSmtrBackend; + +PRIVATE_NAMESPACE_END From 7fe9157df2f38c871cdb912cd2150ea701574358 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 23 Aug 2024 09:05:44 +1200 Subject: [PATCH 189/342] smtr: Add rkt to functional tests --- tests/functional/.gitignore | 1 + tests/functional/rkt_vcd.py | 115 ++++++++++++++++++++++++++++ tests/functional/test_functional.py | 13 ++++ 3 files changed, 129 insertions(+) create mode 100644 tests/functional/rkt_vcd.py diff --git a/tests/functional/.gitignore b/tests/functional/.gitignore index 1ffe9926e..f0c4cf14e 100644 --- a/tests/functional/.gitignore +++ b/tests/functional/.gitignore @@ -3,3 +3,4 @@ my_module_functional_cxx.cc vcd_harness *.vcd *.smt2 +*.rkt diff --git a/tests/functional/rkt_vcd.py b/tests/functional/rkt_vcd.py new file mode 100644 index 000000000..1b2cf31e3 --- /dev/null +++ b/tests/functional/rkt_vcd.py @@ -0,0 +1,115 @@ +from __future__ import annotations +from pathlib import Path +import re +import subprocess +from typing import Dict, List, Tuple +from random import Random + +vcd_version = "Yosys/tests/functional/rkt_vcd.py" +StepList = List[Tuple[int, str]] +SignalStepMap = Dict[str, StepList] +SignalWidthMap = Dict[str, int] + +def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='today'): + with open(filename, 'w') as f: + # Write the header + f.write(f"$date\n {date}\n$end\n") + f.write(f"$timescale {timescale} $end\n") + + # Declare signals + f.write("$scope module gold $end\n") + for signal_name, changes in signals.items(): + signal_size = len(changes[0][1]) + f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") + f.write("$upscope $end\n") + f.write("$enddefinitions $end\n") + + # Collect all unique timestamps + timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) + + # Write initial values + f.write("#0\n") + for signal_name, changes in signals.items(): + for time, value in changes: + if time == 0: + f.write(f"{value} {signal_name}\n") + + # Write value changes + for time in timestamps: + if time != 0: + f.write(f"#{time}\n") + for signal_name, changes in signals.items(): + for change_time, value in changes: + if change_time == time: + f.write(f"{value} {signal_name}\n") + +def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random): + signals: dict[str, list[str]] = {} + inputs: SignalWidthMap = {} + outputs: SignalWidthMap = {} + + current_struct_name: str = "" + with open(rkt_file_path, 'r') as rkt_file: + for line in rkt_file: + m = re.search(r'gold_(Inputs|Outputs|State)', line) + if m: + current_struct_name = m.group(1) + if current_struct_name == "State": break + elif not current_struct_name: continue # skip lines before structs + m = re.search(r'; (.+?)\b \(bitvector (\d+)\)', line) + if not m: continue # skip non matching lines (probably closing the struct) + signal = m.group(1) + width = int(m.group(2)) + if current_struct_name == "Inputs": + inputs[signal] = width + elif current_struct_name == "Outputs": + outputs[signal] = width + + for signal, width in inputs.items(): + step_list: list[int] = [] + for step in range(num_steps): + value = rnd.getrandbits(width) + binary_string = format(value, '0{}b'.format(width)) + step_list.append(binary_string) + signals[signal] = step_list + + test_rkt_file_path = rkt_file_path.with_suffix('.tst.rkt') + with open(test_rkt_file_path, 'w') as test_rkt_file: + test_rkt_file.writelines([ + '#lang rosette\n', + f'(require "{rkt_file_path.name}")\n', + ]) + + for step in range(num_steps): + this_step = f"step_{step}" + value_list: list[str] = [] + for signal, width in inputs.items(): + value = signals[signal][step] + value_list.append(f"(bv #b{value} {width})") + gold_Inputs = f"(gold_Inputs {' '.join(value_list)})" + gold_State = f"(cdr step_{step-1})" if step else "gold_initial" + test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n") + + cmd = ["racket", test_rkt_file_path] + status = subprocess.run(cmd, capture_output=True) + assert status.returncode == 0, f"{cmd[0]} failed" + + for signal in outputs.keys(): + signals[signal] = [] + + for line in status.stdout.decode().splitlines(): + m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line) + assert m, f"Incomplete output definition {line!r}" + for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)): + assert isinstance(value, str), f"Bad value {value!r}" + assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}" + assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})" + int_value = int(value[2:], 16 if value.startswith('#x') else 2) + binary_string = format(int_value, '0{}b'.format(width)) + signals[output].append(binary_string) + + vcd_signals: SignalStepMap = {} + for signal, steps in signals.items(): + vcd_signals[signal] = [(time, f"b{value}") for time, value in enumerate(steps)] + + write_vcd(vcd_path, vcd_signals) diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 55e4acc33..3b006676a 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -72,6 +72,19 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) +def test_rkt(cell, parameters, tmp_path, num_steps, rnd): + import rkt_vcd + + rtlil_file = tmp_path / 'rtlil.il' + rkt_file = tmp_path / 'smtlib.rkt' + vcd_functional_file = tmp_path / 'functional.vcd' + vcd_yosys_sim_file = tmp_path / 'yosys.vcd' + + cell.write_rtlil_file(rtlil_file, parameters) + yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}") + rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt")) + yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) + def test_print_graph(tmp_path): tb_file = base_path / 'tests/functional/picorv32_tb.v' cpu_file = base_path / 'tests/functional/picorv32.v' From 07b69080191c2112e817334d313e5e6d944d3a66 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 30 Aug 2024 09:56:08 +1200 Subject: [PATCH 190/342] smtr: Use rosette/safe --- backends/functional/smtlib_rosette.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index 601f311af..f23953747 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -287,7 +287,7 @@ struct FunctionalSmtrBackend : public Backend { } extra_args(f, filename, args, argidx); - *f << "#lang rosette\n"; + *f << "#lang rosette/safe\n"; if (provides) { *f << "(provide (all-defined-out))\n"; } From 5a29b3e1724e45b6d7afe30f3ebb3e7546f8845e Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 30 Aug 2024 10:44:35 +1200 Subject: [PATCH 191/342] smtr: More sanitization --- backends/functional/smtlib_rosette.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index f23953747..4e6057694 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -31,8 +31,12 @@ using SExprUtil::list; const char *reserved_keywords[] = { // reserved keywords from the racket spec "struct", "lambda", "values", "extract", "concat", "bv", "let", "define", "cons", "list", "read", "write", - "stream", "error", "raise", "exit", "for", "for/list", "begin", "when", "unless", "module", "require", - "provide", "apply", "if", "cond", "even", "odd", "any", "and", "or", "match", "match-define", "values", + "stream", "error", "raise", "exit", "for", "begin", "when", "unless", "module", "require", "provide", "apply", + "if", "cond", "even", "odd", "any", "and", "or", "match", "command-line", "ffi-lib", "thread", "kill", "sync", + "future", "touch", "subprocess", "make-custodian", "custodian-shutdown-all", "current-custodian", "make", "tcp", + "connect", "prepare", "malloc", "free", "_fun", "_cprocedure", "build", "path", "file", "peek", "bytes", + "flush", "with", "lexer", "parser", "syntax", "interface", "send", "make-object", "new", "instantiate", + "define-generics", "set", // reserved for our own purposes "inputs", "state", "name", @@ -45,7 +49,7 @@ struct SmtrScope : public Functional::Scope { reserve(*p); } bool is_character_legal(char c, int index) override { - return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("~!@$%^&*_-+=<>.?/", c)); + return isascii(c) && (isalpha(c) || (isdigit(c) && index > 0) || strchr("@$%^&_+=.", c)); } }; From a2abbcb33f3ae1c2287b4b2a3b9e419494ab8aa0 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 22:05:17 +1200 Subject: [PATCH 192/342] smtr: Use scope.unique_name --- backends/functional/smtlib_rosette.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index 4e6057694..ff47f5706 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -81,7 +81,7 @@ public: SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {} void insert(IdString field_name, SmtrSort sort) { field_names(field_name); - auto base_name = RTLIL::unescape_id(field_name); + auto base_name = scope.unique_name("\\" + RTLIL::unescape_id(field_name)); auto accessor = name + "-" + base_name; scope.reserve(accessor); fields.emplace_back(Field{sort, accessor, base_name}); From d6c5e13bf31043173adf5667b7edc7d9940293db Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 3 Sep 2024 22:23:41 +1200 Subject: [PATCH 193/342] smtr: Structs have local scope Also unique_name can take field_name directly. --- backends/functional/smtlib_rosette.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index ff47f5706..ea14da854 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -75,15 +75,16 @@ class SmtrStruct { }; idict field_names; vector fields; - SmtrScope &scope; + SmtrScope &global_scope; + SmtrScope local_scope; public: std::string name; - SmtrStruct(std::string name, SmtrScope &scope) : scope(scope), name(name) {} + SmtrStruct(std::string name, SmtrScope &scope) : global_scope(scope), local_scope(), name(name) {} void insert(IdString field_name, SmtrSort sort) { field_names(field_name); - auto base_name = scope.unique_name("\\" + RTLIL::unescape_id(field_name)); + auto base_name = local_scope.unique_name(field_name); auto accessor = name + "-" + base_name; - scope.reserve(accessor); + global_scope.reserve(accessor); fields.emplace_back(Field{sort, accessor, base_name}); } void write_definition(SExprWriter &w) { From 0744fac883232fda4106a09100abf6f88eab1220 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 3 Sep 2024 12:39:38 +0200 Subject: [PATCH 194/342] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 855d6f597..03bf5ac57 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.45 .. Yosys 0.46-dev +-------------------------- + Yosys 0.44 .. Yosys 0.45 -------------------------- * Various diff --git a/Makefile b/Makefile index fc2955f1d..61dc51bd5 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45 +YOSYS_VER := 0.45+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -169,7 +169,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From 75ed6d38fc20f490d0b8adcacf6bd26c5e1a8613 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 3 Sep 2024 14:21:56 +0100 Subject: [PATCH 195/342] fix rst formatting in functional_ir.rst --- .../extending_yosys/functional_ir.rst | 111 ++++++++++-------- 1 file changed, 59 insertions(+), 52 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst index 38d000556..29aaf398c 100644 --- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -3,7 +3,7 @@ Writing a new backend using FunctionalIR To simplify the writing of backends for functional languages or similar targets, Yosys provides an alternative intermediate representation called FunctionalIR which maps more directly on those targets. -FunctionalIR represents the design as a function `(inputs, current_state) -> (outputs, next_state)`. +FunctionalIR represents the design as a function ``(inputs, current_state) -> (outputs, next_state)``. This function is broken down into a series of assignments to variables. Each assignment is a simple operation, such as an addition. Complex operations are broken up into multiple steps. @@ -14,72 +14,79 @@ We can thus treat variables and assignments as equivalent and, since this is a g Unlike RTLIL's cells and wires representation, this representation is strictly ordered (topologically sorted) with definitions preceding their use. Every node has a "sort" (the FunctionalIR term for what might otherwise be called a "type"). The sorts available are -- `bit[n]` for an `n`-bit bitvector, and -- `memory[n,m]` for an immutable array of `2**n` values of sort `bit[m]`. -In terms of actual code, Yosys provides a class `Functional::IR` that represents a design in FunctionalIR. -`Functional::IR::from_module` generates an instance from an RTLIL module. +- ``bit[n]`` for an ``n``-bit bitvector, and +- ``memory[n,m]`` for an immutable array of ``2**n`` values of sort ``bit[m]``. + +In terms of actual code, Yosys provides a class ``Functional::IR`` that represents a design in FunctionalIR. +``Functional::IR::from_module`` generates an instance from an RTLIL module. The entire design is stored as a whole in an internal data structure. -To access the design, the `Functional::Node` class provides a reference to a particular node in the design. -The `Functional::IR` class supports the syntax `for(auto node : ir)` to iterate over every node. +To access the design, the ``Functional::Node`` class provides a reference to a particular node in the design. +The ``Functional::IR`` class supports the syntax ``for(auto node : ir)`` to iterate over every node. -`Functional::IR` also keeps track of inputs, outputs and states. +``Functional::IR`` also keeps track of inputs, outputs and states. By a "state" we mean a pair of a "current state" input and a "next state" output. One such pair is created for every register and for every memory. Every input, output and state has a name (equal to their name in RTLIL), a sort and a kind. -The kind field usually remains as the default value `$input`, `$output` or `$state`, however some RTLIL cells such as `$assert` or `$anyseq` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states. -- To access an individual input/output/state, use `ir.input(name, kind)`, `ir.output(name, kind)` or `ir.state(name, kind)`. `kind` defaults to the default kind. -- To iterate over all inputs/outputs/states of a certain kind, methods `ir.inputs`, `ir.outputs`, `ir.states` are provided. Their argument defaults to the default kinds mentioned. -- To iterate over inputs/outputs/states of any kind, use `ir.all_inputs`, `ir.all_outputs` and `ir.all_states`. -- Outputs have a node that indicate the value of the output, this can be retrieved via `output.value()`. -- States have a node that indicate the next value of the state, this can be retrieved via `state.next_value()`. - They also have an initial value that is accessed as either `state.initial_value_signal()` or `state.initial_value_memory()`, depending on their sort. +The kind field usually remains as the default value ``$input``, ``$output`` or ``$state``, however some RTLIL cells such as ``$assert`` or ``$anyseq`` generate auxiliary inputs/outputs/states that are given a different kind to distinguish them from ordinary RTLIL inputs/outputs/states. -Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see `functional.h`). -Functions are represented as an enum `Functional::Fn` and the function field can be accessed as `node.fn()`. -Since the most common operation is a switch over the function that also accesses the arguments, the `Node` class provides a method `visit` that implements the visitor pattern. -For example, for an addition node `node` with arguments `n1` and `n2`, `node.visit(visitor)` would call `visitor.add(node, n1, n2)`. +- To access an individual input/output/state, use ``ir.input(name, kind)``, ``ir.output(name, kind)`` or ``ir.state(name, kind)``. ``kind`` defaults to the default kind. +- To iterate over all inputs/outputs/states of a certain kind, methods ``ir.inputs``, ``ir.outputs``, ``ir.states`` are provided. Their argument defaults to the default kinds mentioned. +- To iterate over inputs/outputs/states of any kind, use ``ir.all_inputs``, ``ir.all_outputs`` and ``ir.all_states``. +- Outputs have a node that indicate the value of the output, this can be retrieved via ``output.value()``. +- States have a node that indicate the next value of the state, this can be retrieved via ``state.next_value()``. + They also have an initial value that is accessed as either ``state.initial_value_signal()`` or ``state.initial_value_memory()``, depending on their sort. + +Each node has a "function", which defines its operation (for a complete list of functions and a specification of their operation, see ``functional.h``). +Functions are represented as an enum ``Functional::Fn`` and the function field can be accessed as ``node.fn()``. +Since the most common operation is a switch over the function that also accesses the arguments, the ``Node`` class provides a method ``visit`` that implements the visitor pattern. +For example, for an addition node ``node`` with arguments ``n1`` and ``n2``, ``node.visit(visitor)`` would call ``visitor.add(node, n1, n2)``. Thus typically one would implement a class with a method for every function. -Visitors should inherit from either `Functional::AbstractVisitor` or `Functional::DefaultVisitor`. -The former will produce a compiler error if a case is unhandled, the latter will call `default_handler(node)` instead. -Visitor methods should be marked as `override` to provide compiler errors if the arguments are wrong. +Visitors should inherit from either ``Functional::AbstractVisitor`` or ``Functional::DefaultVisitor``. +The former will produce a compiler error if a case is unhandled, the latter will call ``default_handler(node)`` instead. +Visitor methods should be marked as ``override`` to provide compiler errors if the arguments are wrong. Utility classes ----------------- -`functional.h` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends. +``functional.h`` also provides utility classes that are independent of the main FunctionalIR representation but are likely to be useful for backends. -`Functional::Writer` provides a simple formatting class that wraps a `std::ostream` and provides the following methods: -- `writer << value` wraps `os << value`. -- `writer.print(fmt, value0, value1, value2, ...)` replaces `{0}`, `{1}`, `{2}`, etc in the string `fmt` with `value0`, `value1`, `value2`, resp. - Each value is formatted using `os << value`. - It is also possible to write `{}` to refer to one past the last index, i.e. `{1} {} {} {7} {}` is equivalent to `{1} {2} {3} {7} {8}`. -- `writer.print_with(fn, fmt, value0, value1, value2, ...)` functions much the same as `print` but it uses `os << fn(value)` to print each value and falls back to `os << value` if `fn(value)` is not legal. +``Functional::Writer`` provides a simple formatting class that wraps a ``std::ostream`` and provides the following methods: -`Functional::Scope` keeps track of variable names in a target language. +- ``writer << value`` wraps ``os << value``. +- ``writer.print(fmt, value0, value1, value2, ...)`` replaces ``{0}``, ``{1}``, ``{2}``, etc in the string ``fmt`` with ``value0``, ``value1``, ``value2``, resp. + Each value is formatted using ``os << value``. + It is also possible to write ``{}`` to refer to one past the last index, i.e. ``{1} {} {} {7} {}`` is equivalent to ``{1} {2} {3} {7} {8}``. +- ``writer.print_with(fn, fmt, value0, value1, value2, ...)`` functions much the same as ``print`` but it uses ``os << fn(value)`` to print each value and falls back to ``os << value`` if ``fn(value)`` is not legal. + +``Functional::Scope`` keeps track of variable names in a target language. It is used to translate between different sets of legal characters and to avoid accidentally re-defining identifiers. -Users should derive a class from `Scope` and supply the following: -- `Scope` takes a template argument that specifies a type that's used to uniquely distinguish variables. - Typically this would be `int` (if variables are used for `Functional::IR` nodes) or `IdString`. -- The derived class should provide a constructor that calls `reserve` for every reserved word in the target language. -- A method `bool is_legal_character(char c, int index)` has to be provided that returns `true` iff `c` is legal in an identifier at position `index`. -Given an instance `scope` of the derived class, the following methods are then available: -- `scope.reserve(std::string name)` marks the given name as being in-use -- `scope.unique_name(IdString suggestion)` generates a previously unused name and attempts to make it similar to `suggestion`. -- `scope(Id id, IdString suggestion)` functions similar to `unique_name`, except that multiple calls with the same `id` are guaranteed to retrieve the same name (independent of `suggestion`). +Users should derive a class from ``Scope`` and supply the following: -`sexpr.h` provides classes that represent and pretty-print s-expressions. -S-expressions can be constructed with `SExpr::list`, for example `SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))` represents `(add x (mul y z))` -(by adding `using SExprUtil::list` to the top of the file, `list` can be used as shorthand for `SExpr::list`). -For prettyprinting, `SExprWriter` wraps an `std::ostream` and provides the following methods: -- `writer << sexpr` writes the provided expression to the output, breaking long lines and adding appropriate indentation. -- `writer.open(sexpr)` is similar to `writer << sexpr` but will omit the last closing parenthesis. - Further arguments can then be added separately with `<<` or `open`. +- ``Scope`` takes a template argument that specifies a type that's used to uniquely distinguish variables. + Typically this would be ``int`` (if variables are used for ``Functional::IR`` nodes) or ``IdString``. +- The derived class should provide a constructor that calls ``reserve`` for every reserved word in the target language. +- A method ``bool is_legal_character(char c, int index)`` has to be provided that returns ``true`` iff ``c`` is legal in an identifier at position ``index``. + +Given an instance ``scope`` of the derived class, the following methods are then available: + +- ``scope.reserve(std::string name)`` marks the given name as being in-use +- ``scope.unique_name(IdString suggestion)`` generates a previously unused name and attempts to make it similar to ``suggestion``. +- ``scope(Id id, IdString suggestion)`` functions similar to ``unique_name``, except that multiple calls with the same ``id`` are guaranteed to retrieve the same name (independent of ``suggestion``). + +``sexpr.h`` provides classes that represent and pretty-print s-expressions. +S-expressions can be constructed with ``SExpr::list``, for example ``SExpr expr = SExpr::list("add", "x", SExpr::list("mul", "y", "z"))`` represents ``(add x (mul y z))`` +(by adding ``using SExprUtil::list`` to the top of the file, ``list`` can be used as shorthand for ``SExpr::list``). +For prettyprinting, ``SExprWriter`` wraps an ``std::ostream`` and provides the following methods: + +- ``writer << sexpr`` writes the provided expression to the output, breaking long lines and adding appropriate indentation. +- ``writer.open(sexpr)`` is similar to ``writer << sexpr`` but will omit the last closing parenthesis. + Further arguments can then be added separately with ``<<`` or ``open``. This allows for printing large s-expressions without needing the construct the whole expression in memory first. -- `writer.open(sexpr, false)` is similar to `writer.open(sexpr)` but further arguments will not be indented. +- ``writer.open(sexpr, false)`` is similar to ``writer.open(sexpr)`` but further arguments will not be indented. This is used to avoid unlimited indentation on structures with unlimited nesting. -- `writer.close(n = 1)` closes the last `n` open s-expressions. -- `writer.push()` and `writer.pop()` are used to automatically close s-expressions. - `writer.pop()` closes all s-expressions opened since the last call to `writer.push()`. -- `writer.comment(string)` writes a comment on a separate-line. - `writer.comment(string, true)` appends a comment to the last printed s-expression. \ No newline at end of file +- ``writer.close(n = 1)`` closes the last ``n`` open s-expressions. +- ``writer.push()`` and ``writer.pop()`` are used to automatically close s-expressions. + ``writer.pop()`` closes all s-expressions opened since the last call to ``writer.push()``. +- ``writer.comment(string)`` writes a comment on a separate-line. + ``writer.comment(string, true)`` appends a comment to the last printed s-expression. \ No newline at end of file From 7de8be14516bc059d2029859b7a5469a322548e7 Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Tue, 3 Sep 2024 14:30:56 +0100 Subject: [PATCH 196/342] functional_ir.rst: fix typo, document SExprWriter::flush --- .../yosys_internals/extending_yosys/functional_ir.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/functional_ir.rst b/docs/source/yosys_internals/extending_yosys/functional_ir.rst index 29aaf398c..a763e0508 100644 --- a/docs/source/yosys_internals/extending_yosys/functional_ir.rst +++ b/docs/source/yosys_internals/extending_yosys/functional_ir.rst @@ -82,11 +82,13 @@ For prettyprinting, ``SExprWriter`` wraps an ``std::ostream`` and provides the f - ``writer << sexpr`` writes the provided expression to the output, breaking long lines and adding appropriate indentation. - ``writer.open(sexpr)`` is similar to ``writer << sexpr`` but will omit the last closing parenthesis. Further arguments can then be added separately with ``<<`` or ``open``. - This allows for printing large s-expressions without needing the construct the whole expression in memory first. + This allows for printing large s-expressions without needing to construct the whole expression in memory first. - ``writer.open(sexpr, false)`` is similar to ``writer.open(sexpr)`` but further arguments will not be indented. This is used to avoid unlimited indentation on structures with unlimited nesting. - ``writer.close(n = 1)`` closes the last ``n`` open s-expressions. - ``writer.push()`` and ``writer.pop()`` are used to automatically close s-expressions. ``writer.pop()`` closes all s-expressions opened since the last call to ``writer.push()``. - ``writer.comment(string)`` writes a comment on a separate-line. - ``writer.comment(string, true)`` appends a comment to the last printed s-expression. \ No newline at end of file + ``writer.comment(string, true)`` appends a comment to the last printed s-expression. +- ``writer.flush()`` flushes any buffering and should be called before any direct access to the underlying ``std::ostream``. It does not close unclosed parentheses. +- The destructor calls ``flush`` but also closes all unclosed parentheses. From 0ce7631956bf293524bbfc6f3356f5a8f722a219 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 3 Sep 2024 19:28:24 +0200 Subject: [PATCH 197/342] internal_stats: init, report current memory consumption on linux and mac --- passes/cmds/Makefile.inc | 1 + passes/cmds/internal_stats.cc | 120 ++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+) create mode 100644 passes/cmds/internal_stats.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 33e3ae1bc..f208e3e06 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -16,6 +16,7 @@ OBJS += passes/cmds/setundef.o OBJS += passes/cmds/splitnets.o OBJS += passes/cmds/splitcells.o OBJS += passes/cmds/stat.o +OBJS += passes/cmds/internal_stats.o OBJS += passes/cmds/setattr.o OBJS += passes/cmds/copy.o OBJS += passes/cmds/splice.o diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc new file mode 100644 index 000000000..fe27bee5e --- /dev/null +++ b/passes/cmds/internal_stats.cc @@ -0,0 +1,120 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include "kernel/yosys.h" +#include "kernel/celltypes.h" +#include "passes/techmap/libparse.h" +#include "kernel/cost.h" +#include "libs/json11/json11.hpp" + +#if defined(__APPLE__) && defined(__MACH__) +#include +#include +#endif + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +std::optional current_mem_bytes() { + +#if defined(__APPLE__) + task_basic_info_64_data_t basicInfo; + mach_msg_type_number_t count = TASK_BASIC_INFO_64_COUNT; + kern_return_t error = task_info(mach_task_self(), TASK_BASIC_INFO_64, (task_info_t)&basicInfo, &count); + if (error != KERN_SUCCESS) { + return {}; // Error getting task information + } + return basicInfo.resident_size; // Return RSS in KB + +#elif defined(__linux__) + // Not all linux distributions have to have this file + std::ifstream statusFile("/proc/self/status"); + std::string line; + while (std::getline(statusFile, line)) { + if (line.find("VmRSS:") == 0) { + std::istringstream iss(line); + std::string token; + // Skip prefix + iss >> token; + uint64_t rss; + iss >> rss; + return rss * 1024; + } + } + // Error reading /proc/self/status + return {}; + +#else + return {}; +#endif +} + +struct InternalStatsPass : public Pass { + InternalStatsPass() : Pass("internal_stats", "print some internal statistics") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); // TODO + } + void execute(std::vector args, RTLIL::Design *design) override + { + bool json_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-json") { + json_mode = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if(!json_mode) + log_header(design, "Printing internal statistics.\n"); + + log_experimental("internal_stats"); + + if (json_mode) { + log("{\n"); + log(" \"creator\": %s,\n", json11::Json(yosys_version_str).dump().c_str()); + std::stringstream invocation; + std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " ")); + log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str()); + if (auto mem = current_mem_bytes()) { + log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str()); + } + } + + // stats go here + + if (json_mode) { + log("\n"); + log("}\n"); + } + + } +} InternalStatsPass; + +PRIVATE_NAMESPACE_END From d56716417336a085afec954f8ecc24722721b98b Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 4 Sep 2024 00:19:13 +0000 Subject: [PATCH 198/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 61dc51bd5..7c52d984e 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+0 +YOSYS_VER := 0.45+3 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 5a476a8d29c541d421d409a48a81f642de30b80e Mon Sep 17 00:00:00 2001 From: Emily Schmidt Date: Wed, 4 Sep 2024 10:30:08 +0100 Subject: [PATCH 199/342] functional tests: run from make tests but not smtlib/rkt tests --- Makefile | 1 + tests/functional/conftest.py | 6 +++++- tests/functional/run-test.sh | 2 +- tests/functional/test_functional.py | 2 ++ 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index fbe099042..2a4f4f587 100644 --- a/Makefile +++ b/Makefile @@ -891,6 +891,7 @@ endif +cd tests/xprop && bash run-test.sh $(SEEDOPT) +cd tests/fmt && bash run-test.sh +cd tests/cxxrtl && bash run-test.sh + +cd tests/functional && bash run-test.sh @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/functional/conftest.py b/tests/functional/conftest.py index 12db7f1d0..a9fbb3c59 100644 --- a/tests/functional/conftest.py +++ b/tests/functional/conftest.py @@ -4,6 +4,10 @@ import random random_seed = random.getrandbits(32) +def pytest_configure(config): + config.addinivalue_line("markers", "smt: test uses smtlib/z3") + config.addinivalue_line("markers", "rkt: test uses racket/rosette") + def pytest_addoption(parser): parser.addoption("--per-cell", type=int, default=None, help="run only N tests per cell") parser.addoption("--steps", type=int, default=1000, help="run each test for N steps") @@ -27,4 +31,4 @@ def pytest_generate_tests(metafunc): seed1 = metafunc.config.getoption("seed") rnd = lambda seed2: random.Random('{}-{}'.format(seed1, seed2)) names, cases = generate_test_cases(per_cell, rnd) - metafunc.parametrize("cell,parameters", cases, ids=names) \ No newline at end of file + metafunc.parametrize("cell,parameters", cases, ids=names) diff --git a/tests/functional/run-test.sh b/tests/functional/run-test.sh index b9a0595f6..9f70462ee 100755 --- a/tests/functional/run-test.sh +++ b/tests/functional/run-test.sh @@ -1,2 +1,2 @@ #!/usr/bin/env bash -pytest -v "$@" +pytest -v -m "not smt and not rkt" "$@" diff --git a/tests/functional/test_functional.py b/tests/functional/test_functional.py index 3b006676a..7a09966d8 100644 --- a/tests/functional/test_functional.py +++ b/tests/functional/test_functional.py @@ -55,6 +55,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd): run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)]) yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) +@pytest.mark.smt def test_smt(cell, parameters, tmp_path, num_steps, rnd): import smt_vcd @@ -72,6 +73,7 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd): smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt")) yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', '')) +@pytest.mark.rkt def test_rkt(cell, parameters, tmp_path, num_steps, rnd): import rkt_vcd From 21494d1f06457c2ec99669c06bf42c8bf9ee92d5 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 5 Sep 2024 11:43:31 +1200 Subject: [PATCH 200/342] Makefile: Update coverage_functional Note sure if this is the best way to do it, but it works? --- Makefile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 2a4f4f587..f377072fb 100644 --- a/Makefile +++ b/Makefile @@ -1052,11 +1052,12 @@ coverage: clean_coverage: find . -name "*.gcda" -type f -delete +FUNC_KERNEL := functional.cc functional.h sexpr.cc sexpr.h compute_graph.h +FUNC_INCLUDES := $(addprefix --include *,functional/* $(FUNC_KERNEL)) coverage_functional: - rm -rf coverage.info coverage2.info coverage_html - lcov --capture -d backends/functional --no-external -o coverage.info - lcov --capture -d kernel --include kernel/functional.cc --include kernel/functional.h --include kernel/sexpr.cc --include kernel/sexpr.h --include kernel/compute_graph.h --no-external -o coverage2.info - genhtml coverage.info coverage2.info --output-directory coverage_html + rm -rf coverage.info coverage_html + lcov --capture -d backends/functional -d kernel $(FUNC_INCLUDES) --no-external -o coverage.info + genhtml coverage.info --output-directory coverage_html qtcreator: echo "$(CXXFLAGS)" | grep -o '\-D[^ ]*' | tr ' ' '\n' | sed 's/-D/#define /' | sed 's/=/ /'> qtcreator.config From 17ee367c7bc3421a180a2043b014f36ec24ba08c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 5 Sep 2024 15:46:49 +1200 Subject: [PATCH 201/342] Docs: Use Read the Docs SPHINXOPTS `-W --keep-going` will build everything but raise an error on any warnings. Should mean that github actions will correctly flag a failure when attempting to build docs. Including this current commit until the `internal_stats` command gets a help message. --- docs/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Makefile b/docs/Makefile index 8be970391..21fcd9623 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -2,7 +2,7 @@ # # You can set these variables from the command line. -SPHINXOPTS = +SPHINXOPTS = -W --keep-going SPHINXBUILD = sphinx-build PAPER = BUILDDIR = build From bd6f7bb4a77096b5fbdedeb4376c0aee7c49aac2 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 5 Sep 2024 11:17:12 +0200 Subject: [PATCH 202/342] ff: improve comments --- kernel/ff.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/ff.h b/kernel/ff.h index e684d3c43..d6cf99b9b 100644 --- a/kernel/ff.h +++ b/kernel/ff.h @@ -131,9 +131,11 @@ struct FfData { bool is_fine; // True if this FF is an $anyinit cell. Depends on has_gclk. bool is_anyinit; - // Polarities, corresponding to sig_*. True means active-high, false - // means active-low. + // Polarities, corresponding to sig_*. + // True means rising edge, false means falling edge. bool pol_clk; + // True means active-high, false + // means active-low. bool pol_ce; bool pol_aload; bool pol_arst; From 14b91554920b8a99408631af37ef6338beae937c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 5 Sep 2024 11:22:21 +0200 Subject: [PATCH 203/342] internal_stats: fix doc build by adding a help string --- passes/cmds/internal_stats.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc index fe27bee5e..8cd62efb6 100644 --- a/passes/cmds/internal_stats.cc +++ b/passes/cmds/internal_stats.cc @@ -70,11 +70,11 @@ std::optional current_mem_bytes() { } struct InternalStatsPass : public Pass { - InternalStatsPass() : Pass("internal_stats", "print some internal statistics") { } + InternalStatsPass() : Pass("internal_stats", "print internal statistics") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); // TODO + log("Print internal statistics for developers (experimental)\n"); } void execute(std::vector args, RTLIL::Design *design) override { From e8951aba29faf774e475f20c1405162993235d7f Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 6 Sep 2024 00:19:21 +0000 Subject: [PATCH 204/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7c52d984e..e835d4814 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+3 +YOSYS_VER := 0.45+11 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From fc10a6eee2d12c18212fbe7ccabd6094408afd30 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 6 Sep 2024 08:47:43 +0200 Subject: [PATCH 205/342] Run functional tests on private runner only --- .github/workflows/test-verific.yml | 1 + Makefile | 3 +++ 2 files changed, 4 insertions(+) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 627a70d47..024f8cddc 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -41,6 +41,7 @@ jobs: echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf echo "ENABLE_CCACHE := 1" >> Makefile.conf + echo "ENABLE_FUNCTIONAL_TESTS := 1" >> Makefile.conf make -j${{ env.procs }} ENABLE_LTO=1 - name: Install Yosys diff --git a/Makefile b/Makefile index f377072fb..c3d572a36 100644 --- a/Makefile +++ b/Makefile @@ -38,6 +38,7 @@ ENABLE_LTO := 0 ENABLE_CCACHE := 0 # sccache is not always a drop-in replacement for ccache in practice ENABLE_SCCACHE := 0 +ENABLE_FUNCTIONAL_TESTS := 0 LINK_CURSES := 0 LINK_TERMCAP := 0 LINK_ABC := 0 @@ -891,7 +892,9 @@ endif +cd tests/xprop && bash run-test.sh $(SEEDOPT) +cd tests/fmt && bash run-test.sh +cd tests/cxxrtl && bash run-test.sh +ifeq ($(ENABLE_FUNCTIONAL_TESTS),1) +cd tests/functional && bash run-test.sh +endif @echo "" @echo " Passed \"make test\"." @echo "" From dcf9f583151cbeeabbc99e5f2c537090e3c1ee74 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 7 Sep 2024 00:18:42 +0000 Subject: [PATCH 206/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f702b940e..b841c2fa6 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+11 +YOSYS_VER := 0.45+106 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From c1205ebc4223928b5f8d1612fe421b48c235b7eb Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sat, 7 Sep 2024 21:30:58 -0700 Subject: [PATCH 207/342] Initialize area stats in stat pass Currently, the area variables in the stat struct are not initialized. This caused the area stats occasionally being an erroneous value. Signed-off-by: Hoa Nguyen --- passes/cmds/stat.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 951a321e8..608505ebf 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -44,8 +44,8 @@ struct statdata_t #define X(_name) unsigned int _name; STAT_INT_MEMBERS #undef X - double area; - double sequential_area; + double area = 0; + double sequential_area = 0; string tech; std::map techinfo; From e64fceef707c355005b5b8336fc54472c28992cd Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 9 Sep 2024 15:00:54 +0200 Subject: [PATCH 208/342] clockgate: prototype clock gating --- passes/techmap/Makefile.inc | 1 + passes/techmap/clockgate.cc | 229 ++++++++++++++++++++++++++++++++++++ tests/techmap/clockgate.ys | 88 ++++++++++++++ 3 files changed, 318 insertions(+) create mode 100644 passes/techmap/clockgate.cc create mode 100644 tests/techmap/clockgate.ys diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 74813bca9..0282af790 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -49,6 +49,7 @@ OBJS += passes/techmap/dffunmap.o OBJS += passes/techmap/flowmap.o OBJS += passes/techmap/extractinv.o OBJS += passes/techmap/cellmatch.o +OBJS += passes/techmap/clockgate.o endif ifeq ($(DISABLE_SPAWN),0) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc new file mode 100644 index 000000000..66f8c7d6c --- /dev/null +++ b/passes/techmap/clockgate.cc @@ -0,0 +1,229 @@ +#include "kernel/yosys.h" +#include "kernel/ff.h" +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ClockGateCell { + IdString name; + IdString ce_pin; + IdString clk_in_pin; + IdString clk_out_pin; +}; + +ClockGateCell icg_from_arg(std::string& name, std::string& str) { + ClockGateCell c; + c.name = RTLIL::escape_id(name); + char delimiter = ':'; + size_t pos1 = str.find(delimiter); + if (pos1 == std::string::npos) + log_cmd_error("Not enough ports in descriptor string"); + size_t pos2 = str.find(delimiter, pos1 + 1); + if (pos2 == std::string::npos) + log_cmd_error("Not enough ports in descriptor string"); + size_t pos3 = str.find(delimiter, pos2 + 1); + if (pos3 != std::string::npos) + log_cmd_error("Too many ports in descriptor string"); + + std::string ce = str.substr(0, pos1); + c.ce_pin = RTLIL::escape_id(ce); + + std::string clk_in = str.substr(pos1 + 1, pos2 - (pos1 + 1)); + c.clk_in_pin = RTLIL::escape_id(clk_in); + + std::string clk_out = str.substr(pos2 + 1, str.size() - (pos2 + 1)); + c.clk_out_pin = RTLIL::escape_id(clk_out); + return c; +} + +struct ClockgatePass : public Pass { + ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { } + void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" clockgate [options] [selection]\n"); + log("\n"); + log("Creates gated clock nets for sets of FFs with clock enable\n"); + log("sharing a clock and replaces the FFs with versions without\n"); + log("clock enable inputs. Intended to reduce power consumption\n"); + log("in ASIC designs.\n"); + log("\n"); + log(" -pos ::\n"); + log(" If specified, rising-edge FFs will have CE inputs\n"); + log(" removed and a gated clock will be created by the\n"); + log(" user-specified ICG (integrated clock gating)\n"); + log(" cell with ports named , , .\n"); + log(" The ICG's clock enable pin must be active high.\n"); + log(" -neg ::\n"); + log(" If specified, falling-edge FFs will have CE inputs\n"); + log(" removed and a gated clock will be created by the\n"); + log(" user-specified ICG (integrated clock gating)\n"); + log(" cell with ports named , , .\n"); + log(" The ICG's clock enable pin must be active high.\n"); + log(" -tie_lo \n"); + log(" Port of the ICG will be tied to zero.\n"); + log(" Intended for DFT scan-enable pins.\n"); + log(" -min_net_size \n"); + log(" Only work on clocks with at least eligible FFs.\n"); + // log(" \n"); + } + + SigMap sigmap; + FfInitVals initvals; + + // One ICG will be generated per ClkNetInfo + // if the number of FFs associated with it is sufficent + struct ClkNetInfo { + // Original, ungated clock into enabled FF + Wire* clk_net; + // Original clock enable into enabled FF + Wire* ce_net; + bool pol_clk; + bool pol_ce; + unsigned int hash() const { + auto t = std::make_tuple(clk_net, ce_net, pol_clk, pol_ce); + unsigned int h = mkhash_init; + h = mkhash(h, hash_ops::hash(t)); + return h; + } + bool operator==(const ClkNetInfo& other) const { + return (clk_net == other.clk_net) && + (ce_net == other.ce_net) && + (pol_clk == other.pol_clk) && + (pol_ce == other.pol_ce); + } + }; + + struct GClkNetInfo { + // How many CE FFs on this CLK net have we seen? + int net_size; + // After ICG generation, we have new gated CLK signals + Wire* new_net; + }; + + ClkNetInfo clk_info_from_ff(FfData& ff) { + Wire* clk = ff.sig_clk.as_wire(); + Wire* ce = ff.sig_ce.as_wire(); + ClkNetInfo info{clk, ce, ff.pol_clk, ff.pol_ce}; + return info; + } + + void execute(std::vector args, RTLIL::Design *design) override { + log_header(design, "Executing CLOCK_GATE pass (extract clock gating out of flip flops).\n"); + + std::optional pos_icg_desc; + std::optional neg_icg_desc; + std::vector tie_lo_ports; + int min_net_size = 0; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-pos" && argidx+2 < args.size()) { + auto name = args[++argidx]; + auto rest = args[++argidx]; + pos_icg_desc = icg_from_arg(name, rest); + } + if (args[argidx] == "-neg" && argidx+2 < args.size()) { + auto name = args[++argidx]; + auto rest = args[++argidx]; + neg_icg_desc = icg_from_arg(name, rest); + } + if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) { + tie_lo_ports.push_back(RTLIL::escape_id(args[++argidx])); + } + if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) { + min_net_size = atoi(args[++argidx].c_str()); + } + } + + extra_args(args, argidx, design); + + pool ce_ffs; + dict clk_nets; + + int gated_flop_count = 0; + for (auto module : design->selected_whole_modules()) { + sigmap.set(module); + initvals.set(&sigmap, module); + for (auto cell : module->cells()) { + if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + continue; + + FfData ff(&initvals, cell); + if (ff.has_ce) { + ce_ffs.insert(cell); + + ClkNetInfo info = clk_info_from_ff(ff); + auto it = clk_nets.find(info); + if (it == clk_nets.end()) + clk_nets[info] = GClkNetInfo(); + clk_nets[info].net_size++; + } + } + + for (auto& clk_net : clk_nets) { + log_debug("checking clk net %s\n", clk_net.first.clk_net->name.c_str()); + auto& clk = clk_net.first; + auto& gclk = clk_net.second; + + if (gclk.net_size < min_net_size) + continue; + + std::optional matching_icg_desc; + + if (pos_icg_desc && clk.pol_clk) + matching_icg_desc = pos_icg_desc; + else if (neg_icg_desc && !clk.pol_clk) + matching_icg_desc = neg_icg_desc; + + if (!matching_icg_desc) + continue; + + log_debug("building ICG for clk net %s\n", clk_net.first.clk_net->name.c_str()); + Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name); + icg->setPort(matching_icg_desc->ce_pin, clk.ce_net); + icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_net); + gclk.new_net = module->addWire(NEW_ID); + icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); + // Tie low DFT ports like scan chain enable + for (auto port : tie_lo_ports) + icg->setPort(port, Const(0)); + // Fix CE polarity if needed + if (!clk.pol_ce) { + SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_net); + icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); + } + } + + for (auto cell : ce_ffs) { + FfData ff(&initvals, cell); + ClkNetInfo info = clk_info_from_ff(ff); + auto it = clk_nets.find(info); + log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets"); + + if (!it->second.new_net) + continue; + + log_debug("Fix up FF %s\n", cell->name.c_str()); + // Now we start messing with the design + ff.has_ce = false; + // Construct the clock gate + // ICG = integrated clock gate, industry shorthand + ff.sig_clk = (*it).second.new_net; + + // Rebuild the flop + (void)ff.emit(); + + gated_flop_count++; + } + ce_ffs.clear(); + clk_nets.clear(); + } + + log("Converted %d FFs.\n", gated_flop_count); + } +} ClockgatePass; + + +PRIVATE_NAMESPACE_END diff --git a/tests/techmap/clockgate.ys b/tests/techmap/clockgate.ys new file mode 100644 index 000000000..9a48344a0 --- /dev/null +++ b/tests/techmap/clockgate.ys @@ -0,0 +1,88 @@ +read_verilog << EOT + +module dffe_00( input clk, en, + input d1, output reg q1, + ); + always @( negedge clk ) begin + if ( ~en ) + q1 <= d1; + end +endmodule + +module dffe_01( input clk, en, + input d1, output reg q1, + ); + always @( negedge clk ) begin + if ( en ) + q1 <= d1; + end +endmodule + +module dffe_10( input clk, en, + input d1, output reg q1, + ); + always @( posedge clk ) begin + if ( ~en ) + q1 <= d1; + end +endmodule + +module dffe_11( input clk, en, + input d1, output reg q1, + ); + always @( posedge clk ) begin + if ( en ) + q1 <= d1; + end +endmodule + +EOT + +proc +opt + +design -save before + +#------------------------------------------------------------------------------ + +clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen + +# falling edge clock flops don't get matched on -pos +select -module dffe_00 -assert-count 0 t:\\pdk_icg +select -module dffe_01 -assert-count 0 t:\\pdk_icg +# falling edge clock flops do get matched on -pos +select -module dffe_10 -assert-count 1 t:\\pdk_icg +select -module dffe_11 -assert-count 1 t:\\pdk_icg +# if necessary, EN is inverted, since the given ICG +# is assumed to have an active-high EN +select -module dffe_10 -assert-count 1 t:\$_NOT_ +select -module dffe_11 -assert-count 0 t:\$_NOT_ + +#------------------------------------------------------------------------------ + +design -load before +clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen + +# rising edge clock flops don't get matched on -neg +select -module dffe_00 -assert-count 1 t:\\pdk_icg +select -module dffe_01 -assert-count 1 t:\\pdk_icg +# rising edge clock flops do get matched on -neg +select -module dffe_10 -assert-count 0 t:\\pdk_icg +select -module dffe_11 -assert-count 0 t:\\pdk_icg +# if necessary, EN is inverted, since the given ICG +# is assumed to have an active-high EN +select -module dffe_00 -assert-count 1 t:\$_NOT_ +select -module dffe_01 -assert-count 0 t:\$_NOT_ + +#------------------------------------------------------------------------------ + +design -load before +clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen + +# No FF set sharing a (clock, clock enable) pair is large enough +select -module dffe_00 -assert-count 0 t:\\pdk_icg +select -module dffe_01 -assert-count 0 t:\\pdk_icg +select -module dffe_10 -assert-count 0 t:\\pdk_icg +select -module dffe_11 -assert-count 0 t:\\pdk_icg + +# TODO test -tie_lo From dc039d8be485070fde5535dba3ffcc14020e9aab Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 9 Sep 2024 21:03:22 +0200 Subject: [PATCH 209/342] clockgate: test fine-grained cells --- tests/techmap/clockgate.ys | 40 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tests/techmap/clockgate.ys b/tests/techmap/clockgate.ys index 9a48344a0..c61dd4e6e 100644 --- a/tests/techmap/clockgate.ys +++ b/tests/techmap/clockgate.ys @@ -36,6 +36,15 @@ module dffe_11( input clk, en, end endmodule +module dffe_wide_11( input clk, en, + input [3:0] d1, output reg [3:0] q1, + ); + always @( posedge clk ) begin + if ( en ) + q1 <= d1; + end +endmodule + EOT proc @@ -45,6 +54,8 @@ design -save before #------------------------------------------------------------------------------ +# Test -pos + clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen # falling edge clock flops don't get matched on -pos @@ -58,8 +69,13 @@ select -module dffe_11 -assert-count 1 t:\\pdk_icg select -module dffe_10 -assert-count 1 t:\$_NOT_ select -module dffe_11 -assert-count 0 t:\$_NOT_ +# Extra credit: multi-bit FFs work fine as well +select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg + #------------------------------------------------------------------------------ +# Test -neg + design -load before clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen @@ -76,6 +92,30 @@ select -module dffe_01 -assert-count 0 t:\$_NOT_ #------------------------------------------------------------------------------ +# Same as first case, but on fine-grained cells + +design -load before + +techmap + +clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen + +# falling edge clock flops don't get matched on -pos +select -module dffe_00 -assert-count 0 t:\\pdk_icg +select -module dffe_01 -assert-count 0 t:\\pdk_icg +# falling edge clock flops do get matched on -pos +select -module dffe_10 -assert-count 1 t:\\pdk_icg +select -module dffe_11 -assert-count 1 t:\\pdk_icg +# if necessary, EN is inverted, since the given ICG +# is assumed to have an active-high EN +select -module dffe_10 -assert-count 1 t:\$_NOT_ +select -module dffe_11 -assert-count 0 t:\$_NOT_ + +# Extra credit: multi-bit FFs work fine as well +select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg + +#------------------------------------------------------------------------------ + design -load before clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen From 7e473299bdc616f0c76931a65a04cf166cc972a1 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 9 Sep 2024 21:20:19 +0200 Subject: [PATCH 210/342] clockgate: bail on constant signals --- passes/techmap/clockgate.cc | 3 ++- tests/techmap/clockgate.ys | 46 +++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 66f8c7d6c..5f5ae81b2 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -151,7 +151,8 @@ struct ClockgatePass : public Pass { continue; FfData ff(&initvals, cell); - if (ff.has_ce) { + // It would be odd to get constants, but we better handle it + if (ff.has_ce && ff.sig_clk.is_wire() && ff.sig_ce.is_wire()) { ce_ffs.insert(cell); ClkNetInfo info = clk_info_from_ff(ff); diff --git a/tests/techmap/clockgate.ys b/tests/techmap/clockgate.ys index c61dd4e6e..23a865e75 100644 --- a/tests/techmap/clockgate.ys +++ b/tests/techmap/clockgate.ys @@ -125,4 +125,50 @@ select -module dffe_01 -assert-count 0 t:\\pdk_icg select -module dffe_10 -assert-count 0 t:\\pdk_icg select -module dffe_11 -assert-count 0 t:\\pdk_icg +#------------------------------------------------------------------------------ + +design -reset +read_rtlil << EOT + +module \bad1 + wire input 1 \clk + wire input 3 \d1 + wire input 2 \en + wire output 4 \q1 + cell $dffe $auto$ff.cc:266:slice$27 + parameter \CLK_POLARITY 1 + parameter \EN_POLARITY 1 + parameter \WIDTH 1 + connect \CLK \clk + connect \D \d1 + connect \EN 1'1 + connect \Q \q1 + end +end + +module \bad2 + wire input 1 \clk + wire input 3 \d1 + wire input 2 \en + wire output 4 \q1 + cell $dffe $auto$ff.cc:266:slice$27 + parameter \CLK_POLARITY 1 + parameter \EN_POLARITY 1 + parameter \WIDTH 1 + connect \CLK 1'1 + connect \D \d1 + connect \EN \en + connect \Q \q1 + end +end + +EOT + +# Check we don't choke on constants +clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen +select -module bad1 -assert-count 0 t:\\pdk_icg +select -module bad2 -assert-count 0 t:\\pdk_icg + +#------------------------------------------------------------------------------ + # TODO test -tie_lo From 693724101280384479e0a3d15647a58a5e445a50 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 10 Sep 2024 00:19:34 +0000 Subject: [PATCH 211/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b841c2fa6..b1ee1c6d9 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+106 +YOSYS_VER := 0.45+109 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From bdc43c659262b4334694273cc6af082af4f10f81 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 21 Aug 2024 16:21:29 +0200 Subject: [PATCH 212/342] Add left and right bound properties to wire. Add test. Fix printing for signed attributes Co-authored-by: N. Engelhardt Co-authored-by: Roland Coeurjoly --- frontends/verific/verific.cc | 13 +++++++++++++ kernel/rtlil.cc | 2 +- kernel/rtlil.h | 2 +- passes/cmds/printattrs.cc | 2 +- tests/verific/bounds.vhd | 18 ++++++++++++++++++ tests/verific/bounds.ys | 6 ++++++ 6 files changed, 40 insertions(+), 3 deletions(-) create mode 100644 tests/verific/bounds.vhd create mode 100644 tests/verific/bounds.ys diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 2dd8aa095..57c3ef14e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -450,6 +450,19 @@ void VerificImporter::import_attributes(dict &att auto type_range = nl->GetTypeRange(obj->Name()); if (!type_range) return; + if (type_range->IsTypeScalar()) { + const long long bottom_bound = type_range->GetScalarRangeLeftBound(); + const long long top_bound = type_range->GetScalarRangeRightBound(); + const unsigned bit_width = type_range->NumElements(); + RTLIL::Const bottom_const(bottom_bound, bit_width); + RTLIL::Const top_const(top_bound, bit_width); + if (bottom_bound < 0 || top_bound < 0) { + bottom_const.flags |= RTLIL::CONST_FLAG_SIGNED; + top_const.flags |= RTLIL::CONST_FLAG_SIGNED; + } + attributes.emplace(ID(bottom_bound), bottom_const); + attributes.emplace(ID(top_bound), top_const); + } if (!type_range->IsTypeEnum()) return; #ifdef VERIFIC_VHDL_SUPPORT diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d3946a620..e208a09fd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -213,7 +213,7 @@ RTLIL::Const::Const(const std::string &str) } } -RTLIL::Const::Const(int val, int width) +RTLIL::Const::Const(long long val, int width) { flags = RTLIL::CONST_FLAG_NONE; bits.reserve(width); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f9da29495..03ab248fa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -662,7 +662,7 @@ struct RTLIL::Const Const() : flags(RTLIL::CONST_FLAG_NONE) {} Const(const std::string &str); - Const(int val, int width = 32); + Const(long long val, int width = 32); Const(RTLIL::State bit, int width = 1); Const(const std::vector &bits) : bits(bits) { flags = CONST_FLAG_NONE; } Const(const std::vector &bits); diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 7973ac262..6f630479d 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -42,7 +42,7 @@ struct PrintAttrsPass : public Pass { static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { if (x.flags == RTLIL::CONST_FLAG_STRING) log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str()); - else if (x.flags == RTLIL::CONST_FLAG_NONE) + else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED) log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str()); else log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail diff --git a/tests/verific/bounds.vhd b/tests/verific/bounds.vhd new file mode 100644 index 000000000..14c6c34a7 --- /dev/null +++ b/tests/verific/bounds.vhd @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity work is + Port ( + a : in INTEGER range -5 to 10; + b : out INTEGER range -6 to 11 + ); +end entity work; + +architecture Behavioral of work is +begin + process(a) + begin + b <= a; + end process; +end architecture Behavioral; diff --git a/tests/verific/bounds.ys b/tests/verific/bounds.ys new file mode 100644 index 000000000..425af717c --- /dev/null +++ b/tests/verific/bounds.ys @@ -0,0 +1,6 @@ +read -vhdl bounds.vhd +verific -import work +select -assert-count 1 a:bottom_bound=5'bs11011 +select -assert-count 1 a:top_bound=5'bs01010 +select -assert-count 1 a:bottom_bound=5'bs11010 +select -assert-count 1 a:top_bound=5'bs01011 \ No newline at end of file From ab35dff702310668b6521466718c56cfd159ec3e Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 11 Sep 2024 10:18:51 +1000 Subject: [PATCH 213/342] Gowin. Add the EMCU primitive. EMCU is a micro-processor based on ARM Cortex-M3 embedded in the GW1NSR-4C chip used in the Tangnano4k board. Signed-off-by: YRabbit --- techlibs/gowin/cells_sim.v | 98 ++++++++++++++++++++++++++++++++++++ techlibs/gowin/cells_xtra.py | 2 +- techlibs/gowin/cells_xtra.v | 3 -- 3 files changed, 99 insertions(+), 4 deletions(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 96121a881..76635355d 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -1966,5 +1966,103 @@ output CLKOUT; parameter DCS_MODE = "RISING"; endmodule +(* blackbox *) +module EMCU ( + input FCLK, + input PORESETN, + input SYSRESETN, + input RTCSRCCLK, + output [15:0] IOEXPOUTPUTO, + output [15:0] IOEXPOUTPUTENO, + input [15:0] IOEXPINPUTI, + output UART0TXDO, + output UART1TXDO, + output UART0BAUDTICK, + output UART1BAUDTICK, + input UART0RXDI, + input UART1RXDI, + output INTMONITOR, + output MTXHRESETN, + output [12:0] SRAM0ADDR, + output [3:0] SRAM0WREN, + output [31:0] SRAM0WDATA, + output SRAM0CS, + input [31:0] SRAM0RDATA, + output TARGFLASH0HSEL, + output [28:0] TARGFLASH0HADDR, + output [1:0] TARGFLASH0HTRANS, + output [2:0] TARGFLASH0HSIZE, + output [2:0] TARGFLASH0HBURST, + output TARGFLASH0HREADYMUX, + input [31:0] TARGFLASH0HRDATA, + input [2:0] TARGFLASH0HRUSER, + input TARGFLASH0HRESP, + input TARGFLASH0EXRESP, + input TARGFLASH0HREADYOUT, + output TARGEXP0HSEL, + output [31:0] TARGEXP0HADDR, + output [1:0] TARGEXP0HTRANS, + output TARGEXP0HWRITE, + output [2:0] TARGEXP0HSIZE, + output [2:0] TARGEXP0HBURST, + output [3:0] TARGEXP0HPROT, + output [1:0] TARGEXP0MEMATTR, + output TARGEXP0EXREQ, + output [3:0] TARGEXP0HMASTER, + output [31:0] TARGEXP0HWDATA, + output TARGEXP0HMASTLOCK, + output TARGEXP0HREADYMUX, + output TARGEXP0HAUSER, + output [3:0] TARGEXP0HWUSER, + input [31:0] TARGEXP0HRDATA, + input TARGEXP0HREADYOUT, + input TARGEXP0HRESP, + input TARGEXP0EXRESP, + input [2:0] TARGEXP0HRUSER, + output [31:0] INITEXP0HRDATA, + output INITEXP0HREADY, + output INITEXP0HRESP, + output INITEXP0EXRESP, + output [2:0] INITEXP0HRUSER, + input INITEXP0HSEL, + input [31:0] INITEXP0HADDR, + input [1:0] INITEXP0HTRANS, + input INITEXP0HWRITE, + input [2:0] INITEXP0HSIZE, + input [2:0] INITEXP0HBURST, + input [3:0] INITEXP0HPROT, + input [1:0] INITEXP0MEMATTR, + input INITEXP0EXREQ, + input [3:0] INITEXP0HMASTER, + input [31:0] INITEXP0HWDATA, + input INITEXP0HMASTLOCK, + input INITEXP0HAUSER, + input [3:0] INITEXP0HWUSER, + output [3:0] APBTARGEXP2PSTRB, + output [2:0] APBTARGEXP2PPROT, + output APBTARGEXP2PSEL, + output APBTARGEXP2PENABLE, + output [11:0] APBTARGEXP2PADDR, + output APBTARGEXP2PWRITE, + output [31:0] APBTARGEXP2PWDATA, + input [31:0] APBTARGEXP2PRDATA, + input APBTARGEXP2PREADY, + input APBTARGEXP2PSLVERR, + input [3:0] MTXREMAP, + output DAPTDO, + output DAPJTAGNSW, + output DAPNTDOEN, + input DAPSWDITMS, + input DAPTDI, + input DAPNTRST, + input DAPSWCLKTCK, + output [3:0] TPIUTRACEDATA, + output TPIUTRACECLK, + input [4:0] GPINT, + input FLASHERR, + input FLASHINT + + ); +endmodule diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py index 224ece02f..3f0047ecb 100644 --- a/techlibs/gowin/cells_xtra.py +++ b/techlibs/gowin/cells_xtra.py @@ -23,7 +23,7 @@ _skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DF 'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4', 'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4', 'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP', - 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC' + 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC', 'DCS', 'EMCU' } def xtract_cells_decl(dir, fout): fname = os.path.join(dir, 'prim_sim.v') diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v index 6ab50a097..4cb4bab2f 100644 --- a/techlibs/gowin/cells_xtra.v +++ b/techlibs/gowin/cells_xtra.v @@ -1699,9 +1699,6 @@ input CLKIN, CE; output CLKOUT, CLKOUTN; endmodule -module EMCU (...); -endmodule - module FLASH64K (...); input[4:0]XADR; input[5:0]YADR; From 8b464341c22f4bc51de4386e6e0b39f25e9442bf Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Sep 2024 10:24:48 +0200 Subject: [PATCH 214/342] clockgate: no initvals --- passes/techmap/clockgate.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 5f5ae81b2..f14af99ca 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -69,9 +69,6 @@ struct ClockgatePass : public Pass { // log(" \n"); } - SigMap sigmap; - FfInitVals initvals; - // One ICG will be generated per ClkNetInfo // if the number of FFs associated with it is sufficent struct ClkNetInfo { @@ -144,13 +141,11 @@ struct ClockgatePass : public Pass { int gated_flop_count = 0; for (auto module : design->selected_whole_modules()) { - sigmap.set(module); - initvals.set(&sigmap, module); for (auto cell : module->cells()) { if (!RTLIL::builtin_ff_cell_types().count(cell->type)) continue; - FfData ff(&initvals, cell); + FfData ff(nullptr, cell); // It would be odd to get constants, but we better handle it if (ff.has_ce && ff.sig_clk.is_wire() && ff.sig_ce.is_wire()) { ce_ffs.insert(cell); @@ -198,7 +193,7 @@ struct ClockgatePass : public Pass { } for (auto cell : ce_ffs) { - FfData ff(&initvals, cell); + FfData ff(nullptr, cell); ClkNetInfo info = clk_info_from_ff(ff); auto it = clk_nets.find(info); log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets"); From 1372c47036ec428a412f62287e945223e28b2df4 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Sep 2024 11:34:20 +0200 Subject: [PATCH 215/342] internal_stats: astnode (sizeof) --- frontends/ast/ast.cc | 4 ++++ frontends/ast/ast.h | 3 +++ passes/cmds/internal_stats.cc | 3 +++ 3 files changed, 10 insertions(+) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index d21b8f02d..6852ef5d3 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -41,6 +41,8 @@ namespace AST { std::string current_filename; void (*set_line_num)(int) = NULL; int (*get_line_num)() = NULL; + unsigned long long astnodes = 0; + unsigned long long astnode_count() { return astnodes; } } // instantiate global variables (private API) @@ -204,6 +206,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch static unsigned int hashidx_count = 123456789; hashidx_count = mkhash_xorshift(hashidx_count); hashidx_ = hashidx_count; + astnodes++; this->type = type; filename = current_filename; @@ -292,6 +295,7 @@ void AstNode::delete_children() // AstNode destructor AstNode::~AstNode() { + astnodes--; delete_children(); } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 6c4a1e15a..bdff015e3 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -410,6 +410,9 @@ namespace AST extern void (*set_line_num)(int); extern int (*get_line_num)(); + // for stats + unsigned long long astnode_count(); + // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive // to control the filename and linenum properties of new nodes not generated by a frontend parser) void use_internal_line_num(); diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc index fe27bee5e..7dcb9fa85 100644 --- a/passes/cmds/internal_stats.cc +++ b/passes/cmds/internal_stats.cc @@ -25,6 +25,7 @@ #include "kernel/celltypes.h" #include "passes/techmap/libparse.h" #include "kernel/cost.h" +#include "frontends/ast/ast.h" #include "libs/json11/json11.hpp" #if defined(__APPLE__) && defined(__MACH__) @@ -105,6 +106,8 @@ struct InternalStatsPass : public Pass { if (auto mem = current_mem_bytes()) { log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str()); } + auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode); + log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str()); } // stats go here From 1e999a3cb799a015f778b555b7891b4b309853bb Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 11 Sep 2024 19:18:25 +0200 Subject: [PATCH 216/342] clockgate: EN can be a bit on a multi-bit wire --- passes/techmap/clockgate.cc | 29 ++++++++++++++++------------- tests/techmap/clockgate.ys | 22 ++++++++++++++++++++++ 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index f14af99ca..f1992aedc 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -73,20 +73,20 @@ struct ClockgatePass : public Pass { // if the number of FFs associated with it is sufficent struct ClkNetInfo { // Original, ungated clock into enabled FF - Wire* clk_net; + SigBit clk_bit; // Original clock enable into enabled FF - Wire* ce_net; + SigBit ce_bit; bool pol_clk; bool pol_ce; unsigned int hash() const { - auto t = std::make_tuple(clk_net, ce_net, pol_clk, pol_ce); + auto t = std::make_tuple(clk_bit, ce_bit, pol_clk, pol_ce); unsigned int h = mkhash_init; h = mkhash(h, hash_ops::hash(t)); return h; } bool operator==(const ClkNetInfo& other) const { - return (clk_net == other.clk_net) && - (ce_net == other.ce_net) && + return (clk_bit == other.clk_bit) && + (ce_bit == other.ce_bit) && (pol_clk == other.pol_clk) && (pol_ce == other.pol_ce); } @@ -100,8 +100,8 @@ struct ClockgatePass : public Pass { }; ClkNetInfo clk_info_from_ff(FfData& ff) { - Wire* clk = ff.sig_clk.as_wire(); - Wire* ce = ff.sig_ce.as_wire(); + SigBit clk = ff.sig_clk[0]; + SigBit ce = ff.sig_ce[0]; ClkNetInfo info{clk, ce, ff.pol_clk, ff.pol_ce}; return info; } @@ -147,7 +147,12 @@ struct ClockgatePass : public Pass { FfData ff(nullptr, cell); // It would be odd to get constants, but we better handle it - if (ff.has_ce && ff.sig_clk.is_wire() && ff.sig_ce.is_wire()) { + if (ff.has_ce) { + if (!ff.sig_clk.is_bit() || !ff.sig_ce.is_bit()) + continue; + if (!ff.sig_clk[0].is_wire() || !ff.sig_ce[0].is_wire()) + continue; + ce_ffs.insert(cell); ClkNetInfo info = clk_info_from_ff(ff); @@ -159,7 +164,6 @@ struct ClockgatePass : public Pass { } for (auto& clk_net : clk_nets) { - log_debug("checking clk net %s\n", clk_net.first.clk_net->name.c_str()); auto& clk = clk_net.first; auto& gclk = clk_net.second; @@ -176,10 +180,9 @@ struct ClockgatePass : public Pass { if (!matching_icg_desc) continue; - log_debug("building ICG for clk net %s\n", clk_net.first.clk_net->name.c_str()); Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name); - icg->setPort(matching_icg_desc->ce_pin, clk.ce_net); - icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_net); + icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit); + icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit); gclk.new_net = module->addWire(NEW_ID); icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); // Tie low DFT ports like scan chain enable @@ -187,7 +190,7 @@ struct ClockgatePass : public Pass { icg->setPort(port, Const(0)); // Fix CE polarity if needed if (!clk.pol_ce) { - SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_net); + SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit); icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); } } diff --git a/tests/techmap/clockgate.ys b/tests/techmap/clockgate.ys index 23a865e75..dac4de0ec 100644 --- a/tests/techmap/clockgate.ys +++ b/tests/techmap/clockgate.ys @@ -171,4 +171,26 @@ select -module bad2 -assert-count 0 t:\\pdk_icg #------------------------------------------------------------------------------ +# Regression test: EN is a bit from a multi-bit wire +design -reset +read_verilog << EOT +module dffe_wide_11( input clk, input [1:0] en, + input [3:0] d1, output reg [3:0] q1, + ); + always @( posedge clk ) begin + if ( en[0] ) + q1 <= d1; + end +endmodule + +EOT + +proc +opt + +clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen +select -assert-count 1 t:\\pdk_icg + +#------------------------------------------------------------------------------ + # TODO test -tie_lo From 38f9e6c3a2dd09f46508e3fba1c69238ddc8d9f4 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Tue, 27 Aug 2024 08:50:10 +0300 Subject: [PATCH 217/342] -y flag for libyosys Python scripts This adds a Python equivalent to the `-c` option, where scripts importing `libyosys` can be imported and used. Most of the work for this was already done to enable Python passes a couple years back, so this is a relatively small changeset. --- kernel/driver.cc | 44 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 1e4cd0052..bd32872a2 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -241,6 +241,7 @@ int main(int argc, char **argv) std::string topmodule = ""; std::string perffile = ""; bool scriptfile_tcl = false; + bool scriptfile_python = false; bool print_banner = true; bool print_stats = true; bool call_abort = false; @@ -305,6 +306,11 @@ int main(int argc, char **argv) printf("\n"); printf(" -C\n"); printf(" enters TCL interatcive shell mode\n"); +#endif +#ifdef WITH_PYTHON + printf("\n"); + printf(" -y python_scriptfile\n"); + printf(" execute the python script"); #endif printf("\n"); printf(" -p command\n"); @@ -379,7 +385,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVCSgm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:r:D:P:E:x:B:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVCSgm:f:Hh:b:o:p:l:L:qv:tds:c:y:W:w:e:r:D:P:E:x:B:")) != -1) { switch (opt) { @@ -464,11 +470,19 @@ int main(int argc, char **argv) case 's': scriptfile = optarg; scriptfile_tcl = false; + scriptfile_python = false; run_shell = false; break; case 'c': scriptfile = optarg; scriptfile_tcl = true; + scriptfile_python = false; + run_shell = false; + break; + case 'y': + scriptfile = optarg; + scriptfile_tcl = false; + scriptfile_python = true; run_shell = false; break; case 'W': @@ -607,8 +621,9 @@ int main(int argc, char **argv) run_pass(vdef_cmd); } - if (scriptfile.empty() || !scriptfile_tcl) { - // Without a TCL script, arguments following '--' are also treated as frontend files + if (scriptfile.empty() || (!scriptfile_tcl && !scriptfile_python)) { + // Without a TCL or Python script, arguments following '--' are also + // treated as frontend files for (int i = optind; i < argc; ++i) frontend_files.push_back(argv[i]); } @@ -636,7 +651,28 @@ int main(int argc, char **argv) if (Tcl_EvalFile(interp, scriptfile.c_str()) != TCL_OK) log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); #else - log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n"); + log_error("Can't execute TCL script: this version of yosys is not built with TCL support enabled.\n"); +#endif + } else if (scriptfile_python) { +#ifdef WITH_PYTHON + PyObject *sys = PyImport_ImportModule("sys"); + PyObject *new_argv = PyList_New(argc - optind + 1); + PyList_SetItem(new_argv, 0, PyUnicode_FromString(scriptfile.c_str())); + for (int i = optind; i < argc; ++i) + PyList_SetItem(new_argv, i - optind + 1, PyUnicode_FromString(argv[i])); + + PyObject *old_argv = PyObject_GetAttrString(sys, "argv"); + PyObject_SetAttrString(sys, "argv", new_argv); + Py_DECREF(old_argv); + + FILE *scriptfp = fopen(scriptfile.c_str(), "r"); + if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { + log_error("Python interpreter encountered an error:\n"); + log_flush(); + PyErr_Print(); + } +#else + log_error("Can't execute Python script: this version of yosys is not built with Python support enabled.\n"); #endif } else run_frontend(scriptfile, "script"); From 738b5eef0bcbf04eff1a263fd8177c9e24ed02da Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Tue, 10 Sep 2024 13:41:04 +0300 Subject: [PATCH 218/342] Add dirname of script file to sys.path This matches the behavior of running a Python interpreter, where the first element of sys.path is the dirname of the script being run. This allows importing of files and modules in the same directory without messing with PYTHONPATH or similar. --- kernel/driver.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index bd32872a2..0e0a8fa7a 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -660,11 +660,13 @@ int main(int argc, char **argv) PyList_SetItem(new_argv, 0, PyUnicode_FromString(scriptfile.c_str())); for (int i = optind; i < argc; ++i) PyList_SetItem(new_argv, i - optind + 1, PyUnicode_FromString(argv[i])); - + PyObject *old_argv = PyObject_GetAttrString(sys, "argv"); PyObject_SetAttrString(sys, "argv", new_argv); Py_DECREF(old_argv); - + + PyRun_SimpleString(("import os;sys.path.insert(0, os.path.dirname(os.path.abspath(\""+scriptfile+"\")))").c_str()); + FILE *scriptfp = fopen(scriptfile.c_str(), "r"); if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { log_error("Python interpreter encountered an error:\n"); From 8dac27108efdb17313fbeb0a96b1eaae0ecaf2b7 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Wed, 11 Sep 2024 21:39:37 +0300 Subject: [PATCH 219/342] Typos --- kernel/driver.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 0e0a8fa7a..d30b19c96 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -305,12 +305,12 @@ int main(int argc, char **argv) printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n"); printf("\n"); printf(" -C\n"); - printf(" enters TCL interatcive shell mode\n"); + printf(" enters TCL interactive shell mode\n"); #endif #ifdef WITH_PYTHON printf("\n"); printf(" -y python_scriptfile\n"); - printf(" execute the python script"); + printf(" execute a python script with libyosys available as a built-in module\n"); #endif printf("\n"); printf(" -p command\n"); From 229d1ea9374ddec28ec4f7e3ca3eb4b404352f1b Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 12 Sep 2024 00:19:38 +0000 Subject: [PATCH 220/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b1ee1c6d9..3a0d87338 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+109 +YOSYS_VER := 0.45+112 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From a8a92d346951371f3572587140b74854e885c3fd Mon Sep 17 00:00:00 2001 From: Emil J Date: Mon, 16 Sep 2024 13:55:53 +0200 Subject: [PATCH 221/342] clockgate: help string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Martin Povišer --- passes/techmap/clockgate.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index f1992aedc..89eb342fe 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -65,7 +65,7 @@ struct ClockgatePass : public Pass { log(" Port of the ICG will be tied to zero.\n"); log(" Intended for DFT scan-enable pins.\n"); log(" -min_net_size \n"); - log(" Only work on clocks with at least eligible FFs.\n"); + log(" Only transform sets of at least eligible FFs.\n"); // log(" \n"); } From be7c93ec6d3503b5c6feda9f069d02c6eb272de8 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 16 Sep 2024 13:58:27 +0200 Subject: [PATCH 222/342] clockgate: 1-bit const 0 --- passes/techmap/clockgate.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 89eb342fe..da40ae076 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -187,7 +187,7 @@ struct ClockgatePass : public Pass { icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); // Tie low DFT ports like scan chain enable for (auto port : tie_lo_ports) - icg->setPort(port, Const(0)); + icg->setPort(port, Const(0, 1)); // Fix CE polarity if needed if (!clk.pol_ce) { SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit); From f193bcf683b8dcbfa11132ea2e20858cd63cd176 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 16 Sep 2024 14:20:33 +0200 Subject: [PATCH 223/342] clockgate: help string --- passes/techmap/clockgate.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index da40ae076..bf53b02bb 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -44,10 +44,9 @@ struct ClockgatePass : public Pass { log("\n"); log(" clockgate [options] [selection]\n"); log("\n"); - log("Creates gated clock nets for sets of FFs with clock enable\n"); - log("sharing a clock and replaces the FFs with versions without\n"); - log("clock enable inputs. Intended to reduce power consumption\n"); - log("in ASIC designs.\n"); + log("This pass transforms each set of FFs sharing the same clock and\n"); + log("enable signal into a clock-gating cell and a set of enable-less FFs.\n"); + log("Primarily a power-saving transformation on ASIC designs.\n"); log("\n"); log(" -pos ::\n"); log(" If specified, rising-edge FFs will have CE inputs\n"); From c8846243c2701c6e723cc5c866b399e3fbc19fd0 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 17 Sep 2024 00:16:41 +0000 Subject: [PATCH 224/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3a0d87338..77cdce22c 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+112 +YOSYS_VER := 0.45+126 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From d0b5dfa6efaf8325be4dc50296647463db23d51f Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Wed, 27 Sep 2023 18:59:53 +0200 Subject: [PATCH 225/342] Add bufnorm pass Signed-off-by: Claire Xenia Wolf --- passes/techmap/Makefile.inc | 1 + passes/techmap/bufnorm.cc | 180 ++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 passes/techmap/bufnorm.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 0282af790..6bf40434d 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -41,6 +41,7 @@ OBJS += passes/techmap/nlutmap.o OBJS += passes/techmap/shregmap.o OBJS += passes/techmap/deminout.o OBJS += passes/techmap/insbuf.o +OBJS += passes/techmap/bufnorm.o OBJS += passes/techmap/attrmvcp.o OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc new file mode 100644 index 000000000..77588bb6b --- /dev/null +++ b/passes/techmap/bufnorm.cc @@ -0,0 +1,180 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct BufnormPass : public Pass { + BufnormPass() : Pass("bufnorm", "convert design into buffered-normalized form") { } + void help() override + { + log("\n"); + log(" bufnorm [options] [selection]\n"); + log("\n"); + log("Insert buffer cells into the design as needed, to make sure that each wire\n"); + log("has exactly one driving cell port, and aliasing wires are buffered using a\n"); + log("chain of buffers in canonical order.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n"); + + bool connections_mode = false, bits_mode = false; + IdString buf_celltype, buf_inport = ID::A, buf_outport = ID::Y; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + std::string arg = args[argidx]; + if (arg == "-conn") { + connections_mode = true; + continue; + } + if (arg == "-bits") { + bits_mode = true; + continue; + } + if (arg == "-buf" && argidx+3 < args.size()) { + buf_celltype = RTLIL::escape_id(args[++argidx]); + buf_inport = RTLIL::escape_id(args[++argidx]); + buf_outport = RTLIL::escape_id(args[++argidx]); + continue; + } + break; + } + extra_args(args, argidx, design); + + if (buf_celltype == IdString()) + buf_celltype = bits_mode ? ID($_BUF_) : ID($pos); + + for (auto module : design->selected_modules()) + { + SigMap sigmap(module); + module->new_connections({}); + + { + vector old_buffers; + for (auto cell : module->cells()) + { + if (cell->type == buf_celltype) + { + SigSpec insig = sigmap(cell->getPort(buf_inport)); + SigSpec outsig = sigmap(cell->getPort(buf_outport)); + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) + sigmap.add(insig[i], outsig[i]); + old_buffers.push_back(cell); + } + else + { + for (auto &conn : cell->connections()) + { + if (!cell->output(conn.first) || conn.second.is_wire()) + continue; + SigSpec insig = module->addWire(NEW_ID, GetSize(conn.second)); + SigSpec outsig = sigmap(conn.second); + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) + sigmap.add(insig[i], outsig[i]); + cell->setPort(conn.first, insig); + } + } + } + for (auto cell : old_buffers) + module->remove(cell); + } + + dict> bit2wires; + dict mapped_bits; + pool unmapped_wires; + + for (auto wire : module->wires()) + { + for (auto key : sigmap(wire)) + bit2wires[key].insert(wire); + + if (wire->port_input) { + for (auto bit : SigSpec(wire)) + mapped_bits[sigmap(bit)] = bit; + } else { + unmapped_wires.insert(wire); + } + } + + for (auto cell : module->cells()) + { + for (auto &conn : cell->connections()) + { + if (!cell->output(conn.first)) + continue; + + for (auto bit : conn.second) + mapped_bits[sigmap(bit)] = bit; + unmapped_wires.erase(conn.second.as_wire()); + } + } + + struct { + bool operator()(Wire *a, Wire *b) const { + if (a->port_id != b->port_id) + return a->port_id < b->port_id; + return a->name.str() < b->name.str(); + } + } compareWires; + + unmapped_wires.sort(compareWires); + + for (auto wire : unmapped_wires) + { + SigSpec keysig = sigmap(wire), insig = wire, outsig = wire; + for (int i = 0; i < GetSize(insig); i++) + insig[i] = mapped_bits.at(keysig[i], State::Sx); + for (int i = 0; i < GetSize(outsig); i++) + mapped_bits[keysig[i]] = outsig[i]; + + if (connections_mode) { + if (bits_mode) { + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) + module->connect(outsig[i], insig[i]); + } else { + module->connect(outsig, insig); + } + } else { + if (bits_mode) { + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) { + Cell *c = module->addCell(NEW_ID, buf_celltype); + c->setPort(buf_inport, insig[i]); + c->setPort(buf_outport, outsig[i]); + c->fixup_parameters(); + } + } else { + Cell *c = module->addCell(NEW_ID, buf_celltype); + c->setPort(buf_inport, insig); + c->setPort(buf_outport, outsig); + c->fixup_parameters(); + } + } + } + } + } +} BufnormPass; + +PRIVATE_NAMESPACE_END From 32808a03935a3874de0a4ac09dae121d4d25f45d Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Wed, 27 Sep 2023 19:27:08 +0200 Subject: [PATCH 226/342] Improvements and fixes to "bufnorm" cmd Signed-off-by: Claire Xenia Wolf --- passes/techmap/bufnorm.cc | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 77588bb6b..ff27c6c8c 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -69,6 +69,8 @@ struct BufnormPass : public Pass { for (auto module : design->selected_modules()) { + log("Buffer-normalizing module %s.\n", log_id(module)); + SigMap sigmap(module); module->new_connections({}); @@ -112,6 +114,7 @@ struct BufnormPass : public Pass { bit2wires[key].insert(wire); if (wire->port_input) { + log(" primary input: %s\n", log_id(module)); for (auto bit : SigSpec(wire)) mapped_bits[sigmap(bit)] = bit; } else { @@ -126,9 +129,14 @@ struct BufnormPass : public Pass { if (!cell->output(conn.first)) continue; + Wire *w = conn.second.as_wire(); + if (w->name.isPublic()) + log(" directly driven by cell %s port %s: %s\n", + log_id(cell), log_id(conn.first), log_id(w)); + for (auto bit : conn.second) mapped_bits[sigmap(bit)] = bit; - unmapped_wires.erase(conn.second.as_wire()); + unmapped_wires.erase(w); } } @@ -142,6 +150,8 @@ struct BufnormPass : public Pass { unmapped_wires.sort(compareWires); + pool added_buffers; + for (auto wire : unmapped_wires) { SigSpec keysig = sigmap(wire), insig = wire, outsig = wire; @@ -150,6 +160,8 @@ struct BufnormPass : public Pass { for (int i = 0; i < GetSize(outsig); i++) mapped_bits[keysig[i]] = outsig[i]; + log(" adding buffer for %s -> %s\n", log_signal(insig), log_signal(outsig)); + if (connections_mode) { if (bits_mode) { for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) @@ -164,12 +176,36 @@ struct BufnormPass : public Pass { c->setPort(buf_inport, insig[i]); c->setPort(buf_outport, outsig[i]); c->fixup_parameters(); + added_buffers.insert(c); } } else { Cell *c = module->addCell(NEW_ID, buf_celltype); c->setPort(buf_inport, insig); c->setPort(buf_outport, outsig); c->fixup_parameters(); + added_buffers.insert(c); + } + } + } + + for (auto cell : module->cells()) + { + if (added_buffers.count(cell)) + continue; + + for (auto &conn : cell->connections()) + { + if (cell->output(conn.first)) + continue; + + SigSpec newsig = conn.second; + for (auto &bit : newsig) + bit = mapped_bits[sigmap(bit)]; + + if (conn.second != newsig) { + log(" fixing input signal on cell %s port %s: %s\n", + log_id(cell), log_id(conn.first), log_signal(newsig)); + cell->setPort(conn.first, newsig); } } } From f4b7ea5fb3434f8e487cc329172accda1154d543 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Thu, 28 Sep 2023 20:42:07 +0200 Subject: [PATCH 227/342] Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf --- passes/techmap/bufnorm.cc | 186 +++++++++++++++++++++++++++++--------- 1 file changed, 141 insertions(+), 45 deletions(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index ff27c6c8c..8e5bfa775 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -31,8 +31,36 @@ struct BufnormPass : public Pass { log(" bufnorm [options] [selection]\n"); log("\n"); log("Insert buffer cells into the design as needed, to make sure that each wire\n"); - log("has exactly one driving cell port, and aliasing wires are buffered using a\n"); - log("chain of buffers in canonical order.\n"); + log("has exactly one driving cell port, and aliasing wires are buffered using\n"); + log("buffer cells, than can be chained in a canonical order.\n"); + log("\n"); + log("Running 'bufnorm' on the whole design enters 'buffered-normalized mode'.\n"); + log("The commands 'bufnorm -conn' exits 'buffered-normalized mode' again.\n"); + log("\n"); + log(" -bits\n"); + log(" Create single-bit $_BUF_ cells instead of multi-bit $pos cells.\n"); + log("\n"); + log(" -chain\n"); + log(" Chain all alias wires. By default only wires with the 'keep'\n"); + log(" attribute on them are chained.\n"); + log("\n"); + log(" -chain-outputs\n"); + log(" Chain ouput ports. (Uneffected by -flat.)\n"); + log("\n"); + log(" -flat\n"); + log(" Do not chain any wires, not even the ones marked with 'keep'.\n"); + log("\n"); + log(" -nosticky\n"); + log(" Disable 'sticky' behavior of output ports already driving whole\n"); + log(" wires, and always enforce canonical sort order instead.\n"); + log("\n"); + log(" -alphasort\n"); + log(" Strictly use alphanumeric sort for chain-order. (Default is\n"); + log(" to chain 'keep' wires first, then ports in declaration order,\n"); + log(" and then the other wires in alphanumeric sort order.)\n"); + log("\n"); + log(" -conn\n"); + log(" Remove buffers and exit 'buffered-normalized mode'.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -40,6 +68,8 @@ struct BufnormPass : public Pass { log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n"); bool connections_mode = false, bits_mode = false; + bool chain_mode = false, flat_mode = false, nosticky_mode = false; + bool chain_outputs_mode = false, alphasort_mode = false; IdString buf_celltype, buf_inport = ID::A, buf_outport = ID::Y; size_t argidx; @@ -54,16 +84,39 @@ struct BufnormPass : public Pass { bits_mode = true; continue; } - if (arg == "-buf" && argidx+3 < args.size()) { - buf_celltype = RTLIL::escape_id(args[++argidx]); - buf_inport = RTLIL::escape_id(args[++argidx]); - buf_outport = RTLIL::escape_id(args[++argidx]); + if (arg == "-chain") { + chain_mode = true; continue; } + if (arg == "-chain-outputs") { + chain_outputs_mode = true; + continue; + } + if (arg == "-flat") { + flat_mode = true; + continue; + } + if (arg == "-nosticky") { + nosticky_mode = true; + continue; + } + if (arg == "-alphasort") { + alphasort_mode = true; + continue; + } + //if (arg == "-buf" && argidx+3 < args.size()) { + // buf_celltype = RTLIL::escape_id(args[++argidx]); + // buf_inport = RTLIL::escape_id(args[++argidx]); + // buf_outport = RTLIL::escape_id(args[++argidx]); + // continue; + //} break; } extra_args(args, argidx, design); + if (chain_mode && flat_mode) + log_cmd_error("Options -chain and -flat are exclusive.\n"); + if (buf_celltype == IdString()) buf_celltype = bits_mode ? ID($_BUF_) : ID($pos); @@ -78,43 +131,34 @@ struct BufnormPass : public Pass { vector old_buffers; for (auto cell : module->cells()) { - if (cell->type == buf_celltype) - { - SigSpec insig = sigmap(cell->getPort(buf_inport)); - SigSpec outsig = sigmap(cell->getPort(buf_outport)); - for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) - sigmap.add(insig[i], outsig[i]); - old_buffers.push_back(cell); - } - else - { - for (auto &conn : cell->connections()) - { - if (!cell->output(conn.first) || conn.second.is_wire()) - continue; - SigSpec insig = module->addWire(NEW_ID, GetSize(conn.second)); - SigSpec outsig = sigmap(conn.second); - for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) - sigmap.add(insig[i], outsig[i]); - cell->setPort(conn.first, insig); - } - } + if (cell->type != buf_celltype) + continue; + + SigSpec insig = sigmap(cell->getPort(buf_inport)); + SigSpec outsig = sigmap(cell->getPort(buf_outport)); + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) + sigmap.add(insig[i], outsig[i]); + old_buffers.push_back(cell); } for (auto cell : old_buffers) module->remove(cell); } dict> bit2wires; + dict> whole_wires; dict mapped_bits; pool unmapped_wires; for (auto wire : module->wires()) { - for (auto key : sigmap(wire)) - bit2wires[key].insert(wire); + SigSpec keysig = sigmap(wire); + whole_wires[keysig].insert(wire); + + for (auto keybit : sigmap(wire)) + bit2wires[keybit].insert(wire); if (wire->port_input) { - log(" primary input: %s\n", log_id(module)); + log(" primary input: %s\n", log_id(wire)); for (auto bit : SigSpec(wire)) mapped_bits[sigmap(bit)] = bit; } else { @@ -122,6 +166,36 @@ struct BufnormPass : public Pass { } } + struct { + bool alphasort_mode; + bool operator()(Wire *a, Wire *b) const + { + if (!alphasort_mode) + { + // Wires with keep attribute first + bool keep_a = a->get_bool_attribute(ID::keep); + bool keep_b = a->get_bool_attribute(ID::keep); + if (keep_a != keep_b) return keep_a; + + // Ports before non-ports + if ((a->port_id != 0) != (b->port_id != 0)) + return a->port_id != 0; + + // Ports in declaration order + if (a->port_id != b->port_id) + return a->port_id < b->port_id; + } + + // Nets with public names first + if (a->name.isPublic() != b->name.isPublic()) + return a->name.isPublic(); + + // Otherwise just sort by name alphanumerically + return a->name.str() < b->name.str(); + } + } compareWires; + compareWires.alphasort_mode = alphasort_mode; + for (auto cell : module->cells()) { for (auto &conn : cell->connections()) @@ -129,38 +203,60 @@ struct BufnormPass : public Pass { if (!cell->output(conn.first)) continue; - Wire *w = conn.second.as_wire(); + Wire *w = nullptr; + + if (!nosticky_mode && conn.second.is_wire()) + w = conn.second.as_wire(); + + if (w == nullptr) + { + SigSpec keysig = sigmap(conn.second); + auto it = whole_wires.find(keysig); + if (it != whole_wires.end()) { + it->second.sort(compareWires); + w = *(it->second.begin()); + } else { + w = module->addWire(NEW_ID, GetSize(conn.second)); + for (int i = 0; i < GetSize(w); i++) + sigmap.add(SigBit(w, i), keysig[i]); + } + } + if (w->name.isPublic()) log(" directly driven by cell %s port %s: %s\n", log_id(cell), log_id(conn.first), log_id(w)); - for (auto bit : conn.second) + for (auto bit : SigSpec(w)) mapped_bits[sigmap(bit)] = bit; unmapped_wires.erase(w); + + cell->setPort(conn.first, w); } } - struct { - bool operator()(Wire *a, Wire *b) const { - if (a->port_id != b->port_id) - return a->port_id < b->port_id; - return a->name.str() < b->name.str(); - } - } compareWires; - - unmapped_wires.sort(compareWires); - pool added_buffers; + unmapped_wires.sort(compareWires); for (auto wire : unmapped_wires) { + bool chain_this_wire = chain_mode; + if (!flat_mode && wire->get_bool_attribute(ID::keep)) + chain_this_wire = true; + if (chain_outputs_mode && wire->port_output) + chain_this_wire = true; + SigSpec keysig = sigmap(wire), insig = wire, outsig = wire; for (int i = 0; i < GetSize(insig); i++) insig[i] = mapped_bits.at(keysig[i], State::Sx); - for (int i = 0; i < GetSize(outsig); i++) - mapped_bits[keysig[i]] = outsig[i]; + if (chain_this_wire) { + for (int i = 0; i < GetSize(outsig); i++) + mapped_bits[keysig[i]] = outsig[i]; + } - log(" adding buffer for %s -> %s\n", log_signal(insig), log_signal(outsig)); + log(" %s %s for %s -> %s\n", + chain_this_wire ? "chaining" : "adding", + connections_mode ? "connection" : "buffer", + log_signal(insig), log_signal(outsig)); if (connections_mode) { if (bits_mode) { From 4d469f461ba375b1562c2f3f252bb1854024c953 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Fri, 29 Sep 2023 07:03:23 +0200 Subject: [PATCH 228/342] Add coarse-grain $buf buffer cell type Signed-off-by: Claire Xenia Wolf --- kernel/calc.cc | 8 ++++++++ kernel/cellaigs.cc | 2 +- kernel/celledges.cc | 2 +- kernel/celltypes.h | 5 +++-- kernel/qcsat.cc | 2 +- kernel/rtlil.cc | 28 ++++++++++++++++++++++++++-- kernel/rtlil.h | 3 +++ kernel/satgen.cc | 6 +++--- techlibs/common/simlib.v | 20 +++++++++++++++++++- 9 files changed, 65 insertions(+), 11 deletions(-) diff --git a/kernel/calc.cc b/kernel/calc.cc index 9b02a6e30..a7de08f89 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -601,6 +601,14 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo return arg1_ext; } +RTLIL::Const RTLIL::const_buf(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) +{ + RTLIL::Const arg1_ext = arg1; + extend_u0(arg1_ext, result_len, signed1); + + return arg1_ext; +} + RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) { RTLIL::Const arg1_ext = arg1; diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 5dda4503f..de0a49394 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -290,7 +290,7 @@ Aig::Aig(Cell *cell) } } - if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($_BUF_))) + if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_))) { for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { int A = mk.inport(ID::A, i); diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 09cdfd55b..0fbe17c56 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -392,7 +392,7 @@ PRIVATE_NAMESPACE_END bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell) { - if (cell->type.in(ID($not), ID($pos))) { + if (cell->type.in(ID($not), ID($pos), ID($buf))) { bitwise_unary_op(this, cell); return true; } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index fde6624e1..9868827e6 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -114,7 +114,7 @@ struct CellTypes void setup_internals_eval() { std::vector unary_ops = { - ID($not), ID($pos), ID($neg), + ID($not), ID($pos), ID($buf), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not), ID($slice), ID($lut), ID($sop) }; @@ -339,7 +339,7 @@ struct CellTypes type = ID($shl); if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) && - type != ID($pos) && type != ID($neg) && type != ID($not)) { + type != ID($pos) && type != ID($buf) && type != ID($neg) && type != ID($not)) { if (!signed1 || !signed2) signed1 = false, signed2 = false; } @@ -381,6 +381,7 @@ struct CellTypes HANDLE_CELL_TYPE(modfloor) HANDLE_CELL_TYPE(pow) HANDLE_CELL_TYPE(pos) + HANDLE_CELL_TYPE(buf) HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE diff --git a/kernel/qcsat.cc b/kernel/qcsat.cc index aaee984fb..c9d00efa1 100644 --- a/kernel/qcsat.cc +++ b/kernel/qcsat.cc @@ -77,7 +77,7 @@ void QuickConeSat::prepare() int QuickConeSat::cell_complexity(RTLIL::Cell *cell) { - if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($_BUF_))) + if (cell->type.in(ID($concat), ID($slice), ID($pos), ID($buf), ID($_BUF_))) return 0; if (cell->type.in(ID($not), ID($and), ID($or), ID($xor), ID($xnor), ID($reduce_and), ID($reduce_or), ID($reduce_xor), diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d62736e15..96ded993d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1108,6 +1108,13 @@ namespace { cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:")) return; + if (cell->type == ID($buf)) { + port(ID::A, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type.in(ID($not), ID($pos), ID($neg))) { param_bool(ID::A_SIGNED); port(ID::A, param(ID::A_WIDTH)); @@ -2493,6 +2500,23 @@ DEF_METHOD(ReduceBool, 1, ID($reduce_bool)) DEF_METHOD(LogicNot, 1, ID($logic_not)) #undef DEF_METHOD +#define DEF_METHOD(_func, _y_size, _type) \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool /* is_signed */, const std::string &src) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->parameters[ID::WIDTH] = sig_a.size(); \ + cell->setPort(ID::A, sig_a); \ + cell->setPort(ID::Y, sig_y); \ + cell->set_src_attribute(src); \ + return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed, const std::string &src) { \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + add ## _func(name, sig_a, sig_y, is_signed, src); \ + return sig_y; \ + } +DEF_METHOD(Buf, sig_a.size(), ID($buf)) +#undef DEF_METHOD + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ @@ -3654,9 +3678,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) return; - if (type == ID($mux) || type == ID($pmux) || type == ID($bmux)) { + if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux)) { parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); - if (type != ID($mux)) + if (type != ID($buf) && type != ID($mux)) parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); check(); return; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 319198711..ba01c6a1b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -503,6 +503,7 @@ namespace RTLIL RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); + RTLIL::Const const_buf (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_mux (const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3); @@ -1280,6 +1281,7 @@ public: RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); + RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); @@ -1414,6 +1416,7 @@ public: RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); + RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = ""); RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = ""); diff --git a/kernel/satgen.cc b/kernel/satgen.cc index a6db78868..946343c63 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -430,7 +430,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) return true; } - if (cell->type.in(ID($pos), ID($neg))) + if (cell->type.in(ID($pos), ID($buf), ID($neg))) { std::vector a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector y = importDefSigSpec(cell->getPort(ID::Y), timestep); @@ -438,7 +438,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector yy = model_undef ? ez->vec_var(y.size()) : y; - if (cell->type == ID($pos)) { + if (cell->type.in(ID($pos), ID($buf))) { ez->assume(ez->vec_eq(a, yy)); } else { std::vector zero(a.size(), ez->CONST_FALSE); @@ -451,7 +451,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) std::vector undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); extendSignalWidthUnary(undef_a, undef_y, cell); - if (cell->type == ID($pos)) { + if (cell->type.in(ID($pos), ID($buf))) { ez->assume(ez->vec_eq(undef_a, undef_y)); } else { int undef_any_a = ez->expression(ezSAT::OpOr, undef_a); diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 5bbad34f6..5593cfe0e 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -58,7 +58,6 @@ endgenerate endmodule - // -------------------------------------------------------- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -88,6 +87,25 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $buf (A, Y) +//- +//- A simple coarse-grain buffer cell type. +//- +module \$buf (A, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +output [WIDTH-1:0] Y; + +assign Y = A; + +endmodule + +// -------------------------------------------------------- + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $neg (A, Y) From d027ead4b582e285731d386ea3c60d72778f3f0d Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Fri, 29 Sep 2023 07:04:22 +0200 Subject: [PATCH 229/342] Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf --- kernel/constids.inc | 1 + passes/techmap/bufnorm.cc | 229 ++++++++++++++++++++++++++------------ 2 files changed, 156 insertions(+), 74 deletions(-) diff --git a/kernel/constids.inc b/kernel/constids.inc index 00db94af4..3052afb49 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -43,6 +43,7 @@ X(CE_OVER_SRST) X(CFG_ABITS) X(CFG_DBITS) X(CFG_INIT) +X(chain) X(CI) X(CLK) X(clkbuf_driver) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 8e5bfa775..0aba2a750 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -35,20 +35,29 @@ struct BufnormPass : public Pass { log("buffer cells, than can be chained in a canonical order.\n"); log("\n"); log("Running 'bufnorm' on the whole design enters 'buffered-normalized mode'.\n"); - log("The commands 'bufnorm -conn' exits 'buffered-normalized mode' again.\n"); log("\n"); - log(" -bits\n"); - log(" Create single-bit $_BUF_ cells instead of multi-bit $pos cells.\n"); + log(" -buf\n"); + log(" Create $buf cells for all buffers. The default is to use $_BUF_ cells\n"); + log(" for sigle-bit buffers and $buf cells only for multi-bit buffers.\n"); log("\n"); log(" -chain\n"); - log(" Chain all alias wires. By default only wires with the 'keep'\n"); - log(" attribute on them are chained.\n"); + log(" Chain all alias wires. By default only wires with positive-valued\n"); + log(" 'chain' or 'keep' attribute on them are chained.\n"); log("\n"); - log(" -chain-outputs\n"); - log(" Chain ouput ports. (Uneffected by -flat.)\n"); + log(" -output\n"); + log(" Enable chaining of ouput ports wires.\n"); + log("\n"); + log(" -public\n"); + log(" Enable chaining of wires wth public names.\n"); + log("\n"); + log(" -nochain\n"); + log(" Disable chaining of wires with 'chain' attribute.\n"); + log("\n"); + log(" -nokeep\n"); + log(" Disable chaining of wires with 'keep' attribute.\n"); log("\n"); log(" -flat\n"); - log(" Do not chain any wires, not even the ones marked with 'keep'.\n"); + log(" Alias for -nokeep and -nochain.\n"); log("\n"); log(" -nosticky\n"); log(" Disable 'sticky' behavior of output ports already driving whole\n"); @@ -59,41 +68,71 @@ struct BufnormPass : public Pass { log(" to chain 'keep' wires first, then ports in declaration order,\n"); log(" and then the other wires in alphanumeric sort order.)\n"); log("\n"); + log(" -noinit\n"); + log(" Do not move 'init' attributes to the wires on FF output ports.\n"); + log("\n"); + log("Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all\n"); + log("$buf buffer cells and exit 'buffered-normalized mode' again.\n"); + log("\n"); + log(" -pos\n"); + log(" Create (multi- and single-bit) $pos cells instead $buf and $_BUF_.\n"); + log("\n"); + log(" -bits\n"); + log(" Create arrays of $_BUF_ cells instead of multi-bit $buf cells.\n"); + log("\n"); log(" -conn\n"); - log(" Remove buffers and exit 'buffered-normalized mode'.\n"); + log(" Create 'direct connections' instead of buffer cells.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n"); - bool connections_mode = false, bits_mode = false; - bool chain_mode = false, flat_mode = false, nosticky_mode = false; - bool chain_outputs_mode = false, alphasort_mode = false; - IdString buf_celltype, buf_inport = ID::A, buf_outport = ID::Y; + bool buf_mode = false; + bool chain_mode = false; + bool output_mode = false; + bool public_mode = false; + bool nochain_mode = false; + bool nokeep_mode = false; + bool nosticky_mode = false; + bool alphasort_mode = false; + bool noinit_mode = false; // FIXME: Actually move init attributes + + bool pos_mode = false; + bool bits_mode = false; + bool conn_mode = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; - if (arg == "-conn") { - connections_mode = true; - continue; - } - if (arg == "-bits") { - bits_mode = true; + if (arg == "-buf") { + buf_mode = true; continue; } if (arg == "-chain") { chain_mode = true; continue; } - if (arg == "-chain-outputs") { - chain_outputs_mode = true; + if (arg == "-output") { + output_mode = true; + continue; + } + if (arg == "-public") { + public_mode = true; + continue; + } + if (arg == "-nochain") { + nochain_mode = true; + continue; + } + if (arg == "-nokeep") { + nokeep_mode = true; continue; } if (arg == "-flat") { - flat_mode = true; + nochain_mode = true; + nokeep_mode = true; continue; } if (arg == "-nosticky") { @@ -104,21 +143,34 @@ struct BufnormPass : public Pass { alphasort_mode = true; continue; } - //if (arg == "-buf" && argidx+3 < args.size()) { - // buf_celltype = RTLIL::escape_id(args[++argidx]); - // buf_inport = RTLIL::escape_id(args[++argidx]); - // buf_outport = RTLIL::escape_id(args[++argidx]); - // continue; - //} + if (arg == "-noinit") { + noinit_mode = true; + continue; + } + if (arg == "-pos") { + pos_mode = true; + continue; + } + if (arg == "-bits") { + bits_mode = true; + continue; + } + if (arg == "-conn") { + conn_mode = true; + continue; + } break; } extra_args(args, argidx, design); - if (chain_mode && flat_mode) - log_cmd_error("Options -chain and -flat are exclusive.\n"); + if (buf_mode && pos_mode) + log_cmd_error("Options -buf and -pos are exclusive.\n"); - if (buf_celltype == IdString()) - buf_celltype = bits_mode ? ID($_BUF_) : ID($pos); + if (buf_mode && conn_mode) + log_cmd_error("Options -buf and -conn are exclusive.\n"); + + if (pos_mode && conn_mode) + log_cmd_error("Options -pos and -conn are exclusive.\n"); for (auto module : design->selected_modules()) { @@ -131,11 +183,11 @@ struct BufnormPass : public Pass { vector old_buffers; for (auto cell : module->cells()) { - if (cell->type != buf_celltype) + if (!cell->type.in(ID($buf), ID($_BUF_))) continue; - SigSpec insig = sigmap(cell->getPort(buf_inport)); - SigSpec outsig = sigmap(cell->getPort(buf_outport)); + SigSpec insig = sigmap(cell->getPort(ID::A)); + SigSpec outsig = sigmap(cell->getPort(ID::Y)); for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) sigmap.add(insig[i], outsig[i]); old_buffers.push_back(cell); @@ -166,35 +218,65 @@ struct BufnormPass : public Pass { } } - struct { - bool alphasort_mode; - bool operator()(Wire *a, Wire *b) const + auto chain_this_wire_f = [&](Wire *wire) + { + if (chain_mode) + return true; + + if (output_mode && wire->port_output) + return true; + + if (public_mode && wire->name.isPublic()) + return true; + + if (!nokeep_mode && wire->get_bool_attribute(ID::keep)) + return true; + + if (!nochain_mode && wire->get_bool_attribute(ID::chain)) + return true; + + return false; + }; + + auto compare_wires_f = [&](Wire *a, Wire *b) + { + // Chaining wires first, then flat wires + bool chain_a = chain_this_wire_f(a); + bool chain_b = chain_this_wire_f(b); + if (chain_a != chain_b) return chain_a; + + if (!alphasort_mode) { - if (!alphasort_mode) - { - // Wires with keep attribute first - bool keep_a = a->get_bool_attribute(ID::keep); - bool keep_b = a->get_bool_attribute(ID::keep); - if (keep_a != keep_b) return keep_a; - - // Ports before non-ports - if ((a->port_id != 0) != (b->port_id != 0)) - return a->port_id != 0; - - // Ports in declaration order - if (a->port_id != b->port_id) - return a->port_id < b->port_id; + // Wires with 'chain' attribute first, high values before low values + if (!nochain_mode) { + int chain_a_val = a->attributes.at(ID::chain, Const(0)).as_int(); + int chain_b_val = b->attributes.at(ID::chain, Const(0)).as_int(); + if (chain_a_val != chain_b_val) return chain_a_val > chain_b_val; } - // Nets with public names first - if (a->name.isPublic() != b->name.isPublic()) - return a->name.isPublic(); + // Then wires with 'keep' attribute + if (!nokeep_mode) { + bool keep_a = a->get_bool_attribute(ID::keep); + bool keep_b = b->get_bool_attribute(ID::keep); + if (keep_a != keep_b) return keep_a; + } - // Otherwise just sort by name alphanumerically - return a->name.str() < b->name.str(); + // Ports before non-ports + if ((a->port_id != 0) != (b->port_id != 0)) + return a->port_id != 0; + + // Ports in declaration order + if (a->port_id != b->port_id) + return a->port_id < b->port_id; } - } compareWires; - compareWires.alphasort_mode = alphasort_mode; + + // Nets with public names first + if (a->name.isPublic() != b->name.isPublic()) + return a->name.isPublic(); + + // Otherwise just sort by name alphanumerically + return a->name.str() < b->name.str(); + }; for (auto cell : module->cells()) { @@ -213,7 +295,7 @@ struct BufnormPass : public Pass { SigSpec keysig = sigmap(conn.second); auto it = whole_wires.find(keysig); if (it != whole_wires.end()) { - it->second.sort(compareWires); + it->second.sort(compare_wires_f); w = *(it->second.begin()); } else { w = module->addWire(NEW_ID, GetSize(conn.second)); @@ -236,14 +318,10 @@ struct BufnormPass : public Pass { pool added_buffers; - unmapped_wires.sort(compareWires); + unmapped_wires.sort(compare_wires_f); for (auto wire : unmapped_wires) { - bool chain_this_wire = chain_mode; - if (!flat_mode && wire->get_bool_attribute(ID::keep)) - chain_this_wire = true; - if (chain_outputs_mode && wire->port_output) - chain_this_wire = true; + bool chain_this_wire = chain_this_wire_f(wire); SigSpec keysig = sigmap(wire), insig = wire, outsig = wire; for (int i = 0; i < GetSize(insig); i++) @@ -255,10 +333,10 @@ struct BufnormPass : public Pass { log(" %s %s for %s -> %s\n", chain_this_wire ? "chaining" : "adding", - connections_mode ? "connection" : "buffer", + conn_mode ? "connection" : "buffer", log_signal(insig), log_signal(outsig)); - if (connections_mode) { + if (conn_mode) { if (bits_mode) { for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) module->connect(outsig[i], insig[i]); @@ -267,17 +345,20 @@ struct BufnormPass : public Pass { } } else { if (bits_mode) { + IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : ID($_BUF_); for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) { - Cell *c = module->addCell(NEW_ID, buf_celltype); - c->setPort(buf_inport, insig[i]); - c->setPort(buf_outport, outsig[i]); + Cell *c = module->addCell(NEW_ID, celltype); + c->setPort(ID::A, insig[i]); + c->setPort(ID::Y, outsig[i]); c->fixup_parameters(); added_buffers.insert(c); } } else { - Cell *c = module->addCell(NEW_ID, buf_celltype); - c->setPort(buf_inport, insig); - c->setPort(buf_outport, outsig); + IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : + GetSize(outsig) == 1 ? ID($_BUF_) : ID($buf); + Cell *c = module->addCell(NEW_ID, celltype); + c->setPort(ID::A, insig); + c->setPort(ID::Y, outsig); c->fixup_parameters(); added_buffers.insert(c); } From 8bb70bac8db5a4e555a1a1457935b1b4164d4c35 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Fri, 29 Sep 2023 10:03:36 +0200 Subject: [PATCH 230/342] Improvements in "bufnorm" pass Signed-off-by: Claire Xenia Wolf --- passes/techmap/bufnorm.cc | 79 ++++++++++++++++++++++++++++++--------- 1 file changed, 62 insertions(+), 17 deletions(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 0aba2a750..4ca96d530 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -172,6 +172,12 @@ struct BufnormPass : public Pass { if (pos_mode && conn_mode) log_cmd_error("Options -pos and -conn are exclusive.\n"); + int count_removed_buffers = 0; + int count_updated_buffers = 0; + int count_kept_buffers = 0; + int count_created_buffers = 0; + int count_updated_cellports = 0; + for (auto module : design->selected_modules()) { log("Buffer-normalizing module %s.\n", log_id(module)); @@ -179,21 +185,29 @@ struct BufnormPass : public Pass { SigMap sigmap(module); module->new_connections({}); + dict, Cell*> old_buffers; + { - vector old_buffers; + vector old_dup_buffers; for (auto cell : module->cells()) { if (!cell->type.in(ID($buf), ID($_BUF_))) continue; - SigSpec insig = sigmap(cell->getPort(ID::A)); - SigSpec outsig = sigmap(cell->getPort(ID::Y)); + SigSpec insig = cell->getPort(ID::A); + SigSpec outsig = cell->getPort(ID::Y); for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) sigmap.add(insig[i], outsig[i]); - old_buffers.push_back(cell); + + pair key(cell->type, outsig.as_wire()); + if (old_buffers.count(key)) + old_dup_buffers.push_back(cell); + else + old_buffers[key] = cell; } - for (auto cell : old_buffers) + for (auto cell : old_dup_buffers) module->remove(cell); + count_removed_buffers += GetSize(old_dup_buffers); } dict> bit2wires; @@ -280,6 +294,9 @@ struct BufnormPass : public Pass { for (auto cell : module->cells()) { + if (cell->type.in(ID($buf), ID($_BUF_))) + continue; + for (auto &conn : cell->connections()) { if (!cell->output(conn.first)) @@ -318,6 +335,34 @@ struct BufnormPass : public Pass { pool added_buffers; + auto make_buffer_f = [&](const IdString &type, const SigSpec &src, const SigSpec &dst) + { + auto it = old_buffers.find(pair(type, dst)); + + if (it != old_buffers.end()) + { + Cell *cell = it->second; + old_buffers.erase(it); + added_buffers.insert(cell); + + if (cell->getPort(ID::A) == src) { + count_kept_buffers++; + } else { + cell->setPort(ID::A, src); + count_updated_buffers++; + } + return; + } + + Cell *cell = module->addCell(NEW_ID, type); + added_buffers.insert(cell); + + cell->setPort(ID::A, src); + cell->setPort(ID::Y, dst); + cell->fixup_parameters(); + count_created_buffers++; + }; + unmapped_wires.sort(compare_wires_f); for (auto wire : unmapped_wires) { @@ -346,25 +391,20 @@ struct BufnormPass : public Pass { } else { if (bits_mode) { IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : ID($_BUF_); - for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) { - Cell *c = module->addCell(NEW_ID, celltype); - c->setPort(ID::A, insig[i]); - c->setPort(ID::Y, outsig[i]); - c->fixup_parameters(); - added_buffers.insert(c); - } + for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++) + make_buffer_f(celltype, insig[i], outsig[i]); } else { IdString celltype = pos_mode ? ID($pos) : buf_mode ? ID($buf) : GetSize(outsig) == 1 ? ID($_BUF_) : ID($buf); - Cell *c = module->addCell(NEW_ID, celltype); - c->setPort(ID::A, insig); - c->setPort(ID::Y, outsig); - c->fixup_parameters(); - added_buffers.insert(c); + make_buffer_f(celltype, insig, outsig); } } } + for (auto &it : old_buffers) + module->remove(it.second); + count_removed_buffers += GetSize(old_buffers); + for (auto cell : module->cells()) { if (added_buffers.count(cell)) @@ -383,10 +423,15 @@ struct BufnormPass : public Pass { log(" fixing input signal on cell %s port %s: %s\n", log_id(cell), log_id(conn.first), log_signal(newsig)); cell->setPort(conn.first, newsig); + count_updated_cellports++; } } } } + + log("Summary: removed %d, updated %d, kept %d, and created %d buffers, and updated %d cell ports.\n", + count_removed_buffers, count_updated_buffers, count_kept_buffers, + count_created_buffers, count_updated_cellports); } } BufnormPass; From 80119386c07dbc18dd2174309f17b6e8e5b2bcc2 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Fri, 29 Sep 2023 15:49:15 +0200 Subject: [PATCH 231/342] Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass Signed-off-by: Claire Xenia Wolf --- backends/rtlil/rtlil_backend.cc | 27 +++++-- backends/rtlil/rtlil_backend.h | 6 +- kernel/rtlil.cc | 133 ++++++++++++++++++++++++++++++++ kernel/rtlil.h | 9 +++ passes/techmap/bufnorm.cc | 76 +++++++++++++++++- 5 files changed, 238 insertions(+), 13 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 032954d8c..e6f8daf96 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -118,13 +118,17 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo } } -void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) +void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d) { for (auto &it : wire->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); dump_const(f, it.second); f << stringf("\n"); } + if (flag_d && wire->driverCell) { + f << stringf("%s" "driver %s %s\n", indent.c_str(), + wire->driverCell->name.c_str(), wire->driverPort.c_str()); + } f << stringf("%s" "wire ", indent.c_str()); if (wire->width != 1) f << stringf("width %d ", wire->width); @@ -298,7 +302,7 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } -void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d) { bool print_header = flag_m || design->selected_whole_module(module->name); bool print_body = !flag_n || !design->selected_whole_module(module->name); @@ -335,7 +339,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (!only_selected || design->selected(module, it)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", it); + dump_wire(f, indent + " ", it, flag_d); } for (auto it : module->memories) @@ -384,7 +388,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu f << stringf("%s" "end\n", indent.c_str()); } -void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) +void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d) { int init_autoidx = autoidx; @@ -410,7 +414,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); - dump_module(f, "", module, design, only_selected, flag_m, flag_n); + dump_module(f, "", module, design, only_selected, flag_m, flag_n, flag_d); } } @@ -456,7 +460,7 @@ struct RTLILBackend : public Backend { log("Output filename: %s\n", filename.c_str()); *f << stringf("# Generated by %s\n", yosys_version_str); - RTLIL_BACKEND::dump_design(*f, design, selected, true, false); + RTLIL_BACKEND::dump_design(*f, design, selected, true, false, false); } } RTLILBackend; @@ -493,6 +497,9 @@ struct DumpPass : public Pass { log(" -n\n"); log(" only dump the module headers if the entire module is selected\n"); log("\n"); + log(" -d\n"); + log(" include driver cell and port info on wires in dump format\n"); + log("\n"); log(" -o \n"); log(" write to the specified file.\n"); log("\n"); @@ -503,7 +510,7 @@ struct DumpPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { std::string filename; - bool flag_m = false, flag_n = false, append = false; + bool flag_m = false, flag_n = false, flag_d = false, append = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -527,6 +534,10 @@ struct DumpPass : public Pass { flag_n = true; continue; } + if (arg == "-d") { + flag_d = true; + continue; + } break; } extra_args(args, argidx, design); @@ -548,7 +559,7 @@ struct DumpPass : public Pass { f = &buf; } - RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n); + RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, flag_d); if (!empty) { delete f; diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 35829729c..21d79d8ec 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -34,7 +34,7 @@ namespace RTLIL_BACKEND { void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); - void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire); + void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d = false); void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory); void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell); void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs); @@ -42,8 +42,8 @@ namespace RTLIL_BACKEND { void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy); void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc); void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right); - void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false); - void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false); + void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false); + void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false); } YOSYS_NAMESPACE_END diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 96ded993d..eaba0fe31 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -21,6 +21,7 @@ #include "kernel/macc.h" #include "kernel/celltypes.h" #include "kernel/binding.h" +#include "kernel/sigtools.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/verilog/preproc.h" #include "backends/rtlil/rtlil_backend.h" @@ -3564,6 +3565,104 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname) } } +void RTLIL::Design::bufNormalize(bool enable) +{ + if (!enable) + { + if (!flagBufferedNormalized) + return; + + for (auto module : modules()) { + module->bufNormQueue.clear(); + for (auto wire : module->wires()) { + wire->driverCell = nullptr; + wire->driverPort = IdString(); + } + } + return; + } + + if (!flagBufferedNormalized) + { + for (auto module : modules()) + { + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + if (!cell->output(conn.first) || GetSize(conn.second) == 0) + continue; + if (conn.second.is_wire()) { + Wire *wire = conn.second.as_wire(); + log_assert(wire->driverCell == nullptr); + wire->driverCell = cell; + wire->driverPort = conn.first; + } else { + pair key(cell, conn.first); + module->bufNormQueue.insert(key); + } + } + } + + flagBufferedNormalized = true; + } + + for (auto module : modules()) + module->bufNormalize(); +} + +void RTLIL::Module::bufNormalize() +{ + if (!design->flagBufferedNormalized) + return; + + while (GetSize(bufNormQueue)) + { + pool> queue; + bufNormQueue.swap(queue); + + pool outWires; + for (auto &conn : connections()) + for (auto &chunk : conn.first.chunks()) + if (chunk.wire) outWires.insert(chunk.wire); + + SigMap sigmap(this); + new_connections({}); + + for (auto &key : queue) + { + Cell *cell = key.first; + const IdString &portname = key.second; + const SigSpec &sig = cell->getPort(portname); + if (GetSize(sig) == 0) continue; + + if (sig.is_wire()) { + Wire *wire = sig.as_wire(); + log_assert(wire->driverCell == nullptr); + wire->driverCell = cell; + wire->driverPort = portname; + continue; + } + + for (auto &chunk : sig.chunks()) + if (chunk.wire) outWires.insert(chunk.wire); + + Wire *wire = addWire(NEW_ID, GetSize(sig)); + sigmap.add(sig, wire); + cell->setPort(portname, wire); + + // FIXME: Move init attributes from old 'sig' to new 'wire' + } + + for (auto wire : outWires) + { + SigSpec outsig = wire, insig = sigmap(wire); + for (int i = 0; i < GetSize(wire); i++) + if (insig[i] == outsig[i]) + insig[i] = State::Sx; + addBuf(NEW_ID, insig, outsig); + } + } +} + void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal) { auto r = connections_.insert(portname); @@ -3583,6 +3682,40 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal log_backtrace("-X- ", yosys_xtrace-1); } + while (module->design && module->design->flagBufferedNormalized && output(portname)) + { + pair key(this, portname); + + if (conn_it->second.is_wire()) { + Wire *w = conn_it->second.as_wire(); + if (w->driverCell == this && w->driverPort == portname) { + w->driverCell = nullptr; + w->driverPort = IdString(); + } + } + + if (GetSize(signal) == 0) { + module->bufNormQueue.erase(key); + break; + } + + if (!signal.is_wire()) { + module->bufNormQueue.insert(key); + break; + } + + Wire *w = signal.as_wire(); + if (w->driverCell != nullptr) { + pair other_key(w->driverCell, w->driverPort); + module->bufNormQueue.insert(other_key); + } + w->driverCell = this; + w->driverPort = portname; + + module->bufNormQueue.erase(key); + break; + } + conn_it->second = std::move(signal); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index ba01c6a1b..3e4c92af3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1066,6 +1066,9 @@ struct RTLIL::Design pool monitors; dict scratchpad; + bool flagBufferedNormalized = false; + void bufNormalize(bool enable=true); + int refcount_modules_; dict modules_; std::vector bindings_; @@ -1210,6 +1213,9 @@ public: std::vector ports; void fixup_ports(); + pool> bufNormQueue; + void bufNormalize(); + template void rewrite_sigspecs(T &functor); template void rewrite_sigspecs2(T &functor); void cloneInto(RTLIL::Module *new_mod) const; @@ -1525,6 +1531,9 @@ public: int width, start_offset, port_id; bool port_input, port_output, upto, is_signed; + RTLIL::Cell *driverCell = nullptr; + RTLIL::IdString driverPort; + #ifdef WITH_PYTHON static std::map *get_all_wires(void); #endif diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 4ca96d530..b3aed1b8e 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -83,11 +83,21 @@ struct BufnormPass : public Pass { log(" -conn\n"); log(" Create 'direct connections' instead of buffer cells.\n"); log("\n"); + log(" -nomode\n"); + log(" Do not automatically enter or leave 'buffered-normalized mode'.\n"); + log("\n"); + log("The 'bufnorm' command can also be used to just switch in and out of\n"); + log("'buffered-normalized mode' and run the low-level re-normalizer.\n"); + log("\n"); + log(" -update\n"); + log(" Enter 'buffered-normalized mode' and (re-)normalize.\n"); + log("\n"); + log(" -reset\n"); + log(" Leave 'buffered-normalized mode' without changing the netlist.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n"); - bool buf_mode = false; bool chain_mode = false; bool output_mode = false; @@ -97,66 +107,97 @@ struct BufnormPass : public Pass { bool nosticky_mode = false; bool alphasort_mode = false; bool noinit_mode = false; // FIXME: Actually move init attributes + bool nomode_mode = false; bool pos_mode = false; bool bits_mode = false; bool conn_mode = false; + bool update_mode = false; + bool reset_mode = false; + bool got_non_update_reset_opt = false; + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-buf") { buf_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-chain") { chain_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-output") { output_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-public") { public_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-nochain") { nochain_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-nokeep") { nokeep_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-flat") { nochain_mode = true; nokeep_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-nosticky") { nosticky_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-alphasort") { alphasort_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-noinit") { noinit_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-pos") { pos_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-bits") { bits_mode = true; + got_non_update_reset_opt = true; continue; } if (arg == "-conn") { conn_mode = true; + got_non_update_reset_opt = true; + continue; + } + if (arg == "-nomode") { + nomode_mode = true; + got_non_update_reset_opt = true; + continue; + } + if (arg == "-update") { + update_mode = true; + continue; + } + if (arg == "-reset") { + reset_mode = true; continue; } break; @@ -172,12 +213,38 @@ struct BufnormPass : public Pass { if (pos_mode && conn_mode) log_cmd_error("Options -pos and -conn are exclusive.\n"); + if (update_mode && reset_mode) + log_cmd_error("Options -update and -reset are exclusive.\n"); + + if (update_mode && got_non_update_reset_opt) + log_cmd_error("Option -update can't be mixed with other options.\n"); + + if (reset_mode && got_non_update_reset_opt) + log_cmd_error("Option -reset can't be mixed with other options.\n"); + + if (update_mode) { + design->bufNormalize(); + return; + } + + if (reset_mode) { + design->bufNormalize(false); + return; + } + + log_header(design, "Executing BUFNORM pass (convert to buffer-normalized form).\n"); + int count_removed_buffers = 0; int count_updated_buffers = 0; int count_kept_buffers = 0; int count_created_buffers = 0; int count_updated_cellports = 0; + if (!nomode_mode && (pos_mode || bits_mode || conn_mode)) { + if (design->selection().full_selection) + design->bufNormalize(false); + } + for (auto module : design->selected_modules()) { log("Buffer-normalizing module %s.\n", log_id(module)); @@ -432,6 +499,11 @@ struct BufnormPass : public Pass { log("Summary: removed %d, updated %d, kept %d, and created %d buffers, and updated %d cell ports.\n", count_removed_buffers, count_updated_buffers, count_kept_buffers, count_created_buffers, count_updated_cellports); + + if (!nomode_mode && !(pos_mode || bits_mode || conn_mode)) { + if (design->selection().full_selection) + design->bufNormalize(true); + } } } BufnormPass; From 865df26facfe26edc2238d1294d67277dbff7210 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 21 May 2024 13:08:40 +0200 Subject: [PATCH 232/342] Adjust buf-normalized mode --- backends/rtlil/rtlil_backend.cc | 26 ++++++++++------------ backends/rtlil/rtlil_backend.h | 6 +++--- kernel/celledges.cc | 2 +- kernel/rtlil.cc | 38 +++++++++++++++++++-------------- kernel/rtlil.h | 14 ++++++++++-- 5 files changed, 49 insertions(+), 37 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index e6f8daf96..ddc4769f6 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -118,16 +118,16 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo } } -void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d) +void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire) { for (auto &it : wire->attributes) { f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str()); dump_const(f, it.second); f << stringf("\n"); } - if (flag_d && wire->driverCell) { - f << stringf("%s" "driver %s %s\n", indent.c_str(), - wire->driverCell->name.c_str(), wire->driverPort.c_str()); + if (wire->driverCell_) { + f << stringf("%s" "# driver %s %s\n", indent.c_str(), + wire->driverCell()->name.c_str(), wire->driverPort().c_str()); } f << stringf("%s" "wire ", indent.c_str()); if (wire->width != 1) @@ -302,7 +302,7 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } -void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d) +void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { bool print_header = flag_m || design->selected_whole_module(module->name); bool print_body = !flag_n || !design->selected_whole_module(module->name); @@ -339,7 +339,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (!only_selected || design->selected(module, it)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", it, flag_d); + dump_wire(f, indent + " ", it); } for (auto it : module->memories) @@ -388,7 +388,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu f << stringf("%s" "end\n", indent.c_str()); } -void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d) +void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n) { int init_autoidx = autoidx; @@ -414,7 +414,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!only_selected || design->selected(module)) { if (only_selected) f << stringf("\n"); - dump_module(f, "", module, design, only_selected, flag_m, flag_n, flag_d); + dump_module(f, "", module, design, only_selected, flag_m, flag_n); } } @@ -460,7 +460,7 @@ struct RTLILBackend : public Backend { log("Output filename: %s\n", filename.c_str()); *f << stringf("# Generated by %s\n", yosys_version_str); - RTLIL_BACKEND::dump_design(*f, design, selected, true, false, false); + RTLIL_BACKEND::dump_design(*f, design, selected, true, false); } } RTLILBackend; @@ -510,7 +510,7 @@ struct DumpPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { std::string filename; - bool flag_m = false, flag_n = false, flag_d = false, append = false; + bool flag_m = false, flag_n = false, append = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -534,10 +534,6 @@ struct DumpPass : public Pass { flag_n = true; continue; } - if (arg == "-d") { - flag_d = true; - continue; - } break; } extra_args(args, argidx, design); @@ -559,7 +555,7 @@ struct DumpPass : public Pass { f = &buf; } - RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, flag_d); + RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n); if (!empty) { delete f; diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 21d79d8ec..35829729c 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -34,7 +34,7 @@ namespace RTLIL_BACKEND { void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true); void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true); - void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d = false); + void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire); void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory); void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell); void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs); @@ -42,8 +42,8 @@ namespace RTLIL_BACKEND { void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy); void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc); void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right); - void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false); - void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false); + void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false); + void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false); } YOSYS_NAMESPACE_END diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 0fbe17c56..bad7124d9 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool(); int a_width = GetSize(cell->getPort(ID::A)); int y_width = GetSize(cell->getPort(ID::Y)); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index eaba0fe31..2d3135378 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3575,10 +3575,12 @@ void RTLIL::Design::bufNormalize(bool enable) for (auto module : modules()) { module->bufNormQueue.clear(); for (auto wire : module->wires()) { - wire->driverCell = nullptr; - wire->driverPort = IdString(); + wire->driverCell_ = nullptr; + wire->driverPort_ = IdString(); } } + + flagBufferedNormalized = false; return; } @@ -3592,9 +3594,9 @@ void RTLIL::Design::bufNormalize(bool enable) continue; if (conn.second.is_wire()) { Wire *wire = conn.second.as_wire(); - log_assert(wire->driverCell == nullptr); - wire->driverCell = cell; - wire->driverPort = conn.first; + log_assert(wire->driverCell_ == nullptr); + wire->driverCell_ = cell; + wire->driverPort_ = conn.first; } else { pair key(cell, conn.first); module->bufNormQueue.insert(key); @@ -3614,7 +3616,7 @@ void RTLIL::Module::bufNormalize() if (!design->flagBufferedNormalized) return; - while (GetSize(bufNormQueue)) + while (GetSize(bufNormQueue) || !connections_.empty()) { pool> queue; bufNormQueue.swap(queue); @@ -3636,9 +3638,13 @@ void RTLIL::Module::bufNormalize() if (sig.is_wire()) { Wire *wire = sig.as_wire(); - log_assert(wire->driverCell == nullptr); - wire->driverCell = cell; - wire->driverPort = portname; + if (wire->driverCell_) { + log_error("Conflict between %s %s in module %s\n", + log_id(cell), log_id(wire->driverCell_), log_id(this)); + } + log_assert(wire->driverCell_ == nullptr); + wire->driverCell_ = cell; + wire->driverPort_ = portname; continue; } @@ -3688,9 +3694,9 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal if (conn_it->second.is_wire()) { Wire *w = conn_it->second.as_wire(); - if (w->driverCell == this && w->driverPort == portname) { - w->driverCell = nullptr; - w->driverPort = IdString(); + if (w->driverCell_ == this && w->driverPort_ == portname) { + w->driverCell_ = nullptr; + w->driverPort_ = IdString(); } } @@ -3705,12 +3711,12 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal } Wire *w = signal.as_wire(); - if (w->driverCell != nullptr) { - pair other_key(w->driverCell, w->driverPort); + if (w->driverCell_ != nullptr) { + pair other_key(w->driverCell_, w->driverPort_); module->bufNormQueue.insert(other_key); } - w->driverCell = this; - w->driverPort = portname; + w->driverCell_ = this; + w->driverPort_ = portname; module->bufNormQueue.erase(key); break; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 3e4c92af3..c49734cd0 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1510,6 +1510,10 @@ public: #endif }; +namespace RTLIL_BACKEND { +void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire); +} + struct RTLIL::Wire : public RTLIL::AttrObject { unsigned int hashidx_; @@ -1521,6 +1525,12 @@ protected: Wire(); ~Wire(); + friend struct RTLIL::Design; + friend struct RTLIL::Cell; + friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire); + RTLIL::Cell *driverCell_ = nullptr; + RTLIL::IdString driverPort_; + public: // do not simply copy wires Wire(RTLIL::Wire &other) = delete; @@ -1531,8 +1541,8 @@ public: int width, start_offset, port_id; bool port_input, port_output, upto, is_signed; - RTLIL::Cell *driverCell = nullptr; - RTLIL::IdString driverPort; + RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; }; + RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; }; #ifdef WITH_PYTHON static std::map *get_all_wires(void); From 38de01807e6cfc711903181f677bb3c07f1f13a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:12:36 +0200 Subject: [PATCH 233/342] Mark `bufnorm` experimental --- passes/techmap/bufnorm.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index b3aed1b8e..75060673e 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -24,7 +24,9 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct BufnormPass : public Pass { - BufnormPass() : Pass("bufnorm", "convert design into buffered-normalized form") { } + BufnormPass() : Pass("bufnorm", "(experimental) convert design into buffered-normalized form") { + experimental(); + } void help() override { log("\n"); From e13ace675e3536d41199d70cb10445fcfedbc63a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Sep 2024 14:42:53 +0200 Subject: [PATCH 234/342] dump: Update help after option removal --- backends/rtlil/rtlil_backend.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index ddc4769f6..434992cc7 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -497,9 +497,6 @@ struct DumpPass : public Pass { log(" -n\n"); log(" only dump the module headers if the entire module is selected\n"); log("\n"); - log(" -d\n"); - log(" include driver cell and port info on wires in dump format\n"); - log("\n"); log(" -o \n"); log(" write to the specified file.\n"); log("\n"); From eeffca947037ddba7efb834d6784dba1e8dfa5bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 17 Sep 2024 10:46:07 +0200 Subject: [PATCH 235/342] simlib: Add `$buf` disclaimer --- techlibs/common/simlib.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 5593cfe0e..60f98af28 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -91,7 +91,9 @@ endmodule //- //- $buf (A, Y) //- -//- A simple coarse-grain buffer cell type. +//- A simple coarse-grain buffer cell type for the experimental buffered-normalized +//- mode. Note this cell does't get removed by 'opt_clean' and is not recommended +//- for general use. //- module \$buf (A, Y); From 4cfdb7ab5031c40c5804612e5c84613c060b0977 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Sep 2024 20:42:55 +0200 Subject: [PATCH 236/342] Adjust operation naming in aigmap test --- tests/techmap/aigmap.ys | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys index 6f6cdd1f2..deec440e2 100644 --- a/tests/techmap/aigmap.ys +++ b/tests/techmap/aigmap.ys @@ -84,14 +84,14 @@ assign name``_y2 = op name``_a2; `BIOP(xnor, ~^, 3, 3, 3) `BIOP(logic_and, &&, 3, 3, 1) `BIOP(logic_or, ||, 3, 3, 1) -`BIOP(logic_eq, ==, 3, 3, 1) -`BIOP(logic_ne, !=, 3, 3, 1) -`BIOP(logic_lt, <, 3, 3, 1) -`BIOP(logic_le, <=, 3, 3, 1) -`BIOP(logic_gt, >, 3, 3, 1) -`BIOP(logic_ge, >=, 3, 3, 1) +`BIOP(eq, ==, 3, 3, 1) +`BIOP(ne, !=, 3, 3, 1) +`BIOP(lt, <, 3, 3, 1) +`BIOP(le, <=, 3, 3, 1) +`BIOP(gt, >, 3, 3, 1) +`BIOP(ge, >=, 3, 3, 1) `UNOP(pos, +, 3) -`UNOP(neg, ~, 3) +`UNOP(not, ~, 3) `UNOP_REDUCE(logic_not, !, 3) `UNOP_REDUCE(reduce_and, &, 3) `UNOP_REDUCE(reduce_or, |, 3) From fb26945a20a5d20585567f90a9d1eaad279f78be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 10 Sep 2024 20:53:23 +0200 Subject: [PATCH 237/342] Start an 'aiger2' backend --- backends/aiger2/Makefile.inc | 1 + backends/aiger2/aiger.cc | 593 +++++++++++++++++++++++++++++++++++ tests/various/aiger2.ys | 156 +++++++++ 3 files changed, 750 insertions(+) create mode 100644 backends/aiger2/Makefile.inc create mode 100644 backends/aiger2/aiger.cc create mode 100644 tests/various/aiger2.ys diff --git a/backends/aiger2/Makefile.inc b/backends/aiger2/Makefile.inc new file mode 100644 index 000000000..494b8d6c6 --- /dev/null +++ b/backends/aiger2/Makefile.inc @@ -0,0 +1 @@ +OBJS += backends/aiger2/aiger.o diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc new file mode 100644 index 000000000..64cde2de4 --- /dev/null +++ b/backends/aiger2/aiger.cc @@ -0,0 +1,593 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) Martin Povišer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// TODOs: +// - gracefully handling inout ports (an error message probably) + +#include "kernel/register.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa) + +#define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool) + +#define LOGIC_OPS ID($logic_and), ID($logic_or), ID($logic_not) + +#define GATE_OPS ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), \ + ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \ + ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_) + +// TODO +//#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) + +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS /*, ARITH_OPS*/ + +template +struct Index { + struct HierCursor; + struct ModuleInfo { + Module *module; + int len; + dict windices; + dict suboffsets; + + bool indexing = false; + bool indexed = false; + }; + + dict modules; + + int index_wires(ModuleInfo &info, RTLIL::Module *m) + { + int sum = 0; + for (auto w : m->wires()) { + info.windices[w] = sum; + sum += w->width; + } + return sum; + } + + int index_module(RTLIL::Module *m) + { + ModuleInfo &info = modules[m]; + + if (info.indexed) + return info.len; + + if (info.indexing && !info.indexed) + log_error("Hierarchy error\n"); + + info.module = m; + int pos = index_wires(info, m); + + for (auto cell : m->cells()) { + if (cell->type.in(KNOWN_OPS)) + continue; + + Module *submodule = m->design->module(cell->type); + if (!submodule || submodule->get_blackbox_attribute()) + log_error("Unsupported cell type: %s (%s in %s)\n", + log_id(cell->type), log_id(cell), log_id(m)); + info.suboffsets[cell] = pos; + pos += index_module(submodule); + } + + info.len = pos; + return info.len; + } + + Design *design; + Module *top; + ModuleInfo *top_minfo; + std::vector lits; + + Index(RTLIL::Module *top) + : design(top->design), top(top) + { + modules.reserve(top->design->modules().size()); + int nlits = index_module(top); + log_debug("allocating for %d literals\n", nlits); + lits.resize(nlits, Writer::empty_lit()); + top_minfo = &modules.at(top); + } + + bool const_folding = false; + + Lit AND(Lit a, Lit b) + { + if (const_folding) { + if (a == Writer::CONST_FALSE || b == Writer::CONST_FALSE) + return Writer::CONST_FALSE; + if (a == Writer::CONST_TRUE) + return b; + if (b == Writer::CONST_TRUE) + return a; + } + + return (static_cast(this))->emit_gate(a, b); + } + + Lit NOT(Lit lit) + { + return Writer::negate(lit); + } + + Lit OR(Lit a, Lit b) + { + return NOT(AND(NOT(a), NOT(b))); + } + + Lit MUX(Lit a, Lit b, Lit s) + { + if (const_folding) { + if (a == b) + return a; + if (s == Writer::CONST_FALSE) + return a; + if (s == Writer::CONST_TRUE) + return b; + } + + return OR(AND(a, NOT(s)), AND(b, s)); + } + + Lit XOR(Lit a, Lit b) + { + return OR(AND(a, NOT(b)), AND(NOT(a), b)); + } + + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) + { + if (cell->type.in(REDUCE_OPS, LOGIC_OPS) && obit != 0) { + return Writer::CONST_FALSE; + } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { + SigSpec inport = cell->getPort(ID::A); + + log_assert(inport.size() > 0); // TODO + + Lit acc = visit(cursor, inport[0]); + for (int i = 1; i < inport.size(); i++) { + Lit l = visit(cursor, inport[i]); + if (cell->type == ID($reduce_and)) { + acc = AND(acc, l); + } else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) { + acc = OR(acc, l); + } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { + acc = XOR(acc, l); + } + } + + if (!cell->type.in(ID($reduce_xnor), ID($logic_not))) + return acc; + else + return NOT(acc); + } else if (cell->type.in(ID($logic_and), ID($logic_or))) { + SigSpec aport = cell->getPort(ID::A); + SigSpec bport = cell->getPort(ID::B); + + log_assert(aport.size() > 0 && bport.size() > 0); // TODO + + Lit a = visit(cursor, aport[0]); + for (int i = 1; i < aport.size(); i++) { + Lit l = visit(cursor, aport[i]); + a = OR(a, l); + } + + Lit b = visit(cursor, bport[0]); + for (int i = 1; i < bport.size(); i++) { + Lit l = visit(cursor, bport[i]); + b = OR(b, l); + } + + if (cell->type == ID($logic_and)) + return AND(a, b); + else if (cell->type == ID($logic_or)) + return OR(a, b); + else + log_abort(); + } else if (cell->type.in(BITWISE_OPS, GATE_OPS)) { + SigSpec aport = cell->getPort(ID::A); + Lit a; + if (obit < aport.size()) { + a = visit(cursor, aport[obit]); + } else { + if (cell->getParam(ID::A_SIGNED).as_bool()) + a = visit(cursor, aport.msb()); + else + a = Writer::CONST_FALSE; + } + + if (cell->type.in(ID($buf), ID($_BUF_))) { + return a; + } else if (cell->type.in(ID($not), ID($_NOT_))) { + return NOT(a); + } else { + SigSpec bport = cell->getPort(ID::B); + Lit b; + if (obit < bport.size()) { + b = visit(cursor, bport[obit]); + } else { + if (cell->getParam(ID::B_SIGNED).as_bool()) + b = visit(cursor, bport.msb()); + else + b = Writer::CONST_FALSE; + } + + if (cell->type.in(ID($and), ID($_AND_))) { + return AND(a, b); + } else if (cell->type.in(ID($_NAND_))) { + return NOT(AND(a, b)); + } else if (cell->type.in(ID($or), ID($_OR_))) { + return OR(a, b); + } else if (cell->type.in(ID($_NOR_))) { + return NOT(OR(a, b)); + } else if (cell->type.in(ID($xor), ID($_XOR_))) { + return XOR(a, b); + } else if (cell->type.in(ID($xnor), ID($_XNOR_))) { + return NOT(XOR(a, b)); + } else if (cell->type.in(ID($_ANDNOT_))) { + return AND(a, NOT(b)); + } else if (cell->type.in(ID($_ORNOT_))) { + return OR(a, NOT(b)); + } else if (cell->type.in(ID($mux), ID($_MUX_))) { + Lit s = visit(cursor, cell->getPort(ID::S)); + return MUX(a, b, s); + } else if (cell->type.in(ID($_NMUX_))) { + Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + return NOT(MUX(a, b, s)); + } else if (cell->type.in(ID($fa))) { + Lit c = visit(cursor, cell->getPort(ID::C)[obit]); + Lit ab = XOR(a, b); + if (oport == ID::Y) { + return XOR(ab, c); + } else /* oport == ID::X */ { + return OR(AND(a, b), AND(c, ab)); + } + } else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { + Lit c, d; + + c = visit(cursor, cell->getPort(ID::C)[obit]); + if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_))) + d = visit(cursor, cell->getPort(ID::D)[obit]); + else + d = cell->type == ID($_AOI3_) ? 1 : 0; + + if (/* aoi */ cell->type.in(ID($_AOI3_), ID($_AOI4_))) + return NOT(OR(AND(a, b), AND(c, d))); + else + return NOT(AND(OR(a, b), OR(c, d))); + } else { + log_abort(); + } + } + } else { + log_abort(); + } + } + + struct HierCursor { + typedef std::pair Level; + std::vector levels; + int instance_offset = 0; + + HierCursor(ModuleInfo &top) + { + levels.push_back(Level(top, nullptr)); + } + + ModuleInfo ¤t_minfo() + { + log_assert(!levels.empty()); + return levels.back().first; + } + + int bitwire_index(SigBit bit) + { + log_assert(bit.wire != nullptr); + return instance_offset + current_minfo().windices[bit.wire] + bit.offset; + } + + Cell *exit() + { + log_assert(levels.size() > 1); + Cell *instance = levels.back().second; + + levels.pop_back(); + instance_offset -= current_minfo().suboffsets.at(instance); + + // return the instance we just exited + return instance; + } + + Module *enter(Index &index, Cell *cell) + { + Design *design = index.design; + auto &minfo = current_minfo(); + log_assert(minfo.suboffsets.count(cell)); + Module *def = design->module(cell->type); + log_assert(def); + levels.push_back(Level(index.modules.at(def), cell)); + instance_offset += minfo.suboffsets.at(cell); + + // return the module definition we just entered + return def; + } + }; + + int visit(HierCursor &cursor, SigBit bit) + { + if (!bit.wire) { + if (bit == State::S1) + return Writer::CONST_TRUE; + else if (bit == State::S0) + return Writer::CONST_FALSE; + else + log_error("Unhandled state %s\n", log_signal(bit)); + } + + int idx = cursor.bitwire_index(bit); + if (lits[idx] != Writer::empty_lit()) { + // literal already assigned + return lits[idx]; + } + + Lit ret; + if (!bit.wire->port_input) { + // an output of a cell + Cell *driver = bit.wire->driverCell(); + + if (driver->type.in(KNOWN_OPS)) { + ret = impl_op(cursor, driver, bit.wire->driverPort(), bit.offset); + } else { + Module *def = cursor.enter(*this, driver); + { + IdString portname = bit.wire->driverPort(); + Wire *w = def->wire(portname); + if (!w) + log_error("Output port %s on instance %s of %s doesn't exist\n", + log_id(portname), log_id(driver), log_id(def)); + if (bit.offset >= w->width) + log_error("Bit position %d of output port %s on instance %s of %s is out of range (port has width %d)\n", + bit.offset, log_id(portname), log_id(driver), log_id(def), w->width); + ret = visit(cursor, SigBit(w, bit.offset)); + } + cursor.exit(); + } + + } else { + // a module input: we cannot be the top module, otherwise + // the branch for pre-existing literals would have been taken + log_assert(cursor.levels.size() > 1); + + // step into the upper module + Cell *instance = cursor.exit(); + { + IdString portname = bit.wire->name; + if (!instance->hasPort(portname)) + log_error("Input port %s on instance %s of %s unconnected\n", + log_id(portname), log_id(instance), log_id(instance->type)); + auto &port = instance->getPort(portname); + if (bit.offset >= port.size()) + log_error("Bit %d of input port %s on instance %s of %s unconnected\n", + bit.offset, log_id(portname), log_id(instance), log_id(instance->type)); + ret = visit(cursor, port[bit.offset]); + } + cursor.enter(*this, instance); + } + + lits[idx] = ret; + return ret; + } + + void set_top_port(SigBit bit, Lit lit) + { + log_assert(bit.wire); + log_assert(bit.wire->module == top); + log_assert(bit.wire->port_input); + + lits[top_minfo->windices[bit.wire] + bit.offset] = lit; + } + + Lit get_top_port(SigBit bit) + { + HierCursor cursor(*top_minfo); + Lit ret = visit(cursor, bit); + log_assert(cursor.levels.size() == 1); + log_assert(cursor.instance_offset == 0); + return ret; + } +}; + +struct AigerWriter : Index { + typedef unsigned int Lit; + + const static Lit CONST_FALSE = 0; + const static Lit CONST_TRUE = 1; + + // for some reason having a 'const static int EMPTY_LIT' + // led to linkage errors + static Lit empty_lit() + { + return 0x80000000; + } + + static Lit negate(Lit lit) { + return lit ^ 1; + } + + std::ostream *f; + Lit lit_counter; + int ninputs, nlatches, noutputs, nands; + + void encode(int delta) + { + log_assert(delta >= 0); + unsigned int x = delta; + while (x & ~0x7f) { + f->put((x & 0x7f) | 0x80); + x = x >> 7; + } + f->put(x); + } + + Lit emit_gate(Lit a, Lit b) + { + Lit out = lit_counter; + nands++; + lit_counter += 2; + + if (a < b) std::swap(a, b); + encode(out - a); + encode(a - b); + return out; + } + + void reset_counters() + { + lit_counter = 2; + ninputs = nlatches = noutputs = nands = 0; + } + + void write_header() { + log_assert(lit_counter == (ninputs + nlatches + nands) * 2 + 2); + + char buf[128]; + snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", + ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands); + f->seekp(0); + f->write(buf, strlen(buf)); + } + + void write(std::ostream *f) { + reset_counters(); + + // populate inputs + std::vector inputs; + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) { + set_top_port(SigBit(w, i), lit_counter); + inputs.push_back(SigBit(w, i)); + lit_counter += 2; + ninputs++; + } + + this->f = f; + // start with the header + write_header(); + // insert padding where output literals will go (once known) + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) { + (void) bit; + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); + f->write(buf, strlen(buf)); + noutputs++; + } + } + auto data_start = f->tellp(); + + // now the guts + std::vector> outputs; + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + outputs.push_back({bit, get_top_port(bit)}); + } + auto data_end = f->tellp(); + + // revisit header and the list of outputs + write_header(); + for (auto pair : outputs) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", pair.second); + f->write(buf, strlen(buf)); + } + // double check we arrived at the same offset for the + // main data section + log_assert(data_start == f->tellp()); + + f->seekp(data_end); + int i = 0; + for (auto pair : outputs) { + if (pair.first.is_wire()) { + char buf[32]; + snprintf(buf, sizeof(buf) - 1, "o%d ", i); + f->write(buf, strlen(buf)); + std::string name = RTLIL::unescape_id(pair.first.wire->name); + f->write(name.data(), name.size()); + f->put('\n'); + } + i++; + } + i = 0; + for (auto bit : inputs) { + if (bit.is_wire()) { + char buf[32]; + snprintf(buf, sizeof(buf) - 1, "i%d ", i); + f->write(buf, strlen(buf)); + std::string name = RTLIL::unescape_id(bit.wire->name); + f->write(name.data(), name.size()); + f->put('\n'); + } + i++; + } + } + + AigerWriter(RTLIL::Module *top) + : Index(top) {} +}; + +struct Aiger2Backend : Backend { + Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") + { + experimental(); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing AIGER2 backend.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + break; + } + extra_args(f, filename, args, argidx); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + design->bufNormalize(true); + AigerWriter writer(top); + writer.write(f); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} Aiger2Backend; + +PRIVATE_NAMESPACE_END diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys new file mode 100644 index 000000000..61e6d275a --- /dev/null +++ b/tests/various/aiger2.ys @@ -0,0 +1,156 @@ +read_verilog -icells < Date: Wed, 11 Sep 2024 11:01:38 +0200 Subject: [PATCH 238/342] aiger2: Support `$pos` --- backends/aiger2/aiger.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 64cde2de4..89a23ff3f 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -38,7 +38,7 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos) /*, ARITH_OPS*/ template struct Index { @@ -203,7 +203,7 @@ struct Index { return OR(a, b); else log_abort(); - } else if (cell->type.in(BITWISE_OPS, GATE_OPS)) { + } else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) { SigSpec aport = cell->getPort(ID::A); Lit a; if (obit < aport.size()) { @@ -215,7 +215,7 @@ struct Index { a = Writer::CONST_FALSE; } - if (cell->type.in(ID($buf), ID($_BUF_))) { + if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) { return a; } else if (cell->type.in(ID($not), ID($_NOT_))) { return NOT(a); From 5671c101731c58c5285d2493527911fde67ec25b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:02:40 +0200 Subject: [PATCH 239/342] aiger2: Add strashing option --- backends/aiger2/aiger.cc | 41 +++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 89a23ff3f..533abc004 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -99,9 +99,15 @@ struct Index { ModuleInfo *top_minfo; std::vector lits; - Index(RTLIL::Module *top) - : design(top->design), top(top) + Index() { + } + + void setup(RTLIL::Module *top) + { + design = top->design; + this->top = top; + modules.reserve(top->design->modules().size()); int nlits = index_module(top); log_debug("allocating for %d literals\n", nlits); @@ -109,7 +115,9 @@ struct Index { top_minfo = &modules.at(top); } - bool const_folding = false; + bool const_folding = true; + bool strashing = false; + dict, int> cache; Lit AND(Lit a, Lit b) { @@ -122,7 +130,20 @@ struct Index { return a; } - return (static_cast(this))->emit_gate(a, b); + if (!strashing) { + return (static_cast(this))->emit_gate(a, b); + } else { + if (a < b) std::swap(a, b); + auto pair = std::make_pair(a, b); + + if (!cache.count(pair)) { + Lit nl = (static_cast(this))->emit_gate(a, b); + cache[pair] = nl; + return nl; + } else { + return cache.at(pair); + } + } } Lit NOT(Lit lit) @@ -552,9 +573,6 @@ struct AigerWriter : Index { i++; } } - - AigerWriter(RTLIL::Module *top) - : Index(top) {} }; struct Aiger2Backend : Backend { @@ -568,8 +586,13 @@ struct Aiger2Backend : Backend { log_header(design, "Executing AIGER2 backend.\n"); size_t argidx; + AigerWriter writer; + writer.const_folding = true; for (argidx = 1; argidx < args.size(); argidx++) { - break; + if (args[argidx] == "-strash") + writer.strashing = true; + else + break; } extra_args(f, filename, args, argidx); @@ -579,7 +602,7 @@ struct Aiger2Backend : Backend { log_cmd_error("No top module selected\n"); design->bufNormalize(true); - AigerWriter writer(top); + writer.setup(top); writer.write(f); // we are leaving the sacred land, un-bufnormalize From de8a2fb936e25eb54074595b129f02fc14144fe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:03:14 +0200 Subject: [PATCH 240/342] aiger2: Fix duplicate symbols on multibit ports --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 533abc004..a49b5bf1e 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -550,7 +550,7 @@ struct AigerWriter : Index { f->seekp(data_end); int i = 0; for (auto pair : outputs) { - if (pair.first.is_wire()) { + if (SigSpec(pair.first).is_wire()) { char buf[32]; snprintf(buf, sizeof(buf) - 1, "o%d ", i); f->write(buf, strlen(buf)); @@ -562,7 +562,7 @@ struct AigerWriter : Index { } i = 0; for (auto bit : inputs) { - if (bit.is_wire()) { + if (SigSpec(bit).is_wire()) { char buf[32]; snprintf(buf, sizeof(buf) - 1, "i%d ", i); f->write(buf, strlen(buf)); From e59387e5a9538ee32fdd3f8554e350d506b7b48b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 11:10:43 +0200 Subject: [PATCH 241/342] aiger2: Add `aigsize` as a second user of index --- backends/aiger2/aiger.cc | 64 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index a49b5bf1e..075bc129d 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -613,4 +613,68 @@ struct Aiger2Backend : Backend { } } Aiger2Backend; +struct AIGCounter : Index { + typedef int Lit; + const static Lit CONST_FALSE = -1; + const static Lit CONST_TRUE = 1; + static Lit empty_lit() { return 0; } + static Lit negate(Lit lit) { return -lit; } + int nvars = 1; + int ngates = 0; + + Lit emit_gate([[maybe_unused]] Lit a, [[maybe_unused]] Lit b) + { + ngates++; + return ++nvars; + } + + void count() { + // populate inputs + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) + set_top_port(SigBit(w, i), ++nvars); + + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + (void) get_top_port(bit); + } + } +}; + +struct AigsizePass : Pass { + AigsizePass() : Pass("aigsize", "estimate AIG size for design") {} + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); + + size_t argidx; + AIGCounter counter; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-strash") + counter.strashing = true; + else + break; + } + extra_args(args, argidx, design); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + design->bufNormalize(true); + counter.setup(top); + counter.count(); + log("Counted %d gates\n", counter.ngates); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} AigsizePass; + PRIVATE_NAMESPACE_END From d7128cb78787a6a5299c1c1c126ec673e8d440e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:08:03 +0200 Subject: [PATCH 242/342] aiger2: Use shorthands --- backends/aiger2/aiger.cc | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 075bc129d..873a44129 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,6 +42,9 @@ PRIVATE_NAMESPACE_BEGIN template struct Index { + static constexpr Lit CFALSE = Writer::CONST_FALSE; + static constexpr Lit CTRUE = Writer::CONST_TRUE; + struct HierCursor; struct ModuleInfo { Module *module; @@ -122,11 +125,11 @@ struct Index { Lit AND(Lit a, Lit b) { if (const_folding) { - if (a == Writer::CONST_FALSE || b == Writer::CONST_FALSE) - return Writer::CONST_FALSE; - if (a == Writer::CONST_TRUE) + if (a == CFALSE || b == CFALSE) + return CFALSE; + if (a == CTRUE) return b; - if (b == Writer::CONST_TRUE) + if (b == CTRUE) return a; } @@ -161,9 +164,9 @@ struct Index { if (const_folding) { if (a == b) return a; - if (s == Writer::CONST_FALSE) + if (s == CFALSE) return a; - if (s == Writer::CONST_TRUE) + if (s == CTRUE) return b; } @@ -233,7 +236,7 @@ struct Index { if (cell->getParam(ID::A_SIGNED).as_bool()) a = visit(cursor, aport.msb()); else - a = Writer::CONST_FALSE; + a = CFALSE; } if (cell->type.in(ID($buf), ID($pos), ID($_BUF_))) { @@ -249,7 +252,7 @@ struct Index { if (cell->getParam(ID::B_SIGNED).as_bool()) b = visit(cursor, bport.msb()); else - b = Writer::CONST_FALSE; + b = CFALSE; } if (cell->type.in(ID($and), ID($_AND_))) { @@ -357,9 +360,9 @@ struct Index { { if (!bit.wire) { if (bit == State::S1) - return Writer::CONST_TRUE; + return CTRUE; else if (bit == State::S0) - return Writer::CONST_FALSE; + return CFALSE; else log_error("Unhandled state %s\n", log_signal(bit)); } From 8e29675a23539c958b2024fbc00021708a3dcdb3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:08:41 +0200 Subject: [PATCH 243/342] aiger2: Support `$bwmux`, comparison operators --- backends/aiger2/aiger.cc | 69 ++++++++++++++++++++++++++++++++++++---- tests/various/aiger2.ys | 15 +++++++-- 2 files changed, 76 insertions(+), 8 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 873a44129..bc22dac94 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa) +#define BITWISE_OPS ID($buf), ID($not), ID($mux), ID($and), ID($or), ID($xor), ID($xnor), ID($fa), \ + ID($bwmux) #define REDUCE_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool) @@ -35,10 +36,12 @@ PRIVATE_NAMESPACE_BEGIN ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_), \ ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_) -// TODO -//#define ARITH_OPS ID($add), ID($sub), ID($lt), ID($le), ID($ge), ID($gt), ID($neg) +#define CMP_OPS ID($eq), ID($ne), ID($lt), ID($le), ID($ge), ID($gt) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos) /*, ARITH_OPS*/ +// TODO +//#define ARITH_OPS ID($add), ID($sub), ID($neg) + +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS /*, ARITH_OPS*/ template struct Index { @@ -178,10 +181,61 @@ struct Index { return OR(AND(a, NOT(b)), AND(NOT(a), b)); } + Lit XNOR(Lit a, Lit b) + { + return NOT(OR(AND(a, NOT(b)), AND(NOT(a), b))); + } + + Lit CARRY(Lit a, Lit b, Lit c) + { + if (const_folding) { + if (c == CTRUE) { + return OR(a, b); + } else if (c == CFALSE) { + return AND(a, b); + } + } + return OR(AND(a, b), AND(c, OR(a, b))); + } + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) { - if (cell->type.in(REDUCE_OPS, LOGIC_OPS) && obit != 0) { - return Writer::CONST_FALSE; + if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { + return CFALSE; + } else if (cell->type.in(CMP_OPS)) { + SigSpec aport = cell->getPort(ID::A); + bool asigned = cell->getParam(ID::A_SIGNED).as_bool(); + SigSpec bport = cell->getPort(ID::B); + bool bsigned = cell->getParam(ID::B_SIGNED).as_bool(); + + int width = std::max(aport.size(), bport.size()) + 1; + aport.extend_u0(width, asigned); + bport.extend_u0(width, bsigned); + + if (cell->type.in(ID($eq), ID($ne))) { + int carry = CTRUE; + for (int i = 0; i < width; i++) { + Lit a = visit(cursor, aport[i]); + Lit b = visit(cursor, bport[i]); + carry = AND(carry, XNOR(a, b)); + } + return (cell->type == ID($eq)) ? carry : /* $ne */ NOT(carry); + } else if (cell->type.in(ID($lt), ID($le), ID($gt), ID($ge))) { + if (cell->type.in(ID($gt), ID($ge))) + std::swap(aport, bport); + int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE; + Lit a, b; + // TODO: this might not be the most economic structure; revisit at a later date + for (int i = 0; i < width; i++) { + a = visit(cursor, aport[i]); + b = visit(cursor, bport[i]); + if (i != width - 1) + carry = CARRY(a, NOT(b), carry); + } + return XOR(carry, XNOR(a, b)); + } else { + log_abort(); + } } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { SigSpec inport = cell->getPort(ID::A); @@ -274,6 +328,9 @@ struct Index { } else if (cell->type.in(ID($mux), ID($_MUX_))) { Lit s = visit(cursor, cell->getPort(ID::S)); return MUX(a, b, s); + } else if (cell->type.in(ID($bwmux))) { + Lit s = visit(cursor, cell->getPort(ID::S)[obit]); + return MUX(a, b, s); } else if (cell->type.in(ID($_NMUX_))) { Lit s = visit(cursor, cell->getPort(ID::S)[obit]); return NOT(MUX(a, b, s)); diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 61e6d275a..5d8c6e848 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -83,6 +83,12 @@ assign name``_y2 = op name``_a2; `BIOP(xnor, ~^, 3, 3, 3) `BIOP(logic_and, &&, 4, 3, 1) `BIOP(logic_or, ||, 3, 3, 2) +`BIOP(eq, ==, 3, 3, 1) +`BIOP(ne, !=, 3, 3, 1) +`BIOP(lt, <, 3, 3, 1) +`BIOP(le, <=, 3, 3, 1) +`BIOP(gt, >, 3, 3, 1) +`BIOP(ge, >=, 3, 3, 1) `UNOP(not, ~, 3) `UNOP_REDUCE(logic_not, !, 3) `UNOP_REDUCE(reduce_and, &, 3) @@ -97,6 +103,11 @@ wire [1:0] fa_a, fa_b, fa_c, fa_x, fa_y; \$fa #( .WIDTH(2) ) fa(.A(fa_a), .B(fa_b), .C(fa_c), .X(fa_x), .Y(fa_y)); + +wire [1:0] bwmux_a, bwmux_b, bwmux_s, bwmux_y; +\$bwmux #( + .WIDTH(2) +) bwmux(.A(bwmux_a), .B(bwmux_b), .S(bwmux_s), .Y(bwmux_y)); endmodule EOF @@ -110,8 +121,8 @@ select -clear delete test read_aiger -module_name test aiger2_ops.aig select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D -miter -equiv -flatten gold test miter -sat -verify -prove trigger 0 miter +miter -equiv -make_outcmp -flatten gold test miter +sat -verify -show-ports -prove trigger 0 miter design -reset read_verilog -icells < Date: Wed, 11 Sep 2024 21:08:57 +0200 Subject: [PATCH 244/342] aiger2: Fix literal typing --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index bc22dac94..0c787f11d 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -413,7 +413,7 @@ struct Index { } }; - int visit(HierCursor &cursor, SigBit bit) + Lit visit(HierCursor &cursor, SigBit bit) { if (!bit.wire) { if (bit == State::S1) From dbc937b2a7482d243b16c5de1f508eee71b19a59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:09:28 +0200 Subject: [PATCH 245/342] aiger2: Describe supported cells in help --- backends/aiger2/aiger.cc | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0c787f11d..34b9eb324 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -21,6 +21,7 @@ // - gracefully handling inout ports (an error message probably) #include "kernel/register.h" +#include "kernel/celltypes.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -641,7 +642,51 @@ struct Aiger2Backend : Backend { experimental(); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_aiger2 [options] [filename]\n"); + log("\n"); + log("Write the current design to an AIGER file.\n"); + log("\n"); + log("This command is able to ingest all combinational cells except for:\n"); + log("\n"); + pool supported = {KNOWN_OPS}; + CellTypes ct; + ct.setup_internals_eval(); + log(" "); + int col = 0; + for (auto pair : ct.cell_types) + if (!supported.count(pair.first)) { + if (col + pair.first.size() + 2 > 72) { + log("\n "); + col = 0; + } + col += pair.first.size() + 2; + log("%s, ", log_id(pair.first)); + } + log("\n"); + log("\n"); + log("And all combinational gates except for:\n"); + log("\n"); + CellTypes ct2; + ct2.setup_stdcells(); + log(" "); + col = 0; + for (auto pair : ct2.cell_types) + if (!supported.count(pair.first)) { + if (col + pair.first.size() + 2 > 72) { + log("\n "); + col = 0; + } + col += pair.first.size() + 2; + log("%s, ", log_id(pair.first)); + } + log("\n"); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override { log_header(design, "Executing AIGER2 backend.\n"); From 9db1ca83fc80a6ffc6bab52cc70924304ed54c6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 11 Sep 2024 21:15:17 +0200 Subject: [PATCH 246/342] aiger2: Drop `empty_lit()` as a function --- backends/aiger2/aiger.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 34b9eb324..d300827d3 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -118,7 +118,7 @@ struct Index { modules.reserve(top->design->modules().size()); int nlits = index_module(top); log_debug("allocating for %d literals\n", nlits); - lits.resize(nlits, Writer::empty_lit()); + lits.resize(nlits, Writer::EMPTY_LIT); top_minfo = &modules.at(top); } @@ -426,7 +426,7 @@ struct Index { } int idx = cursor.bitwire_index(bit); - if (lits[idx] != Writer::empty_lit()) { + if (lits[idx] != Writer::EMPTY_LIT) { // literal already assigned return lits[idx]; } @@ -503,13 +503,7 @@ struct AigerWriter : Index { const static Lit CONST_FALSE = 0; const static Lit CONST_TRUE = 1; - - // for some reason having a 'const static int EMPTY_LIT' - // led to linkage errors - static Lit empty_lit() - { - return 0x80000000; - } + const static constexpr Lit EMPTY_LIT = std::numeric_limits::max(); static Lit negate(Lit lit) { return lit ^ 1; @@ -722,7 +716,7 @@ struct AIGCounter : Index { typedef int Lit; const static Lit CONST_FALSE = -1; const static Lit CONST_TRUE = 1; - static Lit empty_lit() { return 0; } + const static constexpr Lit EMPTY_LIT = 0; static Lit negate(Lit lit) { return -lit; } int nvars = 1; int ngates = 0; From 4d581a97d6f0f3e545bcdaa9462b4276fab99fa3 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 18 Sep 2024 00:19:41 +0000 Subject: [PATCH 247/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 77cdce22c..62b4ed459 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+126 +YOSYS_VER := 0.45+139 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 4976abb867c5e1dc0474975c46c966b238c5ce4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:16:15 +0200 Subject: [PATCH 248/342] read_liberty: Optionally import unit delay arcs --- frontends/liberty/liberty.cc | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 16fed54f2..e183cbf10 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -465,6 +465,9 @@ struct LibertyFrontend : public Frontend { log(" -setattr \n"); log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); + log(" -unit_delay\n"); + log(" import combinational timing arcs under the unit delay model\n"); + log("\n"); } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -475,6 +478,7 @@ struct LibertyFrontend : public Frontend { bool flag_ignore_miss_func = false; bool flag_ignore_miss_dir = false; bool flag_ignore_miss_data_latch = false; + bool flag_unit_delay = false; std::vector attributes; size_t argidx; @@ -514,6 +518,10 @@ struct LibertyFrontend : public Frontend { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } + if (arg == "-unit_delay") { + flag_unit_delay = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -652,6 +660,7 @@ struct LibertyFrontend : public Frontend { continue; RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0))); + log_assert(wire); if (dir && dir->value == "inout") { wire->port_input = true; @@ -690,6 +699,43 @@ struct LibertyFrontend : public Frontend { } module->connect(RTLIL::SigSig(wire, out_sig)); } + + if (flag_unit_delay) { + pool done; + + for (auto timing : node->children) + if (timing->id == "timing" && timing->args.empty()) { + auto type = timing->find("timing_type"); + auto related_pin = timing->find("related_pin"); + if (!type || type->value != "combinational" || !related_pin) + continue; + + Wire *related = module->wire(RTLIL::escape_id(related_pin->value)); + if (!related) + log_error("Failed to find related pin %s for timing of pin %s on %s\n", + related_pin->value.c_str(), log_id(wire), log_id(module)); + + if (done.count(related)) + continue; + + RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2)); + spec->setParam(ID::SRC_WIDTH, 1); + spec->setParam(ID::DST_WIDTH, 1); + spec->setParam(ID::T_FALL_MAX, 1000); + spec->setParam(ID::T_FALL_TYP, 1000); + spec->setParam(ID::T_FALL_MIN, 1000); + spec->setParam(ID::T_RISE_MAX, 1000); + spec->setParam(ID::T_RISE_TYP, 1000); + spec->setParam(ID::T_RISE_MIN, 1000); + spec->setParam(ID::SRC_DST_POL, false); + spec->setParam(ID::SRC_DST_PEN, false); + spec->setParam(ID::FULL, false); + spec->setPort(ID::EN, Const(1, 1)); + spec->setPort(ID::SRC, related); + spec->setPort(ID::DST, wire); + done.insert(related); + } + } } } From 31476e89b6524069b5ebd75e9e80700afdc58f3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:09:47 +0200 Subject: [PATCH 249/342] tests: Avoid temporary script file --- tests/liberty/.gitignore | 1 - tests/liberty/run-test.sh | 5 +---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore index bf5ba57dc..8763aaac5 100644 --- a/tests/liberty/.gitignore +++ b/tests/liberty/.gitignore @@ -1,4 +1,3 @@ *.log -test.ys *.filtered *.verilogsim diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 07d2cce1c..771bb69f7 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -3,10 +3,7 @@ set -e for x in *.lib; do echo "Testing on $x.." - echo "read_verilog small.v" > test.ys - echo "synth -top small" >> test.ys - echo "dfflibmap -info -liberty ${x}" >> test.ys - ../../yosys -ql ${x%.lib}.log -s test.ys + ../../yosys -p "read_verilog small.v; synth -top small; dfflibmap -info -liberty ${x}" -ql ${x%.lib}.log ../../yosys-filterlib - $x 2>/dev/null > $x.filtered ../../yosys-filterlib -verilogsim $x > $x.verilogsim diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok From d5756eb9be6de45bc108fe5c1c5557491f4e96e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:14:52 +0200 Subject: [PATCH 250/342] tests: Add trivial liberty -unit_delay test --- tests/liberty/run-test.sh | 5 +++++ tests/liberty/unit_delay.ys | 3 +++ 2 files changed, 8 insertions(+) create mode 100644 tests/liberty/unit_delay.ys diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh index 771bb69f7..ff5b20d74 100755 --- a/tests/liberty/run-test.sh +++ b/tests/liberty/run-test.sh @@ -8,3 +8,8 @@ for x in *.lib; do ../../yosys-filterlib -verilogsim $x > $x.verilogsim diff $x.filtered $x.filtered.ok && diff $x.verilogsim $x.verilogsim.ok done + +for x in *.ys; do + echo "Running $x.." + ../../yosys -q -s $x -l ${x%.ys}.log +done diff --git a/tests/liberty/unit_delay.ys b/tests/liberty/unit_delay.ys new file mode 100644 index 000000000..8dd409183 --- /dev/null +++ b/tests/liberty/unit_delay.ys @@ -0,0 +1,3 @@ +# Nothing gets imported: the file lacks timing data +read_liberty -wb -unit_delay normal.lib +select -assert-none =*/t:$specify* From 6c1fa45995f690ba1c8f8412ab09d938f83d9130 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Sep 2024 17:20:34 +0200 Subject: [PATCH 251/342] aiger2: Ingest `$pmux` --- backends/aiger2/aiger.cc | 41 +++++++++++++++++++++++++++++++++++++++- tests/various/aiger2.ys | 28 +++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index d300827d3..c0b9a0d7a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,7 +42,7 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, ID($pmux) /*, ARITH_OPS*/ template struct Index { @@ -199,6 +199,28 @@ struct Index { return OR(AND(a, b), AND(c, OR(a, b))); } + Lit REDUCE(std::vector lits, bool op_xor=false) + { + std::vector next; + while (lits.size() > 1) { + next.clear(); + for (int i = 0; i < lits.size(); i += 2) { + if (i + 1 >= lits.size()) { + next.push_back(lits[i]); + } else { + Lit a = lits[i], b = lits[i + 1]; + next.push_back(op_xor ? XOR(a, b) : AND(a, b)); + } + } + next.swap(lits); + } + + if (lits.empty()) + return op_xor ? CFALSE : CTRUE; + else + return lits.front(); + } + Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) { if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { @@ -360,6 +382,23 @@ struct Index { log_abort(); } } + } else if (cell->type == ID($pmux)) { + SigSpec aport = cell->getPort(ID::A); + SigSpec bport = cell->getPort(ID::B); + SigSpec sport = cell->getPort(ID::S); + int width = aport.size(); + + Lit a = visit(cursor, aport[obit]); + + std::vector bar, sels; + for (int i = 0; i < sport.size(); i++) { + Lit s = visit(cursor, sport[i]); + Lit b = visit(cursor, bport[width * i + obit]); + bar.push_back(NOT(AND(s, b))); + sels.push_back(NOT(s)); + } + + return OR(AND(REDUCE(sels), a), NOT(REDUCE(bar))); } else { log_abort(); } diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 5d8c6e848..0efb5dd76 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -165,3 +165,31 @@ read_aiger -module_name test aiger2_ops.aig select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D miter -equiv -flatten gold test miter sat -verify -prove trigger 0 miter + +design -reset +read_verilog -icells < Date: Mon, 16 Sep 2024 17:25:17 +0200 Subject: [PATCH 252/342] aiger2: Use `REDUCE` for reduction ops --- backends/aiger2/aiger.cc | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c0b9a0d7a..0a949be48 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -262,21 +262,21 @@ struct Index { } else if (cell->type.in(REDUCE_OPS, ID($logic_not))) { SigSpec inport = cell->getPort(ID::A); - log_assert(inport.size() > 0); // TODO - - Lit acc = visit(cursor, inport[0]); - for (int i = 1; i < inport.size(); i++) { - Lit l = visit(cursor, inport[i]); - if (cell->type == ID($reduce_and)) { - acc = AND(acc, l); + std::vector lits; + for (int i = 0; i < inport.size(); i++) { + Lit lit = visit(cursor, inport[i]); + if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) { + lits.push_back(lit); } else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) { - acc = OR(acc, l); - } else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) { - acc = XOR(acc, l); + lits.push_back(NOT(lit)); + } else { + log_abort(); } } - if (!cell->type.in(ID($reduce_xnor), ID($logic_not))) + Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor))); + + if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool))) return acc; else return NOT(acc); From 6cecf19ff4929ef04ce6915b4360f4d9b1782075 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 16 Sep 2024 18:26:02 +0200 Subject: [PATCH 253/342] aiger2: Ingest `$bmux` --- backends/aiger2/aiger.cc | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0a949be48..5521a8133 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -42,7 +42,8 @@ PRIVATE_NAMESPACE_BEGIN // TODO //#define ARITH_OPS ID($add), ID($sub), ID($neg) -#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, ID($pmux) /*, ARITH_OPS*/ +#define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ + ID($pmux), ID($bmux) /*, ARITH_OPS*/ template struct Index { @@ -399,6 +400,25 @@ struct Index { } return OR(AND(REDUCE(sels), a), NOT(REDUCE(bar))); + } else if (cell->type == ID($bmux)) { + SigSpec aport = cell->getPort(ID::A); + SigSpec sport = cell->getPort(ID::S); + int width = cell->getParam(ID::WIDTH).as_int(); + + std::vector data; + for (int i = obit; i < aport.size(); i += width) + data.push_back(visit(cursor, aport[i])); + + std::vector next; + for (int i = 0; i < sport.size(); i++) { + Lit s = visit(cursor, sport[i]); + next.clear(); + for (int j = 0; j < data.size(); j += 2) + next.push_back(MUX(data[j], data[j + 1], s)); + data.swap(next); + } + log_assert(data.size() == 1); + return data[0]; } else { log_abort(); } From 1ab7f2993300e5444655b3e7aa8807f2f3bfa180 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 11:55:04 +0200 Subject: [PATCH 254/342] Start read_xaiger2 -sc_mapping --- frontends/aiger2/Makefile.inc | 2 + frontends/aiger2/xaiger.cc | 275 ++++++++++++++++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 frontends/aiger2/Makefile.inc create mode 100644 frontends/aiger2/xaiger.cc diff --git a/frontends/aiger2/Makefile.inc b/frontends/aiger2/Makefile.inc new file mode 100644 index 000000000..b4a9f6b89 --- /dev/null +++ b/frontends/aiger2/Makefile.inc @@ -0,0 +1,2 @@ + +OBJS += frontends/aiger2/xaiger.o diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc new file mode 100644 index 000000000..d2c2aa4b2 --- /dev/null +++ b/frontends/aiger2/xaiger.cc @@ -0,0 +1,275 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) Martin Povišer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +uint32_t read_be32(std::istream &f) { + return ((uint32_t) f.get() << 24) | + ((uint32_t) f.get() << 16) | + ((uint32_t) f.get() << 8) | (uint32_t) f.get(); +} + +IdString read_idstring(std::istream &f) +{ + std::string str; + std::getline(f, str, '\0'); + if (!f.good()) + log_error("failed to read string\n"); + return RTLIL::escape_id(str); +} + +struct Xaiger2Frontend : public Frontend { + Xaiger2Frontend() : Frontend("xaiger2", "read XAIGER file (new)") {} + + void read_sc_mapping(std::istream *&f, std::string filename, std::vector args, Design *design) + { + IdString module_name; + std::string map_filename; + + size_t argidx; + for (argidx = 2; argidx < args.size(); argidx++) { + std::string arg = args[argidx]; + if (arg == "-module_name" && argidx + 1 < args.size()) { + module_name = RTLIL::escape_id(args[++argidx]); + continue; + } + if (arg == "-map2" && argidx + 1 < args.size()) { + map_filename = args[++argidx]; + continue; + } + break; + } + extra_args(f, filename, args, argidx, true); + + if (map_filename.empty()) + log_error("A '-map2' argument required\n"); + if (module_name.empty()) + log_error("A '-module_name' argument required\n"); + + Module *module = design->module(module_name); + if (!module) + log_error("Module '%s' not found\n", log_id(module_name)); + + std::ifstream map_file; + map_file.open(map_filename); + if (!map_file) + log_error("Failed to open map file '%s'\n", map_filename.c_str()); + + unsigned int M, I, L, O, A; + std::string header; + if (!(*f >> header >> M >> I >> L >> O >> A) || header != "aig") + log_error("Bad header\n"); + std::string line; + std::getline(*f, line); + log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A); + + if (L != 0) + log_error("Latches unsupported\n"); + if (I + L + A != M) + log_error("Inconsistent header\n"); + + std::vector outputs; + for (int i = 0; i < O; i++) { + int po; + *f >> po; + log_assert(f->get() == '\n'); + outputs.push_back(po); + } + + std::vector bits(2 + 2*M, RTLIL::Sm); + bits[0] = RTLIL::S0; + bits[1] = RTLIL::S1; + + std::string type; + while (map_file >> type) { + if (type == "pi") { + int pi_idx; + int woffset; + std::string name; + if (!(map_file >> pi_idx >> woffset >> name)) + log_error("Bad map file (1)\n"); + int lit = (2 * pi_idx) + 2; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (2)\n"); + Wire *w = module->wire(name); + if (!w || woffset < 0 || woffset >= w->width) + log_error("Map file references non-existent signal bit %s[%d]\n", + name.c_str(), woffset); + bits[lit] = SigBit(w, woffset); + } else { + std::string scratch; + std::getline(map_file, scratch); + } + } + + for (int i = 0; i < A; i++) { + while (f->get() & 0x80 && !f->eof()); + while (f->get() & 0x80 && !f->eof()); + } + + if (f->get() != 'c') + log_error("Missing 'c' ahead of extensions\n"); + if (f->peek() == '\n') + f->get(); + + bool read_mapping = false; + uint32_t no_cells, no_instances; + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'M') { + uint32_t len = read_be32(*f); + read_mapping = true; + + no_cells = read_be32(*f); + no_instances = read_be32(*f); + + log_debug("M: len=%u no_cells=%u no_instances=%u\n", len, no_cells, no_instances); + + struct MappingCell { + RTLIL::IdString type; + RTLIL::IdString out; + std::vector ins; + }; + std::vector cells; + cells.resize(no_cells); + + for (unsigned i = 0; i < no_cells; ++i) { + auto &cell = cells[i]; + cell.type = read_idstring(*f); + cell.out = read_idstring(*f); + uint32_t nins = read_be32(*f); + for (uint32_t j = 0; j < nins; j++) + cell.ins.push_back(read_idstring(*f)); + log_debug("M: Cell %s (out %s, ins", log_id(cell.type), log_id(cell.out)); + for (auto in : cell.ins) + log_debug(" %s", log_id(in)); + log_debug(")\n"); + } + + for (unsigned i = 0; i < no_instances; ++i) { + uint32_t cell_id = read_be32(*f); + uint32_t out_lit = read_be32(*f); + + log_assert(out_lit < bits.size()); + log_assert(bits[out_lit] == RTLIL::Sm); + log_assert(cell_id < cells.size()); + auto &cell = cells[cell_id]; + Cell *instance = module->addCell(NEW_ID, cell.type); + auto out_w = module->addWire(NEW_ID); + instance->setPort(cell.out, out_w); + bits[out_lit] = out_w; + for (auto in : cell.ins) { + uint32_t in_lit = read_be32(*f); + log_assert(out_lit < bits.size()); + log_assert(bits[in_lit] != RTLIL::Sm); + instance->setPort(in, bits[in_lit]); + } + } + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + + if (!read_mapping) + log_error("Missing mapping (no 'M' section)\n"); + + while (true) { + std::string scratch; + std::getline(*f, scratch); + if (f->eof()) + break; + log_assert(!f->fail()); + log("input file: %s\n", scratch.c_str()); + } + + log("Read %d instances with cell library of size %d.\n", + no_instances, no_cells); + + // TODO + map_file.close(); + map_file.open(map_filename); + while (map_file >> type) { + if (type == "po") { + int po_idx; + int woffset; + std::string name; + if (!(map_file >> po_idx >> woffset >> name)) + log_error("Bad map file (3)\n"); + if (po_idx < 0 || po_idx >= outputs.size()) + log_error("Bad map file (4)\n"); + int lit = outputs[po_idx]; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (5)\n"); + if (bits[lit] == RTLIL::Sm) + log_error("Bad map file (6)\n"); + Wire *w = module->wire(name); + if (!w || woffset < 0 || woffset >= w->width) + log_error("Map file references non-existent signal bit %s[%d]\n", + name.c_str(), woffset); + module->connect(SigBit(w, woffset), bits[lit]); + } else if (type == "pseudopo") { + int po_idx; + int poffset; + std::string box_name; + std::string box_port; + if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) + log_error("Bad map file (7)\n"); + if (po_idx < 0 || po_idx >= outputs.size()) + log_error("Bad map file (8)\n"); + int lit = outputs[po_idx]; + if (lit < 0 || lit >= bits.size()) + log_error("Bad map file (9)\n"); + if (bits[lit] == RTLIL::Sm) + log_error("Bad map file (10)\n"); + Cell *cell = module->cell(box_name); + if (!cell || !cell->hasPort(box_port)) + log_error("Map file references non-existent box port %s/%s\n", + box_name.c_str(), box_port.c_str()); + SigSpec &port = cell->connections_[box_port]; + if (poffset < 0 || poffset >= port.size()) + log_error("Map file references non-existent box port bit %s/%s[%d]\n", + box_name.c_str(), box_port.c_str(), poffset); + port[poffset] = bits[lit]; + } else { + std::string scratch; + std::getline(map_file, scratch); + } + } + } + + void execute(std::istream *&f, std::string filename, std::vector args, Design *design) override + { + log_header(design, "Executing XAIGER2 frontend.\n"); + + if (args.size() > 1 && args[1] == "-sc_mapping") { + read_sc_mapping(f, filename, args, design); + return; + } + + log_cmd_error("Mode '-sc_mapping' must be selected\n"); + } +} Xaiger2Frontend; + +PRIVATE_NAMESPACE_END From 72d65063c32adce9eb2e33bee41736e8339fbea4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:38:05 +0200 Subject: [PATCH 255/342] aiger2: Ignore benign cells --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 5521a8133..c6386b783 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -87,7 +87,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (cell->type.in(KNOWN_OPS)) + if (cell->type.in(KNOWN_OPS) || cell->type.in(ID($scopeinfo), ID($specify2), ID($specify3))) continue; Module *submodule = m->design->module(cell->type); From 2a3e907da847342da56fd7a067e4f288213c36db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:39:05 +0200 Subject: [PATCH 256/342] aiger2: Adjust typing --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c6386b783..d205f8508 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -125,7 +125,7 @@ struct Index { bool const_folding = true; bool strashing = false; - dict, int> cache; + dict, Lit> cache; Lit AND(Lit a, Lit b) { @@ -602,7 +602,7 @@ struct AigerWriter : Index { } void write_header() { - log_assert(lit_counter == (ninputs + nlatches + nands) * 2 + 2); + log_assert(lit_counter == (Lit) (ninputs + nlatches + nands) * 2 + 2); char buf[128]; snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", From ea765686b69c889f0cef7a5f4e0e670a4ab0b6db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:41:05 +0200 Subject: [PATCH 257/342] aiger2: Adjust hierarchy/port handling --- backends/aiger2/aiger.cc | 185 ++++++++++++++++++++++++++++++--------- tests/various/aiger2.ys | 2 +- 2 files changed, 145 insertions(+), 42 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index d205f8508..5e58a9ebc 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -19,6 +19,7 @@ // TODOs: // - gracefully handling inout ports (an error message probably) +// - undriven wires #include "kernel/register.h" #include "kernel/celltypes.h" @@ -56,6 +57,7 @@ struct Index { int len; dict windices; dict suboffsets; + pool found_blackboxes; bool indexing = false; bool indexed = false; @@ -73,6 +75,10 @@ struct Index { return sum; } + bool flatten = false; + bool inline_whiteboxes = false; + bool allow_blackboxes = false; + int index_module(RTLIL::Module *m) { ModuleInfo &info = modules[m]; @@ -91,11 +97,21 @@ struct Index { continue; Module *submodule = m->design->module(cell->type); - if (!submodule || submodule->get_blackbox_attribute()) - log_error("Unsupported cell type: %s (%s in %s)\n", - log_id(cell->type), log_id(cell), log_id(m)); - info.suboffsets[cell] = pos; - pos += index_module(submodule); + + if (submodule && flatten && + !submodule->get_bool_attribute(ID::keep_hierarchy) && + !submodule->get_blackbox_attribute(inline_whiteboxes)) { + info.suboffsets[cell] = pos; + pos += index_module(submodule); + } else { + if (allow_blackboxes) { + info.found_blackboxes.insert(cell); + } else { + if (!submodule || submodule->get_blackbox_attribute()) + log_error("Unsupported cell type: %s (%s in %s)\n", + log_id(cell->type), log_id(cell), log_id(m)); + } + } } info.len = pos; @@ -429,30 +445,36 @@ struct Index { std::vector levels; int instance_offset = 0; - HierCursor(ModuleInfo &top) + HierCursor() { - levels.push_back(Level(top, nullptr)); } - ModuleInfo ¤t_minfo() + ModuleInfo &leaf_minfo(Index &index) { - log_assert(!levels.empty()); - return levels.back().first; + if (levels.empty()) + return *index.top_minfo; + else + return levels.back().first; } - int bitwire_index(SigBit bit) + Module *leaf_module(Index &index) + { + return leaf_minfo(index).module; + } + + int bitwire_index(Index &index, SigBit bit) { log_assert(bit.wire != nullptr); - return instance_offset + current_minfo().windices[bit.wire] + bit.offset; + return instance_offset + leaf_minfo(index).windices[bit.wire] + bit.offset; } - Cell *exit() + Cell *exit(Index &index) { - log_assert(levels.size() > 1); + log_assert(!levels.empty()); Cell *instance = levels.back().second; levels.pop_back(); - instance_offset -= current_minfo().suboffsets.at(instance); + instance_offset -= leaf_minfo(index).suboffsets.at(instance); // return the instance we just exited return instance; @@ -461,7 +483,7 @@ struct Index { Module *enter(Index &index, Cell *cell) { Design *design = index.design; - auto &minfo = current_minfo(); + auto &minfo = leaf_minfo(index); log_assert(minfo.suboffsets.count(cell)); Module *def = design->module(cell->type); log_assert(def); @@ -471,6 +493,47 @@ struct Index { // return the module definition we just entered return def; } + + bool is_top() + { + return levels.empty(); + } + + std::string path() + { + std::string ret; + bool first = true; + for (auto pair : levels) { + if (!first) + ret += "."; + if (!pair.second) + ret += RTLIL::unescape_id(pair.first.module->name); + else + ret += RTLIL::unescape_id(pair.second->name); + first = false; + } + return ret; + } + + int hash() const + { + int hash = 0; + for (auto pair : levels) + hash += (uintptr_t) pair.second; + return hash; + } + + bool operator==(const HierCursor &other) const + { + if (levels.size() != other.levels.size()) + return false; + + for (int i = 0; i < levels.size(); i++) + if (levels[i].second != other.levels[i].second) + return false; + + return true; + } }; Lit visit(HierCursor &cursor, SigBit bit) @@ -484,7 +547,7 @@ struct Index { log_error("Unhandled state %s\n", log_signal(bit)); } - int idx = cursor.bitwire_index(bit); + int idx = cursor.bitwire_index(*this, bit); if (lits[idx] != Writer::EMPTY_LIT) { // literal already assigned return lits[idx]; @@ -510,16 +573,15 @@ struct Index { bit.offset, log_id(portname), log_id(driver), log_id(def), w->width); ret = visit(cursor, SigBit(w, bit.offset)); } - cursor.exit(); + cursor.exit(*this); } - } else { // a module input: we cannot be the top module, otherwise // the branch for pre-existing literals would have been taken - log_assert(cursor.levels.size() > 1); + log_assert(!cursor.is_top()); // step into the upper module - Cell *instance = cursor.exit(); + Cell *instance = cursor.exit(*this); { IdString portname = bit.wire->name; if (!instance->hasPort(portname)) @@ -538,23 +600,54 @@ struct Index { return ret; } - void set_top_port(SigBit bit, Lit lit) + Lit &pi_literal(SigBit bit, HierCursor *cursor=nullptr) { log_assert(bit.wire); - log_assert(bit.wire->module == top); - log_assert(bit.wire->port_input); - lits[top_minfo->windices[bit.wire] + bit.offset] = lit; + if (!cursor) { + log_assert(bit.wire->module == top); + log_assert(bit.wire->port_input); + return lits[top_minfo->windices[bit.wire] + bit.offset]; + } else { + log_assert(bit.wire->module == cursor->leaf_module(*this)); + return lits[cursor->bitwire_index(*this, bit)]; + } } - Lit get_top_port(SigBit bit) + Lit eval_po(SigBit bit, HierCursor *cursor=nullptr) { - HierCursor cursor(*top_minfo); - Lit ret = visit(cursor, bit); - log_assert(cursor.levels.size() == 1); - log_assert(cursor.instance_offset == 0); + Lit ret; + if (!cursor) { + HierCursor cursor_; + ret = visit(cursor_, bit); + log_assert(cursor_.is_top()); + log_assert(cursor_.instance_offset == 0); + } else { + ret = visit(*cursor, bit); + } return ret; } + + void visit_hierarchy(std::function f, + HierCursor &cursor) + { + f(cursor); + + ModuleInfo &minfo = cursor.leaf_minfo(*this); + for (auto cell : minfo.module->cells()) { + if (minfo.suboffsets.count(cell)) { + cursor.enter(*this, cell); + visit_hierarchy(f, cursor); + cursor.exit(*this); + } + } + } + + void visit_hierarchy(std::function f) + { + HierCursor cursor; + visit_hierarchy(f, cursor); + } }; struct AigerWriter : Index { @@ -616,20 +709,25 @@ struct AigerWriter : Index { // populate inputs std::vector inputs; - for (auto w : top->wires()) + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); if (w->port_input) for (int i = 0; i < w->width; i++) { - set_top_port(SigBit(w, i), lit_counter); + pi_literal(SigBit(w, i)) = lit_counter; inputs.push_back(SigBit(w, i)); lit_counter += 2; ninputs++; } + } this->f = f; // start with the header write_header(); // insert padding where output literals will go (once known) - for (auto w : top->wires()) + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); if (w->port_output) { for (auto bit : SigSpec(w)) { (void) bit; @@ -639,6 +737,7 @@ struct AigerWriter : Index { noutputs++; } } + } auto data_start = f->tellp(); // now the guts @@ -646,7 +745,7 @@ struct AigerWriter : Index { for (auto w : top->wires()) if (w->port_output) { for (auto bit : SigSpec(w)) - outputs.push_back({bit, get_top_port(bit)}); + outputs.push_back({bit, eval_po(bit)}); } auto data_end = f->tellp(); @@ -749,6 +848,8 @@ struct Aiger2Backend : Backend { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; else break; } @@ -791,12 +892,12 @@ struct AIGCounter : Index { for (auto w : top->wires()) if (w->port_input) for (int i = 0; i < w->width; i++) - set_top_port(SigBit(w, i), ++nvars); + pi_literal(SigBit(w, i)) = ++nvars; for (auto w : top->wires()) if (w->port_output) { for (auto bit : SigSpec(w)) - (void) get_top_port(bit); + (void) eval_po(bit); } } }; @@ -808,10 +909,12 @@ struct AigsizePass : Pass { log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); size_t argidx; - AIGCounter counter; + AIGCounter writer; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") - counter.strashing = true; + writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; else break; } @@ -823,9 +926,9 @@ struct AigsizePass : Pass { log_cmd_error("No top module selected\n"); design->bufNormalize(true); - counter.setup(top); - counter.count(); - log("Counted %d gates\n", counter.ngates); + writer.setup(top); + writer.count(); + log("Counted %d gates\n", writer.ngates); // we are leaving the sacred land, un-bufnormalize // (if not, this will lead to bugs: the buf-normalized diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index 0efb5dd76..e008cdfaf 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -158,7 +158,7 @@ copy test gold flatten gold techmap submodule1 select test -write_aiger2 aiger2_ops.aig +write_aiger2 -flatten aiger2_ops.aig select -clear delete test read_aiger -module_name test aiger2_ops.aig From 5f8d7ff1702277d380bc90462ec6006222e2eab2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:53:31 +0200 Subject: [PATCH 258/342] Start new write_xaiger2 backend for export w/ boxes --- backends/aiger2/aiger.cc | 439 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 438 insertions(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 5e58a9ebc..6af7b0948 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -700,13 +700,14 @@ struct AigerWriter : Index { char buf[128]; snprintf(buf, sizeof(buf) - 1, "aig %08d %08d %08d %08d %08d\n", ninputs + nlatches + nands, ninputs, nlatches, noutputs, nands); - f->seekp(0); f->write(buf, strlen(buf)); } void write(std::ostream *f) { reset_counters(); + auto file_start = f->tellp(); + // populate inputs std::vector inputs; for (auto id : top->ports) { @@ -750,6 +751,7 @@ struct AigerWriter : Index { auto data_end = f->tellp(); // revisit header and the list of outputs + f->seekp(file_start); write_header(); for (auto pair : outputs) { char buf[16]; @@ -788,6 +790,390 @@ struct AigerWriter : Index { } }; +struct XAigerWriter : AigerWriter { + XAigerWriter() + { + allow_blackboxes = true; + } + + bool mapping_prep = false; + pool keep_wires; + std::ofstream map_file; + + typedef std::pair HierBit; + std::vector pos; + std::vector pis; + int proper_pos_counter = 0; + + pool driven_by_opaque_box; + + void ensure_pi(SigBit bit, HierCursor cursor={}, + bool box_port=false) + { + Lit &lit = pi_literal(bit, &cursor); + if (lit == EMPTY_LIT) { + lit = lit_counter; + pis.push_back(std::make_pair(bit, cursor)); + lit_counter += 2; + if (map_file.is_open() && !box_port) { + log_assert(cursor.is_top()); // TODO + driven_by_opaque_box.insert(bit); + map_file << "pi " << pis.size() - 1 << " " << bit.offset + << " " << bit.wire->name.c_str() << "\n"; + } + } else { + log_assert(!box_port); + } + } + + bool is_pi(SigBit bit, HierCursor cursor={}) + { + return pi_literal(bit, &cursor) != EMPTY_LIT; + } + + void pad_pi() + { + pis.push_back(std::make_pair(RTLIL::Sx, HierCursor{})); + lit_counter += 2; + } + + void append_box_ports(Cell *box, HierCursor &cursor, bool inputs) + { + for (auto &conn : box->connections_) { + bool is_input = box->input(conn.first); + bool is_output = box->output(conn.first); + + if (!(is_input || is_output) || (is_input && is_output)) + log_error("Ambiguous port direction on %s/%s\n", + log_id(box->type), log_id(conn.first)); + + if (is_input && inputs) { + int bitp = 0; + for (auto bit : conn.second) { + if (!bit.wire) { + bitp++; + continue; + } + + if (map_file.is_open()) { + log_assert(cursor.is_top()); + map_file << "pseudopo " << proper_pos_counter++ << " " << bitp + << " " << box->name.c_str() + << " " << conn.first.c_str() << "\n"; + } + + pos.push_back(std::make_pair(bit, cursor)); + + if (mapping_prep) + conn.second[bitp] = RTLIL::Sx; + + bitp++; + } + } else if (is_output && !inputs) { + for (auto &bit : conn.second) { + if (!bit.wire || bit.wire->port_input) + log_error("Bad connection"); + + + ensure_pi(bit, cursor); + keep_wires.insert(bit.wire); + } + } + } + } + + RTLIL::Module *holes_module; + + std::stringstream h_buffer; + static void write_be32(std::ostream &buffer, uint32_t u32) + { + typedef unsigned char uchar; + unsigned char u32_be[4] = { + (uchar) (u32 >> 24), (uchar) (u32 >> 16), (uchar) (u32 >> 8), (uchar) u32 + }; + buffer.write((char *) u32_be, sizeof(u32_be)); + } + + void prep_boxes(int pending_pos_num) + { + // boxes which have timing data, maybe a whitebox model + std::vector> nonopaque_boxes; + // boxes which are fully opaque + std::vector> opaque_boxes; + + log_debug("found boxes:\n"); + visit_hierarchy([&](HierCursor &cursor) { + auto &minfo = cursor.leaf_minfo(*this); + + for (auto box : minfo.found_blackboxes) { + log_debug(" - %s.%s (type %s): ", cursor.path().c_str(), + RTLIL::unescape_id(box->name).c_str(), + log_id(box->type)); + + Module *box_module = design->module(box->type), *box_derived; + + if (box_module && !box->parameters.empty()) { + // TODO: This is potentially costly even if a cached derivation exists + box_derived = design->module(box_module->derive(design, box->parameters)); + log_assert(box_derived); + } else { + box_derived = box_module; + } + + if (box_derived && box_derived->has_attribute(ID::abc9_box_id)) { + // This is an ABC9 box, we have timing data, maybe even a whitebox model + // These need to go last in the AIGER port list. + nonopaque_boxes.push_back(std::make_tuple(cursor, box, box_derived)); + log_debug("non-opaque\n"); + } else { + opaque_boxes.push_back(std::make_tuple(cursor, box, box_derived)); + log_debug("opaque\n"); + } + } + }); + + for (auto [cursor, box, def] : opaque_boxes) + append_box_ports(box, cursor, true); + + holes_module = design->addModule(NEW_ID); + std::vector holes_pis; + int boxes_ci_num = 0, boxes_co_num = 0; + + int box_seq = 0; + + for (auto [cursor, box, def] : nonopaque_boxes) { + // use `def->name` not `box->type` as we want the derived type + Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); + int holes_pi_idx = 0; + + if (map_file.is_open()) { + log_assert(cursor.is_top()); + map_file << "box " << box_seq << " " << box->name.c_str() << "\n"; + } + box_seq++; + + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + log_assert(port); + + SigSpec conn = box->hasPort(port_id) ? box->getPort(port_id) : SigSpec{}; + + if (port->port_input && !port->port_output) { + // primary + for (int i = 0; i < port->width; i++) { + SigBit bit; + if (i < conn.size()) { + bit = conn[i]; + } else { + // FIXME: hierarchical path + log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n", + log_id(port_id), i, log_id(box), log_id(box->type)); + bit = RTLIL::Sx; + } + + pos.push_back(std::make_pair(bit, cursor)); + } + boxes_co_num += port->width; + + if (mapping_prep && !conn.empty()) + box->setPort(port_id, SigSpec(RTLIL::Sx, conn.size())); + + // holes + SigSpec in_conn; + for (int i = 0; i < port->width; i++) { + while (holes_pi_idx >= (int) holes_pis.size()) { + Wire *w = holes_module->addWire(NEW_ID, 1); + w->port_input = true; + holes_module->ports.push_back(w->name); + holes_pis.push_back(w); + } + in_conn.append(holes_pis[i]); + holes_pi_idx++; + } + holes_wb->setPort(port_id, in_conn); + } else if (port->port_output && !port->port_input) { + // primary + for (int i = 0; i < port->width; i++) { + SigBit bit; + if (i < conn.size() && conn[i].is_wire()) { + bit = conn[i]; + } else { + // FIXME: hierarchical path + log_warning("connection on port %s[%d] of instance %s (type %s) missing\n", + log_id(port_id), i, log_id(box), log_id(box->type)); + pad_pi(); + continue; + } + + ensure_pi(bit, cursor, true); + keep_wires.insert(bit.wire); + } + boxes_ci_num += port->width; + + // holes + Wire *w = holes_module->addWire(NEW_ID, port->width); + w->port_output = true; + holes_module->ports.push_back(w->name); + holes_wb->setPort(port_id, w); + } else { + log_error("Ambiguous port direction on %s/%s\n", + log_id(box->type), log_id(port_id)); + } + } + } + + for (auto [cursor, box, def] : opaque_boxes) + append_box_ports(box, cursor, false); + + write_be32(h_buffer, 1); + write_be32(h_buffer, pis.size()); + log_debug("ciNum = %zu\n", pis.size()); + write_be32(h_buffer, pending_pos_num + pos.size()); + log_debug("coNum = %zu\n", boxes_co_num + pos.size()); + write_be32(h_buffer, pis.size() - boxes_ci_num); + log_debug("piNum = %zu\n", pis.size() - boxes_ci_num); + write_be32(h_buffer, pending_pos_num + pos.size() - boxes_co_num); + log_debug("poNum = %zu\n", pending_pos_num + pos.size() - boxes_co_num); + write_be32(h_buffer, nonopaque_boxes.size()); + + box_seq = 0; + for (auto [cursor, box, def] : nonopaque_boxes) { + int box_ci_num = 0, box_co_num = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + log_assert(port); + if (port->port_input && !port->port_output) { + box_co_num += port->width; + } else if (port->port_output && !port->port_input) { + box_ci_num += port->width; + } else { + log_abort(); + } + } + + write_be32(h_buffer, box_co_num); + write_be32(h_buffer, box_ci_num); + write_be32(h_buffer, def->attributes.at(ID::abc9_box_id).as_int()); + write_be32(h_buffer, box_seq++); + } + } + + void clear_boxes() + { + design->remove(holes_module); + } + + void write(std::ostream *f) { + reset_counters(); + + for (auto w : top->wires()) + if (w->port_input) + for (int i = 0; i < w->width; i++) + ensure_pi(SigBit(w, i)); + + int proper_po_num = 0; + for (auto w : top->wires()) + if (w->port_output) + proper_po_num += w->width; + + prep_boxes(proper_po_num); + for (auto w : top->wires()) + if (w->port_output) + for (int i = 0; i < w->width; i++) { + if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) { + map_file << "po " << proper_pos_counter++ << " " << i + << " " << w->name.c_str() << "\n"; + } + pos.push_back(std::make_pair(SigBit(w, i), HierCursor{})); + } + + this->f = f; + // start with the header + ninputs = pis.size(); + noutputs = pos.size(); + write_header(); + // insert padding where output literals will go (once known) + for (auto _ : pos) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", 0); + f->write(buf, strlen(buf)); + } + auto data_start = f->tellp(); + + // now the guts + std::vector outlits; + for (auto &pair : pos) + outlits.push_back(eval_po(pair.first, &pair.second)); + + // revisit header and the list of outputs + f->seekp(0); + ninputs = pis.size(); + noutputs = pos.size(); + write_header(); + for (auto lit : outlits) { + char buf[16]; + snprintf(buf, sizeof(buf) - 1, "%08d\n", lit); + f->write(buf, strlen(buf)); + } + // double check we arrived at the same offset for the + // main data section + log_assert(data_start == f->tellp()); + + // extensions + f->seekp(0, std::ios::end); + + f->put('c'); + + // insert empty 'r' and 's' sections (abc crashes if we provide 'a' without those) + f->put('r'); + write_be32(*f, 4); + write_be32(*f, 0); + f->put('s'); + write_be32(*f, 4); + write_be32(*f, 0); + + f->put('h'); + // TODO: get rid of std::string copy + std::string h_buffer_str = h_buffer.str(); + write_be32(*f, h_buffer_str.size()); + f->write(h_buffer_str.data(), h_buffer_str.size()); + +#if 1 + f->put('a'); + write_be32(*f, 0); // size to be filled later + auto holes_aiger_start = f->tellp(); + { + AigerWriter holes_writer; + holes_writer.flatten = true; + holes_writer.inline_whiteboxes = true; + holes_writer.setup(holes_module); + holes_writer.write(f); + } + auto holes_aiger_size = f->tellp() - holes_aiger_start; + f->seekp(holes_aiger_start, std::ios::beg); + f->seekp(-4, std::ios::cur); + write_be32(*f, holes_aiger_size); +#endif + f->seekp(0, std::ios::end); + + if (mapping_prep) { + std::vector to_remove_cells; + for (auto cell : top->cells()) + if (!top_minfo->found_blackboxes.count(cell)) + to_remove_cells.push_back(cell); + for (auto cell : to_remove_cells) + top->remove(cell); + pool to_remove; + for (auto wire : top->wires()) + if (!wire->port_input && !wire->port_output && !keep_wires.count(wire)) + to_remove.insert(wire); + top->remove(to_remove); + } + + clear_boxes(); + } +}; + struct Aiger2Backend : Backend { Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") { @@ -872,6 +1258,57 @@ struct Aiger2Backend : Backend { } } Aiger2Backend; +struct XAiger2Backend : Backend { + XAiger2Backend() : Backend("xaiger2", "write design to XAIGER file (new)") + { + experimental(); + } + + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override + { + log_header(design, "Executing XAIGER2 backend.\n"); + + size_t argidx; + XAigerWriter writer; + std::string map_filename; + writer.const_folding = true; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-strash") + writer.strashing = true; + else if (args[argidx] == "-flatten") + writer.flatten = true; + else if (args[argidx] == "-mapping_prep") + writer.mapping_prep = true; + else if (args[argidx] == "-map2" && argidx + 1 < args.size()) + map_filename = args[++argidx]; + else + break; + } + extra_args(f, filename, args, argidx); + + Module *top = design->top_module(); + + if (!top || !design->selected_whole_module(top)) + log_cmd_error("No top module selected\n"); + + if (!map_filename.empty()) { + writer.map_file.open(map_filename); + if (!writer.map_file) + log_cmd_error("Failed to open '%s' for writing\n", map_filename.c_str()); + } + + design->bufNormalize(true); + writer.setup(top); + writer.write(f); + + // we are leaving the sacred land, un-bufnormalize + // (if not, this will lead to bugs: the buf-normalized + // flag must not be kept on past the code that can work + // with it) + design->bufNormalize(false); + } +} XAiger2Backend; + struct AIGCounter : Index { typedef int Lit; const static Lit CONST_FALSE = -1; From 3a1b003cc34481a98bcfe61199004cebe6835c7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:53:56 +0200 Subject: [PATCH 259/342] celltypes: Fix `$buf` eval --- kernel/celltypes.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 9868827e6..b6d89a805 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -381,11 +381,10 @@ struct CellTypes HANDLE_CELL_TYPE(modfloor) HANDLE_CELL_TYPE(pow) HANDLE_CELL_TYPE(pos) - HANDLE_CELL_TYPE(buf) HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE - if (type == ID($_BUF_)) + if (type.in(ID($_BUF_), ID($buf))) return arg1; if (type == ID($_NOT_)) return eval_not(arg1); From f168b2f4b18abd4ae6a397a1a7fc4642b218c033 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 18 Sep 2024 16:54:38 +0200 Subject: [PATCH 260/342] read_xaiger2: Update box handling --- frontends/aiger2/xaiger.cc | 183 ++++++++++++++++++++++++++++++++++++- 1 file changed, 178 insertions(+), 5 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index d2c2aa4b2..b60cd0c88 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -95,6 +95,8 @@ struct Xaiger2Frontend : public Frontend { outputs.push_back(po); } + std::vector> boxes; + std::vector retained_boxes; std::vector bits(2 + 2*M, RTLIL::Sm); bits[0] = RTLIL::S0; bits[1] = RTLIL::S1; @@ -115,6 +117,34 @@ struct Xaiger2Frontend : public Frontend { log_error("Map file references non-existent signal bit %s[%d]\n", name.c_str(), woffset); bits[lit] = SigBit(w, woffset); + } else if (type == "box") { + int box_seq; + std::string name; + if (!(map_file >> box_seq >> name)) + log_error("Bad map file (20)\n"); + if (box_seq < 0) + log_error("Bad map file (21)\n"); + + Cell *box = module->cell(RTLIL::escape_id(name)); + if (!box) + log_error("Map file references non-existent box %s\n", + name.c_str()); + + Module *def = design->module(box->type); + if (def && !box->parameters.empty()) { + // TODO: This is potentially costly even if a cached derivation exists + def = design->module(def->derive(design, box->parameters)); + log_assert(def); + } + + if (!def) + log_error("Bad map file (22)\n"); + + if (box_seq >= boxes.size()) { + boxes.resize(box_seq + 1); + retained_boxes.resize(box_seq + 1); + } + boxes[box_seq] = std::make_pair(box, def); } else { std::string scratch; std::getline(map_file, scratch); @@ -130,7 +160,73 @@ struct Xaiger2Frontend : public Frontend { log_error("Missing 'c' ahead of extensions\n"); if (f->peek() == '\n') f->get(); + auto extensions_start = f->tellg(); + log_debug("reading 'h' (first pass)\n"); + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'h') { + uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes; + len = read_be32(*f); + read_be32(*f); + ci_num = read_be32(*f); + co_num = read_be32(*f); + pi_num = read_be32(*f); + po_num = read_be32(*f); + no_boxes = read_be32(*f); + + log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n", + len, ci_num, co_num, pi_num, po_num, no_boxes); + + int ci_counter = 0; + for (uint32_t i = 0; i < no_boxes; i++) { + uint32_t box_inputs, box_outputs, box_id, box_seq; + box_inputs = read_be32(*f); + box_outputs = read_be32(*f); + box_id = read_be32(*f); + box_seq = read_be32(*f); + + log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log_assert(box_seq < boxes.size()); + + auto [cell, def] = boxes[box_seq]; + log_assert(cell && def); + retained_boxes[box_seq] = true; + + int box_ci_idx = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + if (port->port_output) { + if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width) + log_error("Malformed design (1)\n"); + + SigSpec &conn = cell->connections_[port_id]; + for (int j = 0; j < port->width; j++) { + if (conn[j].wire && conn[j].wire->port_output) + conn[j] = module->addWire(module->uniquify( + stringf("$box$%s$%s$%d", + cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(), + port_id.isPublic() ? port_id.c_str() + 1 : port_id.c_str(), + j))); + + bits[2*(pi_num + ci_counter + box_ci_idx++) + 2] = conn[j]; + } + } + } + + log_assert(box_ci_idx == box_outputs); + ci_counter += box_ci_idx; + } + log_assert(pi_num + ci_counter == ci_num); + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + + f->seekg(extensions_start); bool read_mapping = false; uint32_t no_cells, no_instances; for (int c = f->get(); c != EOF; c = f->get()) { @@ -172,10 +268,11 @@ struct Xaiger2Frontend : public Frontend { log_assert(bits[out_lit] == RTLIL::Sm); log_assert(cell_id < cells.size()); auto &cell = cells[cell_id]; - Cell *instance = module->addCell(NEW_ID, cell.type); - auto out_w = module->addWire(NEW_ID); + Cell *instance = module->addCell(module->uniquify(stringf("$sc%d", out_lit)), cell.type); + auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); instance->setPort(cell.out, out_w); bits[out_lit] = out_w; + log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type)); for (auto in : cell.ins) { uint32_t in_lit = read_be32(*f); log_assert(out_lit < bits.size()); @@ -195,6 +292,74 @@ struct Xaiger2Frontend : public Frontend { if (!read_mapping) log_error("Missing mapping (no 'M' section)\n"); + log("Read %d instances with cell library of size %d.\n", + no_instances, no_cells); + + f->seekg(extensions_start); + log_debug("reading 'h' (second pass)\n"); + int co_counter = 0; + for (int c = f->get(); c != EOF; c = f->get()) { + if (c == 'h') { + uint32_t len, ci_num, co_num, pi_num, po_num, no_boxes; + len = read_be32(*f); + read_be32(*f); + ci_num = read_be32(*f); + co_num = read_be32(*f); + pi_num = read_be32(*f); + po_num = read_be32(*f); + no_boxes = read_be32(*f); + + log_debug("len=%u ci_num=%u co_num=%u pi_num=%u po_nun=%u no_boxes=%u\n", + len, ci_num, co_num, pi_num, po_num, no_boxes); + + for (uint32_t i = 0; i < no_boxes; i++) { + uint32_t box_inputs, box_outputs, box_id, box_seq; + box_inputs = read_be32(*f); + box_outputs = read_be32(*f); + box_id = read_be32(*f); + box_seq = read_be32(*f); + + log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log_assert(box_seq < boxes.size()); + + auto [cell, def] = boxes[box_seq]; + log_assert(cell && def); + + int box_co_idx = 0; + for (auto port_id : def->ports) { + Wire *port = def->wire(port_id); + SigSpec conn; + if (port->port_input) { + if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width) + log_error("Malformed design (2)\n"); + + SigSpec conn; + for (int j = 0; j < port->width; j++) { + log_assert(co_counter + box_co_idx < outputs.size()); + int lit = outputs[co_counter + box_co_idx++]; + log_assert(lit >= 0 && lit < bits.size()); + SigBit bit = bits[lit]; + if (bit == RTLIL::Sm) + log_error("Malformed mapping (1)\n"); + conn.append(bit); + } + cell->setPort(port_id, conn); + } + } + + log_assert(box_co_idx == box_inputs); + co_counter += box_co_idx; + } + log_assert(po_num + co_counter == co_num); + } else if (c == '\n') { + break; + } else { + uint32_t len = read_be32(*f); + f->ignore(len); + log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + } + } + while (true) { std::string scratch; std::getline(*f, scratch); @@ -204,10 +369,9 @@ struct Xaiger2Frontend : public Frontend { log("input file: %s\n", scratch.c_str()); } - log("Read %d instances with cell library of size %d.\n", - no_instances, no_cells); + log_debug("co_counter=%d\n", co_counter); - // TODO + // TODO: seek without close/open map_file.close(); map_file.open(map_filename); while (map_file >> type) { @@ -217,11 +381,13 @@ struct Xaiger2Frontend : public Frontend { std::string name; if (!(map_file >> po_idx >> woffset >> name)) log_error("Bad map file (3)\n"); + po_idx += co_counter; if (po_idx < 0 || po_idx >= outputs.size()) log_error("Bad map file (4)\n"); int lit = outputs[po_idx]; if (lit < 0 || lit >= bits.size()) log_error("Bad map file (5)\n"); + log("output=%d lit=%d\n", po_idx, lit); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); Wire *w = module->wire(name); @@ -236,6 +402,7 @@ struct Xaiger2Frontend : public Frontend { std::string box_port; if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) log_error("Bad map file (7)\n"); + po_idx += co_counter; if (po_idx < 0 || po_idx >= outputs.size()) log_error("Bad map file (8)\n"); int lit = outputs[po_idx]; @@ -257,6 +424,12 @@ struct Xaiger2Frontend : public Frontend { std::getline(map_file, scratch); } } + + int box_seq = 0; + for (auto [cell, def] : boxes) { + if (!retained_boxes[box_seq++]) + module->remove(cell); + } } void execute(std::istream *&f, std::string filename, std::vector args, Design *design) override From 9018d06a33d2d66f57ad825053c31f85417339a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 19 Sep 2024 11:21:09 +0200 Subject: [PATCH 261/342] quicklogic: Avoid carry chains in division mapping The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions. --- techlibs/common/techmap.v | 3 ++- techlibs/quicklogic/synth_quicklogic.cc | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 68b276588..119296147 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -304,6 +304,7 @@ endmodule // Divide and Modulo // -------------------------------------------------------- +`ifndef NODIV module \$__div_mod_u (A, B, Y, R); parameter WIDTH = 1; @@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y); .R(Y) ); endmodule - +`endif // -------------------------------------------------------- // Power diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0e7aaa752..76ef44570 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_gates")) { if (inferAdder && family == "qlf_k6n10f") { - run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)"); + run("techmap", "(unless -no_adder)"); } else { run("techmap"); } From b788de932972074e58df9b11db40cfb574dcf12e Mon Sep 17 00:00:00 2001 From: George Rennie Date: Tue, 24 Sep 2024 03:01:49 +0100 Subject: [PATCH 262/342] smtbmc: escape path identifiers * also changes the print format for cover statements to be more uniform with the asserts, allowing easier parsing of cover path * this allows diambiguation of properties with the same name but different paths (see https://github.com/YosysHQ/sby/issues/296) --- backends/smt2/smtbmc.py | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index c3bdcebbe..d17bad3fb 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -1454,6 +1454,10 @@ def write_trace(steps_start, steps_stop, index, allregs=False): if outywfile is not None: write_yw_trace(steps, index, allregs) +def escape_path_segment(segment): + if "." in segment: + return f"\\{segment} " + return segment def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()): assert mod in smt.modinfo @@ -1464,7 +1468,8 @@ def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=() for cellname, celltype in smt.modinfo[mod].cells.items(): cell_infokey = (mod, cellname, infokey) - if print_failed_asserts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname, extrainfo, infomap, cell_infokey): + cell_path = path + "." + escape_path_segment(cellname) + if print_failed_asserts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), cell_path, extrainfo, infomap, cell_infokey): found_failed_assert = True for assertfun, assertinfo in smt.modinfo[mod].asserts.items(): @@ -1497,7 +1502,7 @@ def print_anyconsts_worker(mod, state, path): assert mod in smt.modinfo for cellname, celltype in smt.modinfo[mod].cells.items(): - print_anyconsts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + cellname) + print_anyconsts_worker(celltype, "(|%s_h %s| %s)" % (mod, cellname, state), path + "." + escape_path_segment(cellname)) for fun, info in smt.modinfo[mod].anyconsts.items(): if info[1] is None: @@ -1517,18 +1522,21 @@ def print_anyconsts(state): print_anyconsts_worker(topmod, "s%d" % state, topmod) -def get_cover_list(mod, base): +def get_cover_list(mod, base, path=None): + path = path or mod assert mod in smt.modinfo cover_expr = list() + # A tuple of path and cell name cover_desc = list() for expr, desc in smt.modinfo[mod].covers.items(): cover_expr.append("(ite (|%s| %s) #b1 #b0)" % (expr, base)) - cover_desc.append(desc) + cover_desc.append((path, desc)) for cell, submod in smt.modinfo[mod].cells.items(): - e, d = get_cover_list(submod, "(|%s_h %s| %s)" % (mod, cell, base)) + cell_path = path + "." + escape_path_segment(cell) + e, d = get_cover_list(submod, "(|%s_h %s| %s)" % (mod, cell, base), cell_path) cover_expr += e cover_desc += d @@ -1544,7 +1552,8 @@ def get_assert_map(mod, base, path, key_base=()): assert_map[(expr, key_base)] = ("(|%s| %s)" % (expr, base), path, desc) for cell, submod in smt.modinfo[mod].cells.items(): - assert_map.update(get_assert_map(submod, "(|%s_h %s| %s)" % (mod, cell, base), path + "." + cell, (mod, cell, key_base))) + cell_path = path + "." + escape_path_segment(cell) + assert_map.update(get_assert_map(submod, "(|%s_h %s| %s)" % (mod, cell, base), cell_path, (mod, cell, key_base))) return assert_map @@ -1903,7 +1912,9 @@ elif covermode: new_cover_mask.append(cover_mask[i]) continue - print_msg("Reached cover statement at %s in step %d." % (cover_desc[i], step)) + path = cover_desc[i][0] + name = cover_desc[i][1] + print_msg("Reached cover statement in step %d at %s: %s" % (step, path, name)) new_cover_mask.append("0") cover_mask = "".join(new_cover_mask) @@ -1933,7 +1944,7 @@ elif covermode: if "1" in cover_mask: for i in range(len(cover_mask)): if cover_mask[i] == "1": - print_msg("Unreached cover statement at %s." % cover_desc[i]) + print_msg("Unreached cover statement at %s: %s" % (cover_desc[i][0], cover_desc[i][1])) else: # not tempind, covermode active_assert_keys = get_assert_keys() From 3e3515e7d9a0f74503245ccd1b2ff4456fa619f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 24 Sep 2024 17:46:50 +0200 Subject: [PATCH 263/342] log: Never silence `log_cmd_error` Add extra handling to arrange for `log_cmd_error` never being silenced by the command line `-v N` option. Similar path for `log_error` exists already. --- kernel/log.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/kernel/log.cc b/kernel/log.cc index 55895da06..fabbe09fd 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -459,8 +459,21 @@ void log_cmd_error(const char *format, ...) if (log_cmd_error_throw) { log_last_error = vstringf(format, ap); + + // Make sure the error message gets through any selective silencing + // of log output + bool pop_errfile = false; + if (log_errfile != NULL) { + log_files.push_back(log_errfile); + pop_errfile = true; + } + log("ERROR: %s", log_last_error.c_str()); log_flush(); + + if (pop_errfile) + log_files.pop_back(); + throw log_cmd_error_exception(); } From ce7db661a8b7318fd502f26253d810654f6c63b0 Mon Sep 17 00:00:00 2001 From: rherveille Date: Sun, 29 Sep 2024 23:03:01 +0200 Subject: [PATCH 264/342] Added cast to type support (#4284) --- frontends/ast/ast.cc | 16 +- frontends/ast/simplify.cc | 60 +++- frontends/verilog/verilog_parser.y | 6 + tests/verilog/size_cast.sv | 493 +++++++++++++++++++++++++++++ 4 files changed, 573 insertions(+), 2 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6852ef5d3..127806fce 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -478,6 +478,10 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const fprintf(f, ";\n"); break; + case AST_WIRETYPE: + fprintf(f, "%s", id2vl(str).c_str()); + break; + case AST_MEMORY: fprintf(f, "%s" "memory", indent.c_str()); if (is_signed) @@ -694,7 +698,17 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const break; case AST_CAST_SIZE: - children[0]->dumpVlog(f, ""); + switch (children[0]->type) + { + case AST_WIRE: + if (children[0]->children.size() > 0) + children[0]->children[0]->dumpVlog(f, ""); + else + fprintf(f, "%d'", children[0]->range_left - children[0]->range_right + 1); + break; + default: + children[0]->dumpVlog(f, ""); + } fprintf(f, "'("); children[1]->dumpVlog(f, ""); fprintf(f, ")"); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3d8478ef1..fbf5b90aa 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1500,11 +1500,69 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } break; + case AST_CAST_SIZE: { + int width = 1; + AstNode *node; + AstNode *child = children[0]; + + if (child->type == AST_WIRE) { + if (child->children.size() == 0) { + // Base type (e.g., int) + width = child->range_left - child->range_right +1; + node = mkconst_int(width, child->is_signed); + } else { + // User defined type + log_assert(child->children[0]->type == AST_WIRETYPE); + + const std::string &type_name = child->children[0]->str; + if (!current_scope.count(type_name)) + input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); + AstNode *resolved_type_node = current_scope.at(type_name); + if (resolved_type_node->type != AST_TYPEDEF) + input_error("`%s' does not name a type\n", type_name.c_str()); + log_assert(resolved_type_node->children.size() == 1); + AstNode *template_node = resolved_type_node->children[0]; + + // Ensure typedef itself is fully simplified + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; + + switch (template_node->type) + { + case AST_WIRE: { + if (template_node->children.size() > 0 && template_node->children[0]->type == AST_RANGE) + width = range_width(this, template_node->children[0]); + child->delete_children(); + node = mkconst_int(width, true); + break; + } + + case AST_STRUCT: + case AST_UNION: { + child->delete_children(); + width = size_packed_struct(template_node, 0); + node = mkconst_int(width, false); + break; + } + + default: + log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str()); + } + } + + delete child; + children.erase(children.begin()); + children.insert(children.begin(), node); + } + + detect_width_simple = true; + children_are_self_determined = true; + break; + } + case AST_TO_BITS: case AST_TO_SIGNED: case AST_TO_UNSIGNED: case AST_SELFSZ: - case AST_CAST_SIZE: case AST_CONCAT: case AST_REPLICATE: case AST_REDUCE_AND: diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 15a04eb28..31d69ad0c 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3506,6 +3506,12 @@ basic_expr: $$ = new AstNode(AST_CAST_SIZE, $1, $4); SET_AST_NODE_LOC($$, @1, @4); } | + typedef_base_type OP_CAST '(' expr ')' { + if (!sv_mode) + frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode."); + $$ = new AstNode(AST_CAST_SIZE, $1, $4); + SET_AST_NODE_LOC($$, @1, @4); + } | '(' expr '=' expr ')' { ensureAsgnExprAllowed(); AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $4); diff --git a/tests/verilog/size_cast.sv b/tests/verilog/size_cast.sv index 1636f8d70..a1d6bfae5 100644 --- a/tests/verilog/size_cast.sv +++ b/tests/verilog/size_cast.sv @@ -15,6 +15,18 @@ module top; logic signed [1:0] L2sb10 = 2; logic signed [1:0] L2sb11 = 3; + typedef logic u1bit_t; + typedef logic signed s1bit_t; + typedef logic [1:0] u2bit_t; + typedef logic signed [1:0] s2bit_t; + typedef logic [2:0] u3bit_t; + + typedef struct packed { + u1bit_t sign; + u3bit_t msbs; + byte lsbs; + } s12bit_packed_struct_t; + logic y = 1; always @* begin @@ -32,6 +44,19 @@ module top; assert (1'(L2sb10) == 1'b0); assert (1'(L2sb11) == 1'b1); + assert (u1bit_t'(L1b0 ) == 1'b0); + assert (u1bit_t'(L1b1 ) == 1'b1); + assert (s1bit_t'(L1sb0 ) == 1'b0); + assert (s1bit_t'(L1sb1 ) == 1'b1); + assert (u1bit_t'(L2b00 ) == 1'b0); + assert (u1bit_t'(L2b01 ) == 1'b1); + assert (u1bit_t'(L2b10 ) == 1'b0); + assert (u1bit_t'(L2b11 ) == 1'b1); + assert (s1bit_t'(L2sb00) == 1'b0); + assert (s1bit_t'(L2sb01) == 1'b1); + assert (s1bit_t'(L2sb10) == 1'b0); + assert (s1bit_t'(L2sb11) == 1'b1); + assert (2'(L1b0 ) == 2'b00); assert (2'(L1b1 ) == 2'b01); assert (2'(L1sb0 ) == 2'b00); @@ -45,6 +70,19 @@ module top; assert (2'(L2sb10) == 2'b10); assert (2'(L2sb11) == 2'b11); + assert (u2bit_t'(L1b0 ) == 2'b00); + assert (u2bit_t'(L1b1 ) == 2'b01); + assert (s2bit_t'(L1sb0 ) == 2'b00); + assert (s2bit_t'(L1sb1 ) == 2'b11); + assert (u2bit_t'(L2b00 ) == 2'b00); + assert (u2bit_t'(L2b01 ) == 2'b01); + assert (u2bit_t'(L2b10 ) == 2'b10); + assert (u2bit_t'(L2b11 ) == 2'b11); + assert (s2bit_t'(L2sb00) == 2'b00); + assert (s2bit_t'(L2sb01) == 2'b01); + assert (s2bit_t'(L2sb10) == 2'b10); + assert (s2bit_t'(L2sb11) == 2'b11); + assert (3'(L1b0 ) == 3'b000); assert (3'(L1b1 ) == 3'b001); assert (3'(L1sb0 ) == 3'b000); @@ -58,6 +96,19 @@ module top; assert (3'(L2sb10) == 3'b110); assert (3'(L2sb11) == 3'b111); + assert (u3bit_t'(L1b0 ) == 3'b000); + assert (u3bit_t'(L1b1 ) == 3'b001); + assert (u3bit_t'(L1sb0 ) == 3'b000); + assert (u3bit_t'(L1sb1 ) == 3'b111); + assert (u3bit_t'(L2b00 ) == 3'b000); + assert (u3bit_t'(L2b01 ) == 3'b001); + assert (u3bit_t'(L2b10 ) == 3'b010); + assert (u3bit_t'(L2b11 ) == 3'b011); + assert (u3bit_t'(L2sb00) == 3'b000); + assert (u3bit_t'(L2sb01) == 3'b001); + assert (u3bit_t'(L2sb10) == 3'b110); + assert (u3bit_t'(L2sb11) == 3'b111); + assert (3'(L1b0 | '1) == 3'b111); assert (3'(L1b1 | '1) == 3'b111); assert (3'(L1sb0 | '1) == 3'b111); @@ -71,6 +122,58 @@ module top; assert (3'(L2sb10 | '1) == 3'b111); assert (3'(L2sb11 | '1) == 3'b111); + assert (u3bit_t'(L1b0 | '1) == 3'b111); + assert (u3bit_t'(L1b1 | '1) == 3'b111); + assert (u3bit_t'(L1sb0 | '1) == 3'b111); + assert (u3bit_t'(L1sb1 | '1) == 3'b111); + assert (u3bit_t'(L2b00 | '1) == 3'b111); + assert (u3bit_t'(L2b01 | '1) == 3'b111); + assert (u3bit_t'(L2b10 | '1) == 3'b111); + assert (u3bit_t'(L2b11 | '1) == 3'b111); + assert (u3bit_t'(L2sb00 | '1) == 3'b111); + assert (u3bit_t'(L2sb01 | '1) == 3'b111); + assert (u3bit_t'(L2sb10 | '1) == 3'b111); + assert (u3bit_t'(L2sb11 | '1) == 3'b111); + + assert (byte'(L1b0 | '1) == 8'hff); + assert (byte'(L1b1 | '1) == 8'hff); + assert (byte'(L1sb0 | '1) == 8'hff); + assert (byte'(L1sb1 | '1) == 8'hff); + assert (byte'(L2b00 | '1) == 8'hff); + assert (byte'(L2b01 | '1) == 8'hff); + assert (byte'(L2b10 | '1) == 8'hff); + assert (byte'(L2b11 | '1) == 8'hff); + assert (byte'(L2sb00 | '1) == 8'hff); + assert (byte'(L2sb01 | '1) == 8'hff); + assert (byte'(L2sb10 | '1) == 8'hff); + assert (byte'(L2sb11 | '1) == 8'hff); + + assert (int'(L1b0 | '1) == 32'hffff_ffff); + assert (int'(L1b1 | '1) == 32'hffff_ffff); + assert (int'(L1sb0 | '1) == 32'hffff_ffff); + assert (int'(L1sb1 | '1) == 32'hffff_ffff); + assert (int'(L2b00 | '1) == 32'hffff_ffff); + assert (int'(L2b01 | '1) == 32'hffff_ffff); + assert (int'(L2b10 | '1) == 32'hffff_ffff); + assert (int'(L2b11 | '1) == 32'hffff_ffff); + assert (int'(L2sb00 | '1) == 32'hffff_ffff); + assert (int'(L2sb01 | '1) == 32'hffff_ffff); + assert (int'(L2sb10 | '1) == 32'hffff_ffff); + assert (int'(L2sb11 | '1) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(L1b0 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1b1 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1sb0 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L1sb1 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b00 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b01 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b10 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2b11 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb00 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb01 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb10 | '1) == 12'hfff); + assert (s12bit_packed_struct_t'(L2sb11 | '1) == 12'hfff); + assert (3'(L1b0 | '0) == 3'b000); assert (3'(L1b1 | '0) == 3'b001); assert (3'(L1sb0 | '0) == 3'b000); @@ -84,6 +187,58 @@ module top; assert (3'(L2sb10 | '0) == 3'b010); assert (3'(L2sb11 | '0) == 3'b011); + assert (u3bit_t'(L1b0 | '0) == 3'b000); + assert (u3bit_t'(L1b1 | '0) == 3'b001); + assert (u3bit_t'(L1sb0 | '0) == 3'b000); + assert (u3bit_t'(L1sb1 | '0) == 3'b001); + assert (u3bit_t'(L2b00 | '0) == 3'b000); + assert (u3bit_t'(L2b01 | '0) == 3'b001); + assert (u3bit_t'(L2b10 | '0) == 3'b010); + assert (u3bit_t'(L2b11 | '0) == 3'b011); + assert (u3bit_t'(L2sb00 | '0) == 3'b000); + assert (u3bit_t'(L2sb01 | '0) == 3'b001); + assert (u3bit_t'(L2sb10 | '0) == 3'b010); + assert (u3bit_t'(L2sb11 | '0) == 3'b011); + + assert (byte'(L1b0 | '0) == 8'h00); + assert (byte'(L1b1 | '0) == 8'h01); + assert (byte'(L1sb0 | '0) == 8'h00); + assert (byte'(L1sb1 | '0) == 8'h01); + assert (byte'(L2b00 | '0) == 8'h00); + assert (byte'(L2b01 | '0) == 8'h01); + assert (byte'(L2b10 | '0) == 8'h02); + assert (byte'(L2b11 | '0) == 8'h03); + assert (byte'(L2sb00 | '0) == 8'h00); + assert (byte'(L2sb01 | '0) == 8'h01); + assert (byte'(L2sb10 | '0) == 8'h02); + assert (byte'(L2sb11 | '0) == 8'h03); + + assert (int'(L1b0 | '0) == 32'h0000_0000); + assert (int'(L1b1 | '0) == 32'h0000_0001); + assert (int'(L1sb0 | '0) == 32'h0000_0000); + assert (int'(L1sb1 | '0) == 32'h0000_0001); + assert (int'(L2b00 | '0) == 32'h0000_0000); + assert (int'(L2b01 | '0) == 32'h0000_0001); + assert (int'(L2b10 | '0) == 32'h0000_0002); + assert (int'(L2b11 | '0) == 32'h0000_0003); + assert (int'(L2sb00 | '0) == 32'h0000_0000); + assert (int'(L2sb01 | '0) == 32'h0000_0001); + assert (int'(L2sb10 | '0) == 32'h0000_0002); + assert (int'(L2sb11 | '0) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(L1b0 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L1b1 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L1sb0 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L1sb1 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2b00 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L2b01 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2b10 | '0) == 12'h002); + assert (s12bit_packed_struct_t'(L2b11 | '0) == 12'h003); + assert (s12bit_packed_struct_t'(L2sb00 | '0) == 12'h000); + assert (s12bit_packed_struct_t'(L2sb01 | '0) == 12'h001); + assert (s12bit_packed_struct_t'(L2sb10 | '0) == 12'h002); + assert (s12bit_packed_struct_t'(L2sb11 | '0) == 12'h003); + assert (3'(y ? L1b0 : '1) == 3'b000); assert (3'(y ? L1b1 : '1) == 3'b001); assert (3'(y ? L1sb0 : '1) == 3'b000); @@ -97,6 +252,58 @@ module top; assert (3'(y ? L2sb10 : '1) == 3'b010); assert (3'(y ? L2sb11 : '1) == 3'b011); + assert (u3bit_t'(y ? L1b0 : '1) == 3'b000); + assert (u3bit_t'(y ? L1b1 : '1) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : '1) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : '1) == 3'b001); + assert (u3bit_t'(y ? L2b00 : '1) == 3'b000); + assert (u3bit_t'(y ? L2b01 : '1) == 3'b001); + assert (u3bit_t'(y ? L2b10 : '1) == 3'b010); + assert (u3bit_t'(y ? L2b11 : '1) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : '1) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : '1) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : '1) == 3'b010); + assert (u3bit_t'(y ? L2sb11 : '1) == 3'b011); + + assert (byte'(y ? L1b0 : '1) == 8'h00); + assert (byte'(y ? L1b1 : '1) == 8'h01); + assert (byte'(y ? L1sb0 : '1) == 8'h00); + assert (byte'(y ? L1sb1 : '1) == 8'h01); + assert (byte'(y ? L2b00 : '1) == 8'h00); + assert (byte'(y ? L2b01 : '1) == 8'h01); + assert (byte'(y ? L2b10 : '1) == 8'h02); + assert (byte'(y ? L2b11 : '1) == 8'h03); + assert (byte'(y ? L2sb00 : '1) == 8'h00); + assert (byte'(y ? L2sb01 : '1) == 8'h01); + assert (byte'(y ? L2sb10 : '1) == 8'h02); + assert (byte'(y ? L2sb11 : '1) == 8'h03); + + assert (int'(y ? L1b0 : '1) == 32'h0000_0000); + assert (int'(y ? L1b1 : '1) == 32'h0000_0001); + assert (int'(y ? L1sb0 : '1) == 32'h0000_0000); + assert (int'(y ? L1sb1 : '1) == 32'h0000_0001); + assert (int'(y ? L2b00 : '1) == 32'h0000_0000); + assert (int'(y ? L2b01 : '1) == 32'h0000_0001); + assert (int'(y ? L2b10 : '1) == 32'h0000_0002); + assert (int'(y ? L2b11 : '1) == 32'h0000_0003); + assert (int'(y ? L2sb00 : '1) == 32'h0000_0000); + assert (int'(y ? L2sb01 : '1) == 32'h0000_0001); + assert (int'(y ? L2sb10 : '1) == 32'h0000_0002); + assert (int'(y ? L2sb11 : '1) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(y ? L1b0 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b00 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : '1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : '1) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : '1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : '1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : '1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2sb11 : '1) == 12'h003); + assert (3'(y ? L1b0 : '0) == 3'b000); assert (3'(y ? L1b1 : '0) == 3'b001); assert (3'(y ? L1sb0 : '0) == 3'b000); @@ -110,6 +317,58 @@ module top; assert (3'(y ? L2sb10 : '0) == 3'b010); assert (3'(y ? L2sb11 : '0) == 3'b011); + assert (u3bit_t'(y ? L1b0 : '0) == 3'b000); + assert (u3bit_t'(y ? L1b1 : '0) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : '0) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : '0) == 3'b001); + assert (u3bit_t'(y ? L2b00 : '0) == 3'b000); + assert (u3bit_t'(y ? L2b01 : '0) == 3'b001); + assert (u3bit_t'(y ? L2b10 : '0) == 3'b010); + assert (u3bit_t'(y ? L2b11 : '0) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : '0) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : '0) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : '0) == 3'b010); + assert (u3bit_t'(y ? L2sb11 : '0) == 3'b011); + + assert (byte'(y ? L1b0 : '0) == 8'h00); + assert (byte'(y ? L1b1 : '0) == 8'h01); + assert (byte'(y ? L1sb0 : '0) == 8'h00); + assert (byte'(y ? L1sb1 : '0) == 8'h01); + assert (byte'(y ? L2b00 : '0) == 8'h00); + assert (byte'(y ? L2b01 : '0) == 8'h01); + assert (byte'(y ? L2b10 : '0) == 8'h02); + assert (byte'(y ? L2b11 : '0) == 8'h03); + assert (byte'(y ? L2sb00 : '0) == 8'h00); + assert (byte'(y ? L2sb01 : '0) == 8'h01); + assert (byte'(y ? L2sb10 : '0) == 8'h02); + assert (byte'(y ? L2sb11 : '0) == 8'h03); + + assert (int'(y ? L1b0 : '0) == 32'h0000_0000); + assert (int'(y ? L1b1 : '0) == 32'h0000_0001); + assert (int'(y ? L1sb0 : '0) == 32'h0000_0000); + assert (int'(y ? L1sb1 : '0) == 32'h0000_0001); + assert (int'(y ? L2b00 : '0) == 32'h0000_0000); + assert (int'(y ? L2b01 : '0) == 32'h0000_0001); + assert (int'(y ? L2b10 : '0) == 32'h0000_0002); + assert (int'(y ? L2b11 : '0) == 32'h0000_0003); + assert (int'(y ? L2sb00 : '0) == 32'h0000_0000); + assert (int'(y ? L2sb01 : '0) == 32'h0000_0001); + assert (int'(y ? L2sb10 : '0) == 32'h0000_0002); + assert (int'(y ? L2sb11 : '0) == 32'h0000_0003); + + assert (s12bit_packed_struct_t'(y ? L1b0 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b00 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : '0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : '0) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : '0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : '0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : '0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2sb11 : '0) == 12'h003); + assert (3'(y ? L1b0 : 1'sb0) == 3'b000); assert (3'(y ? L1b1 : 1'sb0) == 3'b001); assert (3'(y ? L1sb0 : 1'sb0) == 3'b000); @@ -123,6 +382,123 @@ module top; assert (3'(y ? L2sb10 : 1'sb0) == 3'b110); assert (3'(y ? L2sb11 : 1'sb0) == 3'b111); + assert (u3bit_t'(y ? L1b0 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L1b1 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : 1'sb0) == 3'b111); + assert (u3bit_t'(y ? L2b00 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L2b01 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L2b10 : 1'sb0) == 3'b010); + assert (u3bit_t'(y ? L2b11 : 1'sb0) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : 1'sb0) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : 1'sb0) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : 1'sb0) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : 1'sb0) == 3'b111); + + assert (byte'(y ? L1b0 : 1'sb0) == 8'h00); + assert (byte'(y ? L1b1 : 1'sb0) == 8'h01); + assert (byte'(y ? L1sb0 : 1'sb0) == 8'h00); + assert (byte'(y ? L1sb1 : 1'sb0) == 8'hff); + assert (byte'(y ? L2b00 : 1'sb0) == 8'h00); + assert (byte'(y ? L2b01 : 1'sb0) == 8'h01); + assert (byte'(y ? L2b10 : 1'sb0) == 8'h02); + assert (byte'(y ? L2b11 : 1'sb0) == 8'h03); + assert (byte'(y ? L2sb00 : 1'sb0) == 8'h00); + assert (byte'(y ? L2sb01 : 1'sb0) == 8'h01); + assert (byte'(y ? L2sb10 : 1'sb0) == 8'hfe); + assert (byte'(y ? L2sb11 : 1'sb0) == 8'hff); + + assert (int'(y ? L1b0 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L1b1 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L1sb0 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L1sb1 : 1'sb0) == 32'hffff_ffff); + assert (int'(y ? L2b00 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L2b01 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L2b10 : 1'sb0) == 32'h0000_0002); + assert (int'(y ? L2b11 : 1'sb0) == 32'h0000_0003); + assert (int'(y ? L2sb00 : 1'sb0) == 32'h0000_0000); + assert (int'(y ? L2sb01 : 1'sb0) == 32'h0000_0001); + assert (int'(y ? L2sb10 : 1'sb0) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : 1'sb0) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : 1'sb0) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : 1'sb0) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : 1'sb0) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : 1'sb0) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : 1'sb0) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : 1'sb0) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : 1'sb0) == 12'hfff); + + assert (3'(y ? L1b0 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L1b1 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L1sb0 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L1sb1 : s1bit_t'(0)) == 3'b111); + assert (3'(y ? L2b00 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L2b01 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L2b10 : s1bit_t'(0)) == 3'b010); + assert (3'(y ? L2b11 : s1bit_t'(0)) == 3'b011); + assert (3'(y ? L2sb00 : s1bit_t'(0)) == 3'b000); + assert (3'(y ? L2sb01 : s1bit_t'(0)) == 3'b001); + assert (3'(y ? L2sb10 : s1bit_t'(0)) == 3'b110); + assert (3'(y ? L2sb11 : s1bit_t'(0)) == 3'b111); + + assert (u3bit_t'(y ? L1b0 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L1b1 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : s1bit_t'(0)) == 3'b111); + assert (u3bit_t'(y ? L2b00 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L2b01 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L2b10 : s1bit_t'(0)) == 3'b010); + assert (u3bit_t'(y ? L2b11 : s1bit_t'(0)) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : s1bit_t'(0)) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : s1bit_t'(0)) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : s1bit_t'(0)) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : s1bit_t'(0)) == 3'b111); + + assert (byte'(y ? L1b0 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L1b1 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L1sb0 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L1sb1 : s1bit_t'(0)) == 8'hff); + assert (byte'(y ? L2b00 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L2b01 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L2b10 : s1bit_t'(0)) == 8'h02); + assert (byte'(y ? L2b11 : s1bit_t'(0)) == 8'h03); + assert (byte'(y ? L2sb00 : s1bit_t'(0)) == 8'h00); + assert (byte'(y ? L2sb01 : s1bit_t'(0)) == 8'h01); + assert (byte'(y ? L2sb10 : s1bit_t'(0)) == 8'hfe); + assert (byte'(y ? L2sb11 : s1bit_t'(0)) == 8'hff); + + assert (int'(y ? L1b0 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L1b1 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L1sb0 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L1sb1 : s1bit_t'(0)) == 32'hffff_ffff); + assert (int'(y ? L2b00 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L2b01 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L2b10 : s1bit_t'(0)) == 32'h0000_0002); + assert (int'(y ? L2b11 : s1bit_t'(0)) == 32'h0000_0003); + assert (int'(y ? L2sb00 : s1bit_t'(0)) == 32'h0000_0000); + assert (int'(y ? L2sb01 : s1bit_t'(0)) == 32'h0000_0001); + assert (int'(y ? L2sb10 : s1bit_t'(0)) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : s1bit_t'(0)) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : s1bit_t'(0)) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : s1bit_t'(0)) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : s1bit_t'(0)) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : s1bit_t'(0)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : s1bit_t'(0)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : s1bit_t'(0)) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : s1bit_t'(0)) == 12'hfff); + assert (3'(y ? L1b0 : 1'sb1) == 3'b000); assert (3'(y ? L1b1 : 1'sb1) == 3'b001); assert (3'(y ? L1sb0 : 1'sb1) == 3'b000); @@ -136,5 +512,122 @@ module top; assert (3'(y ? L2sb10 : 1'sb1) == 3'b110); assert (3'(y ? L2sb11 : 1'sb1) == 3'b111); + assert (u3bit_t'(y ? L1b0 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L1b1 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : 1'sb1) == 3'b111); + assert (u3bit_t'(y ? L2b00 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L2b01 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L2b10 : 1'sb1) == 3'b010); + assert (u3bit_t'(y ? L2b11 : 1'sb1) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : 1'sb1) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : 1'sb1) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : 1'sb1) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : 1'sb1) == 3'b111); + + assert (byte'(y ? L1b0 : 1'sb1) == 8'h00); + assert (byte'(y ? L1b1 : 1'sb1) == 8'h01); + assert (byte'(y ? L1sb0 : 1'sb1) == 8'h00); + assert (byte'(y ? L1sb1 : 1'sb1) == 8'hff); + assert (byte'(y ? L2b00 : 1'sb1) == 8'h00); + assert (byte'(y ? L2b01 : 1'sb1) == 8'h01); + assert (byte'(y ? L2b10 : 1'sb1) == 8'h02); + assert (byte'(y ? L2b11 : 1'sb1) == 8'h03); + assert (byte'(y ? L2sb00 : 1'sb1) == 8'h00); + assert (byte'(y ? L2sb01 : 1'sb1) == 8'h01); + assert (byte'(y ? L2sb10 : 1'sb1) == 8'hfe); + assert (byte'(y ? L2sb11 : 1'sb1) == 8'hff); + + assert (int'(y ? L1b0 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L1b1 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L1sb0 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L1sb1 : 1'sb1) == 32'hffff_ffff); + assert (int'(y ? L2b00 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L2b01 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L2b10 : 1'sb1) == 32'h0000_0002); + assert (int'(y ? L2b11 : 1'sb1) == 32'h0000_0003); + assert (int'(y ? L2sb00 : 1'sb1) == 32'h0000_0000); + assert (int'(y ? L2sb01 : 1'sb1) == 32'h0000_0001); + assert (int'(y ? L2sb10 : 1'sb1) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : 1'sb1) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : 1'sb1) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : 1'sb1) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : 1'sb1) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : 1'sb1) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : 1'sb1) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : 1'sb1) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : 1'sb1) == 12'hfff); + + assert (3'(y ? L1b0 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L1b1 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L1sb0 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L1sb1 : s1bit_t'(1)) == 3'b111); + assert (3'(y ? L2b00 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L2b01 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L2b10 : s1bit_t'(1)) == 3'b010); + assert (3'(y ? L2b11 : s1bit_t'(1)) == 3'b011); + assert (3'(y ? L2sb00 : s1bit_t'(1)) == 3'b000); + assert (3'(y ? L2sb01 : s1bit_t'(1)) == 3'b001); + assert (3'(y ? L2sb10 : s1bit_t'(1)) == 3'b110); + assert (3'(y ? L2sb11 : s1bit_t'(1)) == 3'b111); + + assert (u3bit_t'(y ? L1b0 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L1b1 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L1sb0 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L1sb1 : s1bit_t'(1)) == 3'b111); + assert (u3bit_t'(y ? L2b00 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L2b01 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L2b10 : s1bit_t'(1)) == 3'b010); + assert (u3bit_t'(y ? L2b11 : s1bit_t'(1)) == 3'b011); + assert (u3bit_t'(y ? L2sb00 : s1bit_t'(1)) == 3'b000); + assert (u3bit_t'(y ? L2sb01 : s1bit_t'(1)) == 3'b001); + assert (u3bit_t'(y ? L2sb10 : s1bit_t'(1)) == 3'b110); + assert (u3bit_t'(y ? L2sb11 : s1bit_t'(1)) == 3'b111); + + assert (byte'(y ? L1b0 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L1b1 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L1sb0 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L1sb1 : s1bit_t'(1)) == 8'hff); + assert (byte'(y ? L2b00 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L2b01 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L2b10 : s1bit_t'(1)) == 8'h02); + assert (byte'(y ? L2b11 : s1bit_t'(1)) == 8'h03); + assert (byte'(y ? L2sb00 : s1bit_t'(1)) == 8'h00); + assert (byte'(y ? L2sb01 : s1bit_t'(1)) == 8'h01); + assert (byte'(y ? L2sb10 : s1bit_t'(1)) == 8'hfe); + assert (byte'(y ? L2sb11 : s1bit_t'(1)) == 8'hff); + + assert (int'(y ? L1b0 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L1b1 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L1sb0 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L1sb1 : s1bit_t'(1)) == 32'hffff_ffff); + assert (int'(y ? L2b00 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L2b01 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L2b10 : s1bit_t'(1)) == 32'h0000_0002); + assert (int'(y ? L2b11 : s1bit_t'(1)) == 32'h0000_0003); + assert (int'(y ? L2sb00 : s1bit_t'(1)) == 32'h0000_0000); + assert (int'(y ? L2sb01 : s1bit_t'(1)) == 32'h0000_0001); + assert (int'(y ? L2sb10 : s1bit_t'(1)) == 32'hffff_fffe); + assert (int'(y ? L2sb11 : s1bit_t'(1)) == 32'hffff_ffff); + + assert (s12bit_packed_struct_t'(y ? L1b0 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1b1 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L1sb0 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L1sb1 : s1bit_t'(1)) == 12'hfff); + assert (s12bit_packed_struct_t'(y ? L2b00 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2b01 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2b10 : s1bit_t'(1)) == 12'h002); + assert (s12bit_packed_struct_t'(y ? L2b11 : s1bit_t'(1)) == 12'h003); + assert (s12bit_packed_struct_t'(y ? L2sb00 : s1bit_t'(1)) == 12'h000); + assert (s12bit_packed_struct_t'(y ? L2sb01 : s1bit_t'(1)) == 12'h001); + assert (s12bit_packed_struct_t'(y ? L2sb10 : s1bit_t'(1)) == 12'hffe); + assert (s12bit_packed_struct_t'(y ? L2sb11 : s1bit_t'(1)) == 12'hfff); + end endmodule From 59404f8ce55506cfebfe39d1ad404d1ae62e0b0e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 30 Sep 2024 00:21:26 +0000 Subject: [PATCH 265/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 62b4ed459..1e63bdd3f 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+139 +YOSYS_VER := 0.45+145 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 5fca9b867d269ad2ab6e01779f833d7785c53138 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Mon, 30 Sep 2024 16:25:22 +0200 Subject: [PATCH 266/342] Add Get vcd2fst step to test-yosys job Co-authored-by: Miodrag Milanovic Co-authored-by: Roland Coeurjoly --- .github/workflows/test-build.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 0eb2c65c5..e5aed6af3 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -100,6 +100,16 @@ jobs: cd iverilog echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV + - name: Get vcd2fst + shell: bash + run: | + git clone https://github.com/mmicko/libwave.git + mkdir -p ${{ github.workspace }}/.local/ + cd libwave + cmake . -DCMAKE_INSTALL_PREFIX=${{ github.workspace }}/.local + make -j$procs + make install + - name: Cache iverilog id: cache-iverilog uses: actions/cache@v4 From 35c8ad61ac9baaacf7919359b63b930e37d21b09 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 30 Sep 2024 17:38:43 +0300 Subject: [PATCH 267/342] cli/python: error-checking, python interpreter bugfix * Less brittle method of adding script dirname to sys.path * Check if scriptfp successfully opens before using it * Move `log_error` to after `PyErr_Print()` is called --- kernel/driver.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index d30b19c96..53608c260 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -665,13 +665,19 @@ int main(int argc, char **argv) PyObject_SetAttrString(sys, "argv", new_argv); Py_DECREF(old_argv); - PyRun_SimpleString(("import os;sys.path.insert(0, os.path.dirname(os.path.abspath(\""+scriptfile+"\")))").c_str()); + PyObject *py_path = PyUnicode_FromString(scriptfile.c_str()); + PyObject_SetAttrString(sys, "_yosys_script_path", py_path); + Py_DECREF(py_path); + PyRun_SimpleString("import os, sys; sys.path.insert(0, os.path.dirname(os.path.abspath(sys._yosys_script_path)))"); FILE *scriptfp = fopen(scriptfile.c_str(), "r"); + if (scriptfp == nullptr) { + log_error("Failed to open file '%s' for reading.\n", scriptfile.c_str()); + } if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { - log_error("Python interpreter encountered an error:\n"); log_flush(); PyErr_Print(); + log_error("Python interpreter encountered an exception."); } #else log_error("Can't execute Python script: this version of yosys is not built with Python support enabled.\n"); From 1bf908dea8e09f29e10b7eb44501151a63c68eb3 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 1 Oct 2024 00:23:05 +0000 Subject: [PATCH 268/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1e63bdd3f..b3b8269c5 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+145 +YOSYS_VER := 0.45+148 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 997cb30f1fe2c14a16463a9e3bad969dd89a52b6 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 1 Oct 2024 13:25:07 +0200 Subject: [PATCH 269/342] cxxrtl: test stream operator --- tests/cxxrtl/test_value.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/cxxrtl/test_value.cc b/tests/cxxrtl/test_value.cc index 0750d412e..b6fe3cf4a 100644 --- a/tests/cxxrtl/test_value.cc +++ b/tests/cxxrtl/test_value.cc @@ -49,4 +49,12 @@ int main() cxxrtl::value<1> sel(0u); assert(val.template bmux<4>(sel).get() == 0xfu); } + + { + // stream operator smoke test + cxxrtl::value<8> val(0x1fu); + std::ostringstream oss; + oss << val; + assert(oss.str() == "8'1f"); + } } From ec42b42bd93d08839a0f6315b807042990f093e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Oct 2024 11:26:15 +0200 Subject: [PATCH 270/342] cellmatch: Size the `lut` attribute --- passes/techmap/cellmatch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index a21a4fbad..235599972 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -223,7 +223,7 @@ struct CellmatchPass : Pass { for (auto bit : outputs) { log_assert(bit.is_wire()); bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]); - bit.wire->attributes[ID(lut)] = luts[no++]; + bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size()); } } From 13ecbd5c76b37b8dc14b945a63d1a54b1fcfeced Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 3 Oct 2024 20:05:28 +0100 Subject: [PATCH 271/342] quicklogic: test that dividing by a constant does not infer carry chains --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/div.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys new file mode 100644 index 000000000..5ca5b3051 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -0,0 +1,14 @@ +# division by constants should not infer carry chains. +read_verilog < Date: Sun, 6 Oct 2024 08:38:16 +0200 Subject: [PATCH 272/342] docs: Simplify images generation to allow parallel build - remove the tidy target from the main target. * aux/log file are already excluded in a .gititgnore file * allow parallel generation as the tidy target imposes sequential build --- docs/source/_images/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/_images/Makefile b/docs/source/_images/Makefile index 26cc47284..cc00050f1 100644 --- a/docs/source/_images/Makefile +++ b/docs/source/_images/Makefile @@ -1,4 +1,4 @@ -all: examples all_tex tidy +all: examples all_tex # set a fake time in pdf generation to prevent unnecessary differences in output FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' From d8038c11d1f1f4adf7cc5d00c632752e402cd4e2 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 10:07:17 +1300 Subject: [PATCH 273/342] Add -j flag to make docs CI --- .github/workflows/prepare-docs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 9233e6295..19680e992 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -32,7 +32,7 @@ jobs: - name: Prepare docs shell: bash run: - make docs/prep TARGETS= EXTRA_TARGETS= + make docs/prep -j${{ env.procs }} TARGETS= EXTRA_TARGETS= - name: Upload artifact uses: actions/upload-artifact@v4 From 571d181fb4bcb7fe63f2b886e5b41f02d2519884 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 10:26:29 +1300 Subject: [PATCH 274/342] Fix top-level make docs prerequisites Add `$(TARGETS)` for gen_examples and gen_images since they need the `yosys` executable. Add guidelines source files as a prerequisite to docs/source/generated while we're at it. --- Makefile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index b3b8269c5..71e7891d9 100644 --- a/Makefile +++ b/Makefile @@ -979,16 +979,17 @@ docs/source/cmd/abc.rst: $(TARGETS) $(EXTRA_TARGETS) ./$(PROGRAM_PREFIX)yosys -p 'help -write-rst-command-reference-manual' PHONY: docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs -docs/gen_examples: +docs/gen_examples: $(TARGETS) $(Q) $(MAKE) -C docs examples -docs/gen_images: +docs/gen_images: $(TARGETS) $(Q) $(MAKE) -C docs images DOCS_GUIDELINE_FILES := GettingStarted CodingStyle -docs/guidelines docs/source/generated: +DOCS_GUIDELINE_SOURCE := $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) +docs/guidelines docs/source/generated: $(DOCS_GUIDELINE_SOURCE) $(Q) mkdir -p docs/source/generated - $(Q) cp -f $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) docs/source/generated + $(Q) cp -f $(DOCS_GUIDELINE_SOURCE) docs/source/generated # some commands return an error and print the usage text to stderr define DOC_USAGE_STDERR From 6155c59d00125c58b4eb66f419ef6485439c0de2 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 7 Oct 2024 00:21:37 +0000 Subject: [PATCH 275/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 71e7891d9..5b6fc3ff2 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+148 +YOSYS_VER := 0.45+153 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 2e1181a0923c5d2cb596a086d3435ffd1b476fb1 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 21:25:15 +1300 Subject: [PATCH 276/342] ci: Run make docs on PRs --- .github/workflows/prepare-docs.yml | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 19680e992..e2689d4df 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -1,12 +1,32 @@ name: Build docs artifact with Verific -on: push +on: [push, pull_request] jobs: + check_docs_rebuild: + runs-on: ubuntu-latest + outputs: + skip_check: ${{ steps.skip_check.outputs.should_skip }} + docs_export: ${{ steps.docs_var.outputs.docs_export }} + env: + docs_export: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + steps: + - id: skip_check + uses: fkirc/skip-duplicate-actions@v5 + with: + paths_ignore: '["**/README.md"]' + # don't cancel in case we're updating docs + cancel_others: 'false' + # only run on push *or* pull_request, not both + concurrent_skipping: ${{ env.docs_export && 'never' || 'same_content_newer'}} + - id: docs_var + run: echo "docs_export=${{ env.docs_export }}" >> $GITHUB_OUTPUT + prepare-docs: # docs builds are needed for anything on main, any tagged versions, and any tag # or branch starting with docs-preview - if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} + needs: check_docs_rebuild + if: ${{ needs.check_docs_rebuild.outputs.should_skip != 'true' }} runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys @@ -45,6 +65,7 @@ jobs: docs/source/code_examples - name: Trigger RTDs build + if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} From 468a019c30381b3cf5877430a934b139f6457a52 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 21:56:23 +1300 Subject: [PATCH 277/342] docs: Makefile tidying examples and dots are now orthogonal. --- docs/Makefile | 2 +- docs/source/code_examples/extensions/Makefile | 5 +++-- docs/source/code_examples/fifo/Makefile | 4 +++- docs/source/code_examples/intro/Makefile | 4 +++- docs/source/code_examples/macc/Makefile | 4 +++- docs/source/code_examples/opt/Makefile | 8 ++++---- docs/source/code_examples/scrambler/Makefile | 5 +++-- docs/source/code_examples/selections/Makefile | 5 +++-- docs/source/code_examples/show/Makefile | 5 +++-- docs/source/code_examples/stubnets/Makefile | 5 +++-- docs/source/code_examples/synth_flow/Makefile | 5 +++-- docs/source/code_examples/techmap/Makefile | 5 +++-- 12 files changed, 35 insertions(+), 22 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index 21fcd9623..6dbf6f490 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -238,7 +238,7 @@ Makefile-%: FORCE $(MAKE) -C $(@D) $(*F) CODE_EXAMPLES := $(wildcard source/code_examples/*/Makefile) -TEST_EXAMPLES := $(addsuffix -all,$(CODE_EXAMPLES)) +TEST_EXAMPLES := $(addsuffix -examples,$(CODE_EXAMPLES)) CLEAN_EXAMPLES := $(addsuffix -clean,$(CODE_EXAMPLES)) test-examples: $(TEST_EXAMPLES) clean-examples: $(CLEAN_EXAMPLES) diff --git a/docs/source/code_examples/extensions/Makefile b/docs/source/code_examples/extensions/Makefile index 8b5fa106a..2e621d70b 100644 --- a/docs/source/code_examples/extensions/Makefile +++ b/docs/source/code_examples/extensions/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots test0.log test1.log test2.log +.PHONY: all dots examples +all: dots examples dots: test1.dot +examples: test0.log test1.log test2.log CXXFLAGS=$(shell $(YOSYS)-config --cxxflags) DATDIR=$(shell $(YOSYS)-config --datdir) diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index 0a1186a62..de3abfd99 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -10,8 +10,10 @@ MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells DOTS := $(addsuffix .dot,$(DOT_NAMES)) MAPDOTS := $(addsuffix .dot,$(MAPDOT_NAMES)) -all: dots fifo.out fifo.stat +.PHONY: all dots examples +all: dots examples dots: $(DOTS) $(MAPDOTS) +examples: fifo.out fifo.stat $(DOTS) fifo.out: fifo.v fifo.ys $(YOSYS) fifo.ys -l fifo.out -Q -T diff --git a/docs/source/code_examples/intro/Makefile b/docs/source/code_examples/intro/Makefile index 009c82c62..31df6b623 100644 --- a/docs/source/code_examples/intro/Makefile +++ b/docs/source/code_examples/intro/Makefile @@ -4,8 +4,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: $(DOTS): counter.v counter.ys mycells.lib $(YOSYS) counter.ys diff --git a/docs/source/code_examples/macc/Makefile b/docs/source/code_examples/macc/Makefile index e93fe0657..f06c623a5 100644 --- a/docs/source/code_examples/macc/Makefile +++ b/docs/source/code_examples/macc/Makefile @@ -4,8 +4,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = macc_simple_xmap.dot macc_xilinx_xmap.dot -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys $(YOSYS) macc_simple_test.ys diff --git a/docs/source/code_examples/opt/Makefile b/docs/source/code_examples/opt/Makefile index 12c1c93b1..aa7962ca5 100644 --- a/docs/source/code_examples/opt/Makefile +++ b/docs/source/code_examples/opt/Makefile @@ -6,13 +6,13 @@ DOT_NAMES = opt_share opt_muxtree opt_merge opt_expr DOTS := $(addsuffix .dot,$(DOT_NAMES)) -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: -%_full.dot: %.ys +%.dot: %.ys $(YOSYS) $< - -%.dot: %_full.dot gvpack -u -o $@ $*_full.dot .PHONY: clean diff --git a/docs/source/code_examples/scrambler/Makefile b/docs/source/code_examples/scrambler/Makefile index de475b8b1..a9b56f8d3 100644 --- a/docs/source/code_examples/scrambler/Makefile +++ b/docs/source/code_examples/scrambler/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: scrambler_p01.dot scrambler_p02.dot +examples: scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v $(YOSYS) scrambler.ys diff --git a/docs/source/code_examples/selections/Makefile b/docs/source/code_examples/selections/Makefile index bb506ff38..3ad1bcf20 100644 --- a/docs/source/code_examples/selections/Makefile +++ b/docs/source/code_examples/selections/Makefile @@ -11,9 +11,10 @@ MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO)) SUBMOD = submod_00 submod_01 submod_02 submod_03 SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD)) -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS) +examples: select.dot: select.v select.ys $(YOSYS) select.ys diff --git a/docs/source/code_examples/show/Makefile b/docs/source/code_examples/show/Makefile index 4b269a4ab..6c1906cce 100644 --- a/docs/source/code_examples/show/Makefile +++ b/docs/source/code_examples/show/Makefile @@ -8,9 +8,10 @@ EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE)) CMOS = cmos_00 cmos_01 CMOS_DOTS := $(addsuffix .dot,$(CMOS)) -.PHONY: all dots -all: dots example.out +.PHONY: all dots examples +all: dots examples dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS) +examples: example.out splice.dot: splice.v $(YOSYS) -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v diff --git a/docs/source/code_examples/stubnets/Makefile b/docs/source/code_examples/stubnets/Makefile index ec501f006..17f700c88 100644 --- a/docs/source/code_examples/stubnets/Makefile +++ b/docs/source/code_examples/stubnets/Makefile @@ -1,6 +1,7 @@ -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: +examples: .PHONY: test test: stubnets.so diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile index 7db1c12f4..0dd37ed4d 100644 --- a/docs/source/code_examples/synth_flow/Makefile +++ b/docs/source/code_examples/synth_flow/Makefile @@ -9,9 +9,10 @@ YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys DOTS = $(addsuffix .dot,$(DOT_TARGETS)) -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: $(DOTS) +examples: %.dot: %.v %.ys $(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot' diff --git a/docs/source/code_examples/techmap/Makefile b/docs/source/code_examples/techmap/Makefile index e900fea4c..6736b0f1d 100644 --- a/docs/source/code_examples/techmap/Makefile +++ b/docs/source/code_examples/techmap/Makefile @@ -2,9 +2,10 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -.PHONY: all dots -all: dots +.PHONY: all dots examples +all: dots examples dots: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot +examples: red_or3x1.dot: red_or3x1_* $(YOSYS) red_or3x1_test.ys From 0b1b94d85eebabddd6155ed26e802f8f5927ea87 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:00:28 +1300 Subject: [PATCH 278/342] Docs: Clean example outputs --- docs/source/code_examples/fifo/Makefile | 1 + docs/source/code_examples/fifo/fifo.out | 425 ------------------ docs/source/code_examples/fifo/fifo.stat | 57 --- docs/source/code_examples/selections/Makefile | 5 +- .../code_examples/selections/sumprod.out | 38 -- docs/source/code_examples/show/Makefile | 1 + docs/source/code_examples/show/example.out | 54 --- 7 files changed, 5 insertions(+), 576 deletions(-) delete mode 100644 docs/source/code_examples/fifo/fifo.out delete mode 100644 docs/source/code_examples/fifo/fifo.stat delete mode 100644 docs/source/code_examples/selections/sumprod.out delete mode 100644 docs/source/code_examples/show/example.out diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index de3abfd99..4836dac06 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -24,3 +24,4 @@ $(MAPDOTS) fifo.stat: fifo.v fifo_map.ys .PHONY: clean clean: rm -f *.dot + rm -f fifo.out fifo.stat diff --git a/docs/source/code_examples/fifo/fifo.out b/docs/source/code_examples/fifo/fifo.out deleted file mode 100644 index ac132ee6c..000000000 --- a/docs/source/code_examples/fifo/fifo.out +++ /dev/null @@ -1,425 +0,0 @@ - --- Executing script file `fifo.ys' -- -$ yosys fifo.v - --- Parsing `fifo.v' using frontend ` -vlog2k' -- - -1. Executing Verilog-2005 frontend: fifo.v -Parsing Verilog input from `fifo.v' to AST representation. -Storing AST representation for module `$abstract\addr_gen'. -Storing AST representation for module `$abstract\fifo'. -Successfully finished Verilog frontend. -echo on - -yosys> hierarchy -top addr_gen - -2. Executing HIERARCHY pass (managing design hierarchy). - -3. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. -Generating RTLIL representation for module `\addr_gen'. - -3.1. Analyzing design hierarchy.. -Top module: \addr_gen - -3.2. Analyzing design hierarchy.. -Top module: \addr_gen -Removing unused module `$abstract\fifo'. -Removing unused module `$abstract\addr_gen'. -Removed 2 unused modules. - -yosys> select -module addr_gen - -yosys [addr_gen]> select -list -addr_gen -addr_gen/$1\addr[7:0] -addr_gen/$add$fifo.v:19$3_Y -addr_gen/$eq$fifo.v:16$2_Y -addr_gen/$0\addr[7:0] -addr_gen/addr -addr_gen/rst -addr_gen/clk -addr_gen/en -addr_gen/$add$fifo.v:19$3 -addr_gen/$eq$fifo.v:16$2 -addr_gen/$proc$fifo.v:0$4 -addr_gen/$proc$fifo.v:12$1 - -yosys [addr_gen]> select t:* - -yosys [addr_gen]*> select -list -addr_gen/$add$fifo.v:19$3 -addr_gen/$eq$fifo.v:16$2 - -yosys [addr_gen]*> select -set new_cells % - -yosys [addr_gen]*> select -clear - -yosys> show -format dot -prefix addr_gen_show addr_gen - -4. Generating Graphviz representation of design. -Writing dot description to `addr_gen_show.dot'. -Dumping module addr_gen to page 1. - -yosys> show -format dot -prefix new_cells_show -notitle @new_cells - -5. Generating Graphviz representation of design. -Writing dot description to `new_cells_show.dot'. -Dumping selected parts of module addr_gen to page 1. - -yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier - -6. Generating Graphviz representation of design. -Writing dot description to `addr_gen_hier.dot'. -Dumping module addr_gen to page 1. - -yosys> proc -noopt - -7. Executing PROC pass (convert processes to netlists). - -yosys> proc_clean - -7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -yosys> proc_rmdead - -7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 2 switch rules as full_case in process $proc$fifo.v:12$1 in module addr_gen. -Removed a total of 0 dead cases. - -yosys> proc_prune - -7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -yosys> proc_init - -7.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\addr_gen.$proc$fifo.v:0$4'. - Set init value: \addr = 8'00000000 - -yosys> proc_arst - -7.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \rst in `\addr_gen.$proc$fifo.v:12$1'. - -yosys> proc_rom - -7.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -yosys> proc_mux - -7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'. -Creating decoders for process `\addr_gen.$proc$fifo.v:12$1'. - 1/1: $0\addr[7:0] - -yosys> proc_dlatch - -7.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -yosys> proc_dff - -7.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:12$1'. - created $adff cell `$procdff$10' with positive edge clock and positive level reset. - -yosys> proc_memwr - -7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -yosys> proc_clean - -7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `addr_gen.$proc$fifo.v:0$4'. -Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:12$1'. -Removing empty process `addr_gen.$proc$fifo.v:12$1'. -Cleaned up 2 empty switches. - -yosys> select -set new_cells t:$mux t:*dff - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc - -8. Generating Graphviz representation of design. -Writing dot description to `addr_gen_proc.dot'. -Dumping module addr_gen to page 1. - -yosys> opt_expr - -9. Executing OPT_EXPR pass (perform const folding). -Optimizing module addr_gen. - -yosys> clean -Removed 0 unused cells and 4 unused wires. - -yosys> select -set new_cells t:$eq - -yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean - -10. Generating Graphviz representation of design. -Writing dot description to `addr_gen_clean.dot'. -Dumping module addr_gen to page 1. - -yosys> design -reset - -yosys> read_verilog fifo.v - -11. Executing Verilog-2005 frontend: fifo.v -Parsing Verilog input from `fifo.v' to AST representation. -Generating RTLIL representation for module `\addr_gen'. -Generating RTLIL representation for module `\fifo'. -Successfully finished Verilog frontend. - -yosys> hierarchy -check -top fifo - -12. Executing HIERARCHY pass (managing design hierarchy). - -12.1. Analyzing design hierarchy.. -Top module: \fifo -Used module: \addr_gen -Parameter \MAX_DATA = 256 - -12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. -Parameter \MAX_DATA = 256 -Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. -Parameter \MAX_DATA = 256 -Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. - -12.3. Analyzing design hierarchy.. -Top module: \fifo -Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 - -12.4. Analyzing design hierarchy.. -Top module: \fifo -Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 -Removing unused module `\addr_gen'. -Removed 1 unused modules. - -yosys> proc - -13. Executing PROC pass (convert processes to netlists). - -yosys> proc_clean - -13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -yosys> proc_rmdead - -13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 2 switch rules as full_case in process $proc$fifo.v:62$24 in module fifo. -Marked 1 switch rules as full_case in process $proc$fifo.v:36$16 in module fifo. -Marked 2 switch rules as full_case in process $proc$fifo.v:12$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. -Removed a total of 0 dead cases. - -yosys> proc_prune - -13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 6 assignments to connections. - -yosys> proc_init - -13.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\fifo.$proc$fifo.v:0$31'. - Set init value: \count = 9'000000000 -Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. - Set init value: \addr = 8'00000000 - -yosys> proc_arst - -13.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \rst in `\fifo.$proc$fifo.v:62$24'. -Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - -yosys> proc_rom - -13.6. Executing PROC_ROM pass (convert switches to ROMs). -Converted 0 switches. - - -yosys> proc_mux - -13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\fifo.$proc$fifo.v:0$31'. -Creating decoders for process `\fifo.$proc$fifo.v:62$24'. - 1/1: $0\count[8:0] -Creating decoders for process `\fifo.$proc$fifo.v:36$16'. - 1/3: $1$memwr$\data$fifo.v:38$15_EN[7:0]$22 - 2/3: $1$memwr$\data$fifo.v:38$15_DATA[7:0]$21 - 3/3: $1$memwr$\data$fifo.v:38$15_ADDR[7:0]$20 -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - 1/1: $0\addr[7:0] - -yosys> proc_dlatch - -13.8. Executing PROC_DLATCH pass (convert process syncs to latches). - -yosys> proc_dff - -13.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:62$24'. - created $adff cell `$procdff$55' with positive edge clock and positive level reset. -Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$56' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_ADDR' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$57' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_DATA' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$58' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:38$15_EN' using process `\fifo.$proc$fifo.v:36$16'. - created $dff cell `$procdff$59' with positive edge clock. -Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. - created $adff cell `$procdff$60' with positive edge clock and positive level reset. - -yosys> proc_memwr - -13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -yosys> proc_clean - -13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `fifo.$proc$fifo.v:0$31'. -Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:62$24'. -Removing empty process `fifo.$proc$fifo.v:62$24'. -Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:36$16'. -Removing empty process `fifo.$proc$fifo.v:36$16'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. -Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$32'. -Cleaned up 5 empty switches. - -yosys> opt_expr -keepdc - -13.12. Executing OPT_EXPR pass (perform const folding). -Optimizing module fifo. -Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - -yosys> select -set new_cells t:$memrd - -yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci* - -14. Generating Graphviz representation of design. -Writing dot description to `rdata_proc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> flatten - -15. Executing FLATTEN pass (flatten design). -Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. - - -yosys> clean -Removed 3 unused cells and 25 unused wires. - -yosys> select -set rdata_path o:rdata %ci* - -yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path - -16. Generating Graphviz representation of design. -Writing dot description to `rdata_flat.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> opt_dff - -17. Executing OPT_DFF pass (perform DFF optimizations). -Adding EN signal on $procdff$55 ($adff) from module fifo (D = $0\count[8:0], Q = \count). -Adding EN signal on $flatten\fifo_writer.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$51_Y, Q = \fifo_writer.addr). -Adding EN signal on $flatten\fifo_reader.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$51_Y, Q = \fifo_reader.addr). - -yosys> select -set new_cells t:$adffe - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci* - -18. Generating Graphviz representation of design. -Writing dot description to `rdata_adffe.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> wreduce - -19. Executing WREDUCE pass (reducing word size of cells). -Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$27 ($add). -Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$27 ($add). -Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$30 ($sub). -Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$30 ($sub). -Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$66 ($ne). -Removed cell fifo.$flatten\fifo_writer.$procmux$53 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$34 ($add). -Removed cell fifo.$flatten\fifo_reader.$procmux$53 ($mux). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$34 ($add). -Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$27_Y. -Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$34_Y. - -yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci* - -20. Generating Graphviz representation of design. -Writing dot description to `rdata_wreduce.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> opt_clean - -21. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \fifo.. -Removed 0 unused cells and 4 unused wires. - - -yosys> memory_dff - -22. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\data'[0] in module `\fifo': merging output FF to cell. - Write port 0: non-transparent. - -yosys> select -set new_cells t:$memrd_v2 - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci* - -23. Generating Graphviz representation of design. -Writing dot description to `rdata_memrdv2.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> alumacc - -24. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module fifo: - creating $macc model for $add$fifo.v:66$27 ($add). - creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$34 ($add). - creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$34 ($add). - creating $macc model for $sub$fifo.v:68$30 ($sub). - creating $alu model for $macc $sub$fifo.v:68$30. - creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$34. - creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$34. - creating $alu model for $macc $add$fifo.v:66$27. - creating $alu cell for $add$fifo.v:66$27: $auto$alumacc.cc:485:replace_alu$80 - creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$83 - creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$34: $auto$alumacc.cc:485:replace_alu$86 - creating $alu cell for $sub$fifo.v:68$30: $auto$alumacc.cc:485:replace_alu$89 - created 4 $alu and 0 $macc cells. - -yosys> select -set new_cells t:$alu t:$macc - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* - -25. Generating Graphviz representation of design. -Writing dot description to `rdata_alumacc.dot'. -Dumping selected parts of module fifo to page 1. - -yosys> memory_collect - -26. Executing MEMORY_COLLECT pass (generating $mem cells). - -yosys> select -set new_cells t:$mem_v2 - -yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% - -yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path - -27. Generating Graphviz representation of design. -Writing dot description to `rdata_coarse.dot'. -Dumping selected parts of module fifo to page 1. diff --git a/docs/source/code_examples/fifo/fifo.stat b/docs/source/code_examples/fifo/fifo.stat deleted file mode 100644 index 263c618e3..000000000 --- a/docs/source/code_examples/fifo/fifo.stat +++ /dev/null @@ -1,57 +0,0 @@ - -yosys> stat - -2. Printing statistics. - -=== fifo === - - Number of wires: 28 - Number of wire bits: 219 - Number of public wires: 9 - Number of public wire bits: 45 - Number of memories: 1 - Number of memory bits: 2048 - Number of processes: 3 - Number of cells: 9 - $add 1 - $logic_and 2 - $logic_not 2 - $memrd 1 - $sub 1 - addr_gen 2 - -=== addr_gen === - - Number of wires: 8 - Number of wire bits: 60 - Number of public wires: 4 - Number of public wire bits: 11 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 2 - Number of cells: 2 - $add 1 - $eq 1 - - -yosys> stat -top fifo - -17. Printing statistics. - -=== fifo === - - Number of wires: 94 - Number of wire bits: 260 - Number of public wires: 94 - Number of public wire bits: 260 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 138 - $scopeinfo 2 - SB_CARRY 26 - SB_DFF 26 - SB_DFFER 25 - SB_LUT4 58 - SB_RAM40_4K 1 - diff --git a/docs/source/code_examples/selections/Makefile b/docs/source/code_examples/selections/Makefile index 3ad1bcf20..46a09060a 100644 --- a/docs/source/code_examples/selections/Makefile +++ b/docs/source/code_examples/selections/Makefile @@ -14,12 +14,12 @@ SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD)) .PHONY: all dots examples all: dots examples dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS) -examples: +examples: sumprod.out select.dot: select.v select.ys $(YOSYS) select.ys -$(SUMPROD_DOTS): sumprod.v sumprod.ys +$(SUMPROD_DOTS) sumprod.out: sumprod.v sumprod.ys $(YOSYS) sumprod.ys $(MEMDEMO_DOTS): memdemo.v memdemo.ys @@ -31,3 +31,4 @@ $(SUBMOD_DOTS): memdemo.v submod.ys .PHONY: clean clean: rm -rf *.dot + rm -f sumprod.out diff --git a/docs/source/code_examples/selections/sumprod.out b/docs/source/code_examples/selections/sumprod.out deleted file mode 100644 index f7c259499..000000000 --- a/docs/source/code_examples/selections/sumprod.out +++ /dev/null @@ -1,38 +0,0 @@ - - - attribute \src "sumprod.v:4.21-4.25" - wire width 8 output 5 \prod - - attribute \src "sumprod.v:10.17-10.26" - cell $mul $mul$sumprod.v:10$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $mul$sumprod.v:10$3_Y - connect \B \c - connect \Y \prod - end - - - attribute \src "sumprod.v:10.17-10.22" - wire width 8 $mul$sumprod.v:10$3_Y - - attribute \src "sumprod.v:3.21-3.22" - wire width 8 input 3 \c - - attribute \src "sumprod.v:4.21-4.25" - wire width 8 output 5 \prod - - attribute \src "sumprod.v:10.17-10.26" - cell $mul $mul$sumprod.v:10$4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $mul$sumprod.v:10$3_Y - connect \B \c - connect \Y \prod - end diff --git a/docs/source/code_examples/show/Makefile b/docs/source/code_examples/show/Makefile index 6c1906cce..649691299 100644 --- a/docs/source/code_examples/show/Makefile +++ b/docs/source/code_examples/show/Makefile @@ -28,3 +28,4 @@ $(CMOS_DOTS): cmos.v cmos.ys .PHONY: clean clean: rm -rf *.dot + rm -f example.out diff --git a/docs/source/code_examples/show/example.out b/docs/source/code_examples/show/example.out deleted file mode 100644 index b8569e640..000000000 --- a/docs/source/code_examples/show/example.out +++ /dev/null @@ -1,54 +0,0 @@ - --- Executing script file `example_lscd.ys' -- - -1. Executing Verilog-2005 frontend: example.v -Parsing Verilog input from `example.v' to AST representation. -Generating RTLIL representation for module `\example'. -Successfully finished Verilog frontend. -echo on - -yosys> ls - -1 modules: - example - -yosys> cd example - -yosys [example]> ls - -8 wires: - $0\y[1:0] - $add$example.v:5$2_Y - $ternary$example.v:5$3_Y - a - b - c - clk - y - -2 cells: - $add$example.v:5$2 - $ternary$example.v:5$3 - -1 processes: - $proc$example.v:3$1 - -yosys [example]> dump $2 - - - attribute \src "example.v:5.22-5.27" - cell $add $add$example.v:5$2 - parameter \Y_WIDTH 2 - parameter \B_WIDTH 1 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \A_SIGNED 0 - connect \Y $add$example.v:5$2_Y - connect \B \b - connect \A \a - end - -yosys [example]> cd .. - -yosys> echo off -echo off From 13d7b5fd6aab92e1f28900e778bff1c9505f5e34 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:01:01 +1300 Subject: [PATCH 279/342] Docs: Ignore example outputs --- docs/source/code_examples/.gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/source/code_examples/.gitignore b/docs/source/code_examples/.gitignore index b4a858a01..0eca4be80 100644 --- a/docs/source/code_examples/.gitignore +++ b/docs/source/code_examples/.gitignore @@ -1,2 +1,5 @@ *.dot *.pdf +*.out +*.log +*.stat From 3e6e8c892e9f44c933c2ffc4c660cc38370ea69d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Oct 2024 11:09:02 +0200 Subject: [PATCH 280/342] Bump abc submodule --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 2188bc712..cac8f99ea 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 2188bc71228b0788569d83ad2b7e7b91ca5dcc09 +Subproject commit cac8f99eaa220a5e3db5caeb87cef0a975c953a2 From edf29e725e82a1bf5914089374f4a0e237ae51db Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:20:22 +1300 Subject: [PATCH 281/342] Docs: Add functional_ir to index --- docs/source/yosys_internals/extending_yosys/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 2a4d2dfef..88f36d526 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -10,5 +10,6 @@ of interest for developers looking to customise Yosys builds. extensions build_verific + functional_ir test_suites From 33930e44ac70313b12fe6945450cceb45b7b1202 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:22:10 +1300 Subject: [PATCH 282/342] ci: Test build docs --- .github/workflows/test-build.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index e5aed6af3..41e197424 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -189,3 +189,8 @@ jobs: shell: bash run: | make -C docs test -j${{ env.procs }} + + - name: Test build docs + shell: bash + run: | + make -C docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From f72d0219d151183ced4de2fe2be533c102b645b3 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 7 Oct 2024 22:52:33 +1300 Subject: [PATCH 283/342] Update test-build.yml Call make docs from root --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 41e197424..1502d8aa0 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -193,4 +193,4 @@ jobs: - name: Test build docs shell: bash run: | - make -C docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From d4e009fc2f7152cd3c26f7776c711745a5a90257 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 2 Oct 2024 11:28:19 +0200 Subject: [PATCH 284/342] aiger2: Add TODO --- backends/aiger2/aiger.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 6af7b0948..89ef06a37 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -20,6 +20,7 @@ // TODOs: // - gracefully handling inout ports (an error message probably) // - undriven wires +// - zero-width operands #include "kernel/register.h" #include "kernel/celltypes.h" From e58a9b6ab6cd990a5f2cbe396972a1bdcd7ccb7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 9 Apr 2024 18:30:51 +0200 Subject: [PATCH 285/342] abc9: Understand ASIC options similar to `abc` --- passes/techmap/abc9.cc | 3 ++- passes/techmap/abc9_exe.cc | 43 +++++++++++++++++++++++++++++++------- 2 files changed, 38 insertions(+), 8 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 876917e56..a96a82659 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -220,7 +220,8 @@ struct Abc9Pass : public ScriptPass std::string arg = args[argidx]; if ((arg == "-exe" || arg == "-script" || arg == "-D" || /*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" || - /*arg == "-box" ||*/ arg == "-W") && + /*arg == "-box" ||*/ arg == "-W" || arg == "-genlib" || + arg == "-constr" || arg == "-dont_use" || arg == "-liberty") && argidx+1 < args.size()) { if (arg == "-lut" || arg == "-luts") lut_mode = true; diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 8e02e25a4..e62850aa4 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -166,9 +166,9 @@ struct abc9_output_filter void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file, vector lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, - bool show_tempdir, std::string box_file, std::string lut_file, - std::string wire_delay, std::string tempdir_name -) + bool show_tempdir, std::string box_file, std::string lut_file, std::vector genlib_files, + std::vector liberty_files, std::string wire_delay, std::string tempdir_name, + std::string constr_file, std::vector dont_use_cells) { std::string abc9_script; @@ -176,8 +176,19 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); else if (!lut_file.empty()) abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str()); - else - log_abort(); + else if (!liberty_files.empty() || !genlib_files.empty()) { + std::string dont_use_args; + for (std::string dont_use_cell : dont_use_cells) { + dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); + } + for (std::string liberty_file : liberty_files) { + abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); + } + for (std::string liberty_file : genlib_files) + abc9_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); + if (!constr_file.empty()) + abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str()); + } log_assert(!box_file.empty()); abc9_script += stringf("read_box \"%s\"; ", box_file.c_str()); @@ -411,7 +422,8 @@ struct Abc9ExePass : public Pass { log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n"); std::string exe_file = yosys_abc_executable; - std::string script_file, clk_str, box_file, lut_file; + std::string script_file, clk_str, box_file, lut_file, constr_file; + std::vector genlib_files, liberty_files, dont_use_cells; std::string delay_target, lutin_shared = "-S 1", wire_delay; std::string tempdir_name; bool fast_mode = false, dff_mode = false; @@ -499,6 +511,22 @@ struct Abc9ExePass : public Pass { tempdir_name = args[++argidx]; continue; } + if (arg == "-genlib" && argidx+1 < args.size()) { + genlib_files.push_back(args[++argidx]); + continue; + } + if (arg == "-liberty" && argidx+1 < args.size()) { + liberty_files.push_back(args[++argidx]); + continue; + } + if (arg == "-dont_use" && argidx+1 < args.size()) { + dont_use_cells.push_back(args[++argidx]); + continue; + } + if (arg == "-constr" && argidx+1 < args.size()) { + constr_file = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -562,7 +590,8 @@ struct Abc9ExePass : public Pass { abc9_module(design, script_file, exe_file, lut_costs, dff_mode, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, wire_delay, tempdir_name); + box_file, lut_file, genlib_files, liberty_files, wire_delay, tempdir_name, + constr_file, dont_use_cells); } } Abc9ExePass; From 2b1b5652f1106466dfc538d52bffbe336013de85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 4 Oct 2024 10:02:53 +0200 Subject: [PATCH 286/342] Adjust `read_xaiger2` prints --- frontends/aiger2/xaiger.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index b60cd0c88..56fa5a2a6 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -222,10 +222,12 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } + log_debug("reading 'M' (second pass)\n"); + f->seekg(extensions_start); bool read_mapping = false; uint32_t no_cells, no_instances; @@ -272,7 +274,6 @@ struct Xaiger2Frontend : public Frontend { auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); instance->setPort(cell.out, out_w); bits[out_lit] = out_w; - log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type)); for (auto in : cell.ins) { uint32_t in_lit = read_be32(*f); log_assert(out_lit < bits.size()); @@ -285,7 +286,7 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } @@ -356,7 +357,7 @@ struct Xaiger2Frontend : public Frontend { } else { uint32_t len = read_be32(*f); f->ignore(len); - log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); + log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len); } } @@ -387,7 +388,6 @@ struct Xaiger2Frontend : public Frontend { int lit = outputs[po_idx]; if (lit < 0 || lit >= bits.size()) log_error("Bad map file (5)\n"); - log("output=%d lit=%d\n", po_idx, lit); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); Wire *w = module->wire(name); From 8d12492610e0fdfff84b12fb0fc337daf4e74055 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 4 Oct 2024 10:03:30 +0200 Subject: [PATCH 287/342] read_xaiger2: Fix detecting the end of extensions --- frontends/aiger2/xaiger.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 56fa5a2a6..4c7305876 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -219,6 +219,8 @@ struct Xaiger2Frontend : public Frontend { log_assert(pi_num + ci_counter == ci_num); } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); @@ -283,6 +285,8 @@ struct Xaiger2Frontend : public Frontend { } } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); @@ -354,6 +358,8 @@ struct Xaiger2Frontend : public Frontend { log_assert(po_num + co_counter == co_num); } else if (c == '\n') { break; + } else if (c == 'c') { + break; } else { uint32_t len = read_be32(*f); f->ignore(len); From f7c7371ea9157ef1199c4a76d20364b3699313b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:03:52 +0200 Subject: [PATCH 288/342] aiger2: Fix relative ordering of PI/POs and box I/Os --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 89ef06a37..9df9c9b20 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -934,7 +934,7 @@ struct XAigerWriter : AigerWriter { }); for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, true); + append_box_ports(box, cursor, false); holes_module = design->addModule(NEW_ID); std::vector holes_pis; @@ -1024,7 +1024,7 @@ struct XAigerWriter : AigerWriter { } for (auto [cursor, box, def] : opaque_boxes) - append_box_ports(box, cursor, false); + append_box_ports(box, cursor, true); write_be32(h_buffer, 1); write_be32(h_buffer, pis.size()); From 4c0a8a132614ee354913815f3b651f8735a3a730 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:04:45 +0200 Subject: [PATCH 289/342] aiger2: Add analysis step to order boxes --- backends/aiger2/aiger.cc | 122 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 9df9c9b20..b6994c221 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -537,6 +537,11 @@ struct Index { } }; + bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + { + return false; + } + Lit visit(HierCursor &cursor, SigBit bit) { if (!bit.wire) { @@ -554,6 +559,12 @@ struct Index { return lits[idx]; } + // provide means for the derived class to override + // the visit behavior + if ((static_cast(this))->visit_hook(idx, cursor, bit)) { + return lits[idx]; + } + Lit ret; if (!bit.wire->port_input) { // an output of a cell @@ -791,6 +802,102 @@ struct AigerWriter : Index { } }; +struct XAigerAnalysis : Index { + const static int CONST_FALSE = 0; + const static int CONST_TRUE = 0; + const static constexpr int EMPTY_LIT = -1; + + XAigerAnalysis() + { + allow_blackboxes = true; + + // Disable const folding and strashing as literal values are not unique + const_folding = false; + strashing = false; + } + + static int negate(int lit) + { + return lit; + } + + int emit_gate(int a, int b) + { + return max(a, b) + 1; + } + + pool seen; + + bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + { + log_assert(cursor.is_top()); // TOOD: fix analyzer to work with hierarchy + + if (bit.wire->port_input) + return false; + + Cell *driver = bit.wire->driverCell(); + if (!driver->type.isPublic()) + return false; + + Module *mod = design->module(driver->type); + log_assert(mod); + if (!mod->has_attribute(ID::abc9_box_id)) + return false; + + int max = 1; + for (auto wire : mod->wires()) + if (wire->port_input) + for (int i = 0; i < wire->width; i++) { + int ilevel = visit(cursor, driver->getPort(wire->name)[i]); + max = std::max(max, ilevel + 1); + } + lits[idx] = max; + + if (!seen.count(driver)) + seen.insert(driver); + + return true; + } + + void analyze(Module *top) + { + setup(top); + + for (auto id : top->ports) { + Wire *w = top->wire(id); + log_assert(w); + if (w->port_input) + for (int i = 0; i < w->width; i++) + pi_literal(SigBit(w, i)) = 0; + } + + HierCursor cursor; + for (auto box : top_minfo->found_blackboxes) { + Module *def = design->module(box->type); + if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + for (auto &conn : box->connections_) + if (box->output(conn.first)) + for (auto bit : conn.second) + pi_literal(bit, &cursor) = 0; + } + + for (auto w : top->wires()) + if (w->port_output) { + for (auto bit : SigSpec(w)) + (void) eval_po(bit); + } + + for (auto box : top_minfo->found_blackboxes) { + Module *def = design->module(box->type); + if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id))) + for (auto &conn : box->connections_) + if (box->input(conn.first)) + for (auto bit : conn.second) + (void) eval_po(bit); + } + } +}; + struct XAigerWriter : AigerWriter { XAigerWriter() { @@ -897,6 +1004,11 @@ struct XAigerWriter : AigerWriter { void prep_boxes(int pending_pos_num) { + XAigerAnalysis analysis; + log_debug("preforming analysis on '%s'\n", log_id(top)); + analysis.analyze(top); + log_debug("analysis on '%s' done\n", log_id(top)); + // boxes which have timing data, maybe a whitebox model std::vector> nonopaque_boxes; // boxes which are fully opaque @@ -942,6 +1054,16 @@ struct XAigerWriter : AigerWriter { int box_seq = 0; + std::vector boxes_order(analysis.seen.begin(), analysis.seen.end()); + std::reverse(boxes_order.begin(), boxes_order.end()); + + nonopaque_boxes.clear(); + for (auto box : boxes_order) { + HierCursor cursor; + Module *def = design->module(box->type); + nonopaque_boxes.push_back(std::make_tuple(cursor, box, def)); + } + for (auto [cursor, box, def] : nonopaque_boxes) { // use `def->name` not `box->type` as we want the derived type Cell *holes_wb = holes_module->addCell(NEW_ID, def->name); From b8f389370b0fb3ecb520a9a02d0cda744315aea5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:05:44 +0200 Subject: [PATCH 290/342] aiger2: Convert x-states to zeroes --- backends/aiger2/aiger.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index b6994c221..97b506178 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -549,6 +549,8 @@ struct Index { return CTRUE; else if (bit == State::S0) return CFALSE; + else if (bit == State::Sx) + return CFALSE; else log_error("Unhandled state %s\n", log_signal(bit)); } From e0a86d5483804f4c4977c353232e64e70c539582 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:07:25 +0200 Subject: [PATCH 291/342] abc_new: Start new command for aiger2-based round trip --- passes/techmap/Makefile.inc | 2 + passes/techmap/abc_new.cc | 153 ++++++++++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 passes/techmap/abc_new.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 6bf40434d..4e1d16744 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -12,10 +12,12 @@ OBJS += passes/techmap/abc.o OBJS += passes/techmap/abc9.o OBJS += passes/techmap/abc9_exe.o OBJS += passes/techmap/abc9_ops.o +OBJS += passes/techmap/abc_new.o ifneq ($(ABCEXTERNAL),) passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' passes/techmap/abc9_exe.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' +passes/techmap/abc_new.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' endif endif diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc new file mode 100644 index 000000000..eefe34f84 --- /dev/null +++ b/passes/techmap/abc_new.cc @@ -0,0 +1,153 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Martin Povišer + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/rtlil.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct AbcNewPass : public ScriptPass { + AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)") + { + experimental(); + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" abc_new [options] [selection]\n"); + log("\n"); + log("This command uses the ABC tool [1] to optimize the current design and map it to\n"); + log("the target standard cell library.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -exe \n"); + log(" -script \n"); + log(" -D \n"); + log(" -constr \n"); + log(" -dont_use \n"); + log(" -liberty \n"); + log(" these options are passed on to the 'abc9_exe' command which invokes\n"); + log(" the ABC tool on individual modules of the design. please see\n"); + log(" 'help abc9_exe' for more details\n"); + log("\n"); + log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); + log("\n"); + help_script(); + log("\n"); + } + + bool cleanup; + std::string abc_exe_options; + + void execute(std::vector args, RTLIL::Design *d) override + { + std::string run_from, run_to; + cleanup = true; + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-exe" || args[argidx] == "-script" || + args[argidx] == "-D" || + args[argidx] == "-constr" || args[argidx] == "-dont_use" || + args[argidx] == "-liberty") { + abc_exe_options += " " + args[argidx] + " " + args[argidx + 1]; + argidx++; + } else if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[++argidx].find(':'); + if (pos == std::string::npos) + break; + run_from = args[argidx].substr(0, pos); + run_to = args[argidx].substr(pos + 1); + } else if (args[argidx] == "-nocleanup") { + cleanup = false; + } else { + break; + } + } + extra_args(args, argidx, d); + + log_header(d, "Executing ABC_NEW pass.\n"); + log_push(); + run_script(d, run_from, run_to); + log_pop(); + } + + void script() override + { + if (check_label("check")) { + run("abc9_ops -check"); + } + + if (check_label("prep_boxes")) { + run("box_derive"); + run("abc9_ops -prep_box"); + } + + if (check_label("map")) { + std::vector selected_modules; + + if (!help_mode) { + selected_modules = active_design->selected_whole_modules_warn(); + active_design->selection_stack.emplace_back(false); + } else { + selected_modules = {nullptr}; + run("foreach module in selection"); + } + + for (auto mod : selected_modules) { + std::string tmpdir = ""; + std::string modname = ""; + std::string exe_options = "[options]"; + if (!help_mode) { + tmpdir = cleanup ? (get_base_tmpdir() + "/") : "_tmp_"; + tmpdir += proc_program_prefix() + "yosys-abc-XXXXXX"; + tmpdir = make_temp_dir(tmpdir); + modname = mod->name.str(); + exe_options = abc_exe_options; + log_header(active_design, "Mapping module '%s'.\n", log_id(mod)); + log_push(); + active_design->selection().select(mod); + } + + run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str())); + run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str())); + run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str())); + run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig", + modname.c_str(), tmpdir.c_str(), tmpdir.c_str())); + + if (!help_mode) { + active_design->selection().selected_modules.clear(); + log_pop(); + } + } + + if (!help_mode) { + active_design->selection_stack.pop_back(); + } + } + } +} AbcNewPass; + +PRIVATE_NAMESPACE_END From 81688e3ba2fb4a1dba403541512825264281df76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:12:16 +0200 Subject: [PATCH 292/342] aigsize: Remove --- backends/aiger2/aiger.cc | 66 ---------------------------------------- 1 file changed, 66 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 97b506178..336dad7a7 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1434,70 +1434,4 @@ struct XAiger2Backend : Backend { } } XAiger2Backend; -struct AIGCounter : Index { - typedef int Lit; - const static Lit CONST_FALSE = -1; - const static Lit CONST_TRUE = 1; - const static constexpr Lit EMPTY_LIT = 0; - static Lit negate(Lit lit) { return -lit; } - int nvars = 1; - int ngates = 0; - - Lit emit_gate([[maybe_unused]] Lit a, [[maybe_unused]] Lit b) - { - ngates++; - return ++nvars; - } - - void count() { - // populate inputs - for (auto w : top->wires()) - if (w->port_input) - for (int i = 0; i < w->width; i++) - pi_literal(SigBit(w, i)) = ++nvars; - - for (auto w : top->wires()) - if (w->port_output) { - for (auto bit : SigSpec(w)) - (void) eval_po(bit); - } - } -}; - -struct AigsizePass : Pass { - AigsizePass() : Pass("aigsize", "estimate AIG size for design") {} - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing AIGSIZE pass. (size design AIG)\n"); - - size_t argidx; - AIGCounter writer; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-strash") - writer.strashing = true; - else if (args[argidx] == "-flatten") - writer.flatten = true; - else - break; - } - extra_args(args, argidx, design); - - Module *top = design->top_module(); - - if (!top || !design->selected_whole_module(top)) - log_cmd_error("No top module selected\n"); - - design->bufNormalize(true); - writer.setup(top); - writer.count(); - log("Counted %d gates\n", writer.ngates); - - // we are leaving the sacred land, un-bufnormalize - // (if not, this will lead to bugs: the buf-normalized - // flag must not be kept on past the code that can work - // with it) - design->bufNormalize(false); - } -} AigsizePass; - PRIVATE_NAMESPACE_END From ac79a052ba9013580eadc26f4c9032819f162cb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:12:29 +0200 Subject: [PATCH 293/342] aiger2: Adjust help --- backends/aiger2/aiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 336dad7a7..a6a4b841a 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1300,7 +1300,7 @@ struct XAigerWriter : AigerWriter { }; struct Aiger2Backend : Backend { - Aiger2Backend() : Backend("aiger2", "write design to AIGER file (new)") + Aiger2Backend() : Backend("aiger2", "(experimental) write design to AIGER file") { experimental(); } @@ -1384,7 +1384,7 @@ struct Aiger2Backend : Backend { } Aiger2Backend; struct XAiger2Backend : Backend { - XAiger2Backend() : Backend("xaiger2", "write design to XAIGER file (new)") + XAiger2Backend() : Backend("xaiger2", "(experimental) write design to XAIGER file") { experimental(); } From 3b6dcc7bd0370bff5fde16cfa0406bc60356eace Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:30:22 +0200 Subject: [PATCH 294/342] abc9_exe: Remove `-genlib` option --- passes/techmap/abc9_exe.cc | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index e62850aa4..ccfc7a7f8 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -166,7 +166,7 @@ struct abc9_output_filter void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe_file, vector lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode, - bool show_tempdir, std::string box_file, std::string lut_file, std::vector genlib_files, + bool show_tempdir, std::string box_file, std::string lut_file, std::vector liberty_files, std::string wire_delay, std::string tempdir_name, std::string constr_file, std::vector dont_use_cells) { @@ -176,7 +176,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe abc9_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); else if (!lut_file.empty()) abc9_script += stringf("read_lut \"%s\"; ", lut_file.c_str()); - else if (!liberty_files.empty() || !genlib_files.empty()) { + else if (!liberty_files.empty()) { std::string dont_use_args; for (std::string dont_use_cell : dont_use_cells) { dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); @@ -184,8 +184,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe for (std::string liberty_file : liberty_files) { abc9_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); } - for (std::string liberty_file : genlib_files) - abc9_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); if (!constr_file.empty()) abc9_script += stringf("read_constr -v \"%s\"; ", constr_file.c_str()); } @@ -423,7 +421,7 @@ struct Abc9ExePass : public Pass { std::string exe_file = yosys_abc_executable; std::string script_file, clk_str, box_file, lut_file, constr_file; - std::vector genlib_files, liberty_files, dont_use_cells; + std::vector liberty_files, dont_use_cells; std::string delay_target, lutin_shared = "-S 1", wire_delay; std::string tempdir_name; bool fast_mode = false, dff_mode = false; @@ -511,10 +509,6 @@ struct Abc9ExePass : public Pass { tempdir_name = args[++argidx]; continue; } - if (arg == "-genlib" && argidx+1 < args.size()) { - genlib_files.push_back(args[++argidx]); - continue; - } if (arg == "-liberty" && argidx+1 < args.size()) { liberty_files.push_back(args[++argidx]); continue; @@ -590,7 +584,7 @@ struct Abc9ExePass : public Pass { abc9_module(design, script_file, exe_file, lut_costs, dff_mode, delay_target, lutin_shared, fast_mode, show_tempdir, - box_file, lut_file, genlib_files, liberty_files, wire_delay, tempdir_name, + box_file, lut_file, liberty_files, wire_delay, tempdir_name, constr_file, dont_use_cells); } } Abc9ExePass; From 2e587c835fd95eac7ac5114f26f07f9f3f5982e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:30:37 +0200 Subject: [PATCH 295/342] abc9_exe: Document SC mapping options --- passes/techmap/abc9_exe.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index ccfc7a7f8..651a8375c 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -368,6 +368,26 @@ struct Abc9ExePass : public Pass { log(" of output quality):\n"); log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); log("\n"); + log(" -constr \n"); + log(" pass this file with timing constraints to ABC.\n"); + log(" use with -liberty.\n"); + log("\n"); + log(" a constr file contains two lines:\n"); + log(" set_driving_cell \n"); + log(" set_load \n"); + log("\n"); + log(" the set_driving_cell statement defines which cell type is assumed to\n"); + log(" drive the primary inputs and the set_load statement sets the load in\n"); + log(" femtofarads for each primary output.\n"); + log("\n"); + log(" -liberty \n"); + log(" read the given Liberty file as a description of the target cell library.\n"); + log(" this option can be used multiple times.\n"); + log("\n"); + log(" -dont_use \n"); + log(" avoid usage of the technology cell when mapping the design.\n"); + log(" this option can be used multiple times.\n"); + log("\n"); log(" -D \n"); log(" set delay target. the string {D} in the default scripts above is\n"); log(" replaced by this option when used, and an empty string otherwise\n"); From ebe51e206ea036090d6068a6fa9e26d7b2c769b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 18:37:53 +0200 Subject: [PATCH 296/342] aiger2: Fix warnings --- backends/aiger2/aiger.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index a6a4b841a..0406ca0ac 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -222,8 +222,8 @@ struct Index { std::vector next; while (lits.size() > 1) { next.clear(); - for (int i = 0; i < lits.size(); i += 2) { - if (i + 1 >= lits.size()) { + for (int i = 0; i < (int) lits.size(); i += 2) { + if (i + 1 >= (int) lits.size()) { next.push_back(lits[i]); } else { Lit a = lits[i], b = lits[i + 1]; @@ -430,7 +430,7 @@ struct Index { for (int i = 0; i < sport.size(); i++) { Lit s = visit(cursor, sport[i]); next.clear(); - for (int j = 0; j < data.size(); j += 2) + for (int j = 0; j < (int) data.size(); j += 2) next.push_back(MUX(data[j], data[j + 1], s)); data.swap(next); } @@ -537,7 +537,7 @@ struct Index { } }; - bool visit_hook(int idx, HierCursor &cursor, SigBit bit) + bool visit_hook(int, HierCursor&, SigBit) { return false; } From 373e7a1485a1e8942429dd6df9fecc4fe687eb5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 19:23:11 +0200 Subject: [PATCH 297/342] aiger2: Fix print --- backends/aiger2/aiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 0406ca0ac..8de482bc0 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1154,7 +1154,7 @@ struct XAigerWriter : AigerWriter { write_be32(h_buffer, pis.size()); log_debug("ciNum = %zu\n", pis.size()); write_be32(h_buffer, pending_pos_num + pos.size()); - log_debug("coNum = %zu\n", boxes_co_num + pos.size()); + log_debug("coNum = %zu\n", pending_pos_num + pos.size()); write_be32(h_buffer, pis.size() - boxes_ci_num); log_debug("piNum = %zu\n", pis.size() - boxes_ci_num); write_be32(h_buffer, pending_pos_num + pos.size() - boxes_co_num); From 47fd2b9debadb877837c81f37bad1fd8da8c0476 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Sat, 5 Oct 2024 19:23:30 +0200 Subject: [PATCH 298/342] aiger2: Update help --- backends/aiger2/aiger.cc | 41 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 8de482bc0..29b8ee96b 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1311,8 +1311,15 @@ struct Aiger2Backend : Backend { log("\n"); log(" write_aiger2 [options] [filename]\n"); log("\n"); - log("Write the current design to an AIGER file.\n"); + log("Write the selected module to an AIGER file.\n"); log("\n"); + log(" -strash\n"); + log(" perform structural hashing while writing\n"); + log("\n"); + log(" -flatten\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); log("This command is able to ingest all combinational cells except for:\n"); log("\n"); pool supported = {KNOWN_OPS}; @@ -1384,11 +1391,41 @@ struct Aiger2Backend : Backend { } Aiger2Backend; struct XAiger2Backend : Backend { - XAiger2Backend() : Backend("xaiger2", "(experimental) write design to XAIGER file") + XAiger2Backend() : Backend("xaiger2", "(experimental) write module to XAIGER file") { experimental(); } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_xaiger2 [options] [filename]\n"); + log("\n"); + log("Write the selected module to a XAIGER file including the 'h' and 'a' extensions\n"); + log("with box information for ABC.\n"); + log("\n"); + log(" -strash\n"); + log(" perform structural hashing while writing\n"); + log("\n"); + log(" -flatten\n"); + log(" allow descending into submodules and write a flattened view of the design\n"); + log(" hierarchy starting at the selected top\n"); + log("\n"); + log(" -mapping_prep\n"); + log(" after the file is written, prepare the module for reintegration of\n"); + log(" a mapping in a subsequent command. all cells which are not blackboxed nor\n"); + log(" whiteboxed are removed from the design as well as all wires which only\n"); + log(" connect to removed cells\n"); + log(" (conflicts with -flatten)\n"); + log("\n"); + log(" -map2 \n"); + log(" write a map2 file which 'read_xaiger2 -sc_mapping' can read to\n"); + log(" reintegrate a mapping\n"); + log(" (conflicts with -flatten)\n"); + log("\n"); + } + void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override { log_header(design, "Executing XAIGER2 backend.\n"); From d0a11e26f391a670b73b822671e7b974e112e59a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 11:59:52 +0200 Subject: [PATCH 299/342] aiger2: Add test of writing a flattened view --- tests/various/aiger2.ys | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/tests/various/aiger2.ys b/tests/various/aiger2.ys index e008cdfaf..d2b024d2f 100644 --- a/tests/various/aiger2.ys +++ b/tests/various/aiger2.ys @@ -193,3 +193,32 @@ select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D equiv_make gold test equiv equiv_induct -undef equiv equiv_status -assert equiv + +design -reset +read_verilog -icells < Date: Mon, 7 Oct 2024 12:27:37 +0200 Subject: [PATCH 300/342] aiger2: Try to fix VS build --- backends/aiger2/aiger.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index 29b8ee96b..3fc6ccdba 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -47,11 +47,8 @@ PRIVATE_NAMESPACE_BEGIN #define KNOWN_OPS BITWISE_OPS, REDUCE_OPS, LOGIC_OPS, GATE_OPS, ID($pos), CMP_OPS, \ ID($pmux), ID($bmux) /*, ARITH_OPS*/ -template +template struct Index { - static constexpr Lit CFALSE = Writer::CONST_FALSE; - static constexpr Lit CTRUE = Writer::CONST_TRUE; - struct HierCursor; struct ModuleInfo { Module *module; @@ -664,7 +661,7 @@ struct Index { } }; -struct AigerWriter : Index { +struct AigerWriter : Index { typedef unsigned int Lit; const static Lit CONST_FALSE = 0; @@ -804,7 +801,7 @@ struct AigerWriter : Index { } }; -struct XAigerAnalysis : Index { +struct XAigerAnalysis : Index { const static int CONST_FALSE = 0; const static int CONST_TRUE = 0; const static constexpr int EMPTY_LIT = -1; From f44a418212c61ae032d1aecbdc3de588ba3a1f5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 12:27:54 +0200 Subject: [PATCH 301/342] read_xaiger2: Add casts to silence warnings --- frontends/aiger2/xaiger.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 4c7305876..18cfe94dd 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -88,7 +88,7 @@ struct Xaiger2Frontend : public Frontend { log_error("Inconsistent header\n"); std::vector outputs; - for (int i = 0; i < O; i++) { + for (int i = 0; i < (int) O; i++) { int po; *f >> po; log_assert(f->get() == '\n'); @@ -110,7 +110,7 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> pi_idx >> woffset >> name)) log_error("Bad map file (1)\n"); int lit = (2 * pi_idx) + 2; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (2)\n"); Wire *w = module->wire(name); if (!w || woffset < 0 || woffset >= w->width) @@ -140,7 +140,7 @@ struct Xaiger2Frontend : public Frontend { if (!def) log_error("Bad map file (22)\n"); - if (box_seq >= boxes.size()) { + if (box_seq >= (int) boxes.size()) { boxes.resize(box_seq + 1); retained_boxes.resize(box_seq + 1); } @@ -151,7 +151,7 @@ struct Xaiger2Frontend : public Frontend { } } - for (int i = 0; i < A; i++) { + for (int i = 0; i < (int) A; i++) { while (f->get() & 0x80 && !f->eof()); while (f->get() & 0x80 && !f->eof()); } @@ -185,7 +185,7 @@ struct Xaiger2Frontend : public Frontend { box_id = read_be32(*f); box_seq = read_be32(*f); - log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size()); log_assert(box_seq < boxes.size()); auto [cell, def] = boxes[box_seq]; @@ -213,7 +213,7 @@ struct Xaiger2Frontend : public Frontend { } } - log_assert(box_ci_idx == box_outputs); + log_assert(box_ci_idx == (int) box_outputs); ci_counter += box_ci_idx; } log_assert(pi_num + ci_counter == ci_num); @@ -324,7 +324,7 @@ struct Xaiger2Frontend : public Frontend { box_id = read_be32(*f); box_seq = read_be32(*f); - log("box_seq=%d boxes.size=%d\n", box_seq, boxes.size()); + log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size()); log_assert(box_seq < boxes.size()); auto [cell, def] = boxes[box_seq]; @@ -340,9 +340,9 @@ struct Xaiger2Frontend : public Frontend { SigSpec conn; for (int j = 0; j < port->width; j++) { - log_assert(co_counter + box_co_idx < outputs.size()); + log_assert(co_counter + box_co_idx < (int) outputs.size()); int lit = outputs[co_counter + box_co_idx++]; - log_assert(lit >= 0 && lit < bits.size()); + log_assert(lit >= 0 && lit < (int) bits.size()); SigBit bit = bits[lit]; if (bit == RTLIL::Sm) log_error("Malformed mapping (1)\n"); @@ -352,7 +352,7 @@ struct Xaiger2Frontend : public Frontend { } } - log_assert(box_co_idx == box_inputs); + log_assert(box_co_idx == (int) box_inputs); co_counter += box_co_idx; } log_assert(po_num + co_counter == co_num); @@ -389,10 +389,10 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> po_idx >> woffset >> name)) log_error("Bad map file (3)\n"); po_idx += co_counter; - if (po_idx < 0 || po_idx >= outputs.size()) + if (po_idx < 0 || po_idx >= (int) outputs.size()) log_error("Bad map file (4)\n"); int lit = outputs[po_idx]; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (5)\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (6)\n"); @@ -409,10 +409,10 @@ struct Xaiger2Frontend : public Frontend { if (!(map_file >> po_idx >> poffset >> box_name >> box_port)) log_error("Bad map file (7)\n"); po_idx += co_counter; - if (po_idx < 0 || po_idx >= outputs.size()) + if (po_idx < 0 || po_idx >= (int) outputs.size()) log_error("Bad map file (8)\n"); int lit = outputs[po_idx]; - if (lit < 0 || lit >= bits.size()) + if (lit < 0 || lit >= (int) bits.size()) log_error("Bad map file (9)\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file (10)\n"); From 7989d53c58d793109dee49404bf17b0871277cd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 14:19:49 +0200 Subject: [PATCH 302/342] read_xaiger2: Add help --- frontends/aiger2/xaiger.cc | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 18cfe94dd..04beee396 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -38,7 +38,26 @@ IdString read_idstring(std::istream &f) } struct Xaiger2Frontend : public Frontend { - Xaiger2Frontend() : Frontend("xaiger2", "read XAIGER file (new)") {} + Xaiger2Frontend() : Frontend("xaiger2", "(experimental) read XAIGER file") + { + experimental(); + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" read_xaiger2 -sc_mapping [options] \n"); + log("\n"); + log("Read a standard cell mapping from a XAIGER file into an existing module.\n"); + log("\n"); + log(" -module_name \n"); + log(" name of the target module\n"); + log("\n"); + log(" -map2 \n"); + log(" read file with symbol information\n"); + log("\n"); + } void read_sc_mapping(std::istream *&f, std::string filename, std::vector args, Design *design) { From b01b17689e919ed09ec80918b6aa23d093f355e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 14:49:17 +0200 Subject: [PATCH 303/342] Add test of error not getting silenced --- tests/various/logger_cmd_error.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100755 tests/various/logger_cmd_error.sh diff --git a/tests/various/logger_cmd_error.sh b/tests/various/logger_cmd_error.sh new file mode 100755 index 000000000..dd0585965 --- /dev/null +++ b/tests/various/logger_cmd_error.sh @@ -0,0 +1,9 @@ +#!/usr/bin/env bash + +trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR + +(../../yosys -v 3 -C <&1 | grep -F "ERROR: Module \`nonexistent' not found!" > /dev/null From ca5c2fdff1d2e1e5bc1fbfb1764e75e934f015a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 7 Oct 2024 15:26:48 +0200 Subject: [PATCH 304/342] quicklogic: Relax the LUT number test --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys index 5ca5b3051..dd5de9d3a 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/div.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -10,5 +10,5 @@ EOF equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 26 t:$lut +select -assert-max 100 t:$lut select -assert-none t:$lut %% t:* %D From 407343a7a12385bba40e406f68270b95afabb09b Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 12 Aug 2024 14:21:05 +0300 Subject: [PATCH 305/342] Pyosys Wheels * Created `setup.py`: Python package manifest to build `pyosys` wheels with a custom extension to build and include `libyosys.so` using Make * `.gitignore`: Added byproducts of the Python wheel build process * `Makefile`: Added `-undefined dynamic_lookup` to `libyosys.so` so missing symbols can be resolved by importing into a Python interpreter * `kernel/yosys.cc`: Gated `PyImport_AppendInittab` with `!Py_IsInitialized`; as of Python 3.12, the interpreter is already initialized and `PyImport_AppendInittab` would cause an exception to be raised * Created `wheels.yml`: CI workflow for building wheels for CPython on: * Linux (glibc, musl) and Darwin * x86-64 and arm64 --- .github/workflows/wheels.yml | 111 +++++++++++++++++++++++++++++++++++ .gitignore | 7 ++- Makefile | 2 +- kernel/yosys.cc | 13 ++-- setup.py | 97 ++++++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 6 deletions(-) create mode 100644 .github/workflows/wheels.yml create mode 100644 setup.py diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml new file mode 100644 index 000000000..9f3394d84 --- /dev/null +++ b/.github/workflows/wheels.yml @@ -0,0 +1,111 @@ +name: Build Wheels for PyPI +on: + workflow_dispatch: + push: + # tags: ["yosys-*"] +jobs: + build_wheels: + strategy: + matrix: + os: [ + # You can't cross-compile on Linux, so might as well do the emulated + # workload on its own + { + name: "Ubuntu 22.04", + family: "linux", + runner: "ubuntu-22.04", + archs: "x86_64", + }, + { + name: "Ubuntu 22.04", + family: "linux", + runner: "ubuntu-22.04", + archs: "aarch64", + }, + # While you can cross-compile on macOS, this is less of a headache + { + name: "macOS 13", + family: "macos", + runner: "macos-13", + archs: "x86_64", + }, + { + name: "macOS 14", + family: "macos", + runner: "macos-14", + archs: "arm64", + }, + # TODO: Make Windows Work + # { + # name: "Windows Server 2019", + # family: "windows", + # runner: "windows-2019", + # archs: "AMD64 ARM64", + # }, + ] + name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} + runs-on: ${{ matrix.os.runner }} + steps: + - uses: actions/checkout@v3 + with: + fetch-depth: 0 + submodules: true + - if: ${{ matrix.os.family == 'linux' }} + name: "[Linux] Set up QEMU" + uses: docker/setup-qemu-action@v2 + - uses: actions/setup-python@v3 + - name: Get Boost Source + run: | + mkdir -p boost + curl -L https://sourceforge.net/projects/boost/files/boost/1.83.0/boost_1_83_0.tar.bz2 | tar --strip-components=1 -xjC boost + - name: Seed Makefile.bak + # For every sed, a .bak is created so it can be copied over Makefile to + # rever the change for the next Python version to be built. + # + # This creates a .bak for the first Python version's cp to consume. + run: | + cp Makefile Makefile.bak + - if: ${{ matrix.os.family == 'macos' }} + name: "[macOS] Flex/Bison" + run: | + brew install flex bison + echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV + echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV + - if: ${{ matrix.os.family == 'macos' && matrix.os.archs == 'arm64' }} + name: "[macOS/arm64] Install Python 3.8 (see: https://cibuildwheel.pypa.io/en/stable/faq/#macos-building-cpython-38-wheels-on-arm64)" + uses: actions/setup-python@v5 + with: + python-version: 3.8 + - name: Build wheels + uses: pypa/cibuildwheel@v2.20.0 + env: + # Explaining the build steps: + # 1. Revert previous seds (if any) + # 2. Delete the libboost static archives from previous builds (if any) + # 3. Navigate to boost source extracted in previous GHA step + # 4-5. Build Boost against current version of Python, only for + # static linkage + # (Boost is statically linked because system boost packages + # wildly vary in versions, including the libboost_python3 + # version) + # 6-7. Return to package directory and sed the Makefile to point at + # the newly compiled libboost_python + CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy + CIBW_ARCHS: ${{ matrix.os.archs }} + CIBW_BUILD_VERBOSITY: "1" + CIBW_BEFORE_ALL_LINUX: yum install -y libffi-devel flex bison || apk add libffi-dev flex bison + CIBW_BEFORE_ALL_MAC: brew install libffi + CIBW_BEFORE_BUILD: | + cp Makefile.bak Makefile &&\ + cd ./boost &&\ + rm -rf ./pfx &&\ + ./bootstrap.sh --prefix=./pfx &&\ + ./b2 --prefix=./pfx --with-filesystem --with-system --with-python cxxflags="$(python3-config --includes) -std=c++17 -fPIC" cflags="$(python3-config --includes) -fPIC" link=static variant=release install &&\ + ls ./pfx/lib/libboost_python*.a &&\ + cd {package} &&\ + sed -i'.bak' -e "1i\\ + LINKFLAGS = -L./boost/pfx/lib" -e "1i\\ + CXXFLAGS = -I./boost/pfx/include" -e "s@BOOST_PYTHON_LIB ?=@BOOST_PYTHON_LIB = $(ls ./boost/pfx/lib/libboost_python*.a)\nTrash =@" Makefile + - uses: actions/upload-artifact@v3 + with: + path: ./dist/*.whl diff --git a/.gitignore b/.gitignore index e82343e89..5d6a466db 100644 --- a/.gitignore +++ b/.gitignore @@ -45,4 +45,9 @@ __pycache__ /tests/unit/bintest/ /tests/unit/objtest/ /tests/ystests -/result \ No newline at end of file +/result +/dist +/*.egg-info +/build +/venv +/boost diff --git a/Makefile b/Makefile index 5b6fc3ff2..ebea193cf 100644 --- a/Makefile +++ b/Makefile @@ -742,7 +742,7 @@ $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) ifeq ($(OS), Darwin) - $(P) $(CXX) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) + $(P) $(CXX) -o libyosys.so -shared -undefined dynamic_lookup -Wl,-install_name,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) else $(P) $(CXX) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LINKFLAGS) $^ $(LIBS) $(LIBS_VERIFIC) endif diff --git a/kernel/yosys.cc b/kernel/yosys.cc index efdc54b79..510151479 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -555,10 +555,15 @@ void yosys_setup() #undef X #ifdef WITH_PYTHON - PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); - Py_Initialize(); - PyRun_SimpleString("import sys"); - signal(SIGINT, SIG_DFL); + // With Python 3.12, calling PyImport_AppendInittab on an already + // initialized platform fails (such as when libyosys is imported + // from a Python interpreter) + if (!Py_IsInitialized()) { + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); + Py_Initialize(); + PyRun_SimpleString("import sys"); + signal(SIGINT, SIG_DFL); + } #endif Pass::init_register(); diff --git a/setup.py b/setup.py new file mode 100644 index 000000000..02e6e5843 --- /dev/null +++ b/setup.py @@ -0,0 +1,97 @@ +#!/usr/bin/env python3 +# Copyright (C) 2024 Efabless Corporation +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +import os +import re +import shlex +import shutil +from setuptools import setup, Extension +from setuptools.command.build_ext import build_ext + +__dir__ = os.path.dirname(os.path.abspath(__file__)) + +yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") + +version = yosys_version_rx.search( + open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() +)[1] + + +class libyosys_so_ext(Extension): + def __init__( + self, + ) -> None: + super().__init__( + "libyosys.so", + [], + ) + self.args = [ + "ENABLE_PYOSYS=1", + # Wheel meant to be imported from interpreter + "ENABLE_PYTHON_CONFIG_EMBED=0", + # Would need to be installed separately by the user + "ENABLE_TCL=0", + # Would need to be installed separately by the user + "ENABLE_READLINE=0", + # Show compile commands + "PRETTY=0", + ] + + def custom_build(self, bext: build_ext): + bext.spawn( + ["make", f"-j{os.cpu_count() or 1}", self.name] + + shlex.split(os.getenv("makeFlags", "")) + + self.args + ) + build_path = os.path.dirname(os.path.dirname(bext.get_ext_fullpath(self.name))) + pyosys_path = os.path.join(build_path, "pyosys") + target = os.path.join(pyosys_path, os.path.basename(self.name)) + os.makedirs(pyosys_path, exist_ok=True) + shutil.copyfile(self.name, target) + + # I don't know how debug info is getting here. + bext.spawn(["strip", "-S", target]) + + +class custom_build_ext(build_ext): + def build_extension(self, ext) -> None: + if not hasattr(ext, "custom_build"): + return super().build_extension(ext) + return ext.custom_build(self) + + +setup( + name="pyosys", + packages=["pyosys"], + version=version, + description="Python access to libyosys", + long_description=open(os.path.join(__dir__, "README.md")).read(), + long_description_content_type="text/markdown", + author="Claire Xenia Wolf", + author_email="claire@yosyshq.com", + install_requires=["wheel", "setuptools"], + classifiers=[ + "License :: OSI Approved :: MIT License", + "Programming Language :: Python :: 3", + "Intended Audience :: Developers", + "Operating System :: POSIX :: Linux", + "Operating System :: MacOS :: MacOS X", + ], + package_dir={"pyosys": "misc"}, + python_requires=">=3.8", + ext_modules=[libyosys_so_ext()], + cmdclass={ + "build_ext": custom_build_ext, + }, +) From ab4ea84679a9af5fa6172a4b4ce55c86d7a1ac5c Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 28 Sep 2024 21:03:43 +0300 Subject: [PATCH 306/342] wheels: more compatibility * Update manylinux images * FFI now built as a per-platform static library * Explicitly set minimum macOS deployment target, use clang on macOS * Try enabling Windows (as an experiment) * Disable aarch64-linux, aarch64-windows --- .github/workflows/_run_cibw_linux.py | 44 ++++++++++++ .github/workflows/cibw_before_all.sh | 21 ++++++ .github/workflows/cibw_before_build.sh | 23 +++++++ .github/workflows/wheels.yml | 92 +++++++++++++------------- .gitignore | 1 + 5 files changed, 134 insertions(+), 47 deletions(-) create mode 100644 .github/workflows/_run_cibw_linux.py create mode 100644 .github/workflows/cibw_before_all.sh create mode 100644 .github/workflows/cibw_before_build.sh diff --git a/.github/workflows/_run_cibw_linux.py b/.github/workflows/_run_cibw_linux.py new file mode 100644 index 000000000..675817ae0 --- /dev/null +++ b/.github/workflows/_run_cibw_linux.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# Copyright (C) 2024 Efabless Corporation +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +""" +This runs the cibuildwheel step from the wheels workflow locally. +""" + +import os +import yaml +import platform +import subprocess + +__dir__ = os.path.dirname(os.path.abspath(__file__)) + + +workflow = yaml.safe_load(open(os.path.join(__dir__, "wheels.yml"))) + +env = os.environ.copy() + +steps = workflow["jobs"]["build_wheels"]["steps"] +cibw_step = None +for step in steps: + if (step.get("uses") or "").startswith("pypa/cibuildwheel"): + cibw_step = step + break + +for key, value in cibw_step["env"].items(): + if key.endswith("WIN") or key.endswith("MAC"): + continue + env[key] = value + +env["CIBW_ARCHS"] = os.getenv("CIBW_ARCHS") or platform.machine() +subprocess.check_call(["cibuildwheel"], env=env) diff --git a/.github/workflows/cibw_before_all.sh b/.github/workflows/cibw_before_all.sh new file mode 100644 index 000000000..934902380 --- /dev/null +++ b/.github/workflows/cibw_before_all.sh @@ -0,0 +1,21 @@ +set -e +set -x + +# Build-time dependencies +## Linux Docker Images +if command -v yum &> /dev/null; then + yum install -y flex bison +fi + +if command -v apk &> /dev/null; then + apk add flex bison +fi + +## macOS/Windows -- install in GitHub Action itself, not container + +# Build Static FFI (platform-dependent but not Python version dependent) +cd ffi +SHELL=bash CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx + +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) +sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc diff --git a/.github/workflows/cibw_before_build.sh b/.github/workflows/cibw_before_build.sh new file mode 100644 index 000000000..03baf110b --- /dev/null +++ b/.github/workflows/cibw_before_build.sh @@ -0,0 +1,23 @@ +set -e +set -x + +# Build boost +cd ./boost +## Delete the artefacts from previous builds (if any) +rm -rf ./pfx +## Bootstrap bjam +./bootstrap.sh --prefix=./pfx +## Build Boost against current version of Python, only for +## static linkage (Boost is statically linked because system boost packages +## wildly vary in versions, including the libboost_python3 version) +./b2\ + -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu)\ + --prefix=./pfx\ + --with-filesystem\ + --with-system\ + --with-python\ + cxxflags="$(python3-config --includes) -std=c++17 -fPIC"\ + cflags="$(python3-config --includes) -fPIC"\ + link=static\ + variant=release\ + install diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 9f3394d84..5961f364a 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -6,23 +6,25 @@ on: jobs: build_wheels: strategy: + fail-fast: false matrix: os: [ - # You can't cross-compile on Linux, so might as well do the emulated - # workload on its own { name: "Ubuntu 22.04", family: "linux", runner: "ubuntu-22.04", archs: "x86_64", }, - { - name: "Ubuntu 22.04", - family: "linux", - runner: "ubuntu-22.04", - archs: "aarch64", - }, - # While you can cross-compile on macOS, this is less of a headache + ## Aarch64 is disabled for now: GitHub is committing to EOY + ## for free aarch64 runners for open-source projects and + ## emulation times out: + ## https://github.com/orgs/community/discussions/19197#discussioncomment-10550689 + # { + # name: "Ubuntu 22.04", + # family: "linux", + # runner: "ubuntu-22.04", + # archs: "aarch64", + # }, { name: "macOS 13", family: "macos", @@ -35,13 +37,12 @@ jobs: runner: "macos-14", archs: "arm64", }, - # TODO: Make Windows Work - # { - # name: "Windows Server 2019", - # family: "windows", - # runner: "windows-2019", - # archs: "AMD64 ARM64", - # }, + { + name: "Windows Server 2019", + family: "windows", + runner: "windows-2019", + archs: "AMD64", + }, ] name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} runs-on: ${{ matrix.os.runner }} @@ -55,22 +56,27 @@ jobs: uses: docker/setup-qemu-action@v2 - uses: actions/setup-python@v3 - name: Get Boost Source + shell: bash run: | mkdir -p boost - curl -L https://sourceforge.net/projects/boost/files/boost/1.83.0/boost_1_83_0.tar.bz2 | tar --strip-components=1 -xjC boost - - name: Seed Makefile.bak - # For every sed, a .bak is created so it can be copied over Makefile to - # rever the change for the next Python version to be built. - # - # This creates a .bak for the first Python version's cp to consume. + curl -L https://github.com/boostorg/boost/releases/download/boost-1.86.0/boost-1.86.0-b2-nodocs.tar.gz | tar --strip-components=1 -xzC boost + - name: Get FFI + shell: bash run: | - cp Makefile Makefile.bak + mkdir -p ffi + curl -L https://github.com/libffi/libffi/releases/download/v3.4.6/libffi-3.4.6.tar.gz | tar --strip-components=1 -xzC ffi + ## Software installed by default in GitHub Action Runner VMs: + ## https://github.com/actions/runner-images - if: ${{ matrix.os.family == 'macos' }} name: "[macOS] Flex/Bison" run: | brew install flex bison echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV + - if : ${{ matrix.os.family == 'windows' }} + name: "[Windows] Flex/Bison" + run: | + choco install winflexbison3 - if: ${{ matrix.os.family == 'macos' && matrix.os.archs == 'arm64' }} name: "[macOS/arm64] Install Python 3.8 (see: https://cibuildwheel.pypa.io/en/stable/faq/#macos-building-cpython-38-wheels-on-arm64)" uses: actions/setup-python@v5 @@ -79,33 +85,25 @@ jobs: - name: Build wheels uses: pypa/cibuildwheel@v2.20.0 env: - # Explaining the build steps: - # 1. Revert previous seds (if any) - # 2. Delete the libboost static archives from previous builds (if any) - # 3. Navigate to boost source extracted in previous GHA step - # 4-5. Build Boost against current version of Python, only for - # static linkage - # (Boost is statically linked because system boost packages - # wildly vary in versions, including the libboost_python3 - # version) - # 6-7. Return to package directory and sed the Makefile to point at - # the newly compiled libboost_python CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy CIBW_ARCHS: ${{ matrix.os.archs }} CIBW_BUILD_VERBOSITY: "1" - CIBW_BEFORE_ALL_LINUX: yum install -y libffi-devel flex bison || apk add libffi-dev flex bison - CIBW_BEFORE_ALL_MAC: brew install libffi - CIBW_BEFORE_BUILD: | - cp Makefile.bak Makefile &&\ - cd ./boost &&\ - rm -rf ./pfx &&\ - ./bootstrap.sh --prefix=./pfx &&\ - ./b2 --prefix=./pfx --with-filesystem --with-system --with-python cxxflags="$(python3-config --includes) -std=c++17 -fPIC" cflags="$(python3-config --includes) -fPIC" link=static variant=release install &&\ - ls ./pfx/lib/libboost_python*.a &&\ - cd {package} &&\ - sed -i'.bak' -e "1i\\ - LINKFLAGS = -L./boost/pfx/lib" -e "1i\\ - CXXFLAGS = -I./boost/pfx/include" -e "s@BOOST_PYTHON_LIB ?=@BOOST_PYTHON_LIB = $(ls ./boost/pfx/lib/libboost_python*.a)\nTrash =@" Makefile + # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys + CIBW_MANYLINUX_X86_64_IMAGE: manylinux_2_28 + CIBW_MANYLINUX_AARCH64_IMAGE: manylinux_2_28 + CIBW_BEFORE_ALL: bash ./.github/workflows/cibw_before_all.sh + CIBW_ENVIRONMENT: > + CXXFLAGS=-I./boost/pfx/include + LINKFLAGS=-L./boost/pfx/lib + PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig + makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a' + CIBW_ENVIRONMENT_MACOS: > + CXXFLAGS=-I./boost/pfx/include + LINKFLAGS=-L./boost/pfx/lib + PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig + MACOSX_DEPLOYMENT_TARGET=11 + makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' + CIBW_BEFORE_BUILD: bash ./.github/workflows/cibw_before_build.sh - uses: actions/upload-artifact@v3 with: path: ./dist/*.whl diff --git a/.gitignore b/.gitignore index 5d6a466db..5c3d8f4e9 100644 --- a/.gitignore +++ b/.gitignore @@ -51,3 +51,4 @@ __pycache__ /build /venv /boost +/ffi From ab84c105c14bfca00a6b87828cb665b40740b35b Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sat, 28 Sep 2024 23:11:45 +0300 Subject: [PATCH 307/342] Add test, shell for windows --- .github/workflows/wheels.yml | 5 +++-- .github/workflows/{ => wheels}/_run_cibw_linux.py | 2 +- .github/workflows/{ => wheels}/cibw_before_all.sh | 10 ++++++---- .github/workflows/{ => wheels}/cibw_before_build.sh | 7 +++++++ 4 files changed, 17 insertions(+), 7 deletions(-) rename .github/workflows/{ => wheels}/_run_cibw_linux.py (94%) rename .github/workflows/{ => wheels}/cibw_before_all.sh (55%) rename .github/workflows/{ => wheels}/cibw_before_build.sh (80%) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index 5961f364a..c6af2c8b2 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -91,7 +91,7 @@ jobs: # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys CIBW_MANYLINUX_X86_64_IMAGE: manylinux_2_28 CIBW_MANYLINUX_AARCH64_IMAGE: manylinux_2_28 - CIBW_BEFORE_ALL: bash ./.github/workflows/cibw_before_all.sh + CIBW_BEFORE_ALL: bash ./.github/workflows/wheels/cibw_before_all.sh CIBW_ENVIRONMENT: > CXXFLAGS=-I./boost/pfx/include LINKFLAGS=-L./boost/pfx/lib @@ -103,7 +103,8 @@ jobs: PKG_CONFIG_PATH=./ffi/pfx/lib/pkgconfig MACOSX_DEPLOYMENT_TARGET=11 makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' - CIBW_BEFORE_BUILD: bash ./.github/workflows/cibw_before_build.sh + CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh + CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v3 with: path: ./dist/*.whl diff --git a/.github/workflows/_run_cibw_linux.py b/.github/workflows/wheels/_run_cibw_linux.py similarity index 94% rename from .github/workflows/_run_cibw_linux.py rename to .github/workflows/wheels/_run_cibw_linux.py index 675817ae0..894470a5a 100644 --- a/.github/workflows/_run_cibw_linux.py +++ b/.github/workflows/wheels/_run_cibw_linux.py @@ -24,7 +24,7 @@ import subprocess __dir__ = os.path.dirname(os.path.abspath(__file__)) -workflow = yaml.safe_load(open(os.path.join(__dir__, "wheels.yml"))) +workflow = yaml.safe_load(open(os.path.join(os.path.dirname(__dir__), "wheels.yml"))) env = os.environ.copy() diff --git a/.github/workflows/cibw_before_all.sh b/.github/workflows/wheels/cibw_before_all.sh similarity index 55% rename from .github/workflows/cibw_before_all.sh rename to .github/workflows/wheels/cibw_before_all.sh index 934902380..28aae85ac 100644 --- a/.github/workflows/cibw_before_all.sh +++ b/.github/workflows/wheels/cibw_before_all.sh @@ -11,11 +11,13 @@ if command -v apk &> /dev/null; then apk add flex bison fi -## macOS/Windows -- install in GitHub Action itself, not container +## macOS/Windows -- installed in GitHub Action itself, not container # Build Static FFI (platform-dependent but not Python version dependent) cd ffi -SHELL=bash CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx - -make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) +## Ultimate libyosys.so will be shared, so we need fPIC for the static libraries +CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx +## Without this, SHELL has a space in its path which breaks the makefile +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) SHELL=bash +## Forces static library to be used in all situations sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc diff --git a/.github/workflows/cibw_before_build.sh b/.github/workflows/wheels/cibw_before_build.sh similarity index 80% rename from .github/workflows/cibw_before_build.sh rename to .github/workflows/wheels/cibw_before_build.sh index 03baf110b..29fffe090 100644 --- a/.github/workflows/cibw_before_build.sh +++ b/.github/workflows/wheels/cibw_before_build.sh @@ -1,6 +1,13 @@ set -e set -x +# Don't use objects from previous compiles on Windows/macOS +make clean + +# DEBUG: show python3 and python3-config outputs +python3 --version +python3-config --includes + # Build boost cd ./boost ## Delete the artefacts from previous builds (if any) From 67f17a1c97a097eb59d8a7d1b81fc5aff66f0da8 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sun, 29 Sep 2024 12:28:18 +0300 Subject: [PATCH 308/342] wheels: symlink python3-config --- .github/workflows/wheels.yml | 2 +- .github/workflows/wheels/cibw_before_build.sh | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index c6af2c8b2..eafaa957f 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -83,7 +83,7 @@ jobs: with: python-version: 3.8 - name: Build wheels - uses: pypa/cibuildwheel@v2.20.0 + uses: pypa/cibuildwheel@v2.21.1 env: CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy CIBW_ARCHS: ${{ matrix.os.archs }} diff --git a/.github/workflows/wheels/cibw_before_build.sh b/.github/workflows/wheels/cibw_before_build.sh index 29fffe090..018b0e0df 100644 --- a/.github/workflows/wheels/cibw_before_build.sh +++ b/.github/workflows/wheels/cibw_before_build.sh @@ -5,6 +5,10 @@ set -x make clean # DEBUG: show python3 and python3-config outputs +if [ "$(uname)" != "Linux" ]; then + # https://github.com/pypa/cibuildwheel/issues/2021 + ln -s $(dirname $(readlink -f $(which python3)))/python3-config $(dirname $(which python3))/python3-config +fi python3 --version python3-config --includes From 08c23b7632a744c1bf3a42f035611757cb64a1ea Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Sun, 29 Sep 2024 16:02:37 +0300 Subject: [PATCH 309/342] wheels: skip musllinux for now --- .github/workflows/wheels.yml | 8 ++++++-- .github/workflows/wheels/cibw_before_all.sh | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index eafaa957f..a91c873fb 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -85,7 +85,11 @@ jobs: - name: Build wheels uses: pypa/cibuildwheel@v2.21.1 env: - CIBW_SKIP: pp* # The Makefile requires python3-config which is not in pypy + # * APIs not supported by PyPy + # * Musllinux temporarily disabled because it takes too much time + CIBW_SKIP: > + pp* + *musllinux* CIBW_ARCHS: ${{ matrix.os.archs }} CIBW_BUILD_VERBOSITY: "1" # manylinux2014 (default) does not have a modern enough C++ compiler for Yosys @@ -107,4 +111,4 @@ jobs: CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v3 with: - path: ./dist/*.whl + path: ./wheelhouse/*.whl diff --git a/.github/workflows/wheels/cibw_before_all.sh b/.github/workflows/wheels/cibw_before_all.sh index 28aae85ac..fbb8dcad8 100644 --- a/.github/workflows/wheels/cibw_before_all.sh +++ b/.github/workflows/wheels/cibw_before_all.sh @@ -18,6 +18,6 @@ cd ffi ## Ultimate libyosys.so will be shared, so we need fPIC for the static libraries CFLAGS=-fPIC CXXFLAGS=-fPIC ./configure --prefix=$PWD/pfx ## Without this, SHELL has a space in its path which breaks the makefile -make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) SHELL=bash +make install -j$(getconf _NPROCESSORS_ONLN 2>/dev/null || sysctl -n hw.ncpu) ## Forces static library to be used in all situations sed -i.bak 's@-L${toolexeclibdir} -lffi@${toolexeclibdir}/libffi.a@' ./pfx/lib/pkgconfig/libffi.pc From 0bb1f899e84f97b53a765581a5e91450a8074215 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Fri, 4 Oct 2024 16:14:26 +0300 Subject: [PATCH 310/342] wheels: convert versions to match pypa spec, add uploading * wheel versions now replace `+` with `.post` to match spec at https://packaging.python.org/en/latest/specifications/version-specifiers/ * CI updates: * Bump action versions * Disabled Windows for now and documented why * Added a new job to upload all wheels * Added new variable, `PYPI_INDEX`: fallback 'https://pypi.org/' if unset * Added new secret, `PYPI_TOKEN` * .editorconfig now uses 2 spaces for YML (it kept setting mine to tabs and GitHub Actions doesn't like that) --- .editorconfig | 4 +++ .github/workflows/wheels.yml | 49 +++++++++++++++++++++++++----------- setup.py | 2 +- 3 files changed, 40 insertions(+), 15 deletions(-) diff --git a/.editorconfig b/.editorconfig index f5444d81a..572b73bd2 100644 --- a/.editorconfig +++ b/.editorconfig @@ -10,3 +10,7 @@ insert_final_newline = true indent_style = space indent_size = 2 trim_trailing_whitespace = false + +[*.yml] +indent_style = space +indent_size = 2 diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index a91c873fb..c6132685b 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -1,8 +1,7 @@ name: Build Wheels for PyPI on: workflow_dispatch: - push: - # tags: ["yosys-*"] + jobs: build_wheels: strategy: @@ -37,24 +36,27 @@ jobs: runner: "macos-14", archs: "arm64", }, - { - name: "Windows Server 2019", - family: "windows", - runner: "windows-2019", - archs: "AMD64", - }, + ## Windows is disabled because of an issue with compiling FFI as + ## under MinGW in the GitHub Actions environment (SHELL variable has + ## whitespace.) + # { + # name: "Windows Server 2019", + # family: "windows", + # runner: "windows-2019", + # archs: "AMD64", + # }, ] name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} runs-on: ${{ matrix.os.runner }} steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 with: fetch-depth: 0 submodules: true - if: ${{ matrix.os.family == 'linux' }} name: "[Linux] Set up QEMU" - uses: docker/setup-qemu-action@v2 - - uses: actions/setup-python@v3 + uses: docker/setup-qemu-action@v3 + - uses: actions/setup-python@v5 - name: Get Boost Source shell: bash run: | @@ -73,7 +75,7 @@ jobs: brew install flex bison echo "PATH=$(brew --prefix flex)/bin:$PATH" >> $GITHUB_ENV echo "PATH=$(brew --prefix bison)/bin:$PATH" >> $GITHUB_ENV - - if : ${{ matrix.os.family == 'windows' }} + - if: ${{ matrix.os.family == 'windows' }} name: "[Windows] Flex/Bison" run: | choco install winflexbison3 @@ -86,7 +88,7 @@ jobs: uses: pypa/cibuildwheel@v2.21.1 env: # * APIs not supported by PyPy - # * Musllinux temporarily disabled because it takes too much time + # * Musllinux disabled because it increases build time from 48m to ~3h CIBW_SKIP: > pp* *musllinux* @@ -109,6 +111,25 @@ jobs: makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@v4 with: + name: python-wheels path: ./wheelhouse/*.whl + upload_wheels: + name: Upload Wheels + runs-on: ubuntu-latest + needs: build_wheels + steps: + - uses: actions/download-artifact@v4 + with: + name: python-wheels + path: "." + - run: | + ls + mkdir -p ./dist + mv *.whl ./dist + - name: Publish + uses: pypa/gh-action-pypi-publish@release/v1 + with: + password: ${{ secrets.PYPI_TOKEN }} + repository-url: ${{ vars.PYPI_INDEX || 'https://upload.pypi.org/legacy/' }} diff --git a/setup.py b/setup.py index 02e6e5843..f9d455f0b 100644 --- a/setup.py +++ b/setup.py @@ -25,7 +25,7 @@ yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") version = yosys_version_rx.search( open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() -)[1] +)[1].replace("+", ".post") class libyosys_so_ext(Extension): From 43128f628311e7dd69fc5aab802b9a0242efef87 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 7 Oct 2024 16:51:17 +0300 Subject: [PATCH 311/342] wheels: move from postreleases to minor versions, remove authors --- setup.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/setup.py b/setup.py index f9d455f0b..221965971 100644 --- a/setup.py +++ b/setup.py @@ -25,7 +25,9 @@ yosys_version_rx = re.compile(r"YOSYS_VER\s*:=\s*([\w\-\+\.]+)") version = yosys_version_rx.search( open(os.path.join(__dir__, "Makefile"), encoding="utf8").read() -)[1].replace("+", ".post") +)[1].replace( + "+", "." +) # Convert to patch version class libyosys_so_ext(Extension): @@ -78,8 +80,6 @@ setup( description="Python access to libyosys", long_description=open(os.path.join(__dir__, "README.md")).read(), long_description_content_type="text/markdown", - author="Claire Xenia Wolf", - author_email="claire@yosyshq.com", install_requires=["wheel", "setuptools"], classifiers=[ "License :: OSI Approved :: MIT License", From a76bcdc58fd22ba9441cdcc2b80c565966034c6e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 7 Oct 2024 17:58:48 +0200 Subject: [PATCH 312/342] bufnorm: avoid remove warning. NFC --- passes/techmap/bufnorm.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 75060673e..3c2cd9230 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -70,9 +70,9 @@ struct BufnormPass : public Pass { log(" to chain 'keep' wires first, then ports in declaration order,\n"); log(" and then the other wires in alphanumeric sort order.)\n"); log("\n"); - log(" -noinit\n"); - log(" Do not move 'init' attributes to the wires on FF output ports.\n"); - log("\n"); + // log(" -noinit\n"); + // log(" Do not move 'init' attributes to the wires on FF output ports.\n"); + // log("\n"); log("Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all\n"); log("$buf buffer cells and exit 'buffered-normalized mode' again.\n"); log("\n"); @@ -108,7 +108,7 @@ struct BufnormPass : public Pass { bool nokeep_mode = false; bool nosticky_mode = false; bool alphasort_mode = false; - bool noinit_mode = false; // FIXME: Actually move init attributes + // bool noinit_mode = false; // FIXME: Actually move init attributes bool nomode_mode = false; bool pos_mode = false; @@ -169,11 +169,11 @@ struct BufnormPass : public Pass { got_non_update_reset_opt = true; continue; } - if (arg == "-noinit") { - noinit_mode = true; - got_non_update_reset_opt = true; - continue; - } + // if (arg == "-noinit") { + // noinit_mode = true; + // got_non_update_reset_opt = true; + // continue; + // } if (arg == "-pos") { pos_mode = true; got_non_update_reset_opt = true; From d7cf0238fda76e6a7f565dc4b521828e164c00f6 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Mon, 7 Oct 2024 20:17:05 +0300 Subject: [PATCH 313/342] wheels: properly migrate to artifact@v4 --- .github/workflows/wheels.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index c6132685b..d59f8e1ec 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -113,7 +113,7 @@ jobs: CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" - uses: actions/upload-artifact@v4 with: - name: python-wheels + name: python-wheels-${{ matrix.os.runner }} path: ./wheelhouse/*.whl upload_wheels: name: Upload Wheels @@ -122,8 +122,9 @@ jobs: steps: - uses: actions/download-artifact@v4 with: - name: python-wheels path: "." + pattern: python-wheels-* + merge-multiple: true - run: | ls mkdir -p ./dist From b15103625b4161f41c9c468c1e71c58df24f4884 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 8 Oct 2024 07:49:14 +1300 Subject: [PATCH 314/342] ci: Switch test build docs to our runner --- .github/workflows/prepare-docs.yml | 5 +++++ .github/workflows/test-build.yml | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index e2689d4df..6d3f4ecea 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -64,6 +64,11 @@ jobs: docs/source/_images docs/source/code_examples + - name: Test build docs + shell: bash + run: | + make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + - name: Trigger RTDs build if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} uses: dfm/rtds-action@v1.1.0 diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 1502d8aa0..e5aed6af3 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -189,8 +189,3 @@ jobs: shell: bash run: | make -C docs test -j${{ env.procs }} - - - name: Test build docs - shell: bash - run: | - make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= From c1604424aad3116c435bfb08c12f92447e140f6b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 8 Oct 2024 08:11:35 +1300 Subject: [PATCH 315/342] ci: Call make html directly Since `docs/prep` is a prerequisite of `docs`, and should be the *only* prerequisite, calling `make docs` could end up hiding a problem with files missing from the uploaded artifact. Instead, call `make` from the docs directory which should be closer to what will run on RTDs. --- .github/workflows/prepare-docs.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 6d3f4ecea..e0388c7a3 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -67,7 +67,7 @@ jobs: - name: Test build docs shell: bash run: | - make docs -j${{ env.procs }} TARGETS= EXTRA_TARGETS= + make -C docs html -j${{ env.procs }} TARGETS= EXTRA_TARGETS= - name: Trigger RTDs build if: ${{ needs.check_docs_rebuild.outputs.docs_export == 'true' }} From 1e3973c5cb009944ed65eb6117d548fc17c78639 Mon Sep 17 00:00:00 2001 From: Mike Inouye Date: Mon, 7 Oct 2024 21:57:30 +0000 Subject: [PATCH 316/342] Explictly #include for std::variant usage. Signed-off-by: Mike Inouye --- kernel/hashlib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/hashlib.h b/kernel/hashlib.h index 157ccf4ce..859115829 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include From 408597b478f884681254f07a25c14f9485a7b5e6 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 8 Oct 2024 00:20:07 +0000 Subject: [PATCH 317/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5b6fc3ff2..92274a56d 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+153 +YOSYS_VER := 0.45+217 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From f079772ade52cedb30f056fa5819cd9df92d8356 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 8 Oct 2024 08:47:51 +0200 Subject: [PATCH 318/342] Add TODO for missing help messages --- backends/functional/cxx.cc | 2 ++ backends/functional/test_generic.cc | 2 ++ passes/cmds/example_dt.cc | 2 ++ 3 files changed, 6 insertions(+) diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index b8b25df8b..1f677120a 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -246,6 +246,8 @@ struct FunctionalCxxBackend : public Backend { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } void printCxx(std::ostream &stream, std::string, Module *module) diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 10a7a50f0..dc235d79a 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -122,6 +122,8 @@ struct FunctionalTestGeneric : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index aaf07dadd..1912d7da1 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -27,6 +27,8 @@ struct ExampleDtPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); + log("TODO: add help message\n"); + log("\n"); } From b4fd8e7ed837a86ee205cdf8766387239880743a Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 9 Oct 2024 00:20:28 +0000 Subject: [PATCH 319/342] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f4276b94d..4985bbade 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+217 +YOSYS_VER := 0.45+240 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From e97731b9dda91fa5fa53ed87df7c34163ba59a41 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 08:08:00 +0200 Subject: [PATCH 320/342] Release version 0.46 --- CHANGELOG | 22 +++++++++++++++++++++- Makefile | 4 ++-- docs/source/conf.py | 2 +- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 03bf5ac57..ab7690b4b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,28 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.45 .. Yosys 0.46-dev +Yosys 0.45 .. Yosys 0.46 -------------------------- + * Various + - Added new "functional backend" infrastructure with three example + backends (C++, SMTLIB and Rosette). + - Added new coarse-grain buffer cell type "$buf" to RTLIL. + - Added "-y" command line option to execute a Python script with + libyosys available as a built-in module. + - Added support for casting to type in Verilog frontend. + + * New commands and options + - Added "clockgate" pass for automatic clock gating cell insertion. + - Added "bufnorm" experimental pass to convert design into + buffered-normalized form. + - Added experimental "aiger2" and "xaiger2" backends, and an + experimental "abc_new" command + - Added "-force-detailed-loop-check" option to "check" pass. + - Added "-unit_delay" option to "read_liberty" pass. + + * Verific support + - Added left and right bound properties to wires when using + specific VHDL types. Yosys 0.44 .. Yosys 0.45 -------------------------- diff --git a/Makefile b/Makefile index 4985bbade..fe07074eb 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.45+240 +YOSYS_VER := 0.46 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -170,7 +170,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4371b79f1..8e30fcc7c 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,7 +5,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2024 YosysHQ GmbH' -yosys_ver = "0.45" +yosys_ver = "0.46" # select HTML theme html_theme = 'furo' From 8893dadc4b6be686f84870292f3182290325f7ad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 08:12:44 +0200 Subject: [PATCH 321/342] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index ab7690b4b..4106885fa 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.46 .. Yosys 0.47-dev +-------------------------- + Yosys 0.45 .. Yosys 0.46 -------------------------- * Various diff --git a/Makefile b/Makefile index fe07074eb..f81e1fea2 100644 --- a/Makefile +++ b/Makefile @@ -154,7 +154,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.46 +YOSYS_VER := 0.46+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -170,7 +170,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline e97731b.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From c93c7f8307f1d8ec81b71aabe9c761280752338d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 09:50:36 +0200 Subject: [PATCH 322/342] CI: lld is now separate brew package --- .github/actions/setup-build-env/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index c5a0d14ab..12ae883bd 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -14,7 +14,7 @@ runs: if: runner.os == 'macOS' shell: bash run: | - HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm + HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld - name: Linux runtime environment if: runner.os == 'Linux' From 3d6b8b8e1a350ae1ec688d41b8d8eae0109e5119 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Wed, 9 Oct 2024 12:44:52 +0300 Subject: [PATCH 323/342] wheels: fix missing yosys-abc/share directory * `misc/__init__.py`: * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc` * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname` * `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled * `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled * `Makefile`: add new target, `share`, to only create the extra targets * `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build * `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI --- .github/workflows/wheels.yml | 2 +- Makefile | 6 +++++ kernel/yosys.cc | 52 ++++++++++++++++++++++++------------ misc/__init__.py | 14 ++++++++++ setup.py | 34 +++++++++++++++++++---- tests/arch/ecp5/add_sub.py | 20 ++++++++++++++ 6 files changed, 105 insertions(+), 23 deletions(-) create mode 100644 tests/arch/ecp5/add_sub.py diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index d59f8e1ec..d66239a16 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -110,7 +110,7 @@ jobs: MACOSX_DEPLOYMENT_TARGET=11 makeFlags='BOOST_PYTHON_LIB=./boost/pfx/lib/libboost_python*.a CONFIG=clang' CIBW_BEFORE_BUILD: bash ./.github/workflows/wheels/cibw_before_build.sh - CIBW_TEST_COMMAND: python3 -c "from pyosys import libyosys as ys;d=ys.Design();ys.run_pass('help', d)" + CIBW_TEST_COMMAND: python3 {project}/tests/arch/ecp5/add_sub.py - uses: actions/upload-artifact@v4 with: name: python-wheels-${{ matrix.os.runner }} diff --git a/Makefile b/Makefile index f81e1fea2..0be664b9a 100644 --- a/Makefile +++ b/Makefile @@ -737,6 +737,12 @@ compile-only: $(OBJS) $(GENFILES) $(EXTRA_TARGETS) @echo " Compile successful." @echo "" +.PHONY: share +share: $(EXTRA_TARGETS) + @echo "" + @echo " Share directory created." + @echo "" + $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) $(P) $(CXX) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LINKFLAGS) $(LINKFLAGS) $(OBJS) $(LIBS) $(LIBS_VERIFIC) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 510151479..374b07d06 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -554,17 +554,17 @@ void yosys_setup() #include "kernel/constids.inc" #undef X - #ifdef WITH_PYTHON - // With Python 3.12, calling PyImport_AppendInittab on an already - // initialized platform fails (such as when libyosys is imported - // from a Python interpreter) - if (!Py_IsInitialized()) { - PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); - Py_Initialize(); - PyRun_SimpleString("import sys"); - signal(SIGINT, SIG_DFL); - } - #endif +#ifdef WITH_PYTHON + // With Python 3.12, calling PyImport_AppendInittab on an already + // initialized platform fails (such as when libyosys is imported + // from a Python interpreter) + if (!Py_IsInitialized()) { + PyImport_AppendInittab((char*)"libyosys", INIT_MODULE); + Py_Initialize(); + PyRun_SimpleString("import sys"); + signal(SIGINT, SIG_DFL); + } +#endif Pass::init_register(); yosys_design = new RTLIL::Design; @@ -1013,6 +1013,16 @@ void init_share_dirname() #else void init_share_dirname() { +# ifdef WITH_PYTHON + PyObject *sys_obj = PyImport_ImportModule("sys"); + + if (PyObject_HasAttrString(sys_obj, "_pyosys_share_dirname")) { + PyObject *share_path_obj = PyObject_GetAttrString(sys_obj, "_pyosys_share_dirname"); + const char *share_path = PyUnicode_AsUTF8(share_path_obj); + yosys_share_dirname = std::string(share_path); + return; + } +# endif std::string proc_self_path = proc_self_dirname(); # if defined(_WIN32) && !defined(YOSYS_WIN32_UNIX_DIR) std::string proc_share_path = proc_self_path + "share\\"; @@ -1058,12 +1068,20 @@ void init_abc_executable_name() } #else yosys_abc_executable = proc_self_dirname() + proc_program_prefix()+ "yosys-abc"; -#endif -#ifdef _WIN32 -#ifndef ABCEXTERNAL +# ifdef _WIN32 if (!check_file_exists(yosys_abc_executable + ".exe") && check_file_exists(proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc.exe")) yosys_abc_executable = proc_self_dirname() + "..\\" + proc_program_prefix() + "yosys-abc"; -#endif +# endif + +# ifdef WITH_PYTHON + PyObject *sys_obj = PyImport_ImportModule("sys"); + + if (PyObject_HasAttrString(sys_obj, "_pyosys_abc")) { + PyObject *abc_path_obj = PyObject_GetAttrString(sys_obj, "_pyosys_abc"); + const char *abc_path = PyUnicode_AsUTF8(abc_path_obj); + yosys_abc_executable = std::string(abc_path); + } +# endif #endif } @@ -1132,7 +1150,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi if (command == "auto") { std::string filename_trim = filename; - + auto has_extension = [](const std::string& filename, const std::string& extension) { if (filename.size() >= extension.size()) { return filename.compare(filename.size() - extension.size(), extension.size(), extension) == 0; @@ -1143,7 +1161,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi if (has_extension(filename_trim, ".gz")) { filename_trim.erase(filename_trim.size() - 3); } - + if (has_extension(filename_trim, ".v")) { command = " -vlog2k"; } else if (has_extension(filename_trim, ".sv")) { diff --git a/misc/__init__.py b/misc/__init__.py index 330fd6d86..d74e3f5bd 100644 --- a/misc/__init__.py +++ b/misc/__init__.py @@ -1,5 +1,19 @@ import os import sys + sys.setdlopenflags(os.RTLD_NOW | os.RTLD_GLOBAL) +__dir__ = os.path.abspath(os.path.dirname(__file__)) +sys._pyosys_dir = os.path.abspath(__dir__) + +bin_ext = ".exe" if os.name == "nt" else "" + +_share_candidate = os.path.join(__dir__, "share") +if os.path.isdir(_share_candidate): + sys._pyosys_share_dirname = _share_candidate + os.path.sep + +_abc_candidate = os.path.join(__dir__, f"yosys-abc{bin_ext}") +if os.path.isfile(_abc_candidate): + sys._pyosys_abc = _abc_candidate + __all__ = ["libyosys"] diff --git a/setup.py b/setup.py index 221965971..b3a6a9280 100644 --- a/setup.py +++ b/setup.py @@ -44,26 +44,50 @@ class libyosys_so_ext(Extension): "ENABLE_PYTHON_CONFIG_EMBED=0", # Would need to be installed separately by the user "ENABLE_TCL=0", - # Would need to be installed separately by the user "ENABLE_READLINE=0", + "ENABLE_EDITLINE=0", + # Always compile and include ABC in wheel + "ABCEXTERNAL=", # Show compile commands "PRETTY=0", ] def custom_build(self, bext: build_ext): bext.spawn( - ["make", f"-j{os.cpu_count() or 1}", self.name] + [ + "make", + f"-j{os.cpu_count() or 1}", + self.name, + "yosys-abc", + "share", + ] + shlex.split(os.getenv("makeFlags", "")) + self.args ) build_path = os.path.dirname(os.path.dirname(bext.get_ext_fullpath(self.name))) pyosys_path = os.path.join(build_path, "pyosys") - target = os.path.join(pyosys_path, os.path.basename(self.name)) os.makedirs(pyosys_path, exist_ok=True) - shutil.copyfile(self.name, target) + + # libyosys.so + target = os.path.join(pyosys_path, os.path.basename(self.name)) + shutil.copy(self.name, target) + bext.spawn(["strip", "-S", target]) + + # yosys-abc + yosys_abc_target = os.path.join(pyosys_path, "yosys-abc") + shutil.copy("yosys-abc", yosys_abc_target) + bext.spawn(["strip", "-S", "yosys-abc"]) + + # share directory + share_target = os.path.join(pyosys_path, "share") + try: + shutil.rmtree(share_target) + except FileNotFoundError: + pass + + shutil.copytree("share", share_target) # I don't know how debug info is getting here. - bext.spawn(["strip", "-S", target]) class custom_build_ext(build_ext): diff --git a/tests/arch/ecp5/add_sub.py b/tests/arch/ecp5/add_sub.py new file mode 100644 index 000000000..0232ac1db --- /dev/null +++ b/tests/arch/ecp5/add_sub.py @@ -0,0 +1,20 @@ +import os +from pyosys import libyosys as ys + +__dir__ = os.path.dirname(os.path.abspath(__file__)) +add_sub = os.path.join(__dir__, "..", "common", "add_sub.v") + +base = ys.Design() +ys.run_pass(f"read_verilog {add_sub}", base) +ys.run_pass("hierarchy -top top", base) +ys.run_pass("proc", base) +ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base) + +postopt = ys.Design() +ys.run_pass("design -load postopt", postopt) +ys.run_pass("cd top", postopt) +ys.run_pass("select -assert-min 25 t:LUT4", postopt) +ys.run_pass("select -assert-max 26 t:LUT4", postopt) +ys.run_pass("select -assert-count 10 t:PFUMX", postopt) +ys.run_pass("select -assert-count 6 t:L6MUX21", postopt) +ys.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D", postopt) From a6ccf2204787fb264dbd8cc23b998939ac5e41f6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 9 Oct 2024 14:09:10 +0200 Subject: [PATCH 324/342] force brew formula update --- .github/actions/setup-build-env/action.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index 12ae883bd..0c8cd281c 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -14,6 +14,7 @@ runs: if: runner.os == 'macOS' shell: bash run: | + HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew update HOMEBREW_NO_INSTALLED_DEPENDENTS_CHECK=1 brew install bison flex gawk libffi pkg-config bash autoconf llvm lld - name: Linux runtime environment From 575415ade2d8877b26944cf08ac3f6dd2ad3d035 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 9 Oct 2024 15:07:56 +0200 Subject: [PATCH 325/342] driver: switch to cxxopts, replace -B --- .gitmodules | 3 + kernel/driver.cc | 538 +++++++++++++++++++---------------------------- libs/cxxopts | 1 + 3 files changed, 219 insertions(+), 323 deletions(-) create mode 160000 libs/cxxopts diff --git a/.gitmodules b/.gitmodules index d88d4b1e5..de3bb2e74 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "abc"] path = abc url = https://github.com/YosysHQ/abc +[submodule "libs/cxxopts"] + path = libs/cxxopts + url = git@github.com:jarro2783/cxxopts.git diff --git a/kernel/driver.cc b/kernel/driver.cc index 53608c260..0c0dc9023 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -19,6 +19,8 @@ #include "kernel/yosys.h" #include "libs/sha1/sha1.h" +#include "libs/cxxopts/include/cxxopts.hpp" +#include #ifdef YOSYS_ENABLE_READLINE # include @@ -55,55 +57,6 @@ USING_YOSYS_NAMESPACE -char *optarg; -int optind = 1, optcur = 1, optopt = 0; -int getopt(int argc, char **argv, const char *optstring) -{ - if (optind >= argc) - return -1; - - if (argv[optind][0] != '-' || argv[optind][1] == 0) { - optopt = 1; - optarg = argv[optind++]; - return optopt; - } - - bool takes_arg = false; - optopt = argv[optind][optcur]; - - if (optopt == '-') { - ++optind; - return -1; - } - - for (int i = 0; optstring[i]; i++) - if (optopt == optstring[i] && optstring[i + 1] == ':') - takes_arg = true; - - if (!takes_arg) { - if (argv[optind][++optcur] == 0) - optind++, optcur = 1; - return optopt; - } - - if (argv[optind][++optcur]) { - optarg = argv[optind++] + optcur; - optcur = 1; - return optopt; - } - - if (++optind >= argc) { - fprintf(stderr, "%s: option '-%c' expects an argument\n", argv[0], optopt); - optopt = '?'; - return optopt; - } - - optarg = argv[optind]; - optind++, optcur = 1; - - return optopt; -} - #ifdef EMSCRIPTEN # include # include @@ -235,6 +188,7 @@ int main(int argc, char **argv) std::vector passes_commands; std::vector frontend_files; std::vector plugin_filenames; + std::vector special_args; std::string output_filename = ""; std::string scriptfile = ""; std::string depsfile = ""; @@ -251,305 +205,243 @@ int main(int argc, char **argv) bool mode_v = false; bool mode_q = false; - if (argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "-help") || !strcmp(argv[1], "--help"))) - { - printf("\n"); - printf("Usage: %s [options] [ [..]]\n", argv[0]); - printf("\n"); - printf(" -Q\n"); - printf(" suppress printing of banner (copyright, disclaimer, version)\n"); - printf("\n"); - printf(" -T\n"); - printf(" suppress printing of footer (log hash, version, timing statistics)\n"); - printf("\n"); - printf(" -q\n"); - printf(" quiet operation. only write warnings and error messages to console\n"); - printf(" use this option twice to also quiet warning messages\n"); - printf("\n"); - printf(" -v \n"); - printf(" print log headers up to level to the console. (this\n"); - printf(" implies -q for everything except the 'End of script.' message.)\n"); - printf("\n"); - printf(" -t\n"); - printf(" annotate all log messages with a time stamp\n"); - printf("\n"); - printf(" -d\n"); - printf(" print more detailed timing stats at exit\n"); - printf("\n"); - printf(" -l logfile\n"); - printf(" write log messages to the specified file\n"); - printf("\n"); - printf(" -L logfile\n"); - printf(" like -l but open log file in line buffered mode\n"); - printf("\n"); - printf(" -o outfile\n"); - printf(" write the design to the specified file on exit\n"); - printf("\n"); - printf(" -b backend\n"); - printf(" use this backend for the output file specified on the command line\n"); - printf("\n"); - printf(" -f frontend\n"); - printf(" use the specified frontend for the input files on the command line\n"); - printf("\n"); - printf(" -H\n"); - printf(" print the command list\n"); - printf("\n"); - printf(" -h command\n"); - printf(" print the help message for the specified command\n"); - printf("\n"); - printf(" -s scriptfile\n"); - printf(" execute the commands in the script file\n"); + cxxopts::Options options(argv[0], "Yosys Open SYnthesis Suite"); + options.set_width(SIZE_MAX); + + options.add_options("operation") + ("b,backend", "use for the output file specified on the command line", + cxxopts::value(), "") + ("f,frontend", "use for the input files on the command line", + cxxopts::value(), "") + ("s,scriptfile", "execute the commands in ", + cxxopts::value(), "") #ifdef YOSYS_ENABLE_TCL - printf("\n"); - printf(" -c tcl_scriptfile\n"); - printf(" execute the commands in the tcl script file (see 'help tcl' for details)\n"); - printf("\n"); - printf(" -C\n"); - printf(" enters TCL interactive shell mode\n"); -#endif + ("c,tcl-scriptfile", "execute the commands in the TCL (see 'help tcl' for details)", + cxxopts::value(),"") + ("C,tcl-interactive", "enters TCL interactive shell mode") +#endif // YOSYS_ENABLE_TCL #ifdef WITH_PYTHON - printf("\n"); - printf(" -y python_scriptfile\n"); - printf(" execute a python script with libyosys available as a built-in module\n"); -#endif - printf("\n"); - printf(" -p command\n"); - printf(" execute the commands (to chain commands, separate them with semicolon + whitespace: 'cmd1; cmd2')\n"); - printf("\n"); - printf(" -m module_file\n"); - printf(" load the specified module (aka plugin)\n"); - printf("\n"); - printf(" -X\n"); - printf(" enable tracing of core data structure changes. for debugging\n"); - printf("\n"); - printf(" -M\n"); - printf(" will slightly randomize allocated pointer addresses. for debugging\n"); - printf("\n"); - printf(" -A\n"); - printf(" will call abort() at the end of the script. for debugging\n"); - printf("\n"); - printf(" -r \n"); - printf(" elaborate command line arguments using the specified top module\n"); - printf("\n"); - printf(" -D [=]\n"); - printf(" set the specified Verilog define (via \"read -define\")\n"); - printf("\n"); - printf(" -P [:]\n"); - printf(" dump the design when printing the specified log header to a file.\n"); - printf(" yosys_dump_.il is used as filename if none is specified.\n"); - printf(" Use 'ALL' as to dump at every header.\n"); - printf("\n"); - printf(" -W regex\n"); - printf(" print a warning for all log messages matching the regex.\n"); - printf("\n"); - printf(" -w regex\n"); - printf(" if a warning message matches the regex, it is printed as regular\n"); - printf(" message instead.\n"); - printf("\n"); - printf(" -e regex\n"); - printf(" if a warning message matches the regex, it is printed as error\n"); - printf(" message instead and the tool terminates with a nonzero return code.\n"); - printf("\n"); - printf(" -E \n"); - printf(" write a Makefile dependencies file with in- and output file names\n"); - printf("\n"); - printf(" -x \n"); - printf(" do not print warnings for the specified experimental feature\n"); - printf("\n"); - printf(" -g\n"); - printf(" globally enable debug log messages\n"); - printf("\n"); - printf(" -V\n"); - printf(" print version information and exit\n"); - printf("\n"); - printf("The option -S is a shortcut for calling the \"synth\" command, a default\n"); - printf("script for transforming the Verilog input to a gate-level netlist. For example:\n"); - printf("\n"); - printf(" yosys -o output.blif -S input.v\n"); - printf("\n"); - printf("For more complex synthesis jobs it is recommended to use the read_* and write_*\n"); - printf("commands in a script file instead of specifying input and output files on the\n"); - printf("command line.\n"); - printf("\n"); - printf("When no commands, script files or input files are specified on the command\n"); - printf("line, yosys automatically enters the interactive command mode. Use the 'help'\n"); - printf("command to get information on the individual commands.\n"); - printf("\n"); + ("y,py-scriptfile", "execute the Python