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HACK to unconditionally debug bufnorm drivers in show output
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parent
4de384d776
commit
efb08dcdc2
2 changed files with 20 additions and 2 deletions
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@ -1880,6 +1880,7 @@ public:
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int width, start_offset, port_id;
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bool port_input, port_output, upto, is_signed;
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bool driverKnown() const { return driverCell_ != nullptr; }
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RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
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RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
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@ -267,7 +267,7 @@ struct ShowWorker
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return ret;
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}
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr)
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std::string gen_portbox(std::string port, RTLIL::SigSpec sig, bool driver, std::string *node = nullptr, std::string *forceColor = nullptr)
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{
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std::string code;
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std::string net = gen_signode_simple(sig);
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@ -355,6 +355,9 @@ struct ShowWorker
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else
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net_conn_map[net].out.insert({port, GetSize(sig)});
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net_conn_map[net].color = nextColor(sig, net_conn_map[net].color);
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if (forceColor)
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net_conn_map[net].color = *forceColor;
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}
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if (node != nullptr)
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*node = net;
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@ -496,8 +499,22 @@ struct ShowWorker
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std::string code;
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for (auto &conn : cell->connections()) {
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std::string force_color;
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if (conn.second.is_wire()) {
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RTLIL::PortDir pd = ct.cell_port_dir(cell->type, conn.first);
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if (pd != RTLIL::PD_INPUT) {
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Wire *wire = conn.second.as_wire();
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if (wire->driverKnown()) {
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if (wire->driverCell()->name == cell->name && wire->driverPort() == conn.first) {
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force_color = "color=green";
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} else {
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force_color = "color=red";
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}
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}
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}
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}
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code += gen_portbox(stringf("c%d:p%d", id2num(cell->name), id2num(conn.first)),
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conn.second, ct.cell_output(cell->type, conn.first));
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conn.second, ct.cell_output(cell->type, conn.first), nullptr, force_color.empty() ? nullptr : &force_color);
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}
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std::string src_href;
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