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Merge
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commit
ef98c62bf2
4 changed files with 114 additions and 1 deletions
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@ -2043,6 +2043,8 @@ struct RTLIL::Design
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void run_pass(std::string command);
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static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
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std::string to_rtlil_str(bool only_selected = true) const;
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};
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struct RTLIL::Module : public RTLIL::NamedObject
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@ -2409,6 +2411,7 @@ public:
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std::string rtlil_dump();
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unsigned int rtlil_hash();
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std::string to_rtlil_str() const;
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#ifdef YOSYS_ENABLE_PYTHON
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static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
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#endif
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@ -2462,6 +2465,7 @@ public:
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return zero_index + start_offset;
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}
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std::string to_rtlil_str() const;
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#ifdef YOSYS_ENABLE_PYTHON
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static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
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#endif
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@ -2479,6 +2483,8 @@ struct RTLIL::Memory : public RTLIL::NamedObject
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Memory();
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int width, start_offset, size;
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std::string to_rtlil_str() const;
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#ifdef YOSYS_ENABLE_PYTHON
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~Memory();
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static std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);
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@ -2537,6 +2543,8 @@ public:
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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std::string to_rtlil_str() const;
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#ifdef YOSYS_ENABLE_PYTHON
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static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
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#endif
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@ -2615,6 +2623,7 @@ public:
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::Process *clone() const;
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std::string to_rtlil_str() const;
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};
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