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address review comments

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Zachary Snow 2024-04-14 11:55:57 -04:00 • committed by Martin Povišer
parent 73cf658996
commit ef9772bd8d
2 changed files with 15 additions and 4 deletions
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8
tests/simple/memwr_port_connection.sv
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@ -5,11 +5,17 @@ module producer(
endmodule
module top(
output logic [3:0] out0, out1
output logic [3:0] out0, out1, out2, out3
);
logic [3:0] v[1:0];
logic [1:0] u[1:0];
logic [1:0] t[1:0];
producer p0(v[0]);
producer p1({v[1]});
producer p2({u[1], u[0]});
producer p3({{t[1]}, {t[0]}});
assign out0 = v[0];
assign out1 = v[1];
assign out2 = {u[1], u[0]};
assign out3 = {t[1], t[0]};
endmodule