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https://github.com/YosysHQ/yosys
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Improve simplec back-end
This commit is contained in:
Clifford Wolf
parent
7931e1ebb4
commit
ef7594ce3d
3 changed files with 79 additions and 13 deletions
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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@ -134,6 +135,8 @@ struct SimplecWorker
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dict<Module*, dict<SigBit, pool<tuple<Cell*, IdString, int>>>> bit2cell;
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dict<Module*, dict<SigBit, pool<SigBit>>> bit2output;
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dict<Cell*, int> topoidx;
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SimplecWorker(Design *design) : design(design)
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{
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}
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@ -290,11 +293,49 @@ struct SimplecWorker
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create_module_struct(design->module(c->type));
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}
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struct_declarations.push_back("");
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struct_declarations.push_back(stringf("struct %s_state_t {", cid(mod->name).c_str()));
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TopoSort<IdString> topo;
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for (Cell *c : mod->cells())
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{
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topo.node(c->name);
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for (auto &conn : c->connections())
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{
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if (!c->input(conn.first))
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continue;
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for (auto bit : sigmaps.at(mod)(conn.second))
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for (auto &it : bit2cell[mod][bit])
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topo.edge(c->name, std::get<0>(it)->name);
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}
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}
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topo.analyze_loops = false;
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topo.sort();
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for (int i = 0; i < GetSize(topo.sorted); i++)
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topoidx[mod->cell(topo.sorted[i])] = i;
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struct_declarations.push_back("");
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struct_declarations.push_back(stringf("struct %s_state_t", cid(mod->name).c_str()));
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struct_declarations.push_back("{");
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struct_declarations.push_back(" // Input Ports");
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for (Wire *w : mod->wires())
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struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
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if (w->port_input)
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struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
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struct_declarations.push_back("");
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struct_declarations.push_back(" // Output Ports");
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for (Wire *w : mod->wires())
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if (!w->port_input && w->port_output)
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struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
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struct_declarations.push_back("");
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struct_declarations.push_back(" // Internal Wires");
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for (Wire *w : mod->wires())
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if (!w->port_input && !w->port_output)
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struct_declarations.push_back(stringf(" %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));
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for (Cell *c : mod->cells())
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if (design->module(c->type))
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@ -303,7 +344,7 @@ struct SimplecWorker
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struct_declarations.push_back(stringf("};"));
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}
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void eval_cell(HierDirtyFlags *work, string &prefix, string &/* log_prefix */, Cell *cell)
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void eval_cell(HierDirtyFlags *work, const string &prefix, const string &/* log_prefix */, Cell *cell)
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{
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if (cell->type.in("$_BUF_", "$_NOT_"))
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{
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@ -420,10 +461,13 @@ struct SimplecWorker
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log_error("No C model for %s available at the moment (FIXME).\n", log_id(cell->type));
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}
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void eval_dirty(HierDirtyFlags *work, string prefix, string log_prefix, string parent_prefix)
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void eval_dirty(HierDirtyFlags *work, const string &prefix, const string &log_prefix, const string &parent_prefix, const string &parent_log_prefix)
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{
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while (work->dirty)
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{
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if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty()))
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log("In %s:\n", log_prefix.c_str());
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while (!work->dirty_bits.empty() || !work->dirty_cells.empty())
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{
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if (!work->dirty_bits.empty())
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@ -431,8 +475,11 @@ struct SimplecWorker
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SigSpec dirtysig(work->dirty_bits);
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dirtysig.sort_and_unify();
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for (SigChunk chunk : dirtysig.chunks())
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funct_declarations.push_back(stringf(" // New dirty bits in %s: %s", log_prefix.c_str(), log_signal(chunk)));
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for (SigChunk chunk : dirtysig.chunks()) {
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if (verbose)
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log(" Propagating %s.%s[%d:%d].\n", log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
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funct_declarations.push_back(stringf(" // Updated signal in %s: %s", log_prefix.c_str(), log_signal(chunk)));
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}
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for (SigBit bit : dirtysig)
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{
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@ -453,21 +500,34 @@ struct SimplecWorker
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util_get_bit(bit.wire->width, bit.offset).c_str(),
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(prefix + cid(bit.wire->name)).c_str()));
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work->parent->set_dirty(parent_bit);
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if (verbose)
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log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", log_prefix.c_str(), log_id(bit.wire), bit.offset,
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parent_log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset);
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}
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for (auto &port : bit2cell[work->module][bit])
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{
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if (work->children.count(std::get<0>(port)->name)) {
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if (work->children.count(std::get<0>(port)->name))
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{
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HierDirtyFlags *child = work->children.at(std::get<0>(port)->name);
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SigBit child_bit = sigmaps.at(child->module)(SigBit(child->module->wire(std::get<1>(port)), std::get<2>(port)));
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log_assert(bit.wire && child_bit.wire);
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funct_declarations.push_back(stringf(" %s(&%s, %s(&%s));",
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util_set_bit(child_bit.wire->width, child_bit.offset).c_str(),
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(prefix + cid(child->hiername) + "." + cid(child_bit.wire->name)).c_str(),
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util_get_bit(bit.wire->width, bit.offset).c_str(),
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(prefix + cid(bit.wire->name)).c_str()));
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child->set_dirty(child_bit);
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if (verbose)
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log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", log_prefix.c_str(), log_id(bit.wire), bit.offset,
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log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset);
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} else {
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if (verbose)
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log(" Marking cell %s.%s (via %s.%s[%d]).\n", log_prefix.c_str(), log_id(std::get<0>(port)),
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log_prefix.c_str(), log_id(bit.wire), bit.offset);
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work->set_dirty(std::get<0>(port));
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}
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}
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@ -477,14 +537,20 @@ struct SimplecWorker
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if (!work->dirty_cells.empty())
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{
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Cell *cell = *work->dirty_cells.begin();
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Cell *cell = nullptr;
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for (auto c : work->dirty_cells)
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if (cell == nullptr || topoidx.at(cell) < topoidx.at(c))
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cell = c;
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if (verbose)
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log(" Evaluating %s.%s (%s, best of %d).\n", log_prefix.c_str(), log_id(cell), log_id(cell->type), GetSize(work->dirty_cells));
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eval_cell(work, prefix, log_prefix, cell);
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work->unset_dirty(cell);
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}
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}
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for (auto &child : work->children)
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eval_dirty(child.second, prefix + cid(child.first) + ".", log_prefix + "." + cid(child.first), prefix);
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eval_dirty(child.second, prefix + cid(child.first) + ".", log_prefix + "." + cid(child.first), prefix, log_prefix);
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}
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}
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@ -509,7 +575,7 @@ struct SimplecWorker
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dirty_flags->set_dirty(bit);
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}
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eval_dirty(dirty_flags, "state->", log_id(mod), "");
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eval_dirty(dirty_flags, "state->", log_id(mod), "", "");
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funct_declarations.push_back("}");
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@ -1,5 +1,5 @@
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#!/bin/bash
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set -ex
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../../yosys -p 'synth -top test; write_simplec -i8 test00_uut.c' test00_uut.v
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../../yosys -p 'synth -top test; write_simplec -verbose -i8 test00_uut.c' test00_uut.v
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clang -o test00_tb test00_tb.c
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./test00_tb
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@ -16,7 +16,7 @@ int main()
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struct test_state_t state;
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uint32_t a, b, c, x, y, z;
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for (int i = 0; i < 100; i++)
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for (int i = 0; i < 10; i++)
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{
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a = xorshift32();
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b = xorshift32();
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