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opt_clean: refactor
This commit is contained in:
Emil J. Tywoniak
parent
17d667eab0
commit
ef536c4b1d
1 changed files with 98 additions and 93 deletions
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@ -665,18 +665,18 @@ struct AnalysisContext {
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AnalysisContext(RTLIL::Module* m, ParallelDispatchThreadPool::Subpool &p) : assign_map(m), mod(m), subpool(p) {}
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};
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struct SigAnalysis {
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// `registers` and `connected` will help us decide later on
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// on picking representatives out of groups of connected signals
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/**
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* What kinds of things are signals connected to?
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* Helps pick representatives out of groups of connected signals */
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struct SigConnKinds {
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// Wire bits driven by registers (with clk2fflogic exception)
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ShardedSigPool registers;
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// Wire bits connected to any cell port
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ShardedSigPool connected;
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ShardedSigPool cells;
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// construct a pool of wires which are directly driven by a known celltype,
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// this will influence our choice of representatives
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ShardedSigSpecPool direct;
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SigAnalysis(bool purge_mode, const AnalysisContext& actx) {
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SigConnKinds(bool purge_mode, const AnalysisContext& actx) {
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ShardedSigPool::Builder register_signals_builder(actx.subpool);
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ShardedSigPool::Builder connected_signals_builder(actx.subpool);
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ShardedSigSpecPool::Builder direct_sigs_builder(actx.subpool);
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@ -712,17 +712,17 @@ struct SigAnalysis {
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direct_sigs_builder.process(ctx);
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});
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registers = register_signals_builder;
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connected = connected_signals_builder;
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cells = connected_signals_builder;
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direct = direct_sigs_builder;
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}
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void clear(const ParallelDispatchThreadPool::RunCtx &ctx) {
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registers.clear(ctx);
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connected.clear(ctx);
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cells.clear(ctx);
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direct.clear(ctx);
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}
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};
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ShardedVector<RTLIL::SigBit> build_candidates(DirectWires& direct_wires, const SigAnalysis& sig_analysis, const AnalysisContext& actx) {
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ShardedVector<RTLIL::SigBit> build_candidates(DirectWires& direct_wires, const SigConnKinds& sig_analysis, const AnalysisContext& actx) {
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ShardedVector<RTLIL::SigBit> sigmap_canonical_candidates(actx.subpool);
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actx.subpool.run([&actx, &sig_analysis, &sigmap_canonical_candidates, &direct_wires](const ParallelDispatchThreadPool::RunCtx &ctx) {
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std::optional<DirectWires> local_direct_wires;
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@ -738,7 +738,7 @@ ShardedVector<RTLIL::SigBit> build_candidates(DirectWires& direct_wires, const S
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for (int j = 0; j < wire->width; ++j) {
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RTLIL::SigBit s1(wire, j);
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RTLIL::SigBit s2 = actx.assign_map(s1);
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if (compare_signals(s2, s1, sig_analysis.registers, sig_analysis.connected, *this_thread_direct_wires))
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if (compare_signals(s2, s1, sig_analysis.registers, sig_analysis.cells, *this_thread_direct_wires))
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sigmap_canonical_candidates.insert(ctx, s1);
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}
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}
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@ -746,89 +746,95 @@ ShardedVector<RTLIL::SigBit> build_candidates(DirectWires& direct_wires, const S
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return sigmap_canonical_candidates;
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}
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bool update_assign_map(ShardedVector<RTLIL::SigBit>& sigmap_canonical_candidates, DirectWires& direct_wires, const SigAnalysis& sig_analysis, SigMap& assign_map) {
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void update_assign_map(ShardedVector<RTLIL::SigBit>& sigmap_canonical_candidates, DirectWires& direct_wires, const SigConnKinds& sig_analysis, SigMap& assign_map) {
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for (RTLIL::SigBit candidate : sigmap_canonical_candidates) {
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RTLIL::SigBit current_canonical = assign_map(candidate);
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if (compare_signals(current_canonical, candidate, sig_analysis.registers, sig_analysis.connected, direct_wires))
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if (compare_signals(current_canonical, candidate, sig_analysis.registers, sig_analysis.cells, direct_wires))
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assign_map.add(candidate);
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}
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}
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struct UsedSigAnalysis {
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struct DeferredUpdates {
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// Deferred updates to the assign_map
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ShardedVector<UpdateConnection> update_connections;
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// Wires we should remove init from
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ShardedVector<RTLIL::Wire*> initialized_wires;
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DeferredUpdates(ParallelDispatchThreadPool::Subpool &subpool) : update_connections(subpool), initialized_wires(subpool) {}
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};
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struct UsedSignals {
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// here, "used" means "driven or driving something"
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// meanwhile, "unused" means "driving nothing"
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// TODO ...
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// used signals sigmapped
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ShardedSigPool used;
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ShardedSigPool connected;
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// used signals pre-sigmapped
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ShardedSigPool raw_used;
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ShardedSigPool raw_connected;
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// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
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ShardedSigPool used_nodrivers;
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ShardedSigPool used;
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// Deferred updates to the assign_map
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ShardedVector<UpdateConnection> update_connections;
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ShardedVector<RTLIL::Wire*> initialized_wires;
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UsedSigAnalysis(SigAnalysis& sig_analysis, const AnalysisContext& actx) : update_connections(actx.subpool), initialized_wires(actx.subpool) {
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ShardedSigPool::Builder used_builder(actx.subpool);
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ShardedSigPool::Builder raw_used_builder(actx.subpool);
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ShardedSigPool::Builder used_nodrivers_builder(actx.subpool);
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// gather the usage information for cells and update cell connections with the altered sigmap
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// also gather the usage information for ports, wires with `keep`
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// also gather init bits
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actx.subpool.run([&actx, &sig_analysis, &used_builder, &raw_used_builder, &used_nodrivers_builder, this](const ParallelDispatchThreadPool::RunCtx &ctx) {
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// Parallel destruction of these sharded structures
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sig_analysis.clear(ctx);
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for (int i : ctx.item_range(actx.mod->cells_size())) {
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RTLIL::Cell *cell = actx.mod->cell_at(i);
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for (const auto &[port, sig] : cell->connections_) {
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SigSpec spec = actx.assign_map(sig);
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if (spec != sig)
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update_connections.insert(ctx, {cell, port, spec});
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add_spec(raw_used_builder, ctx, spec);
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add_spec(used_builder, ctx, spec);
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if (!ct_all.cell_output(cell->type, port))
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add_spec(used_nodrivers_builder, ctx, spec);
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}
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}
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for (int i : ctx.item_range(actx.mod->wires_size())) {
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RTLIL::Wire *wire = actx.mod->wire_at(i);
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if (wire->port_id > 0) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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add_spec(raw_used_builder, ctx, sig);
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actx.assign_map.apply(sig);
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add_spec(used_builder, ctx, sig);
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if (!wire->port_input)
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add_spec(used_nodrivers_builder, ctx, sig);
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}
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if (wire->get_bool_attribute(ID::keep)) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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actx.assign_map.apply(sig);
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add_spec(used_builder, ctx, sig);
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}
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auto it = wire->attributes.find(ID::init);
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if (it != wire->attributes.end())
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initialized_wires.insert(ctx, wire);
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}
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void clear(ParallelDispatchThreadPool::Subpool &subpool) {
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subpool.run([this](const ParallelDispatchThreadPool::RunCtx &ctx) {
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connected.clear(ctx);
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raw_connected.clear(ctx);
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used.clear(ctx);
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});
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actx.subpool.run([&used_builder, &raw_used_builder, &used_nodrivers_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
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used_builder.process(ctx);
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raw_used_builder.process(ctx);
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used_nodrivers_builder.process(ctx);
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});
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ShardedSigPool used_signals(used_builder);
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ShardedSigPool raw_used_signals(raw_used_builder);
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ShardedSigPool used_signals_nodrivers(used_nodrivers_builder);
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}
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void clear(const ParallelDispatchThreadPool::RunCtx &ctx) {
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used.clear(ctx);
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raw_used.clear(ctx);
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used_nodrivers.clear(ctx);
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}
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};
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std::tuple<DeferredUpdates, UsedSignals> analyse_connectivity(SigConnKinds& sig_analysis, const AnalysisContext& actx) {
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DeferredUpdates deferred(actx.subpool);
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ShardedSigPool::Builder used_builder(actx.subpool);
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ShardedSigPool::Builder raw_used_builder(actx.subpool);
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ShardedSigPool::Builder used_nodrivers_builder(actx.subpool);
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// gather the usage information for cells and update cell connections with the altered sigmap
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// also gather the usage information for ports, wires with `keep`
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// also gather init bits
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actx.subpool.run([&deferred, &used_builder, &raw_used_builder, &used_nodrivers_builder, &sig_analysis, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
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// Parallel destruction of these sharded structures
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sig_analysis.clear(ctx);
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for (int i : ctx.item_range(actx.mod->cells_size())) {
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RTLIL::Cell *cell = actx.mod->cell_at(i);
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for (const auto &[port, sig] : cell->connections_) {
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SigSpec spec = actx.assign_map(sig);
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if (spec != sig)
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deferred.update_connections.insert(ctx, {cell, port, spec});
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add_spec(raw_used_builder, ctx, spec);
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add_spec(used_builder, ctx, spec);
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if (!ct_all.cell_output(cell->type, port))
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add_spec(used_nodrivers_builder, ctx, spec);
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}
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}
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for (int i : ctx.item_range(actx.mod->wires_size())) {
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RTLIL::Wire *wire = actx.mod->wire_at(i);
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if (wire->port_id > 0) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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add_spec(raw_used_builder, ctx, sig);
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actx.assign_map.apply(sig);
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add_spec(used_builder, ctx, sig);
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if (!wire->port_input)
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add_spec(used_nodrivers_builder, ctx, sig);
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}
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if (wire->get_bool_attribute(ID::keep)) {
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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actx.assign_map.apply(sig);
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add_spec(used_builder, ctx, sig);
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}
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auto it = wire->attributes.find(ID::init);
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if (it != wire->attributes.end())
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deferred.initialized_wires.insert(ctx, wire);
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}
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});
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actx.subpool.run([&used_builder, &raw_used_builder, &used_nodrivers_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
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used_builder.process(ctx);
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raw_used_builder.process(ctx);
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used_nodrivers_builder.process(ctx);
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});
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UsedSignals used {used_builder, raw_used_builder, used_nodrivers_builder};
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return {std::move(deferred), std::move(used)};
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}
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struct WireDeleter {
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pool<RTLIL::Wire*> del_wires_queue;
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ShardedVector<RTLIL::Wire*> remove_init;
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@ -836,7 +842,7 @@ struct WireDeleter {
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ShardedVector<RTLIL::SigSig> new_connections;
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ShardedVector<RTLIL::Wire*> remove_unused_bits;
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ShardedVector<std::pair<RTLIL::Wire*, RTLIL::Const>> set_unused_bits;
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WireDeleter(UsedSigAnalysis& used_sig_analysis, bool purge_mode, const AnalysisContext& actx) :
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WireDeleter(UsedSignals& used_sig_analysis, bool purge_mode, const AnalysisContext& actx) :
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remove_init(actx.subpool),
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set_init(actx.subpool),
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new_connections(actx.subpool),
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@ -867,10 +873,10 @@ struct WireDeleter {
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if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
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// do not delete anything with "keep" or module ports or initialized wires
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} else
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if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_used, s1) || check_any(used_sig_analysis.used, s2) || s1 != s2)) {
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if (!purge_mode && check_public_name(wire->name) && (check_any(used_sig_analysis.raw_connected, s1) || check_any(used_sig_analysis.connected, s2) || s1 != s2)) {
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// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
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} else
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if (!check_any(used_sig_analysis.raw_used, s1)) {
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if (!check_any(used_sig_analysis.raw_connected, s1)) {
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// delete wires that aren't used by anything directly
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goto delete_this_wire;
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}
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@ -903,12 +909,12 @@ struct WireDeleter {
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set_init.insert(ctx, {wire, std::move(initval)});
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std::string unused_bits;
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if (!check_all(used_sig_analysis.used_nodrivers, s2)) {
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if (!check_all(used_sig_analysis.used, s2)) {
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for (int i = 0; i < GetSize(s2); i++) {
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if (s2[i].wire == NULL)
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continue;
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SigBit b = s2[i];
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if (used_sig_analysis.used_nodrivers.find({b, b.hash_top().yield()}) == nullptr) {
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if (used_sig_analysis.used.find({b, b.hash_top().yield()}) == nullptr) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%d", i);
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@ -962,32 +968,31 @@ struct WireDeleter {
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bool rmunused_module_signals(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool purge_mode, bool verbose, RmStats &stats)
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{
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AnalysisContext actx(module, subpool);
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SigAnalysis sig_analysis(purge_mode, actx);
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SigConnKinds conn_kinds(purge_mode, actx);
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// Main thread's cached direct wires are retained and used later:
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DirectWires direct_wires(sig_analysis.direct, actx.assign_map);
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DirectWires direct_wires(conn_kinds.direct, actx.assign_map);
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// Other threads' caches get discarded when threads finish in build_candidates
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// but the per-thread results are collected into sigmap_canonical_candidates
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ShardedVector<RTLIL::SigBit> sigmap_canonical_candidates = build_candidates(direct_wires, sig_analysis, actx);
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ShardedVector<RTLIL::SigBit> sigmap_canonical_candidates = build_candidates(direct_wires, conn_kinds, actx);
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// Cache all the direct_wires results that we might possible need. This avoids the results
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// changing when we update `assign_map` below.
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direct_wires.cache_all(sigmap_canonical_candidates);
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// Modify assign_map to reflect the connectivity we want, not the one we have
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update_assign_map(sigmap_canonical_candidates, direct_wires, sig_analysis, actx.assign_map);
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update_assign_map(sigmap_canonical_candidates, direct_wires, conn_kinds, actx.assign_map);
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// Remove all wire-wire connections
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module->connections_.clear();
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UsedSigAnalysis used_sig_analysis(sig_analysis, actx);
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fixup_update_ports(used_sig_analysis.update_connections);
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consume_inits(used_sig_analysis.initialized_wires, actx.assign_map).apply_normalised_inits();
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// UsedSigConnKinds used_sig_analysis(sig_analysis, actx);
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auto [deferred, used] = analyse_connectivity(conn_kinds, actx);
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fixup_update_ports(deferred.update_connections);
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consume_inits(deferred.initialized_wires, actx.assign_map).apply_normalised_inits();
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WireDeleter deleter(used_sig_analysis, purge_mode, actx);
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WireDeleter deleter(used, purge_mode, actx);
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subpool.run([&used_sig_analysis](const ParallelDispatchThreadPool::RunCtx &ctx) {
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used_sig_analysis.clear(ctx);
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});
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used.clear(subpool);
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deleter.commit_changes(module);
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int deleted_and_unreported = deleter.delete_wires(module, verbose);
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