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https://github.com/YosysHQ/yosys
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Add SV "rand" and "const rand" support
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1d1f56a361
commit
ef4a28e112
3 changed files with 33 additions and 10 deletions
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@ -59,6 +59,7 @@ namespace VERILOG_FRONTEND {
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bool default_nettype_wire;
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bool sv_mode, formal_mode, lib_mode;
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bool norestrict_mode, assume_asserts_mode;
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bool current_wire_rand, current_wire_const;
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std::istream *lexin;
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}
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YOSYS_NAMESPACE_END
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@ -100,7 +101,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
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bool boolean;
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}
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%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REALVAL TOK_PRIMITIVE
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%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
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%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
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%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
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%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
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@ -115,6 +116,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
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%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
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%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
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%token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
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%token TOK_RAND TOK_CONST
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%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
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%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
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@ -355,6 +357,8 @@ delay:
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wire_type:
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{
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astbuf3 = new AstNode(AST_WIRE);
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current_wire_rand = false;
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current_wire_const = false;
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} wire_type_token_list delay {
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$$ = astbuf3;
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};
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@ -392,6 +396,12 @@ wire_type_token:
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} |
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TOK_SIGNED {
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astbuf3->is_signed = true;
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} |
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TOK_RAND {
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current_wire_rand = true;
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} |
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TOK_CONST {
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current_wire_const = true;
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};
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non_opt_range:
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@ -730,7 +740,15 @@ wire_name_list:
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wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
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wire_name_and_opt_assign:
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wire_name |
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wire_name {
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if (current_wire_rand) {
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AstNode *wire = new AstNode(AST_IDENTIFIER);
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AstNode *fcall = new AstNode(AST_FCALL);
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wire->str = ast_stack.back()->children.back()->str;
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fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq";
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ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
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}
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} |
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wire_name '=' expr {
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AstNode *wire = new AstNode(AST_IDENTIFIER);
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wire->str = ast_stack.back()->children.back()->str;
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@ -1362,7 +1380,7 @@ basic_expr:
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rvalue {
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$$ = $1;
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} |
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'(' expr ')' TOK_CONST {
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'(' expr ')' TOK_CONSTVAL {
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if ($4->substr(0, 1) != "'")
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frontend_verilog_yyerror("Syntax error.");
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AstNode *bits = $2;
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@ -1372,7 +1390,7 @@ basic_expr:
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$$ = new AstNode(AST_TO_BITS, bits, val);
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delete $4;
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} |
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hierarchical_id TOK_CONST {
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hierarchical_id TOK_CONSTVAL {
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if ($2->substr(0, 1) != "'")
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frontend_verilog_yyerror("Syntax error.");
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AstNode *bits = new AstNode(AST_IDENTIFIER);
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@ -1384,14 +1402,14 @@ basic_expr:
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delete $1;
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delete $2;
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} |
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TOK_CONST TOK_CONST {
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TOK_CONSTVAL TOK_CONSTVAL {
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$$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
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if ($$ == NULL || (*$2)[0] != '\'')
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log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
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delete $1;
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delete $2;
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} |
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TOK_CONST {
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TOK_CONSTVAL {
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$$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
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if ($$ == NULL)
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log_error("Value conversion failed: `%s'\n", $1->c_str());
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