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verific: set VHDL entity source location from another attribute if available

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This commit is contained in:
Miodrag Milanovic 2025-03-31 08:48:11 +02:00
parent 314842d2a0
commit ef3c16d4c4
2 changed files with 9 additions and 5 deletions
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12
frontends/verific/verific.cc
View file

@ -408,7 +408,7 @@ static const std::string verific_unescape(const char *value)
} }
#endif #endif
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint) void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl, int wire_width_hint, bool is_module)
{ {
if (!obj) if (!obj)
return; return;
@ -416,15 +416,19 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
MapIter mi; MapIter mi;
Att *attr; Att *attr;
IdString src = ID::src;
if (is_module && nl->IsFromVhdl() && nl->GetAtt(" src_entity")) src = ID(src_architecture);
#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS #ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
if (obj->Linefile()) if (obj->Linefile())
attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); attributes[src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
#else #else
if (obj->Linefile()) if (obj->Linefile())
attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); attributes[src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
#endif #endif
FOREACH_ATTRIBUTE(obj, mi, attr) { FOREACH_ATTRIBUTE(obj, mi, attr) {
if (is_module && nl->IsFromVhdl() && std::string(attr->Key())==" src_entity")
attributes[ID::src] = verific_const(nullptr, attr->Value(), obj);
if (attr->Key()[0] == ' ' || attr->Value() == nullptr) if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
continue; continue;
attributes[RTLIL::escape_id(attr->Key())] = verific_const(nullptr, attr->Value(), obj); attributes[RTLIL::escape_id(attr->Key())] = verific_const(nullptr, attr->Value(), obj);
@ -1464,7 +1468,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
} else { } else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl, -1, true);
if (module->name.isPublic()) if (module->name.isPublic())
module->set_string_attribute(ID::hdlname, nl->CellBaseName()); module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name()); module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());

2
frontends/verific/verific.h
View file

@ -81,7 +81,7 @@ struct VerificImporter
RTLIL::SigBit net_map_at(Verific::Net *net); RTLIL::SigBit net_map_at(Verific::Net *net);
RTLIL::IdString new_verific_id(Verific::DesignObj *obj); RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr, int wire_width_hint = -1); void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr, int wire_width_hint = -1, bool is_module = false);
RTLIL::SigBit netToSigBit(Verific::Net *net); RTLIL::SigBit netToSigBit(Verific::Net *net);
RTLIL::SigSpec operatorInput(Verific::Instance *inst); RTLIL::SigSpec operatorInput(Verific::Instance *inst);