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Revert "Widen $polarity cell to multiple ports"

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This reverts commit 0c7afe8e31.
This commit is contained in:
Emil J. Tywoniak 2026-01-19 12:22:50 +01:00
parent 57fa330572
commit eee069e5a4
8 changed files with 58 additions and 74 deletions
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29
techlibs/common/techmap.v
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@ -683,33 +683,30 @@ endmodule
(* techmap_celltype = "$priority" *)
module \$priority (A, Y);
parameter WIDTH = 0;
parameter P_WIDTH = 0;
parameter POLARITY = 0;
(* force_downto *)
input [P_WIDTH*WIDTH-1:0] A;
input [WIDTH-1:0] A;
(* force_downto *)
output [P_WIDTH*WIDTH-1:0] Y;
output [WIDTH-1:0] Y;
(* force_downto *)
wire [P_WIDTH*WIDTH-1:0] tmp;
wire [WIDTH-1:0] tmp;
(* force_downto *)
wire [P_WIDTH*WIDTH-1:0] A_active;
wire [P_WIDTH*WIDTH-1:0] Y_active;
wire [WIDTH-1:0] A_active;
wire [WIDTH-1:0] Y_active;
assign A_active = A ^ ~POLARITY;
assign Y = Y_active ^ ~POLARITY;
genvar i, offset;
genvar i;
generate
for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
if (P_WIDTH > 0) begin
assign tmp[offset] = A_active[offset];
assign Y_active[offset] = A_active[offset];
end
for (i = offset + 1; i < offset + P_WIDTH; i = i + 1) begin
assign Y_active[i] = tmp[i - 1] ? 1'b0 : A_active[i];
assign tmp[i] = tmp[i - 1] | A_active[i];
end
if (WIDTH > 0) begin
assign tmp[0] = A_active[0];
assign Y_active[0] = A_active[0];
end
for (i = 1; i < WIDTH; i = i + 1) begin
assign Y_active[i] = tmp[i-1] ? 1'b0 : A_active[i];
assign tmp[i] = tmp[i-1] | A_active[i];
end
endgenerate