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read_aiger: uniquify wires with $aiger<autoidx> prefix

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This commit is contained in:
Eddie Hung 2020-01-13 21:28:27 -08:00
parent 565d349dc9
commit ee95fa959a
2 changed files with 13 additions and 9 deletions
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19
frontends/aiger/aigerparse.cc
View file

@ -206,7 +206,7 @@ eval_end:
}; };
AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports) AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports) : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports), aiger_autoidx(autoidx++)
{ {
module = new RTLIL::Module; module = new RTLIL::Module;
module->name = module_name; module->name = module_name;
@ -323,18 +323,18 @@ static uint32_t parse_xaiger_literal(std::istream &f)
return from_big_endian(l); return from_big_endian(l);
} }
static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal) RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned literal)
{ {
const unsigned variable = literal >> 1; const unsigned variable = literal >> 1;
const bool invert = literal & 1; const bool invert = literal & 1;
RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
RTLIL::Wire *wire = module->wire(wire_name); RTLIL::Wire *wire = module->wire(wire_name);
if (wire) return wire; if (wire) return wire;
log_debug2("Creating %s\n", wire_name.c_str()); log_debug2("Creating %s\n", wire_name.c_str());
wire = module->addWire(wire_name); wire = module->addWire(wire_name);
wire->port_input = wire->port_output = false; wire->port_input = wire->port_output = false;
if (!invert) return wire; if (!invert) return wire;
RTLIL::IdString wire_inv_name(stringf("$%d", variable)); RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
RTLIL::Wire *wire_inv = module->wire(wire_inv_name); RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
if (wire_inv) { if (wire_inv) {
if (module->cell(wire_inv_name)) return wire; if (module->cell(wire_inv_name)) return wire;
@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
} }
log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
module->addNotGate(stringf("$not$%d", variable), wire_inv, wire); module->addNotGate(stringf("$not$aiger%d$%d", aiger_autoidx, variable), wire_inv, wire);
return wire; return wire;
} }
@ -422,13 +422,14 @@ void AigerReader::parse_xaiger()
uint32_t rootNodeID = parse_xaiger_literal(f); uint32_t rootNodeID = parse_xaiger_literal(f);
uint32_t cutLeavesM = parse_xaiger_literal(f); uint32_t cutLeavesM = parse_xaiger_literal(f);
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
RTLIL::Wire *output_sig = module->wire(stringf("$%d", rootNodeID)); RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_sig);
uint32_t nodeID; uint32_t nodeID;
RTLIL::SigSpec input_sig; RTLIL::SigSpec input_sig;
for (unsigned j = 0; j < cutLeavesM; ++j) { for (unsigned j = 0; j < cutLeavesM; ++j) {
nodeID = parse_xaiger_literal(f); nodeID = parse_xaiger_literal(f);
log_debug2("\t%u\n", nodeID); log_debug2("\t%u\n", nodeID);
RTLIL::Wire *wire = module->wire(stringf("$%d", nodeID)); RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
log_assert(wire); log_assert(wire);
input_sig.append(wire); input_sig.append(wire);
} }
@ -445,10 +446,10 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr); log_assert(o.wire == nullptr);
lut_mask[gray] = o.data; lut_mask[gray] = o.data;
} }
RTLIL::Cell *output_cell = module->cell(stringf("$and$%d", rootNodeID)); RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_cell); log_assert(output_cell);
module->remove(output_cell); module->remove(output_cell);
module->addLut(stringf("$lut$%d", rootNodeID), input_sig, output_sig, std::move(lut_mask)); module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::move(lut_mask));
} }
} }
else if (c == 'r') { else if (c == 'r') {

3
frontends/aiger/aigerparse.h
View file

@ -33,6 +33,7 @@ struct AigerReader
RTLIL::Module *module; RTLIL::Module *module;
std::string map_filename; std::string map_filename;
bool wideports; bool wideports;
const int aiger_autoidx;
unsigned M, I, L, O, A; unsigned M, I, L, O, A;
unsigned B, C, J, F; // Optional in AIGER 1.9 unsigned B, C, J, F; // Optional in AIGER 1.9
@ -51,6 +52,8 @@ struct AigerReader
void parse_aiger_ascii(); void parse_aiger_ascii();
void parse_aiger_binary(); void parse_aiger_binary();
void post_process(); void post_process();
RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal);
}; };
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END