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Remove references to ilang

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Krystine Sherwin 2024-11-05 12:36:31 +13:00
parent 52c231dd64
commit ee73a91f44
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28 changed files with 39 additions and 69 deletions
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tests/verilog/assign_to_reg.ys
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@ -1,6 +1,6 @@
# https://github.com/yosyshq/yosys/issues/2035
read_ilang <<END
read_rtlil <<END
module \top
wire width 1 input 0 \halfbrite
wire width 2 output 1 \r_on