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Remove references to ilang
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28 changed files with 39 additions and 69 deletions
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@ -1,4 +1,4 @@
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read_ilang << EOT
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read_rtlil << EOT
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module \top
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wire width 4 input 1 \a
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wire width 2 input 2 \b
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@ -188,7 +188,7 @@ equiv_opt -assert -run prepare: dummy
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design -reset
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read_ilang <<EOT
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read_rtlil <<EOT
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module \m
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wire width 3 input 1 \a
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