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Remove WIP ABC9 flop support

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This commit is contained in:
Eddie Hung 2019-06-14 10:37:52 -07:00
parent 42f6b48d56
commit ee428f73ab
5 changed files with 78 additions and 78 deletions
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64
backends/aiger/xaiger.cc
View file

@ -219,37 +219,37 @@ struct XAigerWriter
//}
RTLIL::Module* inst_module = module->design->module(cell->type);
bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
if (inst_flop) {
SigBit d, q;
for (const auto &c : cell->connections()) {
auto is_input = cell->input(c.first);
auto is_output = cell->output(c.first);
log_assert(is_input || is_output);
RTLIL::Wire* port = inst_module->wire(c.first);
for (auto b : c.second.bits()) {
if (is_input && port->attributes.count("\\abc_flop_d")) {
d = b;
SigBit I = sigmap(d);
if (I != d)
alias_map[I] = d;
unused_bits.erase(d);
}
if (is_output && port->attributes.count("\\abc_flop_q")) {
q = b;
SigBit O = sigmap(q);
if (O != q)
alias_map[O] = q;
undriven_bits.erase(O);
}
}
}
if (!abc_box_seen)
abc_box_seen = inst_module->attributes.count("\\abc_box_id");
//bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
//if (inst_flop) {
// SigBit d, q;
// for (const auto &c : cell->connections()) {
// auto is_input = cell->input(c.first);
// auto is_output = cell->output(c.first);
// log_assert(is_input || is_output);
// RTLIL::Wire* port = inst_module->wire(c.first);
// for (auto b : c.second.bits()) {
// if (is_input && port->attributes.count("\\abc_flop_d")) {
// d = b;
// SigBit I = sigmap(d);
// if (I != d)
// alias_map[I] = d;
// unused_bits.erase(d);
// }
// if (is_output && port->attributes.count("\\abc_flop_q")) {
// q = b;
// SigBit O = sigmap(q);
// if (O != q)
// alias_map[O] = q;
// undriven_bits.erase(O);
// }
// }
// }
// if (!abc_box_seen)
// abc_box_seen = inst_module->attributes.count("\\abc_box_id");
ff_bits.emplace_back(d, q);
}
else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
// ff_bits.emplace_back(d, q);
//}
/*else*/ if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
abc_box_seen = true;
}
else {
@ -310,8 +310,8 @@ struct XAigerWriter
if (cell->output(conn.first)) {
RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
log_assert(inst_module_port);
if (inst_module_port->attributes.count("\\abc_flop_q"))
continue;
//if (inst_module_port->attributes.count("\\abc_flop_q"))
// continue;
for (auto bit : topomap(conn.second))
bit_drivers[bit].insert(cell->name);
}

6
techlibs/ecp5/cells_sim.v
View file

@ -213,7 +213,7 @@ endmodule
// ---------------------------------------
module TRELLIS_FF(input CLK, LSR, CE, DI, M, (* abc_flop_q *) output reg Q);
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
@ -474,13 +474,13 @@ module DP16KD(
input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
input CEA, OCEA, CLKA, WEA, RSTA,
input CSA2, CSA1, CSA0,
(* abc_flop_q *) output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
input CEB, OCEB, CLKB, WEB, RSTB,
input CSB2, CSB1, CSB0,
(* abc_flop_q *) output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
);
parameter DATA_WIDTH_A = 18;
parameter DATA_WIDTH_B = 18;

50
techlibs/ice40/cells_sim.v
View file

@ -143,7 +143,7 @@ endmodule
// Positive Edge SiliconBlue FF Cells
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
module SB_DFF (output `SB_DFF_REG, input C, D);
`ifndef _ABC
always @(posedge C)
Q <= D;
@ -152,13 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
`endif
endmodule
module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
module SB_DFFE (output `SB_DFF_REG, input C, E, D);
always @(posedge C)
if (E)
Q <= D;
endmodule
module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
always @(posedge C)
if (R)
Q <= 0;
@ -166,7 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
module SB_DFFR (output `SB_DFF_REG, input C, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@ -174,7 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
always @(posedge C)
if (S)
Q <= 1;
@ -182,7 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
module SB_DFFS (output `SB_DFF_REG, input C, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@ -190,7 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
always @(posedge C)
if (E) begin
if (R)
@ -200,7 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
end
endmodule
module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@ -208,7 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
always @(posedge C)
if (E) begin
if (S)
@ -218,7 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
end
endmodule
module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@ -228,18 +228,18 @@ endmodule
// Negative Edge SiliconBlue FF Cells
module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
module SB_DFFN (output `SB_DFF_REG, input C, D);
always @(negedge C)
Q <= D;
endmodule
module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
always @(negedge C)
if (E)
Q <= D;
endmodule
module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
always @(negedge C)
if (R)
Q <= 0;
@ -247,7 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@ -255,7 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
always @(negedge C)
if (S)
Q <= 1;
@ -263,7 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@ -271,7 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
always @(negedge C)
if (E) begin
if (R)
@ -281,7 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
end
endmodule
module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@ -289,7 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
always @(negedge C)
if (E) begin
if (S)
@ -299,7 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
end
endmodule
module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@ -310,7 +310,7 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
(* abc_flop_q *) output [15:0] RDATA,
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@ -478,7 +478,7 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
(* abc_flop_q *) output [15:0] RDATA,
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
@ -543,7 +543,7 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
(* abc_flop_q *) output [15:0] RDATA,
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@ -608,7 +608,7 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
(* abc_flop_q *) output [15:0] RDATA,
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
input WCLKN, WCLKE, WE,
@ -902,7 +902,7 @@ module SB_SPRAM256KA (
input [15:0] DATAIN,
input [3:0] MASKWREN,
input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
(* abc_flop_q *) output reg [15:0] DATAOUT
output reg [15:0] DATAOUT
);
`ifndef BLACKBOX
`ifndef EQUIV

16
techlibs/xilinx/brams_bb.v
View file

@ -19,10 +19,10 @@ module RAMB18E1 (
input [1:0] WEA,
input [3:0] WEBWE,
(* abc_flop_q *) output [15:0] DOADO,
(* abc_flop_q *) output [15:0] DOBDO,
(* abc_flop_q *) output [1:0] DOPADOP,
(* abc_flop_q *) output [1:0] DOPBDOP
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -143,10 +143,10 @@ module RAMB36E1 (
input [3:0] WEA,
input [7:0] WEBWE,
(* abc_flop_q *) output [31:0] DOADO,
(* abc_flop_q *) output [31:0] DOBDO,
(* abc_flop_q *) output [3:0] DOPADOP,
(* abc_flop_q *) output [3:0] DOPBDOP
output [31:0] DOADO,
output [31:0] DOBDO,
output [3:0] DOPADOP,
output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

20
techlibs/xilinx/cells_sim.v
View file

@ -205,7 +205,7 @@ endmodule
`endif
module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R);
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -217,7 +217,7 @@ module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R);
endcase endgenerate
endmodule
module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -229,7 +229,7 @@ module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S);
endcase endgenerate
endmodule
module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -243,7 +243,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
endcase endgenerate
endmodule
module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -257,25 +257,25 @@ module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
endcase endgenerate
endmodule
module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R);
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S);
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR);
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
@ -315,7 +315,7 @@ module RAM128X1D (
endmodule
module SRL16E (
(* abc_flop_q *) output Q,
output Q,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
@ -333,7 +333,7 @@ module SRL16E (
endmodule
module SRLC32E (
(* abc_flop_q *) output Q,
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D