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https://github.com/YosysHQ/yosys
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Remove WIP ABC9 flop support
This commit is contained in:
Eddie Hung
parent
42f6b48d56
commit
ee428f73ab
5 changed files with 78 additions and 78 deletions
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@ -143,7 +143,7 @@ endmodule
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// Positive Edge SiliconBlue FF Cells
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module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
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module SB_DFF (output `SB_DFF_REG, input C, D);
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`ifndef _ABC
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always @(posedge C)
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Q <= D;
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@ -152,13 +152,13 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
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`endif
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endmodule
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module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
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module SB_DFFE (output `SB_DFF_REG, input C, E, D);
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always @(posedge C)
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if (E)
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Q <= D;
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endmodule
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module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
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always @(posedge C)
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if (R)
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Q <= 0;
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@ -166,7 +166,7 @@ module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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Q <= D;
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endmodule
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module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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module SB_DFFR (output `SB_DFF_REG, input C, R, D);
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always @(posedge C, posedge R)
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if (R)
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Q <= 0;
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@ -174,7 +174,7 @@ module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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Q <= D;
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endmodule
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module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
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always @(posedge C)
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if (S)
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Q <= 1;
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@ -182,7 +182,7 @@ module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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Q <= D;
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endmodule
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module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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module SB_DFFS (output `SB_DFF_REG, input C, S, D);
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always @(posedge C, posedge S)
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if (S)
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Q <= 1;
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@ -190,7 +190,7 @@ module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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Q <= D;
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endmodule
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module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
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always @(posedge C)
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if (E) begin
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if (R)
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@ -200,7 +200,7 @@ module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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end
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endmodule
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module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
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always @(posedge C, posedge R)
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if (R)
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Q <= 0;
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@ -208,7 +208,7 @@ module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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Q <= D;
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endmodule
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module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
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always @(posedge C)
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if (E) begin
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if (S)
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@ -218,7 +218,7 @@ module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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end
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endmodule
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module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
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always @(posedge C, posedge S)
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if (S)
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Q <= 1;
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@ -228,18 +228,18 @@ endmodule
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// Negative Edge SiliconBlue FF Cells
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module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
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module SB_DFFN (output `SB_DFF_REG, input C, D);
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always @(negedge C)
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Q <= D;
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endmodule
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module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
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module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
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always @(negedge C)
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if (E)
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Q <= D;
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endmodule
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module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
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always @(negedge C)
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if (R)
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Q <= 0;
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@ -247,7 +247,7 @@ module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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Q <= D;
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endmodule
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module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
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always @(negedge C, posedge R)
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if (R)
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Q <= 0;
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@ -255,7 +255,7 @@ module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
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Q <= D;
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endmodule
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module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
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always @(negedge C)
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if (S)
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Q <= 1;
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@ -263,7 +263,7 @@ module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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Q <= D;
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endmodule
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module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
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always @(negedge C, posedge S)
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if (S)
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Q <= 1;
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@ -271,7 +271,7 @@ module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
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Q <= D;
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endmodule
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module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
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always @(negedge C)
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if (E) begin
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if (R)
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@ -281,7 +281,7 @@ module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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end
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endmodule
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module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
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always @(negedge C, posedge R)
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if (R)
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Q <= 0;
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@ -289,7 +289,7 @@ module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
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Q <= D;
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endmodule
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module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
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always @(negedge C)
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if (E) begin
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if (S)
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@ -299,7 +299,7 @@ module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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end
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endmodule
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module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
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module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
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always @(negedge C, posedge S)
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if (S)
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Q <= 1;
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@ -310,7 +310,7 @@ endmodule
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// SiliconBlue RAM Cells
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module SB_RAM40_4K (
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(* abc_flop_q *) output [15:0] RDATA,
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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@ -478,7 +478,7 @@ module SB_RAM40_4K (
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endmodule
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module SB_RAM40_4KNR (
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(* abc_flop_q *) output [15:0] RDATA,
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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input WCLK, WCLKE, WE,
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@ -543,7 +543,7 @@ module SB_RAM40_4KNR (
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endmodule
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module SB_RAM40_4KNW (
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(* abc_flop_q *) output [15:0] RDATA,
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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input WCLKN, WCLKE, WE,
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@ -608,7 +608,7 @@ module SB_RAM40_4KNW (
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endmodule
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module SB_RAM40_4KNRNW (
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(* abc_flop_q *) output [15:0] RDATA,
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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input WCLKN, WCLKE, WE,
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@ -902,7 +902,7 @@ module SB_SPRAM256KA (
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input [15:0] DATAIN,
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input [3:0] MASKWREN,
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input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
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(* abc_flop_q *) output reg [15:0] DATAOUT
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output reg [15:0] DATAOUT
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);
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`ifndef BLACKBOX
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`ifndef EQUIV
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