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Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto

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ast: swap range regardless of range_left >= 0
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Claire Wolf 2020-05-14 18:06:18 +02:00 • committed by GitHub
commit ee0beb481d
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4 changed files with 35 additions and 8 deletions
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frontends/ast/simplify.cc
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@ -1080,7 +1080,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
if (old_range_valid != range_valid)
did_something = true;
if (range_valid && range_left >= 0 && range_right > range_left) {
if (range_valid && range_right > range_left) {
int tmp = range_right;
range_right = range_left;
range_left = tmp;