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This commit is contained in:
Eddie Hung 2019-08-21 17:36:38 -07:00
parent 15188033da
commit ed7be3e6b6
1 changed files with 4 additions and 0 deletions
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4
passes/pmgen/xilinx_srl.cc
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@ -218,6 +218,10 @@ struct XilinxSrlPass : public Pass {
do { do {
auto pm = xilinx_srl_pm(module, module->selected_cells()); auto pm = xilinx_srl_pm(module, module->selected_cells());
pm.ud_variable.minlen = minlen; pm.ud_variable.minlen = minlen;
// Since `nusers` does not count module ports as a user,
// and since `sigmap` does not always make such ports
// the canonical signal.. need to maintain a pool these
// ourselves
for (auto p : module->ports) { for (auto p : module->ports) {
auto w = module->wire(p); auto w = module->wire(p);
if (w->port_output) if (w->port_output)